[TYPES/announce] ACM SIGBED Paul Caspi Dissertation Award : deadline March 1st, 2016
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] ACM SIGBED Paul Caspi Dissertation Award http://sigbed.blogspot.fr/p/awards.html The nomination should be submitted via EasyChair at https://easychair.org/conferences/?conf=caspiaward16 by March 1, 2016. For further information, contact Wang Yi (y...@it.uu.se) The Paul Caspi Dissertation Award is a new ACM SIGBED award established in 2013. The award will recognize outstanding doctoral dissertations that significantly advance the state of the art in the science of embedded systems, in the spirit and legacy of Dr. Paul Caspi's work. The ACM SIGBED Paul Caspi Dissertation Award will be presented annually to the author of an outstanding dissertation in the area of Embedded Systems. The author of the winning dissertation will be invited to publish a dissertation summary in the ACM SIGBED Newsletter and to submit their work to the journal ACM TECS (Transactions on Embedded Computing Systems) for possible publication, after the normal peer-review process. The award will include an award certificate for the author and an honorarium of 2000 USD. A public citation for the award paper will be placed on the SIGBED web site. Selection Committee Christoph Kirsch Nikil Dutt Rolf Ernst Tei-Wei Kuo Florence Maraninchi Oleg Sokolsky Reinhard Wilhelm Wang Yi (Chair) Selection Process The award is for an outstanding doctoral dissertation dated within one year preceding the nomination due date. A selection committee and a selection committee chair will be selected by the current SIGBED Executive Committee. A member of the current SIGBED Executive Committee will be one of the selection committee members. The committee chair shall adjudicate conflicts of interest, appointing substitutes to the committee as necessary. Dissertations supervised by a selection committee member are ineligible to be nominated. For purposes of continuity, committee members may remain on the committee for up to three years. The selection committee shall be no less than three persons in size. Nomination Process Nominations will be solicited annually, being due March 1st each year, via major mailing lists and web forums. Additionally, dissertation advisers of each eligible year will be contacted for solicitation of award nominations. A nomination should consist of the following items: - Name, address, phone number, and email address of the person making the nomination (the nominator). - Name, address, phone number, and email address of the candidate for whom an award is recommended (the nominee). - A short statement (200-500 words) explaining why the nominee deserves the award. - Supporting statements from up to two persons in addition to the nominator. - The nominated dissertation in an English language version. - A list of the nominee's publications that were used as the basis of chapters in the nominated dissertation. - The CV of the nominee. The selection committee will make a recommendation on the winner of the award to the SIGBED Executive Committee, which will approve and announce the final winner. SIGBED Executive Committee members who have conflicts of interest with any nominee will be excluded from the approval process. The primary selection criterion will be the quality of the candidate's work, with the aim to recognize outstanding doctoral dissertations. The selection committee may choose to issue no award in a given year. The award may not be given to multiple recipients.
[TYPES/announce] SYNCHRON 2014 : call for participation : Aussois, France, Nov 30th to Dec 5th, 2014
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] SYNCHRON 2014 International Open Workshop on Synchronous Programming http://synchron2014.inria.fr/ November 30, December 5, 2014 Centre CNRS Paul Langevin, Aussois, France The 21st International Open Workshop on Synchronous Programmings (SYNCHRON'14) will be held in the Alps ski resort of Aussois, France, between November 30-December 4, 2014. The registration is now open online at: http://synchron2014.inria.fr SYNCHRON is the yearly rendezvous for all researchers working in or around the field of synchronous programming. It's an open forum where students and researchers can present and discuss about ongoing work on the numerous topics related to synchronous programming: language design, compilation, validation, case-studies, models of computation and communication, domain-specific languages, concurrency and scheduling theory etc. IMPORTANT NOTE: The Centre CNRS Paul Langevin will be open for the workshop from Sunday Nov. 30th 2pm, to Friday Dec. 5th 6pm, which means that you will need to find another accommodation if you plan to arrive sooner and/or leave later. IMPORTANT NOTE #2: Since there will be another workshop hosted in the Centre CNRS Paul Langevin at the same time, it is advised that you register as soon as possible. Kind regards, The Synchron'14 organisers (pascal.raym...@imag.fr and alain.gira...@inria.fr)
[TYPES/announce] CALL FOR PAPERS DATE 2015: Topic: E3 Model-based Design and Verification for Embedded Systems
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] === CALL FOR PAPERS DATE 2015 Topic: E3 Model-based Design and Verification for Embedded Systems DATE (Design, Automation Test in Europe) Conference Grenoble, France, 9-13 March, 2015 === DEADLINES - Paper Submission: Sunday, September 14, 2014 - Notification of Acceptance: Friday, November 07, 2014 - Camera-Ready Paper: Friday, November 28, 2014 === QUICK LINKS - Conference http://www.date-conference.com - Call for Papers http://www.date-conference.com/call-for-papers - Instructions http://www.date-conference.com/submission-instructions === The Design, Automation and Test in Europe conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. This five-day event consists of a conference with plenary keynotes, regular papers, interactive presentations, panels and hot-topic sessions, tutorials, master courses and workshops. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services. Both the conference and the exhibition, together with the many user group meetings, fringe meetings, university booth and social events offer a wide variety of opportunities to meet and exchange information. You are invited to submit your research contributions to the topic E3 Model-based Design and Verification for Embedded Systems which is devoted to: - Verification techniques for embedded systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. - Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. - Model-based design of software architectures and deployment. - Theories, languages and tools supporting model-based design flows covering software, control and physical components. -- E3 Topic Program Committee: -- Saddek Bensalem, Universite Joseph Fourier/Verimag, France (Chair) Linh Thi Xuan Phan, University of Pennsylvania, USA (Co-Chair) Borzoo Bonakdarpour, University of Waterloo, Canada Petru Eles, Linkoping University, Sweden Alain Girault, INRIA, France Oleg Sokolsky, University of Pennsylvania, USA Wang Yi, Uppsala University, Sweden -- - Alain GIRAULT http://pop-art.inrialpes.fr/~girault INRIA senior researcher tel: +(33|0) 476 61 53 51 Member of the SPADES project-team fax: +(33|0) 476 61 52 52 - Sauvons la Recherche ! http://www.sauvonslarecherche.fr -
[TYPES/announce] Call for Papers DATE 2015 : Grenoble, France - March 9-13, 2015
; Autonomous and semi-autonomous large-scale CPS and related issues; Socio-technical systems (ex. empowered consumer and organizational behavior in smart grids) and CPS; Cognitive control for CPS; Modeling and analysis of networked control, switched control, and distributed control systems in CPS; control/architecture co-design in CPS; architecture-aware controller synthesis; Case studies in CPS ranging from automotive systems, and avionics, to smart buildings and smart grids. --- PAPER SUBMISSION --- All manuscripts must be submitted electronically before Sunday, September 14, 2014, following the instructions on the conference Web page: www.date-conference.com The accepted file format is PDF. Any other format and manuscripts received in hard-copy form will not be processed. Papers can be submitted for either formal oral presentation or for interactive presentation. Oral presentations require novel and complete research work supported by experimental results. Interactive presentations are expected to articulate emerging and future design, verification and test problems including work in progress and identify open problems that merit innovative future research. These presentations are given on a laptop in a face-to-face discussion area. Submissions should not exceed 6 pages in length for oral-presentation papers and 4 pages in length for interactive-presentation papers, and should be formatted as close as possible to the final format: A4 or letter sheets, double column, single spaced, Times or equivalent font of minimum 10pt (templates are available on the DATE Web site for your convenience). To permit blind review, submissions should not include the author names. Any submission not in line with the above rules will be discarded. All papers will be evaluated with regard to their suitability for the conference, originality, and technical soundness. The Programme Committee reserves the right to reorient oral-presentation papers to interactive-presentation and vice versa, to obtain the most suitable presentation format. --- INFORMATION --- Lothar Thiele - DATE Embedded Systems Software Track Chair - thi...@ethz.ch David Atienza - DATE Program Chair - david.atie...@epfl.ch -- - Alain GIRAULT http://pop-art.inrialpes.fr/~girault INRIA senior researcher tel: +(33|0) 476 61 53 51 Member of the SPADES project-team fax: +(33|0) 476 61 52 52 - Sauvons la Recherche ! http://www.sauvonslarecherche.fr -
[TYPES/announce] SYNCHRON 2014 early announcement : November 30 to December 4, 2014, Aussois, France
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] SYNCHRON'14 (EARLY ANNOUNCEMENT) International Open Workshop on Synchronous Programming November 30, December 4, 2014 Centre CNRS Paul Langevin, Aussois, France The 21st International Open Workshop on Synchronous Programming (SYNCHRON'14) will be held in the Alps ski resort of Aussois, France, between November 30 and December 4, 2014. SYNCHRON is the yearly rendezvous for all researchers working in or around the field of synchronous programming. It's an open forum where students and researchers can present and discuss about ongoing work on the numerous topics related to synchronous programming: language design, compilation, validation, case-studies, models of computation and communication, domain-specific languages, concurrency and scheduling theory etc. PLEASE SAVE THE DATE: The opening of the registration site will be announced later, during September. Kind regards, The SYNCHRON'14 organizers (pascal.raym...@imag.fr and alain.gira...@inria.fr)
[TYPES/announce] RePP 2014 workshop call for participation: Grenoble, France, Sunday April 6th, 2014
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] RePP 2014 http://repp14.inria.fr Reconciling Performance with Predictability Grenoble, France, Sunday April 6th, 2014 An ETAPS 2014 satellite event = Final program = 9.15 - 9.30 Opening 9.30 - 10.30 Sebastian Hahn, Jan Reineke, and Reinhard Wilhelm Saarland University, Saarbruecken: Compositionality in Execution Time Analysis David Broman University of California, Berkeley: Precision Timed Processors and WCET-Aware Code Management for Mixed-Criticality Systems 10.30 - 11.00 Coffee Break 11.00 - 12.30 Sophie Quinton and Rolf Ernst INRIA Grenobles and Technical University Braunschweig: Typical Worst-Case Analysis: Designing Real-Time Systems for the Hard and Weakly-Hard Case Joerg Mische, Stefan Metzlaff, and Theo Ungerer University of Augsburg: Distributed Memory on Chip - Bringing Together Low Power and Real-Time Thomas Carle, Manel Djemal, Dumitru Potop Butucaru, Robert de Simone, Zhen Zhang, Francois Pecheux, and Franck Wajbuerst INRIA, IRT SystemX, and UPMC/LIP6: Reconciling performance and predictability on a many-core through off-line mapping 12.30 - 14.00 Lunch Pascal Raymond, Claire Maiza, Catherine Parent-Vigouroux, Fabienne Carrier, and Mihail Asavoae Grenoble-Alpes University and Verimag: Timing Analysis Enhancement for Synchronous Program Florian Kluge, Mike Gerdes, Florian Haas, and Theo Ungerer University of Augsburg: A Generic Timing Model for Cyber-Physical Systems Insa Fuhrmann, David Broman, Steven Smyth, and Reinhard von Hanxleden Christian-Albrechts-University, Kiel, and University of California, Berkeley, and Linkoeping University: Towards Interactive Timing Analysis for Designing Reactive Systems Michael Mendler, Brino Bodin, Partha Roop, and Jai Jie Wang Otto-Friedrich University of Bamberg, University of Edinburgh, and The University of Auckland: The WCRT analysis of synchronous programs: Studying the tick alignment problem 16.00 - 16.30 Coffee Break 16.30 - 17.30 Moderated Discussion
[TYPES/announce] Post-doctoral Position at INRIA Grenoble
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] Proposal for a Post-doctoral Position at INRIA Grenoble === Title = Advanced dataflow programming Model of computation and parallel schedule generation. Programmation flot de données avancée Modèle de calcul et génération d'ordonnancement paralleles Location, supervisors, duration INRIA Grenoble (France), Spades Team Pascal FRADET Alain GIRAULT pascal.fra...@inria.fr alain.gira...@inria.fr The postdoc position is for 1 year, starting end of 2014 (October ideally) Salary: 2.620 euros gross monthly (about 2.135 euros net). Abstract We are interested in dataflow models of computation to program applications for manycore chips. In order to ensure analysis and scheduling, the synchronous dataflow model (SDF) is widely used because it allows static analyses (liveness and buffer boundedness) and scheduling. SDF has a clean semantics and leads to efficient implementations but it cannot express many dynamic features. In particular, it cannot express dynamic I/O rate modifications, nor dynamic topology modifications. For this reason, many variants of SDF have been proposed, among which we can cite BDF, CSDF, HDF, VRDF, PSDF, and SPDF. We have recently proposed BPDF [1], a dataflow model with integer and boolean parameters able to express dynamicity while remaining verifiable and schedulable. Integer parameters define rate modifications while boolean parameters specify some dynamic topology modifications (activation and deactivation of dataflow edges). The postdoctoral project will focus on extending the expressivity of BPDF and/or study multi-criteria scheduling of the model on multi-core platforms. - possible extensions of BPDF are more expressive changes of the topology (e.g., adding/removing actors and edges). Since the model of computation should remain analysable for liveness and boundedness, such linguistic extensions usually entails extensions of the corresponding analyses. - parallel schedules of BPDF dataflow applications for manycore chips can be generated according several criteria: throughput (useful for streaming application), input-output latency (useful for real-time applications), power consumption (useful for autonomous applications), to cite a few. One of the difficulty here resides in multi-criteria scheduling with antagonistic criteria. Required Skills === A PhD in formal methods, embedded systems, and/or real-time programming (e.g., analysis, semantics, verification, validation, code generation, ...). A knowledge of dataflow programming and/or scheduling would be a plus. Send CV + contact information of 2 or 3 recommenders to Pascal Fradet and Alain Girault. References == [1] Vagelis Bebelis, Pascal Fradet, Alain Girault, Bruno Lavigueur: BPDF: A Statically Analyzable Dataflow Model with Integer and Boolean Parameters; In International Conference on Embedded Software, EMSOFT'13, September 2013.
[TYPES/announce] RePP 2014 workshop extension deadline: Grenoble, France, Sunday April 6th, 2014
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] RePP 2014 http://repp14.inria.fr Reconciling Performance with Predictability Grenoble, France, Sunday April 6th, 2014 An ETAPS 2014 satellite event Workshop description The RePP workshop targets embedded systems with both efficiency requirements and critical temporal constraints, occurring in many industrial domains: avionics, automotive, railway, energy, and robotics. Guaranteeing the temporal constraints depends on the predictability properties of the whole system (processor architecture, software, OS, scheduling strategy, communications, and middleware). However, system efficiency is measured by means of average-case behavior with performance, resource utilization, and power consumption criteria. Reasons for the gap between average-case and worst-case behavior are the variation and non-determinism of the system environment, and the interferences caused by shared resources. Unfortunately, new classes of hardware platforms such as multi-core processors and multiprocessors-on-a-chip as well as the demand for adaptive and multi-mode applications quickly increase system efficiency if worst-case behavior needs to be guaranteed. The workshop will discuss approaches that attack the improvement of both worst-case predictability and of average-case performance. Topics of interest include mixed-criticality approaches, predictable (multi-core) architectures, worst-case execution time and interference analysis, resource-aware compilers, scheduling and allocation considering worst-case and average-case performance, and certification. Workshop topics === Contributions should relate to the main subject of the workshop. The following issues and questions are of special interest: - Concepts and metrics for characterizing predictability. - Computer science has been successful in removing resource interactions from interfaces. Does it make sense to enrich interfaces with resource-related information. If yes, on which level of abstraction (instruction set, software components, …). - Do resource interactions have an influence across abstraction layers? In particular, can improvements on one layer lead to degradation on another layer? - Designing new hardware with special support for predictability. - Using mainstream software development for predictability, for instance with the support of new compilers for classical programming languages. - Multicore predictable processors: How can embedded multicore processors be designed in a time predictable fashion? - Parallel predictable processors: How can embedded control algorithms that require a higher performance than sequential processors can deliver be parallelized and allow for time predictability of the parallel task? - Mixed criticality: Is the execution of mixed real-time and non-real-time applications on an embedded multicore processor feasible? - Case studies involving applications where one needs to guarantee deadlines AND average performance. Programme committee === David Broman: UC Berkeley, bro...@eecs.berkeley.edu Jian-Jia Chen: Karlsruhe Institute of Technology, jian-jia.c...@kit.edu Alain Girault: INRIA, alain.gira...@inria.fr Michael Mendler: U. Bamberg, michael.mend...@uni-bamberg.de Partha Roop: U. Auckland, p.r...@auckland.ac.nz Lothar Thiele: ETHZ, lothar.thi...@ethz.ch Reinhard Wilhelm: U. des Saarlandes, wilh...@cs.uni-saarland.de Theo Ungerer: U. Augsburg, unge...@informatik.uni-augsburg.de Paper submission We welcome original, unpublished, research papers on the above mentioned topics. The submission format should be in the LNCS format, between 10 and 15 pages long. The accepted papers will be printed to be handed out to the workshop participants but they will not be formally published. Instead, a follow-up call for papers will take place for LITES, the Leibniz Transactions on Embedded Systems (http://www.dagstuhl.de/en/publications/lites). Important dates === Submission deadline: February 14th, 2014 Paper notification: March 7th, 2014 Final version: March 21st, 2014 Workshop: April 6th, 2014
[TYPES/announce] RePP 2014 workshop call for papers: Grenoble, France, Sunday April 6th, 2014
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] RePP 2014 http://repp14.inria.fr Reconciling Performance with Predictability Grenoble, France, Sunday April 6th, 2014 An ETAPS 2014 satellite event Workshop description The RePP workshop targets embedded systems with both efficiency requirements and critical temporal constraints, occurring in many industrial domains: avionics, automotive, railway, energy, and robotics. Guaranteeing the temporal constraints depends on the predictability properties of the whole system (processor architecture, software, OS, scheduling strategy, communications, and middleware). However, system efficiency is measured by means of average-case behavior with performance, resource utilization, and power consumption criteria. Reasons for the gap between average-case and worst-case behavior are the variation and non-determinism of the system environment, and the interferences caused by shared resources. Unfortunately, new classes of hardware platforms such as multi-core processors and multiprocessors-on-a-chip as well as the demand for adaptive and multi-mode applications quickly increase system efficiency if worst-case behavior needs to be guaranteed. The workshop will discuss approaches that attack the improvement of both worst-case predictability and of average-case performance. Topics of interest include mixed-criticality approaches, predictable (multi-core) architectures, worst-case execution time and interference analysis, resource-aware compilers, scheduling and allocation considering worst-case and average-case performance, and certification. Workshop topics === Contributions should relate to the main subject of the workshop. The following issues and questions are of special interest: - Concepts and metrics for characterizing predictability. - Computer science has been successful in removing resource interactions from interfaces. Does it make sense to enrich interfaces with resource-related information. If yes, on which level of abstraction (instruction set, software components, …). - Do resource interactions have an influence across abstraction layers? In particular, can improvements on one layer lead to degradation on another layer? - Designing new hardware with special support for predictability. - Using mainstream software development for predictability, for instance with the support of new compilers for classical programming languages. - Multicore predictable processors: How can embedded multicore processors be designed in a time predictable fashion? - Parallel predictable processors: How can embedded control algorithms that require a higher performance than sequential processors can deliver be parallelized and allow for time predictability of the parallel task? - Mixed criticality: Is the execution of mixed real-time and non-real-time applications on an embedded multicore processor feasible? - Case studies involving applications where one needs to guarantee deadlines AND average performance. Programme committee === David Broman: UC Berkeley, bro...@eecs.berkeley.edu Jian-Jia Chen: Karlsruhe Institute of Technology, jian-jia.c...@kit.edu Alain Girault: INRIA, alain.gira...@inria.fr Michael Mendler: U. Bamberg, michael.mend...@uni-bamberg.de Partha Roop: U. Auckland, p.r...@auckland.ac.nz Lothar Thiele: ETHZ, lothar.thi...@ethz.ch Reinhard Wilhelm: U. des Saarlandes, wilh...@cs.uni-saarland.de Theo Ungerer: U. Augsburg, unge...@informatik.uni-augsburg.de Paper submission We welcome original, unpublished, research papers on the above mentioned topics. The submission format should be in the LNCS format, between 10 and 15 pages long. The accepted papers will be printed to be handed out to the workshop participants but they will not be formally published. Instead, a follow-up call for papers will take place for LITES, the Leibniz Transactions on Embedded Systems (http://www.dagstuhl.de/en/publications/lites). Important dates === Paper submission: January 21st, 2014 Notification of acceptance: February 21st, 2014 Final version due: March 14th, 2014 Workshop: April 6th, 2014
[TYPES/announce] DATE'14, E3: Model-based design and verification of embedded systems
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] (apologies if you receive multiple copies) === CALL FOR PAPERS DATE 2014 TOPIC E3: Model-Based Design and Verification for Embedded Systems DESIGN AUTOMATION AND TEST IN EUROPE CONFERENCE ICC, DRESDEN, GERMANY 24TH-28TH MARCH 2014 http://www.date-conference.com === DEADLINES - Paper Submissions September 13, 2013 - Special Session Proposals September 13, 2013 - Tutorial Proposals September 13, 2013 - Notification of Acceptance November 17, 2013 - Camera-Ready Paper December 15, 2013 === The Design, Automation and Test in Europe conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. This five-day event consists of a conference with plenary keynotes, regular papers, interactive presentations, panels and hot-topic sessions, tutorials, master courses and workshops. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services. Both the conference and the exhibition, together with the many user group meetings, fringe meetings, university booth and social events offer a wide variety of opportunities to meet and exchange information. You are invited to submit your research contributions to the Topic E3: Model-Based Design and Verification for Embedded Systems Areas of interests include (but not limited to): Verification techniques for embedded systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures, and system integration and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components; Case studies and industrial applications of model-based methods and tools for embedded systems design. === TPC MEMBERS of DATE'14, topic E3 Saddek Bensalem, Verimag, France Petru Eles, Linköping University, Sweden Alain Girault, INRIA, France Kim Larsen, Aalborg University, Denmark Linh Thi Xuan Phan, University of Pennsylvania, USA Abhik Roychoudhury, National University of Singapore Wang Yi, Uppsala University === QUICK LINKS - Conferencehttp://www.date-conference.com - Call for Papershttp://www.date-conference.com/call-for-papers - Instructionshttp://www.date-conference.com/submission-instructions
[TYPES/announce] MEMOCODE 2011 Call for Papers
) Local Chair:Robert Mullins (University of Cambridge) PROGRAM COMMITTEE: David Atienza Alonso (EPFL) Twan Basten (Eindhoven University of Technology) Roderick Bloem (Graz University of Technology) Forrest Brewer (University of California, Santa Barbara) Tevfik Bultan (University of California, Santa Barbara) Luca Carloni (Columbia University) Satrajit Chatterjee (Intel) Ashish Darbari (ARM) Robert de Simone (INRIA, Sophia Antipolis) Rolf Drechsler (University of Bremen) Stephen A. Edwards (Columbia University) Franco Fummi (University of Verona) Thierry Gautier (INRIA) Alain Girault (INRIA) Ganesh Gopalakrishnan (University of Utah) David Greaves (Univ. Cambridge) Andreas Griesmayer (Imperial College London) Ziyad Hanna (Jasper Design Automation) Franjo Ivancic (NEC Labs) Barbara Jobstmann (CNRS/Verimag) Michael Kishinevsky (Intel) Daniel Kroening (Oxford University) Luciano Lavagno (Politecnico Torino) Elizabeth Leonard (Naval Research Laboratory) Alan Mycroft (University of Cambridge) Rishiyur S. Nikhil (Bluespec, Inc.) John O'Leary (Intel) Jan Reineke (University of California, Berkeley) Klaus Schneider (University of Kaiserslautern) Natasha Sharygina (University of Lugano) Satnam Singh (Microsoft Research) Daryl Stewart (ARM) Michael Theobald (D. E. Shaw Research) * Sponsorship approval pending -- - Alain GIRAULT http://pop-art.inrialpes.fr/~girault INRIA senior researcher tel: +(33|0) 476 61 53 51 Head of the POP ART project-teamfax: +(33|0) 476 61 52 52 - Sauvons la Recherche ! http://www.sauvonslarecherche.fr -
Re: [TYPES/announce] Reviewing for POPL: a concrete proposal
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] Dear all First, I completely agree with Simon's proposal. Then, concerning how to accommodate more papers at the conference, my preference also goes to solution A (i.e., parallel sessions). cheers Alain If this proposal were to be accepted, we would need to figure out how to accommodate many more papers at the physical meeting. How to achieve this is secondary to my main proposal, but a number of proposals have been floated, including * Parallel sessions * A lottery among accepted papers * Voting by conference registrants * Program committee decision I know this is secondary, but I want to make sure I get my two cents in: the only rational choice is to go to parallel sessions or to extend the length of the conference. I believe that voting, either by PC or conference registrants, has the potential to be much more unfair than current paper selection practice. If part of the voting explicitly depends upon answering the question who will give a good talk? as opposed to what is the content of the paper then this introduces an extreme bias towards old, famous, successful researchers and away from young, new, unheard of researchers and students. Whereas we now at least try to judge POPL papers purely on the merit of the current technical document, we would instead be veering away from that crucial principle. And the more we start asking personality-based questions such as who will give a good talk, the more we may be susceptible to subconscious biases against various minorities (women, racial, etc) or the more we may try to overcompensate for such biases, resulting in reverse-discrimination. I also believe that lottery for talks is bad. What a lottery does is select some set of papers for which the talk audience is zero. With parallel sessions, the talk audiences will be smaller, but not zero. If I had a really great idea, I'd rather present it 6 months later at PLDI than have it appear 6 months earlier in the POPL proceedings, but not have the chance to give a talk. One last thing: while we may be getting all tied in knots over this popl review process right now, from what I've heard, within computer science, our community is really pretty great when it comes to selecting papers for inclusion in conferences based on their merits. I've heard of all kinds of dysfunctionality and biases and turf wars and sketchiness in other communities that we don't seem to be suffering from at all. Of course, that's probably because we're constantly working to try to make the process better and more fair to all. Cheers, Dave -- - Alain GIRAULT http://pop-art.inrialpes.fr/~girault INRIA senior researcher tel: +(33|0) 476 61 53 51 Head of the POP ART project-teamfax: +(33|0) 476 61 52 52 - Sauvons la Recherche ! http://www.sauvonslarecherche.fr -
[TYPES/announce] Call for participation: ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'09)
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] LCTES 2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (In conjunction with PLDI 2009) Dublin, Ireland, June 19~20 2009 http://www.cse.psu.edu/lctes09/ Call for participation: === As embedded systems increase in number, complexity, and diversity, new research challenges are encountered in areas such as verification, validation, meeting performance goals and resource constraints, creating and exploiting new hardware architectures, and scaling up to multicores and distributed systems built from multicores. The LCTES 2009 technical programme features papers presenting original work on programming languages, compilers, tools, and architectures that help meet these challenges. Registration: = - Early registration deadline: May 20, 2009. - Registration is through the PLDI web server: https://regmaster3.com/conf/PLDI09/register.php Invited speakers: = - Edward Lee, UC Berkeley - Famantanantsoa Randimbivololona, Airbus List of accepted papers: Modulo Scheduling without Overlapped Lifetimes o Eric Stotzer and Ernst Leiss Synchronous Objects with Scheduling Policies, Introducing safe shared memory in Lustre o Paul Caspi, Jean-louis Colaço, Léonard Gérard, Marc Pouzet and Pascal Raymond Recurrence Cycle Aware Modulo Scheduling for Coarse-Grained Reconfigurable Architectures o Taewook Oh, Bernhard Egger, Hyunchul Park and Scott Mahlke PTIDES on Flexible Task Graph: Real-Time Embedded System Building from Theory to Practice o Jia Zou, Joshua Auerbach, David F. Bacon and Edward A. Lee Lunch A Compiler Optimization to Reduce Soft Errors in Register Files o Jongeun Lee and Aviral Shrivastava Raced Profiles: Efficient Selection of Competing Compiler Optimizations o Hugh Leather, Michael O'Boyle and Bruce Warton Eliminating the Call Stack to Save RAM o Xuejun Yang, Nathan Cooprider and John Regehr Live-range Unsplitting for Faster Optimal Coalescing o Sandrine Blazy and Benoît Robillard Push-Assisted Migration of Real-Time Tasks in Multi-Core Processors o Abhik Sarkar, Frank Mueller, Harini Ramaprasad and Sibin Mohan Software Transactional Memory for Multicore Embedded Systems o Jennifer Mankin and David Kaeli Synergistic Execution of Stream Programs on Multicores with Accelerators o Abhishek Udupa, R. Govindarajan and Matthew J. Thazhuthaveetil Towards device emulation code generation o Thomas Heinz and Reinhard Wilhelm Guaranteeing Instruction Fetch Behavior with a Lookahead Instruction Fetch Engine (LIFE) o Stephen Hines, Yuval Peress, Peter Gavin, David Whalley and Gary Tyson Debugging FPGA-based Packet Processing Systems through Transaction-level Communication-centric Monitoring o Paul McKechnie, Michaela Blott and Wim Vanderbauwhede Tracing Interrupts in Embedded Software o Giovani Gracioli and Sebastian Fischmeister Addressing the Challenges of DBT for the ARM Architecture o Ryan W. Moore, Jose A. Baiocchi, Bruce R. Childers, Jack W. Davidson and Jason D. Hiser Integrating Hardware and Software Information Flow Analyses o Colin Fidge and Diane Corney Specification and Verification of Time Requirements with CCSL and Esterel o Charles André and Frédéric Mallet -- - Alain GIRAULT http://pop-art.inrialpes.fr/~girault INRIA senior researcher tel: +(33|0) 476 61 53 51 Head of the POP ART project-teamfax: +(33|0) 476 61 52 52 - Sauvons la Recherche ! http://www.sauvonslarecherche.fr -
[TYPES/announce] Final Call for Papers: ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'09)
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] LCTES 2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (In conjunction with PLDI 2009) Dublin, Ireland, June 19~20 2009 http://www.cse.psu.edu/lctes09/ Submission deadline extension: February 16, 2009 (Please see the web site for details about paper submission.) Final Call for Papers: == As embedded systems increase in number, complexity, and diversity, new research challenges are encountered in areas such as verification, validation, meeting performance goals and resource constraints, creating and exploiting new hardware architectures, and scaling up to multicores and distributed systems built from multicores. LCTES 2009 solicits papers presenting original work on programming languages, compilers, tools, and architectures that help meet these challenges. Research papers (which propose innovative techniques) and experience papers (which report experimentation with and lessons learned from real-world systems and applications) are both welcome. In addition to its regular sessions, LCTES 2009 will feature special events such as an industrial panel, keynotes, tutorials and demonstrations to bring out the latest and more interesting aspects of embedded systems. Examples include tools for multi-cores, emerging platforms such as smart phones, multi-player game machines and autonomous vehicles and embedded supercomputing. Papers are solicited on, but not limited to, the following aspects of embedded and cyber physical systems design: Programming language issues in embedded systems, including (*)Language features to exploit multi-core, single-chip SIMD, reconfigurable architecture and other emerging architectures (*)Language features for distributed real-time control, media players, and other complex embedded systems (*)Language features to enhance reliability and security (*)Virtual machines, concurrency, inter-processor synchronization mechanisms, concurrency, memory management techniques Compiler issues in embedded systems, including (*)Interaction between embedded computer architectures, operating systems and compilers (*)Interpreters, binary translation and just-in-time compilation (*)Support for debugging, profiling, exception and interrupt handling, for reliability and security (*)Optimization for low power, low energy, low code and data size, and high (real-time) performance Tools for analysis, specification, design and implementation of embedded systems, including (*)Hardware, system software, and application, and their interface (*)Distributed real-time control, media players, reconfigurable architectures and other complex systems (*)Validation and verification, system integration and testing (*)Timing analysis, timing predictability, WCET analysis and real-time scheduling analysis (*)Performance monitoring and tuning (*)Runtime system support for embedded systems Novel embedded architectures (*)Design and implementation of novel embedded architectures (*)Workload analysis and performance evaluation (*)Architecture support for new language features, new compiler techniques and debugging tools Program Committee: == (*)Dhruva Chakrabarti (*)Swarat Chaudhuri (*)Bruce Childers (*)Andreas Krall (*)Prasad Kulkarni (*)Tei-Wei Kuo (*)Insup Lee (*)Liqian Luo (*)Jan Madsen (*)Sally McKee (*)Florence Maraninchi (*)Peter Marwedel (*)Frank Mueller (*)Tamiya Onodera (*)Alex Orailoglu (*)Emre Ozer (*)Preeti R. Panda (*)Tajana Simunic (*)Reinhard Wilhelm (*)Wayne Wolf (*)Wang Yi Steering Committee: === (*)Koen De Bosschere (*)Ron Cytron (*)Srinivas Devadas (*)Krisztian Flautner (*)Rajiv Gupta (*)Mary Jane Irwin (*)Annie Liu (*)Thomas Marlowe (*)Peter Marwedel (*)Frank Mueller (*)Yunheung Paek (*)Santosh Pande (*)John Regeher (*)Per Stenstrom (*)David Whalley (*)Reinhard Wilhelm General Chair: == Christoph Kirsch University of Salzburg Program Chair: == Mahmut Kandemir Penn State University Poster Chair: = Aviral Shrivastava Arizona State University Publicity Chair: Alain Girault INRIA Grenoble Rhône-Alpes -- - Alain GIRAULT http://pop-art.inrialpes.fr/~girault INRIA senior researcher tel: +(33|0) 476 61 53 51 Head of the POP ART project-teamfax: +(33|0) 476 61 52 52 - Sauvons la Recherche ! http://www.sauvonslarecherche.fr -
[TYPES/announce] Second Call for Papers: ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'09)
[ The Types Forum (announcements only), http://lists.seas.upenn.edu/mailman/listinfo/types-announce ] LCTES 2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (In conjunction with PLDI 2009) Dublin, Ireland, June 19~20 2009 http://www.cse.psu.edu/lctes09/ Second Call for Papers: === As embedded systems increase in number, complexity, and diversity, new research challenges are encountered in areas such as verification, validation, meeting performance goals and resource constraints, creating and exploiting new hardware architectures, and scaling up to multicores and distributed systems built from multicores. LCTES 2009 solicits papers presenting original work on programming languages, compilers, tools, and architectures that help meet these challenges. Research papers (which propose innovative techniques) and experience papers (which report experimentation with and lessons learned from real-world systems and applications) are both welcome. In addition to its regular sessions, LCTES 2009 will feature special events such as an industrial panel, keynotes, tutorials and demonstrations to bring out the latest and more interesting aspects of embedded systems. Examples include tools for multi-cores, emerging platforms such as smart phones, multi-player game machines and autonomous vehicles and embedded supercomputing. Papers are solicited on, but not limited to, the following aspects of embedded and cyber physical systems design: Programming language issues in embedded systems, including (*)Language features to exploit multi-core, single-chip SIMD, reconfigurable architecture and other emerging architectures (*)Language features for distributed real-time control, media players, and other complex embedded systems (*)Language features to enhance reliability and security (*)Virtual machines, concurrency, inter-processor synchronization mechanisms, concurrency, memory management techniques Compiler issues in embedded systems, including (*)Interaction between embedded computer architectures, operating systems and compilers (*)Interpreters, binary translation and just-in-time compilation (*)Support for debugging, profiling, exception and interrupt handling, for reliability and security (*)Optimization for low power, low energy, low code and data size, and high (real-time) performance Tools for analysis, specification, design and implementation of embedded systems, including (*)Hardware, system software, and application, and their interface (*)Distributed real-time control, media players, reconfigurable architectures and other complex systems (*)Validation and verification, system integration and testing (*)Timing analysis, timing predictability, WCET analysis and real-time scheduling analysis (*)Performance monitoring and tuning (*)Runtime system support for embedded systems Novel embedded architectures (*)Design and implementation of novel embedded architectures (*)Workload analysis and performance evaluation (*)Architecture support for new language features, new compiler techniques and debugging tools Submission deadline: February 9, 2009 = (Please see the web site for details about paper submission.) Program Committee: == (*)Dhruva Chakrabarti (*)Swarat Chaudhuri (*)Bruce Childers (*)Andreas Krall (*)Prasad Kulkarni (*)Tei-Wei Kuo (*)Insup Lee (*)Liqian Luo (*)Jan Madsen (*)Sally McKee (*)Florence Maraninchi (*)Peter Marwedel (*)Frank Mueller (*)Tamiya Onodera (*)Alex Orailoglu (*)Emre Ozer (*)Preeti R. Panda (*)Tajana Simunic (*)Reinhard Wilhelm (*)Wayne Wolf (*)Wang Yi Steering Committee: === (*)Koen De Bosschere (*)Ron Cytron (*)Srinivas Devadas (*)Krisztian Flautner (*)Rajiv Gupta (*)Mary Jane Irwin (*)Annie Liu (*)Thomas Marlowe (*)Peter Marwedel (*)Frank Mueller (*)Yunheung Paek (*)Santosh Pande (*)John Regeher (*)Per Stenstrom (*)David Whalley (*)Reinhard Wilhelm General Chair: == Christoph Kirsch University of Salzburg Program Chair: == Mahmut Kandemir Penn State University Poster Chair: = Aviral Shrivastava Arizona State University Publicity Chair: Alain Girault INRIA Grenoble Rhône-Alpes -- - Alain GIRAULT http://pop-art.inrialpes.fr/~girault INRIA senior researcher tel: +(33|0) 476 61 53 51 Head of the POP ART project-teamfax: +(33|0) 476 61 52 52 - Sauvons la Recherche ! http://www.sauvonslarecherche.fr -
