Re: [U-Boot] [PATCH v8] Marvell Kirkwood family SOC support
> -Original Message- > From: u-boot-boun...@lists.denx.de > [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Prafulla Wadaskar > Sent: Wednesday, May 20, 2009 2:30 PM > To: Wolfgang Denk > Cc: u-boot@lists.denx.de; Ashish Karkare; Prabhanjan Sarnaik; > Ronen Shitrit > Subject: Re: [U-Boot] [PATCH v8] Marvell Kirkwood family SOC support > > Dear Wolfgand Denk > > Thanks for your review comments > > > -Original Message- > > From: Wolfgang Denk [mailto:w...@denx.de] > > Sent: Wednesday, May 20, 2009 3:29 AM > > To: Prafulla Wadaskar > > Cc: u-boot@lists.denx.de; Ashish Karkare; Prabhanjan Sarnaik; Ronen > > Shitrit > > Subject: Re: [U-Boot] [PATCH v8] Marvell Kirkwood family SOC support > > > > Dear Prafulla Wadaskar, > > > > In message > > <1242763678-13724-1-git-send-email-prafu...@marvell.com> you wrote: > > > > > > Kirkwood family controllers are highly integrated SOCs based on > > > Feroceon-88FR131/Sheeva-88SV131 cpu core. > > ... > > > +/* > > > + * Window Size > > > + * Used with the Base register to set the address window > > size and location. > > > + * Must be programmed from LSB to MSB as sequence of 1’s > > followed > > > +by > > > + * sequence of 0’s. The number of 1’s specifies the > > size of the > > > +window in > > > + * 64 KByte granularity (e.g., a value of 0x00FF specifies > > 256 = 16 MByte). > > > + * NOTE: A value of 0x0 specifies 64-KByte size. > > > + */ > > > > You have a number of strange special characters here. > Please try and > > restrict yourself to plain ASCII text in normal C comments. > I checked the patch that I send across and associated source code too. > I didn’t find the above special chars in it I am using > git-send-email to send the patches and vim as my editor I > wonder how these special characters appeared in the patch > I will check this issue with my system admin Hi Wolfgang Denk We have discovered the root cause of this problem I was using apostrophes, those were getting converted to weird characters by the mailer software (just a guess). I have replaced then with strings (i.e. "1's" with "ones" and "0's" with "zeros") Of course I will not release a new patch (V11) for this :-) but I have corrected at my end and will reflect in next patch after review feedback for V10 Thanks for pointing this... Regards.. Prafulla . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/6] mpc83xx: USB: Reorganized its support
> From: Kumar Gala [mailto:ga...@kernel.crashing.org] > > +#if defined(CONFIG_USB_PHY_TYPE) > > + "usb_phy_type=" MK_STR(CONFIG_USB_PHY_TYPE) "\0" > > +#endif > > #ifdef CONFIG_EXTRA_ENV_SETTINGS > > CONFIG_EXTRA_ENV_SETTINGS > > #endif > > I'm guessing Wolfgang isn't going to like this and suggest we > just do this via board specific setting of CONFIG_EXTRA_ENV_SETTINGS > > - k > Okay, that's doable. I will wait for comments from Wolfgang & others and will re-submit the patch series to this list following that. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] bootstrap nand write function
Hi Scott Yes thats the exact problem im going to face. But the function is a must. Could you help me understand what all are the things i will have to keep in mind if I have to write the nand write function.. i have made a list of instructions which i would have to follow from the datasheet: 1. Serial data input command - 0x80 2. 5 cycle address input 3. Serial Data loading 4 Page program confirm command - 0x10 5. read status register command - 0x70 my function just has to write over the environment variable part at 0x6 address could you tell me wat all things i shud take care of.? Regards, Deepak Gopalakrishnan Scott Wood 05/21/2009 10:21 PM To Deepak Gopalakrishnan cc u-boot@lists.denx.de Subject Re: [U-Boot] bootstrap nand write function On Thu, May 21, 2009 at 01:56:37PM +0530, Deepak Gopalakrishnan wrote: > Hi > i want to write a function using which i will be able to add a new env > variable from the bootstrap. > cud you help me with the sequence i should follow when im writing this > function... > thanks and regards, > Deepak Gopalakrishnan If by "bootstrap" you mean a 4K or so bit of code that loads the main u-boot into RAM, then there's probably not enough room to do that (at least not without hacking something together that is very special-purpose and doesn't use much of the existing environment or NAND infrastructure). -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please help for Data TLB Error in MPC8544
> My board can't boot normally, and I found it just hang in > data tlb error > through the system.map. > Could any one help for this? > Some regisers are as below: > > DEAR: 0xf400fff0 (L1 init ram base address is 0xf401) > IVPR : 0xfff8 , IVPR3: 0x04000 > EELADR: 0xf401 , CSn_BNDS: all 0x (I think SPD of > DDR is not > found yet) > L2MMU_TLB0 : 8400 5100 ff700 ff700 (CCSR is > not relocated to > 0xe000 yet) EELADR - 0XF401, it is INIT_RAM address, why the transaction with address(0xF401) go to system bus? It should keep in the cache due to cache lock, never out to system bus. > > > The TLB1 registers from CodeWarrior is as below: > = > L2MMU_CAM0 67CA 1C08 FFC0 FFC01 (boot flash, 4M) > L2MMU_CAM1 A0007FCA 1C08 8000 80001 (PCIE, 1G) > L2MMU_CAM2 90003FCA 1C08 C000 C0001 (PCI, 256M) > L2MMU_CAM3 90003FCA 1C08 D000 D0001 (PCI, 256M) > L2MMU_CAM4 80001FCA 1C08 E000 E0001 (CCSR, 64M) > L2MMU_CAM5 80001FCA 1C08 F000 F0001 (?? , 64M) > L2MMU_CAM6 30CA 1808 FF04 FF041 (NAND, 64K) > L2MMU_CAM7 2042 1808 FF01 FF011 (NAND, 16K) > L2MMU_CAM8 2042 1808 FF05 FF051 (NAND, 16K) > L2MMU_CAM9 C87FD651 EB4D 27DE6000 2397E000 > L2MMU_CAM10 D0E2E2DF EB680009 B494F000 8F634000 > L2MMU_CAM11 00FC8DCA 5A11000D BCB9B000 77EF6000 > L2MMU_CAM12 30CA 1808 FF00 FF01 (NAND, 64K) > L2MMU_CAM13 D891AFD8 18180002 50A7 F7AB6000 > L2MMU_CAM14 E0F6AE97 DA390009 F5DF6000 4F425000 > L2MMU_CAM15 D8EFEF88 C75F AEBA7000 3229F000 > === > > And this is my init.s below: > == > #include > #include > #include > #include > #include > #include > > #define LAWAR_TRGT_PCI1 0x > #define LAWAR_TRGT_PCIE1 0x0020 > #define LAWAR_TRGT_PCIE2 0x0010 > #define LAWAR_TRGT_PCIE3 0x0030 > #define LAWAR_TRGT_LBC0x0040 > #define LAWAR_TRGT_DDR0x00f0 > > #define entry_start \ > mflrr1 ; \ > bl 0f ; > > #define entry_end \ > 0:mflrr0 ; \ > mtlrr1 ; \ > blr ; > > > .section.bootpg, "ax" > .globl tlb1_entry > tlb1_entry: > entry_start > > /* >* Number of TLB0 and TLB1 entries in the following table >*/ > .long (2f-1f)/16 > 1: > /* >* TLB0 4K Non-cacheable, guarded >* 0xff70 4K Initial CCSRBAR mapping >* >* This ends up at a TLB0 Index==0 entry, and must not collide >* with other TLB0 Entries. >*/ > .long TLB1_MAS0(0, 0, 0) > .long TLB1_MAS1(1, 0, 0, 0, 0) > .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), > 0,0,0,0,1,0,1,0) > .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), > 0,0,0,0,0,1,0,1,0,1) > > /* >* TLB0 16K Cacheable, guarded >* Temporary Global data for initialization >* >* Use four 4K TLB0 entries. These entries must be cacheable >* as they provide the bootstrap memory before the memory >* controler and real memory have been configured. >* >* These entries end up at TLB0 Indicies 0x10, 0x14, > 0x18 and 0x1c, >* and must not collide with other TLB0 entries. >*/ > .long TLB1_MAS0(0, 0, 0) > .long TLB1_MAS1(1, 0, 0, 0, 0) > .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,0,1,0) > .long > TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,1,0,1,0,1) > > .long TLB1_MAS0(0, 0, 0) > .long TLB1_MAS1(1, 0, 0, 0, 0) > .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * > 1024),0,0,0,0,0,0,1,0) > .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * > 1024),0,0,0,0,0,1,0,1,0,1) > > .long TLB1_MAS0(0, 0, 0) > .long TLB1_MAS1(1, 0, 0, 0, 0) > .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * > 1024),0,0,0,0,0,0,1,0) > .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * > 1024),0,0,0,0,0,1,0,1,0,1) > > .long TLB1_MAS0(0, 0, 0) > .long TLB1_MAS1(1, 0, 0, 0, 0) > .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * > 1024),0,0,0,0,0,0,1,0) > .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * > 1024),0,0,0,0,0,1,0,1,0,1) > > > /* >* TLB 0: 4M Non-cacheable, guarded >* 0xffc0 4M Covers FLASH at 0xFFC0 >* Out of reset this entry is only 4K. >*/ > .long TLB1_MAS0(1, 0, 0) > .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M) > .long
Re: [U-Boot] [PATCH 00/11] 85xx/86xx dma updates
On Thu, 2009-05-21 at 12:37 -0700, Ira Snyder wrote: > On Thu, May 21, 2009 at 12:09:58PM -0500, Peter Tyser wrote: > > This patch series attempts to clean up the DMA implementation for the > > 85xx and 86xx architectures. The changes include: > > - consolidate 85xx and 86xx structures and code > > - add defines for bitfields > > - use proper IO accessors > > - add support for arbitrarily large transfer sizes > > - rename dma_xfer() to dmacpy() and make dmacpy's prototype similar > > to memcpy() > > > > The patches are based on the mainline "next" branch. > > > > I've tested the code on MPC8572 and MPC8640-based boards. > > > > I'm not initimately familar with the 83xx platform, but at a glance > > it looked like the fsl_dma driver could be extended to support it > > with some ifdeffery. > > > > I've been doing some Linux work with the 83xx DMA controller. The only > real differences between the 83xx/85xx controller are the register > endianness and snoop bits. The 83xx controller's registers are all > little-endian, while the 85xx is all big-endian. > > Also, there are some snoop bits that need to be enabled on 83xx as well, > in the control register as well as in each descriptor if you're running > in chaining mode. > > That's everything that I've noticed that is different. I don't have an > 85xx/86xx to test anything with, but I'm happy to run some tests on my > mpc8349emds if you want to try adding support for 83xx. Thanks! I believe some of the register locations are slightly different too, for example the source address on the 85xx is at offset 0x114 while its at 0x110 on the 83xx. I don't think any 83xx boards currently use the 83xx DMA implementation in cpu/mpc83xx/cpu.c. Before spending any time on the 83xx, is there any good reason to support the 83xx in U-Boot? There would be no users of the updated implementation as is. Best, Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/15 v3] Update the number of ethxaddr in reading system eeprom
We support up to 8 mac addresses in system eeprom, so we define the macro
MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
according to mac_count.
Signed-off-by: Haiying Wang
---
v3 change: Modify printf info and replace 8 with MAX_NUM_PORTS for array mac[]
board/freescale/common/sys_eeprom.c | 23 ++-
1 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/board/freescale/common/sys_eeprom.c
b/board/freescale/common/sys_eeprom.c
index 988cb94..ba44b6b 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006, 2008 Freescale Semiconductor
+ * Copyright 2006, 2008-2009 Freescale Semiconductor
* York Sun (york...@freescale.com)
* Haiying Wang (haiying.w...@freescale.com)
* Timur Tabi (ti...@freescale.com)
@@ -34,6 +34,8 @@
#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or
CONFIG_SYS_I2C_EEPROM_NXID"
#endif
+#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */
+
/**
* static eeprom: EEPROM layout for CCID or NXID formats
*
@@ -50,7 +52,7 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_0[40]; /* 0x18 - 0x3f Reserved */
u8 mac_count; /* 0x40Number of MAC addresses */
u8 mac_flag; /* 0x41MAC table flags */
- u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72CRC32 checksum */
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
@@ -66,7 +68,7 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40Number of MAC addresses */
u8 mac_flag; /* 0x41MAC table flags */
- u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72CRC32 checksum */
#endif
} e;
@@ -119,7 +121,8 @@ static void show_eeprom(void)
e.date[3] & 0x80 ? "PM" : "");
/* Show MAC addresses */
- for (i = 0; i < min(e.mac_count, 8); i++) {
+ for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
+
u8 *p = e.mac[i];
printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
@@ -404,7 +407,17 @@ int mac_read_from_eeprom(void)
}
}
- for (i = 0; i < min(4, e.mac_count); i++) {
+ /* Check the number of MAC addresses which is limited to
+* MAX_NUM_PORTS.
+*/
+ if (e.mac_count > MAX_NUM_PORTS) {
+ printf("Warning: The number of MAC addresses is greater"
+ " than %u, force it to %u.\n", MAX_NUM_PORTS,
+ MAX_NUM_PORTS);
+ e.mac_count = MAX_NUM_PORTS;
+ }
+
+ for (i = 0; i < e.mac_count; i++) {
if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
char ethaddr[18];
--
1.6.0.2
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Re: [U-Boot] [PATCH 08/11] 8xxx: Rename dma_xfer() to dmacpy()
On Thu, 2009-05-21 at 12:46 -0500, Scott Wood wrote:
> On Thu, May 21, 2009 at 12:10:06PM -0500, Peter Tyser wrote:
> > -int dma_xfer(void *dest, uint count, void *src) {
> > +int dmacpy(void *dest, const void *src, size_t n) {
>
> While we're changing this, perhaps it should take phys_addr_t rather than
> pointers?
It looks like addresses > 32bits can be used by using a few bits in the
SATR/DATR so you're right, using phys_addr_t/phys_size_t makes sense.
Thanks,
Peter
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Re: [U-Boot] [PATCH 10/15 v2] Update the number of ethxaddr in reading system eeprom
Dear Timur Tabi,
In message you
wrote:
> On Thu, May 21, 2009 at 2:34 PM, Haiying Wang
> wrote:
> > +printf("Warning: The number of MAC address > is greater"
> > +" than MAX_NUM_PORTS, force> it to MAX_NUM_PORTS.\n");
>
> I think you meant to do this:
>
> printf("Warning: The number of MAC address is greater"
> " than %u, force it to %u.\n", MAX_NUM_PORTS, MAX_NUM_POR>
> TS);
Actually it should be "number of MAC addresses", i. e. plural.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Anyone who isn't confused here doesn't really know what's going on.
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Re: [U-Boot] Support in u-boot for PCI-Express NIC
Dear "Srinivasan Srikanth-R9AABP", In message you wrote: > > > At least the e1000 has been successfully tested not so long ago. > > Thanks Wolfgang. That's good news. > Can you pl point me to the pci-express card/device id that was tested > recently (and/or the mails that talk about it)? I think that was it: commit aa3b8bf9c30065bb2ea852799d32db5020598495 Author: Wolfgang Grandegger Date: Wed May 28 19:55:19 2008 +0200 E1000: Add support for the 82541GI LF Intel Pro 1000 GT Desktop Adapter Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The joys of love made her human and the agonies of love destroyed her. -- Spock, "Requiem for Methuselah", stardate 5842.8 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/11] 85xx/86xx dma updates
On Thu, May 21, 2009 at 12:09:58PM -0500, Peter Tyser wrote: > This patch series attempts to clean up the DMA implementation for the > 85xx and 86xx architectures. The changes include: > - consolidate 85xx and 86xx structures and code > - add defines for bitfields > - use proper IO accessors > - add support for arbitrarily large transfer sizes > - rename dma_xfer() to dmacpy() and make dmacpy's prototype similar > to memcpy() > > The patches are based on the mainline "next" branch. > > I've tested the code on MPC8572 and MPC8640-based boards. > > I'm not initimately familar with the 83xx platform, but at a glance > it looked like the fsl_dma driver could be extended to support it > with some ifdeffery. > I've been doing some Linux work with the 83xx DMA controller. The only real differences between the 83xx/85xx controller are the register endianness and snoop bits. The 83xx controller's registers are all little-endian, while the 85xx is all big-endian. Also, there are some snoop bits that need to be enabled on 83xx as well, in the control register as well as in each descriptor if you're running in chaining mode. That's everything that I've noticed that is different. I don't have an 85xx/86xx to test anything with, but I'm happy to run some tests on my mpc8349emds if you want to try adding support for 83xx. Ira ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/15 v2] Update the number of ethxaddr in reading system eeprom
On Thu, May 21, 2009 at 2:34 PM, Haiying Wang
wrote:
> + printf("Warning: The number of MAC address is greater"
> + " than MAX_NUM_PORTS, force it to MAX_NUM_PORTS.\n");
I think you meant to do this:
printf("Warning: The number of MAC address is greater"
" than %u, force it to %u.\n", MAX_NUM_PORTS, MAX_NUM_PORTS);
But since you defined MAX_NUM_PORTS, you should also do this:
u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
To indicate where the dependency on 8 comes from.
--
Timur Tabi
Linux kernel developer at Freescale
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Re: [U-Boot] FLASH write bug on NGW100
>top-post :-)> Sorry.. a little to quick >> > > when using the latest u-boot version from >> > > git://www.denx.de/git/u-boot-avr32.git, it is not possible for me to >> > > write (I have tried saveenv and protect) to NOR FLASH anymore. >> > > >> > > U-Boot gives the following error: "start or end address not on sector >> > > boundary" >> > > >> > > Is this a known problem? >> > > >> > > Gerhard >> > > >> > >> > Post the exact commands you are using. Probably you are using wrong >> > addresses >> > >> >> The exact command: >> >> ?U-Boot> saveenv >> Saving Environment to Flash... >> Error: start and/or end address not on sector boundary >> >> Seriously, it's that easy. The addresses are the default ones found in >> include/configs/atngw100.h since the dawn of time :-) >> >> --Ben. >? >> On Wed, 2009-05-20 at 13:08 +0200, Eirik Aanonsen wrote: >> ?I dont have tha board. What result do you get if you run: Flinfo ( post it >> back here ) >On Wed, 2009-05-20 at 15:54 +0200, Gerhard Berghofer wrote: >> Hi Eirik, >> >> flinfo with u-boot version >= 2009.03 gives the following output: >> >> ## >> Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors >> AMD Standard command set, Manufacturer ID: 0x1F, Device ID: 0x1D6 >> Erase timeout: 8192 ms, write timeout: 1 ms >> Buffer write timeout: 1 ms, buffer size: 4 bytes >> >> Sector Start Addresses: >> A000A0002000A0004000A0006000 A0008000 >> >> A000A000A000C000A000E000A001 A002 >> >> A003A004A005A006 A007 >> > >... >> >> flinfo with u-boot version 2008.10 gives the following output: >> >> ## >> Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors >> AMD Standard command set, Manufacturer ID: 0x1F, Device ID: 0x1D6 >> Erase timeout: 8192 ms, write timeout: 1 ms >> Buffer write timeout: 1 ms, buffer size: 4 bytes >> >> Sector Start Addresses: >> RO 2000 RO 4000 RO 6000 RO 8000 >> RO >> A000 RO C000 RO E000 RO 0001 RO 0002 >> >> 00030004000500060007 >> >... >> ?the FLASH seems to be attached to a wrong address range ... >Well on the AVR32 both addresses are correct - the first accessed the >flash through the uncached, untranslatable segment, now it's both cached >and translated but that should only be a win. I guess though that the >environment address (which in the config is set to 007F) is still >somehow somewhere being translated to A07F then breaking all the >flash range checking. >But I'm kinda guessing here, I hope someone on the u-boot list can tell >us it's known and fixed and we should be have scoured their archives >harder ;-) > --Ben. How about to try and change the base to 0xA000 ? #define CONFIG_SYS_FLASH_BASE 0x That could help some on how to get the env address set ok.. Not sure of this would break the #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE Eirik Aanonsen SW Developer E-mail: e...@wprmedical.com Phone: +47 90 68 11 92 Fax: +47 37 03 56 77 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/15 v2] Update the number of ethxaddr in reading system eeprom
We support up to 8 mac addresses in system eeprom, so we define the macro
MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
according to mac_count.
Signed-off-by: Haiying Wang
---
v2 change: define MAC_NUM_PORTS to limit the mac_count
board/freescale/common/sys_eeprom.c | 16 +---
1 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/board/freescale/common/sys_eeprom.c
b/board/freescale/common/sys_eeprom.c
index 988cb94..671eb00 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006, 2008 Freescale Semiconductor
+ * Copyright 2006, 2008-2009 Freescale Semiconductor
* York Sun (york...@freescale.com)
* Haiying Wang (haiying.w...@freescale.com)
* Timur Tabi (ti...@freescale.com)
@@ -34,6 +34,8 @@
#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or
CONFIG_SYS_I2C_EEPROM_NXID"
#endif
+#define MAX_NUM_PORTS 8
+
/**
* static eeprom: EEPROM layout for CCID or NXID formats
*
@@ -119,7 +121,8 @@ static void show_eeprom(void)
e.date[3] & 0x80 ? "PM" : "");
/* Show MAC addresses */
- for (i = 0; i < min(e.mac_count, 8); i++) {
+ for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
+
u8 *p = e.mac[i];
printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
@@ -404,7 +407,14 @@ int mac_read_from_eeprom(void)
}
}
- for (i = 0; i < min(4, e.mac_count); i++) {
+ /* Check the number of MAC address which is limited to MAX_NUM_PORTS */
+ if (e.mac_count > MAX_NUM_PORTS) {
+ printf("Warning: The number of MAC address is greater"
+ " than MAX_NUM_PORTS, force it to MAX_NUM_PORTS.\n");
+ e.mac_count = MAX_NUM_PORTS;
+ }
+
+ for (i = 0; i < e.mac_count; i++) {
if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
char ethaddr[18];
--
1.6.0.2
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[U-Boot] [PATCH 06/15 v2] drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang
Acked-by: Timur Tabi
---
v2 change: rename riscRx and riscTx to risc_rx and risc_tx
drivers/qe/qe.c|3 ---
drivers/qe/qe.h| 17 +++--
drivers/qe/uec.c | 32 +++-
drivers/qe/uec.h |4 ++--
include/asm-ppc/immap_qe.h |8
5 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index f114fe0..30fe726 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -258,9 +258,6 @@ int qe_set_mii_clk_src(int ucc_num)
return 0;
}
-/* The maximum number of RISCs we support */
-#define MAX_QE_RISC 2
-
/* Firmware information stored here for qe_get_firmware_info() */
static struct qe_firmware_info qe_firmware_info;
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index d78edba..2128f56 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu
* based on source code of Shlomi Gridish
@@ -46,11 +46,16 @@ typedef struct qe_snum {
/* QE RISC allocation
*/
-typedef enum qe_risc_allocation {
- QE_RISC_ALLOCATION_RISC1= 1, /* RISC 1 */
- QE_RISC_ALLOCATION_RISC2= 2, /* RISC 2 */
- QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */
-} qe_risc_allocation_e;
+#defineQE_RISC_ALLOCATION_RISC10x1 /* RISC 1 */
+#defineQE_RISC_ALLOCATION_RISC20x2 /* RISC 2 */
+#defineQE_RISC_ALLOCATION_RISC30x4 /* RISC 3 */
+#defineQE_RISC_ALLOCATION_RISC40x8 /* RISC 4 */
+#defineQE_RISC_ALLOCATION_RISC1_AND_RISC2
(QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2)
+#defineQE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2 | \
+QE_RISC_ALLOCATION_RISC3 | \
+QE_RISC_ALLOCATION_RISC4)
/* QE CECR commands for UCC fast.
*/
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2..eadcc2c 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu
*
@@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RI
[U-Boot] [PATCH] drivers/qe: Rename the camel-case identifiers in uec
Rename riscRx/riscTx to risc_rx/risc_tx to comply with Codingstyle.
Signed-off-by: Haiying Wang
---
This patch should be applied before the 15 patches I sent out yesterday
drivers/qe/uec.c | 32
drivers/qe/uec.h |4 ++--
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2..e67c0ba 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -46,8 +46,8 @@ static uec_info_t eth1_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +69,8 @@ static uec_info_t eth2_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +92,8 @@ static uec_info_t eth3_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +115,8 @@ static uec_info_t eth4_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC4_PHY_ADDR,
@@ -138,8 +138,8 @@ static uec_info_t eth5_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC5_PHY_ADDR,
@@ -161,8 +161,8 @@ static uec_info_t eth6_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC6_PHY_ADDR,
@@ -1020,7 +1020,7 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t
*uec,
/* Init Rx global parameter pointer */
p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
-(u32)uec_info->riscRx;
+(u32)uec_info->risc_rx;
/* Init Rx threads */
for (i = 0; i < (thread_rx + 1); i++) {
@@ -1038,13 +1038,13 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t
*uec,
}
entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
-init_enet_offset | (u32)uec_info->riscRx;
+init_enet_offset | (u32)uec_info->risc_rx;
p_init_enet_param->rxthread[i] = entry_val;
}
/* Init Tx global parameter pointer */
p_init_enet_param->txglobal = uec
Re: [U-Boot] [PATCH 08/11] 8xxx: Rename dma_xfer() to dmacpy()
On Thu, May 21, 2009 at 12:10:06PM -0500, Peter Tyser wrote:
> -int dma_xfer(void *dest, uint count, void *src) {
> +int dmacpy(void *dest, const void *src, size_t n) {
While we're changing this, perhaps it should take phys_addr_t rather than
pointers?
-Scott
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[U-Boot] beagleboard, and building only host tools from u-boot
a couple short questions. first, is the denx git repo reasonably up-to-date WRT beagleboard support? it would appear to be since include/configs contains the appropriate omap3_beagle.h file, i just wasn't sure how quickly any BB enhancements got committed. and is there technically any need for a working cross-compiler if all i want to do is build the host-side tools? specifically, if i want to build "mkimage?" i ask since the build structure for android required a host-side mkimage, so i need to build and install that on the host before i can do the actual android build. but since mkimage runs on the build host, i don't see an immediate need for an ARM cross-compiler, and yet you can do "make tools" without one. is there any way around this? i'm just curious. rday -- Robert P. J. Day Waterloo, Ontario, CANADA Linux Consulting, Training and Annoying Kernel Pedantry. Web page: http://crashcourse.ca Linked In: http://www.linkedin.com/in/rpjday Twitter: http://twitter.com/rpjday ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC/PATCH 2/3] mtest: Add optional support for DMA memory test
Add a basic memory test which uses a DMA engine to perform a memory
copy. The DMA copies generally result in burst transactions to SDRAM
which can otherwise be hard to generate on boards which don't have
their data cache enabled.
The DMA memory test is enabled when CONFIG_SYS_ALT_MEMTEST and
CONFIG_SYS_DMA_MEMTEST are defined and requires dmacpy() to be
implemented.
Signed-off-by: Peter Tyser
---
common/cmd_mem.c | 65 ++
1 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 2d4fc2a..9e6ee4b 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -618,6 +618,65 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
}
#endif /* CONFIG_LOOPW */
+#if (defined(CONFIG_SYS_ALT_MEMTEST) && defined(CONFIG_SYS_DMA_MEMTEST))
+/*
+ * DMA memory test: Fill the 1st half of the test region with a known,
+ * semi random pattern, DMA it to the 2nd half of the test region,
+ * and verify region 2. The DMA memory test is useful in
+ * stressing memory as it generally results in bursts which are otherwise
+ * difficult to generate if testing SDRAM before caches are enabled
+ * or enabling caches makes a board unstable.
+ */
+int memtest_dma(vu_long *start, vu_long *end)
+{
+ ulong len = ((ulong)end - (ulong)start) / 2;
+ ulong *halfway = (ulong*)(((ulong)start) + len);
+ ulong rand;
+ ulong readback;
+ ulong pattern;
+ vu_long *addr;
+ ulong val;
+ int i;
+
+ /* Generate a random number ala K&R */
+ rand = get_timer(0) * 1103515245 + 12345;
+ pattern = (rand % 0x1) << 16;
+ rand = rand * 1103515245 + 12345;
+ pattern |= (rand % 0x1);
+
+ for (i = 0; i < 2; i++) {
+ /* Fill 1st half of test region with a known pattern */
+ for (addr = start, val = pattern; addr < halfway; addr++) {
+ WATCHDOG_RESET();
+ *addr = val;
+ val = (val & 0x8000) ? -val : ~val;
+ }
+
+ /* Perform the transfer to fill in 2nd half of test region */
+ dmacpy(halfway, (void*)start, len);
+ WATCHDOG_RESET();
+
+ /* Verify 2nd half of the test region */
+ for (addr = halfway, val = pattern; addr < end; addr++) {
+ WATCHDOG_RESET();
+ readback = *addr;
+ if (readback != val) {
+ printf ("\nFAILURE: DMA memory test @ %p:"
+ " expected 0x%.8lx, actual 0x%.8lx\n",
+ addr, readback, val);
+ return 1;
+ }
+ val = (val & 0x8000) ? -val : ~val;
+ }
+
+ /* Invert pattern for 2nd iteration */
+ pattern = ~pattern;
+ }
+
+ return 0;
+}
+#endif
+
/*
* Perform a memory test. A more complete alternative test can be
* configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until
@@ -883,8 +942,14 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
}
start[offset] = 0;
}
+
+#if defined(CONFIG_SYS_DMA_MEMTEST)
+ if (memtest_dma(start, end))
+ return 1;
+#endif
}
+
#else /* The original, quickie test */
incr = 1;
for (;;) {
--
1.6.2.1
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[U-Boot] [RFC/PATCH 0/3] Add optional dma transfers to mtest
This series tries to add a DMA memory test to the mtest tests. The DMA test performs bursts to SDRAM which can be useful in stressing memory and can be difficult to produce reliably in certain circumstances (eg running with data caches disabled). It can be enabled on 85xx and 86xx boards by defining CONFIG_FSL_DMA, CONFIG_SYS_ALT_MEMTEST, and CONFIG_SYS_DMA_MEMTEST. Other platforms will need to support the dmacpy() function in order to enable the DMA memory test. Peter Tyser (3): fsl_dma: Make DMA transactions snoopable mtest: Add optional support for DMA memory test XPedite5200, XPedite5370: Enable DMA memory test common/cmd_mem.c | 65 + drivers/dma/fsl_dma.c |4 +- include/configs/XPEDITE5200.h |4 ++- include/configs/XPEDITE5370.h |2 + 4 files changed, 72 insertions(+), 3 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC/PATCH 3/3] XPedite5200, XPedite5370: Enable DMA memory test
Enable the Freescale DMA driver and DMA portion of mtest for the XPedite5200 and XPedite5370 boards Signed-off-by: Peter Tyser --- include/configs/XPEDITE5200.h |4 +++- include/configs/XPEDITE5370.h |2 ++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index 89ab692..11c9690 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -88,6 +88,7 @@ * Diagnostics */ #define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_DMA_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x1000 #define CONFIG_SYS_MEMTEST_END 0x2000 @@ -361,7 +362,8 @@ #define CONFIG_FIT 1 #define CONFIG_FIT_VERBOSE 1 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_DMA /* Enable Freescale DMA engine */ /* * For booting Linux, the board info and command line data diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 536e063..10e00d8 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -100,6 +100,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Diagnostics */ #define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_DMA_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x1000 #define CONFIG_SYS_MEMTEST_END 0x2000 @@ -405,6 +406,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FIT 1 #define CONFIG_FIT_VERBOSE 1 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ +#define CONFIG_FSL_DMA /* Enable Freescale DMA engine */ /* * For booting Linux, the board info and command line data -- 1.6.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC/PATCH 1/3] fsl_dma: Make DMA transactions snoopable
Make DMA transactions snoopable so that CPUs can keep caches up-to-date.
This allows dma transactions to be used for operations such as memory
copies without any additional cache control operations.
Signed-off-by: Peter Tyser
---
drivers/dma/fsl_dma.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index b7497b5..572f8b6 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -72,8 +72,8 @@ static uint dma_check(void) {
void dma_init(void) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
- out_be32(&dma->satr, FSL_DMA_SATR_SREAD_NO_SNOOP);
- out_be32(&dma->datr, FSL_DMA_DATR_DWRITE_NO_SNOOP);
+ out_be32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
+ out_be32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
out_be32(&dma->sr, 0x); /* clear any errors */
dma_sync();
}
--
1.6.2.1
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[U-Boot] [PATCH 10/11] 85xx, 86xx: Move dma_init() call to common code
Signed-off-by: Peter Tyser
---
board/mpc8540eval/mpc8540eval.c |2 +-
board/sbc8560/sbc8560.c |2 +-
cpu/mpc85xx/cpu_init.c |4 +++-
cpu/mpc85xx/ddr-gen1.c |2 --
cpu/mpc86xx/cpu_init.c |3 +++
5 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index 3d395c6..27d7a3d 100644
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -140,7 +140,7 @@ phys_size_t initdram (int board_type)
uint *p = 0;
uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_init();
+
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
*p = (unsigned int)0xdeadbeef;
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index 0b8e3e5..64d4154 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -341,7 +341,7 @@ phys_size_t initdram (int board_type)
uint *p = 0;
uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_init();
+
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
*p = (unsigned int)0xdeadbeef;
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index c98dd8d..41de694 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -261,7 +261,9 @@ void cpu_init_f (void)
#if defined(CONFIG_MPC8536)
fsl_serdes_init();
#endif
-
+#if defined(CONFIG_FSL_DMA)
+ dma_init();
+#endif
}
diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c
index 6e628bd..5529021 100644
--- a/cpu/mpc85xx/ddr-gen1.c
+++ b/cpu/mpc85xx/ddr-gen1.c
@@ -77,8 +77,6 @@ ddr_enable_ecc(unsigned int dram_size)
uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_init();
-
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) {
ppcDcbz((unsigned long) p);
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 49528aa..341e815 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -113,6 +113,9 @@ void cpu_init_f(void)
memctl->or7 = CONFIG_SYS_OR7_PRELIM;
memctl->br7 = CONFIG_SYS_BR7_PRELIM;
#endif
+#if defined(CONFIG_FSL_DMA)
+ dma_init();
+#endif
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x400);
--
1.6.2.1
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[U-Boot] [PATCH 08/11] 8xxx: Rename dma_xfer() to dmacpy()
Also update dmacpy()'s argument order and type to match memcpy's for
clarity
Signed-off-by: Peter Tyser
---
board/mpc8540eval/mpc8540eval.c | 22 +++---
board/sbc8560/sbc8560.c | 22 +++---
cpu/mpc83xx/cpu.c |4 ++--
cpu/mpc83xx/spd_sdram.c | 24
cpu/mpc85xx/ddr-gen1.c | 24
drivers/dma/fsl_dma.c | 12 ++--
6 files changed, 54 insertions(+), 54 deletions(-)
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index 72a1ad3..3d395c6 100644
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -148,28 +148,28 @@ phys_size_t initdram (int board_type)
}
/* 8K */
- dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+ dmacpy((uint *)0x2000, (uint *)0, 0x2000);
/* 16K */
- dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+ dmacpy((uint *)0x4000, (uint *)0, 0x4000);
/* 32K */
- dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+ dmacpy((uint *)0x8000, (uint *)0, 0x8000);
/* 64K */
- dma_xfer((uint *)0x1,0x1,(uint *)0);
+ dmacpy((uint *)0x1, (uint *)0, 0x1);
/* 128k */
- dma_xfer((uint *)0x2,0x2,(uint *)0);
+ dmacpy((uint *)0x2, (uint *)0, 0x2);
/* 256k */
- dma_xfer((uint *)0x4,0x4,(uint *)0);
+ dmacpy((uint *)0x4, (uint *)0, 0x4);
/* 512k */
- dma_xfer((uint *)0x8,0x8,(uint *)0);
+ dmacpy((uint *)0x8, (uint *)0, 0x8);
/* 1M */
- dma_xfer((uint *)0x10,0x10,(uint *)0);
+ dmacpy((uint *)0x10, (uint *)0, 0x10);
/* 2M */
- dma_xfer((uint *)0x20,0x20,(uint *)0);
+ dmacpy((uint *)0x20, (uint *)0, 0x20);
/* 4M */
- dma_xfer((uint *)0x40,0x40,(uint *)0);
+ dmacpy((uint *)0x40, (uint *)0, 0x40);
for (i = 1; i < dram_size / 0x80; i++) {
- dma_xfer((uint *)(0x80*i),0x80,(uint *)0);
+ dmacpy((uint *)(0x80*i), (uint *)0, 0x80);
}
/* Enable errors for ECC */
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index 7f032c8..0b8e3e5 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -349,28 +349,28 @@ phys_size_t initdram (int board_type)
}
/* 8K */
- dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+ dmacpy((uint *)0x2000, (uint *)0, 0x2000);
/* 16K */
- dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+ dmacpy((uint *)0x4000, (uint *)0, 0x4000);
/* 32K */
- dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+ dmacpy((uint *)0x8000, (uint *)0, 0x8000);
/* 64K */
- dma_xfer((uint *)0x1,0x1,(uint *)0);
+ dmacpy((uint *)0x1, (uint *)0, 0x1);
/* 128k */
- dma_xfer((uint *)0x2,0x2,(uint *)0);
+ dmacpy((uint *)0x2, (uint *)0, 0x2);
/* 256k */
- dma_xfer((uint *)0x4,0x4,(uint *)0);
+ dmacpy((uint *)0x4, (uint *)0, 0x4);
/* 512k */
- dma_xfer((uint *)0x8,0x8,(uint *)0);
+ dmacpy((uint *)0x8, (uint *)0, 0x8);
/* 1M */
- dma_xfer((uint *)0x10,0x10,(uint *)0);
+ dmacpy((uint *)0x10, (uint *)0, 0x10);
/* 2M */
- dma_xfer((uint *)0x20,0x20,(uint *)0);
+ dmacpy((uint *)0x20, (uint *)0, 0x20);
/* 4M */
- dma_xfer((uint *)0x40,0x40,(uint *)0);
+ dmacpy((uint *)0x40, (uint *)0, 0x40);
for (i = 1; i < dram_size / 0x80; i++) {
- dma_xfer((uint *)(0x80*i),0x80,(uint *)0);
+ dmacpy((uint *)(0x80*i), (uint *)0, 0x80);
}
/* Enable errors for ECC */
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 876f5c7..3b93a32 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -327,7 +327,7 @@ uint dma_check(void)
return status;
}
-int dma_xfer(void *dest, u32 count, void *src)
+int dmacpy(void *dest, const void *src, size_t count)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile dma83xx_t *dma = &immap->dma;
@@ -336,7 +336,7 @@ int dma_xfer(void *dest, u32 count, voi
[U-Boot] [PATCH 02/11] 85xx, 86xx: Sync up DMA code
The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:
85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register. These bits
only have an affect when the SBPATMU bit is set.
- Write 0x instead of 0xfff to clear errors in the DMA
status register. We may as well clear all 32 bits of the register...
86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
the controller
- Clear the channel start bit in the DMA mode register after a transfer
Signed-off-by: Peter Tyser
---
cpu/mpc85xx/cpu.c|8
cpu/mpc86xx/cpu.c| 14 --
include/asm-ppc/immap_86xx.h |2 ++
3 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 8c57404..86b19a6 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -263,9 +263,9 @@ void dma_init(void) {
volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->satr = 0x02c4;
- dma->datr = 0x02c4;
- dma->sr = 0xfff; /* clear any errors */
+ dma->satr = 0x0004;
+ dma->datr = 0x0004;
+ dma->sr = 0x; /* clear any errors */
asm("sync; isync; msync");
return;
}
@@ -280,7 +280,7 @@ uint dma_check(void) {
status = dma->sr;
}
- /* clear MR0[CS] channel start bit */
+ /* clear MR[CS] channel start bit */
dma->mr &= 0x0001;
asm("sync;isync;msync");
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index f35323a..d47cc5e 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -182,20 +182,19 @@ watchdog_reset(void)
void
dma_init(void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_dma_t *dma_base = &immap->im_dma;
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
volatile fsl_dma_t *dma = &dma_base->dma[0];
dma->satr = 0x0004;
dma->datr = 0x0004;
+ dma->sr = 0x; /* clear any errors */
asm("sync; isync");
}
uint
dma_check(void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_dma_t *dma_base = &immap->im_dma;
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
volatile fsl_dma_t *dma = &dma_base->dma[0];
volatile uint status = dma->sr;
@@ -204,6 +203,10 @@ dma_check(void)
status = dma->sr;
}
+ /* clear MR[CS] channel start bit */
+ dma->mr &= 0x0001;
+ asm("sync;isync");
+
if (status != 0) {
printf("DMA Error: status = %x\n", status);
}
@@ -213,8 +216,7 @@ dma_check(void)
int
dma_xfer(void *dest, uint count, void *src)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_dma_t *dma_base = &immap->im_dma;
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
volatile fsl_dma_t *dma = &dma_base->dma[0];
dma->dar = (uint) dest;
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 689c720..a839834 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1295,5 +1295,7 @@ extern immap_t *immr;
#define CONFIG_SYS_MPC86xx_DDR_ADDR(CONFIG_SYS_IMMR +
CONFIG_SYS_MPC86xx_DDR_OFFSET)
#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000)
#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR +
CONFIG_SYS_MPC86xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000)
+#define CONFIG_SYS_MPC86xx_DMA_ADDR(CONFIG_SYS_IMMR +
CONFIG_SYS_MPC86xx_DMA_OFFSET)
#endif /*__IMMAP_86xx__*/
--
1.6.2.1
___
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[U-Boot] [PATCH 06/11] fsl_dma: Add support for arbitrarily large transfers
Support DMA transfers larger than the DMA controller's limit of
(2 ^ 26 - 1) bytes
Signed-off-by: Peter Tyser
---
drivers/dma/fsl_dma.c | 42 ++
1 files changed, 30 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index 33ea828..91a6d84 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -30,6 +30,9 @@
#include
#include
+/* Controller can only transfer 2^26 - 1 bytes at a time */
+#define FSL_DMA_MAX_SIZE (0x3ff)
+
#if defined(CONFIG_MPC85xx)
ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
#elif defined(CONFIG_MPC86xx)
@@ -77,20 +80,35 @@ void dma_init(void) {
int dma_xfer(void *dest, uint count, void *src) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
+ uint xfer_size;
- out_be32(&dma->dar, (uint) dest);
- out_be32(&dma->sar, (uint) src);
- out_be32(&dma->bcr, count);
+ while (count) {
+ xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
- /* Disable bandwidth control, use direct transfer mode */
- out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT);
- dma_sync();
+ debug("count = 0x%x, xfer_size = 0x%x, src = %p, dest = %p\n",
+ count, xfer_size, src, dest);
+ out_be32(&dma->dar, (uint) dest);
+ out_be32(&dma->sar, (uint) src);
+ out_be32(&dma->bcr, xfer_size);
- /* Start the transfer */
- out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS |
- FSL_DMA_MR_CTM_DIRECT |
- FSL_DMA_MR_CS);
- dma_sync();
+ /* Disable bandwidth control, use direct transfer mode */
+ out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT);
+ dma_sync();
+
+ /* Start the transfer */
+ out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS |
+ FSL_DMA_MR_CTM_DIRECT |
+ FSL_DMA_MR_CS);
+
+ count -= xfer_size;
+ src += xfer_size;
+ dest += xfer_size;
+
+ dma_sync();
+
+ if (dma_check())
+ return -1;
+ }
- return dma_check();
+ return 0;
}
--
1.6.2.1
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[U-Boot] [PATCH 03/11] 85xx, 86xx: Break out DMA code to a common file
DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
previous CONFIG_DDR_ECC
Signed-off-by: Peter Tyser
---
cpu/mpc85xx/cpu.c | 47
cpu/mpc86xx/cpu.c | 55
drivers/dma/Makefile|1 +
drivers/dma/fsl_dma.c | 92 +++
include/configs/PM854.h |1 +
include/configs/PM856.h |1 +
6 files changed, 95 insertions(+), 102 deletions(-)
create mode 100644 drivers/dma/fsl_dma.c
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 86b19a6..416ea08 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -258,53 +258,6 @@ reset_85xx_watchdog(void)
}
#endif /* CONFIG_WATCHDOG */
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void) {
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->satr = 0x0004;
- dma->datr = 0x0004;
- dma->sr = 0x; /* clear any errors */
- asm("sync; isync; msync");
- return;
-}
-
-uint dma_check(void) {
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
- volatile uint status = dma->sr;
-
- /* While the channel is busy, spin */
- while((status & 4) == 4) {
- status = dma->sr;
- }
-
- /* clear MR[CS] channel start bit */
- dma->mr &= 0x0001;
- asm("sync;isync;msync");
-
- if (status != 0) {
- printf ("DMA Error: status = %x\n", status);
- }
- return status;
-}
-
-int dma_xfer(void *dest, uint count, void *src) {
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->dar = (uint) dest;
- dma->sar = (uint) src;
- dma->bcr = count;
- dma->mr = 0xf04;
- asm("sync;isync;msync");
- dma->mr = 0xf05;
- asm("sync;isync;msync");
- return dma_check();
-}
-#endif
-
/*
* Configures a UPM. The function requires the respective MxMR to be set
* before calling this function. "size" is the number or entries, not a sizeof.
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index d47cc5e..1f26ba1 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -177,61 +177,6 @@ watchdog_reset(void)
}
#endif /* CONFIG_WATCHDOG */
-
-#if defined(CONFIG_DDR_ECC)
-void
-dma_init(void)
-{
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->satr = 0x0004;
- dma->datr = 0x0004;
- dma->sr = 0x; /* clear any errors */
- asm("sync; isync");
-}
-
-uint
-dma_check(void)
-{
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
- volatile uint status = dma->sr;
-
- /* While the channel is busy, spin */
- while ((status & 4) == 4) {
- status = dma->sr;
- }
-
- /* clear MR[CS] channel start bit */
- dma->mr &= 0x0001;
- asm("sync;isync");
-
- if (status != 0) {
- printf("DMA Error: status = %x\n", status);
- }
- return status;
-}
-
-int
-dma_xfer(void *dest, uint count, void *src)
-{
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->dar = (uint) dest;
- dma->sar = (uint) src;
- dma->bcr = count;
- dma->mr = 0xf04;
- asm("sync;isync");
- dma->mr = 0xf05;
- asm("sync;isync");
- return dma_check();
-}
-
-#endif /* CONFIG_DDR_ECC */
-
-
/*
* Print out the state of various machine registers.
* Currently prints out LAWs, BR0/OR0, and BATs
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index cf29efa..36d99f9 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libdma.a
COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
+COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
new file mode 100644
index 000..a9989ee
--- /dev/null
+++ b/drivers/dma/fsl_dma.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
+ * (C) Copyright 2002, 2003 Motorola Inc.
+ * Xianghua Xiao (x.x...@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at y
[U-Boot] [PATCH 11/11] fsl_dma: Break out common memory initialization function
Signed-off-by: Peter Tyser
---
board/mpc8540eval/mpc8540eval.c | 33 +
board/sbc8560/sbc8560.c | 33 +
cpu/mpc85xx/ddr-gen1.c | 27 +--
drivers/dma/fsl_dma.c | 32
include/asm-ppc/fsl_dma.h |3 +++
5 files changed, 38 insertions(+), 90 deletions(-)
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index 27d7a3d..7c27233 100644
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -137,40 +137,9 @@ phys_size_t initdram (int board_type)
{
/* Initialize all of memory for ECC, then
* enable errors */
- uint *p = 0;
- uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
- if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
- *p = (unsigned int)0xdeadbeef;
- if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
- }
-
- /* 8K */
- dmacpy((uint *)0x2000, (uint *)0, 0x2000);
- /* 16K */
- dmacpy((uint *)0x4000, (uint *)0, 0x4000);
- /* 32K */
- dmacpy((uint *)0x8000, (uint *)0, 0x8000);
- /* 64K */
- dmacpy((uint *)0x1, (uint *)0, 0x1);
- /* 128k */
- dmacpy((uint *)0x2, (uint *)0, 0x2);
- /* 256k */
- dmacpy((uint *)0x4, (uint *)0, 0x4);
- /* 512k */
- dmacpy((uint *)0x8, (uint *)0, 0x8);
- /* 1M */
- dmacpy((uint *)0x10, (uint *)0, 0x10);
- /* 2M */
- dmacpy((uint *)0x20, (uint *)0, 0x20);
- /* 4M */
- dmacpy((uint *)0x40, (uint *)0, 0x40);
-
- for (i = 1; i < dram_size / 0x80; i++) {
- dmacpy((uint *)(0x80*i), (uint *)0, 0x80);
- }
+ dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
/* Enable errors for ECC */
ddr->err_disable = 0x;
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index 64d4154..c40b5e3 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -338,40 +338,9 @@ phys_size_t initdram (int board_type)
{
/* Initialize all of memory for ECC, then
* enable errors */
- uint *p = 0;
- uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
- if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
- *p = (unsigned int)0xdeadbeef;
- if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
- }
-
- /* 8K */
- dmacpy((uint *)0x2000, (uint *)0, 0x2000);
- /* 16K */
- dmacpy((uint *)0x4000, (uint *)0, 0x4000);
- /* 32K */
- dmacpy((uint *)0x8000, (uint *)0, 0x8000);
- /* 64K */
- dmacpy((uint *)0x1, (uint *)0, 0x1);
- /* 128k */
- dmacpy((uint *)0x2, (uint *)0, 0x2);
- /* 256k */
- dmacpy((uint *)0x4, (uint *)0, 0x4);
- /* 512k */
- dmacpy((uint *)0x8, (uint *)0, 0x8);
- /* 1M */
- dmacpy((uint *)0x10, (uint *)0, 0x10);
- /* 2M */
- dmacpy((uint *)0x20, (uint *)0, 0x20);
- /* 4M */
- dmacpy((uint *)0x40, (uint *)0, 0x40);
-
- for (i = 1; i < dram_size / 0x80; i++) {
- dmacpy((uint *)(0x80*i), (uint *)0, 0x80);
- }
+ dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
/* Enable errors for ECC */
ddr->err_disable = 0x;
diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c
index 5529021..54437dd 100644
--- a/cpu/mpc85xx/ddr-gen1.c
+++ b/cpu/mpc85xx/ddr-gen1.c
@@ -73,34 +73,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
void
ddr_enable_ecc(unsigned int dram_size)
{
- uint *p = 0;
- uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
- if (((unsigned int)p & 0x1f) == 0) {
- ppcDcbz((unsigned long) p);
- }
- *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
- if (((unsigned int)p & 0x1c) == 0x1c) {
- ppcD
[U-Boot] [PATCH 09/11] fsl_dma: Move dma function prototypes to common header file
Signed-off-by: Peter Tyser
---
cpu/mpc85xx/ddr-gen1.c|4
include/asm-ppc/fsl_dma.h |5 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c
index 7c7a458..6e628bd 100644
--- a/cpu/mpc85xx/ddr-gen1.c
+++ b/cpu/mpc85xx/ddr-gen1.c
@@ -66,10 +66,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
}
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void dma_init(void);
-extern uint dma_check(void);
-extern int dmacpy(void *dest, const void *src, size_t n);
-
/*
* Initialize all of memory for ECC, then enable errors.
*/
diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h
index c9ec6b5..06ecdcd 100644
--- a/include/asm-ppc/fsl_dma.h
+++ b/include/asm-ppc/fsl_dma.h
@@ -94,4 +94,9 @@ typedef struct fsl_dma {
charres4[56];
} fsl_dma_t;
+#ifdef CONFIG_FSL_DMA
+void dma_init(void);
+int dmacpy(void *dest, const void *src, size_t n);
+#endif
+
#endif /* _ASM_DMA_H_ */
--
1.6.2.1
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[U-Boot] [PATCH 07/11] fsl_dma: Fix Channel Start bug in dma_check()
The Channel Start (CS) bit in the Mode Register (MR) should actually be
cleared as the comment in the code suggests. Previously, CS was being
set, not cleared.
Assuming normal operation of the DMA engine, this change shouldn't have
any real affect.
Signed-off-by: Peter Tyser
---
drivers/dma/fsl_dma.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index 91a6d84..d41f04c 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -60,7 +60,7 @@ static uint dma_check(void) {
} while (status & FSL_DMA_SR_CB);
/* clear MR[CS] channel start bit */
- out_be32(&dma->mr, in_be32(&dma->mr) & FSL_DMA_MR_CS);
+ out_be32(&dma->mr, in_be32(&dma->mr) & ~FSL_DMA_MR_CS);
dma_sync();
if (status != 0)
--
1.6.2.1
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[U-Boot] [PATCH 05/11] fsl_dma: Update to use proper I/O accessor functions
Signed-off-by: Peter Tyser
---
drivers/dma/fsl_dma.c | 32 ++--
1 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index baf2942..33ea828 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -27,12 +27,13 @@
#include
#include
+#include
#include
#if defined(CONFIG_MPC85xx)
-volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
#elif defined(CONFIG_MPC86xx)
-volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
+ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
#else
#error "Freescale DMA engine not supported on your processor"
#endif
@@ -48,14 +49,15 @@ static void dma_sync(void)
static uint dma_check(void) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
- volatile uint status = dma->sr;
+ uint status;
/* While the channel is busy, spin */
- while (status & FSL_DMA_SR_CB)
- status = dma->sr;
+ do {
+ status = in_be32(&dma->sr);
+ } while (status & FSL_DMA_SR_CB);
/* clear MR[CS] channel start bit */
- dma->mr &= FSL_DMA_MR_CS;
+ out_be32(&dma->mr, in_be32(&dma->mr) & FSL_DMA_MR_CS);
dma_sync();
if (status != 0)
@@ -67,25 +69,27 @@ static uint dma_check(void) {
void dma_init(void) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->satr = FSL_DMA_SATR_SREAD_NO_SNOOP;
- dma->datr = FSL_DMA_DATR_DWRITE_NO_SNOOP;
- dma->sr = 0x; /* clear any errors */
+ out_be32(&dma->satr, FSL_DMA_SATR_SREAD_NO_SNOOP);
+ out_be32(&dma->datr, FSL_DMA_DATR_DWRITE_NO_SNOOP);
+ out_be32(&dma->sr, 0x); /* clear any errors */
dma_sync();
}
int dma_xfer(void *dest, uint count, void *src) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->dar = (uint) dest;
- dma->sar = (uint) src;
- dma->bcr = count;
+ out_be32(&dma->dar, (uint) dest);
+ out_be32(&dma->sar, (uint) src);
+ out_be32(&dma->bcr, count);
/* Disable bandwidth control, use direct transfer mode */
- dma->mr = FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT;
+ out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT);
dma_sync();
/* Start the transfer */
- dma->mr = FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_CS;
+ out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS |
+ FSL_DMA_MR_CTM_DIRECT |
+ FSL_DMA_MR_CS);
dma_sync();
return dma_check();
--
1.6.2.1
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[U-Boot] [PATCH 01/11] fsl: Create common fsl_dma.h for 85xx and 86xx cpus
Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication
Signed-off-by: Peter Tyser
---
cpu/mpc85xx/cpu.c| 31 +
cpu/mpc86xx/cpu.c| 27 ---
include/asm-ppc/fsl_dma.h| 51
include/asm-ppc/immap_85xx.h | 76 ++
include/asm-ppc/immap_86xx.h | 76 ++
5 files changed, 89 insertions(+), 172 deletions(-)
create mode 100644 include/asm-ppc/fsl_dma.h
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index ef976a4..8c57404 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -260,26 +260,28 @@ reset_85xx_watchdog(void)
#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
- volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->satr0 = 0x02c4;
- dma->datr0 = 0x02c4;
- dma->sr0 = 0xfff; /* clear any errors */
+ dma->satr = 0x02c4;
+ dma->datr = 0x02c4;
+ dma->sr = 0xfff; /* clear any errors */
asm("sync; isync; msync");
return;
}
uint dma_check(void) {
- volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile uint status = dma->sr0;
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
+ volatile uint status = dma->sr;
/* While the channel is busy, spin */
while((status & 4) == 4) {
- status = dma->sr0;
+ status = dma->sr;
}
/* clear MR0[CS] channel start bit */
- dma->mr0 &= 0x0001;
+ dma->mr &= 0x0001;
asm("sync;isync;msync");
if (status != 0) {
@@ -289,14 +291,15 @@ uint dma_check(void) {
}
int dma_xfer(void *dest, uint count, void *src) {
- volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->dar0 = (uint) dest;
- dma->sar0 = (uint) src;
- dma->bcr0 = count;
- dma->mr0 = 0xf04;
+ dma->dar = (uint) dest;
+ dma->sar = (uint) src;
+ dma->bcr = count;
+ dma->mr = 0xf04;
asm("sync;isync;msync");
- dma->mr0 = 0xf05;
+ dma->mr = 0xf05;
asm("sync;isync;msync");
return dma_check();
}
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 653a137..f35323a 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -183,10 +183,11 @@ void
dma_init(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma_base = &immap->im_dma;
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->satr0 = 0x0004;
- dma->datr0 = 0x0004;
+ dma->satr = 0x0004;
+ dma->datr = 0x0004;
asm("sync; isync");
}
@@ -194,12 +195,13 @@ uint
dma_check(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
- volatile uint status = dma->sr0;
+ volatile ccsr_dma_t *dma_base = &immap->im_dma;
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
+ volatile uint status = dma->sr;
/* While the channel is busy, spin */
while ((status & 4) == 4) {
- status = dma->sr0;
+ status = dma->sr;
}
if (status != 0) {
@@ -212,14 +214,15 @@ int
dma_xfer(void *dest, uint count, void *src)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma_base = &immap->im_dma;
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->dar0 = (uint) dest;
- dma->sar0 = (uint) src;
- dma->bcr0 = count;
- dma->mr0 = 0xf04;
+ dma->dar = (uint) dest;
+ dma->sar = (uint) src;
+ dma->bcr = count;
+ dma->mr = 0xf04;
asm("sync;isync");
- dma->mr0 = 0xf05;
+ dma->mr = 0xf05;
asm("sync;isync");
return dma_check();
}
diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h
new file mode 100644
index 000..aab8720
--- /dev/null
+++ b/include/asm-ppc/fsl_dma.h
@@ -0,0 +1,51 @@
+/*
+ * Freescale DMA Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+
[U-Boot] [PATCH 00/11] 85xx/86xx dma updates
This patch series attempts to clean up the DMA implementation for the 85xx and 86xx architectures. The changes include: - consolidate 85xx and 86xx structures and code - add defines for bitfields - use proper IO accessors - add support for arbitrarily large transfer sizes - rename dma_xfer() to dmacpy() and make dmacpy's prototype similar to memcpy() The patches are based on the mainline "next" branch. I've tested the code on MPC8572 and MPC8640-based boards. I'm not initimately familar with the 83xx platform, but at a glance it looked like the fsl_dma driver could be extended to support it with some ifdeffery. Peter Tyser (11): fsl: Create common fsl_dma.h for 85xx and 86xx cpus 85xx, 86xx: Sync up DMA code 85xx, 86xx: Break out DMA code to a common file fsl_dma: Add bitfield definitions for common registers fsl_dma: Update to use proper I/O accessor functions fsl_dma: Add support for arbitrarily large transfers fsl_dma: Fix Channel Start bug in dma_check() 8xxx: Rename dma_xfer() dmacpy() fsl_dma: Move dma function prototypes to common header file 85xx, 86xx: Move dma_init() call to common code fsl_dma: Break out common memory initialization function board/mpc8540eval/mpc8540eval.c | 35 +- board/sbc8560/sbc8560.c | 33 +- cpu/mpc83xx/cpu.c |4 +- cpu/mpc83xx/spd_sdram.c | 24 +++--- cpu/mpc85xx/cpu.c | 44 cpu/mpc85xx/cpu_init.c |4 +- cpu/mpc85xx/ddr-gen1.c | 33 +- cpu/mpc86xx/cpu.c | 50 - cpu/mpc86xx/cpu_init.c |3 + drivers/dma/Makefile|1 + drivers/dma/fsl_dma.c | 146 +++ include/asm-ppc/fsl_dma.h | 105 include/asm-ppc/immap_85xx.h| 76 +--- include/asm-ppc/immap_86xx.h| 78 ++--- include/configs/PM854.h |1 + include/configs/PM856.h |1 + 16 files changed, 286 insertions(+), 352 deletions(-) create mode 100644 drivers/dma/fsl_dma.c create mode 100644 include/asm-ppc/fsl_dma.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/11] fsl_dma: Add bitfield definitions for common registers
Signed-off-by: Peter Tyser
---
drivers/dma/fsl_dma.c | 12 +-
include/asm-ppc/fsl_dma.h | 46 +
2 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index a9989ee..baf2942 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -51,11 +51,11 @@ static uint dma_check(void) {
volatile uint status = dma->sr;
/* While the channel is busy, spin */
- while (status & 4)
+ while (status & FSL_DMA_SR_CB)
status = dma->sr;
/* clear MR[CS] channel start bit */
- dma->mr &= 1;
+ dma->mr &= FSL_DMA_MR_CS;
dma_sync();
if (status != 0)
@@ -67,8 +67,8 @@ static uint dma_check(void) {
void dma_init(void) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->satr = 0x0004;
- dma->datr = 0x0004;
+ dma->satr = FSL_DMA_SATR_SREAD_NO_SNOOP;
+ dma->datr = FSL_DMA_DATR_DWRITE_NO_SNOOP;
dma->sr = 0x; /* clear any errors */
dma_sync();
}
@@ -81,11 +81,11 @@ int dma_xfer(void *dest, uint count, void *src) {
dma->bcr = count;
/* Disable bandwidth control, use direct transfer mode */
- dma->mr = 0xf04;
+ dma->mr = FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT;
dma_sync();
/* Start the transfer */
- dma->mr = 0xf05;
+ dma->mr = FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_CS;
dma_sync();
return dma_check();
diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h
index aab8720..c9ec6b5 100644
--- a/include/asm-ppc/fsl_dma.h
+++ b/include/asm-ppc/fsl_dma.h
@@ -29,12 +29,58 @@
typedef struct fsl_dma {
uintmr; /* DMA mode register */
+#define FSL_DMA_MR_CS 0x0001 /* Channel start */
+#define FSL_DMA_MR_CC 0x0002 /* Channel continue */
+#define FSL_DMA_MR_CTM 0x0004 /* Channel xfer mode */
+#define FSL_DMA_MR_CTM_DIRECT 0x0004 /* Direct channel xfer mode */
+#define FSL_DMA_MR_CA 0x0008 /* Channel abort */
+#define FSL_DMA_MR_CDSM0x0010
+#define FSL_DMA_MR_XFE 0x0020 /* Extended features en */
+#define FSL_DMA_MR_EIE 0x0040 /* Error interrupt en */
+#define FSL_DMA_MR_EOLSIE 0x0080 /* End-of-lists interrupt en */
+#define FSL_DMA_MR_EOLNIE 0x0100 /* End-of-links interrupt en */
+#define FSL_DMA_MR_EOSIE 0x0200 /* End-of-seg interrupt en */
+#define FSL_DMA_MR_SRW 0x0400 /* Single register write */
+#define FSL_DMA_MR_SAHE0x1000 /* Source addr hold
enable */
+#define FSL_DMA_MR_DAHE0x2000 /* Dest addr hold
enable */
+#define FSL_DMA_MR_SAHTS_MASK 0xc000 /* Source addr hold xfer size */
+#define FSL_DMA_MR_DAHTS_MASK 0x0003 /* Dest addr hold xfer size */
+#define FSL_DMA_MR_EMS_EN 0x0004 /* Ext master start en */
+#define FSL_DMA_MR_EMP_EN 0x0020 /* Ext master pause en */
+#define FSL_DMA_MR_BWC_MASK0x0f00 /* Bandwidth/pause ctl */
+#define FSL_DMA_MR_BWC_DIS 0x0f00 /* Bandwidth/pause ctl disable
*/
uintsr; /* DMA status register */
+#define FSL_DMA_SR_EOLSI 0x0001 /* End-of-list interrupt */
+#define FSL_DMA_SR_EOSI0x0002 /* End-of-segment
interrupt */
+#define FSL_DMA_SR_CB 0x0004 /* Channel busy */
+#define FSL_DMA_SR_EOLNI 0x0008 /* End-of-links interrupt */
+#define FSL_DMA_SR_PE 0x0010 /* Programming error */
+#define FSL_DMA_SR_CH 0x0020 /* Channel halted */
+#define FSL_DMA_SR_TE 0x0080 /* Transfer error */
charres0[4];
uintclndar; /* DMA current link descriptor address register
*/
uintsatr; /* DMA source attributes register */
+#define FSL_DMA_SATR_ESAD_MASK 0x01ff /* Extended source addr
*/
+#define FSL_DMA_SATR_SREAD_NO_SNOOP0x0004 /* Read, don't snoop */
+#define FSL_DMA_SATR_SREAD_SNOOP 0x0005 /* Read, snoop */
+#define FSL_DMA_SATR_SREAD_UNLOCK 0x0007 /* Read, unlock l2 */
+#define FSL_DMA_SATR_STRAN_MASK0x00f0 /* Source
interface */
+#define FSL_DMA_SATR_SSME 0x0100 /* Source stride en */
+#define FSL_DMA_SATR_SPCIORDER 0x0200 /* PCI transaction
order */
+#define FSL_DMA_SATR_STFLOWLVL_MASK0x0c00 /* RIO flow level */
+#define FSL_DMA_SATR_SBPATRMU 0x2000 /* Bypass ATMU */
uintsar;/* DMA source address register */
uintdatr; /* DMA destination attributes register */
+#define FSL_DMA_DATR_EDAD_MASK
Re: [U-Boot] bootstrap nand write function
On Thu, May 21, 2009 at 01:56:37PM +0530, Deepak Gopalakrishnan wrote: > Hi > i want to write a function using which i will be able to add a new env > variable from the bootstrap. > cud you help me with the sequence i should follow when im writing this > function... > thanks and regards, > Deepak Gopalakrishnan If by "bootstrap" you mean a 4K or so bit of code that loads the main u-boot into RAM, then there's probably not enough room to do that (at least not without hacking something together that is very special-purpose and doesn't use much of the existing environment or NAND infrastructure). -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Support in u-boot for PCI-Express NIC
> -Original Message- > From: u-boot-boun...@lists.denx.de > [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Wolfgang Denk > Sent: Wednesday, May 20, 2009 2:01 PM > To: Srinivasan Srikanth-R9AABP > Cc: u-boot@lists.denx.de > Subject: Re: [U-Boot] Support in u-boot for PCI-Express NIC [SNIP] > At least the e1000 has been successfully tested not so long ago. > Thanks Wolfgang. That's good news. Can you pl point me to the pci-express card/device id that was tested recently (and/or the mails that talk about it)? ~Sri > Best regards, > > Wolfgang Denk > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Marvell Sheevaplug Board support
References: http://plugcomputer.org/ Serial console Setup http://openplug.org/plugwiki/index.php/Serial_terminal_program#Linux OpenOCD Setup http://openplug.org/plugwiki/index.php/Setting_Up_OpenOCD_Under_Linux This patch is tested for- 1. Boot from DRAM/NAND flash 2. File transfer using tftp 3. NAND flash read/write/erase Signed-off-by: Prafulla Wadaskar --- MAKEALL |1 + Makefile |8 +- board/Marvell/sheevaplug/Makefile | 52 + board/Marvell/sheevaplug/config.mk| 25 + board/Marvell/sheevaplug/nand.c | 80 ++ board/Marvell/sheevaplug/sheevaplug.c | 135 +++ board/Marvell/sheevaplug/sheevaplug.h | 37 +++ include/configs/sheevaplug.h | 191 + 8 files changed, 526 insertions(+), 3 deletions(-) create mode 100644 board/Marvell/sheevaplug/Makefile create mode 100644 board/Marvell/sheevaplug/config.mk create mode 100644 board/Marvell/sheevaplug/nand.c create mode 100644 board/Marvell/sheevaplug/sheevaplug.c create mode 100644 board/Marvell/sheevaplug/sheevaplug.h create mode 100644 include/configs/sheevaplug.h diff --git a/MAKEALL b/MAKEALL index 6719d7b..e3d33cb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -144,6 +144,7 @@ LIST_8xx=" \ RPXlite \ RPXlite_DW \ RRvision\ + sheevaplug \ SM850 \ spc1920 \ SPD823TS\ diff --git a/Makefile b/Makefile index 8144ecd..34a863b 100644 --- a/Makefile +++ b/Makefile @@ -1122,6 +1122,9 @@ RRvision_LCD_config: unconfig @echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h @$(MKCONFIG) -a RRvision ppc mpc8xx RRvision +sheevaplug_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood + SM850_config : unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc @@ -2808,9 +2811,6 @@ lpd7a400_config \ lpd7a404_config: unconfig @$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x -mv88f6281gtw_ge_config: unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood - mx1ads_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t mx1ads NULL imx @@ -3110,6 +3110,8 @@ omap2420h4_config : unconfig qong_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 qong davedenx mx31 +sheevapluge_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood # ## ARM1176 Systems diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile new file mode 100644 index 000..6520776 --- /dev/null +++ b/board/Marvell/sheevaplug/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := sheevaplug.o +COBJS += nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/Marvell/sheevaplug/config.mk b/board/Marvell/sheevaplug/config.mk new file mode 100644 index 000..fb29a1b --- /dev/null +++ b/board/Marvell/sheevaplug/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; eith
[U-Boot] [PATCH] Marvell MV88E1116 PHY Driver support
Suports Basic PHY init (i.e. PHY reset)
optional supported configurations:
led_init, mdipn_reverse, rgmii_delay config
This driver is tested with sheevaplug board
Signed-off-by: Prafulla Wadaskar
---
drivers/net/phy/Makefile|1 +
drivers/net/phy/mv88e1116.c | 90 +++
drivers/net/phy/mv88e1116.h | 38 ++
include/netdev.h| 31 +++
4 files changed, 160 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/phy/mv88e1116.c
create mode 100644 drivers/net/phy/mv88e1116.h
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 3b92614..ed624b4 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libphy.a
COBJS-$(CONFIG_BITBANGMII) += miiphybb.o
+COBJS-$(CONFIG_MV88E1116_PHY) += mv88e1116.o
COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o
COBJS := $(COBJS-y)
diff --git a/drivers/net/phy/mv88e1116.c b/drivers/net/phy/mv88e1116.c
new file mode 100644
index 000..bd210f6
--- /dev/null
+++ b/drivers/net/phy/mv88e1116.c
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ * Prafulla Wadaskar
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include "mv88e1116.h"
+
+/*
+ * Marvell 88E61XX PHY initialization
+ */
+int mv88e1116_phy_initialize(struct mv88e1116_config *phycfg)
+{
+ char *name = phycfg->name;
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name)) {
+ printf("%s failed\n", __FUNCTION__);
+ return -1;
+ }
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Error..could not read PHY dev address\n");
+ return -1;
+ }
+
+ /*
+* Leds link and activity
+* LED[0] On-Link, Blink-Activity, Off-NoLink
+*/
+ if (phycfg->led_init == MV88E1116_LED_INIT_EN) {
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0x3);
+ miiphy_read(name, devadr, MV88E1116_LED_FCTRL_REG, ®);
+ reg &= ~0xf;
+ reg |= 0x1;
+ miiphy_write(name, devadr, MV88E1116_LED_FCTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+ }
+
+ /*
+* Enable RGMII delay on Tx and Rx for CPU port
+* Ref: sec 4.7.2 of chip datasheet
+*/
+ if (phycfg->rgmii_delay == MV88E1116_RGMII_DELAY_EN) {
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, 21, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, 21, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+ }
+
+ /*
+* Reverse Transmit polarity for Media Dependent Interface
+* Pins (MDIP) bits in Copper Specific Control Register 3
+* Reference: table 53 chip datasheet
+*/
+ if (phycfg->mdip == MV88E1116_MDIP_REVERSE) {
+ miiphy_read(name, devadr, MV88E1116_CPRSP_CR3_REG, ®);
+ reg |= 0xf;
+ miiphy_write(name, devadr, MV88E1116_CPRSP_CR3_REG, reg);
+ }
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+ return 0;
+}
diff --git a/drivers/net/phy/mv88e1116.h b/drivers/net/phy/mv88e1116.h
new file mode 100644
index 000..b12be22
--- /dev/null
+++ b/drivers/net/phy/mv88e1116.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ * Prafulla Wadaskar
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERC
Re: [U-Boot] [PATCH] 85xx: Always attempt ethernet device tree fixup
On Thu, May 21, 2009 at 8:36 AM, Kumar Gala wrote: > Its reasonable that we may have ethernet devices but dont have drivers > or support enabled for them in u-boot and want the device tree fixed up. > Unconditionally calling the ethernet fixup is fine since if we dont have > ethernet nodes that match (or aliases) we will not attempt to do > anything. > > Signed-off-by: Kumar Gala Acked-by: Timur Tabi -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please help for Data TLB Error in MPC8544
Hi all, My board can't boot normally, and I found it just hang in data tlb error through the system.map. Could any one help for this? Some regisers are as below: DEAR: 0xf400fff0 (L1 init ram base address is 0xf401) IVPR : 0xfff8 , IVPR3: 0x04000 EELADR: 0xf401 , CSn_BNDS: all 0x (I think SPD of DDR is not found yet) L2MMU_TLB0 : 8400 5100 ff700 ff700 (CCSR is not relocated to 0xe000 yet) The TLB1 registers from CodeWarrior is as below: = L2MMU_CAM0 67CA 1C08 FFC0 FFC01 (boot flash, 4M) L2MMU_CAM1 A0007FCA 1C08 8000 80001 (PCIE, 1G) L2MMU_CAM2 90003FCA 1C08 C000 C0001 (PCI, 256M) L2MMU_CAM3 90003FCA 1C08 D000 D0001 (PCI, 256M) L2MMU_CAM4 80001FCA 1C08 E000 E0001 (CCSR, 64M) L2MMU_CAM5 80001FCA 1C08 F000 F0001 (?? , 64M) L2MMU_CAM6 30CA 1808 FF04 FF041 (NAND, 64K) L2MMU_CAM7 2042 1808 FF01 FF011 (NAND, 16K) L2MMU_CAM8 2042 1808 FF05 FF051 (NAND, 16K) L2MMU_CAM9 C87FD651 EB4D 27DE6000 2397E000 L2MMU_CAM10 D0E2E2DF EB680009 B494F000 8F634000 L2MMU_CAM11 00FC8DCA 5A11000D BCB9B000 77EF6000 L2MMU_CAM12 30CA 1808 FF00 FF01 (NAND, 64K) L2MMU_CAM13 D891AFD8 18180002 50A7 F7AB6000 L2MMU_CAM14 E0F6AE97 DA390009 F5DF6000 4F425000 L2MMU_CAM15 D8EFEF88 C75F AEBA7000 3229F000 === And this is my init.s below: == #include #include #include #include #include #include #define LAWAR_TRGT_PCI1 0x #define LAWAR_TRGT_PCIE1 0x0020 #define LAWAR_TRGT_PCIE2 0x0010 #define LAWAR_TRGT_PCIE3 0x0030 #define LAWAR_TRGT_LBC 0x0040 #define LAWAR_TRGT_DDR 0x00f0 #define entry_start \ mflrr1 ; \ bl 0f ; #define entry_end \ 0: mflrr0 ; \ mtlrr1 ; \ blr ; .section.bootpg, "ax" .globl tlb1_entry tlb1_entry: entry_start /* * Number of TLB0 and TLB1 entries in the following table */ .long (2f-1f)/16 1: /* * TLB0 4K Non-cacheable, guarded * 0xff70 4K Initial CCSRBAR mapping * * This ends up at a TLB0 Index==0 entry, and must not collide * with other TLB0 Entries. */ .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) /* * TLB0 16K Cacheable, guarded * Temporary Global data for initialization * * Use four 4K TLB0 entries. These entries must be cacheable * as they provide the bootstrap memory before the memory * controler and real memory have been configured. * * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, * and must not collide with other TLB0 entries. */ .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),0,0,0,0,0,1,0,1,0,1) /* * TLB 0: 4M Non-cacheable, guarded * 0xffc0 4M Covers FLASH at 0xFFC0 * Out of reset this entry is only 4K. */ .long TLB1_MAS0(1, 0, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M) .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1) /* * TLB 1: 1G Non-cacheable, guarded * 0x8000 1G PCIE 8,9,a,b */ .long TLB1_MAS0(1, 1, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) .long
Re: [U-Boot] [PATCH 3/6] mpc83xx: USB: Reorganized its support
On May 21, 2009, at 7:02 AM, Vivek Mahajan wrote:
> The following patch reorganizes/reworks the USB support for mpc83xx
> as under:-
>
> * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to
>cpu/mpx83xx/cpu_init.c
>
> * Board specific usb_phy_type is read from the environment
>
> * Adds USB EHCI specific structure in include/usb/ehci-fsl.h
>
> * Copyrights revamped in most of the following files
>
> Signed-off-by: Vivek Mahajan
> ---
> common/env_common.c |3 ++
> common/env_embedded.c|3 ++
> cpu/mpc83xx/cpu_init.c | 19 -
> drivers/usb/host/ehci-fsl.c | 53 +++
> +---
> include/asm-ppc/immap_83xx.h |5 ++-
> include/usb/ehci-fsl.h | 63 +
> -
> 6 files changed, 108 insertions(+), 38 deletions(-)
>
> diff --git a/common/env_common.c b/common/env_common.c
> index 6be3bb0..e3811ca 100644
> --- a/common/env_common.c
> +++ b/common/env_common.c
> @@ -133,6 +133,9 @@ uchar default_environment[] = {
> #if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
> "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY)"\0"
> #endif
> +#if defined(CONFIG_USB_PHY_TYPE)
> + "usb_phy_type=" MK_STR(CONFIG_USB_PHY_TYPE) "\0"
> +#endif
> #ifdef CONFIG_EXTRA_ENV_SETTINGS
> CONFIG_EXTRA_ENV_SETTINGS
> #endif
> diff --git a/common/env_embedded.c b/common/env_embedded.c
> index ae6cac4..af5b9f5 100644
> --- a/common/env_embedded.c
> +++ b/common/env_embedded.c
> @@ -180,6 +180,9 @@ env_t environment __PPCENV__ = {
> #if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
> "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY)"\0"
> #endif
> +#if defined(CONFIG_USB_PHY_TYPE)
> + "usb_phy_type=" MK_STR(CONFIG_USB_PHY_TYPE) "\0"
> +#endif
> #ifdef CONFIG_EXTRA_ENV_SETTINGS
> CONFIG_EXTRA_ENV_SETTINGS
> #endif
I'm guessing Wolfgang isn't going to like this and suggest we just do
this via board specific setting of CONFIG_EXTRA_ENV_SETTINGS
- k
___
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[U-Boot] [PATCH] 85xx: Always attempt ethernet device tree fixup
Its reasonable that we may have ethernet devices but dont have drivers or support enabled for them in u-boot and want the device tree fixed up. Unconditionally calling the ethernet fixup is fine since if we dont have ethernet nodes that match (or aliases) we will not attempt to do anything. Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c |3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 26a8f48..a692529 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -278,12 +278,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) if (!IS_E_PROCESSOR(get_svr())) fdt_fixup_crypto_node(blob, 0); -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ -defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob); fdt_add_enet_stashing(blob); -#endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 8, 1); -- 1.6.0.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Uboot bitmap utility
Wolfgang, I resolved my issue. I am now able to write bitmaps to the framebuffer. Thanks, Steve - Steven Zedeck wrote: > > Wolfgang, > Yes, I do see what U-boot is doing. I looked at bmp_logo.c and its output. > It seems that the color palette entries are all 16 bits (unsigned short). > For my application, I have 24 bit color, which expects each pixel to be 32 > bits, of which only 24 bits are used. So the palette, I assume, should be > unsigned longs for each color entry. Correct or am I missing something? > > Did I interpret the code correctly? Does it expect 16 bits per color? > Thanks, > Steve > - > > wd wrote: >> >> Dear Steven Zedeck, >> >> In message <23217700.p...@talk.nabble.com> you wrote: >>> >>> I'm referring to the palatte and bitmap structs. >>> thanks again, >> >> Are you talking about the logo support? Noite that this is different >> from plain bitmap support. >> >>> > It seems that UBoot needs two data structures to display a bitmap in >>> the >>> > framebuffer. Is there a utility that converts a Windows bitmap (BMP?) >>> file >>> > and creates the 2 data structures that I can embedd in my code? >> >> Did you have a look at what U-Boot is doing? For example, how it uses >> the tools in the (he!) tools/ directory, for example tools/bmp_logo ? >> >> Best regards, >> >> Wolfgang Denk >> >> -- >> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel >> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de >> HR Manager to job candidate "I see you've had no computer training. >> Although that qualifies you for upper management, it means you're >> under-qualified for our entry level positions." >> ___ >> U-Boot mailing list >> U-Boot@lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot >> >> > > -- View this message in context: http://www.nabble.com/Uboot-bitmap-utility-tp23217619p23652400.html Sent from the Uboot - Users mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/6] mpc85xx: 8536ds: Add USB related CONFIGs
This patch adds CONFIGs for enabling USB in mpc8536ds and also updates its Copyright. Signed-off-by: Vivek Mahajan --- include/configs/MPC8536DS.h | 12 +++- 1 files changed, 11 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index bbb448d..ef163b5 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -463,6 +463,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_EXT2 #endif +/* + * USB + */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_PHY_TYPE"ulpi" +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -- 1.5.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/6] mpc83xx: 8315erdb: Add USB related CONFIGs
This patch adds CONFIGs for enabling USB in mpc8315erdb and also revamps its Copyright. Signed-off-by: Vivek Mahajan --- include/configs/MPC8315ERDB.h | 10 +- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 9fa91f4..2a59d61 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. * * Dave Liu * @@ -345,6 +345,14 @@ #endif #define CONFIG_HAS_FSL_DR_USB +#define CONFIG_SYS_SCCR_USBDRCM3 + +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_PHY_TYPE"utmi" +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* * TSEC -- 1.5.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/6] mpc85xx: USB: Add support
The following patch adds 85xx-specific USB support and also
revamps Copyright in immap_85xx.h
Signed-off-by: Vivek Mahajan
---
include/asm-ppc/immap_85xx.h |5 -
include/usb/ehci-fsl.h |2 ++
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index d3c6b86..bbdf374 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1,7 +1,7 @@
/*
* MPC85xx Internal Memory Map
*
- * Copyright 2007 Freescale Semiconductor.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.x...@motorola.com)
@@ -1732,5 +1732,8 @@ typedef struct ccsr_gur {
#define CONFIG_SYS_MPC85xx_SERDES1_ADDR(CONFIG_SYS_IMMR +
CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100)
#define CONFIG_SYS_MPC85xx_SERDES2_ADDR(CONFIG_SYS_IMMR +
CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
+#define CONFIG_SYS_MPC85xx_USB_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
#endif /*__IMMAP_85xx__*/
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 7ae948c..1140561 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -87,6 +87,8 @@
#if defined(CONFIG_MPC83XX)
#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
+#elif defined(CONFIG_MPC85xx)
+#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
#endif
/*
--
1.5.6.5
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[U-Boot] [PATCH 3/6] mpc83xx: USB: Reorganized its support
The following patch reorganizes/reworks the USB support for mpc83xx
as under:-
* Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to
cpu/mpx83xx/cpu_init.c
* Board specific usb_phy_type is read from the environment
* Adds USB EHCI specific structure in include/usb/ehci-fsl.h
* Copyrights revamped in most of the following files
Signed-off-by: Vivek Mahajan
---
common/env_common.c |3 ++
common/env_embedded.c|3 ++
cpu/mpc83xx/cpu_init.c | 19 -
drivers/usb/host/ehci-fsl.c | 53 ---
include/asm-ppc/immap_83xx.h |5 ++-
include/usb/ehci-fsl.h | 63 +-
6 files changed, 108 insertions(+), 38 deletions(-)
diff --git a/common/env_common.c b/common/env_common.c
index 6be3bb0..e3811ca 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -133,6 +133,9 @@ uchar default_environment[] = {
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY)"\0"
#endif
+#if defined(CONFIG_USB_PHY_TYPE)
+ "usb_phy_type=" MK_STR(CONFIG_USB_PHY_TYPE) "\0"
+#endif
#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
diff --git a/common/env_embedded.c b/common/env_embedded.c
index ae6cac4..af5b9f5 100644
--- a/common/env_embedded.c
+++ b/common/env_embedded.c
@@ -180,6 +180,9 @@ env_t environment __PPCENV__ = {
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY)"\0"
#endif
+#if defined(CONFIG_USB_PHY_TYPE)
+ "usb_phy_type=" MK_STR(CONFIG_USB_PHY_TYPE) "\0"
+#endif
#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 8e9c875..7224c27 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,6 +23,10 @@
#include
#include
#include
+#ifdef CONFIG_USB_EHCI_FSL
+#include
+#include
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -294,6 +298,19 @@ void cpu_init_f (volatile immap_t * im)
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
+#ifdef CONFIG_USB_EHCI_FSL
+ uint32_t temp;
+ struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+
+ /* Configure interface. */
+ setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
+
+ /* Wait for clock to stabilize */
+ do {
+ temp = in_be32((void *)ehci->control);
+ udelay(1000);
+ } while (!(temp & PHY_CLK_VALID));
+#endif
}
int cpu_init_r (void)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 9d7d4fc..bf148c4 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -1,4 +1,6 @@
/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
*
* Author: Tor Krill t...@excito.com
@@ -22,12 +24,10 @@
#include
#include
#include
-#include
#include
-#include
+#include
#include "ehci.h"
-#include
#include "ehci-core.h"
/*
@@ -38,50 +38,33 @@
*/
int ehci_hcd_init(void)
{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- uint32_t addr, temp;
+ struct usb_ehci *ehci;
- addr = (uint32_t)&(im->usb[0]);
- hccr = (struct ehci_hccr *)(addr + FSL_SKIP_PCI);
+ ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+ hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- /* Configure clock */
- clrsetbits_be32(&(im->clk.sccr), MPC83XX_SCCR_USB_MASK,
- MPC83XX_SCCR_USB_DRCM_11);
-
- /* Confgure interface. */
- temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
- out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp
-| REFSEL_16MHZ | UTMI_PHY_EN);
-
- /* Wait for clock to stabilize */
- do {
- temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
- udelay(1000);
- } while (!(temp & PHY_CLK_VALID));
-
/* Set to Host mode */
- temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE));
- out_le32((void *)(addr + FSL_SOC_USB_USBMODE), temp | CM_HOST);
+ setbits_le32((void *)ehci->usbmode, CM_HOST);
- out_be32((void *)(addr + FSL_SOC_USB_SNOOP1), SNOOP_SIZE_2GB);
- out_be32((void *)(addr + FSL_SOC_USB_SNOOP2),
-0x8000 | SNOOP_SIZE_2GB);
+ out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB);
+ out_be32((void *)ehci->snoop2, 0x8000 | S
[U-Boot] [PATCH 2/6] mpc8xxx: USB: Relocates ehci-fsl.h to include/usb
The following patch moves 8xxx-specifc USB #defines from
drivers/usb/host/ehci-fsl.h to include/usb.
Signed-off-by: Vivek Mahajan
---
drivers/usb/host/ehci-fsl.c |2 +-
{drivers/usb/host => include/usb}/ehci-fsl.h |0
2 files changed, 1 insertions(+), 1 deletions(-)
rename {drivers/usb/host => include/usb}/ehci-fsl.h (100%)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index cff6024..9d7d4fc 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,7 +27,7 @@
#include
#include "ehci.h"
-#include "ehci-fsl.h"
+#include
#include "ehci-core.h"
/*
diff --git a/drivers/usb/host/ehci-fsl.h b/include/usb/ehci-fsl.h
similarity index 100%
rename from drivers/usb/host/ehci-fsl.h
rename to include/usb/ehci-fsl.h
--
1.5.6.5
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[U-Boot] [PATCH 1/6] mpc8xxx: USB: Removed reenablement of its interface
To prepare for the 85xx USB support, which requires interface enablement only once in (specified) order, no different than instructions for enabling the interface under 83xx. It is unknown why the original author enabled the interface twice (checked for references in errata, etc). Signed-off-by: Vivek Mahajan --- drivers/usb/host/ehci-fsl.c |4 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 86ee1d5..cff6024 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -81,10 +81,6 @@ int ehci_hcd_init(void) out_be32((void *)(addr + FSL_SOC_USB_AGECNTTHRSH), 0x0040); out_be32((void *)(addr + FSL_SOC_USB_SICTRL), 0x0001); - /* Enable interface. */ - temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); - out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN); - temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE)); return 0; -- 1.5.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] my u-boot freezing at Uncompress Linux...
>I doubt that. Actually your Linux kernel freezes - U-Boots last message >is the "Starting kernel .." message. It's all Linux from there. >So start troubleshooting your kernel. Searching the archieve for this >mailing list will probably be a good start point. thanks for your reply , Detlev : ) i rebuild a new kernel-2.6.24 and my console freezes at "Starting kernel..." and i will search this issue in forum . but i still confuse in my case , it mean my u-boot setting is "correct" and my kernel cause this issue ?? -- View this message in context: http://www.nabble.com/-U-boot-my-u-boot-freezing-at-Uncompress-Linux...-tp23610073p23650633.html Sent from the Uboot - Users mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] uBoot Debug: GPIO Toggling does not working over 8536DSuboot
> CPU: MPC8536DS [Core E500, Freescale] > Flash: 16MB [50MHz Local bus Clk) > DDR: 1G (SODIMM, 400 MHz) > Baord: Network Evaluation Cutom MPC8536E Board > > U-Boot Debug Issue (GPIO Toggling code help) > _ > > -> as i am not able to debug uboot over jtag and the CW tool > till now, [MPC8536 CPU Suoort to the CW is not available now > it will be released in future.] > > so i have to debug it via the printf statments meanwhile > after the UART initialization get over. > But till when the UART initialization is not done so ihave to > check the Uboot process via the GPIO Togging. ;) > > So when i wrote u-boot.bin file to the Flash via Jtag CW > FlashProgrammer tool, and power on the SW of te board it does > not bootup and the GPIO toggling is not over yet what i have to do .. > is my code to toggle the GPIO is wrong or i am mistaking > anything. (This code i am testing over MPC8536DS Calamari > baord, not working there too) > > /cpu/mpc85xx/statrt.S > > . > > .section .bootpg,"ax" > .globl _start_e500 > > _start_e500: > > /* 20090520 DEBUG LED Code start */ > lis r2,adr_cfg_g...@h > ori r2,r2,adr_cfg_g...@l > > lis r3,dir_g...@h > ori r3,r3,dir_g...@l > > stw r3,0(r2) > isync > msync > > lis r2,adr_g...@h > ori r2,r2,adr_g...@l > > lis r3,dat_g...@h > ori r3,r3,dat_g...@l > isync > msync No TLB set up for the GPIO address(FF70,) So you need have one TLB for CCSR space. > and i declared the used macro in the file > ./include/configs/MPC8536DS.h > > ... > > > #define ADR_CFG_GPIO 0xFF70FC00 /* GPIO > LED Configuration Register address */ > #define ADR_GPIO 0xFF70FC08 /* GPIO > LED Data Register */ > #define DIR_GPIO 0x /* GPIO > DIRECTION though it is GPIO [0-15] */ > #define DAT_GPIO 0xF28FF28F /* GPIO > Data GPIO[6-8] will set as toggle alternate */ > > . > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] bootstrap nand write function
Hi i want to write a function using which i will be able to add a new env variable from the bootstrap. cud you help me with the sequence i should follow when im writing this function... thanks and regards, Deepak Gopalakrishnan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] uBoot Debug: GPIO Toggling does not working over 8536DS uboot
Project details: CPU: MPC8536DS [Core E500, Freescale] Flash: 16MB [50MHz Local bus Clk) DDR: 1G (SODIMM, 400 MHz) Baord: Network Evaluation Cutom MPC8536E Board U-Boot Debug Issue (GPIO Toggling code help) _ -> as i am not able to debug uboot over jtag and the CW tool till now, [MPC8536 CPU Suoort to the CW is not available now it will be released in future.] so i have to debug it via the printf statments meanwhile after the UART initialization get over. But till when the UART initialization is not done so ihave to check the Uboot process via the GPIO Togging. ;) So when i wrote u-boot.bin file to the Flash via Jtag CW FlashProgrammer tool, and power on the SW of te board it does not bootup and the GPIO toggling is not over yet what i have to do .. is my code to toggle the GPIO is wrong or i am mistaking anything. (This code i am testing over MPC8536DS Calamari baord, not working there too) /cpu/mpc85xx/statrt.S . .section .bootpg,"ax" .globl _start_e500 _start_e500: /* 20090520 DEBUG LED Code start */ lis r2,adr_cfg_g...@h ori r2,r2,adr_cfg_g...@l lis r3,dir_g...@h ori r3,r3,dir_g...@l stw r3,0(r2) isync msync lis r2,adr_g...@h ori r2,r2,adr_g...@l lis r3,dat_g...@h ori r3,r3,dat_g...@l isync msync _T_LED: /* xori r1,r1,0x */ stw r3,0(r2) isync msync b_T_LED /* TED 20090520 DEBUG LED Code End */ /* clear registers/arrays not reset by hardware */ /* L1 */ li r0,2 mtspr L1CSR0,r0 /* invalidate d-cache */ mtspr L1CSR1,r0 /* invalidate i-cache */ mfspr r1,DBSR mtspr DBSR,r1 /* Clear all valid bits */ . and i declared the used macro in the file ./include/configs/MPC8536DS.h ... #define ADR_CFG_GPIO0xFF70FC00 /* GPIO LED Configuration Register address */ #define ADR_GPIO0xFF70FC08 /* GPIO LED Data Register */ #define DIR_GPIO0x /* GPIO DIRECTION though it is GPIO [0-15] */ #define DAT_GPIO0xF28FF28F /* GPIO Data GPIO[6-8] will set as toggle alternate */ . i tried setting as too #define DIR_GPIO0x0380 /* Only GPIO[6:8] */ #define DAT_GPIO0x0280 But not workied for me :( isync msync too not worked i put this after I cache D Cache disable too please suggest me how to debug the GPIO toggling code and the process of debugging uboot. -> also suggest me any Application note or manual over the PPC Assembly coding manual. * In case we cannot put this code here so what is the method to check the Uboot activity following like till where uboot does well or it hangs arround and after this and that kind of stuff? and from when we can do toggling the GPIO's waiting for the reply this time more eagerly ..W.w.W.. --- Ashish Agarwal ★━・:*:*:・ ゜・:*:*:・★☆★ アガルワル アシッシュ ★☆★・:*:*:・ ゜・:*:*:・━★ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Which U-Boot releases have Device Tree support
Dear JEW-DONG, In message <23644965.p...@talk.nabble.com> you wrote: > > > Thanks for the information. This is the first time I am searching for the > u-boot source code for MPC8360E-RDK. Three more questions here: ... > Secondly, how do I use GIT to download the source code? ... > Lastly, how do I tell make to build the u-boot for MPC8360E-RDK board? I do not intend to answer questions that are well-documented on ythe U-Boot web site and in the manual. Please read the documentation. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Work 8 hours, sleep 8 hours; but not the same 8 hours. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
