Re: [U-Boot] [PATCH] microblaze: avoid interrupt race conditions

2012-02-22 Thread Michal Simek 

Stephan Linz wrote:

The interrupt acknowledge action have to run after the
registered interrupt handler. So we have a chance to
bear out the corresponding interrupt request in the
corresponding controller hardware.

With this reorderng, we optain a proper interrupt


obtain



handling for level triggerd interrupt sources -- for


triggered


example the new axi_timer v1.02.a introduced in ISE 13.2

Signed-off-by: Stephan Linz l...@li-pro.net
---
 arch/microblaze/cpu/interrupts.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index 5a13211..e7ca859 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -155,8 +155,6 @@ void interrupt_handler (void)
 #endif
struct irq_action *act = vecs + irqs;
 
-	intc-iar = mask  irqs;

-
 #ifdef DEBUG_INT
printf
(Jumping to interrupt handler rutine addr %x,count %x,arg %x\n,
@@ -165,6 +163,8 @@ void interrupt_handler (void)
act-handler (act-arg);
act-count++;
 
+	intc-iar = mask  irqs;

+
 #ifdef DEBUG_INT
printf (Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n, intc-isr,
intc-ier, intc-iar, intc-mer);


Agree. This is good patch.

Please fix that commit message and add my
Acked-by: Michal Simek mon...@monstr.eu

Thanks,
Michal



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Re: [U-Boot] [PATCH] imximage: header v2: Remove overwriting of flash_offset

2012-02-22 Thread Dirk Behme 

On 21.02.2012 22:49, stefano babic wrote:

Am 21/02/2012 20:18, schrieb Dirk Behme:


I think we have then a problem when there is not a BOOT_FROM statement
in the configuration file, that let  imxhdr-flash_offset unset.

We need to set it with the default value
Hmm, my understanding is that there can't be any default value? 


This is desirable, but it does not correspond to the code.


What do
you think would be a default value? The one for SD boot? The one for
NAND? Or? Who will decide what the default should be?


Whatever we choose, it is wrong. We can select SD, and one board has not
a SD interface. The same with NAND, ...

The best one is we have not a default value.


Yes, agree.


at the beginning of the
processing or to raise an error if we want to make this statement
mandatory in the configuration file.

If there can't be a default value, I think to raise an error if no
BOOT_FROM statement is there is the only option.


Agree - BOOT_FROM must be mandatory.


What do you think about anything like below then [1]?

I looked through the imximage.c code and, well, due to the mixture to 
support the v1 and v2 header format, the execution path isn't the 
cleanest one. So, while it doesn't seem to be the cleanest way to exit 
directly in set_imx_hdr_v2, it seems to be the easiest and best place to 
add this check. Some other functions have some exit() calls, too, so it 
seems to be common practice in this code.


If this is ok, I will send a v2 of the patch.

Best regards

Dirk

[1]

--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -253,8 +253,12 @@ static void set_imx_hdr_v2(struct imx_header 
*imxhdr, uint32_t dcd_len,

imx_header_v2_t *hdr_v2 = imxhdr-header.hdr_v2;
flash_header_v2_t *fhdr_v2 = hdr_v2-fhdr;

-   /* Set default offset */
-   imxhdr-flash_offset = FLASH_OFFSET_STANDARD;
+   /* Exit if there is no BOOT_FROM field specifying the flash_offset */
+   if(imxhdr-flash_offset == 0) {
+   fprintf(stderr, Error: Header v2: No BOOT_FROM tag in %s\n,
+   params-imagename);
+   exit(EXIT_FAILURE);
+   }

/* Set magic number */
fhdr_v2-header.tag = IVT_HEADER_TAG; /* 0xD1 */
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Re: [U-Boot] [PATCH] imximage: header v2: Remove overwriting of flash_offset

2012-02-22 Thread Stefano Babic 
On 22/02/2012 09:14, Dirk Behme wrote:
 On 21.02.2012 22:49, stefano babic wrote:
 Am 21/02/2012 20:18, schrieb Dirk Behme:


Hi Dirk,

 What do you think about anything like below then [1]?
 
 I looked through the imximage.c code and, well, due to the mixture to
 support the v1 and v2 header format, the execution path isn't the
 cleanest one. So, while it doesn't seem to be the cleanest way to exit
 directly in set_imx_hdr_v2, it seems to be the easiest and best place to
 add this check. Some other functions have some exit() calls, too, so it
 seems to be common practice in this code.

It is common in all mkimage - when there is an error, it makes no sense
to go on.

You must also fix this issue for V1 in set_imx_hdr_v1() as well, because
we do not want default value at all. I suggest also you do not check
with if(imxhdr-flash_offset == 0), in case Freescale will put a SOC
without an offset in the future. But it is easy to add a value that is
not allowed. If we add something like

FLASH_OFFSET_UNDEFINED = 0xFF

or whatever you want that is not 32-bit aligned, we are on the safest side.

 
 If this is ok, I will send a v2 of the patch.

Ok, thanks.

Best regards,
Stefano

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Re: [U-Boot] [PATCH] imximage: header v2: Remove overwriting of flash_offset

2012-02-22 Thread Dirk Behme 

On 22.02.2012 10:29, Stefano Babic wrote:

On 22/02/2012 09:14, Dirk Behme wrote:

On 21.02.2012 22:49, stefano babic wrote:

Am 21/02/2012 20:18, schrieb Dirk Behme:



Hi Dirk,


What do you think about anything like below then [1]?

I looked through the imximage.c code and, well, due to the mixture to
support the v1 and v2 header format, the execution path isn't the
cleanest one. So, while it doesn't seem to be the cleanest way to exit
directly in set_imx_hdr_v2, it seems to be the easiest and best place to
add this check. Some other functions have some exit() calls, too, so it
seems to be common practice in this code.


It is common in all mkimage - when there is an error, it makes no sense
to go on.

You must also fix this issue for V1 in set_imx_hdr_v1() as well, because
we do not want default value at all.


Ok, the V1 topic is new.

I can't touch V1 because I don't know anything about it. And I don't 
have any hardware to test anything V1 related.


Even though the V1 code might have a similar issue, it's my 
understanding that it doesn't hurt there as in V1 there are no 
flash_offsets != FLASH_OFFSET_STANDARD. Therefore in V1 the existing 
code works fine (?). Same as the V2 code before Freescale introduced 
flash offsets which are not FLASH_OFFSET_STANDARD (== 0x400).



I suggest also you do not check
with if(imxhdr-flash_offset == 0), in case Freescale will put a SOC
without an offset in the future. But it is easy to add a value that is
not allowed. If we add something like

FLASH_OFFSET_UNDEFINED = 0xFF

or whatever you want that is not 32-bit aligned, we are on the safest side.


I will look where the correct location might be to add this.


If this is ok, I will send a v2 of the patch.


I will try to update the V2 header with something like 
FLASH_OFFSET_UNDEFINED as proposed above and then send a v2 of the patch.


Best regards

Dirk
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Re: [U-Boot] [PATCH] microblaze: fix build failure due to undefined reference to `get_ticks'

2012-02-22 Thread Michal Simek 

Stephan Linz wrote:

after http://patchwork.ozlabs.org/patch/136415/ was applied.
The Microblaze generic build fails with below error


Please sure patch subject + sha1 sum instead of link to system
which doesn't need to work in future. Git reference will work.

Thanks,
Michal

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Re: [U-Boot] [PATCH] imximage: header v2: Remove overwriting of flash_offset

2012-02-22 Thread Stefano Babic 
On 22/02/2012 10:40, Dirk Behme wrote:

 You must also fix this issue for V1 in set_imx_hdr_v1() as well, because
 we do not want default value at all.
 
 Ok, the V1 topic is new.
 
 I can't touch V1 because I don't know anything about it. And I don't
 have any hardware to test anything V1 related.
 

It is enough if you add the same check in set_imx_hdr_v1() you want to
put in  set_imx_hdr_v2().

 Even though the V1 code might have a similar issue, it's my
 understanding that it doesn't hurt there as in V1 there are no
 flash_offsets != FLASH_OFFSET_STANDARD.

This is not correct. For the MX51, there is a different offset for the
onenand device. But there is not a board booting from onenand in mainline.

However, we want that BOOT_FROM is mandatory to avoid confusion. All V1
boards in mainline have BOOT_FROM in their imximage file, so it is
enough to test if we can build the boards.

 Therefore in V1 the existing
 code works fine (?). Same as the V2 code before Freescale introduced
 flash offsets which are not FLASH_OFFSET_STANDARD (== 0x400).

It is the same with both versions - also with V1 there are different
offset, but SD / NAND / SPI share the same offset.

 
 I suggest also you do not check
 with if(imxhdr-flash_offset == 0), in case Freescale will put a SOC
 without an offset in the future. But it is easy to add a value that is
 not allowed. If we add something like

 FLASH_OFFSET_UNDEFINED = 0xFF

 or whatever you want that is not 32-bit aligned, we are on the safest
 side.
 
 I will look where the correct location might be to add this.

Add it into imximage.h

Best regards,
Stefano

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[U-Boot] PR1-Appliance UART Boot Issue

2012-02-22 Thread Amber and Sarosh 




Hi all We have somehow damaged u-boot of PR1-Appliance. Now are trying to 
unbrick the device.We read in one of the posts at the switchfin forum   that we 
can unbrick the device by changing the Boot mode to UART.

Here are the steps that we are following to address this issue.
 
1. Changing the bootmode to UART 2. Loading the u-boot  file in ldr format 
through LdrViewer. 
3.  Accessing this u-boot in hyperterminal via serial connection
4. Transfering the u-boot file for SPI mode in ldr format to the board via tftp 
to a RAM location.
5. Writing this u-boot to the SPI flash using sf commands of erase and write.
6.Changing the bootmode to SPI again.
7. Trying to access this u-boot from SPI flash .
 
In these setps, the u-boot  files that are accesed successfully in both UART 
and SPI boot modes are the ones compiled for BF537 STAMP board on the terminal 
emulator. This uboot is unable to boot a uImage compiled for PR1-Appliance. The 
ones  we compiled for PR1 Appliance dont show up on the terminal emulator in 
both modes, and same is the result for the precompiled u-boot for PR1 
Appliance. 
Can anyone please guide us, what to do in order to access u-boot of 
PR1-Appliance and to boot the image?
Let us know if you require any other details.We shall be very thankful!
 
Regards,
Amber  Sarosh 
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[U-Boot] Patch: Fix device enumeration through API.

2012-02-22 Thread Tim Kientzle 
The one-line patch below fixes device enumeration through the
U-Boot API.

Device enumeration crashes when the system in question doesn't
have any RAM mapped to address zero (I discovered this on a
BeagleBone board), since the enumeration calls get_dev with a
NULL ifname sometimes which then gets passed down to strncmp().

This fix simply ensures that get_dev returns NULL when invoked
with a NULL ifname.

This could also be fixed by reworking the device enumeration to
never call get_dev with a NULL argument, but that's a much more
extensive change.  (get_dev is called from several places and the
code is driven by a list that's constructed in a way that naturally
leaves lots of NULLs.)

Cheers,

Tim Kientzle

diff --git a/disk/part.c b/disk/part.c
index f07a17f..1a82539 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -84,7 +84,7 @@ block_dev_desc_t *get_dev(char* ifname, int dev)
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
name += gd-reloc_off;
 #endif
-   while (drvr-name) {
+   while (ifname  drvr-name) {
name = drvr-name;
reloc_get_dev = drvr-get_dev;
 #ifdef CONFIG_NEEDS_MANUAL_RELOC

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[U-Boot] [PATCH] ARMV7/Vexpress: add missing get_ticks() and get_tbclk()

2012-02-22 Thread Liming Wang 
From: walimis walimis...@gmail.com

commit f31a911fe (arm, post: add missing post_time_ms for arm)
enables get_ticks and get_tbclk for all arm based boards,
arm/vexpress also needs these functions to work.

Signed-off-by: walimis walimis...@gmail.com
---
 board/armltd/vexpress/ca9x4_ct_vxp.c |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c 
b/board/armltd/vexpress/ca9x4_ct_vxp.c
index da6f14d..0b36d12 100644
--- a/board/armltd/vexpress/ca9x4_ct_vxp.c
+++ b/board/armltd/vexpress/ca9x4_ct_vxp.c
@@ -226,3 +226,13 @@ void lowlevel_init(void)
 ulong get_board_rev(void){
return readl((u32 *)SYS_ID);
 }
+
+unsigned long long get_ticks(void)
+{
+   return get_timer(0);
+}
+
+ulong get_tbclk (void)
+{
+   return (ulong)CONFIG_SYS_HZ;
+}
-- 
1.7.0.4

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[U-Boot] [PATCH 1/9] Define UART4 and UART5 base addresses

2012-02-22 Thread Stefano Babic 
Signed-off-by: Stefano Babic sba...@denx.de
---
 arch/arm/include/asm/arch-mx5/imx-regs.h |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 4fa6658..07296b5 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -93,6 +93,7 @@
 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E)
 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
+#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F)
 #endif
 /*
  * AIPS 2
@@ -133,6 +134,10 @@
 #define VPU_BASE_ADDR  (AIPS2_BASE_ADDR + 0x000F4000)
 #define SAHARA_BASE_ADDR   (AIPS2_BASE_ADDR + 0x000F8000)
 
+#if defined(CONFIG_MX53)
+#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009)
+#endif
+
 /*
  * WEIM CSnGCR1
  */
-- 
1.7.5.4

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[U-Boot] [PATCH 3/9] NET: fec_mxc.c: Add a way to disable auto negotiation

2012-02-22 Thread Stefano Babic 
Signed-off-by: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
 drivers/net/fec_mxc.c |4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 201e5d2..a45ac3f 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -175,9 +175,10 @@ int fec_phy_write(struct mii_dev *bus, int phyAddr, int 
dev_addr, int regAddr,
 #ifndef CONFIG_PHYLIB
 static int miiphy_restart_aneg(struct eth_device *dev)
 {
+   int ret = 0;
+#if !defined(CONFIG_FEC_MXC_NO_ANEG)
struct fec_priv *fec = (struct fec_priv *)dev-priv;
struct ethernet_regs *eth = fec-bus-priv;
-   int ret = 0;
 
/*
 * Wake up from sleep if necessary
@@ -201,6 +202,7 @@ static int miiphy_restart_aneg(struct eth_device *dev)
if (fec-mii_postcall)
ret = fec-mii_postcall(fec-phy_id);
 
+#endif
return ret;
 }
 
-- 
1.7.5.4

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[U-Boot] [PATCH 2/9] NET: fec_mxc.c: Add support for MII for MX5 SOCs

2012-02-22 Thread Stefano Babic 
Signed-off-by: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
 drivers/net/fec_mxc.c |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1fdd071..201e5d2 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -419,8 +419,13 @@ static int fec_open(struct eth_device *edev)
while (readw(fec-eth-miigsk_enr)  MIIGSK_ENR_READY)
udelay(2);
 
+#if !defined(CONFIG_MII)
/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
writew(MIIGSK_CFGR_IF_MODE_RMII, fec-eth-miigsk_cfgr);
+#else
+   /* configure gasket for MII, no loopback, and no echo */
+   writew(MIIGSK_CFGR_IF_MODE_MII, fec-eth-miigsk_cfgr);
+#endif
 
/* re-enable the gasket */
writew(MIIGSK_ENR_EN, fec-eth-miigsk_enr);
-- 
1.7.5.4

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[U-Boot] [PATCH 4/9] MX5: Add definitions for SATA controller

2012-02-22 Thread Stefano Babic 
Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.

Signed-off-by: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
CC: Dirk Behme dirk.be...@de.bosch.com
---
 arch/arm/cpu/armv7/mx5/clock.c   |2 ++
 arch/arm/include/asm/arch-mx5/clock.h|1 +
 arch/arm/include/asm/arch-mx5/imx-regs.h |1 +
 3 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index e92f106..8f8d01c 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -380,6 +380,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
case MXC_FEC_CLK:
return decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_SYS_MX5_HCLK);
+   case MXC_SATA_CLK:
+   return get_ahb_clk();
default:
break;
}
diff --git a/arch/arm/include/asm/arch-mx5/clock.h 
b/arch/arm/include/asm/arch-mx5/clock.h
index ea972a3..f9f82f3 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -32,6 +32,7 @@ enum mxc_clock {
MXC_UART_CLK,
MXC_CSPI_CLK,
MXC_FEC_CLK,
+   MXC_SATA_CLK,
 };
 
 unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 07296b5..a4245a3 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -43,6 +43,7 @@
 #define NFC_BASE_ADDR_AXI   0xF7FF
 #define IRAM_BASE_ADDR  0xF800
 #define CS1_BASE_ADDR   0xF400
+#define SATA_BASE_ADDR 0x1000
 #else
 #error CPU_TYPE not defined
 #endif
-- 
1.7.5.4

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[U-Boot] [PATCH 6/9] MX53: add function to set SATA clock to internal

2012-02-22 Thread Stefano Babic 
The MX53 SATA interface can use an internal clock (USB PHY1)
instead of an external clock. This is an undocumented feature, but used
on most Freescale's evaluation boards, such as MX53-loco.

As stated by Freescale's support:

Fuses (but not pins) may be used to configure SATA clocks.
Particularly the i.MX53 Fuse_Map contains the next information
about configuring SATA clocks :
SATA_ALT_REF_CLK[1:0] (offset 0x180C)

'00' - 100MHz (External)
'01' - 50MHz (External)
'10' - 120MHz, internal (USB PHY)
'11' - Reserved

Signed-off-by: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
 arch/arm/cpu/armv7/mx5/clock.c|   24 
 arch/arm/include/asm/arch-mx5/clock.h |1 +
 2 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 8f8d01c..d769a4d 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -399,6 +399,30 @@ u32 imx_get_fecclk(void)
return mxc_get_clock(MXC_IPG_CLK);
 }
 
+#ifdef CONFIG_MX53
+/*
+ * The clock for the external interface can be set to use internal clock
+ * if fuse bank 4, row 3, bit 2 is set.
+ * This is an undocumented feature and it was confirmed by Freescale's support:
+ * Fuses (but not pins) may be used to configure SATA clocks.
+ * Particularly the i.MX53 Fuse_Map contains the next information
+ * about configuring SATA clocks :  SATA_ALT_REF_CLK[1:0] (offset 0x180C)
+ * '00' - 100MHz (External)
+ * '01' - 50MHz (External)
+ * '10' - 120MHz, internal (USB PHY)
+ * '11' - Reserved
+*/
+void mxc_set_sata_internal_clock(void)
+{
+   u32 *tmp_base =
+   (u32 *)(IIM_BASE_ADDR + 0x180c);
+
+   set_usb_phy1_clk();
+
+   writel((readl(tmp_base)  (~0x7)) | 0x4, tmp_base);
+}
+#endif
+
 /*
  * Dump some core clockes.
  */
diff --git a/arch/arm/include/asm/arch-mx5/clock.h 
b/arch/arm/include/asm/arch-mx5/clock.h
index f9f82f3..e822809 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -45,5 +45,6 @@ void set_usb_phy2_clk(void);
 void enable_usb_phy2_clk(unsigned char enable);
 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
+void mxc_set_sata_internal_clock(void);
 
 #endif /* __ASM_ARCH_CLOCK_H */
-- 
1.7.5.4

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[U-Boot] [PATCH 5/9] SATA: check for return value from sata functions

2012-02-22 Thread Stefano Babic 
sata functions are called even if previous functions failed
because return value is not checked.

Signed-off-by: Stefano Babic sba...@denx.de
CC: Dirk Behme dirk.be...@de.bosch.com
CC: Fabio Estevam fabio.este...@freescale.com
---
 common/cmd_sata.c |9 ++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/common/cmd_sata.c b/common/cmd_sata.c
index f62c0cb..dfa5300 100644
--- a/common/cmd_sata.c
+++ b/common/cmd_sata.c
@@ -48,9 +48,12 @@ int __sata_initialize(void)
sata_dev_desc[i].block_write = sata_write;
 
rc = init_sata(i);
-   rc = scan_sata(i);
-   if ((sata_dev_desc[i].lba  0)  (sata_dev_desc[i].blksz  0))
-   init_part(sata_dev_desc[i]);
+   if (!rc) {
+   rc = scan_sata(i);
+   if (!rc  (sata_dev_desc[i].lba  0) 
+   (sata_dev_desc[i].blksz  0))
+   init_part(sata_dev_desc[i]);
+   }
}
sata_curr_device = 0;
return rc;
-- 
1.7.5.4

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[U-Boot] [PATCH 8/9] MX53: Add support to ESG ima3 board

2012-02-22 Thread Stefano Babic 
The ESG ima3-mx53 board is based on the Freescale
i.MX53 SOC. It boots from NOR (128 MB) and
supports Ethernet (FEC), SATA.

Signed-off-by: Stefano Babic sba...@denx.de
---
 board/esg/ima3-mx53/Makefile |   41 +
 board/esg/ima3-mx53/ima3-mx53.c  |  302 ++
 board/esg/ima3-mx53/imximage.cfg |  108 ++
 boards.cfg   |1 +
 include/configs/ima3-mx53.h  |  269 +
 5 files changed, 721 insertions(+), 0 deletions(-)
 create mode 100644 board/esg/ima3-mx53/Makefile
 create mode 100644 board/esg/ima3-mx53/ima3-mx53.c
 create mode 100644 board/esg/ima3-mx53/imximage.cfg
 create mode 100644 include/configs/ima3-mx53.h

diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile
new file mode 100644
index 000..f3b13bc
--- /dev/null
+++ b/board/esg/ima3-mx53/Makefile
@@ -0,0 +1,41 @@
+#
+# Copyright (C) 2012, Stefano Babic sba...@denx.de
+#
+# Based on ti/evm/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS  := ima3-mx53.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+   $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c
new file mode 100644
index 000..9ecf31d
--- /dev/null
+++ b/board/esg/ima3-mx53/ima3-mx53.c
@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2012, Stefano Babic sba...@denx.de
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include common.h
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/arch/mx5x_pins.h
+#include asm/arch/sys_proto.h
+#include asm/arch/crm_regs.h
+#include asm/arch/clock.h
+#include asm/arch/iomux.h
+#include asm/errno.h
+#include netdev.h
+#include mmc.h
+#include fsl_esdhc.h
+#include asm/gpio.h
+
+/* NOR flash configuration */
+#define IMA3_MX53_CS0GCR1  (CSEN | DSZ(2))
+#define IMA3_MX53_CS0GCR2  0
+#define IMA3_MX53_CS0RCR1  (RCSN(2) | OEN(1) | RWSC(15))
+#define IMA3_MX53_CS0RCR2  0
+#define IMA3_MX53_CS0WCR1  (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
+#define IMA3_MX53_CS0WCR2  0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void weim_nor_settings(void)
+{
+   struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+   writel(IMA3_MX53_CS0GCR1, weim_regs-cs0gcr1);
+   writel(IMA3_MX53_CS0GCR2, weim_regs-cs0gcr2);
+   writel(IMA3_MX53_CS0RCR1, weim_regs-cs0rcr1);
+   writel(IMA3_MX53_CS0RCR2, weim_regs-cs0rcr2);
+   writel(IMA3_MX53_CS0WCR1, weim_regs-cs0wcr1);
+   writel(IMA3_MX53_CS0WCR2, weim_regs-cs0wcr2);
+   writel(0x0, weim_regs-wcr);
+
+   set_chipselect_size(CS0_128);
+}
+
+int dram_init(void)
+{
+   gd-ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+   PHYS_SDRAM_1_SIZE);
+   return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+   /* UART4 RXD */
+   mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
+   mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
+   PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+   PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
+   PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+

[U-Boot] [PATCH 7/9] SATA: add driver for MX5 / MX6 SOCs

2012-02-22 Thread Stefano Babic 
This driver is part of Freescale's LTIB for
MX5 / MX6.

Signed-off-by: Stefano Babic sba...@denx.de
Signed-off-by: Terry Lv r65...@freescale.com
CC: Fabio Estevam fabio.este...@freescale.com
CC: Dirk Behme dirk.be...@de.bosch.com
---
 drivers/block/Makefile |1 +
 drivers/block/dwc_ahsata.c |  969 
 drivers/block/dwc_ahsata.h |  335 +++
 include/ahci.h |5 +-
 4 files changed, 1308 insertions(+), 2 deletions(-)
 create mode 100644 drivers/block/dwc_ahsata.c
 create mode 100644 drivers/block/dwc_ahsata.h

diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 98560ef..b9c2047 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -27,6 +27,7 @@ LIB   := $(obj)libblock.o
 
 COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
 COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
+COBJS-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
 COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o
 COBJS-$(CONFIG_IDE_FTIDE020) += ftide020.o
 COBJS-$(CONFIG_LIBATA) += libata.o
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
new file mode 100644
index 000..2703d3d
--- /dev/null
+++ b/drivers/block/dwc_ahsata.c
@@ -0,0 +1,969 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Terry Lv r65...@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ *
+ */
+
+#include libata.h
+#include ahci.h
+#include fis.h
+
+#include common.h
+#include malloc.h
+#include linux/ctype.h
+#include asm/errno.h
+#include asm/io.h
+#include linux/bitops.h
+#include asm/arch/clock.h
+#include dwc_ahsata.h
+
+struct sata_port_regs {
+   u32 clb;
+   u32 clbu;
+   u32 fb;
+   u32 fbu;
+   u32 is;
+   u32 ie;
+   u32 cmd;
+   u32 res1[1];
+   u32 tfd;
+   u32 sig;
+   u32 ssts;
+   u32 sctl;
+   u32 serr;
+   u32 sact;
+   u32 ci;
+   u32 sntf;
+   u32 res2[1];
+   u32 dmacr;
+   u32 res3[1];
+   u32 phycr;
+   u32 physr;
+};
+
+struct sata_host_regs {
+   u32 cap;
+   u32 ghc;
+   u32 is;
+   u32 pi;
+   u32 vs;
+   u32 ccc_ctl;
+   u32 ccc_ports;
+   u32 res1[2];
+   u32 cap2;
+   u32 res2[30];
+   u32 bistafr;
+   u32 bistcr;
+   u32 bistfctr;
+   u32 bistsr;
+   u32 bistdecr;
+   u32 res3[2];
+   u32 oobr;
+   u32 res4[8];
+   u32 timer1ms;
+   u32 res5[1];
+   u32 gparam1r;
+   u32 gparam2r;
+   u32 pparamr;
+   u32 testr;
+   u32 versionr;
+   u32 idr;
+};
+
+#define MAX_DATA_BYTES_PER_SG  (4 * 1024 * 1024)
+#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
+
+#define writel_with_flush(a, b)do { writel(a, b); readl(b); } while (0)
+
+static int is_ready;
+
+static inline u32 ahci_port_base(u32 base, u32 port)
+{
+   return base + 0x100 + (port * 0x80);
+}
+
+static int waiting_for_cmd_completed(u8 *offset,
+   int timeout_msec,
+   u32 sign)
+{
+   int i;
+   u32 status;
+
+   for (i = 0;
+   ((status = readl(offset))  sign)  i  timeout_msec;
+   ++i)
+   mdelay(1);
+
+   return (i  timeout_msec) ? 0 : -1;
+}
+
+static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent,
+   int clk)
+{
+   struct sata_host_regs *host_mmio =
+   (struct sata_host_regs *)probe_ent-mmio_base;
+
+   writel(SATA_HOST_OOBR_WE, (host_mmio-oobr));
+   writel(0x02060b14, (host_mmio-oobr));
+
+   return 0;
+}
+
+static int ahci_host_init(struct ahci_probe_ent *probe_ent)
+{
+   u32 tmp, cap_save, num_ports;
+   int i, j, timeout = 1000;
+   struct sata_port_regs *port_mmio = NULL;
+   struct sata_host_regs *host_mmio =
+   (struct sata_host_regs *)probe_ent-mmio_base;
+   int clk = mxc_get_clock(MXC_SATA_CLK);
+
+   cap_save = readl((host_mmio-cap));
+   cap_save |= SATA_HOST_CAP_SSS;
+
+   /* global controller reset */
+   tmp = readl((host_mmio-ghc));
+   if ((tmp  SATA_HOST_GHC_HR) == 0)
+   writel_with_flush(tmp | SATA_HOST_GHC_HR, (host_mmio-ghc));
+
+   while ((readl((host_mmio-ghc))

[U-Boot] [PATCH 9/9] MX53: mx53loco: Add SATA support

2012-02-22 Thread Stefano Babic 
Signed-off-by: Stefano Babic sba...@denx.de
CC: Jason Liu jason@linaro.org
---
 board/freescale/mx53loco/mx53loco.c |3 +++
 include/configs/mx53loco.h  |   11 +++
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx53loco/mx53loco.c 
b/board/freescale/mx53loco/mx53loco.c
index d736141..7ea9f6e 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -27,6 +27,7 @@
 #include asm/arch/mx5x_pins.h
 #include asm/arch/sys_proto.h
 #include asm/arch/crm_regs.h
+#include asm/arch/clock.h
 #include asm/arch/iomux.h
 #include asm/arch/clock.h
 #include asm/errno.h
@@ -302,6 +303,8 @@ int board_init(void)
 {
gd-bd-bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+   mxc_set_sata_internal_clock();
+
return 0;
 }
 
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 34a4edd..af59307 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -56,6 +56,7 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 
 /* Eth Configs */
@@ -193,4 +194,14 @@
 
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+   #define CONFIG_DWC_AHSATA
+   #define CONFIG_SYS_SATA_MAX_DEVICE  1
+   #define CONFIG_DWC_AHSATA_PORT_ID   0
+   #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
+   #define CONFIG_LBA48
+   #define CONFIG_LIBATA
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.7.5.4

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Re: [U-Boot] [PATCH 8/9] MX53: Add support to ESG ima3 board

2012-02-22 Thread Dirk Behme 

On 22.02.2012 11:24, Stefano Babic wrote:
...

It boots from NOR (128 MB)


Ah. I wonder why I was under the impression that I was the only guy 
fighting with the imximage NOR header pain, then ;)



diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
new file mode 100644
index 000..fa6b42d
--- /dev/null
+++ b/board/esg/ima3-mx53/imximage.cfg

...

+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)


Maybe the above comment should be updated for nor? ;)


+BOOT_FROM  nor


I assume that you have tested this and it works with the imximage?

Best regards

Dirk
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Re: [U-Boot] [PATCH 8/9] MX53: Add support to ESG ima3 board

2012-02-22 Thread Stefano Babic 
On 22/02/2012 11:30, Dirk Behme wrote:
 On 22.02.2012 11:24, Stefano Babic wrote:
 ...
 It boots from NOR (128 MB)
 
 Ah. I wonder why I was under the impression that I was the only guy
 fighting with the imximage NOR header pain, then ;)

When something goes wrong, it does for everybody...

 
 diff --git a/board/esg/ima3-mx53/imximage.cfg
 b/board/esg/ima3-mx53/imximage.cfg
 new file mode 100644
 index 000..fa6b42d
 --- /dev/null
 +++ b/board/esg/ima3-mx53/imximage.cfg
 ...
 +# Boot Device : one of
 +# spi, sd (the board has no nand neither onenand)
 
 Maybe the above comment should be updated for nor? ;)

Yes, I'll do

 
 +BOOT_FROM  nor
 
 I assume that you have tested this and it works with the imximage?

I have not any problem with the current imximage, so I am quite
confused. Agree that you are fixing a bug, but I have not understood why
I have not seen any issue on my board, a MX53 using V2 image header.

My board boots flawlessly from the NOR interface. I will try to
investigate why and, of course, I will be able to test your patch on my
board.

Can you confirm that your board does not boot ? Or are there other
symptoms ?

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 0/9] Fix a few warnings that bug me

2012-02-22 Thread Stefano Babic 
On 21/02/2012 19:40, Simon Glass wrote:

 Yes but not just those. There are detailed notes with each patch, but
 here is a summary. I think 6 out of 9 patches should be applied
 regardless of toolchain.
 
 68k only:
  arch/m68k/lib/board.c   |2 +-
 - I believe this fix is sensible for the reasons described in the
 patch, regardless of what the toolchain does.

Agree - I will send my ACK and merge it into my u-boot-staging

  arch/powerpc/lib/board.c|7 +--
 - Similar to the68k patch, again I think it makes sense to apply this.
 The variable is unsigned char for no good reason.

Agree, there is no reason. I will merge also this one into u-boot-staging.

 
 Sandbox:
  arch/sandbox/cpu/os.c   |   11 +++--
 - This should be applied as it is not toolchain dependent (Mike may
 have picked it up already)

Ok, the patch has already found its way to mainline

 
 ARM and PPC:
  drivers/usb/host/ohci-hcd.c |   26 ++--
 - These happen with my 4.4.4 compiler, apparently not on 4.6. Drop
 them if you like.
 
 ARM:
  include/configs/snapper9260.h   |1 -
 - This fixes a real problem regardless of toolchain.

Right. I will send my ACK with CC to Albert. He can pick-up it directly
into u-boot-arm.

Best regards,
Stefano

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Re: [U-Boot] [PATCH] ARMV7/Vexpress: add missing get_ticks() and get_tbclk()

2012-02-22 Thread Marek Vasut 
 From: walimis walimis...@gmail.com
 
 commit f31a911fe (arm, post: add missing post_time_ms for arm)
 enables get_ticks and get_tbclk for all arm based boards,
 arm/vexpress also needs these functions to work.
 
 Signed-off-by: walimis walimis...@gmail.com

Please, put your real name in the SoB line. That's the purpose of the SoB line!

 ---
  board/armltd/vexpress/ca9x4_ct_vxp.c |   10 ++
  1 files changed, 10 insertions(+), 0 deletions(-)
 
 diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c
 b/board/armltd/vexpress/ca9x4_ct_vxp.c index da6f14d..0b36d12 100644
 --- a/board/armltd/vexpress/ca9x4_ct_vxp.c
 +++ b/board/armltd/vexpress/ca9x4_ct_vxp.c
 @@ -226,3 +226,13 @@ void lowlevel_init(void)
  ulong get_board_rev(void){
   return readl((u32 *)SYS_ID);
  }
 +
 +unsigned long long get_ticks(void)
 +{
 + return get_timer(0);
 +}
 +
 +ulong get_tbclk (void)
 +{
 + return (ulong)CONFIG_SYS_HZ;
 +}
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Re: [U-Boot] [PATCH 7/9] Remove CONFIG_SYS_EXTBDINFO from snapper9260.h

2012-02-22 Thread Stefano Babic 
On 06/01/2012 04:54, Simon Glass wrote:
 This feature is not available on ARM, so it is an error to define it.
 
 Signed-off-by: Simon Glass s...@chromium.org
 ---
  include/configs/snapper9260.h |1 -
  1 files changed, 0 insertions(+), 1 deletions(-)
 
 diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
 index cb3c674..cee65d1 100644
 --- a/include/configs/snapper9260.h
 +++ b/include/configs/snapper9260.h
 @@ -157,7 +157,6 @@
  #define CONFIG_SYS_PBSIZE(CONFIG_SYS_CBSIZE +\
sizeof(CONFIG_SYS_PROMPT) + 16)
  #define CONFIG_SYS_LONGHELP
 -#define CONFIG_SYS_EXTBDINFO
  #define CONFIG_CMDLINE_EDITING
  #define CONFIG_AUTO_COMPLETE
  #define CONFIG_SYS_HUSH_PARSER

Acked-by: Stefano Babic sba...@denx.de

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH 8/9] MX53: Add support to ESG ima3 board

2012-02-22 Thread Dirk Behme 

On 22.02.2012 11:46, Stefano Babic wrote:

On 22/02/2012 11:30, Dirk Behme wrote:

On 22.02.2012 11:24, Stefano Babic wrote:
...

+BOOT_FROM  nor

I assume that you have tested this and it works with the imximage?


I have not any problem with the current imximage, so I am quite
confused. 


Hmm, yes, this is quite confusing :(


Agree that you are fixing a bug, but I have not understood why
I have not seen any issue on my board, a MX53 using V2 image header.

My board boots flawlessly from the NOR interface. I will try to
investigate why and, of course, I will be able to test your patch on my
board.

Can you confirm that your board does not boot ? 


Yes, removing the imximage fix stops the board from booting. 
Unfortunately it's hard to debug how the boot ROM deals with the header 
information. So either it works, or not, but there is little chance to 
debug :(


For testing, taking the SabreLite (mx6qsabrelite), switching it to NOR 
[1] and then compiling it without and with my imximage fix, results in 
the following difference in the header (disassembly of u-boot.imx):


-  20:  177ff800
+  20:  177fec00

At offset 0x20 in the header, this is the target address in the 
destination memory. Having a header with the size of 0x400 (like here) 
the destination address should be TEXT_BASE - 0x400 (header size) - 
0x1000 (NOR offset), i.e. 0x1780 - 0x1400. So my understanding is 
that 0x177fec00 is correct for NOR, while 0x177ff800 is valid for all 
FLASH_OFFSET_STANDARD devices.


Best regards

Dirk

[1]

board/freescale/mx6qsabrelite/imximage.cfg
BOOT_FROM   nor
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Re: [U-Boot] [PATCH 9/9] ppc: Change memsz variable to signed char

2012-02-22 Thread Stefano Babic 
On 06/01/2012 04:54, Simon Glass wrote:
 This seems to be unsigned char for no good reason. Tidy this up and
 remove the casts.
 
 Signed-off-by: Simon Glass s...@chromium.org
 ---

Applied to u-boot-staging, sba...@denx.de branch, thanks.

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 8/9] m68k: Change memsz to a signed char to avoid warning

2012-02-22 Thread Stefano Babic 
On 06/01/2012 04:54, Simon Glass wrote:
 There doesn't seem to be any reason for using uchar here, so change it
 to char. This fixes a warning:
 
 pointer targets in passing argument 1 of 'sprintf' differ in signedness
 
 Signed-off-by: Simon Glass s...@chromium.org
 ---

Applied to u-boot-staging, sba...@denx.de branch, thanks.

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] sh: i2c: Add support I2C controller of SH7734

2012-02-22 Thread Marek Vasut 
 On Tuesday 21 February 2012 20:13:47 Nobuhiro Iwamatsu wrote:
  --- /dev/null
  +++ b/drivers/i2c/sh_sh7734_i2c.c
  
  +#if DEBUG
  +static void sh_i2c_dump_reg(struct sh_i2c *base)
  +{
  +   printf(iccr1 : %02X\n, readb(base-iccr1));
  +   printf(iccr2 : %02X\n, readb(base-iccr2));
  +   printf(icmr  : %02X\n, readb(base-icmr));
  +   printf(icier : %02X\n, readb(base-icier));
  +   printf(icsr  : %02X\n, readb(base-icsr));
  +   printf(sar   : %02X\n, readb(base-sar));
  +   printf(icdrt : %02X\n, readb(base-icdrt));
  +   printf(icdrr : %02X\n, readb(base-icdrr));
  +   printf(nf2cyc: %02X\n, readb(base-nf2cyc));
  +}
  +#endif
 
 if you used debug(), you wouldn't need the DEBUG check

But this puts lower amount of strain on the CPP. It doesn't have to check if 
DEBUG is defined 10 times, but only once ;-) Putting this into one big debug() 
call is also possible btw., though I don't like it.

 
  +static int
  +i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size)
  +{
  +   int i;
  +   u8 data;
  +
  +   if (i2c_set_addr(base, id, reg)) {
  +   printf(Fail set slave address\n);
 
 should use puts() when there's no fmt
 
  +   for (i = 0 ; i  size ; i++) {
 
 no space before the semi-colon
 
  +int i2c_set_bus_num(unsigned int bus)
  +{
  +   if ((bus  0) || (bus = CONFIG_SYS_MAX_I2C_BUS)) {
  +   printf(Bad bus: %d\n, bus);
  +   return -1;
  +   }
  +
  +   switch (bus) {
  +   case 0:
  +   base = (void *)CONFIG_SH_I2C_BASE0;
  +   break;
  +   case 1:
  +   base = (void *)CONFIG_SH_I2C_BASE1;
  +   break;
  +   default:
  +   return -1;
  +   }
 
 do you need the if() check if you have default here ?

CONFIG_SYS_MAX_I2C_BUS may be different in some obscure case?

M

 -mike
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[U-Boot] [PATCH v2 0/4] Add DDR3 memory support for SMDK5250.

2012-02-22 Thread Hatim Ali 
SMDK5250 boards are available with different DDR memory variants like
LPDDR2, LPDDR3 and DDR3. This patch series adds support for DDR3
memory @ 667Mhz for SMDK5250 board.

In this patchset:
* Renamed dmc_init.c file to dmc_init_lpddr2.c
* Moved functions common to LPDDR2 and DDR3 memory setup from dmc_init_lpddr2.c
  to dmc_common.c
* Replaced register hex values with macro values for clarity.

Hatim Ali (4):
  SMDK5250: LPDDR2: Renaming the dmc_init.c file to dmc_init_lpddr2.c
  SMDK5250: LPDDR2: Renaming the PHY_RESET_VAL macro and fixing a minor
typo.
  SMDK5250: Creating a common file to be used by all variants of DDR
  SMDK5250: DDR3: Add memory initialization code for DDR3.

 board/samsung/smdk5250/Makefile|9 +-
 board/samsung/smdk5250/dmc_common.c|  133 ++
 board/samsung/smdk5250/dmc_init_ddr3.c |  276 
 .../smdk5250/{dmc_init.c = dmc_init_lpddr2.c} |  166 +---
 board/samsung/smdk5250/setup.h |  199 +--
 include/configs/smdk5250.h |6 +
 6 files changed, 607 insertions(+), 182 deletions(-)
 create mode 100644 board/samsung/smdk5250/dmc_common.c
 create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c
 rename board/samsung/smdk5250/{dmc_init.c = dmc_init_lpddr2.c} (66%)

-- 
1.7.2.3

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[U-Boot] [PATCH 1/4] SMDK5250: LPDDR2: Renaming the dmc_init.c file to dmc_init_lpddr2.c

2012-02-22 Thread Hatim Ali 
SMDK5250 board support different type of memory chips like DDR3, LPDDR2
and LPDDR3. Since the memory setup sequence for different types of
chips are different, therefore, we will have different dmc_init_xxx.c files.
Hence, renaming the dmc_init.c file (which is specific to LPDDR2)
to dmc_init_lpddr2.c

Signed-off-by: Hatim Ali hatim...@samsung.com

diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 226db1f..b18002a 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,7 +27,7 @@ LIB   = $(obj)lib$(BOARD).o
 SOBJS  := lowlevel_init.o
 
 COBJS  := clock_init.o
-COBJS  += dmc_init.o
+COBJS  += dmc_init_lpddr2.o
 COBJS  += tzpc_init.o
 
 ifndef CONFIG_SPL_BUILD
diff --git a/board/samsung/smdk5250/dmc_init.c 
b/board/samsung/smdk5250/dmc_init_lpddr2.c
similarity index 100%
rename from board/samsung/smdk5250/dmc_init.c
rename to board/samsung/smdk5250/dmc_init_lpddr2.c
-- 
1.7.2.3

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[U-Boot] [PATCH 2/4] SMDK5250: LPDDR2: Renaming the PHY_RESET_VAL macro and fixing a minor typo.

2012-02-22 Thread Hatim Ali 
The patch renames the macro PHY_RESET_VAL to LPDDR3PHY_CTRL_PHY_RESET for
clarity and also fixes a minor typo error to make the bit description similar
to as described in the Exynos user manual.

Signed-off-by: Hatim Ali hatim...@samsung.com

diff --git a/board/samsung/smdk5250/dmc_init_lpddr2.c 
b/board/samsung/smdk5250/dmc_init_lpddr2.c
index 7881074..846469e 100644
--- a/board/samsung/smdk5250/dmc_init_lpddr2.c
+++ b/board/samsung/smdk5250/dmc_init_lpddr2.c
@@ -53,7 +53,7 @@ static void reset_phy_ctrl(void)
 {
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
 
-   writel(PHY_RESET_VAL, clk-lpddr3phy_ctrl);
+   writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, clk-lpddr3phy_ctrl);
sdelay(0x1);
 }
 
@@ -246,9 +246,9 @@ static void config_rdlvl(struct exynos5_dmc *dmc,
/*
 * Set ctrl_gateadj, ctrl_readadj
 * ctrl_gateduradj, rdlvl_pass_adj
-* rdlvl_rddataPadj
+* rdlvl_rddata_adj
 */
-   val = SET_RDLVL_RDDATAPADJ;
+   val = SET_RDLVL_RDDATA_ADJ;
writel(val, phy0_ctrl-phy_con1);
writel(val, phy1_ctrl-phy_con1);
 
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
index 1276fd3..cf572ac 100644
--- a/board/samsung/smdk5250/setup.h
+++ b/board/samsung/smdk5250/setup.h
@@ -353,7 +353,8 @@
 /* (Memory Interleaving Size = 1  IV_SIZE) */
 #define CONFIG_IV_SIZE 0x07
 
-#define PHY_RESET_VAL  (0  0)
+#define LPDDR3PHY_CTRL_PHY_RESET   (1  0)
+#define LPDDR3PHY_CTRL_PHY_RESET_OFF   (0  0)
 
 /*ZQ Configurations */
 #define PHY_CON16_RESET_VAL0x08000304
@@ -397,9 +398,9 @@
 #define SET_CTRL_DDR_MODE(x, y)(x = (x  ~(0x3  11)) | y  11)
 
 #define PHY_CON1_RESET_VAL 0x9210100
-#define RDLVL_RDDATAPADJ   0x1
-#define SET_RDLVL_RDDATAPADJ   ((PHY_CON1_RESET_VAL  ~(0x  0))\
-   | RDLVL_RDDATAPADJ  0)
+#define RDLVL_RDDATA_ADJ   0x1
+#define SET_RDLVL_RDDATA_ADJ   ((PHY_CON1_RESET_VAL  ~(0x  0)) \
+   | RDLVL_RDDATA_ADJ  0)
 
 #define PHY_CON2_RESET_VAL 0x00010004
 #define RDLVL_EN   (1  25)
-- 
1.7.2.3

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[U-Boot] [PATCH 3/4] SMDK5250: Creating a common file to be used by all variants of DDR

2012-02-22 Thread Hatim Ali 
The patch creates a common file containing functions which will be
used by all variants of DDR.

Signed-off-by: Hatim Ali hatim...@samsung.com

diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index b18002a..3b4aa06 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,6 +27,7 @@ LIB   = $(obj)lib$(BOARD).o
 SOBJS  := lowlevel_init.o
 
 COBJS  := clock_init.o
+COBJS  += dmc_common.o
 COBJS  += dmc_init_lpddr2.o
 COBJS  += tzpc_init.o
 
diff --git a/board/samsung/smdk5250/dmc_common.c 
b/board/samsung/smdk5250/dmc_common.c
new file mode 100644
index 000..e940340
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_common.c
@@ -0,0 +1,133 @@
+/*
+ * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include setup.h
+
+void config_zq(struct exynos5_phy_control *phy0_ctrl,
+   struct exynos5_phy_control *phy1_ctrl)
+{
+   unsigned long val = 0;
+   /*
+* ZQ Calibration:
+* Select Driver Strength,
+* long calibration for manual calibration
+*/
+   val = PHY_CON16_RESET_VAL;
+   SET_ZQ_MODE_DDS_VAL(val);
+   SET_ZQ_MODE_TERM_VAL(val);
+   val |= ZQ_CLK_DIV_EN;
+   writel(val, phy0_ctrl-phy_con16);
+   writel(val, phy1_ctrl-phy_con16);
+
+   /* Disable termination */
+   val |= ZQ_MODE_NOTERM;
+   writel(val, phy0_ctrl-phy_con16);
+   writel(val, phy1_ctrl-phy_con16);
+
+   /* ZQ_MANUAL_START: Enable */
+   val |= ZQ_MANUAL_STR;
+   writel(val, phy0_ctrl-phy_con16);
+   writel(val, phy1_ctrl-phy_con16);
+   sdelay(0x1);
+
+   /* ZQ_MANUAL_START: Disable */
+   val = ~ZQ_MANUAL_STR;
+   writel(val, phy0_ctrl-phy_con16);
+   writel(val, phy1_ctrl-phy_con16);
+}
+
+void update_reset_dll(struct exynos5_dmc *dmc)
+{
+   unsigned long val;
+   /*
+* Update DLL Information:
+* Force DLL Resyncronization
+*/
+   val = readl(dmc-phycontrol0);
+   val |= FP_RSYNC;
+   writel(val, dmc-phycontrol0);
+
+   /* Reset Force DLL Resyncronization */
+   val = readl(dmc-phycontrol0);
+   val = ~FP_RSYNC;
+   writel(val, dmc-phycontrol0);
+}
+
+void config_mrs(struct exynos5_dmc *dmc)
+{
+   unsigned long channel, chip, mask = 0, val;
+
+   for (channel = 0; channel  CONFIG_DMC_CHANNELS; channel++) {
+   SET_CMD_CHANNEL(mask, channel);
+   for (chip = 0; chip  CONFIG_CHIPS_PER_CHANNEL; chip++) {
+   SET_CMD_CHIP(mask, chip);
+
+   /* Sending NOP command */
+   val = DIRECT_CMD_NOP | mask;
+   writel(val, dmc-directcmd);
+   sdelay(0x1);
+
+   /* Sending EMRS/MRS commands */
+   val = DIRECT_CMD_MRS1 | mask;
+   writel(val, dmc-directcmd);
+   sdelay(0x1);
+
+   val = DIRECT_CMD_MRS2 | mask;
+   writel(val, dmc-directcmd);
+   sdelay(0x1);
+
+   val = DIRECT_CMD_MRS3 | mask;
+   writel(val, dmc-directcmd);
+   sdelay(0x1);
+
+   val = DIRECT_CMD_MRS4 | mask;
+   writel(val, dmc-directcmd);
+   sdelay(0x1);
+   }
+   }
+}
+
+void config_prech(struct exynos5_dmc *dmc)
+{
+   unsigned long channel, chip, mask = 0, val;
+
+   for (channel = 0; channel  CONFIG_DMC_CHANNELS; channel++) {
+   SET_CMD_CHANNEL(mask, channel);
+   for (chip = 0; chip  CONFIG_CHIPS_PER_CHANNEL; chip++) {
+   SET_CMD_CHIP(mask, chip);
+   /* PALL (all banks precharge) CMD */
+   val = DIRECT_CMD_PALL | mask;
+   writel(val, dmc-directcmd);
+   sdelay(0x1);
+   }
+   }
+}
+
+void config_memory(struct exynos5_dmc *dmc)
+{
+   writel(DMC_MEMCONFIG0_VAL,

[U-Boot] [PATCH resend] ARMV7/Vexpress: add missing get_ticks() and get_tbclk()

2012-02-22 Thread walimis 
From: Liming Wang walimis...@gmail.com

commit f31a911fe (arm, post: add missing post_time_ms for arm)
enables get_ticks and get_tbclk for all arm based boards,
arm/vexpress also needs these functions to work.

Signed-off-by: Liming Wang walimis...@gmail.com
---
 board/armltd/vexpress/ca9x4_ct_vxp.c |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c 
b/board/armltd/vexpress/ca9x4_ct_vxp.c
index da6f14d..0b36d12 100644
--- a/board/armltd/vexpress/ca9x4_ct_vxp.c
+++ b/board/armltd/vexpress/ca9x4_ct_vxp.c
@@ -226,3 +226,13 @@ void lowlevel_init(void)
 ulong get_board_rev(void){
return readl((u32 *)SYS_ID);
 }
+
+unsigned long long get_ticks(void)
+{
+   return get_timer(0);
+}
+
+ulong get_tbclk (void)
+{
+   return (ulong)CONFIG_SYS_HZ;
+}
-- 
1.7.0.4

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Re: [U-Boot] [PATCH] sh: i2c: Add support I2C controller of SH7734

2012-02-22 Thread Mike Frysinger 
On Wednesday 22 February 2012 08:53:50 Marek Vasut wrote:
  On Tuesday 21 February 2012 20:13:47 Nobuhiro Iwamatsu wrote:
   --- /dev/null
   +++ b/drivers/i2c/sh_sh7734_i2c.c
   
   +#if DEBUG
   +static void sh_i2c_dump_reg(struct sh_i2c *base)
   +{
   + printf(iccr1 : %02X\n, readb(base-iccr1));
   + printf(iccr2 : %02X\n, readb(base-iccr2));
   + printf(icmr  : %02X\n, readb(base-icmr));
   + printf(icier : %02X\n, readb(base-icier));
   + printf(icsr  : %02X\n, readb(base-icsr));
   + printf(sar   : %02X\n, readb(base-sar));
   + printf(icdrt : %02X\n, readb(base-icdrt));
   + printf(icdrr : %02X\n, readb(base-icdrr));
   + printf(nf2cyc: %02X\n, readb(base-nf2cyc));
   +}
   +#endif
  
  if you used debug(), you wouldn't need the DEBUG check
 
 But this puts lower amount of strain on the CPP. It doesn't have to check
 if DEBUG is defined 10 times, but only once ;-) Putting this into one big
 debug() call is also possible btw., though I don't like it.

assuming you're not joking, i'm fairly certain that's now how the CPP engine 
works.  we want to minimize ifdef's and let the compiler to code checking as 
much as possible and do DCE on unused stuff.

   +int i2c_set_bus_num(unsigned int bus)
   +{
   + if ((bus  0) || (bus = CONFIG_SYS_MAX_I2C_BUS)) {
   + printf(Bad bus: %d\n, bus);
   + return -1;
   + }
   +
   + switch (bus) {
   + case 0:
   + base = (void *)CONFIG_SH_I2C_BASE0;
   + break;
   + case 1:
   + base = (void *)CONFIG_SH_I2C_BASE1;
   + break;
   + default:
   + return -1;
   + }
  
  do you need the if() check if you have default here ?
 
 CONFIG_SYS_MAX_I2C_BUS may be different in some obscure case?

unlikely, but you're right.  the code could still be unified though:
if (bus = CONFIG_SYS_MAX_I2C_BUS)
goto case_bad_bus;
switch (bus) {
case 0:
...
case 1:
...
case_bad_bus:
default:
printf(...warning...);
return -1;
}
-mike


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Re: [U-Boot] PR1-Appliance UART Boot Issue

2012-02-22 Thread Mike Frysinger 
On Wednesday 22 February 2012 01:16:54 Amber and Sarosh wrote:
 In these setps, the u-boot  files that are accesed successfully in both
 UART and SPI boot modes are the ones compiled for BF537 STAMP board on the
 terminal emulator. This uboot is unable to boot a uImage compiled for
 PR1-Appliance. The ones  we compiled for PR1 Appliance dont show up on the
 terminal emulator in both modes, and same is the result for the
 precompiled u-boot for PR1 Appliance. Can anyone please guide us, what to
 do in order to access u-boot of PR1-Appliance and to boot the image? Let
 us know if you require any other details.We shall be very thankful!

what source tree are you compiling exactly ?
-mike


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Re: [U-Boot] [PATCH 1/2] openrisc/bitops: add hweightX defines

2012-02-22 Thread Stefan Kristiansson 
On Wed, Feb 22, 2012 at 07:10:09PM +0200, Stefan Kristiansson wrote:
 Signed-off-by: Stefan Kristiansson stefan.kristians...@saunalahti.fi
 ---
  arch/openrisc/include/asm/bitops.h |4 
  1 files changed, 4 insertions(+), 0 deletions(-)
 
 diff --git a/arch/openrisc/include/asm/bitops.h 
 b/arch/openrisc/include/asm/bitops.h
 index c001a5d..c76a409 100644
 --- a/arch/openrisc/include/asm/bitops.h
 +++ b/arch/openrisc/include/asm/bitops.h
 @@ -25,4 +25,8 @@
  #define PLATFORM_FFS
  #include asm/bitops/ffs.h
  
 +#define hweight32(x) generic_hweight32(x)
 +#define hweight16(x) generic_hweight16(x)
 +#define hweight8(x) generic_hweight8(x)
 +
  #endif /* __ASM_GENERIC_BITOPS_H */
 -- 
 1.7.5.4
 

Sorry, screwed up when I format-patched this,
there is no part 2 to it.

Stefan
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[U-Boot] [PATCH 1/2] openrisc/bitops: add hweightX defines

2012-02-22 Thread Stefan Kristiansson 
Signed-off-by: Stefan Kristiansson stefan.kristians...@saunalahti.fi
---
 arch/openrisc/include/asm/bitops.h |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/openrisc/include/asm/bitops.h 
b/arch/openrisc/include/asm/bitops.h
index c001a5d..c76a409 100644
--- a/arch/openrisc/include/asm/bitops.h
+++ b/arch/openrisc/include/asm/bitops.h
@@ -25,4 +25,8 @@
 #define PLATFORM_FFS
 #include asm/bitops/ffs.h
 
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
 #endif /* __ASM_GENERIC_BITOPS_H */
-- 
1.7.5.4

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[U-Boot] [PATCH] openrisc: implement get_ticks and get_tbclk

2012-02-22 Thread Stefan Kristiansson 
Signed-off-by: Stefan Kristiansson stefan.kristians...@saunalahti.fi
---
 arch/openrisc/lib/timer.c |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/openrisc/lib/timer.c b/arch/openrisc/lib/timer.c
index 4e92a31..89e644b 100644
--- a/arch/openrisc/lib/timer.c
+++ b/arch/openrisc/lib/timer.c
@@ -86,6 +86,16 @@ void set_timer(ulong t)
timestamp = t;
 }
 
+unsigned long long get_ticks(void)
+{
+   return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+   return CONFIG_SYS_HZ;
+}
+
 void __udelay(ulong usec)
 {
ulong elapsed = 0;
-- 
1.7.5.4

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Re: [U-Boot] PR1-Appliance UART Boot Issue

2012-02-22 Thread Amber and Sarosh 

We are compiling from these sources:
https://switchfin.svn.sourceforge.net/svnroot/switchfin/switchfin/trunkhttps://switchfin.svn.sourceforge.net/svnroot/switchfin/switchfin/tags/br4-ui2.15
 
https://blackfin.uclinux.org/gf/download/frsrelease/360/3630/u-boot-trunk-svn.src.tar.bz2https://blackfin.uclinux.org/gf/download/frsrelease/533/9651/u-boot-2011.11-2011R1-RC5.tar.bz2
Regards,Amber  Sarosh

 From: vap...@gentoo.org
 To: u-boot@lists.denx.de; d...@switchfin.org
 Subject: Re: [U-Boot] PR1-Appliance UART Boot Issue
 Date: Wed, 22 Feb 2012 11:42:03 -0500
 CC: amber_sar...@hotmail.com
 
 On Wednesday 22 February 2012 01:16:54 Amber and Sarosh wrote:
  In these setps, the u-boot  files that are accesed successfully in both
  UART and SPI boot modes are the ones compiled for BF537 STAMP board on the
  terminal emulator. This uboot is unable to boot a uImage compiled for
  PR1-Appliance. The ones  we compiled for PR1 Appliance dont show up on the
  terminal emulator in both modes, and same is the result for the
  precompiled u-boot for PR1 Appliance. Can anyone please guide us, what to
  do in order to access u-boot of PR1-Appliance and to boot the image? Let
  us know if you require any other details.We shall be very thankful!
 
 what source tree are you compiling exactly ?
 -mike
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Re: [U-Boot] [PATCH] microblaze: fix build failure due to undefined reference to `get_ticks'

2012-02-22 Thread Stephan Linz 
Am Mittwoch, den 22.02.2012, 10:52 +0100 schrieb Michal Simek: 
 Stephan Linz wrote:
  after http://patchwork.ozlabs.org/patch/136415/ was applied.
  The Microblaze generic build fails with below error
 
 Please sure patch subject + sha1 sum instead of link to system
 which doesn't need to work in future. Git reference will work.

OK, I'll resend the patch. Can I already add your ACK ?


-- 
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Stephan Linz
__
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[U-Boot] [PATCH] microblaze: avoid interrupt race conditions

2012-02-22 Thread Stephan Linz 
The interrupt acknowledge action have to run after the
registered interrupt handler. So we have a chance to
bear out the corresponding interrupt request in the
corresponding controller hardware.

With this reordering, we optain a proper interrupt
handling for level triggered interrupt sources -- for
example the new axi_timer v1.02.a introduced in ISE 13.2.

Signed-off-by: Stephan Linz l...@li-pro.net
Acked-by: Michal Simek mon...@monstr.eu
---
 arch/microblaze/cpu/interrupts.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index 5a13211..e7ca859 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -155,8 +155,6 @@ void interrupt_handler (void)
 #endif
struct irq_action *act = vecs + irqs;
 
-   intc-iar = mask  irqs;
-
 #ifdef DEBUG_INT
printf
(Jumping to interrupt handler rutine addr %x,count %x,arg %x\n,
@@ -165,6 +163,8 @@ void interrupt_handler (void)
act-handler (act-arg);
act-count++;
 
+   intc-iar = mask  irqs;
+
 #ifdef DEBUG_INT
printf (Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n, intc-isr,
intc-ier, intc-iar, intc-mer);
-- 
1.7.0.4

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Re: [U-Boot] [PATCH] microblaze: fix build failure due to undefined reference to `get_ticks'

2012-02-22 Thread Michal Šimek 


Stephan Linz l...@li-pro.net napsal(a):

Am Mittwoch, den 22.02.2012, 10:52 +0100 schrieb Michal Simek: 
 Stephan Linz wrote:
  after http://patchwork.ozlabs.org/patch/136415/ was applied.
  The Microblaze generic build fails with below error
 
 Please sure patch subject + sha1 sum instead of link to system
 which doesn't need to work in future. Git reference will work.

OK, I'll resend the patch. Can I already add your ACK ?

Yes, you can.

Michal

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[U-Boot] [PATCH] microblaze: fix build failure due to undefined reference to `get_ticks'

2012-02-22 Thread Stephan Linz 
after commit 9c34831 was applied. The Microblaze generic build
fails with error below:

common/libcommon.o: In function `cread_line':
/devel/u-boot/common/main.c:717: undefined reference to `get_ticks'
/devel/u-boot/common/main.c:717: undefined reference to `get_tbclk'
/devel/u-boot/common/main.c:720: undefined reference to `get_ticks'

Signed-off-by: Stephan Linz l...@li-pro.net
Acked-by: Michal Simek mon...@monstr.eu
---
 arch/microblaze/cpu/timer.c |   18 ++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c
index a167755..1952804 100644
--- a/arch/microblaze/cpu/timer.c
+++ b/arch/microblaze/cpu/timer.c
@@ -62,3 +62,21 @@ int timer_init (void)
 }
 #endif
 #endif
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On Microblaze it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+   return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On Microblaze it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+   return CONFIG_SYS_HZ;
+}
-- 
1.7.0.4

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Re: [U-Boot] [PATCH v5] sandbox: gpio: Add basic driver for simulating GPIOs

2012-02-22 Thread Mike Frysinger 
On Wednesday 22 February 2012 00:45:52 Simon Glass wrote:
 On Tue, Feb 21, 2012 at 9:08 PM, Mike Frysinger vap...@gentoo.org wrote:
  let's get your ack-back on this and i'll merge it into my branch.
  only diff from last code is restored assert() to get_gpio_flags().
  -mike
  
  From f67fd9b82ec180d8a227bf036a45eb31e713a5a9 Mon Sep 17 00:00:00 2001
  From: Simon Glass s...@chromium.org
  Date: Wed, 15 Feb 2012 15:51:13 -0800
  Subject: [PATCH v5] sandbox: gpio: Add basic driver for simulating GPIOs
  
  This provides a way of simulating GPIOs by setting values which are seen
  by the normal gpio_get/set_value() calls.
  
  Signed-off-by: Simon Glass s...@chromium.org
  Signed-off-by: Mike Frysinger vap...@gentoo.org
 
 Acked-by: Simon Glass s...@chromium.org

ok, on to command line processing ;)
-mike


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Re: [U-Boot] PR1-Appliance UART Boot Issue

2012-02-22 Thread Mike Frysinger 
On Wednesday 22 February 2012 12:54:22 Amber and Sarosh wrote:
 We are compiling from these sources:
 https://switchfin.svn.sourceforge.net/svnroot/switchfin/switchfin/trunkhttp
 s://switchfin.svn.sourceforge.net/svnroot/switchfin/switchfin/tags/br4-ui2.
 15
 https://blackfin.uclinux.org/gf/download/frsrelease/360/3630/u-boot-trunk-
 svn.src.tar.bz2https://blackfin.uclinux.org/gf/download/frsrelease/533/9651
 /u-boot-2011.11-2011R1-RC5.tar.bz2

well, you'll prob have to wait for feedback from the switchfin guys.  what you 
describe sounds right, and the bf537-stamp boots, so that's good.

off the top of my head, you'll want to make sure you do `make clean` before 
doing `make xxx_config` to be sure all previous objects have been removed.
-mike


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[U-Boot] state of LL TEMAC evaluation

2012-02-22 Thread Stephan Linz 
Hi Michal,

have you ever found time to evaluate the V10 patch set of the refactored
LL TEMAC driver ?

http://lists.denx.de/pipermail/u-boot/2012-January/116807.html

I would like to resubmit the patch set with some corrections:

include/configs/microblaze-generic.h: use XILINX_LLTEMAC_BASEADDR only
for the if-condition of CONFIG_XILINX_LL_TEMAC -- at least we have
defined the first BASEADDR at every time

drivers/net/xilinx_ll_temac.c
board/xilinx/microblaze-generic/xparameters.h
board/xilinx/microblaze-generic/xconversions.h: support only two TEMAC
instances in xilinx_ll_temac_standard_init() -- we can easily expand in
the future


-- 
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Stephan Linz
__
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[U-Boot] [PATCH] microblaze: fix build failure due to undefined reference to `get_ticks'

2012-02-22 Thread Stephan Linz 
after commit common: add possibility for readline_into_buffer
timeout (sha1:9c34831) was applied. The Microblaze generic build
fails with error below:

common/libcommon.o: In function `cread_line':
/devel/u-boot/common/main.c:717: undefined reference to `get_ticks'
/devel/u-boot/common/main.c:717: undefined reference to `get_tbclk'
/devel/u-boot/common/main.c:720: undefined reference to `get_ticks'

Signed-off-by: Stephan Linz l...@li-pro.net
Acked-by: Michal Simek mon...@monstr.eu
---
 arch/microblaze/cpu/timer.c |   18 ++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c
index a167755..1952804 100644
--- a/arch/microblaze/cpu/timer.c
+++ b/arch/microblaze/cpu/timer.c
@@ -62,3 +62,21 @@ int timer_init (void)
 }
 #endif
 #endif
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On Microblaze it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+   return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On Microblaze it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+   return CONFIG_SYS_HZ;
+}
-- 
1.7.0.4

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Re: [U-Boot] [PATCH 1/2] openrisc/bitops: add hweightX defines

2012-02-22 Thread Marek Vasut 
 On Wed, Feb 22, 2012 at 07:10:09PM +0200, Stefan Kristiansson wrote:
  Signed-off-by: Stefan Kristiansson stefan.kristians...@saunalahti.fi
  ---
  
   arch/openrisc/include/asm/bitops.h |4 
   1 files changed, 4 insertions(+), 0 deletions(-)
  
  diff --git a/arch/openrisc/include/asm/bitops.h
  b/arch/openrisc/include/asm/bitops.h index c001a5d..c76a409 100644
  --- a/arch/openrisc/include/asm/bitops.h
  +++ b/arch/openrisc/include/asm/bitops.h
  @@ -25,4 +25,8 @@
  
   #define PLATFORM_FFS
   #include asm/bitops/ffs.h
  
  +#define hweight32(x) generic_hweight32(x)
  +#define hweight16(x) generic_hweight16(x)
  +#define hweight8(x) generic_hweight8(x)
  +
  
   #endif /* __ASM_GENERIC_BITOPS_H */
 
 Sorry, screwed up when I format-patched this,
 there is no part 2 to it.
 
Hey,

looks like get_tbclk() and get_ticks() looks all the same just about 
everywhere. 
What about introducing a weak alias for these functions so in case weird 
platform pops up, these can be overridden.

M
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Re: [U-Boot] [PATCH 1/2] openrisc/bitops: add hweightX defines

2012-02-22 Thread Mike Frysinger 
On Wednesday 22 February 2012 17:15:50 Marek Vasut wrote:
 looks like get_tbclk() and get_ticks() looks all the same just about
 everywhere. What about introducing a weak alias for these functions so in
 case weird platform pops up, these can be overridden.

the unified timer core that Graeme/Simon were doing takes care of that 
implicitly
-mike


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Re: [U-Boot] [PATCH 1/2] openrisc/bitops: add hweightX defines

2012-02-22 Thread Marek Vasut 
 On Wednesday 22 February 2012 17:15:50 Marek Vasut wrote:
  looks like get_tbclk() and get_ticks() looks all the same just about
  everywhere. What about introducing a weak alias for these functions so in
  case weird platform pops up, these can be overridden.
 
 the unified timer core that Graeme/Simon were doing takes care of that
 implicitly

Unified timer core?

M
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Re: [U-Boot] [PATCH 1/2] openrisc/bitops: add hweightX defines

2012-02-22 Thread Graeme Russ 
Ho Marek,

On Thu, Feb 23, 2012 at 10:24 AM, Marek Vasut marek.va...@gmail.com wrote:
 On Wednesday 22 February 2012 17:15:50 Marek Vasut wrote:
  looks like get_tbclk() and get_ticks() looks all the same just about
  everywhere. What about introducing a weak alias for these functions so in
  case weird platform pops up, these can be overridden.

 the unified timer core that Graeme/Simon were doing takes care of that
 implicitly

 Unified timer core?

I don't know what this has to do with openrisc/bitops but a while ago there
was a discussion regarding the implementation of new timer API. I did some
initial tidy-up work but we kind of got stuck on the finer details. It
still in my todo list, but several other items have taken priority

Regards,

Graeme
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Re: [U-Boot] [PATCH 2/2] nios2: implement get_ticks and get_tbclk

2012-02-22 Thread Thomas Chou 

On 02/20/2012 03:34 PM, Alex Hornung wrote:

  * Copy over Blackfin's get_ticks and get_tbclk - they work just fine on
Nios2.

Signed-off-by: Alex Hornunga...@alexhornung.com
---
  arch/nios2/cpu/interrupts.c |   22 ++
  1 files changed, 22 insertions(+), 0 deletions(-)


Dear Alex,

Applied. Thanks.

Best regards,
Thomas
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Re: [U-Boot] PR1-Appliance UART Boot Issue

2012-02-22 Thread Amber and Sarosh 

We did that too.. Even if its a compilation error, the precompiled u-boot for 
PR1 Appliance should have worked atleast, but it does not.

 From: vap...@gentoo.org
 To: amber_sar...@hotmail.com
 Subject: Re: [U-Boot] PR1-Appliance UART Boot Issue
 Date: Wed, 22 Feb 2012 13:46:18 -0500
 CC: u-boot@lists.denx.de; d...@switchfin.org
 
 On Wednesday 22 February 2012 12:54:22 Amber and Sarosh wrote:
  We are compiling from these sources:
  https://switchfin.svn.sourceforge.net/svnroot/switchfin/switchfin/trunkhttp
  s://switchfin.svn.sourceforge.net/svnroot/switchfin/switchfin/tags/br4-ui2.
  15
  https://blackfin.uclinux.org/gf/download/frsrelease/360/3630/u-boot-trunk-
  svn.src.tar.bz2https://blackfin.uclinux.org/gf/download/frsrelease/533/9651
  /u-boot-2011.11-2011R1-RC5.tar.bz2
 
 well, you'll prob have to wait for feedback from the switchfin guys.  what 
 you 
 describe sounds right, and the bf537-stamp boots, so that's good.
 
 off the top of my head, you'll want to make sure you do `make clean` before 
 doing `make xxx_config` to be sure all previous objects have been removed.
 -mike
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