Re: [U-Boot] [RFC] arm926ejs, at91: add common phy_reset function
Hi Heiko, On 11/13/2013 01:04 PM, Heiko Schocher wrote: Hello Bo, Am 13.11.2013 02:35, schrieb Bo Shen: Hi Heiko, On 11/12/2013 09:50 PM, Heiko Schocher wrote: Hello Andreas, Am 12.11.2013 13:56, schrieb Andreas Bießmann: Hello Heiko, On 11/12/2013 11:21 AM, Heiko Schocher wrote: add common phy reset code into a common function. Signed-off-by: Heiko Schocherh...@denx.de Cc: Andreas Bießmannandreas.de...@googlemail.com Cc: Bo Shenvoice.s...@atmel.com Cc: Jens Scharsige...@bus-elektronik.de Cc: Sergey Lapinsla...@ossfans.org Cc: Stelian Popstel...@popies.net Cc: Albin Tonnerrealbin.tonne...@free-electrons.com Cc: Eric Benarde...@eukrea.com Cc: Markus Hubigmhu...@imko.de --- Patch based on the spl patchset from Bo Shen (as I want to collect this function in at91-common directory), see: http://lists.denx.de/pipermail/u-boot/2013-November/166272.html (reworked this against newest Kconfig Makefile changes ... @Bo: Do you plan an update for this patchset for the Kconfig changes? @Bo: I'll review the patches also these days. After Andreas finish reviewing the code, I will update this patchset for the Kconfig changes if needed. Great, so I wait for your update, before I sent my updated patch, thanks! Perfect! Maybe my change in arch/arm/cpu/at91-common/Makefile could be done better... Do we have a common define for all this variants? I think not, but how about defining a new one? I am fine with this too... --- arch/arm/cpu/Makefile | 1 + arch/arm/cpu/at91-common/Makefile | 5 +++ arch/arm/cpu/at91-common/phy.c | 48 + arch/arm/include/asm/arch-at91/at91_common.h | 1 + board/BuS/vl_ma2sc/vl_ma2sc.c | 18 ++ board/afeb9260/afeb9260.c | 18 +- board/atmel/at91sam9260ek/at91sam9260ek.c | 19 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 19 ++ board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 19 +- board/bluewater/snapper9260/snapper9260.c | 16 + board/calao/sbc35_a9g20/sbc35_a9g20.c | 19 +- board/eukrea/cpu9260/cpu9260.c | 18 +- board/taskit/stamp9g20/stamp9g20.c | 31 +--- spl/Makefile | 4 --- 14 files changed, 66 insertions(+), 170 deletions(-) create mode 100644 arch/arm/cpu/at91-common/phy.c diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index fd0da53..886347d 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_TEGRA) += $(SOC)-common/ obj-$(CONFIG_TEGRA) += tegra-common/ +obj-$(CONFIG_AT91FAMILY) += at91-common/ snip diff --git a/spl/Makefile b/spl/Makefile index 736c6ca..cbd3d27 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -111,10 +111,6 @@ ifneq ($(CONFIG_MX23)$(CONFIG_MX35),) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif -ifeq ($(SOC),at91) -LIBS-y += arch/$(ARCH)/cpu/at91-common/libat91-common.o -endif - That should not be removed here. See my change in arch/arm/cpu/Makefile With this change, this in the spl/Makefile is not needed ... I did this, because arch/arm/cpu/at91-common/ contains not only spl code. But maybe this should be changed in the spl patchset from bo? I am not fully got your means. what should I change? Could you add to your patchset the following change? OK. I will add this after reviewing. Thanks. diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index fd0da53..886347d 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_TEGRA) += $(SOC)-common/ obj-$(CONFIG_TEGRA) += tegra-common/ +obj-$(CONFIG_AT91FAMILY) += at91-common/ diff --git a/spl/Makefile b/spl/Makefile index 736c6ca..cbd3d27 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -111,10 +111,6 @@ ifneq ($(CONFIG_MX23)$(CONFIG_MX35),) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif -ifeq ($(SOC),at91) -LIBS-y += arch/$(ARCH)/cpu/at91-common/libat91-common.o -endif - bye, Heiko Best Regards, Bo Shen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH V2] imx: add multi-BOM README
Hi Eric, On 09/11/2013 23:51, Eric Nelson wrote: Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com --- V2 replaces the words arch and architecture, since we're talking about processor variations within a family, not different processor architectures. doc/README.imx6-multi-bom | 241 ++ 1 file changed, 241 insertions(+) create mode 100644 doc/README.imx6-multi-bom We have a quite empty README.imx6. I think you can add your stuff to that file instead of a new one. diff --git a/doc/README.imx6-multi-bom b/doc/README.imx6-multi-bom new file mode 100644 index 000..be66e0a --- /dev/null +++ b/doc/README.imx6-multi-bom @@ -0,0 +1,241 @@ +Supporting multiple bills of material on Freescale i.MX6 boards. + +This file describes how to support multiple variants of the iMX6 CPU +(i.MX6DQ and i.MX6DLS) in a single U-Boot image. + +Because memory configuration differs between the various CPU +models, auto-configuration of DDR is also covered. + +1. BACKGROUND +- +The Freescale i.MX6 processor family contains four variants which are pin +compatible. Refer to http://freescale.com/imx6series for details and +reference manuals, but the highlights from a U-Boot perspective are +as follows: + +i.MX6Q - Quad core, 64-bit DDR1066, 256K OCRAM +i.MX6D - Dual core, 64-bit DDR1066, 256K OCRAM +i.MX6DL - Dual core, 64-bit DDR800, 128K OCRAM +i.MX6S - Single core, 32-bit DDR800, 128K OCRAM + +These processors are also largely register-compatible, but not completely. +In particular, the IOMUX registers for common functions are in different +locations and have different selector values. + +The register addresses and values are consistent between the first two +processors in the list above (i.MX6DQ processors) and the second two +(i.MX6DLS for Dual-Lite/Solo). + +The i.MX6SL (Solo-Lite) processor is not pin compatible, so this document +does not describe support for that variant. + +Because of the pin-compatibility, a number of manufacturers produce +identical boards with BOM options for two or more of the processors. + +Similarly, identical boards are offered in a number of different memory +layouts, whether by partially populating the DRAM sockets or by populating +them with different densities of DDR. + +By following the conventions described in this document, a board can +support each of these options in a single boot image, and decrease the +overhead for managing images. + +Note that adding multi-BOM support will add to the size of the bootable +image and slow the boot process slightly. If size and speed are critical, +a configuration-specific build can be produced that removes this overhead. + +2. BOOT FLOW + +The boot process for i.MX6 processors begins with execution of a first +level loader in the processor's internal ROM. This loader samples boot +pins and on-chip fuses to determine the source of the secondary boot +image. + +The boot image itself consists of a header (the DCD) If we check exactly the terms, DCD is only a part of a whole header. which describes the +load address and payload (the U-Boot firmware). It also contains a set of +register/value pairs used to initialize the CPU prior to execution of +U-Boot. + +The boot image is produced in a final stage of the build process by the +imximage tool by processing a configuration (.cfg) file. This description is quite a summary of the Boot Chapter in i.MX6 manual. This is also true for other i.MXes (even older MX3 when booting in internal mode). Maybe it is enough to make a reference to the manual instead of explaining everything again. + +In a single-BOM image, the DCD can include DDR memory initialization +values and the load address may be DDR directly. + +In order to support all of the processors in this family, the DCD must +contain a load address for the i.MX6's internal RAM (OCRAM) because the +DDR memory speed (at least) will be dependent on the processor variant. +Thankfully, the DCD items needed to load this binary are consistent +between all of the processors. + +For this reason, support for SPL (secondary program loader) is a requirement +in order to support multiple BOMS in the same image. The SPL image will +determine the processor variant and memory organization, configure the +IOMUX controller and DDR appropriately, and load either a full version of +U-Boot or an O/S. + +3. DDR configuration + + +The DDR configuration data for single BOM boards is defined +completely within .cfg files in the various board directories. + +As of this writing, most boards use the structure defined in the directory +board/boundary/nitrogen6x/ which separates the pieces of DCD data +according to function, with this general form: We should not put the path of the files into the README, as they could be moved,
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
Hi Vaibhav,
On Wednesday 06 November 2013 07:24 PM, Lokesh Vutla wrote:
On Wednesday 06 November 2013 06:32 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvu...@ti.com wrote:
GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
- Enable VTT regulator
- Configure VTP
- Configure DDR IO settings
- Disable initialization and refreshes until EMIF registers are programmed.
- Program Timing registers
- Program leveling registers
- Program PHY control and Temp alert and ZQ config registers.
Temp alert? Is that really relevant here?
Yes, Need to configure all the emif registers before accessing SDRAM.
- Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/emif4d5.c |8 ++-
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++-
board/ti/am43xx/board.c | 89
++-
3 files changed, 101 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c
b/arch/arm/cpu/armv7/am33xx/emif4d5.c
index eea1fa3..8bac0f2 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4d5.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c
@@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
void do_sdram_init(const struct ctrl_ioregs *ioregs,
const struct emif_regs *regs,
- const u32 *ext_phy_ctrl_const_regs)
+ const u32 *ext_phy_ctrl_const_regs, u32 sdram_type)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
@@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs,
writel(regs-sdram_config, emif-emif_sdram_config);
writel(regs-ref_ctrl, emif-emif_sdram_ref_ctrl);
- configure_mr(EMIF1_BASE, 0);
- configure_mr(EMIF1_BASE, 1);
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) {
+ configure_mr(EMIF1_BASE, 0);
+ configure_mr(EMIF1_BASE, 1);
+ }
}
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 1880415..796e9df 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -134,6 +134,14 @@
#define LPDDR2_DATA2_IOCTRL_VALUE 0x2294
#define LPDDR2_DATA3_IOCTRL_VALUE 0x2294
+#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x
+#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x
+#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
+#define DDR3_DATA0_IOCTRL_VALUE 0x84
+#define DDR3_DATA1_IOCTRL_VALUE 0x84
+#define DDR3_DATA2_IOCTRL_VALUE 0x84
+#define DDR3_DATA3_IOCTRL_VALUE 0x84
+
/**
* Configure DMM
*/
@@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
void do_sdram_init(const struct ctrl_ioregs *ioregs,
const struct emif_regs *emif_regs,
- const u32 *ext_phy_ctrl_const_regs);
+ const u32 *ext_phy_ctrl_const_regs, u32 ddr_type);
#endif /* _DDR_DEFS_H */
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 83d184d..a943b45 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -140,6 +140,57 @@ const u32
ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x08102040
};
+const struct ctrl_ioregs ioregs_ddr3 = {
+ .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
+ .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+ .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+ .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .emif_sdram_config_ext = 0x0043,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x0C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x0005,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1= 0x0E084007,
+ .emif_ddr_ext_phy_ctrl_1= 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2= 0x00400040,
+ .emif_ddr_ext_phy_ctrl_3= 0x00400040,
+ .emif_ddr_ext_phy_ctrl_4= 0x00400040,
+ .emif_ddr_ext_phy_ctrl_5= 0x00400040
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x00400040,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
Re: [U-Boot] [PATCH 2/4] mx6: add structs for mmdc and ddr iomux registers
Hi Tapani,
On 13/11/2013 06:50, Tapani wrote:
Stefano,
I'll reply to this, since including the __attribute__ was my suggestion.
+ u32 res10[25];
+ u32 mpmur0;
+}__attribute__((packed, aligned(4)));
+
I am missing why the packed is needed.
This was discussed before, and I tried to explain it already then.
Short answer: to make a broken design slightly less likely to cause problems.
Long answer: Using structs the way required by u-boot maintainers is invalid
C.
It is a compiler quirk that it happens to work. This is clear from ANSI C89
standard: http://www.lysator.liu.se/c/rat/c5.html#3-5-2-1
However people (like Microsoft famously with Office) kept shooting themselves
in the foot with structure members and padding, this was clarified even
further in the C99 standard (see pt. 1424 in
http://c0x.coding-guidelines.com/6.7.2.1.html )
Meanwhile, the gcc people added a compiler hint, __attribute__((packed)), to
kindly ask the compiler not to add any padding structs. (So you guys certainly
are not the first ones doing this kind of hacks :-).
The specific question should have been: why do we use packed when all
fields in the structure are already u32 ? The compiler does not
introduce padding, at least now : packed will be necessary if there are
16bit or 8 bit registers.
If gcc in the future will generate padding (let's say, all fields will
become 64 bit), this become a general issue and must be globally fixed -
I mean for all structures accessing to internal registers. But using
this only here is not consistent.
While on topic, the aligned(4) is needed because of the packed attribute.
This is clear, but again, if we needed, the fix should go globally.
Currently all structures in u-boot do not use it.
There is a drawback with the gcc __attribute__((packed)). The compiler might
no longer be able to assume any alignment of the members (what if the struct
resides on an odd address?).
In u-boot such as structures are not allocated, but there address is set
in code, such as:
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
of course, if SRC_ADDR is not aligned, it crashes - but this is a bug. I
think (not tested) that if you force the compiler to align the address,
and for example SRC_BASE_ADDR is not correct and set on an odd address,
the compiler will force it to the nearest aligned address, that is
presumably wrong and generates unpredictable results.
To remedy this some compilers create complicated
code for accessing the struct members in a way that no CPU exceptions are
raised, to make the structure accesses work (and some compilers just let the
Bus Errors happen). The __attribute__((aligned(4))) tells the compiler that
it
may assume that the struct will always be aligned on a 4-byte boundary.
But in the way u-boot uses the structures, a crash or CPU exception must
be raised because it signals a bug.
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
Ok - if these structure is to make it available for other components, it
should replace the structure esd_mmdc_regs in cpu.c. We cannot have both.
So would you suggest we add a union inside the structure to differentiate
imx5 and imx6? Or just make the structure imx6s/dl/q specific?
The main point is that I disagree on duplicating code. The same
structure with your patch is defined twice, this cannot be.
The specific register layout is defined into the corresponding
imx-regs.h (./arch/arm/include/asm/arch-mx5/imx-regs.h or
./arch/arm/include/asm/arch-mx6/imx-regs.h). If there is the same
structure (let's say, the same controller with different layout) on
different socs, you have to define the structures in the imx-regs.h for
each SOC that uses that structure.
Best regards,
Stefano Babic
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Re: [U-Boot] [PATCH v1 1/4] udoo: Move and optimize platform register setting.
Hi Giuseppe, On 11/11/2013 18:11, Giuseppe Pagano wrote: Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board. Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com CC: Stefano Babic sba...@denx.de CC: Fabio Estevam fabio.este...@freescale.com --- diff --git a/boards.cfg b/boards.cfg index cec154b..1863f2a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -288,7 +288,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic sba...@denx.de -Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam fabio.este...@freescale.com +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam fabio.este...@freescale.com Fabio's mail address is corrupted by some tool. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/4] udoo: Add ethernet support (FEC + Micrel KSZ9031).
Hi Giuseppe,
On 11/11/2013 18:11, Giuseppe Pagano wrote:
Add Ethernet and networking support on uDoo board (FEC + phy Micrel KSZ9031).
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
ok - remember to increment the version number of the patchset for next
time (this is really V2 instead of V1).
board/udoo/udoo.c | 140
include/configs/udoo.h | 16 ++
include/micrel.h |5 ++
3 files changed, 161 insertions(+)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index e9d6375..ca49ebb 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -9,6 +9,7 @@
#include asm/arch/clock.h
#include asm/arch/imx-regs.h
#include asm/arch/iomux.h
+#include malloc.h
#include asm/arch/mx6-pins.h
#include asm/errno.h
#include asm/gpio.h
@@ -18,6 +19,9 @@
#include asm/arch/crm_regs.h
#include asm/io.h
#include asm/arch/sys_proto.h
+#include micrel.h
+#include miiphy.h
+#include netdev.h
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -58,6 +65,99 @@ static iomux_v3_cfg_t const wdog_pads[] = {
MX6_PAD_EIM_D19__GPIO_3_19,
};
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /*
+ * Bug: Apparently uDoo does not works with Gigabit switches...
+ * Limiting speed to 10/100Mbps, and setting master mode, seems to
+ * be the only way to have a successfull PHY auto negotiation.
+ * How to fix: Understand why Linux kernel do not have this issue.
+ */
Fine. This is ok, but could you also add to the commit message that
Ethernet is currently limited to 10/100Mbps ?
Best regards,
Stefano Babic
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Re: [U-Boot] [PATCH v2] configs: imx: Make CONFIG_SYS_PROMPT uniform across FSL boards
On 01/11/2013 11:12, Fabio Estevam wrote: There is no real benefit in adding the board name into U-boot's prompt, so remove the custom CONFIG_SYS_PROMPT definitions so that the standard = prompt is used across FSL boards. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mxs_gpio: fix the handling in gpio_direction_output()
On 03/11/2013 22:59, Michael Heimpold wrote: Setting the direction and an output value should be done by 1) set the desired output value, 2) switch to output. If this is done in the inverse order, there can be a glitch on the GPIO line. This patch fixes this by using the order as described above. Signed-off-by: Michael Heimpold m...@heimpold.de --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] titanium: Return the error when cpu_eth_init() fails
On 04/11/2013 01:12, Fabio Estevam wrote: From: Fabio Estevam fabio.este...@freescale.com When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] wandboard: Return the error immediately when ipuv3_fb_init() fails
On 04/11/2013 01:03, Fabio Estevam wrote: From: Fabio Estevam fabio.este...@freescale.com If ipuv3_fb_init() fails, we should return the error immediately. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] wandboard: Return the error when cpu_eth_init() fails
On 04/11/2013 01:03, Fabio Estevam wrote: From: Fabio Estevam fabio.este...@freescale.com When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mx6: titanium: Move BSP code to barco board directory
On 04/11/2013 08:35, Stefan Roese wrote: Since the titanium board is not a Freescale board, move its BSP code from the freescale board directory to the newly created barco board directory. Signed-off-by: Stefan Roese s...@denx.de Cc: Peter Korsgaard peter.korsga...@barco.com Cc: Stefano Babic sba...@denx.de --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/5] i.MX6 (DQ/DLS): consolidate mux and pad names
Hi Eric, On 05/11/2013 01:00, Eric Nelson wrote: This patch set consolidates mux and pad declarations for the i.MX6 Dual/Quad and Dual-Lite/Solo processor variants. Patch 1 replaces the mux/pad names with their equivalents from the Linux kernel (from linux-next). This Patch 2 removes a set of completely useless pad declarations Patch 3 adds a number of registers that are defined in the Linux kernel and in the DLS variant, but not in the DQ. Patch 4 removes pad declarations that aren't used and aren't defined in the Linux kernel tree Patch 5 cleans up the whitespace in mx6[q|dl]_pins.h so the IOMUX_PAD() columns line up. Eric, thanks again for the great job. Applied (whole patchset) to u-boot-imx, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114
On Fri, Jun 21, 2013 at 6:20 PM, Stephen Warren swar...@wwwdotorg.org wrote: On 06/21/2013 05:05 AM, Jim Lin wrote: Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards. Changes in v5: - Move changes on fdtdec.h and fdtdec.c to patch 2/3 - Modify PHY type to hsic for USB2 port HSIC is an odd choice; ULPI is much more common. Still, this isn't a big deal; this is simply a default value, so any board that enables USB2 can simply set the property to ulpi if needed. Long time ago but now I am working on a board support for tegra30 which has ASIX-eth on USB2-HSIC and don't get it to work. Checking the code leads me to the question: Is it possible that phy_type = hsic is not handled at all? Andreas ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] trats: usb: Add usb_cable_connected() function
Changes:
- define function usb_cable_connected() in trats board file
which returns 1 if cable is connected and 0 otherwise
- trats.h: add CONFIG_USB_CHECK_CABLE
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
board/samsung/trats/trats.c | 10 ++
include/configs/trats.h |1 +
2 files changed, 11 insertions(+)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 7f61d17..9ed70d3 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -500,6 +500,16 @@ void board_usb_init(void)
debug(USB_udc_probe\n);
s3c_udc_probe(s5pc210_otg_data);
}
+
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
+{
+ struct pmic *muic = pmic_get(MAX8997_MUIC);
+ int cable_connected = muic-chrg-chrg_type(muic);
+
+ return !!cable_connected;
+}
+#endif
#endif
static void pmic_reset(void)
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 24ea06b..7f8009e 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -300,6 +300,7 @@
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW2
+#define CONFIG_USB_CABLE_CHECK
/* LCD */
#define CONFIG_EXYNOS_FB
--
1.7.9.5
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Re: [U-Boot] [PATCH v3 1/6] arm: atmel: sama5d3: correct the ID for DBGU and PIT
Hi Bo, On 11/06/2013 06:29 AM, Bo Shen wrote: As the DBGU and PIT has its own ID on sama5d3 SoC, while not share with SYS ID. So, correct them. Signed-off-by: Bo Shen voice.s...@atmel.com --- no complaints Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] s5p: gpio: change gpio coding method for s5p gpio.
Old s5p gpio coding method returns bad bank address in few cases. Now it is working properly with every gpio part bank and pin and it is easy to extend. Gpio coding mask: 0x00ff - pin number 0x0000 - bank offset 0xff00 - part number Tested on: Goni, Universal, Trats, Trats2. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com CC: Minkyu Kang mk7.k...@samsung.com --- arch/arm/include/asm/arch-exynos/gpio.h | 169 +++--- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 47 +++-- drivers/gpio/s5p_gpio.c | 15 +-- include/configs/s5p_goni.h |4 +- include/configs/s5pc210_universal.h | 12 +-- include/configs/trats.h |8 +- include/configs/trats2.h | 12 +-- 7 files changed, 125 insertions(+), 142 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index a1a7439..b7dc8f5 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -196,117 +196,72 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); /* GPIO pins per bank */ #define GPIO_PER_BANK 8 -#define exynos4_gpio_part1_get_nr(bank, pin) \ - ((unsigned int) (((struct exynos4_gpio_part1 *) \ - EXYNOS4_GPIO_PART1_BASE)-bank)) \ - - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4_gpio_part2_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos4_gpio_part2 *) \ - EXYNOS4_GPIO_PART2_BASE)-bank)) \ - - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) - -#define exynos4x12_gpio_part1_get_nr(bank, pin) \ - ((unsigned int) (((struct exynos4x12_gpio_part1 *) \ - EXYNOS4X12_GPIO_PART1_BASE)-bank)) \ - - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4x12_gpio_part2_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos4x12_gpio_part2 *) \ - EXYNOS4X12_GPIO_PART2_BASE)-bank)) \ - - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) - -#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4x12_gpio_part3_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos4x12_gpio_part3 *) \ - EXYNOS4X12_GPIO_PART3_BASE)-bank)) \ - - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) - -#define exynos5_gpio_part1_get_nr(bank, pin) \ - ((unsigned int) (((struct exynos5_gpio_part1 *) \ - EXYNOS5_GPIO_PART1_BASE)-bank)) \ - - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5_gpio_part2_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos5_gpio_part2 *) \ - EXYNOS5_GPIO_PART2_BASE)-bank)) \ - - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX) - -#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5_gpio_part3_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos5_gpio_part3 *) \ - EXYNOS5_GPIO_PART3_BASE)-bank)) \ - - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) - -static inline unsigned int s5p_gpio_base(int nr) +#define S5P_GPIO_PART_SHIFT(24) +#define S5P_GPIO_PART_MASK (0xff) +#define S5P_GPIO_BANK_SHIFT(8) +#define S5P_GPIO_BANK_MASK (0x) +#define S5P_GPIO_PIN_MASK (0xff) + +#define S5P_GPIO_SET_PART(x) \ + ((x S5P_GPIO_PART_MASK) S5P_GPIO_PART_SHIFT) + +#define S5P_GPIO_GET_PART(x) \ + ((x S5P_GPIO_PART_SHIFT) S5P_GPIO_PART_MASK) + +#define S5P_GPIO_SET_PIN(x) \ + (x S5P_GPIO_PIN_MASK) + +#define EXYNOS4_GPIO_SET_BANK(part,
Re: [U-Boot] [PATCH v3 3/6] arm: atmel: sama5d3: the offset of MULA is 18
Hi Bo, On 11/06/2013 06:29 AM, Bo Shen wrote: The offset of MULA field in PLLA register in sama5d3 is 18, and the length only 7 bits. Signed-off-by: Bo Shen voice.s...@atmel.com --- no complaints Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/6] arm: atmel: sama5d3: early enable PIO peripherals
Hi Bo,
On 11/06/2013 06:29 AM, Bo Shen wrote:
Enable the PIO peripherals early than other peripherals.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
- Correct the clock enable code, the ID can not OR
Changes in v2:
- None
board/atmel/sama5d3xek/sama5d3xek.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c
b/board/atmel/sama5d3xek/sama5d3xek.c
index b0965ef..f245f98 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -158,6 +158,12 @@ void lcd_show_board_info(void)
int board_early_init_f(void)
I'm still not really sure if _board_ init is the right place ... I feel
more like some _arch_ init.
But I would accept it here for getting the first SPL in at91. We need to
rework that whole arch vs. board related init anyways, so we could
change it then (and insisting on that _now_ would definitely break the
release date).
{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+ at91_periph_clk_enable(ATMEL_ID_PIOE);
+
at91_seriald_hw_init();
return 0;
To say it clear, for this patch no change requested.
Best regards
Andreas Bießmann
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[U-Boot] [PATCH 1/9 V7] EXYNOS5: Create a common board file
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.
exynos_init function is provided for platform specific code.
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added check for the compilation of MAX77686 pmic.
Changes in V5:
- Moved board_eth_init and board_mmc_init in case of
device tree support
Changes in V6:
- None.
Changes in V7:
- None
arch/arm/include/asm/arch-exynos/board.h | 17 ++
board/samsung/common/Makefile| 4 +
board/samsung/common/board.c | 405 +++
board/samsung/smdk5250/exynos5-dt.c | 361 +--
board/samsung/smdk5250/smdk5250.c| 182 +-
include/configs/exynos5250-dt.h | 2 +
6 files changed, 435 insertions(+), 536 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/board.h
create mode 100644 board/samsung/common/board.c
diff --git a/arch/arm/include/asm/arch-exynos/board.h
b/arch/arm/include/asm/arch-exynos/board.h
new file mode 100644
index 000..243fb12
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/board.h
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Rajeshwari Shinde rajeshwar...@samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _EXYNOS_BOARD_H
+#define _EXYNOS_BOARD_H
+
+/*
+ * Exynos baord specific changes for
+ * board_init
+ */
+int exynos_init(void);
+
+#endif /* EXYNOS_BOARD_H */
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index 9e48a7b..eab8ab2 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -11,6 +11,10 @@ LIB = $(obj)libsamsung.o
COBJS-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
+ifeq ($(CONFIG_SPL_BUILD),)
+COBJS-$(CONFIG_BOARD_COMMON) += board.o
+endif
+
SRCS:= $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
new file mode 100644
index 000..9ebfc42
--- /dev/null
+++ b/board/samsung/common/board.c
@@ -0,0 +1,405 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * Rajeshwari Shinde rajeshwar...@samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include cros_ec.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include tmu.h
+#include netdev.h
+#include asm/io.h
+#include asm/arch/board.h
+#include asm/arch/cpu.h
+#include asm/arch/dwmmc.h
+#include asm/arch/gpio.h
+#include asm/arch/mmc.h
+#include asm/arch/pinmux.h
+#include asm/arch/power.h
+#include power/pmic.h
+#include asm/arch/sromc.h
+#include power/max77686_pmic.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct local_info {
+ struct cros_ec_dev *cros_ec_dev;/* Pointer to cros_ec device */
+ int cros_ec_err;/* Error for cros_ec, 0 if ok */
+};
+
+static struct local_info local;
+
+#if defined CONFIG_EXYNOS_TMU
+/*
+ * Boot Time Thermal Analysis for SoC temperature threshold breach
+ */
+static void boot_temp_check(void)
+{
+ int temp;
+
+ switch (tmu_monitor(temp)) {
+ case TMU_STATUS_NORMAL:
+ break;
+ /* Status TRIPPED ans WARNING means corresponding threshold breach */
+ case TMU_STATUS_TRIPPED:
+ puts(EXYNOS_TMU: TRIPPING! Device power going down ...\n);
+ set_ps_hold_ctrl();
+ hang();
+ break;
+ case TMU_STATUS_WARNING:
+ puts(EXYNOS_TMU: WARNING! Temperature very high\n);
+ break;
+ /*
+* TMU_STATUS_INIT means something is wrong with temperature sensing
+* and TMU status was changed back from NORMAL to INIT.
+*/
+ case TMU_STATUS_INIT:
+ default:
+ debug(EXYNOS_TMU: Unknown TMU state\n);
+ }
+}
+#endif
+
+int board_init(void)
+{
+ gd-bd-bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#if defined CONFIG_EXYNOS_TMU
+ if (tmu_init(gd-fdt_blob) != TMU_STATUS_NORMAL) {
+ debug(%s: Failed to init TMU\n, __func__);
+ return -1;
+ }
+ boot_temp_check();
+#endif
+
+#ifdef CONFIG_EXYNOS_SPI
+ spi_init();
+#endif
+ return exynos_init();
+}
+
+int dram_init(void)
+{
+ int i;
+ u32 addr;
+
+ for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ gd-ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ }
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ int i;
+ u32 addr, size;
+
+ for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+ gd-bd-bi_dram[i].start = addr;
+ gd-bd-bi_dram[i].size =
[U-Boot] [PATCH 0/9 V7] EXYNOS5420: Add SMDK5420 board support
This patch adds basic board support for SMDK5420 board. These patches are tested for booting fine on EVT1 SMDK5420. Changes in V2: - Corrected a compilation issue for SMDK5420. Changes in V3: - Add patch to support variable size SPL support - Add patch to disable SMU for eMMC. Changes in V4: - Added check for MAX77686 pmic compilation. - Added correct calculation of gpio based addresses. - Rebased on the latest u-boot code. - Removed patches for UART and TZPC changes as they were not needed. - Added flag to disable SMU for eMMC. Changes in V5: - Moved functions board_mmc_init and board_eth_init to common/board.c in case of device tree support. Changes in V6: - Rebased on the latest mainline branch. - Moved the definitions for SMU to arch/arm dwmmc.h Changes in V7: - Removed below patch as it is already merged DWMMC: SMDK5420: Disable SMU for eMMC - Corrected the multi line comments and removal of blank spaces and lines. - Corrected the license. Rajeshwari S Shinde (9): EXYNOS5: Create a common board file Exynos5420: Add base addresses for 5420 Exynos5420: Add clock initialization for 5420 Exynos5420: Add DDR3 initialization for 5420 Exynos5420: Add support for 5420 in pinmux and gpio Exynos5420: Add base patch for SMDK5420 DTS: Add dts support for SMDK5420 Config: Add initial config for SMDK5420 SPL: EXYNOS: Prepare for variable size SPL support arch/arm/cpu/armv7/exynos/clock.c | 258 - arch/arm/cpu/armv7/exynos/clock_init.h | 17 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++- arch/arm/cpu/armv7/exynos/dmc_common.c | 10 +- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 421 +- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 738 +++-- arch/arm/cpu/armv7/exynos/pinmux.c | 243 +++- arch/arm/dts/exynos5.dtsi | 198 +++ arch/arm/dts/exynos5250.dtsi | 196 +-- arch/arm/dts/exynos5420.dtsi | 70 +++ arch/arm/include/asm/arch-exynos/board.h | 17 + arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 494 + arch/arm/include/asm/arch-exynos/cpu.h | 51 +- arch/arm/include/asm/arch-exynos/dmc.h | 123 +++-- arch/arm/include/asm/arch-exynos/gpio.h| 143 - arch/arm/include/asm/arch-exynos/periph.h | 3 + board/samsung/common/Makefile | 4 + board/samsung/common/board.c | 407 ++ board/samsung/dts/exynos5420-smdk5420.dts | 169 ++ board/samsung/smdk5250/exynos5-dt.c| 361 +--- board/samsung/smdk5250/smdk5250.c | 182 +- board/samsung/smdk5420/Makefile| 34 ++ board/samsung/smdk5420/smdk5420.c | 159 ++ board/samsung/smdk5420/smdk5420_spl.c | 52 ++ boards.cfg | 1 + include/configs/arndale.h | 1 + include/configs/exynos5-dt.h | 300 ++ include/configs/exynos5250-dt.h| 316 +-- include/configs/smdk5420.h | 56 ++ spl/Makefile | 7 +- tools/Makefile | 3 +- tools/mkexynosspl.c| 167 -- 33 files changed, 4211 insertions(+), 1343 deletions(-) create mode 100644 arch/arm/dts/exynos5.dtsi create mode 100644 arch/arm/dts/exynos5420.dtsi create mode 100644 arch/arm/include/asm/arch-exynos/board.h create mode 100644 board/samsung/common/board.c create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts create mode 100644 board/samsung/smdk5420/Makefile create mode 100644 board/samsung/smdk5420/smdk5420.c create mode 100644 board/samsung/smdk5420/smdk5420_spl.c create mode 100644 include/configs/exynos5-dt.h create mode 100644 include/configs/smdk5420.h -- 1.7.12.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/9 V7] Exynos5420: Add base addresses for 5420
Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added base address for TZPC.
Changes in V5:
- None
Chnages in V6:
- Rebased on latest samsung mainline branch.
Changes in V7:
- Corrected the comments
arch/arm/include/asm/arch-exynos/cpu.h | 47 +-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index 4b67191..a465e6d 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -88,7 +88,7 @@
#define EXYNOS4X12_DMC_PHY_BASEDEVICE_NOT_AVAILABLE
#define EXYNOS4X12_AUDIOSS_BASEDEVICE_NOT_AVAILABLE
-/* EXYNOS5 Common*/
+/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING0x1
#define EXYNOS5_AUDIOSS_BASE 0x0381
@@ -124,6 +124,44 @@
#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
+/* EXYNOS5420 */
+#define EXYNOS5420_AUDIOSS_BASE0x0381
+#define EXYNOS5420_GPIO_PART5_BASE 0x0386
+#define EXYNOS5420_PRO_ID 0x1000
+#define EXYNOS5420_CLOCK_BASE 0x1001
+#define EXYNOS5420_POWER_BASE 0x1004
+#define EXYNOS5420_SWRESET 0x10040400
+#define EXYNOS5420_SYSREG_BASE 0x1005
+#define EXYNOS5420_TZPC_BASE 0x100E
+#define EXYNOS5420_WATCHDOG_BASE 0x101D
+#define EXYNOS5420_ACE_SFR_BASE0x1083
+#define EXYNOS5420_DMC_PHY_BASE0x10C0
+#define EXYNOS5420_DMC_CTRL_BASE 0x10C2
+#define EXYNOS5420_DMC_TZASC0_BASE 0x10D4
+#define EXYNOS5420_DMC_TZASC1_BASE 0x10D5
+#define EXYNOS5420_USB_HOST_EHCI_BASE 0x1211
+#define EXYNOS5420_MMC_BASE0x1220
+#define EXYNOS5420_SROMC_BASE 0x1225
+#define EXYNOS5420_UART_BASE 0x12C0
+#define EXYNOS5420_I2C_BASE0x12C6
+#define EXYNOS5420_I2C_8910_BASE 0x12E0
+#define EXYNOS5420_SPI_BASE0x12D2
+#define EXYNOS5420_I2S_BASE0x12D6
+#define EXYNOS5420_PWMTIMER_BASE 0x12DD
+#define EXYNOS5420_SPI_ISP_BASE0x131A
+#define EXYNOS5420_GPIO_PART2_BASE 0x1340
+#define EXYNOS5420_GPIO_PART3_BASE 0x1341
+#define EXYNOS5420_GPIO_PART4_BASE 0x1400
+#define EXYNOS5420_GPIO_PART1_BASE 0x1401
+#define EXYNOS5420_MIPI_DSIM_BASE 0x1450
+#define EXYNOS5420_DP_BASE 0x145B
+
+#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_ADC_BASEDEVICE_NOT_AVAILABLE
+#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
+
#ifndef __ASSEMBLY__
#include asm/io.h
/* CPU detection macros */
@@ -157,6 +195,10 @@ static inline void s5p_set_cpu_id(void)
/* Exynos5250 */
s5p_cpu_id = 0x5250;
break;
+ case 0x420:
+ /* Exynos5420 */
+ s5p_cpu_id = 0x5420;
+ break;
}
}
@@ -184,6 +226,7 @@ static inline int __attribute__((no_instrument_function)) \
IS_EXYNOS_TYPE(exynos4210, 0x4210)
IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
+IS_EXYNOS_TYPE(exynos5420, 0x5420)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int __attribute__((no_instrument_function)) \
@@ -194,6 +237,8 @@ static inline unsigned int
__attribute__((no_instrument_function)) \
return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
} else if (cpu_is_exynos5()) { \
+ if (proid_is_exynos5420()) \
+ return EXYNOS5420_##base; \
return EXYNOS5_##base; \
} \
return 0; \
--
1.7.12.4
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 8/9 V7] Config: Add initial config for SMDK5420
Adding initial config for SMDK5420 to build and boot U-Boot over Exynos based SMDK5420. Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com Signed-off-by: Akshay Saraswat aksha...@samsung.com Acked-by: Simon Glass s...@chromium.org --- Changes in V2: - None Changes in V3: - None Changes in V4: - Created a common exynos5-dt.h Changes in V5: - None Changes in V6: - None Chnages in V7: - Corrected the coding style nits. include/configs/exynos5-dt.h| 300 + include/configs/exynos5250-dt.h | 319 +--- include/configs/smdk5420.h | 49 ++ 3 files changed, 357 insertions(+), 311 deletions(-) create mode 100644 include/configs/exynos5-dt.h create mode 100644 include/configs/smdk5420.h diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h new file mode 100644 index 000..2b3714f --- /dev/null +++ b/include/configs/exynos5-dt.h @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ + +#include asm/arch/cpu.h /* get chip and board defs */ + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_EXYNOS_SPL + +/* Enable fdt support for Exynos5250 */ +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* Allow tracing to be enabled */ +#define CONFIG_TRACE +#define CONFIG_CMD_TRACE +#define CONFIG_TRACE_BUFFER_SIZE (16 20) +#define CONFIG_TRACE_EARLY_SIZE(8 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR0x5000 + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_DCACHE_OFF + +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_SHA_HW_ACCEL + +/* input clock of PLL: SMDK5250 has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ2400 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP0x0BAD +#define S5P_CHECK_DIDLE0xBAD0 +#define S5P_CHECK_LPA 0xABAD + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 +#define INFORM2_OFFSET 0x808 +#define INFORM3_OFFSET 0x80c + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 20)) + +/* select serial console configuration */ +#define CONFIG_BAUDRATE115200 +#define EXYNOS5_DEFAULT_UART_OFFSET0x01 +#define CONFIG_SILENT_CONSOLE + +/* Enable keyboard */ +#define CONFIG_CROS_EC /* CROS_EC protocol */ +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ +#define CONFIG_CROS_EC_KEYB/* CROS_EC keyboard input */ +#define CONFIG_CMD_CROS_EC +#define CONFIG_KEYBOARD + +/* Console configuration */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define EXYNOS_DEVICE_SETTINGS \ + stdin=serial,cros-ec-keyb\0 \ + stdout=serial,lcd\0 \ + stderr=serial,lcd\0 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_S5P_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_SUPPORT_EMMC_BOOT + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* PWM */ +#define CONFIG_PWM + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include config_cmd_default.h + +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NET +#define CONFIG_CMD_HASH + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* Thermal Management Unit */ +#define CONFIG_EXYNOS_TMU +#define CONFIG_CMD_DTT +#define CONFIG_TMU_CMD_DTT + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS +#define CONFIG_USB_STORAGE + +/* USB boot mode */ +#define CONFIG_USB_BOOTING +#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 +#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 +#define
[U-Boot] [PATCH 5/9 V7] Exynos5420: Add support for 5420 in pinmux and gpio
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added correct calculation of gpio based addresses.
Changes in V5:
- None
Changes in V6:
- None
Changes in V7:
- Corrected the coding style nits.
arch/arm/cpu/armv7/exynos/pinmux.c| 243 +-
arch/arm/include/asm/arch-exynos/gpio.h | 143 --
arch/arm/include/asm/arch-exynos/periph.h | 3 +
3 files changed, 374 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 8002bce..3090339 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -46,6 +46,42 @@ static void exynos5_uart_config(int peripheral)
}
}
+static void exynos5420_uart_config(int peripheral)
+{
+ struct exynos5420_gpio_part1 *gpio1 =
+ (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank;
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ bank = gpio1-a0;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ bank = gpio1-a0;
+ start = 4;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ bank = gpio1-a1;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ bank = gpio1-a1;
+ start = 4;
+ count = 2;
+ break;
+ }
+
+ for (i = start; i start + count; i++) {
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
+}
+
static int exynos5_mmc_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
@@ -101,6 +137,69 @@ static int exynos5_mmc_config(int peripheral, int flags)
return 0;
}
+static int exynos5420_mmc_config(int peripheral, int flags)
+{
+ struct exynos5420_gpio_part3 *gpio3 =
+ (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
+ struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
+ int i, start = 0;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ bank = gpio3-c0;
+ bank_ext = gpio3-c3;
+ break;
+ case PERIPH_ID_SDMMC1:
+ bank = gpio3-c1;
+ bank_ext = gpio3-d1;
+ start = 4;
+ break;
+ case PERIPH_ID_SDMMC2:
+ bank = gpio3-c2;
+ bank_ext = NULL;
+ break;
+ }
+
+ if ((flags PINMUX_FLAG_8BIT_MODE) !bank_ext) {
+ debug(SDMMC device %d does not support 8bit mode,
+ peripheral);
+ return -1;
+ }
+
+ if (flags PINMUX_FLAG_8BIT_MODE) {
+ for (i = start; i = (start + 3); i++) {
+ s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+ s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ }
+ }
+
+ for (i = 0; i 3; i++) {
+ /*
+* MMC0 is intended to be used for eMMC. The
+* card detect pin is used as a VDDEN signal to
+* power on the eMMC. The 5420 iROM makes
+* this same assumption.
+*/
+ if ((peripheral == PERIPH_ID_SDMMC0) (i == 2)) {
+ s5p_gpio_set_value(bank, i, 1);
+ s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+ } else {
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+
+ for (i = 3; i = 6; i++) {
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+
+ return 0;
+}
+
static void exynos5_sromc_config(int flags)
{
struct exynos5_gpio_part1 *gpio1 =
@@ -216,6 +315,59 @@ static void exynos5_i2c_config(int peripheral, int flags)
}
}
+static void exynos5420_i2c_config(int peripheral)
+{
+ struct exynos5420_gpio_part1 *gpio1 =
+ (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(gpio1-b3, 0,
[U-Boot] [PATCH 4/9 V7] Exynos5420: Add DDR3 initialization for 5420
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- Corrected a compilation issue for SMDK5250.
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None
Changes in V6:
- None
Changes in V7:
- Fixed multi line comment.
arch/arm/cpu/armv7/exynos/dmc_common.c| 10 +-
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 421 +-
arch/arm/include/asm/arch-exynos/cpu.h| 4 +
arch/arm/include/asm/arch-exynos/dmc.h| 123 ++---
4 files changed, 513 insertions(+), 45 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c
b/arch/arm/cpu/armv7/exynos/dmc_common.c
index 53cfe6e..9e432c2 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_common.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
@@ -1,5 +1,5 @@
/*
- * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ * Mem setup common file for different types of DDR present on Exynos boards.
*
* Copyright (C) 2012 Samsung Electronics
*
@@ -152,14 +152,6 @@ void dmc_config_prech(struct mem_timings *mem, struct
exynos5_dmc *dmc)
}
}
-void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
-{
- writel(mem-memconfig, dmc-memconfig0);
- writel(mem-memconfig, dmc-memconfig1);
- writel(DMC_MEMBASECONFIG0_VAL, dmc-membaseconfig0);
- writel(DMC_MEMBASECONFIG1_VAL, dmc-membaseconfig1);
-}
-
void mem_ctrl_init(int reset)
{
struct spl_machine_param *param = spl_get_machine_params();
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 5f5914e..3fab50b 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -1,5 +1,5 @@
/*
- * DDR3 mem setup file for SMDK5250 board based on EXYNOS5
+ * DDR3 mem setup file for board based on EXYNOS5
*
* Copyright (C) 2012 Samsung Electronics
*
@@ -15,8 +15,9 @@
#include exynos5_setup.h
#include clock_init.h
-#define RDLVL_COMPLETE_TIMEOUT 1
+#define TIMEOUT1
+#ifdef CONFIG_EXYNOS5250
static void reset_phy_ctrl(void)
{
struct exynos5_clock *clk =
@@ -108,7 +109,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned
long mem_iv_size,
/* Precharge Configuration */
writel(mem-prechconfig_tp_cnt PRECHCONFIG_TP_CNT_SHIFT,
- dmc-prechconfig);
+ dmc-prechconfig0);
/* Power Down mode Configuration */
writel(mem-dpwrdn_cyc PWRDNCONFIG_DPWRDN_CYC_SHIFT |
@@ -174,7 +175,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned
long mem_iv_size,
writel(val, phy1_ctrl-phy_con1);
writel(CTRL_RDLVL_GATE_ENABLE, dmc-rdlvl_config);
- i = RDLVL_COMPLETE_TIMEOUT;
+ i = TIMEOUT;
while ((readl(dmc-phystatus)
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) i 0) {
@@ -215,3 +216,415 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned
long mem_iv_size,
| (mem-aref_en CONCONTROL_AREF_EN_SHIFT), dmc-concontrol);
return 0;
}
+#endif
+
+#ifdef CONFIG_EXYNOS5420
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+ int reset)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
+ struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
+ struct exynos5_dmc *drex0, *drex1;
+ struct exynos5_tzasc *tzasc0, *tzasc1;
+ uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
+ int chip;
+ int i;
+
+ phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
+ phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
+ + DMC_OFFSET);
+ drex0 = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
+ drex1 = (struct exynos5_dmc *)(samsung_get_base_dmc_ctrl()
+ + DMC_OFFSET);
+ tzasc0 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC0_BASE;
+ tzasc1 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC1_BASE;
+
+ /* Enable PAUSE for DREX */
+ setbits_le32(clk-pause, ENABLE_BIT);
+
+ /* Enable BYPASS mode */
+ setbits_le32(clk-bpll_con1, BYPASS_EN);
+
+ writel(MUX_BPLL_SEL_FOUTBPLL, clk-src_cdrex);
+ do {
+ val = readl(clk-mux_stat_cdrex);
+ val = BPLL_SEL_MASK;
+ } while (val != FOUTBPLL);
+
+ clrbits_le32(clk-bpll_con1, BYPASS_EN);
+
+ /* Specify the DDR memory type as DDR3 */
+ val = readl(phy0_ctrl-phy_con0);
+ val =
[U-Boot] [PATCH 9/9 V7] SPL: EXYNOS: Prepare for variable size SPL support
When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.
The enhancements include
- adding a command line option, '--vs' to indicate the need for the
variable size encapsulation
- padding the fixed size encapsulated blob with 0xff instead of random
memory contents
- do not silently truncate the input file, report error instead
- no need to explicitly closing files/freeing memory, this all happens
on exit; removing cleanups it makes code clearer
- profuse commenting
- modify Makefile to allow enabling the new feature per board
Signed-off-by: Vadim Bendebury vben...@chromium.org
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Created a common exynos5-dt.h
Changes in V5:
- None
Changes in V6:
- None.
Changes in V7:
- None.
include/configs/smdk5420.h | 7 ++
spl/Makefile | 7 +-
tools/mkexynosspl.c| 167 +
3 files changed, 137 insertions(+), 44 deletions(-)
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index e580049..447f8e5 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -19,6 +19,8 @@
#define CONFIG_ARCH_DEVICE_TREEexynos5420
+#define CONFIG_VAR_SIZE_SPL
+
#define CONFIG_SYS_SDRAM_BASE 0x2000
#define CONFIG_SYS_TEXT_BASE 0x23E0
@@ -31,7 +33,12 @@
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
+#ifdef CONFIG_VAR_SIZE_SPL
+#define CONFIG_SPL_TEXT_BASE 0x02024410
+#else
#define CONFIG_SPL_TEXT_BASE 0x02024400
+#endif
+
#define CONFIG_BOOTCOMMAND mmc read 20007000 451 2000; bootm 20007000
#define CONFIG_SYS_PROMPT SMDK5420 #
diff --git a/spl/Makefile b/spl/Makefile
index b366ac2..d5f6ae8 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -184,8 +184,13 @@ endif
all: $(ALL-y)
ifdef CONFIG_SAMSUNG
+ifdef CONFIG_VAR_SIZE_SPL
+VAR_SIZE_PARAM = --vs
+else
+VAR_SIZE_PARAM =
+endif
$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
- $(OBJTREE)/tools/mk$(BOARD)spl \
+ $(OBJTREE)/tools/mk$(BOARD)spl $(VAR_SIZE_PARAM) \
$(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin
endif
diff --git a/tools/mkexynosspl.c b/tools/mkexynosspl.c
index ef685b7..32b786c 100644
--- a/tools/mkexynosspl.c
+++ b/tools/mkexynosspl.c
@@ -14,93 +14,174 @@
#include compiler.h
#define CHECKSUM_OFFSET(14*1024-4)
-#define BUFSIZE(14*1024)
#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \
| S_IWGRP | S_IROTH | S_IWOTH)
/*
-* Requirement:
-* IROM code reads first 14K bytes from boot device.
-* It then calculates the checksum of 14K-4 bytes and compare with data at
-* 14K-4 offset.
-*
-* This function takes two filenames:
-* IN u-boot-spl.bin and
-* OUT $(BOARD)-spl.bin as filenames.
-* It reads the u-boot-spl.bin in 16K buffer.
-* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
-* It writes the buffer to $(BOARD)-spl.bin file.
-*/
+ * Requirement for the fixed size SPL header:
+ * IROM code reads first (CHECKSUM_OFFSET + 4) bytes from boot device. It then
+ * calculates the checksum of CHECKSUM_OFFSET bytes and compares with data at
+ * CHECKSUM_OFFSET location.
+ *
+ * Requirement for the variable size SPL header:
+
+ * IROM code reads the below header to find out the size of the blob (total
+ * size, header size included) and its checksum. Then it reads the rest of the
+ * blob [i.e size - sizeof(struct var_size_header) bytes], calculates the
+ * checksum and compares it with value read from the header.
+ */
+struct var_size_header {
+ uint32_t spl_size;
+ uint32_t spl_checksum;
+ uint32_t reserved[2];
+};
+
+static const char *prog_name;
+
+static void write_to_file(int ofd, void *buffer, int size)
+{
+ if (write(ofd, buffer, size) == size)
+ return;
+
+ fprintf(stderr, %s: Failed to write to output file: %s\n,
+ prog_name, strerror(errno));
+ exit(EXIT_FAILURE);
+}
+/*
+ * The argv is expected to include one optional parameter and two filenames:
+ * [--vs] IN OUT
+ *
+ * --vs - turns on the variable size SPL mode
+ * IN - the u-boot SPL binary, usually u-boot-spl.bin
+ * OUT - the prepared SPL blob, usually ${BOARD}-spl.bin
+ *
+ * This utility first reads the u-boot-spl.bin into a buffer. In case of
+ * fixed size SPL the buffer size is exactly CHECKSUM_OFFSET (such that
+ * smaller u-boot-spl.bin gets padded with 0xff bytes, the larger than limit
+ * u-boot-spl.bin causes an
[U-Boot] [PATCH 7/9 V7] DTS: Add dts support for SMDK5420
This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added /include/ exynos5420.dtsi
Changes in V5:
- None
Changes in V6:
- None
Changes in V7:
- Corrected the license.
arch/arm/dts/exynos5.dtsi | 198 ++
arch/arm/dts/exynos5250.dtsi | 196 +
arch/arm/dts/exynos5420.dtsi | 70 +++
board/samsung/dts/exynos5420-smdk5420.dts | 169 +
4 files changed, 441 insertions(+), 192 deletions(-)
create mode 100644 arch/arm/dts/exynos5.dtsi
create mode 100644 arch/arm/dts/exynos5420.dtsi
create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
new file mode 100644
index 000..f8c8741
--- /dev/null
+++ b/arch/arm/dts/exynos5.dtsi
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2013 The Chromium OS Authors
+ * SAMSUNG EXYNOS5 SoC device tree source
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/include/ skeleton.dtsi
+
+/ {
+ compatible = samsung,exynos5;
+
+ sromc@1225 {
+ compatible = samsung,exynos-sromc;
+ reg = 0x1225 0x20;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ i2c@12c6 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,s3c2440-i2c;
+ reg = 0x12C6 0x100;
+ interrupts = 0 56 0;
+ };
+
+ i2c@12c7 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,s3c2440-i2c;
+ reg = 0x12C7 0x100;
+ interrupts = 0 57 0;
+ };
+
+ i2c@12c8 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,s3c2440-i2c;
+ reg = 0x12C8 0x100;
+ interrupts = 0 58 0;
+ };
+
+ i2c@12c9 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,s3c2440-i2c;
+ reg = 0x12C9 0x100;
+ interrupts = 0 59 0;
+ };
+
+ spi@12d2 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,exynos-spi;
+ reg = 0x12d2 0x30;
+ interrupts = 0 68 0;
+ };
+
+ spi@12d3 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,exynos-spi;
+ reg = 0x12d3 0x30;
+ interrupts = 0 69 0;
+ };
+
+ spi@12d4 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,exynos-spi;
+ reg = 0x12d4 0x30;
+ clock-frequency = 5000;
+ interrupts = 0 70 0;
+};
+
+ spi@131a {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,exynos-spi;
+ reg = 0x131a 0x30;
+ interrupts = 0 129 0;
+ };
+
+ spi@131b {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,exynos-spi;
+ reg = 0x131b 0x30;
+ interrupts = 0 130 0;
+ };
+
+ ehci@1211 {
+ compatible = samsung,exynos-ehci;
+ reg = 0x1211 0x100;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ phy {
+ compatible = samsung,exynos-usb-phy;
+ reg = 0x1213 0x100;
+ };
+ };
+
+ tmu@1006 {
+ compatible = samsung,exynos-tmu;
+ reg = 0x1006 0x1;
+ };
+
+ fimd@1440 {
+ compatible = samsung,exynos-fimd;
+ reg = 0x1440 0x1;
+ #address-cells = 1;
+ #size-cells = 1;
+ };
+
+ dp@145b {
+ compatible = samsung,exynos5-dp;
+ reg = 0x145b 0x1000;
+ #address-cells = 1;
+ #size-cells = 1;
+ };
+
+ xhci0: xhci@1200 {
+ compatible = samsung,exynos5250-xhci;
+ reg = 0x1200 0x1;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ phy {
+ compatible = samsung,exynos5250-usb3-phy;
+ reg = 0x1210 0x100;
+ };
+ };
+
+ mmc@1220 {
+
[U-Boot] [PATCH 6/9 V7] Exynos5420: Add base patch for SMDK5420
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Rebased on latest u-boot-samsung tree.
Changes in V5:
- Removed functions board_eth_init and board_mmc_init
as they were moved to common/board.c
Changes in V6:
- None
Changes in V7:
- added CONFIG_EXYNOS_SPL to build 5420 and 5250
board/samsung/common/board.c | 2 +
board/samsung/smdk5420/Makefile | 34
board/samsung/smdk5420/smdk5420.c | 159 ++
board/samsung/smdk5420/smdk5420_spl.c | 52 +++
boards.cfg| 1 +
include/configs/arndale.h | 1 +
include/configs/exynos5250-dt.h | 1 +
tools/Makefile| 3 +-
8 files changed, 252 insertions(+), 1 deletion(-)
create mode 100644 board/samsung/smdk5420/Makefile
create mode 100644 board/samsung/smdk5420/smdk5420.c
create mode 100644 board/samsung/smdk5420/smdk5420_spl.c
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9ebfc42..2512a59 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -143,6 +143,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void)
return local.cros_ec_dev;
}
+#ifdef CONFIG_CROS_EC
static int board_init_cros_ec_devices(const void *blob)
{
local.cros_ec_err = cros_ec_init(blob, local.cros_ec_dev);
@@ -151,6 +152,7 @@ static int board_init_cros_ec_devices(const void *blob)
return 0;
}
+#endif
#if defined(CONFIG_POWER)
#ifdef CONFIG_POWER_MAX77686
diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile
new file mode 100644
index 000..be538ec
--- /dev/null
+++ b/board/samsung/smdk5420/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright (C) 2013 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS += smdk5420_spl.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS += smdk5420.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL:= $(obj).depend $(LIB)
+
+all: $(ALL)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
new file mode 100644
index 000..d85b953
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include fdtdec.h
+#include asm/io.h
+#include i2c.h
+#include lcd.h
+#include spi.h
+#include asm/arch/board.h
+#include asm/arch/cpu.h
+#include asm/arch/gpio.h
+#include asm/arch/pinmux.h
+#include asm/arch/dp_info.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+static int board_usb_vbus_init(void)
+{
+ struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+ samsung_get_base_gpio_part1();
+
+ /* Enable VBUS power switch */
+ s5p_gpio_direction_output(gpio1-x2, 6, 1);
+
+ /* VBUS turn ON time */
+ mdelay(3);
+
+ return 0;
+}
+#endif
+
+int exynos_init(void)
+{
+#ifdef CONFIG_USB_EHCI_EXYNOS
+ board_usb_vbus_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_LCD
+void cfg_lcd_gpio(void)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+
+ /* For Backlight */
+ s5p_gpio_cfg_pin(gpio1-b2, 0, GPIO_OUTPUT);
+ s5p_gpio_set_value(gpio1-b2, 0, 1);
+
+ /* LCD power on */
+ s5p_gpio_cfg_pin(gpio1-x1, 5, GPIO_OUTPUT);
+ s5p_gpio_set_value(gpio1-x1, 5, 1);
+
+ /* Set Hotplug detect for DP */
+ s5p_gpio_cfg_pin(gpio1-x0, 7, GPIO_FUNC(0x3));
+}
+
+vidinfo_t panel_info = {
+ .vl_freq= 60,
+ .vl_col = 2560,
+ .vl_row = 1600,
+ .vl_width = 2560,
+ .vl_height = 1600,
+ .vl_clkp= CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_LOW,
+ .vl_bpix= 4,/* LCD_BPP = 2^4, for output conosle on LCD */
+
+ /* wDP panel timing infomation */
+ .vl_hspw= 32,
+ .vl_hbpd= 80,
+ .vl_hfpd= 48,
+
+ .vl_vspw= 6,
+ .vl_vbpd= 37,
+
Re: [U-Boot] [PATCH v3 2/6] arm: atmel: sama5d3: correct the error define of DIV
Hi Bo,
On 11/06/2013 06:29 AM, Bo Shen wrote:
Correct the error define of DIV.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
- None
Changes in v2:
- None
arch/arm/include/asm/arch-at91/at91_pmc.h |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h
b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 003920c..ed5462c 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -124,8 +124,8 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_MDIV_MASK 0x0300
#endif
-#define AT91_PMC_MCKR_PLLADIV_1 0x1000
-#define AT91_PMC_MCKR_PLLADIV_2 0x2000
+#define AT91_PMC_MCKR_PLLADIV_1 0x
+#define AT91_PMC_MCKR_PLLADIV_2 0x1000
this change will touch pm9261 board. I dunno if your change is correct
for that board. I also wonder why one should set bit position 13 in MCKR
... I can't find any source what that bit could be. However mature
documentation for sam9261 (which is the SoC on pm9261) doesn't name bit
position 12 either.
So I'm fine with your change, but please fix the pm9261 board also (use
the PLLADIV_2 define).
#define AT91_PMC_IXR_MOSCS 0x0001
#define AT91_PMC_IXR_LOCKA 0x0002
Best regards
Andreas Bießmann
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Re: [U-Boot] [PATCH v3 5/6] arm: atmel: add ddr2 initialization function
Hi Bo,
On 11/06/2013 06:29 AM, Bo Shen wrote:
The MPDDRC supports different type of SDRAM
This patch add ddr2 initialization function
Signed-off-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
- Move to at91 common folder
Changes in v2:
- None
arch/arm/cpu/at91-common/Makefile | 32 +++
arch/arm/cpu/at91-common/mpddrc.c | 123
+
arch/arm/include/asm/arch-at91/atmel_mpddrc.h | 111 ++
spl/Makefile |4 +
4 files changed, 270 insertions(+)
create mode 100644 arch/arm/cpu/at91-common/Makefile
create mode 100644 arch/arm/cpu/at91-common/mpddrc.c
create mode 100644 arch/arm/include/asm/arch-at91/atmel_mpddrc.h
diff --git a/arch/arm/cpu/at91-common/Makefile
b/arch/arm/cpu/at91-common/Makefile
new file mode 100644
index 000..6f1a9e6
--- /dev/null
+++ b/arch/arm/cpu/at91-common/Makefile
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2013 Atmel Corporation
+# Bo Shen voice.s...@atmel.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libat91-common.o
+
+COBJS-$(CONFIG_SPL_BUILD) += mpddrc.o
+
+SRCS:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
please rewrite in KBuild style.
diff --git a/arch/arm/cpu/at91-common/mpddrc.c
b/arch/arm/cpu/at91-common/mpddrc.c
new file mode 100644
index 000..1abde1e
--- /dev/null
+++ b/arch/arm/cpu/at91-common/mpddrc.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ * Bo Shen voice.s...@atmel.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/atmel_mpddrc.h
+
+static void atmel_mpddr_op(int mode, u32 ram_address)
static inline, could give the compiler a hint to optimize here.
+{
+ struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+
+ writel(mode, mpddr-mr);
+ writel(0, ram_address);
+}
+
+int ddr2_init(u32 ram_address, struct atmel_mpddr *mpddr_value)
could you please constify mpddr_value for the very same reason?
+{
+ struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ u32 ba_off, cr;
+
+ /* Compute bank offset according to NC in configuration register */
+ ba_off = (mpddr_value-cr ATMEL_MPDDRC_CR_NC_MASK) + 9;
+ if (!(mpddr_value-cr ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
+ ba_off += ((mpddr-cr ATMEL_MPDDRC_CR_NR_MASK) 2) + 11;
+
+ ba_off += (mpddr_value-mdr ATMEL_MPDDRC_MDR_DBW_MASK) ? 1 : 2;
+
+ /* Program the memory device type into the memory device register */
+ writel(mpddr_value-mdr, mpddr-mdr);
+
+ /* Program the configuration register */
+ writel(mpddr_value-cr, mpddr-cr);
+
+ /* Program the timing register */
+ writel(mpddr_value-tp0r, mpddr-tp0r);
+ writel(mpddr_value-tp1r, mpddr-tp1r);
+ writel(mpddr_value-tp2r, mpddr-tp2r);
+
+ /* Issue a NOP command */
+ atmel_mpddr_op(ATMEL_MPDDRC_MR_NOP_CMD, ram_address);
+
+ /* A 200 us is provided to precede any signal toggle */
+ udelay(200);
+
+ /* Issue a NOP command */
+ atmel_mpddr_op(ATMEL_MPDDRC_MR_NOP_CMD, ram_address);
+
+ /* Issue an all banks precharge command */
+ atmel_mpddr_op(ATMEL_MPDDRC_MR_PRCGALL_CMD, ram_address);
+
+ /* Issue an extended mode register set(EMRS2) to choose operation */
+ atmel_mpddr_op(ATMEL_MPDDRC_MR_EXT_LMR_CMD,
+ram_address + (0x2 ba_off));
+
+ /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
+ atmel_mpddr_op(ATMEL_MPDDRC_MR_EXT_LMR_CMD,
+ram_address + (0x3 ba_off));
+
+ /*
+ * Issue an extended mode register set(EMRS1) to enable DLL and
+ * program D.I.C (output driver impedance control)
+ */
+ atmel_mpddr_op(ATMEL_MPDDRC_MR_EXT_LMR_CMD,
+ram_address + (0x1 ba_off));
+
+ /* Enable DLL reset */
+ cr = readl(mpddr-cr);
+ writel(cr | ATMEL_MPDDRC_CR_EN_RESET_DLL, mpddr-cr);
+
+ /* A mode register set(MRS) cycle is issued to reset DLL */
+ atmel_mpddr_op(ATMEL_MPDDRC_MR_LMR_CMD, ram_address);
+
+ /* Issue an all banks precharge command */
+ atmel_mpddr_op(ATMEL_MPDDRC_MR_PRCGALL_CMD, ram_address);
+
+ /* Two auto-refresh (CBR) cycles are provided */
+ atmel_mpddr_op(ATMEL_MPDDRC_MR_RFSH_CMD,
Re: [U-Boot] [PATCH v3 6/6] arm: atmel: sama5d3: spl boot from fat fs SD card
Hi Bo,
On 11/06/2013 06:29 AM, Bo Shen wrote:
Enable Atmel sama5d3xek boart spl boot support, which can load u-boot
from SD card with FAT file system.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
- Move plla and mck configure to spl.c file
Changes in v2:
- Move spl related code to at91-common folder
arch/arm/cpu/armv7/Makefile |2 +-
arch/arm/cpu/at91-common/Makefile|1 +
arch/arm/cpu/at91-common/spl.c | 90
++
arch/arm/cpu/at91-common/u-boot-spl.lds | 50 ++
arch/arm/include/asm/arch-at91/at91_common.h |4 ++
arch/arm/include/asm/arch-at91/spl.h | 20 ++
board/atmel/sama5d3xek/sama5d3xek.c | 82 +++
include/configs/sama5d3xek.h | 34 ++
8 files changed, 282 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/at91-common/spl.c
create mode 100644 arch/arm/cpu/at91-common/u-boot-spl.lds
create mode 100644 arch/arm/include/asm/arch-at91/spl.h
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ee4b021..aea4e8b 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -16,7 +16,7 @@ COBJS += cache_v7.o
COBJS+= cpu.o
COBJS+= syslib.o
-ifneq
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
+ifneq
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
SOBJS+= lowlevel_init.o
endif
diff --git a/arch/arm/cpu/at91-common/Makefile
b/arch/arm/cpu/at91-common/Makefile
index 6f1a9e6..4377a0b 100644
--- a/arch/arm/cpu/at91-common/Makefile
+++ b/arch/arm/cpu/at91-common/Makefile
@@ -13,6 +13,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libat91-common.o
COBJS-$(CONFIG_SPL_BUILD) += mpddrc.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
SRCS:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
new file mode 100644
index 000..37c0cc4
--- /dev/null
+++ b/arch/arm/cpu/at91-common/spl.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ * Bo Shen voice.s...@atmel.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/at91_common.h
+#include asm/arch/at91_pmc.h
+#include asm/arch/at91_wdt.h
+#include asm/arch/clk.h
+#include spl.h
+
+static void at91_disable_wdt(void)
Why should we disable the WDT in SPL? I think it would be better to
configure a working timer value than just disable it.
Well it's easy and works, but for the future I think it would be good to
let it run while in SPL and u-boot.
+{
+ struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
+
+ writel(AT91_WDT_MR_WDDIS, wdt-mr);
+}
+
+void at91_plla_init(u32 pllar)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
We should ensure bit 29 to be '1' here.
+ writel(pllar, pmc-pllar);
+ while (!(readl(pmc-sr) (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
+ ;
Especially for doing such things it would be best handled by the WDT on
error.
+}
+
+void at91_mck_init(u32 mckr)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ u32 tmp;
+
+ tmp = readl(pmc-mckr);
+ tmp = ~(AT91_PMC_MCKR_PRES_MASK |
+ AT91_PMC_MCKR_MDIV_MASK |
+ AT91_PMC_MCKR_PLLADIV_2);
+ tmp |= mckr (AT91_PMC_MCKR_PRES_MASK |
+AT91_PMC_MCKR_MDIV_MASK |
+AT91_PMC_MCKR_PLLADIV_2);
Why gets the at91_mck_init() just some parts of the MCK register (some
fields are preserved here) while the at91_plla_init() just rewrites the
PLLA register?
I think it is not much more than hiding the writel() register access. I
think a better API would be to request some specific frequency and we
calculate the register values with that input.
Please let us discuss this.
+ writel(tmp, pmc-mckr);
+
+ while (!(readl(pmc-sr) AT91_PMC_MCKRDY))
+ ;
+}
+
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+ return BOOT_DEVICE_MMC1;
+#endif
Isn't there some way to detect the boot source by asking for example the
ROM code? Is there some register that holds that information?
+ return BOOT_DEVICE_NONE;
+}
+
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+#ifdef CONFIG_SYS_USE_MMC
+ case BOOT_DEVICE_MMC1:
+ return MMCSD_MODE_FAT;
+ break;
+#endif
+ case BOOT_DEVICE_NONE:
+ default:
+ hang();
+ }
+}
+
+void s_init(void)
+{
+ /* disable watchdog */
+ at91_disable_wdt();
+
+ /* PMC configuration */
+
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla lokeshvu...@ti.com wrote: [...] I checked with hardware folks. There is no register or some way to tell if VTT is present. It is not added in EEPROM also and I have no answer why it is not added in EEPROM..:( It is specific to boards using DDR3. So its good to have it in board files as I did it here instead of adding this check in emif file. That EEPROM is clearly not getting used the way i think it should be :\ I would have made a lot of noise to get details like this added there. You should at least check for the GP EVM (if possible) and then enable VTT. Doing this unconditionally is bound to cause problems later on. I would also put in a big comment over there so that folks who design their own board with DDR3 don't miss this fact. Regards, Vaibhav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/6] adapt s3c24x0 driver to new i2c framework
This patch series adapts the s3c24x0 driver to the new i2c framework. Config file is modified for all the boards that use the driver. Boards VCMA9, arndale and exynos5250 are compile tested only. Boards Trats and Trats2 were hardware tested. All boards compile clean. Piotr Wilczek (6): driver:i2c:s3c24x0: adapt driver to new i2c board:arndale: switch to new i2c framework board:VCMA9 switch to new i2c framework board:smdk5250: switch to new i2c framework board:trats: switch to new i2c framework board:trats2: switch Trats2 to new i2c framework board/samsung/smdk5250/exynos5-dt.c |2 - board/samsung/trats/trats.c | 21 +++-- board/samsung/trats2/trats2.c | 35 ++-- drivers/i2c/Makefile|2 +- drivers/i2c/s3c24x0_i2c.c | 157 ++- include/configs/VCMA9.h |8 +- include/configs/arndale.h |9 +- include/configs/exynos5250-dt.h |8 +- include/configs/trats.h | 25 ++ include/configs/trats2.h| 29 +++ 10 files changed, 174 insertions(+), 122 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/6] board:arndale: switch to new i2c framework
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com CC: Inderpal Singh inderpal.si...@linaro.org --- include/configs/arndale.h |9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 45fa047..ea8753b 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -214,13 +214,12 @@ /* I2C */ #define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_SPEED 10 /* 100 Kbps */ -#define CONFIG_DRIVER_S3C24X0_I2C -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ +#define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_MAX_I2C_NUM 8 -#define CONFIG_SYS_I2C_SLAVE0x0 +#define CONFIG_SYS_I2C_S3C24X0_SLAVE0x0 #define CONFIG_I2C_EDID /* PMIC */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] driver:i2c:s3c24x0: adapt driver to new i2c
The s3c24x0 i2c driver is adapted to new i2c framework.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Heiko Schocher h...@denx.de
---
drivers/i2c/Makefile |2 +-
drivers/i2c/s3c24x0_i2c.c | 157 +
2 files changed, 101 insertions(+), 58 deletions(-)
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 553b519..fa3a875 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
-obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
@@ -24,6 +23,7 @@ obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index f77a9d1..0051cac 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -23,8 +23,6 @@
#include i2c.h
#include s3c24x0_i2c.h
-#ifdef CONFIG_HARD_I2C
-
#defineI2C_WRITE 0
#define I2C_READ 1
@@ -127,7 +125,6 @@
* For SPL boot some boards need i2c before SDRAM is initialised so force
* variables to live in SRAM
*/
-static unsigned int g_current_bus __attribute__((section(.data)));
static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
__attribute__((section(.data)));
@@ -143,6 +140,7 @@ static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
struct s3c24x0_i2c_bus *bus;
bus = i2c_bus[bus_idx];
+
if (bus-active)
return bus;
}
@@ -254,17 +252,17 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
writel(readl(i2c-iiccon) ~I2CCON_IRPND, i2c-iiccon);
}
-static struct s3c24x0_i2c *get_base_i2c(void)
+static struct s3c24x0_i2c *get_base_i2c(int bus)
{
#ifdef CONFIG_EXYNOS4
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
+ (EXYNOS4_I2C_SPACING
- * g_current_bus));
+ * bus));
return i2c;
#elif defined CONFIG_EXYNOS5
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
+ (EXYNOS5_I2C_SPACING
- * g_current_bus));
+ * bus));
return i2c;
#else
return s3c24x0_get_base_i2c();
@@ -298,7 +296,6 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed,
int slaveadd)
writel(I2C_MODE_MT | I2C_TXRX_ENA, i2c-iicstat);
}
-#ifdef CONFIG_I2C_MULTI_BUS
static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
{
struct exynos5_hsi2c *hsregs = i2c_bus-hsregs;
@@ -307,8 +304,10 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus
*i2c_bus)
unsigned int i = 0, utemp0 = 0, utemp1 = 0;
unsigned int t_ftl_cycle;
-#if defined CONFIG_EXYNOS5
+#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
clkin = get_i2c_clk();
+#else
+ clkin = get_PCLK();
#endif
/* FPCLK / FI2C =
* (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
@@ -330,7 +329,6 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus
*i2c_bus)
}
return -1;
}
-#endif
static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
{
@@ -401,49 +399,18 @@ static void exynos5_i2c_reset(struct s3c24x0_i2c_bus
*i2c_bus)
hsi2c_ch_init(i2c_bus);
}
-/*
- * MULTI BUS I2C support
- */
-
-#ifdef CONFIG_I2C_MULTI_BUS
-int i2c_set_bus_num(unsigned int bus)
-{
- struct s3c24x0_i2c_bus *i2c_bus;
-
- i2c_bus = get_bus(bus);
- if (!i2c_bus)
- return -1;
- g_current_bus = bus;
-
- if (i2c_bus-is_highspeed) {
- if (hsi2c_get_clk_details(i2c_bus))
- return -1;
- hsi2c_ch_init(i2c_bus);
- } else {
- i2c_ch_init(i2c_bus-regs, i2c_bus-clock_frequency,
- CONFIG_SYS_I2C_SLAVE);
- }
-
- return 0;
-}
-
-unsigned int i2c_get_bus_num(void)
-{
- return g_current_bus;
-}
-#endif
-
-void i2c_init(int speed, int slaveadd)
+static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int
[U-Boot] [PATCH 4/6] board:smdk5250: switch to new i2c framework
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com CC: Chander Kashyap k.chan...@samsung.com --- board/samsung/smdk5250/exynos5-dt.c |2 -- include/configs/exynos5250-dt.h |8 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index 6bcc883..6aa0509 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -150,8 +150,6 @@ int power_init_board(void) set_ps_hold_ctrl(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (pmic_init(I2C_PMIC)) return -1; diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index bdefee1..0155322 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -249,13 +249,13 @@ /* I2C */ #define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_SPEED 10 /* 100 Kbps */ -#define CONFIG_DRIVER_S3C24X0_I2C +#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ +#define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_I2C_MULTI_BUS #define CONFIG_MAX_I2C_NUM 8 -#define CONFIG_SYS_I2C_SLAVE0x0 +#define CONFIG_SYS_I2C_S3C24X0_SLAVE0x0 #define CONFIG_I2C_EDID /* PMIC */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/6] board:trats: switch to new i2c framework
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Lukasz Majewski l.majew...@samsung.com
---
board/samsung/trats/trats.c | 21 -
include/configs/trats.h | 25 -
2 files changed, 20 insertions(+), 26 deletions(-)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 7012c13..44be5fc 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -57,15 +57,18 @@ int board_init(void)
void i2c_init_board(void)
{
- struct exynos4_gpio_part1 *gpio1 =
- (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+ int err;
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- /* I2C_5 - PMIC - Adapter 0 */
- s5p_gpio_direction_output(gpio1-b, 7, 1);
- s5p_gpio_direction_output(gpio1-b, 6, 1);
- /* I2C_9 - FG - Adapter 1 */
+ /* I2C_5 - PMIC */
+ err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
+ if (err) {
+ debug(I2C%d not configured\n, (I2C_5));
+ return;
+ }
+
+ /* I2C_8 - FG */
s5p_gpio_direction_output(gpio2-y4, 0, 1);
s5p_gpio_direction_output(gpio2-y4, 1, 1);
}
@@ -290,10 +293,10 @@ int power_init_board(void)
* The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
* to logical I2C adapter 1
*/
- ret = pmic_init(I2C_0);
+ ret = pmic_init(I2C_5);
ret |= pmic_init_max8997();
- ret |= power_fg_init(I2C_1);
- ret |= power_muic_init(I2C_0);
+ ret |= power_fg_init(I2C_8);
+ ret |= power_muic_init(I2C_5);
ret |= power_bat_init(0);
if (ret)
return ret;
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 3d080c4..f163303 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -16,6 +16,7 @@
*/
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
#define CONFIG_S5P /* which is in a S5P Family */
+#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
#define CONFIG_TRATS /* working with TRATS */
#define CONFIG_TIZEN /* TIZEN lib */
@@ -268,31 +269,21 @@
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED 10
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE
+#define CONFIG_MAX_I2C_NUM 8
#define CONFIG_SYS_I2C_SOFT/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED 5
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#define I2C_SOFT_DECLARATIONS2
-#define CONFIG_SYS_I2C_SOFT_SPEED_2 5
-#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SOFT_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS 15
#include asm/arch/gpio.h
-/* I2C PMIC */
-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
-
/* I2C FG */
-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
-
-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
-#define I2C_INIT multi_i2c_init()
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0)
#define CONFIG_POWER
#define CONFIG_POWER_I2C
--
1.7.9.5
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[U-Boot] [PATCH 6/6] board:trats2: switch Trats2 to new i2c framework
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
board/samsung/trats2/trats2.c | 35 +--
include/configs/trats2.h | 29 -
2 files changed, 41 insertions(+), 23 deletions(-)
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index d44d825..8df85ee 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -115,12 +115,17 @@ static void board_external_gpio_init(void)
#ifdef CONFIG_SYS_I2C_INIT_BOARD
static void board_init_i2c(void)
{
+ int err;
+
gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
/* I2C_7 */
- s5p_gpio_direction_output(gpio1-d0, 2, 1);
- s5p_gpio_direction_output(gpio1-d0, 3, 1);
+ err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
+ if (err) {
+ debug(I2C%d not configured\n, (I2C_7));
+ return;
+ }
/* I2C_8 */
s5p_gpio_direction_output(gpio1-f1, 4, 1);
@@ -132,6 +137,24 @@ static void board_init_i2c(void)
}
#endif
+#ifdef CONFIG_SYS_I2C_SOFT
+int get_soft_i2c_scl_pin(void)
+{
+ if (I2C_ADAP_HWNR)
+ return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
+ else
+ return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
+}
+
+int get_soft_i2c_sda_pin(void)
+{
+ if (I2C_ADAP_HWNR)
+ return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
+ else
+ return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
+}
+#endif
+
int board_early_init_f(void)
{
check_hw_revision();
@@ -167,11 +190,11 @@ int power_init_board(void)
#ifdef CONFIG_SYS_I2C_INIT_BOARD
board_init_i2c();
#endif
- pmic_init(I2C_0); /* I2C adapter 0 - bus name I2C_5 */
+ pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */
pmic_init_max77686();
- pmic_init_max77693(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
- power_muic_init(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
- power_fg_init(I2C_1); /* I2C adapter 1 - bus name I2C_9 */
+ pmic_init_max77693(I2C_9); /* I2C adapter 9 - bus name soft1 */
+ power_muic_init(I2C_9); /* I2C adapter 9 - bus name soft1 */
+ power_fg_init(I2C_8); /* I2C adapter 8 - bus name soft0 */
power_bat_init(0);
p_chrg = pmic_get(MAX77693_PMIC);
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 0e93836..3bcdfb1 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -260,30 +260,25 @@
#include asm/arch/gpio.h
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT/* I2C bit-banged */
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED 10
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
+#define CONFIG_MAX_I2C_NUM 8
+#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SOFT_SPEED 5
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
#define I2C_SOFT_DECLARATIONS2
#define CONFIG_SYS_I2C_SOFT_SPEED_2 5
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00
-#define I2C_SOFT_DECLARATIONS3
-#define CONFIG_SYS_I2C_SOFT_SPEED_3 5
-#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x00
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SOFT_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS 15
-
-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3)
-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2)
-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4)
-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5)
-#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1)
-#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0)
-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
-#define I2C_INIT multi_i2c_init()
+
+#ifndef __ASSEMBLY__
+int get_soft_i2c_scl_pin(void);
+int get_soft_i2c_sda_pin(void);
+#endif
+#define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin()
+#define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin()
/* POWER */
#define CONFIG_POWER
--
1.7.9.5
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[U-Boot] [PATCH 3/6] board:VCMA9 switch to new i2c framework
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com CC: David Müller d.muel...@elsoft.ch --- include/configs/VCMA9.h |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 79a6079..57b620d 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -73,12 +73,12 @@ * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at * address 0x50 with 16bit addressing */ -#define CONFIG_HARD_I2C/* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 10 /* I2C speed */ -#define CONFIG_SYS_I2C_SLAVE 0x7F/* I2C slave addr */ +#define CONFIG_SYS_I2C /* we use the built-in I2C controller */ -#define CONFIG_DRIVER_S3C24X0_I2C +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_SYS_I2C_S3C24X0_SPEED10 /* I2C speed */ +#define CONFIG_SYS_I2C_S3C24X0_SLAVE0x7F /* I2C slave addr */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Separate EBV Socrates board from Altera Cyclone 5 board
On Tue, 2013-11-12 at 16:17 +0100, Michal Simek wrote: On 11/12/2013 03:46 PM, Chin Liang See wrote: Hi all, On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote: On 11/12/2013 10:56 AM, Detlev Zundel wrote: Hi Michal, On 11/11/2013 09:33 PM, Tom Rini wrote: On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: Altera Cyclone 5 board is very different board (big, rectangular, expensive) than EBV Socrates (small, circular, cheap) board. Different parts are used there, too, but same configuration of u-boot works on both. Nevertheless, printing wrong name confuses users. Therefore this splits the configuration so that u-boot knows they are different. So far it is only used for correcting the puts, but there may be other uses in future. Signed-off-by: Pavel Machek pa...@denx.de Is there any way at run time to tell which board we are on? Why do you care about board name in general? We care for board names for a very long time in U-Boot and I'd like to keep this. I actually expect a sensible board name on any platform that I touch. The board name is an important extra information additional to the SoC name. So the question is the other way round - since when do we _not_ care about board names? There could be i2c memory on board where you can find out this information but that's problematic if it is empty or you want to use this i2c for something else. For all microblaze boards I use XILINX_BOARD_NAME which reflects hw design (if user is smart enough board name is the part of hw design name). For zynq/socfpga sensible solution is probably to load this name for DTS. Currently, the SOCFPGA SPL is customized through a set of handoff files which located at board folders. These handoff files are generated by tools based on board and user design in FPGA. With that, not much decision being made during run time based on the board. With this handoff and tools approach, it will shield off the complexity of hardware configuration and errors (if user change it manually without tools help). Thanks Which nice copy of our approach. :-) Hmmm... is it true? This approach being used since few years back at NIOS soft processor. Besides that, we are utilizing the SPL framework for our second stage boot loader. I believe you guys are not using SPL right? It seems you guys would need tools to generate and even build you guys own version of boot loader. It creates high dependency for user to your tools. For our solution, customer can just grab the code from git and build it using the normal U-Boot way (if they don't want to use the tools). With the SPL also, we are taking advantage of open source community power to make our second stage boot loader more powerful and user friendly to user. Our user can grab any drivers or leverage the supports from the open community too. I believe that is the power of open source :) Chin Liang But anyway I believe that you are also generating one macro which define name of this configuration based on hw design/board you are using. And then you can use this macro for showing board/design name in u-boot. Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Question re HYP mode and IRQ/FIQ stack setting
On 12 November 2013 22:22, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Christoffer, On Tue, 12 Nov 2013 14:34:00 -0800, Christoffer Dall christoffer.d...@linaro.org wrote: On 12 November 2013 13:29, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Christoffer, On Tue, 12 Nov 2013 09:09:23 -0800, Christoffer Dall christoffer.d...@linaro.org wrote: I suspect that if you are in Hyp mode, you should not worry about FIQ/IRQ mode, but just make sure to configure Hyp mode properly to handle interrupts. (it's a separate entry in the exception vector and you probably need to look at the HSR register whn you've taken an interrupt). So, as Andre suggests below, it depends on your use case. Ok, so les me try to sum that up from my perspective (IRQ and FIQ stacks in U-Boot): Some ARM U-Boot targets run in SVC32 mode, and some in HYP mode. For targets which run in SVC32 mode: aborts execute in abort mode, IRQs in IRQ mode, FIQs in FIQ mode, etc., each mode having its own stack. correct For targets which run in HYP mode: aborts, FIQ and IRQs all run in HYP mode, using always the same stack. correct. In both types of targers: prefetch and data aborts, FIQs and IRQs execute through the usual vectors; in SVC32 mode, because there's no other way; in HYP mode, because exceptions occurring while in HYP mode use the normal vector, not the HYP vector. Correct? no, this sounds fishy. Look at the ARM ARMv7 (DDI 0406C.b) page B1-1166. Table B1-3 will tell you what you need to know. Hyp mode has its own vectors, pointed to by the HVBAR control register. I strongly suggest you familiarize yourself with these parts of the ARM ARM before writing code to that effect. To clarify my meaning: I wasn't speaking about the exceptions base address, but about the exception vector offset. IOW, I did not mean to say that in HYP mode, aborts, FIQs, IRQs etc use the SVC32 table of vectors rather than the HYP table. I meant to say that e.g. an IRQ will fire at offset 0x18, whether it fires while from SVC32 into IRQ mode, or from HYP mode into HYP mode. This seemed consistent with figure B1-8 on page B1-1179 of DDI 0406C.b, respectively first and sixth exit box on the right. Is this clearer and more correct? yes, now I understand. It's correct. If so, then U-Boot stack requirements for SVC32 and HYP mode are as follows: in SVC32, we need separate IRQ and FIQ stacks, and the main (SVC32) stack does not have to accommodate for interrupt handler context storage. In HYP mode, the only stack is the HYP one and exception handlers will use it too, so it has to accommodate for their context storage. That is correct, your Hyp mode stack should always be valid (have a page or so, like the kernel) and then you can always push things on there, even when taking an exception. Thanks Christoffer! This should allow me to refactor interrupt stack settings as I intended. -Christoffer Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Separate EBV Socrates board from Altera Cyclone 5 board
On 11/13/2013 03:39 PM, Chin Liang See wrote: On Tue, 2013-11-12 at 16:17 +0100, Michal Simek wrote: On 11/12/2013 03:46 PM, Chin Liang See wrote: Hi all, On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote: On 11/12/2013 10:56 AM, Detlev Zundel wrote: Hi Michal, On 11/11/2013 09:33 PM, Tom Rini wrote: On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: Altera Cyclone 5 board is very different board (big, rectangular, expensive) than EBV Socrates (small, circular, cheap) board. Different parts are used there, too, but same configuration of u-boot works on both. Nevertheless, printing wrong name confuses users. Therefore this splits the configuration so that u-boot knows they are different. So far it is only used for correcting the puts, but there may be other uses in future. Signed-off-by: Pavel Machek pa...@denx.de Is there any way at run time to tell which board we are on? Why do you care about board name in general? We care for board names for a very long time in U-Boot and I'd like to keep this. I actually expect a sensible board name on any platform that I touch. The board name is an important extra information additional to the SoC name. So the question is the other way round - since when do we _not_ care about board names? There could be i2c memory on board where you can find out this information but that's problematic if it is empty or you want to use this i2c for something else. For all microblaze boards I use XILINX_BOARD_NAME which reflects hw design (if user is smart enough board name is the part of hw design name). For zynq/socfpga sensible solution is probably to load this name for DTS. Currently, the SOCFPGA SPL is customized through a set of handoff files which located at board folders. These handoff files are generated by tools based on board and user design in FPGA. With that, not much decision being made during run time based on the board. With this handoff and tools approach, it will shield off the complexity of hardware configuration and errors (if user change it manually without tools help). Thanks Which nice copy of our approach. :-) Hmmm... is it true? This approach being used since few years back at NIOS soft processor. Besides that, we are utilizing the SPL framework for our second stage boot loader. I believe you guys are not using SPL right? It seems you guys would need tools to generate and even build you guys own version of boot loader. It creates high dependency for user to your tools. Interesting discussion. :-) I believe we will use SPL at some point in future for Microblaze just because of easier maintenance . But will see. I don't understand your point regarding to tool dependency. For DTSes I believe you are also generating this structure from design tools or you can write it by hand. We are also generating U-boot configuration but if someone wants to write it by hand they can. For our solution, customer can just grab the code from git and build it using the normal U-Boot way (if they don't want to use the tools). With the SPL also, we are taking advantage of open source community power to make our second stage boot loader more powerful and user friendly to user. Our user can grab any drivers or leverage the supports from the open community too. I believe that is the power of open source :) We have the same for Microblaze and Zynq. Cheers, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
Hi Vaibhav, On 11/13/2013 7:38 PM, Vaibhav Bedia wrote: On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla lokeshvu...@ti.com wrote: [...] I checked with hardware folks. There is no register or some way to tell if VTT is present. It is not added in EEPROM also and I have no answer why it is not added in EEPROM..:( It is specific to boards using DDR3. So its good to have it in board files as I did it here instead of adding this check in emif file. That EEPROM is clearly not getting used the way i think it should be :\ I would have made a lot of noise to get details like this added there. The EEPROM was designed as a way to differentiate between different TI EVMs, not as a generic way to differentiate between various possible board hook-ups. Even if we did define it that way, why would all boards using AM437x have an onboard EEPROM? We could request this information be placed in EEPROM and see if hardware folks oblige, but I don't see how that's going to be used beyond TI EVMs. Thanks, Sekhar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 2/3] i2c: tegra: Add the fifth bus on SoC with more than 4 buses
Create the i2c adapter object for the fifth bus on SoC with more than 4 buses. This allow using all the bus available on T30. Signed-off-by: Alban Bedel alban.be...@avionic-design.de --- drivers/i2c/tegra_i2c.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 9847cf1..594e5dd 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -629,3 +629,8 @@ U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe, U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe, tegra_i2c_read, tegra_i2c_write, tegra_i2c_set_bus_speed, 10, 0, 3) +#if TEGRA_I2C_NUM_CONTROLLERS 4 +U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe, +tegra_i2c_read, tegra_i2c_write, +tegra_i2c_set_bus_speed, 10, 0, 4) +#endif -- 1.8.4.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 1/3] ARM: tegra: support SKU b1 of Tegra30
Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
Reviewed-by: Julian Scheel julian.sch...@avionic-design.de
---
V4: Renamed SKU_ID_TM30MQS_A3 to SKU_ID_TM30MQS_P_A3, according to
Thierry Reding this ID should be better suited as there is another
TM30MQS variant with another SKU.
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
arch/arm/cpu/tegra-common/ap.c | 1 +
arch/arm/include/asm/arch-tegra/tegra.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 6fb11cb..60d71a6 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -71,6 +71,7 @@ int tegra_get_chip_sku(void)
switch (sku_id) {
case SKU_ID_T33:
case SKU_ID_T30:
+ case SKU_ID_TM30MQS_P_A3:
return TEGRA_SOC_T30;
}
break;
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h
b/arch/arm/include/asm/arch-tegra/tegra.h
index 25d1fc4..e99f681 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -65,6 +65,7 @@ enum {
SKU_ID_T25E = 0x1c,
SKU_ID_T33 = 0x80,
SKU_ID_T30 = 0x81, /* Cardhu value */
+ SKU_ID_TM30MQS_P_A3 = 0xb1,
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
};
--
1.8.4.2
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[U-Boot] [PATCH v4 3/3] ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board
Add support for the new Tamonten™ NG platform from Avionic Design.
Currently only I2C, MMC, USB and ethernet have been tested.
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
V3: * Removed the retries from pmu_write()
* Removed the not strictly needed power init
V4: * Removed the unused PMU defines
* Removed the useless #ifdef
* Reworked the DTS to enable the device at the proper level
* Re-numbered the i2c bus to match the kernel numbering
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
.../common/pinmux-config-tamonten-ng.h | 385 +
board/avionic-design/common/tamonten-ng.c | 85 +
board/avionic-design/dts/tegra30-tamonten.dtsi | 69
board/avionic-design/dts/tegra30-tec-ng.dts| 18 +
board/avionic-design/tec-ng/Makefile | 32 ++
boards.cfg | 1 +
include/configs/tec-ng.h | 84 +
7 files changed, 674 insertions(+)
create mode 100644 board/avionic-design/common/pinmux-config-tamonten-ng.h
create mode 100644 board/avionic-design/common/tamonten-ng.c
create mode 100644 board/avionic-design/dts/tegra30-tamonten.dtsi
create mode 100644 board/avionic-design/dts/tegra30-tec-ng.dts
create mode 100644 board/avionic-design/tec-ng/Makefile
create mode 100644 include/configs/tec-ng.h
diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h
b/board/avionic-design/common/pinmux-config-tamonten-ng.h
new file mode 100644
index 000..39df731
--- /dev/null
+++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h
@@ -0,0 +1,385 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH www.avionic-design.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
+#define _PINMUX_CONFIG_TAMONTEN_NG_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull,\
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT,\
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset= PMUX_PIN_IO_RESET_DEFAULT,\
+ }
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull,\
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock,\
+ .od = PMUX_PIN_OD_##_od,\
+ .ioreset= PMUX_PIN_IO_RESET_DEFAULT,\
+ }
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull,\
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock,\
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset= PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt,
_hsm) \
+ { \
+ .padgrp = PDRIVE_PINGROUP_##_padgrp,\
+ .slwf = _slwf,\
+ .slwr = _slwr,\
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PGRP_LPMD_##_lpmd,\
+ .schmt = PGRP_SCHMT_##_schmt, \
+ .hsm= PGRP_HSM_##_hsm, \
+ }
+
+static struct pingroup_config tamonten_ng_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP,
[U-Boot] [PATCH v4 0/3] ARM: tegra: Add the Tamonten-NG Evaluation carrier boards
Hi everyone, I hope everything requiered is there this time: * The SKU ID has been changed to SKU_ID_T30MQS_P_A3 as suggested by Thierry * A new patch has been added to enable the 5th i2c bus on T30, this is now needed because: * The i2c buses have been re-numbered to match the numbering used in the kernel * The DTS has been re-worked to better reflect the split between COM and base board. For the i2c buses the split was done according to where the pull-ups are. So buses enabled in the COM dts have their pull-ups on the COM module. * All the useless defines have now been removed. Alban Bedel (3): ARM: tegra: support SKU b1 of Tegra30 i2c: tegra: Add the fifth bus on SoC with more than 4 buses ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board arch/arm/cpu/tegra-common/ap.c | 1 + arch/arm/include/asm/arch-tegra/tegra.h| 1 + .../common/pinmux-config-tamonten-ng.h | 385 + board/avionic-design/common/tamonten-ng.c | 85 + board/avionic-design/dts/tegra30-tamonten.dtsi | 69 board/avionic-design/dts/tegra30-tec-ng.dts| 18 + board/avionic-design/tec-ng/Makefile | 32 ++ boards.cfg | 1 + drivers/i2c/tegra_i2c.c| 5 + include/configs/tec-ng.h | 84 + 10 files changed, 681 insertions(+) create mode 100644 board/avionic-design/common/pinmux-config-tamonten-ng.h create mode 100644 board/avionic-design/common/tamonten-ng.c create mode 100644 board/avionic-design/dts/tegra30-tamonten.dtsi create mode 100644 board/avionic-design/dts/tegra30-tec-ng.dts create mode 100644 board/avionic-design/tec-ng/Makefile create mode 100644 include/configs/tec-ng.h -- 1.8.4.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114
On 11/13/2013 02:28 AM, Andreas Müller wrote: On Fri, Jun 21, 2013 at 6:20 PM, Stephen Warren swar...@wwwdotorg.org wrote: On 06/21/2013 05:05 AM, Jim Lin wrote: Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards. Changes in v5: - Move changes on fdtdec.h and fdtdec.c to patch 2/3 - Modify PHY type to hsic for USB2 port HSIC is an odd choice; ULPI is much more common. Still, this isn't a big deal; this is simply a default value, so any board that enables USB2 can simply set the property to ulpi if needed. Long time ago but now I am working on a board support for tegra30 which has ASIX-eth on USB2-HSIC and don't get it to work. Checking the code leads me to the question: Is it possible that phy_type = hsic is not handled at all? Almost certainly. I don't believe any of the boards we currently support in upstream U-Boot or the Linux kernel actually use/support HSIC, so it's quite unlikely that the driver support for HSIC is present. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/5] i.MX6 (DQ/DLS): consolidate mux and pad names
Thanks Stefano, On 11/13/2013 02:36 AM, Stefano Babic wrote: Hi Eric, On 05/11/2013 01:00, Eric Nelson wrote: This patch set consolidates mux and pad declarations for the i.MX6 Dual/Quad and Dual-Lite/Solo processor variants. Patch 1 replaces the mux/pad names with their equivalents from the Linux kernel (from linux-next). This Patch 2 removes a set of completely useless pad declarations Patch 3 adds a number of registers that are defined in the Linux kernel and in the DLS variant, but not in the DQ. Patch 4 removes pad declarations that aren't used and aren't defined in the Linux kernel tree Patch 5 cleans up the whitespace in mx6[q|dl]_pins.h so the IOMUX_PAD() columns line up. Eric, thanks again for the great job. Applied (whole patchset) to u-boot-imx, thanks ! Oops. I was kinda hoping to get a head-not from Fabio on the macro-fication of mx6[q|dl]_pins.h. If we can get that, we can drop patch 5 of this patch set, since the white-space changes all around... Regards, Eric ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/5] i.MX6 (DQ/DLS): consolidate mux and pad names
Hi Eric, On Wed, Nov 13, 2013 at 3:23 PM, Eric Nelson eric.nel...@boundarydevices.com wrote: Applied (whole patchset) to u-boot-imx, thanks ! Oops. I was kinda hoping to get a head-not from Fabio on the macro-fication of mx6[q|dl]_pins.h. If we can get that, we can drop patch 5 of this patch set, since the white-space changes all around... I am not sure I understood the issue with patch 5. Please clarify. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] socfpga: Adding Scan Manager
Adding Scan Manager driver and handoff files. Scan Manager driver will be called to configure the IO buffer setting. Signed-off-by: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Wolfgang Denk w...@denx.de CC: Pavel Machek pa...@denx.de Cc: Tom Rini tr...@ti.com Cc: Albert Aribaud albert.u.b...@aribaud.net Chin Liang See (2): socfpga: Adding Scan Manager driver socfpga: Adding Scan Manager IOCSR handoff files arch/arm/cpu/armv7/socfpga/Makefile|2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 +++ arch/arm/cpu/armv7/socfpga/spl.c |4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + board/altera/socfpga/iocsr_config.c| 653 board/altera/socfpga/iocsr_config.h| 12 + include/configs/socfpga_cyclone5.h |1 + 8 files changed, 1000 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h create mode 100644 board/altera/socfpga/iocsr_config.c create mode 100644 board/altera/socfpga/iocsr_config.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 231
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 97
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
include/configs/socfpga_cyclone5.h |1 +
6 files changed, 335 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..4edc5d4 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..30cbb8b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include common.h
+#include asm/io.h
+#include asm/arch/freeze_controller.h
+#include asm/arch/scan_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(scan_manager_base-stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
+ || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) 0)) {
+
+ max_iter--;
+
+ if (max_iter 0)
+ scanmgr_status = readl(scan_manager_base-stat);
+ else
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
+ }
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
+}
+
+
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /* De-assert reinit if the IO scan chain is intended for HIO */
+ if (3 == io_scan_chain_id)
+ clrbits_le32(freeze_controller_base-hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
+ != scan_mgr_io_scan_chain_engine_is_idle(
+ MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
+ return 1;
+ }
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(scan_manager_base-en, 1 io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+ tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD
+ TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+ /* Program IO scan chain in 128-bit iteration */
+ for (i = 0; i io_program_iter; i++) {
+
+ /* write TDI_TDO packet header to scan manager */
+ writel(tdi_tdo_header, scan_manager_base-fifodoublebyte);
+
+ /* calculate array index */
+ index = i * 4;
+
+
[U-Boot] [PATCH 2/2] socfpga: Adding Scan Manager IOCSR handoff files
The IOCSR handoff files will be consumed by Scan Manager driver.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
board/altera/socfpga/iocsr_config.c | 653 +++
board/altera/socfpga/iocsr_config.h | 12 +
2 files changed, 665 insertions(+)
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/board/altera/socfpga/iocsr_config.c
b/board/altera/socfpga/iocsr_config.c
new file mode 100644
index 000..7e66ff8
--- /dev/null
+++ b/board/altera/socfpga/iocsr_config.c
@@ -0,0 +1,653 @@
+
+/* This file is generated by Preloader Generator */
+
+#include iocsr_config.h
+
+const unsigned long iocsr_scan_chain0_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+ 0x,
+ 0x,
+ 0x0FF0,
+ 0xC000,
+ 0x003F,
+ 0x8000,
+ 0x00020080,
+ 0x0802,
+ 0x0800,
+ 0x00018020,
+ 0x,
+ 0x4000,
+ 0x00010040,
+ 0x0401,
+ 0x0400,
+ 0x0010,
+ 0x4010,
+ 0x2000,
+ 0x0002,
+ 0x02008000,
+ 0x0200,
+ 0x0008,
+ 0x2008,
+ 0x1000,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+ 0x000C0300,
+ 0x1004,
+ 0x10C0,
+ 0x0040,
+ 0x00010040,
+ 0x8000,
+ 0x0008,
+ 0x1806,
+ 0x1800,
+ 0x0060,
+ 0x00018060,
+ 0x4000,
+ 0x00010040,
+ 0x1000,
+ 0x0400,
+ 0x0010,
+ 0x4010,
+ 0x2000,
+ 0x06008020,
+ 0x02008000,
+ 0x01FE,
+ 0xF800,
+ 0x0007,
+ 0x1000,
+ 0x4010,
+ 0x01004000,
+ 0x0100,
+ 0x3004,
+ 0x1004,
+ 0x0800,
+ 0x,
+ 0x,
+ 0x0080,
+ 0x0002,
+ 0x2000,
+ 0x0400,
+ 0x,
+ 0x00401000,
+ 0x0003,
+ 0x,
+ 0x,
+ 0x0200,
+ 0x00600802,
+ 0x,
+ 0x8020,
+ 0x8600,
+ 0x0200,
+ 0x0100,
+ 0x00300401,
+ 0xC0100400,
+ 0x4010,
+ 0x4300,
+ 0x000C0100,
+ 0x0080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+ 0x80040100,
+ 0x,
+ 0x0FF0,
+ 0x,
+ 0x0C010040,
+ 0x8000,
+ 0x18020080,
+ 0x,
+ 0x0800,
+ 0x00040020,
+ 0x06018060,
+ 0x4000,
+ 0x0C010040,
+ 0x0401,
+ 0x0030,
+ 0x,
+ 0x03004010,
+ 0x2000,
+ 0x06008020,
+ 0x02008000,
+ 0x0218,
+ 0x6008,
+ 0x01802008,
+ 0x1000,
+ 0x03004010,
+ 0x01004000,
+ 0x010C,
+ 0x3004,
+ 0x00C01004,
+ 0x0800,
+};
+
+const unsigned long iocsr_scan_chain3_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+ 0x2C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x0790,
+ 0x0802,
+ 0x0010,
+ 0x0A80,
+ 0x0790,
+ 0x0802,
+ 0x0010,
+ 0xC880,
+ 0x3001,
+ 0x00C00722,
+ 0x,
+ 0x0021,
+ 0x8204,
+ 0x0540,
+ 0x03C8,
+ 0x0401,
+ 0x0008,
+ 0x0540,
+ 0x03C8,
+ 0x0540,
+ 0x03C8,
+ 0xE440,
+ 0x1800,
+ 0x00600391,
+ 0x800E4400,
+ 0x0001,
+ 0x4002,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x7220,
+ 0x8C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C88,
+ 0x2300,
+ 0x0004,
+ 0x5067,
+ 0x0070,
+ 0x2459,
+ 0x1000,
+ 0xA034,
+ 0x0D01,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D,
+ 0x24906808,
+ 0x00A28340,
+ 0xD01A,
+ 0x06808A20,
+ 0x1004,
+ 0x0020,
+ 0x1004,
+ 0x0020,
+ 0x1500,
+ 0x0F20,
+ 0x1500,
+ 0x0F20,
+ 0x01FE,
+ 0x,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x,
+ 0x0A81,
+
Re: [U-Boot] [PATCH v4 3/3] ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board
On 11/13/2013 09:27 AM, Alban Bedel wrote: Add support for the new Tamonten™ NG platform from Avionic Design. Currently only I2C, MMC, USB and ethernet have been tested. Signed-off-by: Alban Bedel alban.be...@avionic-design.de --- V3: * Removed the retries from pmu_write() * Removed the not strictly needed power init V4: * Removed the unused PMU defines * Removed the useless #ifdef * Reworked the DTS to enable the device at the proper level * Re-numbered the i2c bus to match the kernel numbering Note that the kernel doesn't have a defined I2C bus numbering; any numbering that exists is a side-effect of the non-guaranteed I2C node enumeration order. That said, feel free to make the bus ordering in U-Boot be whatever you want. diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile I believe there's been a recent cleanup pass on all the Makefiles, so a lot of this boiler-plate needs to be removed to conform with the new style. Take a look at board/nvidia/*/Makefile for some examples. Aside from that, the series briefly, Reviewed-by: Stephen Warren swar...@nvidia.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCH v4 1/1] socfpga: Adding Freeze Controller driver
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v4
- Removed additional lines
- Single function call to freeze and thaw all channels
Changes for v3
- Removed unused macro in freeze_controller.h
Changes for v2
- Removed FREEZE_CONTROLLER_FSM_HW
- Removed the get_timer_count_masked and convert to use delay in us
- Used shorter local variables
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/freeze_controller.c | 216
arch/arm/cpu/armv7/socfpga/spl.c |9 +
.../include/asm/arch-socfpga/freeze_controller.h | 50 +
4 files changed, 276 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/freeze_controller.c
create mode 100644 arch/arm/include/asm/arch-socfpga/freeze_controller.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index dac2bbd..3e84a0c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c
b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
new file mode 100644
index 000..330b4aa
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include common.h
+#include asm/io.h
+#include asm/arch/freeze_controller.h
+#include asm/arch/timer.h
+#include asm/errno.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Default state from cold reset is FREEZE_ALL; the global
+ * flag is set to TRUE to indicate the IO banks are frozen
+ */
+static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
+ = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
+ FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
+
+/* Freeze HPS IOs */
+void sys_mgr_frzctrl_freeze_req(void)
+{
+ u32 ioctrl_reg_offset;
+ u32 reg_value;
+ u32 reg_cfg_mask;
+ u32 channel_id;
+
+ /* select software FSM */
+ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, freeze_controller_base-src);
+
+ /* Freeze channel 0 to 2 */
+ for (channel_id = 0; channel_id = 2; channel_id++) {
+ ioctrl_reg_offset = (u32)(
+ freeze_controller_base-vioctrl +
+ (channel_id SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+ /*
+* Assert active low enrnsl, plniotri
+* and niotri signals
+*/
+ reg_cfg_mask =
+ SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
+ | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+ | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+ clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
+
+ /*
+* Note: Delay for 20ns at min
+* Assert active low bhniotri signal and de-assert
+* active high csrdone
+*/
+ reg_cfg_mask
+ = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+ | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+ clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
+
+ /* Set global flag to indicate channel is frozen */
+ frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+ }
+
+ /* Freeze channel 3 */
+ /*
+* Assert active low enrnsl, plniotri and
+* niotri signals
+*/
+ reg_cfg_mask
+ = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+ clrbits_le32(freeze_controller_base-hioctrl, reg_cfg_mask);
+
+ /*
+* assert active low bhniotri nfrzdrv signals,
+* de-assert active high csrdone and assert
+* active high frzreg and nfrzdrv signals
+*/
+ reg_value = readl(freeze_controller_base-hioctrl);
+ reg_cfg_mask
+ = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
+ reg_value
+ = (reg_value ~reg_cfg_mask)
+ | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
+ |
Re: [U-Boot] [PATCH 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
Hi Sekhar :) On Wed, Nov 13, 2013 at 11:08 AM, Sekhar Nori nsek...@ti.com wrote: Hi Vaibhav, On 11/13/2013 7:38 PM, Vaibhav Bedia wrote: On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla lokeshvu...@ti.com wrote: [...] I checked with hardware folks. There is no register or some way to tell if VTT is present. It is not added in EEPROM also and I have no answer why it is not added in EEPROM..:( It is specific to boards using DDR3. So its good to have it in board files as I did it here instead of adding this check in emif file. That EEPROM is clearly not getting used the way i think it should be :\ I would have made a lot of noise to get details like this added there. The EEPROM was designed as a way to differentiate between different TI EVMs, not as a generic way to differentiate between various possible board hook-ups. Even if we did define it that way, why would all boards using AM437x have an onboard EEPROM? We could request this information be placed in EEPROM and see if hardware folks oblige, but I don't see how that's going to be used beyond TI EVMs. I understand the intent of customers to get rid of all the components they can to lower the cost. But if one just thinks about this a bit more, the current solution does a half-hearted attempt to differentiate the boards variants. It doesn't really capture the differences that are there and that is leading to hard coding to a certain extent. From AM335x boards we should now have a decent idea of what things change across boards that go into production. I don't think it makes sense to throw away all that knowledge and go ahead assuming we will never make a change. The request for change is just to future proof the current code and have the EEPROM actually help us do our jobs. Why? Because life's too short to keep worrying about why a board rev that a you pick up from a neighbor's desk doesn't boot, hooking up the JTAG to trace the DDR setup code, figure out what needs to change in the boot-loader, add in the appropriate check and then get to the task at hand ;) Regards, Vaibhav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/5] i.MX6 (DQ/DLS): consolidate mux and pad names
Hi Fabio,
On 11/13/2013 10:30 AM, Fabio Estevam wrote:
Hi Eric,
On Wed, Nov 13, 2013 at 3:23 PM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
Applied (whole patchset) to u-boot-imx, thanks !
Oops.
I was kinda hoping to get a head-not from Fabio on the
macro-fication of mx6[q|dl]_pins.h.
If we can get that, we can drop patch 5 of this patch set,
since the white-space changes all around...
I am not sure I understood the issue with patch 5.
In the RFC e-mail change regarding README.imx6-something,
I proposed that we replace the pad declaration form
currently in use:
enum {
MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(...)
};
with macros of this form so that they can be pre-pended
with MX6Q_ and MX6DL_ when we need both in an image
(SPL?) that can run on either variant of processor.
MX6_PAD_DECL(SD3_DAT2__USDHC3_DAT2, ...)
If we do this, then lining up the columns based on the
first form doesn't make much sense.
Section 3 of this post is the easiest place to see things:
http://lists.denx.de/pipermail/u-boot/2013-November/166678.html
This post has my list of oustanding questions:
http://lists.denx.de/pipermail/u-boot/2013-November/166876.html
And we're addressing #1 and 2:
1. Whether to turn declarations in mx6q_pins.h/mx6dl_pins.h
into macros
2. Whether to double-include the same in mx6-pins.h
3. Whether to define baseline pads (the 90% case) in a header
and double-include it, and
4. Whether to macro-fy the memory layout files like
1066mhz_4x128mx16.cfg so they can be used by imximage and gcc.
Regards,
Eric
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Re: [U-Boot] [PATCH] Separate EBV Socrates board from Altera Cyclone 5 board
Hi, Currently, the SOCFPGA SPL is customized through a set of handoff files which located at board folders. These handoff files are generated by tools based on board and user design in FPGA. With that, not much decision being made during run time based on the board. With this handoff and tools approach, it will shield off the complexity of hardware configuration and errors (if user change it manually without tools help). Thanks Which nice copy of our approach. :-) Hmmm... is it true? This approach being used since few years back at NIOS soft processor. Besides that, we are utilizing the SPL framework for our second stage boot loader. I believe you guys are not using SPL right? It seems you guys would need tools to generate and even build you guys own version of boot loader. It creates high dependency for user to your tools. Interesting discussion. :-) I believe we will use SPL at some point in future for Microblaze just because of easier maintenance . But will see. Yup, utilizing SPL will gain you the power of open source :) I don't understand your point regarding to tool dependency. For DTSes I believe you are also generating this structure from design tools or you can write it by hand. We are also generating U-boot configuration but if someone wants to write it by hand they can. I believe we have misalignment on the term used. For us, second stage bootloader is referring to the bootloader loaded by BootROM. I believe you guys are referring that as FSBL. For our solution, customer can just grab the code from git and build it using the normal U-Boot way (if they don't want to use the tools). With the SPL also, we are taking advantage of open source community power to make our second stage boot loader more powerful and user friendly to user. Our user can grab any drivers or leverage the supports from the open community too. I believe that is the power of open source :) We have the same for Microblaze and Zynq. Same as above, I believe both of us are using U-Boot. But for bootloader before U-Boot, we are using SPL while you guys using FSBL which is not SPL framework, right? With that, I believe you guys would need a proprietary tools to compile and build the FSBL. We would not have this dependency when building the SPL code. Thanks Chin Liang Cheers, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/5] i.MX6 (DQ/DLS): consolidate mux and pad names
Hi Eric,
On Wed, Nov 13, 2013 at 3:56 PM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
In the RFC e-mail change regarding README.imx6-something,
I proposed that we replace the pad declaration form
currently in use:
enum {
MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(...)
};
with macros of this form so that they can be pre-pended
with MX6Q_ and MX6DL_ when we need both in an image
(SPL?) that can run on either variant of processor.
MX6_PAD_DECL(SD3_DAT2__USDHC3_DAT2, ...)
I thinks this macro approach should work fine. Do we see any objections?
If we do this, then lining up the columns based on the
first form doesn't make much sense.
Understood it now. Thanks for clarifying.
Regards,
Fabio Estevam
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Re: [U-Boot] [PATCH] mx6: Add initial support for Carrier1 mx6solo board
Hi Stefano, On Sat, Nov 2, 2013 at 4:41 PM, Fabio Estevam feste...@gmail.com wrote: From: Fabio Estevam fabio.este...@freescale.com Solid Run designed the Carrier1 board based on mx6q/dl/solo. Add the initial support for the mx6 solo variant. More information about this hardware can be found at: http://cubox-i.com/ Signed-off-by: Fabio Estevam fabio.este...@freescale.com I would like to send another patch that depends on this one. Could you please let me know if you think this one looks good? Thanks, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/5] i.MX6 (DQ/DLS): consolidate mux and pad names
Hi Fabio,
On 11/13/2013 01:07 PM, Fabio Estevam wrote:
Hi Eric,
On Wed, Nov 13, 2013 at 3:56 PM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
In the RFC e-mail change regarding README.imx6-something,
I proposed that we replace the pad declaration form
currently in use:
enum {
MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(...)
};
with macros of this form so that they can be pre-pended
with MX6Q_ and MX6DL_ when we need both in an image
(SPL?) that can run on either variant of processor.
MX6_PAD_DECL(SD3_DAT2__USDHC3_DAT2, ...)
I thinks this macro approach should work fine. Do we
see any objections?
Not so far.
I think everybody would rather not have so much macro-fu,
but the only real alternatives are either lots of duplication
or an immediate big bang switch to have all boards
support all CPU variants.
Since we have some boards that are expected to be Solo-Only
or Quad-Only forever, we'd like to retain the single-variant
build without explicitly listing the pads as MX6Q_ or MX6DL_.
If we do this, then lining up the columns based on the
first form doesn't make much sense.
Understood it now. Thanks for clarifying.
Cool.
I'll re-base the macro patch I have floating here
and submit it officially.
It's mostly mechanical and easy to validate.
I'll also submit an updated patch for README.imx6,
but will keep it separate because I expect more suggestions
regarding the wording.
Regards,
Eric
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[U-Boot] pull-request: u-boot-mpc85xx/master
Tom,
The following changes since commit 63c4f17b2f8017d22241522a48c765073b8791b0:
cm_t35: use scf0403 driver (2013-11-12 10:12:07 +0100)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you to fetch changes up to 51abee64eee0186634858d1e6f91a65969c90125:
powerpc/85xx: fix broken cpu clock-frequency property (2013-11-13
12:41:28 -0800)
Laurentiu TUDOR (3):
powerpc/t4240: set pcie liodn in the correct register
powerpc/t4240: fix per pci endpoint liodn offsets
powerpc/85xx: fix broken cpu clock-frequency property
Prabhakar Kushwaha (1):
powerpc/t1040: enable PBL tool for T1040
Priyanka Jain (3):
powerpc/t1040: Update defines to support T1040SoC personalities
powerpc/t104xrdb: Add T1040RDB board support
powerpc/t104xrdb: Add T1042RDB_PI board support
Shengzhou Liu (1):
powerpc/p1010rdb: update readme for p1010rdb-pa and p1010rdb-pb
ramneek mehresh (1):
powerpc/83xx: Define USB1 and USB2 base addr for MPC834x
arch/powerpc/cpu/mpc85xx/Makefile | 10 +
arch/powerpc/cpu/mpc85xx/fdt.c |5 +-
arch/powerpc/cpu/mpc85xx/liodn.c | 25 +-
arch/powerpc/cpu/mpc85xx/t4240_ids.c |8 +-
arch/powerpc/include/asm/config_mpc85xx.h |3 +-
arch/powerpc/include/asm/immap_83xx.h |5 +
arch/powerpc/include/asm/immap_85xx.h |7 +-
.../p1010rdb/{README = README.P1010RDB-PA}|4 +-
board/freescale/p1010rdb/README.P1010RDB-PB| 188 ++
board/freescale/t1040qds/t1040_pbi.cfg | 27 +
board/freescale/t1040qds/t1040_rcw.cfg |7 +
board/freescale/t104xrdb/Makefile | 12 +
board/freescale/t104xrdb/README| 200 ++
board/freescale/t104xrdb/ddr.c | 132
board/freescale/t104xrdb/ddr.h | 76 +++
board/freescale/t104xrdb/law.c | 32 +
board/freescale/t104xrdb/pci.c | 23 +
board/freescale/t104xrdb/t104xrdb.c| 93 +++
board/freescale/t104xrdb/t104xrdb.h| 13 +
board/freescale/t104xrdb/tlb.c | 107 +++
boards.cfg |2 +
doc/README.p1010rdb| 198 --
drivers/net/fm/Makefile|3 +
include/configs/T1040QDS.h |2 +
include/configs/T1040RDB.h | 690
+++
include/configs/T1042RDB_PI.h | 694
26 files changed, 2353 insertions(+), 213 deletions(-)
rename board/freescale/p1010rdb/{README = README.P1010RDB-PA} (97%)
create mode 100644 board/freescale/p1010rdb/README.P1010RDB-PB
create mode 100644 board/freescale/t1040qds/t1040_pbi.cfg
create mode 100644 board/freescale/t1040qds/t1040_rcw.cfg
create mode 100644 board/freescale/t104xrdb/Makefile
create mode 100644 board/freescale/t104xrdb/README
create mode 100644 board/freescale/t104xrdb/ddr.c
create mode 100644 board/freescale/t104xrdb/ddr.h
create mode 100644 board/freescale/t104xrdb/law.c
create mode 100644 board/freescale/t104xrdb/pci.c
create mode 100644 board/freescale/t104xrdb/t104xrdb.c
create mode 100644 board/freescale/t104xrdb/t104xrdb.h
create mode 100644 board/freescale/t104xrdb/tlb.c
delete mode 100644 doc/README.p1010rdb
create mode 100644 include/configs/T1040RDB.h
create mode 100644 include/configs/T1042RDB_PI.h
Thanks.
York
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Re: [U-Boot] [U-Boot,1/6] video: remove AT91 legacy API from bus_vcxk
Dear Andreas Devel, Andreas Devel andreas.de...@googlemail.com writes: Signed-off-by: Andreas Bießmann andreas.de...@googlemail.com Acked-by: Jens Scharsig (BuS Elektronik) e...@bus-elektronik.de Acked-by: Anatolij Gustschin ag...@denx.de --- drivers/video/bus_vcxk.c | 15 --- 1 file changed, 15 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,2/6] i2c: switch from AT91 legacy to ATMEL legacy
Dear Andreas Devel, Andreas Devel andreas.de...@googlemail.com writes: Since the required API is gpio which is enclosed with CONFIG_ATMEL_LEGACY use that switch here. Signed-off-by: Andreas Bießmann andreas.de...@googlemail.com Acked-by: Heiko Schocher h...@denx.de --- drivers/i2c/soft_i2c.c |2 +- include/i2c.h |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,3/6] at91sam9m10g45ek: remove unused CONFIG_AT91_LEGACY
Dear Andreas Devel, Andreas Devel andreas.de...@googlemail.com writes: Signed-off-by: Andreas Bießmann andreas.de...@googlemail.com Acked-by: Bo Shen voice.s...@atmel.com --- include/configs/at91sam9m10g45ek.h |1 - 1 file changed, 1 deletion(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,4/6] snapper9260: remove unused AT91_LEGACY
Dear Andreas Devel, Andreas Devel andreas.de...@googlemail.com writes: Signed-off-by: Andreas Bießmann andreas.de...@googlemail.com --- include/configs/snapper9260.h |1 - 1 file changed, 1 deletion(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,6/6] at91: remove all occourances of CONFIG_AT91_LEGACY
Dear Andreas Devel, Andreas Devel andreas.de...@googlemail.com writes: Signed-off-by: Andreas Bießmann andreas.de...@googlemail.com --- arch/arm/include/asm/arch-at91/at91_pio.h | 33 arch/arm/include/asm/arch-at91/at91_pit.h | 16 -- arch/arm/include/asm/arch-at91/at91_pmc.h | 51 ++ arch/arm/include/asm/arch-at91/at91_spi.h |2 +- arch/arm/include/asm/arch-at91/at91_wdt.h | 21 arch/arm/include/asm/arch-at91/at91cap9.h | 69 - arch/arm/include/asm/arch-at91/at91sam9_smc.h | 60 - doc/README.at91-soc |7 +++ 8 files changed, 13 insertions(+), 246 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM: at91: sama5d3: add support for sama5d36 chip
Dear Josh Wu, Josh Wu josh...@atmel.com writes: The SAMA5D36 chip is the superset product of SAMA5D3x family. For detail information please refer to: http://www.atmel.com/Microsite/sama5d3/default.aspx Signed-off-by: Josh Wu josh...@atmel.com Acked-by: Bo Shen voice.s...@atmel.com --- arch/arm/cpu/armv7/at91/sama5d3_devices.c |4 +++- arch/arm/include/asm/arch-at91/sama5d3.h |3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,5/6] net: remove unused CONFIG_AT91_LEGACY
Dear Andreas Devel, Andreas Devel andreas.de...@googlemail.com writes: Signed-off-by: Andreas Bießmann andreas.de...@googlemail.com --- drivers/net/at91_emac.c |9 - 1 file changed, 9 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PULL] u-boot-atmel/master - u-boot-arm/master
Dear Albert Aribaud, please pull the following changes into u-boot-arm/master. The following changes since commit 56eb3da43fab5990a4b7bc118b76c7cae2ceb140: arm, am335x: update for the siemens boards (2013-11-12 09:53:59 -0500) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to 6182e9546aa602c97d55963e133c7e1a85ec: ARM: at91: sama5d3: add support for sama5d36 chip (2013-11-13 22:18:18 +0100) Andreas Bießmann (6): video: remove AT91 legacy API from bus_vcxk i2c: switch from AT91 legacy to ATMEL legacy at91sam9m10g45ek: remove unused CONFIG_AT91_LEGACY snapper9260: remove unused AT91_LEGACY net: remove unused CONFIG_AT91_LEGACY at91: remove all occourances of CONFIG_AT91_LEGACY Wu, Josh (1): ARM: at91: sama5d3: add support for sama5d36 chip arch/arm/cpu/armv7/at91/sama5d3_devices.c |4 +- arch/arm/include/asm/arch-at91/at91_pio.h | 33 arch/arm/include/asm/arch-at91/at91_pit.h | 16 -- arch/arm/include/asm/arch-at91/at91_pmc.h | 51 ++ arch/arm/include/asm/arch-at91/at91_spi.h |2 +- arch/arm/include/asm/arch-at91/at91_wdt.h | 21 arch/arm/include/asm/arch-at91/at91cap9.h | 69 - arch/arm/include/asm/arch-at91/at91sam9_smc.h | 60 - arch/arm/include/asm/arch-at91/sama5d3.h |3 ++ doc/README.at91-soc |7 +++ drivers/i2c/soft_i2c.c|2 +- drivers/net/at91_emac.c |9 drivers/video/bus_vcxk.c | 15 -- include/configs/at91sam9m10g45ek.h|1 - include/configs/snapper9260.h |1 - include/i2c.h |2 +- 16 files changed, 21 insertions(+), 275 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] imx6: fix random hang when download by usb
ROM did not invalidate L1 cache when download by usb
Need invalidate L1 cache before enable cache
Signed-off-by: Huang yongcai b20...@freescale.com
Signed-off-by: Frank Li frank...@freescale.com
---
arch/arm/cpu/armv7/mx6/soc.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index bc65767..2cbab4e 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -117,6 +117,8 @@ int arch_cpu_init(void)
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
+ /* Avoid random hang when download by usb */
+ invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
--
1.7.6
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[U-Boot] [PATCH 1/1] imx6: fix random hang when download by mfgtools
ROM did not invalidate L1 cache when download by usb
Need invalidate L1 cache before enable cache
Signed-off-by: Huang yongcai b20...@freescale.com
Signed-off-by: Frank Li frank...@freescale.com
---
arch/arm/cpu/armv7/mx6/soc.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index bc65767..2cbab4e 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -117,6 +117,8 @@ int arch_cpu_init(void)
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
+ /* Avoid random hang when download by usb */
+ invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
--
1.7.6
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Re: [U-Boot] u-boot gerrit server
On Tue, 2013-11-12 at 10:24 -0800, Vadim Bendebury wrote: On Tue, Nov 12, 2013 at 10:07 AM, Otavio Salvador ota...@ossystems.com.br wrote: On Tue, Nov 12, 2013 at 3:30 PM, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Otavio, On Tue, 12 Nov 2013 15:16:15 -0200, Otavio Salvador ota...@ossystems.com.br wrote: Hello Albert, On Tue, Nov 12, 2013 at 3:13 PM, Albert ARIBAUD albert.u.b...@aribaud.net wrote: On Tue, 12 Nov 2013 15:00:06 -0200, Otavio Salvador ota...@ossystems.com.br wrote: On Tue, Nov 12, 2013 at 2:55 PM, Vadim Bendebury (вб) vben...@google.com wrote: On Tue, Nov 12, 2013 at 8:47 AM, Otavio Salvador ota...@ossystems.com.br wrote: Besides, how people will 'transfer' one patch from one tree to another? This will happen quite often as someone mistakenly sending a patch for the wrong tree or custodians wanting the set to go together in a single merge... How is it handled today? Gerrit is after all just a means of keeping track of patches in a more efficient way, the rest could be similar to what is in use now, or enhanced using gerrit's features. Currently it is just reassigned in Patchwork; using multiple trees will complicate this. How about one branch per custodian? At my previous job we had a couple branches, one per distinct product. I am not aware of a way to 'transfer' a patch from one branch to another. There would not be such transfers -- we don't do this right now with our trees. We do merge requests, which means pulling two custodian repos into the same working repo, doing a merge between what are now two custodian branches, and pushing the result back onto one of the custodian trees. So here, if there is one branch per custodian, what we would need is the ability to merge one custodian branch into another. Right but currently you are not 'denied' to review a patch someone didn't put for you. The custodians as done 'on-the-fly' as each custodian takes his duties and process the patches and apply them, later updating patchwork. On the 'new Gerrit' workflow, if it is assigned for a branch/tree and this is mistakenly done, how it will be done? the patch can always be abandoned on gerrit, so no problem there. As for moving it to the right tree - either the original submitter could resubmit it, And the custodians would have to carefully check that it was actually the same patch that the previous custodian acked to go through the second custodian's tree... -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/t1040: enable PBL tool for T1040
On Oct 1, 2013, at 1:26 AM, Prabhakar Kushwaha wrote: Use a default RCW of protocol 0x66. A PBI configure file which uses CPC as 256KB SRAM. It can be used by PBL tool on T1040 to build a pbl boot image. Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] powerpc/p1010rdb: update readme for p1010rdb-pa and p1010rdb-pb
On Oct 11, 2013, at 8:02 AM, Shengzhou Liu wrote: - Remove duplicate doc/README.p1010rdb - Rename README to README.P1010RDB-PA - Add new README.P1010RDB-PB P1010RDB-PB is a variation of previous P1010RDB-PA board. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- v4: keep readme support for p1010rdb-pa v3: add frequency combination support v2: removed duplicate doc/README.p1010rdb Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc/t1040: Update defines to support T1040SoC personalities
On Oct 18, 2013, at 12:00 AM, Priyanka Jain wrote: T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com Signed-off-by: Priyanka Jain priyanka.j...@freescale.com --- Based on u-boot-mpc85xx/next branch. Changes for v2: Updated defined in arch/powerpc/cpu/mpc85xx/Makefile and drivers/net/fm/Makefiles as well. Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2][v2] powerpc/t104xrdb: Add T1040RDB board support
On Oct 18, 2013, at 4:49 AM, Priyanka Jain wrote: T1040RDB is Freescale Reference Design Board supporting the T1040 QorIQ Power Architecture™ processor. T1040RDB board Overview --- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: - PCI - SGMII - QSGMII - SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com Signed-off-by: Priyanka Jain priyanka.j...@freescale.com --- Based on u-boot-mpc85xx/next branch. Changes for v2: Updated description with I2c devices, some ethernet specifc configs and check of number of DDR controller to =1, as T1040 has only one DDR controller Applied to u-boot-mpc85xx/master after fixing Makefile. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2][v2] powerpc/t104xrdb: Add T1042RDB_PI board support
On Oct 18, 2013, at 4:49 AM, Priyanka Jain wrote: T1042RDB_PI is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture™ processor. T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit. The board is designed with low power features targeted for Printing Image Market. T1042RDB_PI is similar to T1040RDB board with few differences like it has video interface, supports T1042 personality T1042RDB_PI board Overview --- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Two on-board RGMII 10/100/1G ethernet ports. - SERDES Connections, 8 lanes supporting: — PCI — SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Video - DIU supports video at up to 1280x1024x32bpp - HDMI connector - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Device connected: EEPROM, thermal monitor, VID controller, RTC - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com Signed-off-by: Priyanka Jain priyanka.j...@freescale.com --- Based on u-boot-mpc85xx/next branch. Depends on patch at http://patchwork.ozlabs.org/patch/284452/ Changes for v2: Updated CONFIG_PPC to CONFIG_PPC_T1042 in boards,cfg file Updated ethernet specific configs Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/83xx: Define USB1 and USB2 base addr for MPC834x
On Oct 19, 2013, at 7:03 AM, Ramneek Mehresh wrote: Define base addresse for both MPH(USB1) and DR(USB2) controllers for MPC834x socs Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/t4240: set pcie liodn in the correct register
On Oct 23, 2013, at 5:20 AM, Laurentiu Tudor wrote: The liodn for the T4240's PCIE controller is no longer set through a register in the guts register block but with one in the PCIE register block itself. Use the already existing SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com Cc: Scott Wood scottw...@freescale.com Cc: York Sun york...@freescale.com --- Based on: git://git.denx.de/u-boot-mpc85xx.git master Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/t4240: fix per pci endpoint liodn offsets
On Oct 23, 2013, at 5:20 AM, Laurentiu Tudor wrote: Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = 0 0xffcd 0xffcf 0xffd1 0xffd3 0xffd5 0xffd7 0xffd9 0xffdb; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com Cc: Scott Wood scottw...@freescale.com Cc: York Sun york...@freescale.com --- Based on: git://git.denx.de/u-boot-mpc85xx.git master Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/85xx: fix broken cpu clock-frequency property
On Oct 23, 2013, at 5:20 AM, Laurentiu Tudor wrote: When indexing freqProcessor[] we use the first value in the cpu's reg property, which on new e6500 cores IDs the threads. But freqProcessor[] should be indexed with a core index so, when fixing the clock-frequency cpu node property, access the freqProcessor[] with the core index derived from the reg' property. If we don't do this, last half of the cpu nodes will have broken clock-frequency values. Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com Cc: York Sun york...@freescale.com --- Based on: git://git.denx.de/u-boot-mpc85xx.git master Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] i.MX6 (DQ/DLS): use macros for mux and pad declarations
Updates i.MX6DQ and i.MXDLS mux/pad declarations to be declared using macros to allow their use in a binary supporting all four variants of the pin-compatible processors. This patch set was broken into two parts to allow validation using git show --word-diff. The patches apply to u-boot-imx/master with commit a31d3efa (a previous and superfluous white-space change) reverted. Compile-tested against all mx6 boards. Run-time tested against nitrogen6q. Eric Nelson (2): i.MX6 (DQ/DLS): use macros for mux and pad declarations i.MX6DQ/DLS: whitespace: Align MX6_PAD_DECL columns arch/arm/include/asm/arch-mx6/mx6-pins.h | 33 +- arch/arm/include/asm/arch-mx6/mx6dl_pins.h| 2145 - arch/arm/include/asm/arch-mx6/mx6q_pins.h | 2054 --- board/barco/titanium/titanium.c |2 +- board/freescale/mx6qarm2/mx6qarm2.c |2 +- board/freescale/mx6qsabreauto/mx6qsabreauto.c |2 +- 6 files changed, 2127 insertions(+), 2111 deletions(-) -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: merge commonly-defined PLATFORM_RELFLAGS
All arch/arm/cpu/${CPU}/config.mk had the same
PLATFORM_RELFLAGS definitions.
This commit merges them into arch/arm/config.mk.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
arch/arm/config.mk | 4 +++-
arch/arm/cpu/arm1136/config.mk | 7 ---
arch/arm/cpu/arm1176/config.mk | 8
arch/arm/cpu/arm720t/config.mk | 8
arch/arm/cpu/arm920t/config.mk | 7 ---
arch/arm/cpu/arm926ejs/config.mk | 7 ---
arch/arm/cpu/arm946es/config.mk | 7 ---
arch/arm/cpu/arm_intcm/config.mk | 7 ---
arch/arm/cpu/armv7/config.mk | 8
arch/arm/cpu/ixp/config.mk | 8
arch/arm/cpu/pxa/config.mk | 7 ---
arch/arm/cpu/sa1100/config.mk| 7 ---
12 files changed, 3 insertions(+), 82 deletions(-)
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index bdabcf4..e2ff323 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -17,7 +17,9 @@ endif
LDFLAGS_FINAL += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
--fno-common -ffixed-r9 -msoft-float
+-fno-common -ffixed-r9 -msoft-float \
+$(call cc-option,-mshort-load-bytes,\
+$(call cc-option,-malignment-traps,))
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk
index b4d396d..f74228c 100644
--- a/arch/arm/cpu/arm1136/config.mk
+++ b/arch/arm/cpu/arm1136/config.mk
@@ -7,13 +7,6 @@
# Make ARMv5 to allow more compilers to work, even though its v6.
PLATFORM_CPPFLAGS += -march=armv5
-# =
-#
-# Supply options according to compiler version
-#
-# =
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call
cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_SPL
diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk
index f4631cb..5dc2ebb 100644
--- a/arch/arm/cpu/arm1176/config.mk
+++ b/arch/arm/cpu/arm1176/config.mk
@@ -7,11 +7,3 @@
# Make ARMv5 to allow more compilers to work, even though its v6.
PLATFORM_CPPFLAGS += -march=armv5t
-# =
-#
-# Supply options according to compiler version
-#
-# =
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
- $(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk
index 2581f0a..772fb41 100644
--- a/arch/arm/cpu/arm720t/config.mk
+++ b/arch/arm/cpu/arm720t/config.mk
@@ -7,11 +7,3 @@
#
PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
-# =
-#
-# Supply options according to compiler version
-#
-# =
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
- $(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk
index 67537dc..799afff 100644
--- a/arch/arm/cpu/arm920t/config.mk
+++ b/arch/arm/cpu/arm920t/config.mk
@@ -6,10 +6,3 @@
#
PLATFORM_CPPFLAGS += -march=armv4
-# =
-#
-# Supply options according to compiler version
-#
-# =
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call
cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
index 12b0d09..4d9895f 100644
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -6,13 +6,6 @@
#
PLATFORM_CPPFLAGS += -march=armv5te
-# =
-#
-# Supply options according to compiler version
-#
-# =
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call
cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_SPL
diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk
index eb81a57..438668d 100644
--- a/arch/arm/cpu/arm946es/config.mk
+++ b/arch/arm/cpu/arm946es/config.mk
@@ -6,10 +6,3 @@
#
PLATFORM_CPPFLAGS += -march=armv4
-# =
-#
-# Supply options according to compiler version
-#
-#
Re: [U-Boot] [U-Boot, v2, 1/3] am33xx: elm: add support for BCH16_ECC - ELM driver updates
On Tue, Sep 10, 2013 at 12:55:06PM +0530, pekon gupta wrote: With increase in NAND flash densities occurence of bit-flips has increased. Thus stronger ECC schemes are required for detecting and correcting multiple simultaneous bit-flips in same NAND page. But stronger ECC schemes have large ECC syndrome which require more space in OOB/Spare. This patch add support for BCH16_ECC: (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page = 26 * (page-size / 512) Signed-off-by: Pekon Gupta pe...@ti.com --- arch/arm/cpu/armv7/am33xx/elm.c| 95 ++ arch/arm/include/asm/arch-am33xx/elm.h | 16 +++--- 2 files changed, 69 insertions(+), 42 deletions(-) omap_gpmc.c: In function 'omap_correct_data_bch': omap_gpmc.c:550:19: error: conversion to incomplete type It looks like this is fixed in patch 2/3, but this breaks bisectability. Also, does this code really belong under arch/arm rather than drivers/mtd/nand? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Microblaze and Sparc boards are broken because of common timer func
Hello Michal. This should be fixed by this patch - at least for microblaze. commit 65ba7add0d609bbd035b8d42fafdaf428ac24751 Author: Rob Herring rob.herr...@calxeda.com Date: Fri Nov 8 08:40:43 2013 -0600 time: add weak annotation to timer_read_counter declaration A weak annotation is needed in order to prevent link errors when get_ticks is overridden. This fixes sandbox build. Signed-off-by: Rob Herring rob.herr...@calxeda.com No. I tried both the current u-boot/master and commit 65ba7add0d, but Microblaze board failed with the same error message. Look at this log - uboot section. http://www.monstr.eu/wiki/doku.php?id=log:2013-11-12_13_29_22 Which toolchain do you use? Microblaze crosstools I use is available at: http://dev.gentoo.org/~vapier/u-boot/microblaze.tar.xz Before commit 8dfafdde88eb, I could build the microblaze-generic board with it. But I can't build for the current u-boot/master. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 2/3] mtd: nand: omap: add support for BCH16_ECC - NAND driver updates
On Tue, Sep 10, 2013 at 12:55:07PM +0530, pekon gupta wrote:
With increase in NAND flash densities occurence of bit-flips has increased.
Thus stronger ECC schemes are required for detecting and correcting multiple
simultaneous bit-flips in same NAND page. But stronger ECC schemes have large
ECC syndrome which require more space in OOB/Spare.
This patch add support for BCH16_ECC:
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page = 26 * (page-size / 512)
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/include/asm/arch-am33xx/cpu.h | 15 -
arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 4 +-
drivers/mtd/nand/omap_gpmc.c | 87
+++-
include/mtd/mtd-abi.h| 3 +-
4 files changed, 90 insertions(+), 19 deletions(-)
This doesn't apply cleanly.
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 10b56e0..1de92e6 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -63,7 +63,16 @@ struct gpmc_cs {
};
struct bch_res_0_3 {
- u32 bch_result_x[4];
+ u32 bch_result0;
+ u32 bch_result1;
+ u32 bch_result2;
+ u32 bch_result3;
+};
Is this really an improvement?
It would also be nice if headers for things in drivers/mtd/nand weren't
in arch.
-Scott
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Re: [U-Boot] [U-Boot, 1/5] MTD: nand: increase the max eccpos size to 448 to support 8k page nand
On Fri, Oct 18, 2013 at 05:46:30PM +0800, Wu, Josh wrote:
For example, Micron MT29F64G08CBAAAWP has 8192 bytes page with 448 byte
oob. It needs 24bit ecc per page.
If 24bit error correction per 1024 bytes need extra 42 bytes in oob.
That means we need eccpos array size is 336 byte.
Signed-off-by: Josh Wu josh...@atmel.com
---
include/mtd/mtd-abi.h |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
index d51c1ab..f6f7370 100644
--- a/include/mtd/mtd-abi.h
+++ b/include/mtd/mtd-abi.h
@@ -156,13 +156,14 @@ struct nand_oobfree {
};
#define MTD_MAX_OOBFREE_ENTRIES 8
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE448
/*
* ECC layout control structure. Exported to userspace for
* diagnosis and to allow creation of raw images
*/
struct nand_ecclayout {
uint32_t eccbytes;
- uint32_t eccpos[128];
+ uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
uint32_t oobavail;
struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
};
See http://patchwork.ozlabs.org/patch/280488/
-Scott
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[U-Boot] [PATCH] mtd: Add _LARGE to MTD_MAX_*_ENTRIES
This makes the names match current Linux source, and resolves
a conflict between
http://patchwork.ozlabs.org/patch/280488/
and
http://patchwork.ozlabs.org/patch/284513/
The former was posted first and is closer to matching Linux, but unlike
Linux it does not add _LARGE to the names. The second adds _LARGE to
one of the names, and depends on it in a subsequent patch
(http://patchwork.ozlabs.org/patch/284512/).
I do wish this just used ARRAY_SIZE(), though. :-P
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Prabhakar Kushwaha prabha...@freescale.com
Cc: Josh Wu josh...@atmel.com
Cc: Lukasz Majewski l.majew...@samsung.com
---
Depends on http://patchwork.ozlabs.org/patch/280488/
---
drivers/mtd/onenand/onenand_base.c | 15 ++-
include/linux/mtd/mtd.h| 8
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/onenand/onenand_base.c
b/drivers/mtd/onenand/onenand_base.c
index 067f8ef..979e4af 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -761,7 +761,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd,
uint8_t *buf,
uint8_t *oob_buf = this-oob_buf;
free = this-ecclayout-oobfree;
- for (i = 0; i MTD_MAX_OOBFREE_ENTRIES free-length; i++, free++) {
+ for (i = 0; i MTD_MAX_OOBFREE_ENTRIES_LARGE free-length;
+i++, free++) {
if (readcol = lastgap)
readcol += free-offset - lastgap;
if (readend = lastgap)
@@ -770,7 +771,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd,
uint8_t *buf,
}
this-read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0,
mtd-oobsize);
free = this-ecclayout-oobfree;
- for (i = 0; i MTD_MAX_OOBFREE_ENTRIES free-length; i++, free++) {
+ for (i = 0; i MTD_MAX_OOBFREE_ENTRIES_LARGE free-length;
+i++, free++) {
int free_end = free-offset + free-length;
if (free-offset readend free_end readcol) {
int st = max_t(int,free-offset,readcol);
@@ -1356,7 +1358,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd,
u_char *oob_buf,
unsigned int i;
free = this-ecclayout-oobfree;
- for (i = 0; i MTD_MAX_OOBFREE_ENTRIES free-length; i++, free++) {
+ for (i = 0; i MTD_MAX_OOBFREE_ENTRIES_LARGE free-length;
+i++, free++) {
if (writecol = lastgap)
writecol += free-offset - lastgap;
if (writeend = lastgap)
@@ -1364,7 +1367,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd,
u_char *oob_buf,
lastgap = free-offset + free-length;
}
free = this-ecclayout-oobfree;
- for (i = 0; i MTD_MAX_OOBFREE_ENTRIES free-length; i++, free++) {
+ for (i = 0; i MTD_MAX_OOBFREE_ENTRIES_LARGE free-length;
+i++, free++) {
int free_end = free-offset + free-length;
if (free-offset writeend free_end writecol) {
int st = max_t(int,free-offset,writecol);
@@ -2750,7 +2754,8 @@ int onenand_scan(struct mtd_info *mtd, int maxchips)
* the out of band area
*/
this-ecclayout-oobavail = 0;
- for (i = 0; i MTD_MAX_OOBFREE_ENTRIES
+
+ for (i = 0; i MTD_MAX_OOBFREE_ENTRIES_LARGE
this-ecclayout-oobfree[i].length; i++)
this-ecclayout-oobavail +=
this-ecclayout-oobfree[i].length;
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 3a18f8f..5004909 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -96,8 +96,8 @@ struct mtd_oob_ops {
uint8_t *oobbuf;
};
-#define MTD_MAX_OOBFREE_ENTRIES32
-#define MTD_MAX_ECCPOS_ENTRIES 640
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE 640
/*
* ECC layout control structure. Exported to userspace for
@@ -105,9 +105,9 @@ struct mtd_oob_ops {
*/
struct nand_ecclayout {
uint32_t eccbytes;
- uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES];
+ uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
uint32_t oobavail;
- struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
+ struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
};
struct mtd_info {
--
1.8.1.2
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[U-Boot] [PATCH] imx: Define common routines to set cpu and board environment variables
These can be used in bootcmd to produce DTB file names.
set_board_env() allows over-ride for use when a developing custom
DTB files. Both are declared __weak to allow complete override by
a board.
Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com
---
I'm feeling like I missed something here. Routines in imx-common/cpu.c
are shared between various i.MX processors, but there doesn't appear
to be a common header file.
It seems that arch/arm/include/asm/imx-common.h should be present
but isn't. Am I missing something?
I also think there should be a way we could pull this into multiple
boards without adding a full-up board_late_init() function into
each board file, but tracing the init sequence, I'm not seeing an
architecture-specific spot after env_init.
arch/arm/imx-common/cpu.c | 15 +--
arch/arm/include/asm/arch-mx6/sys_proto.h | 9 +
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 0cd2538..5e13c43 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -99,8 +99,6 @@ unsigned imx_ddr_size(void)
}
#endif
-#if defined(CONFIG_DISPLAY_CPUINFO)
-
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
@@ -121,6 +119,19 @@ const char *get_imx_type(u32 imxtype)
}
}
+void __weak set_cpu_env()
+{
+ setenv(cpu,get_imx_type(cpu_type(get_cpu_rev(;
+}
+
+void __weak set_board_env()
+{
+ char *old = getenv(board);
+ if (!old)
+ setenv(board, CONFIG_SYS_BOARD);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 cpurev;
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h
b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 8c21364..6d9b1f2 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -27,8 +27,17 @@ u32 get_cpu_rev(void);
#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
const char *get_imx_type(u32 imxtype);
+
unsigned imx_ddr_size(void);
+/* Set standard board and cpu environment variables.
+ * for use in loading DTB files.
+ *
+ * Call these in board_late_init if needed
+ */
+void set_cpu_env();
+void set_board_env();
+
void set_vddsoc(u32 mv);
/*
--
1.8.1.2
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Re: [U-Boot] [U-Boot, 2/5] mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flash
On Fri, Oct 18, 2013 at 05:46:31PM +0800, Wu, Josh wrote:
@@ -840,6 +841,13 @@ static int atmel_pmecc_nand_init_params(struct nand_chip
*nand,
nand-ecc.steps = 1;
nand-ecc.bytes = host-pmecc_bytes_per_sector *
host-pmecc_sector_number;
+
+ if (nand-ecc.bytes MTD_MAX_ECCPOS_ENTRIES_LARGE) {
+ dev_err(host-dev, too large eccpos entries. max
support ecc.bytes is %d\n,
+ MTD_MAX_ECCPOS_ENTRIES_LARGE);
+ return -EINVAL;
+ }
I won't hold up acceptance over this, but wouldn't it be more useful to
show the actual ecc.bytes rather than the constant limit which could be
easily looked up in the source? Or better, print both.
-Scott
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[U-Boot] [PATCH V2] imx: Define common routines to set cpu and board environment variables
These can be used in bootcmd to produce DTB file names.
set_board_env() allows over-ride for use when a developing custom
DTB files.
Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com
---
V2 adds void to the function declarations and definitions and adds
a blank to keep checkpatch clean.
I'm feeling like I missed something here. Routines in imx-common/cpu.c
are shared between various i.MX processors, but there doesn't appear
to be a common header file.
It seems that arch/arm/include/asm/imx-common.h should be present
but isn't. Am I missing something?
I also think there should be a way we could pull this into multiple
boards without adding a full-up board_late_init() function into
each board file, but tracing the init sequence, I'm not seeing an
architecture-specific spot after env_init.
arch/arm/imx-common/cpu.c | 15 +--
arch/arm/include/asm/arch-mx6/sys_proto.h | 9 +
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 0cd2538..4214946 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -99,8 +99,6 @@ unsigned imx_ddr_size(void)
}
#endif
-#if defined(CONFIG_DISPLAY_CPUINFO)
-
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
@@ -121,6 +119,19 @@ const char *get_imx_type(u32 imxtype)
}
}
+void __weak set_cpu_env(void)
+{
+ setenv(cpu, get_imx_type(cpu_type(get_cpu_rev(;
+}
+
+void __weak set_board_env(void)
+{
+ char *old = getenv(board);
+ if (!old)
+ setenv(board, CONFIG_SYS_BOARD);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 cpurev;
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h
b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 8c21364..f58ebc3 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -27,8 +27,17 @@ u32 get_cpu_rev(void);
#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
const char *get_imx_type(u32 imxtype);
+
unsigned imx_ddr_size(void);
+/* Set standard board and cpu environment variables.
+ * for use in loading DTB files.
+ *
+ * Call these in board_late_init if needed
+ */
+void set_cpu_env(void);
+void set_board_env(void);
+
void set_vddsoc(u32 mv);
/*
--
1.8.1.2
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Re: [U-Boot] [U-Boot,PATCHv4] Optimized nand_read_buf for kirkwood
On Mon, Aug 26, 2013 at 02:10:56PM +0200, Phil Sutter wrote: From: Nico Erfurth n...@erfurth.eu The basic idea is taken from the linux-kernel, but further optimized. First align the buffer to 8 bytes, then use ldrd/strd to read and store in 8 byte quantities, then do the final bytes. Tested using: 'date ; nand read.raw 0xE0 0x0 0x1 ; date'. Without this patch, NAND read of 132MB took 49s (~2.69MB/s). With this patch in place, reading the same amount of data was done in 27s (~4.89MB/s). So read performance is increased by ~80%! Signed-off-by: Nico Erfurth n...@erfurth.eu Tested-by: Phil Sutter phil.sut...@viprinet.com Cc: Prafulla Wadaskar prafu...@marvell.com --- Changed since V3: - fixed author --- drivers/mtd/nand/kirkwood_nand.c | 32 1 file changed, 32 insertions(+) I tried to build-test this, and I couldn't find any board that defines CONFIG_NAND_KIRKWOOD. The patch that removed it was commit b5befd8211b54ae2d2fca3fbed061c879951ceaa (arm/km: fix u-boot.kwb build breakage), over two years ago. It's not clear whether the removal was intentional. What target did you use to test this? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 1/4] mtd: nand: add NAND_BUSWIDTH_AUTO to autodetect bus width
On Tue, Sep 10, 2013 at 06:57:05PM +0530, pekon gupta wrote: From: Matthieu CASTET matthieu.cas...@parrot.com This patch is slightly modified from following linux patch http://lists.infradead.org/pipermail/linux-mtd/2012-November/044803.html Which is now commit 64b37b2a63eb2f80b65c7185f0013f8ffc637ae3 So retaining the authorship to Matthieu CASTET matthieu.cas...@parrot.com *Modifications from original patch* reset chip-read_byte, chip-read_buf, chip-write_buf before setting defaults. Why does U-Boot need this if Linux doesn't? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/10 V6] Exynos5420: Add clock initialization for 5420
Dear Rajeshwari,
On 13 November 2013 20:17, Rajeshwari Birje rajeshwari.bi...@gmail.comwrote:
Hi Minkyu Kang,
Thank you for comments,
On Wed, Nov 13, 2013 at 8:15 AM, Minkyu Kang proms...@gmail.com wrote:
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde rajeshwar...@samsung.com
wrote:
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Corrected the multiline commenting style
Changes in V5:
- None
Changes in V6:
- None
arch/arm/cpu/armv7/exynos/clock.c | 270 -
arch/arm/cpu/armv7/exynos/clock_init.h | 17 +
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++-
arch/arm/cpu/armv7/exynos/exynos5_setup.h | 740
+++--
arch/arm/include/asm/arch-exynos/clk.h | 1 +
arch/arm/include/asm/arch-exynos/clock.h | 494 +
6 files changed, 1673 insertions(+), 201 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 36fedd6..b52e61a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
r, unsigned int k)
freq = CONFIG_SYS_CLK_FREQ;
- if (pllreg == EPLL) {
+ if (pllreg == EPLL || pllreg == RPLL) {
k = k 0x;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / PLL_DIV_65536) * (freq / (p * (1
s)));
@@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned
int
r, unsigned int k)
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
- else if (proid_is_exynos5250())
+ else if (cpu_is_exynos5())
please don't mix proid_is... and cpu_is...
Since both 5420 and 5250 need same value added cpu_is_exynos5(),
instead of doing a or of both.
I know, but this if statement for proid..
then, you should use same statement.
you can do this.
else if (proid_is_exynos5250() || prois_is_exynos5420())
or
if (cpu_is_exynos4()) {
if (proid_is) {
} else if (proid_is) {
}
} else if (cpu_is_exynos5()) {
.
}
Thanks,
Minkyu Kang.
--
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[U-Boot] [PATCH] tools: imls: Remove a broken and unused tool.
It looks like tools/imls/Makefile is invoked from nowhere. And also it is broken. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- I tried to build tools/imls/Makefile somehow. But compile failed with the following error message: tools/imls/imls.c:17:22: fatal error: asm/page.h: No such file or directory #include asm/page.h ^ compilation terminated. make[1]: *** [imls.o] Error 1 I posted an e-mail How to build tools/imls? to the ML, but there has been no reply. So I decided to delete this tool because I don't want to make effort to adjust broken tools to Kbuild. If someone still uses this tool, please stop me. tools/imls/Makefile | 84 - tools/imls/README | 41 - tools/imls/imls.c | 256 3 files changed, 381 deletions(-) delete mode 100644 tools/imls/Makefile delete mode 100644 tools/imls/README delete mode 100644 tools/imls/imls.c diff --git a/tools/imls/Makefile b/tools/imls/Makefile deleted file mode 100644 index b045df2..000 --- a/tools/imls/Makefile +++ /dev/null @@ -1,84 +0,0 @@ -# -# (C) Copyright 2009 Marco Stornelli marco.storne...@gmail.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -# Generated executable files -BIN_FILES-y += imls - -# Source files which exist outside the tools/imls directory -EXT_OBJ_FILES-y += lib/crc32.o -EXT_OBJ_FILES-y += lib/md5.o -EXT_OBJ_FILES-y += lib/sha1.o -EXT_OBJ_FILES-y += common/image.o - -# Source files located in the tools/imls directory -OBJ_FILES-y += imls.o - -# Flattened device tree objects -LIBFDT_OBJ_FILES-y += fdt.o -LIBFDT_OBJ_FILES-y += fdt_ro.o -LIBFDT_OBJ_FILES-y += fdt_rw.o -LIBFDT_OBJ_FILES-y += fdt_strerror.o -LIBFDT_OBJ_FILES-y += fdt_wip.o - -# now $(obj) is defined -SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) -BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y))) -LIBFDT_OBJS:= $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y)) - -# -# Compile for a hosted environment on the target -# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps -# -HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \ - -idirafter $(SRCTREE)/arch/$(ARCH)/include \ - -idirafter $(OBJTREE)/include \ - -I $(SRCTREE)/lib/libfdt \ - -I $(SRCTREE)/tools \ - -DUSE_HOSTCC -D__KERNEL_STRICT_NAMES - -ifeq ($(MTD_VERSION),old) -HOSTCPPFLAGS += -DMTD_OLD -endif - -all: $(BINS) - -$(obj)imls:$(obj)imls.o $(obj)crc32.o $(obj)image.o $(obj)md5.o \ - $(obj)sha1.o $(LIBFDT_OBJS) - $(CC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(STRIP) $@ - -# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED -$(obj)image.o: $(SRCTREE)/common/image.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $ - -$(obj)imls.o: $(SRCTREE)/tools/imls/imls.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $ - -# Some of the tool objects need to be accessed from outside the tools/imls directory -$(obj)%.o: $(SRCTREE)/common/%.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $ - -$(obj)%.o: $(SRCTREE)/lib/%.c - $(CC) -g $(HOSTCFLAGS) -c -o $@ $ - -$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $ - -clean: - rm -rf *.o imls - -# - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -# diff --git a/tools/imls/README b/tools/imls/README deleted file mode 100644 index 9adf923..000 --- a/tools/imls/README +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2009 Marco Stornelli marco.storne...@gmail.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -IMLS -- - -imls is an implementation of a Linux command line tool to access -to raw flash partitions and list images made with mkimage command. - -For building against older versions of the MTD headers (meaning before -v2.6.8-rc1) it is required to pass the argument MTD_VERSION=old to -make. - -Usage examples --- - -1) Flash with sectors of 128KiB and 32 sectors: - - imls -c 32 -s 131072 /dev/mtd0 -Searching... -Image Name: foo -Created: Fri Apr 10 18:11:30 2009 -Image Type: Intel x86 Linux Standalone Program (uncompressed) -Data Size:10716 Bytes = 10.46 kB = 0.01 MB -Load Address: -Entry Point: - -2) Flash with sectors of 64KiB and 128 sectors and with a search offset of one -sector: - - imls -o 1 -c 128 -s 65536 /dev/mtd0 -Searching... -Image Name: foo -Created: Fri Apr 10 18:11:30 2009 -Image Type: Intel x86 Linux Standalone Program (uncompressed) -Data Size:10716 Bytes = 10.46 kB = 0.01 MB -Load Address: -Entry Point: diff --git
[U-Boot] [PATCH] tools: updater: Remove remainders of dead board
tools/updater needs board/MAI/AmigaOneG3SE board for compiling. But AmigaOneG3SE board was already deleted by Commit 953b7e6. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- In order to compile tools/updater, we need AmigaOneG3SE board. See tools/updater/Makefile $(obj)memio.S: rm -f $(obj)memio.c ln -s $(SRCTREE)/board/MAI/AmigaOneG3SE/memio.S $(obj)memio.S But AmigaOneG3SE has gone to README.scrapyard. Makefile | 5 +- tools/updater/Makefile| 89 --- tools/updater/cmd_flash.c | 401 - tools/updater/ctype.c | 40 --- tools/updater/dummy.c | 1 - tools/updater/flash.c | 168 tools/updater/flash_hw.c | 643 -- tools/updater/junk| 1 - tools/updater/ppcstring.S | 213 --- tools/updater/string.c| 340 tools/updater/update.c| 63 - tools/updater/utils.c | 148 --- 12 files changed, 1 insertion(+), 2111 deletions(-) delete mode 100644 tools/updater/Makefile delete mode 100644 tools/updater/cmd_flash.c delete mode 100644 tools/updater/ctype.c delete mode 100644 tools/updater/dummy.c delete mode 100644 tools/updater/flash.c delete mode 100644 tools/updater/flash_hw.c delete mode 100644 tools/updater/junk delete mode 100644 tools/updater/ppcstring.S delete mode 100644 tools/updater/string.c delete mode 100644 tools/updater/update.c delete mode 100644 tools/updater/utils.c diff --git a/Makefile b/Makefile index 1f499c5..cde4678 100644 --- a/Makefile +++ b/Makefile @@ -593,9 +593,6 @@ $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend $(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend $(MAKE) -C spl all CONFIG_TPL_BUILD=y -updater: - $(MAKE) -C tools/updater all - # Explicitly make _depend in subdirs containing multiple targets to prevent # parallel sub-makes creating .depend files simultaneously. depend dep:$(TIMESTAMP_FILE) $(VERSION_FILE) \ @@ -738,7 +735,7 @@ else# !config.mk all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ $(filter-out tools,$(SUBDIRS)) \ -updater depend dep tags ctags etags cscope $(obj)System.map: +depend dep tags ctags etags cscope $(obj)System.map: @echo System not configured - see README 2 @ exit 1 diff --git a/tools/updater/Makefile b/tools/updater/Makefile deleted file mode 100644 index 19dd5eb..000 --- a/tools/updater/Makefile +++ /dev/null @@ -1,89 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, w...@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -LOAD_ADDR = 0x4 - -include $(TOPDIR)/config.mk - -PROG = $(obj)updater -IMAGE = $(obj)updater.image - -COBJS = update.o flash.o flash_hw.o utils.o cmd_flash.o string.o ctype.o dummy.o -COBJS_LINKS= stubs.o -AOBJS = ppcstring.o -AOBJS_LINKS= memio.o - -OBJS := $(addprefix $(obj),$(COBJS) $(COBJS_LINKS) $(AOBJS) $(AOBJS_LINKS)) -SRCS := $(COBJS:.o=.c) $(AOBJS:.o=.S) $(addprefix $(obj), $(COBJS_LINKS:.o:.c) $(AOBJS_LINKS:.o:.S)) - -CPPFLAGS += -I$(TOPDIR) -I$(TOPDIR)/board/MAI/AmigaOneG3SE -CFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE -AFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE - -DEPS = $(OBJTREE)/u-boot.bin $(OBJTREE)/tools/mkimage -ifneq ($(DEPS),$(wildcard $(DEPS))) -$(error updater: Missing required objects, please run regular build first) -endif - -all: $(obj).depend $(PROG) $(IMAGE) - -# - -$(obj)%.srec: %.o $(LIB) - $(LD) -g -Ttext $(LOAD_ADDR) -o $(:.o=) -e $(:.o=) $ $(LIB) - $(OBJCOPY) -O srec $(:.o=) $@ - -$(obj)%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $ - -$(obj)%.o: %.S - $(CC) $(AFLAGS) -c -o $@ $ - -$(obj)memio.o: $(obj)memio.S - $(CC) $(AFLAGS) -c -o $@ $ - -$(obj)memio.S: - rm -f $(obj)memio.c - ln -s $(SRCTREE)/board/MAI/AmigaOneG3SE/memio.S $(obj)memio.S - -$(obj)stubs.o: $(obj)stubs.c - $(CC) $(CFLAGS) -c -o $@ $ - -$(obj)stubs.c: - rm -f $(obj)stubs.c - ln -s $(SRCTREE)/examples/stubs.c $(obj)stubs.c - -# - -$(obj)updater: $(OBJS) - $(LD) -g -Ttext $(LOAD_ADDR) -o $(obj)updater -e _main $(OBJS) - $(OBJCOPY) -O binary $(obj)updater $(obj)updater.bin - -$(obj)updater.image: $(obj)updater $(OBJTREE)/u-boot.bin - cat /tmp/tempimage $(obj)updater.bin junk $(OBJTREE)/u-boot.bin - $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \ - -e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \ - -n Firmware Updater -d /tmp/tempimage $(obj)updater.image - rm /tmp/tempimage - cp $(obj)updater.image /tftpboot - -(obj)updater.image2: $(obj)updater $(OBJTREE)/u-boot.bin -
Re: [U-Boot] [PATCH 07/10 V6] DTS: Add dts support for SMDK5420
Dear Rajeshwari,
On 13 November 2013 13:26, Rajeshwari Birje rajeshwari.bi...@gmail.comwrote:
Hi Minkyu Kang,
Thank you for comments.
On Wed, Nov 13, 2013 at 8:47 AM, Minkyu Kang proms...@gmail.com wrote:
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde rajeshwar...@samsung.com
wrote:
This patch adds support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added /include/ exynos5420.dtsi
Changes in V5:
- None
Changes in V6:
- None
arch/arm/dts/exynos5.dtsi | 211
++
arch/arm/dts/exynos5250.dtsi | 178
+
arch/arm/dts/exynos5420.dtsi | 74 +++
board/samsung/dts/exynos5420-smdk5420.dts | 172
4 files changed, 458 insertions(+), 177 deletions(-)
create mode 100644 arch/arm/dts/exynos5.dtsi
create mode 100644 arch/arm/dts/exynos5420.dtsi
create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
diff --git a/board/samsung/dts/exynos5420-smdk5420.dts
b/board/samsung/dts/exynos5420-smdk5420.dts
new file mode 100644
index 000..5ef0c92
--- /dev/null
+++ b/board/samsung/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,172 @@
+/*
+ * SAMSUNG SMDK5420 board device tree source
+ *
+ * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can
be
+ * found in the LICENSE file.
is it right?
Iam sorry did not get your question, about what are you pointing to?.
The Copyright and License.
+ */
+
+/dts-v1/;
+/include/ exynos5420.dtsi
+
+/ {
+ model = SAMSUNG SMDK5420 board based on EXYNOS5420;
+ compatible = samsung,smdk5420, samsung,exynos5;
+
+ config {
+ hwid = smdk5420 TEST A-A 9382;
+ };
+
+ aliases {
+ i2c0 = /i2c@12c6;
+ i2c1 = /i2c@12c7;
+ i2c2 = /i2c@12c8;
+ i2c3 = /i2c@12c9;
+ i2c4 = /i2c@12ca;
+ i2c5 = /i2c@12cb;
+ i2c6 = /i2c@12cc;
+ i2c7 = /i2c@12cd;
+ i2c8 = /i2c@12e0;
+ i2c9 = /i2c@12e1;
+ i2c10 = /i2c@12e2;
+ spi0 = /spi@12d2;
+ spi1 = /spi@12d3;
+ spi2 = /spi@12d4;
+ spi3 = /spi@131a;
+ spi4 = /spi@131b;
+ mmc0 = /mmc@1220;
+ mmc1 = /mmc@1221;
+ mmc2 = /mmc@1222;
+ xhci0 = /xhci@1200;
+ xhci1 = /xhci@1240;
+ serial0 = /serial@12C3;
+ console = /serial@12C3;
+ };
+
+ tmu@1006 {
+ samsung,min-temp= 25;
+ samsung,max-temp= 125;
+ samsung,start-warning = 95;
+ samsung,start-tripping = 105;
+ samsung,hw-tripping = 110;
+ samsung,efuse-min-value = 40;
+ samsung,efuse-value = 55;
+ samsung,efuse-max-value = 100;
+ samsung,slope = 274761730;
+ samsung,dc-value= 25;
+ };
+
+ /* s2mps11 is on i2c bus 4 */
+ i2c@12ca {
+ #address-cells = 1;
+ #size-cells = 0;
+ pmic@66 {
+ reg = 0x66;
+ compatible = samsung,s2mps11-pmic;
+ };
+ };
+
+ spi@12d2 { /* spi0 */
+ spi-max-frequency = 5000;
+ firmware_storage_spi: flash@0 {
+ reg = 0;
+ };
+ };
+
+ fimd@1440 {
+ samsung,vl-freq = 60;
+ samsung,vl-col = 2560;
+ samsung,vl-row = 1600;
+ samsung,vl-width = 2560;
+ samsung,vl-height = 1600;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = 4;
+
+ samsung,vl-hspw = 32;
+ samsung,vl-hbpd = 80;
+ samsung,vl-hfpd = 48;
+ samsung,vl-vspw = 6;
+ samsung,vl-vbpd = 37;
+ samsung,vl-vfpd = 3;
+ samsung,vl-cmd-allow-len = 0xf;
+
+ samsung,winid = 3;
+ samsung,interface-mode = 1;
+
Re: [U-Boot] [U-Boot,v5,09/11] S3C24XX: Add NAND Flash driver
On Fri, Sep 21, 2012 at 07:47:46PM +0100, José Miguel Gonçalves wrote: NAND Flash driver with HW ECC for the S3C24XX SoCs. Currently it only supports SLC NAND chips. Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt --- Changes for v2: - Coding style cleanup - Use of clrsetbits_le32() - Use of register bit macros instead of magic numbers Changes for v3: - Removed magic numbers - Removed a macro to declare a void printf() - Replaced one printf() with a puts() Changes for v4: - Coding style cleanup - Use of a struct to store chip private data - Replaced u_long by u32 - Replaced u_char by uint8_t - Added error message in s3c_nand_select_chip() - Optimization of s3c_nand_hwcontrol() Changes for v5: - Dropped const attribute in the private struct - Added const attribute to 'cs' field in the private struct --- drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/s3c24xx_nand.c | 255 +++ 2 files changed, 256 insertions(+) create mode 100644 drivers/mtd/nand/s3c24xx_nand.c Minkyu, what's the status of this patchset? I don't see any comments in patchwork. Is this patch still active and needing my ack? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio
On 13 November 2013 15:04, Rajeshwari Birje rajeshwari.bi...@gmail.comwrote:
Hi Minkyu Kang,
Thank you for comments.
On Wed, Nov 13, 2013 at 8:31 AM, Minkyu Kang proms...@gmail.com wrote:
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde rajeshwar...@samsung.com
wrote:
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added correct calculation of gpio based addresses.
Changes in V5:
- None
Changes in V6:
- None
arch/arm/cpu/armv7/exynos/pinmux.c| 241
+-
arch/arm/include/asm/arch-exynos/gpio.h | 143 --
arch/arm/include/asm/arch-exynos/periph.h | 3 +
3 files changed, 372 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 8002bce..417ecae 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -46,6 +46,41 @@ static void exynos5_uart_config(int peripheral)
}
}
+static void exynos5420_uart_config(int peripheral)
+{
+ struct exynos5420_gpio_part1 *gpio1 =
+ (struct exynos5420_gpio_part1
*)samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank;
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ bank = gpio1-a0;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ bank = gpio1-a0;
+ start = 4;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ bank = gpio1-a1;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ bank = gpio1-a1;
+ start = 4;
+ count = 2;
+ break;
+ }
please add blank line.
will correct this
+ for (i = start; i start + count; i++) {
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
+}
+
static int exynos5_mmc_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
@@ -101,6 +136,70 @@ static int exynos5_mmc_config(int peripheral, int
flags)
return 0;
}
+static int exynos5420_mmc_config(int peripheral, int flags)
+{
+ struct exynos5420_gpio_part3 *gpio3 =
+ (struct exynos5420_gpio_part3
*)samsung_get_base_gpio_part3();
+ struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
+ int i, start = 0, gpio_func = 0;
I think we don' have to set to 0 to start and gpio_func.
Will remove gpio_func, but if I dont set start to 0 I get following error:
pinmux.c: In function ‘exynos_pinmux_config’:
pinmux.c:173:20: warning: ‘start’ may be used uninitialized in this
function [-Wmaybe-uninitialized]
pinmux.c:145:9: note: ‘start’ was declared here
because you missing start = 0 at MMC2.
Actually I like to set values explicitly at every conditions instead of
initial value.
It looks more clearly.
Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net
___
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