Re: [U-Boot] [PATCH v2 1/4] x86: Do CPU identification in the early phase
Hi Simon,
On Tue, Nov 11, 2014 at 2:53 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 9 November 2014 07:18, Bin Meng bmeng...@gmail.com wrote:
The CPU identification happens in x86_cpu_init_f() and corresponding
fields are saved in the global data for later use.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes for v2:
- Update the patch per review comments from Simon Glass
- cpu_vendor_name() and fill_processor_name() are not static now
arch/x86/cpu/cpu.c | 277
+++--
arch/x86/include/asm/cpu.h | 168 +-
arch/x86/include/asm/global_data.h | 5 +
3 files changed, 402 insertions(+), 48 deletions(-)
Applied to u-boot-x86/master, thanks!
Note I had to clean up style problems in these patches. I decided to
do this instead of asking for a respin since I didn't check it for
version 1.
$ patman -nm -c4
Cleaned 4 patches
8 errors, 8 warnings, 2 checks for
0001-x86-Do-CPU-identification-in-the-early-phase.patch:
error: arch/x86/cpu/cpu.c,57: code indent should use tabs where possible
warning: arch/x86/cpu/cpu.c,57: please, no spaces at the start of a line
error: arch/x86/cpu/cpu.c,58: code indent should use tabs where possible
warning: arch/x86/cpu/cpu.c,58: please, no spaces at the start of a line
error: arch/x86/cpu/cpu.c,59: code indent should use tabs where possible
warning: arch/x86/cpu/cpu.c,59: please, no spaces at the start of a line
error: arch/x86/cpu/cpu.c,60: code indent should use tabs where possible
warning: arch/x86/cpu/cpu.c,60: please, no spaces at the start of a line
warning: arch/x86/cpu/cpu.c,84: static const char * array should
probably be static const char * const
error: arch/x86/cpu/cpu.c,213: space prohibited before that close
parenthesis ')'
warning: arch/x86/cpu/cpu.c,245: braces {} are not necessary for any
arm of this statement
warning: arch/x86/cpu/cpu.c,255: braces {} are not necessary for
single statement blocks
error: arch/x86/cpu/cpu.c,269: else should follow close brace '}'
error: arch/x86/cpu/cpu.c,275: space required before the open parenthesis '('
error: arch/x86/cpu/cpu.c,490: that open brace { should be on the previous
line
check: arch/x86/cpu/cpu.c,491: Alignment should match open parenthesis
warning: arch/x86/cpu/cpu.c,527: line over 80 characters
check: arch/x86/cpu/cpu.c,528: Alignment should match open parenthesis
0 errors, 0 warnings, 2 checks for
0002-x86-Do-TSC-MSR-calibration-only-for-known-supported-.patch:
check: arch/x86/lib/tsc_timer.c,62: Alignment should match open parenthesis
check: arch/x86/lib/tsc_timer.c,105: Alignment should match open parenthesis
0 errors, 1 warnings, 0 checks for
0003-x86-Add-quick-TSC-calibration-via-PIT.patch:
warning: arch/x86/lib/tsc_timer.c,162: line over 80 characters
Please can you make sure you submit them with patman so that these
problems are checked?
I am really sorry for not checking the patches before sending them
out. I will do it in the future. Thanks again!
Regards,
Bin
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Re: [U-Boot] [PATCH v2 2/4] x86: Do TSC MSR calibration only for known/supported CPUs
Hi Simon,
On Tue, Nov 11, 2014 at 2:54 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 9 November 2014 07:19, Bin Meng bmeng...@gmail.com wrote:
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
processors which do not have this MSR. Instead only doing the MSR
calibration for known/supported CPUs.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
arch/x86/lib/tsc_timer.c | 116
---
1 file changed, 109 insertions(+), 7 deletions(-)
Applied to u-boot-x86/master, thanks!
(Please see note below)
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index 8b38702..fafbbfc 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -1,6 +1,9 @@
/*
* Copyright (c) 2012 The Chromium OS Authors.
*
+ * TSC calibration codes are adapted from Linux kernel
+ * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
+ *
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -12,8 +15,108 @@
#include asm/msr.h
#include asm/u-boot-x86.h
+/* CPU reference clock frequency: in KHz */
+#define FREQ_8383200
+#define FREQ_100 99840
+#define FREQ_133 133200
+#define FREQ_166 166400
+
+#define MAX_NUM_FREQS 8
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * According to Intel 64 and IA-32 System Programming Guide,
+ * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
+ * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
+ * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
+ * so we need manually differentiate SoC families. This is what the
+ * field msr_plat does.
+ */
+struct freq_desc {
+ u8 x86_family; /* CPU family */
+ u8 x86_model; /* model */
+ u8 msr_plat;/* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS
*/
+ u32 freqs[MAX_NUM_FREQS];
+};
+
+static struct freq_desc freq_desc_tables[] = {
+ /* PNW */
+ { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* CLV+ */
+ { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* TNG */
+ { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
+ /* VLV2 */
+ { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 }
},
+ /* ANN */
+ { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 }
},
+};
+
+static int match_cpu(u8 family, u8 model)
+{
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(freq_desc_tables); i++) {
+ if ((family == freq_desc_tables[i].x86_family)
+ (model == freq_desc_tables[i].x86_model))
+ return i;
+ }
+
+ return -1;
+}
+
+/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
+#define id_to_freq(cpu_index, freq_id) \
+ (freq_desc_tables[cpu_index].freqs[freq_id])
+
+/*
+ * Do MSR calibration only for known/supported CPUs.
+ *
+ * Returns the calibration value or 0 if MSR calibration failed.
+ */
+static unsigned long try_msr_calibrate_tsc(void)
+{
+ u32 lo, hi, ratio, freq_id, freq;
+ unsigned long res;
+ int cpu_index;
+
+ cpu_index = match_cpu(gd-arch.x86, gd-arch.x86_model);
+ if (cpu_index 0)
+ return 0;
+
+ if (freq_desc_tables[cpu_index].msr_plat) {
+ rdmsr(MSR_PLATFORM_INFO, lo, hi);
+ ratio = (lo 8) 0x1f;
+ } else {
+ rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ ratio = (hi 8) 0x1f;
+ }
+ debug(Maximum core-clock to bus-clock ratio: 0x%x\n, ratio);
+
+ if (!ratio)
+ goto fail;
+
+ /* Get FSB FREQ ID */
+ rdmsr(MSR_FSB_FREQ, lo, hi);
+ freq_id = lo 0x7;
+ freq = id_to_freq(cpu_index, freq_id);
+ debug(Resolved frequency ID: %u, frequency: %u KHz\n,
+ freq_id, freq);
+ if (!freq)
+ goto fail;
+
+ /* TSC frequency = maximum resolved freq * maximum resolved bus
ratio */
+ res = freq * ratio / 1000;
+ debug(TSC runs at %lu MHz\n, res);
+
+ return res;
+
+fail:
+ debug(Fast TSC calibration using MSR failed\n);
+ return 0;
+}
+
void timer_set_base(u64 base)
{
gd-arch.tsc_base = base;
@@ -34,17 +137,16 @@ u64 __attribute__((no_instrument_function))
get_ticks(void)
return now_tick - gd-arch.tsc_base;
}
-#define PLATFORM_INFO_MSR 0xce
-
/* Get the speed of the TSC timer in MHz */
unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
+ unsigned long fast_calibrate;
+
+ fast_calibrate = try_msr_calibrate_tsc();
+ if (!fast_calibrate)
+
Re: [U-Boot] [PATCH v3 4/8] imx6: add some flexibility for defining macros
Hi John, On 10/11/2014 00:53, John Tobias wrote: @@ -29,7 +29,9 @@ #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE 0x1 #define CONFIG_SPL_START_S_PATH arch/arm/cpu/armv7 +#ifndef CONFIG_SPL_STACK #define CONFIG_SPL_STACK 0x0091FFB8 +#endif Why is this required ? Other iMX6 chip has different STACK address and the current defined address does not compatibile for the iMX6 SabreSD. This is exactly what I have not understood. Why is this board so special to require a different value ? SPL will run into the IRAM, whose size and layout is the same for i.MX6Q. Is there a reserved area in the IRAM only for sabreSD and if yes, for which reason ? Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 19/39] x86: Build a .rom file which can be flashed to an x86 machine
Hi Simon, On Tue, Nov 11, 2014 at 8:28 AM, Simon Glass s...@chromium.org wrote: Hi Bin, [snip] + $(srctree)/board/$(BOARDDIR)/descriptor.bin I don't see where the descriptor.bin is created? This needs to be downloaded and provided, as with mrc.bin, etc. I thought the descriptor.bin is used to describe the u-boot.rom layout, but seems you are saying it is coming from Intel(?). Is the format defined by Intel so that all the BIOS for that platform (u-boot.rom in our case) has to obey? I think I will adjust it (later) so that it builds an empty u-boot.rom and prints a warning on stdout if the binaries are not available. That way the buildman build will still succeed, but the user will see the problem. It might also be useful to have U-Boot report missing binaries when it starts up. Sounds good. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init
Hi Simon, On Tue, Nov 11, 2014 at 8:29 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 9 November 2014 23:49, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. [snip] diff --git a/Makefile b/Makefile index 86d0510..4f0260f 100644 --- a/Makefile +++ b/Makefile @@ -956,9 +956,14 @@ u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ $(srctree)/board/$(BOARDDIR)/descriptor.bin $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp Can we make the ME injection depend on something like CONFIG_X86_HAVE_ME? Sure - do you have a case that doesn't use ME? The platform (Atom E6xx and EG20T) I am working on does not have the ME. Note it also does not have the descriptor.bin. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull req on u-boot-sunxi/sunxi-wip
Hi, On 11/11/2014 12:28 AM, Zoltan HERPAI wrote: Hi Hans, Sorry for the noise, I screwed up the pull request. All it was meant to be is to fix up the bananapi gmac magic bit toucher - please ignore/drop, I'll redo it. Thanks for catching this, note we don't do pull-reqs for u-boot, other the from sub-maintainers - maintainers. Please do a git-send-email with the patch to the u-boot list U-Boot u-boot@lists.denx.de, and I'll pick it up from there. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 7/8] imx6: SPL support for iMX6 SabreSD
Hi John,
On 10/11/2014 01:23, John Tobias wrote:
Hi Stefano,
On Sun, Nov 9, 2014 at 1:16 PM, Stefano Babic sba...@denx.de wrote:
Hi John,
On 08/11/2014 22:27, John Tobias wrote:
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
---
board/freescale/mx6sabresd/mx6sabresd.c | 211
+++-
1 file changed, 209 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 3d81fff..f443337 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -55,8 +55,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
+ gd-ram_size = imx_ddr_size();
return 0;
}
@@ -607,3 +606,211 @@ int checkboard(void)
puts(Board: MX6-SabreSD\n);
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include spl.h
+#include libfdt.h
+
+#define BOOT_CFG 0x20D8004
+#define __REG(x)(*((volatile u32 *)(x)))
+
+struct fsl_esdhc_cfg spl_usdhc_cfg;
+/*
+ * Got it from mx6q_4x_mt41j128.cfg file
+ */
+void set_mt41j128_ddr(void)
+{
+ __REG(0x020e05a8) = 0x0028;
+ __REG(0x020e05b0) = 0x0028;
+ __REG(0x020e0524) = 0x0028;
+ __REG(0x020e051c) = 0x0028;
+
+ __REG(0x020e0518) = 0x0028;
+ __REG(0x020e050c) = 0x0028;
+ __REG(0x020e05b8) = 0x0028;
+ __REG(0x020e05c0) = 0x0028;
+
+ __REG(0x020e05ac) = 0x0028;
+ __REG(0x020e05b4) = 0x0028;
+ __REG(0x020e0528) = 0x0028;
+ __REG(0x020e0520) = 0x0028;
+
+ __REG(0x020e0514) = 0x0028;
+ __REG(0x020e0510) = 0x0028;
+ __REG(0x020e05bc) = 0x0028;
+ __REG(0x020e05c4) = 0x0028;
+
+ __REG(0x020e056c) = 0x0030;
+ __REG(0x020e0578) = 0x0030;
+ __REG(0x020e0588) = 0x0030;
+ __REG(0x020e0594) = 0x0030;
+
+ __REG(0x020e057c) = 0x0030;
+ __REG(0x020e0590) = 0x0030;
+ __REG(0x020e0598) = 0x0030;
+ __REG(0x020e058c) = 0x;
+
+ __REG(0x020e059c) = 0x3030;
+ __REG(0x020e05a0) = 0x3030;
+ __REG(0x020e0784) = 0x0028;
+ __REG(0x020e0788) = 0x0028;
+
+ __REG(0x020e0794) = 0x0028;
+ __REG(0x020e079c) = 0x0028;
+ __REG(0x020e07a0) = 0x0028;
+ __REG(0x020e07a4) = 0x0028;
+
+ __REG(0x020e07a8) = 0x0028;
+ __REG(0x020e0748) = 0x0028;
+ __REG(0x020e074c) = 0x0030;
+ __REG(0x020e0750) = 0x0002;
+
+ __REG(0x020e0758) = 0x;
+ __REG(0x020e0774) = 0x0002;
+ __REG(0x020e078c) = 0x0030;
+ __REG(0x020e0798) = 0x000C;
+
+ __REG(0x021b081c) = 0x;
+ __REG(0x021b0820) = 0x;
+ __REG(0x021b0824) = 0x;
+ __REG(0x021b0828) = 0x;
+
+ __REG(0x021b481c) = 0x;
+ __REG(0x021b4820) = 0x;
+ __REG(0x021b4824) = 0x;
+ __REG(0x021b4828) = 0x;
+
+ __REG(0x021b0018) = 0x1740;
+
+ __REG(0x021b001c) = 0x8000;
+ __REG(0x021b000c) = 0x8A8F7975;
+ __REG(0x021b0010) = 0xFF538E64;
+ __REG(0x021b0014) = 0x01FF00DB;
+ __REG(0x021b002c) = 0x26D2;
+
+ __REG(0x021b0030) = 0x008F0E21;
+ __REG(0x021b0008) = 0x09444040;
+ __REG(0x021b0004) = 0x00020036;
+ __REG(0x021b0040) = 0x0047;
+ __REG(0x021b) = 0x841A;
+
+ __REG(0x021b001c) = 0x04088032;
+ __REG(0x021b001c) = 0x8033;
+ __REG(0x021b001c) = 0x00428031;
+ __REG(0x021b001c) = 0x09408030;
+
+ __REG(0x021b001c) = 0x04008040;
+ __REG(0x021b0800) = 0xA1380003;
+ __REG(0x021b0020) = 0x5800;
+ __REG(0x021b0818) = 0x0007;
+ __REG(0x021b4818) = 0x0007;
+
+ /* Calibration values based on ARD and 528MHz */
+ __REG(0x021b083c) = 0x434B0358;
+ __REG(0x021b0840) = 0x033D033C;
+ __REG(0x021b483c) = 0x03520362;
+ __REG(0x021b4840) = 0x03480318;
+ __REG(0x021b0848) = 0x41383A3C;
+ __REG(0x021b4848) = 0x3F3C374A;
+ __REG(0x021b0850) = 0x4243;
+ __REG(0x021b4850) = 0x4932473A;
+
+ __REG(0x021b080c) = 0x001F001F;
+ __REG(0x021b0810) = 0x001F001F;
+
+ __REG(0x021b480c) = 0x001F001F;
+ __REG(0x021b4810) = 0x001F001F;
+
+ __REG(0x021b08b8) = 0x0800;
+ __REG(0x021b48b8) = 0x0800;
+
+ __REG(0x021b0404) = 0x00011006;
+ __REG(0x021b0004) = 0x00025576;
+
+ __REG(0x021b001c) = 0x;
+
+ __REG(0x020c4068) = 0x00C03F3F;
+ __REG(0x020c406c) = 0x0030FC00;
+ __REG(0x020c4070) = 0x0FFFC000;
+ __REG(0x020c4074) = 0x3FF0;
+ __REG(0x020c4078) = 0x00FFF300;
+ __REG(0x020c407c) = 0x0FC3;
+ __REG(0x020c4080) = 0x03FF;
+}
+
This cannot be accepted. Firstly, you
Re: [U-Boot] [PATCH v2 06/33] x86: config: Move common x86 configs to a common file
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
Many of the x86 CONFIG options will be common across different boards. Move
them to a common file.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Move some features out of the common file
include/configs/coreboot.h | 265
++-
include/configs/x86-common.h | 251
2 files changed, 260 insertions(+), 256 deletions(-)
create mode 100644 include/configs/x86-common.h
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index fef267f..2581380 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -6,7 +6,6 @@
* SPDX-License-Identifier:GPL-2.0+
*/
-#include asm/ibmpc.h
/*
* board/config.h - configuration options, board specific
*/
@@ -14,27 +13,23 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include configs/x86-common.h
+
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_SYS_COREBOOT
-#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_SYS_VSNPRINTF
-#define CONFIG_ZBOOT_32
-#define CONFIG_PHYSMEM
#define CONFIG_SYS_EARLY_PCI_INIT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
+#define CONFIG_SYS_CAR_ADDR0x1920
+#define CONFIG_SYS_CAR_SIZE(16 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_LMB
-#define CONFIG_OF_LIBFDT
+#define CONFIG_TRACE_EARLY_SIZE(8 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR0x0140
#define CONFIG_BOOTSTAGE
#define CONFIG_BOOTSTAGE_REPORT
@@ -45,26 +40,6 @@
#define CONFIG_BOOTSTAGE_STASH_SIZE0x7fc
#define CONFIG_BOOTSTAGE_USER_COUNT60
-#define CONFIG_LZO
-#define CONFIG_FIT
-#undef CONFIG_ZLIB
-#undef CONFIG_GZIP
-#define CONFIG_SYS_BOOTM_LEN (16 20)
-
-/*---
- * Watchdog Configuration
- */
-#undef CONFIG_WATCHDOG
-#undef CONFIG_HW_WATCHDOG
-
-/* SATA AHCI storage */
-
-#define CONFIG_SCSI_AHCI
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
-#define CONFIG_SYS_64BIT_LBA
-#define CONFIG_SATA_INTEL 1
#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
{PCI_VENDOR_ID_INTEL, \
@@ -74,249 +49,27 @@
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID2
-#define CONFIG_SYS_SCSI_MAX_LUN1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-/* Generic TPM interfaced through LPC bus */
-#define CONFIG_TPM
-#define CONFIG_TPM_TIS_LPC
-#define CONFIG_TPM_TIS_BASE_ADDRESS0xfed4
-
-/*---
- * Real Time Clock Configuration
- */
-#define CONFIG_RTC_MC146818
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
-
-/*---
- * Serial Configuration
- */
#define CONFIG_COREBOOT_SERIAL
-#define CONFIG_SYS_NS16550
-#define CONFIG_BAUDRATE115200
-#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
-9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_PORT_MAPPED
#define CONFIG_STD_DEVICES_SETTINGS stdin=usbkbd,vga,serial\0 \
stdout=vga,serial,cbmem\0 \
stderr=vga,serial,cbmem\0
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_CBMEM_CONSOLE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SUPPORT_VFAT
-/
- * ATAPI support (experimental)
- /
-#define CONFIG_ATAPI
-
-/
- * DISK Partition support
- /
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
-
-#define CONFIG_CMD_PART
-#define CONFIG_CMD_CBFS
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define
[U-Boot] AM335x Boot Device 6 (NAND?)
Hi Tom, we have equipped some of our am335x boards (draco from mainline U-Boot) with NAND devices from Hynix. And as it seems, the BootROM passes now a different bootdevice number to SPL. Its not 5 as it used to be for NAND but 6 instead. So SPL hangs of course as this boot-device is not supported. Could you please let me know what this boot-device == 6 means / represents? Should it be handled identical as the normal NAND boot-device (5)? Just to make this clear. This is the code that I'm referring to: arch/arm/cpu/armv7/omap-common/boot-common.c: /* * rom_params can be type casted to omap_boot_parameters and * used. But it not correct to assume that romcode structure * encoding would be same as u-boot. So use the defined offsets. */ gd-arch.omap_boot_params.omap_bootdevice = boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); BTW: U-Boot can handle this Hynix NAND (same layout as the other NAND chips we use) without any problems. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 07/33] x86: Add processor functions to halt and get stack pointer
Reviewed-by: Bin Meng bmeng...@gmail.com
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
Add a function to get the stack pointer and another to halt the CPU.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Remove the cpuid functions since they were already added in another patch
arch/x86/include/asm/processor.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/x86/include/asm/processor.h
b/arch/x86/include/asm/processor.h
index bb3172f..b2854a9 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -30,4 +30,23 @@ enum {
#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
+#ifndef __ASSEMBLY__
+
+static inline __attribute__((always_inline)) void cpu_hlt(void)
+{
+ asm(hlt);
+}
+
+static inline ulong cpu_get_sp(void)
+{
+ ulong result;
+
+ asm volatile(
+ mov %%esp, %%eax
+ : =a (result));
+ return result;
+}
+
+#endif /* __ASSEMBLY__ */
+
#endif
--
2.1.0.rc2.206.gedb03e5
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Re: [U-Boot] [PATCH v2 08/33] x86: Remove unnecessary find_fdt(), prepare_fdt() functions
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
These are no-longer needed so drop them.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Remove definition of find_fdt() also
- Remove prepare_fdt() also
arch/x86/include/asm/init_helpers.h | 2 --
arch/x86/lib/init_helpers.c | 27 ---
common/board_f.c| 5 -
3 files changed, 34 deletions(-)
diff --git a/arch/x86/include/asm/init_helpers.h
b/arch/x86/include/asm/init_helpers.h
index b07887e..8cbe08e 100644
--- a/arch/x86/include/asm/init_helpers.h
+++ b/arch/x86/include/asm/init_helpers.h
@@ -13,7 +13,5 @@ int calculate_relocation_address(void);
int init_cache_f_r(void);
int init_bd_struct_r(void);
int init_func_spi(void);
-int find_fdt(void);
-int prepare_fdt(void);
#endif /* !_INIT_HELPERS_H_ */
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index b5d937f..be4eb12 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -87,30 +87,3 @@ int init_func_spi(void)
puts(ready\n);
return 0;
}
-
-int find_fdt(void)
-{
-#ifdef CONFIG_OF_EMBED
- /* Get a pointer to the FDT */
- gd-fdt_blob = __dtb_dt_begin;
-#elif defined CONFIG_OF_SEPARATE
- /* FDT is at end of image */
- gd-fdt_blob = (ulong *)_end;
-#endif
- /* Allow the early environment to override the fdt address */
- gd-fdt_blob = (void *)getenv_ulong(fdtcontroladdr, 16,
- (uintptr_t)gd-fdt_blob);
-
- return 0;
-}
-
-int prepare_fdt(void)
-{
- /* For now, put this check after the console is ready */
- if (fdtdec_prepare_fdt()) {
- panic(** CONFIG_OF_CONTROL defined but no FDT - please see
- doc/README.fdt-control);
- }
-
- return 0;
-}
diff --git a/common/board_f.c b/common/board_f.c
index f81f70d..6e6a1a2 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -818,11 +818,6 @@ static init_fnc_t init_sequence_f[] = {
probecpu,
#endif
arch_cpu_init, /* basic arch cpu dependent setup */
-#ifdef CONFIG_X86
-# ifdef CONFIG_OF_CONTROL
- find_fdt, /* TODO(s...@chromium.org): remove */
-# endif
-#endif
mark_bootstage,
#ifdef CONFIG_OF_CONTROL
fdtdec_check_fdt,
--
Reviewed-by: Bin Meng bmeng...@gmail.com
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Re: [U-Boot] [PATCH v2 09/33] x86: Replace fill_processor_name() with cpu_get_name()
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to replace fill_processor_name() with cpu_get_name()
arch/x86/cpu/cpu.c | 22 ++
arch/x86/include/asm/cpu.h | 11 ---
2 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index a4e639d..0d75941 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -491,14 +491,14 @@ const char *cpu_vendor_name(int vendor)
return name;
}
-void fill_processor_name(char *processor_name)
+char *cpu_get_name(char *name)
{
+ unsigned int *name_as_ints = (unsigned int *)name;
struct cpuid_result regs;
- char temp_processor_name[49];
- char *processor_name_start;
- unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
+ char *ptr;
int i;
+ /* This bit adds up to 48 bytes */
for (i = 0; i 3; i++) {
regs = cpuid(0x8002 + i);
name_as_ints[i * 4 + 0] = regs.eax;
@@ -506,19 +506,17 @@ void fill_processor_name(char *processor_name)
name_as_ints[i * 4 + 2] = regs.ecx;
name_as_ints[i * 4 + 3] = regs.edx;
}
-
- temp_processor_name[48] = 0;
+ name[CPU_MAX_NAME_LEN - 1] = '\0';
/* Skip leading spaces. */
- processor_name_start = temp_processor_name;
- while (*processor_name_start == ' ')
- processor_name_start++;
+ ptr = name;
+ while (*ptr == ' ')
+ ptr++;
- memset(processor_name, 0, 49);
- strcpy(processor_name, processor_name_start);
+ return ptr;
}
-int print_cpuinfo(void)
+int default_print_cpuinfo(void)
{
printf(CPU: %s, vendor %s, device %xh\n,
cpu_has_64bit() ? x86_64 : x86,
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 89b748b..c839291 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -179,12 +179,17 @@ int cpu_has_64bit(void);
*/
const char *cpu_vendor_name(int vendor);
+#define CPU_MAX_NAME_LEN 49
+
/**
- * fill_processor_name() - Get processor name
+ * cpu_get_name() - Get the name of the current cpu
*
- * @processor_name:Address to hold the processor name string
+ * @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including
+ * @return pointer to name, which will likely be a few bytes after the start
+ * of @name
+ * \0 terminator
*/
-void fill_processor_name(char *processor_name);
+char *cpu_get_name(char *name);
/**
* cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
--
Reviewed-by: Bin Meng bmeng...@gmail.com
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Re: [U-Boot] [PATCH v2 10/33] x86: Tidy up timer code for Intel core architecture
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
We can use an MSR to obtain the time base. Add this back in and consolidate
the code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to tidy up timer code for Intel core architecture
arch/x86/cpu/interrupts.c | 28
arch/x86/lib/tsc_timer.c | 16 +++-
2 files changed, 15 insertions(+), 29 deletions(-)
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 51e2c59..4822c11 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -603,31 +603,3 @@ asm(.globl irq_common_entry\n \
DECLARE_INTERRUPT(253) \
DECLARE_INTERRUPT(254) \
DECLARE_INTERRUPT(255));
-
-#if defined(CONFIG_INTEL_CORE_ARCH)
-/*
- * Get the number of CPU time counter ticks since it was read first time
after
- * restart. This yields a free running counter guaranteed to take almost 6
- * years to wrap around even at 100GHz clock rate.
- */
-u64 get_ticks(void)
-{
- u64 now_tick = rdtsc();
-
- if (!gd-arch.tsc_base)
- gd-arch.tsc_base = now_tick;
-
- return now_tick - gd-arch.tsc_base;
-}
-
-#define PLATFORM_INFO_MSR 0xce
-
-unsigned long get_tbclk(void)
-{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
-
- ratio = (platform_info 8) 0xff;
- return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio
*/
-}
-#endif
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index f091c91..3936b36 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -180,6 +180,20 @@ static inline int pit_expect_msb(unsigned char val, u64
*tscp,
return count 5;
}
+#define PLATFORM_INFO_MSR 0xce
+
+/* Get the speed of the TSC timer in MHz */
+unsigned __attribute__((no_instrument_function))
+ long get_tbclk_mhz_from_msr(void)
+{
+ u32 ratio;
+ u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
+
+ /* 100MHz times Max Non Turbo ratio */
+ ratio = (platform_info 8) 0xff;
+ return 100 * ratio;
+}
+
/*
* How many MSB values do we want to see? We aim for
* a maximum error rate of 500ppm (in practice the
@@ -302,7 +316,7 @@ unsigned __attribute__((no_instrument_function)) long
get_tbclk_mhz(void)
fast_calibrate = quick_pit_calibrate();
if (!fast_calibrate)
- panic(TSC frequency is ZERO);
+ fast_calibrate = get_tbclk_mhz_from_msr();
gd-arch.tsc_mhz = fast_calibrate;
return fast_calibrate;
--
Adding MSR calibration back for Intel CORE this way is inconsistent
with the code logic. Can you please try adding the family number and
model number in the freq_desc_tables[]?
Regards,
Bin
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Re: [U-Boot] [PATCH v2 13/33] x86: Emit post codes in startup code for Chromebooks
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.
On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Move early init code into early_board_init
arch/x86/cpu/coreboot/coreboot.c | 3 ++-
arch/x86/cpu/start.S | 4
arch/x86/include/asm/post.h | 32
board/google/chromebook_link/Kconfig | 4
board/google/common/early_init.S | 21 -
5 files changed, 62 insertions(+), 2 deletions(-)
create mode 100644 arch/x86/include/asm/post.h
diff --git a/arch/x86/cpu/coreboot/coreboot.c
b/arch/x86/cpu/coreboot/coreboot.c
index 874b59d..d9662d9 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -15,6 +15,7 @@
#include asm/cache.h
#include asm/cpu.h
#include asm/io.h
+#include asm/post.h
#include asm/arch-coreboot/tables.h
#include asm/arch-coreboot/sysinfo.h
#include asm/arch/timestamp.h
@@ -70,7 +71,7 @@ void show_boot_progress(int val)
gd-arch.tsc_prev = now;
}
#endif
- outb(val, 0x80);
+ outb(val, POST_PORT);
}
int last_stage_init(void)
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index b18f320..1b738f9 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -13,6 +13,7 @@
#include config.h
#include version.h
#include asm/global_data.h
+#include asm/post.h
#include asm/processor.h
#include asm/processor-flags.h
#include generated/generic-asm-offsets.h
@@ -67,6 +68,7 @@ _start:
jmp early_board_init
.globl early_board_init_ret
early_board_init_ret:
+ post_code(POST_START)
/* Initialise Cache-As-RAM */
jmp car_init
@@ -96,6 +98,7 @@ car_init_ret:
/* Align global data to 16-byte boundary */
andl$0xfff0, %esp
+ post_code(POST_START_STACK)
/* Zero the global data since it won't happen later */
xorl%eax, %eax
@@ -131,6 +134,7 @@ car_init_ret:
callsetup_gdt
/* Set parameter to board_init_f() to boot flags */
+ post_code(POST_START_DONE)
xorl%eax, %eax
/* Enter, U-boot! */
diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
new file mode 100644
index 000..3371185
--- /dev/null
+++ b/arch/x86/include/asm/post.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _post_h
+#define _post_h
+
+/* port to use for post codes */
+#define POST_PORT 0x80
+
+/* post codes which represent various stages of init */
+#define POST_START 0x1e
+#define POST_CAR_START 0x1f
+
+#define POST_START_STACK 0x29
+#define POST_START_DONE0x2a
+
+/* Output a post code using al - value must be 0 to 0xff */
+#ifdef __ASSEMBLY__
+#define post_code(value) \
+ movb$value, %al; \
+ outb%al, $POST_PORT
+#else
+static inline void post_code(int code)
+{
+ outb(code, POST_PORT);
+}
+#endif
+
+#endif
diff --git a/board/google/chromebook_link/Kconfig
b/board/google/chromebook_link/Kconfig
index 975d557..9c715ba 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -12,4 +12,8 @@ config SYS_SOC
config SYS_CONFIG_NAME
default chromebook_link
+config EARLY_POST_CROS_EC
+ bool Enable early post to Chrome OS EC
+ default y
+
endif
diff --git a/board/google/common/early_init.S
b/board/google/common/early_init.S
index cf70ae4..15f2ff2 100644
--- a/board/google/common/early_init.S
+++ b/board/google/common/early_init.S
@@ -6,5 +6,24 @@
.globl early_board_init
early_board_init:
- /* No 32-bit board specific initialisation */
+ /* Enable post codes to EC */
+#ifdef CONFIG_EARLY_POST_CROS_EC
+ mov$0x1b, %ecx
+ rdmsr
+ and$0x100, %eax
+ test %eax, %eax
+ je 2f
1f, maybe nitpicking.
+ mov$0x8000f8f0, %eax
+ mov$0xcf8, %dx
+ out%eax, (%dx)
+ mov$0xfed1c001, %eax
+ mov$0xcfc, %dx
+ out%eax, (%dx)
+ mov$0xfed1f410, %esp
+ mov(%esp), %eax
+ and$0xfffb, %eax
+ mov%eax, (%esp)
+2:
1:
[U-Boot] [GIT PULL] Zynq patches
Hi Tom, [cc: Albert] please pull these 4 patches to your tree. It adds support for Zybo board and add support for new ps7_init_gpl file. Thanks, Michal The following changes since commit 11ada9225a16ed2d8ddbf0715a2416245a777cbc: Merge branch 'rmobile' of git://www.denx.de/git/u-boot-sh (2014-11-05 13:11:18 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git zynq for you to fetch changes up to 61eb3cf2d5ef174b5a3008df6f7530b21f393261: kconfig: zynq: Add ZYBO board (2014-11-11 11:02:52 +0100) Peter Crosthwaite (2): arm: dts: zynq: Add digilent ZYBO board dts kconfig: zynq: Add ZYBO board Soren Brinkmann (1): zynq: Use GPLed files for SPL Tinghui Wang (1): configs: zynq: Add config support for ZYBO arch/arm/cpu/armv7/zynq/Kconfig | 4 arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-zybo.dts | 23 +++ board/xilinx/zynq/.gitignore| 1 + board/xilinx/zynq/Makefile | 6 -- board/xilinx/zynq/legacy.c | 2 ++ board/xilinx/zynq/xil_io.h | 2 +- configs/zynq_zybo_defconfig | 4 include/configs/zynq_zybo.h | 31 +++ 9 files changed, 71 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/zynq-zybo.dts create mode 100644 board/xilinx/zynq/legacy.c create mode 100644 configs/zynq_zybo_defconfig create mode 100644 include/configs/zynq_zybo.h -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mmc: Cosmetic fix for nicer, aligned device list printout
If print_mmc_devices() was called with a '\n' separator (as done
for example by the mmc list command), it offset the 2-nd and
all subsequent lines by one space. Fixing this.
Signed-off-by: Lubomir Popov l-po...@ti.com
---
drivers/mmc/mmc.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 44a4feb..e0ea833 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1401,8 +1401,11 @@ void print_mmc_devices(char separator)
printf(%s: %d, m-cfg-name, m-block_dev.dev);
- if (entry-next != mmc_devices)
- printf(%c , separator);
+ if (entry-next != mmc_devices) {
+ printf(%c, separator);
+ if (separator != '\n')
+ puts ( );
+ }
}
printf(\n);
--
1.7.9.5
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Re: [U-Boot] [PATCH v4] zynq: Use GPLed files for SPL
On 10/30/2014 06:52 PM, Soren Brinkmann wrote: The latest Xilinx tools generate ps7_init files that are explicitly available under GPL. Change the makefile to allow drop in of those files for building the SPL. Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com Acked-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Reviewed-and-tested-by: Masahiro Yamada yamad...@jp.panasonic.com Applied. Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2015.01-rc1 released
On Mon, 10 Nov 2014 16:29:38 -0500 Tom Rini tr...@ti.com wrote: Hey all, I've pushed v2015.01-rc1 out to the repository and tarballs should exist soon. Half a day has passed since Tom's I've pushed v2015.rc-rc1 mail, but I still don't see it. I have been often wondering why we can see the release much lator of Tom's announce mail. When I push my u-boot-uniphier repo, I can see the update on the public repo. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ot1200: fix card detect for usdhc4
Today I got the final board and found out that a different
connector is used as the one on my development board. The
new connector has swaped pins for cd and wp.
This change is tested on a production ready baord.
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
board/bachmann/ot1200/ot1200.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 2ed8cf7..007c1ef 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -159,8 +159,8 @@ int board_mmc_getcd(struct mmc *mmc)
gpio_direction_input(IMX_GPIO_NR(4, 5));
ret = gpio_get_value(IMX_GPIO_NR(4, 5));
} else {
- gpio_direction_input(IMX_GPIO_NR(1, 4));
- ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
+ gpio_direction_input(IMX_GPIO_NR(1, 5));
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
}
return ret;
--
1.9.3
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Re: [U-Boot] [PATCH v4 3/3] omap_hsmmc: Board-specific TWL4030 MMC power initializations
Le lundi 10 novembre 2014 à 13:46 -0500, Tom Rini a écrit :
On Sat, Nov 08, 2014 at 10:29:24PM +0100, Paul Kocialkowski wrote:
Le samedi 08 novembre 2014 à 20:55 +0100, Paul Kocialkowski a écrit :
Boards using the TWL4030 regulator may not all use the LDOs the same way
(e.g. MMC2 power can be controlled by another LDO than VMMC2).
This delegates TWL4030 MMC power initializations to board-specific
functions,
that may still call twl4030_power_mmc_init for the default behavior.
Signed-off-by: Paul Kocialkowski cont...@paulk.fr
---
board/comelit/dig297/dig297.c | 5 +
board/compulab/cm_t35/cm_t35.c | 7 +++
board/corscience/tricorder/tricorder.c | 7 +++
board/isee/igep00x0/igep00x0.c | 7 +++
board/logicpd/omap3som/omap3logic.c| 7 +++
board/logicpd/zoom1/zoom1.c| 5 +
board/matrix_vision/mvblx/mvblx.c | 6 ++
board/nokia/rx51/rx51.c| 6 ++
board/overo/overo.c| 7 +++
board/pandora/pandora.c| 5 +
board/technexion/tao3530/tao3530.c | 7 +++
board/ti/beagle/beagle.c | 7 +++
board/ti/evm/evm.c | 7 +++
board/ti/sdp3430/sdp.c | 5 +
board/timll/devkit8000/devkit8000.c| 7 +++
drivers/mmc/omap_hsmmc.c | 7 +--
16 files changed, 96 insertions(+), 6 deletions(-)
diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c
index 2b826df..9d4c41b 100644
--- a/board/comelit/dig297/dig297.c
+++ b/board/comelit/dig297/dig297.c
@@ -133,6 +133,11 @@ int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
I just figured, in the context of the SPL, board_mmc_init will be called
from omap3/board.c instead of the board file, so perhaps it would be
worth adding, in board_mmc_power_init: #ifdef CONFIG_SPL_BUILD and then
checking spl_boot_device to only enable the relevant LDO.
If we get to this point we can do the same thing we do for
board_mmc_init which is have one in say
arch/arm/cpu/armv7/omap-common/boot-common.c that checks
spl_boot_device()
That wouldn't work for my use case, on the Optimus Black, where
regulators are used in a non-standard way. The whole point of this to me
is to not have platform-common code to handle MMC regulators, because
the way those are wired to MMC devices is not the same for each
platform, but is instead board-specific.
Is there any objection to making a v5 that takes the SPL context in
account on each of those boards?
Thanks
--
Paul Kocialkowski, Replicant developer
Replicant is a fully free Android distribution
Website: http://www.replicant.us/
Blog: http://blog.replicant.us/
Wiki/tracker/forums: http://redmine.replicant.us/
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Re: [U-Boot] AM335x Boot Device 6 (NAND?)
On Tue, Nov 11, 2014 at 10:10:41AM +0100, Stefan Roese wrote: Hi Tom, we have equipped some of our am335x boards (draco from mainline U-Boot) with NAND devices from Hynix. And as it seems, the BootROM passes now a different bootdevice number to SPL. Its not 5 as it used to be for NAND but 6 instead. So SPL hangs of course as this boot-device is not supported. Could you please let me know what this boot-device == 6 means / represents? Should it be handled identical as the normal NAND boot-device (5)? Well, my guess is that you've wired it up, or at least selected SYSBOOT pins saying that this is a NAND+I2C device where the geometry is stored on an i2c eeprom (see 26.1.7.4 of the TRM). Is this really what you wanted is my first question. :) -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fs: make it possible to read the filesystem UUID
Hi
2014-11-03 22:00 GMT+01:00 Stephen Warren swar...@wwwdotorg.org:
On 10/31/2014 09:08 AM, Christian Gmeiner wrote:
Some filesystems have a UUID stored in its superblock. To
allow using root=UUID=... for the kernel command line we
need a way to read-out the filesystem UUID.
Hit any key to stop autoboot: 0
= fsuuid
fsuuid - Look up a filesystem UUID
Usage:
fsuuid interface dev:part
- print filesystem UUID
fsuuid interface dev:part varname
- set environment variable to filesystem UUID
= fsuuid mmc 0:1
d9f9fc05-45ae-4a36-a616-fccce0e4f887
= fsuuid mmc 0:2
eb3db83c-7b28-499f-95ce-9e0bb21cda81
= fsuuid mmc 0:1 uuid1
= fsuuid mmc 0:2 uuid2
= printenv uuid1
uuid1=d9f9fc05-45ae-4a36-a616-fccce0e4f887
= printenv uuid2
uuid2=eb3db83c-7b28-499f-95ce-9e0bb21cda81
=
Acked-by: Stephen Warren swar...@nvidia.com
It'd be nice if you could implement fat_uuid() too, and plumb that in. That
could be a separate commit though I suppose.
IIRC, the kernel accepts the format -MM where is the 32-bit
FAT disk ID (I don't recall the exact correct term) in 0-filled hex and MM
is the partition number in 0-filled decimal.
Lets see if I can find the motivation to look into fat :)
diff --git a/fs/fs.c b/fs/fs.c
+int fs_uuid(char *uuid_str)
+{
+ struct fstype_info *info = fs_get_info(fs_type);
+ int ret = -ENOSYS;
+
+ if (info-uuid)
+ ret = info-uuid(uuid_str);
+
+ return ret;
+}
Actually, that might be better as:
return info-uuid(uuid_str);
To make that work, you'd need to implement a fs_uuid_unsuported() function
and fill it in for all the fs types in fstypes[]. That would be more
consistent with the way other optional functionality works in this file.
I will do it that way - looks more consistent.
greets
--
Christian Gmeiner, MSc
https://soundcloud.com/christian-gmeiner
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Re: [U-Boot] [PATCH] fs: make it possible to read the filesystem UUID
Hi
2014-11-04 7:31 GMT+01:00 Simon Glass s...@chromium.org:
Hi Christian,
On 31 October 2014 09:08, Christian Gmeiner christian.gmei...@gmail.com
wrote:
Some filesystems have a UUID stored in its superblock. To
allow using root=UUID=... for the kernel command line we
need a way to read-out the filesystem UUID.
Hit any key to stop autoboot: 0
= fsuuid
fsuuid - Look up a filesystem UUID
Usage:
fsuuid interface dev:part
- print filesystem UUID
fsuuid interface dev:part varname
- set environment variable to filesystem UUID
= fsuuid mmc 0:1
d9f9fc05-45ae-4a36-a616-fccce0e4f887
= fsuuid mmc 0:2
eb3db83c-7b28-499f-95ce-9e0bb21cda81
= fsuuid mmc 0:1 uuid1
= fsuuid mmc 0:2 uuid2
= printenv uuid1
uuid1=d9f9fc05-45ae-4a36-a616-fccce0e4f887
= printenv uuid2
uuid2=eb3db83c-7b28-499f-95ce-9e0bb21cda81
=
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
README | 1 +
common/Makefile | 1 +
fs/ext4/ext4fs.c | 15 +++
fs/fs.c | 39 +++
include/ext4fs.h | 1 +
include/fs.h | 2 ++
6 files changed, 59 insertions(+)
diff --git a/README b/README
index 7b5538e..53b84a6 100644
--- a/README
+++ b/README
@@ -989,6 +989,7 @@ The following options need to be configured:
CONFIG_CMD_EXT4 * ext4 command support
CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls)
that work for multiple fs types
+ CONFIG_CMD_FS_UUID * Look up a filesystem UUID
CONFIG_CMD_SAVEENVsaveenv
CONFIG_CMD_FDC * Floppy Disk Support
CONFIG_CMD_FAT * FAT command support
diff --git a/common/Makefile b/common/Makefile
index 6cc4de8..508a0b2 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -188,6 +188,7 @@ obj-y += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
+obj-$(CONFIG_CMD_FS_UUID) += cmd_fs_uuid.o
obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index cbdc220..61b6dc2 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -187,6 +187,21 @@ int ext4fs_size(const char *filename)
return ext4fs_open(filename);
}
+int ext4fs_uuid(char *uuid_str)
+{
+ if (ext4fs_root == NULL)
+ return -1;
One other tiny note - should that be -ENOENT or some other error perhaps?
I used the other functions as inspiration. I think that needs to be in
a follow up commit
as it affects more functions.
greets
--
Christian Gmeiner, MSc
https://soundcloud.com/christian-gmeiner
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Re: [U-Boot] [PATCH] fs: make it possible to read the filesystem UUID
Hi 2014-11-04 19:41 GMT+01:00 Simon Glass s...@chromium.org: Hi Christian, On 3 November 2014 02:47, Christian Gmeiner christian.gmei...@gmail.com wrote: Hi Simon, [snip] + + if (argc == 4) + setenv(argv[3], uuid); + else + printf(%s\n, uuid); + + return 0; +} diff --git a/include/ext4fs.h b/include/ext4fs.h index 6c419f3..19816de 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -137,6 +137,7 @@ void ext4fs_reinit_global(void); int ext4fs_ls(const char *dirname); int ext4fs_exists(const char *filename); int ext4fs_size(const char *filename); +int ext4fs_uuid(char *uuid_str); void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf); void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); diff --git a/include/fs.h b/include/fs.h index 06a45f2..41082b3 100644 --- a/include/fs.h +++ b/include/fs.h @@ -92,5 +92,7 @@ int file_exists(const char *dev_type, const char *dev_part, const char *file, int fstype); int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); +int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype); Can you please add a function comment for this? Yes I will add one - directly here in the .h file? Yes I think so - this is where the API is Great! Cheers -- Christian Gmeiner, MSc https://soundcloud.com/christian-gmeiner ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] omap_hsmmc: Board-specific TWL4030 MMC power initializations
On Tue, Nov 11, 2014 at 12:57:45PM +0100, Paul Kocialkowski wrote:
Le lundi 10 novembre 2014 à 13:46 -0500, Tom Rini a écrit :
On Sat, Nov 08, 2014 at 10:29:24PM +0100, Paul Kocialkowski wrote:
Le samedi 08 novembre 2014 à 20:55 +0100, Paul Kocialkowski a écrit :
Boards using the TWL4030 regulator may not all use the LDOs the same way
(e.g. MMC2 power can be controlled by another LDO than VMMC2).
This delegates TWL4030 MMC power initializations to board-specific
functions,
that may still call twl4030_power_mmc_init for the default behavior.
Signed-off-by: Paul Kocialkowski cont...@paulk.fr
---
board/comelit/dig297/dig297.c | 5 +
board/compulab/cm_t35/cm_t35.c | 7 +++
board/corscience/tricorder/tricorder.c | 7 +++
board/isee/igep00x0/igep00x0.c | 7 +++
board/logicpd/omap3som/omap3logic.c| 7 +++
board/logicpd/zoom1/zoom1.c| 5 +
board/matrix_vision/mvblx/mvblx.c | 6 ++
board/nokia/rx51/rx51.c| 6 ++
board/overo/overo.c| 7 +++
board/pandora/pandora.c| 5 +
board/technexion/tao3530/tao3530.c | 7 +++
board/ti/beagle/beagle.c | 7 +++
board/ti/evm/evm.c | 7 +++
board/ti/sdp3430/sdp.c | 5 +
board/timll/devkit8000/devkit8000.c| 7 +++
drivers/mmc/omap_hsmmc.c | 7 +--
16 files changed, 96 insertions(+), 6 deletions(-)
diff --git a/board/comelit/dig297/dig297.c
b/board/comelit/dig297/dig297.c
index 2b826df..9d4c41b 100644
--- a/board/comelit/dig297/dig297.c
+++ b/board/comelit/dig297/dig297.c
@@ -133,6 +133,11 @@ int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
I just figured, in the context of the SPL, board_mmc_init will be called
from omap3/board.c instead of the board file, so perhaps it would be
worth adding, in board_mmc_power_init: #ifdef CONFIG_SPL_BUILD and then
checking spl_boot_device to only enable the relevant LDO.
If we get to this point we can do the same thing we do for
board_mmc_init which is have one in say
arch/arm/cpu/armv7/omap-common/boot-common.c that checks
spl_boot_device()
That wouldn't work for my use case, on the Optimus Black, where
regulators are used in a non-standard way. The whole point of this to me
is to not have platform-common code to handle MMC regulators, because
the way those are wired to MMC devices is not the same for each
platform, but is instead board-specific.
Is there any objection to making a v5 that takes the SPL context in
account on each of those boards?
Oh that's right, hmm. I think the answer is that for the SPL case where
we _need_ to do something different, the board can already provide that
and do it, with v4. The general case is that ROM will have done what
needs doing for MMCSD load and in your case you can always go and turn
it on in the board code.
--
Tom
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[U-Boot] [PATCH] ARM: UniPhier: decrease pre-reloc malloc area size
In the current implementation of the boot sequence of UniPhier platform, 32KB temporary RAM is available before relocation. The malloc area and the stack shares the 32KB area. With CONFIG_SYS_MALLOC_F_LEN set to 0x7000 (28KB), only 0x1000 (4KB) is left for the stack. In some use cases, the system hangs up with stack over-flow. Even with driver-model UART enabled, the malloc area of 0x2000 (8KB) should be enough. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- include/configs/uniphier-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h index b18ae6d..ef81914 100644 --- a/include/configs/uniphier-common.h +++ b/include/configs/uniphier-common.h @@ -43,7 +43,7 @@ are defined. Select only one of them. #define CONFIG_SMC911X_BASECONFIG_SUPPORT_CARD_ETHER_BASE #define CONFIG_SMC911X_32_BIT -#define CONFIG_SYS_MALLOC_F_LEN 0x7000 +#define CONFIG_SYS_MALLOC_F_LEN 0x2000 /*--- * MMU and Cache Setting -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 0/3] Adds support for Exynos5422 odroid xu3 board
On 10 November 2014 10:41, Hyungwon Hwang human.hw...@samsung.com wrote:
This is v6 of the patchset adding support Odroud XU3 board.
link to the previous version:
v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html
v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html
v4: https://patchwork.ozlabs.org/patch/407411/
v5: https://patchwork.ozlabs.org/patch/407941/
This patchset fixes GPIO information of Exynos5420 which is needed to
support Exynos5422 Odroid XU3 board. On the base of the fixes, this
patchset adds support for Exynos5422 Odroid XU3 board. I have done this
work on the master branch in http://git.denx.de/u-boot-samsung.git (sha1:
26f195c71252e98aebfffd5cfa994a4475559370) with patches by Akshay Saraswat.
link: https://patchwork.ozlabs.org/patch/405246/ (updated)
How to test this patch:
1. git clone http://git.denx.de/u-boot-samsung.git
2. git reset --hard 26f195c71252e98aebfffd5cfa994a4475559370
3. Get and apply the patchset of Akshay Saraswat
https://patchwork.ozlabs.org/patch/405246/
https://patchwork.ozlabs.org/patch/405247/
https://patchwork.ozlabs.org/patch/405248/
https://patchwork.ozlabs.org/patch/405249/
https://patchwork.ozlabs.org/patch/405250/
https://patchwork.ozlabs.org/patch/405251/
https://patchwork.ozlabs.org/patch/405252/
4. Apply this patchset
5. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- odroid-xu3_config
6. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j8
7. Now you can use u-boot-dtb.bin for your downloading
Note: If you use micro SD card for your test you have to apply the below
patch additionally. This patch is needed, because micro sd card is
recognized as MMC1 instead of MMC0. Additional work is needed to make it
work regardless of device id.
diff --git a/include/configs/exynos5-common.h
b/include/configs/exynos5-common.h
index ba591e7..437eaae 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -109,7 +109,7 @@
#define CONFIG_SYS_MONITOR_BASE0x
-#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SECURE_BL1_ONLY
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index cda4f26..b46ccad 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -110,15 +110,15 @@
run kernel_args; \
bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0 \
autoboot= \
- if test -e mmc 0 Image.itb; then; \
+ if test -e mmc 1 Image.itb; then; \
run boot_fit; \
- elif test -e mmc 0 zImage; then; \
+ elif test -e mmc 1 zImage; then; \
run boot_zimg; \
- elif test -e mmc 0 uImage; then; \
+ elif test -e mmc 1 uImage; then; \
run boot_uimg; \
fi;\0 \
console= CONFIG_DEFAULT_CONSOLE \
- mmcbootdev=0\0 \
+ mmcbootdev=1\0 \
mmcbootpart=1\0 \
mmcrootdev=0\0 \
mmcrootpart=2\0 \
I think you can make it selectable as env value.
How you think?
Thanks,
Minkyu Kang.
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[U-Boot] [PATCH v2] fs: make it possible to read the filesystem UUID
Some filesystems have a UUID stored in its superblock. To
allow using root=UUID=... for the kernel command line we
need a way to read-out the filesystem UUID.
changes rfc - v1:
- make the environment variable an option parameter. If not
given, the UUID is printed out. If given, it is stored in the env
variable.
- corrected typos
- return error codes
changes v1 - v2:
- fix return code of do_fs_uuid(..)
- document do_fs_uuid(..)
- implement fs_uuid_unsuported(..) be more consistent with the
way other optional functionality works
Hit any key to stop autoboot: 0
= fsuuid
fsuuid - Look up a filesystem UUID
Usage:
fsuuid interface dev:part
- print filesystem UUID
fsuuid interface dev:part varname
- set environment variable to filesystem UUID
= fsuuid mmc 0:1
d9f9fc05-45ae-4a36-a616-fccce0e4f887
= fsuuid mmc 0:2
eb3db83c-7b28-499f-95ce-9e0bb21cda81
= fsuuid mmc 0:1 uuid1
= fsuuid mmc 0:2 uuid2
= printenv uuid1
uuid1=d9f9fc05-45ae-4a36-a616-fccce0e4f887
= printenv uuid2
uuid2=eb3db83c-7b28-499f-95ce-9e0bb21cda81
=
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
README | 1 +
common/Makefile | 1 +
common/cmd_fs_uuid.c | 26 ++
fs/ext4/ext4fs.c | 15 +++
fs/fs.c | 43 +++
include/ext4fs.h | 1 +
include/fs.h | 7 +++
7 files changed, 94 insertions(+)
create mode 100644 common/cmd_fs_uuid.c
diff --git a/README b/README
index 7b5538e..53b84a6 100644
--- a/README
+++ b/README
@@ -989,6 +989,7 @@ The following options need to be configured:
CONFIG_CMD_EXT4 * ext4 command support
CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls)
that work for multiple fs types
+ CONFIG_CMD_FS_UUID * Look up a filesystem UUID
CONFIG_CMD_SAVEENVsaveenv
CONFIG_CMD_FDC * Floppy Disk Support
CONFIG_CMD_FAT * FAT command support
diff --git a/common/Makefile b/common/Makefile
index 6cc4de8..508a0b2 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -188,6 +188,7 @@ obj-y += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
+obj-$(CONFIG_CMD_FS_UUID) += cmd_fs_uuid.o
obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
diff --git a/common/cmd_fs_uuid.c b/common/cmd_fs_uuid.c
new file mode 100644
index 000..613f3a4
--- /dev/null
+++ b/common/cmd_fs_uuid.c
@@ -0,0 +1,26 @@
+/*
+ * cmd_fs_uuid.c -- fsuuid command
+ *
+ * Copyright (C) 2014, Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include command.h
+#include fs.h
+
+static int do_fs_uuid_wrapper(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ return do_fs_uuid(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+ fsuuid, 4, 1, do_fs_uuid_wrapper,
+ Look up a filesystem UUID,
+ interface dev:part\n
+ - print filesystem UUID\n
+ fsuuid interface dev:part varname\n
+ - set environment variable to filesystem UUID\n
+);
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index cbdc220..19757d2 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -231,3 +231,18 @@ int ext4_read_file(const char *filename, void *buf, int
offset, int len)
return len_read;
}
+
+int ext4fs_uuid(char *uuid_str)
+{
+ if (ext4fs_root == NULL)
+ return -1;
+
+#ifdef CONFIG_LIB_UUID
+ uuid_bin_to_str((unsigned char *)ext4fs_root-sblock.unique_id,
+ uuid_str, UUID_STR_FORMAT_STD);
+
+ return 0;
+#endif
+
+ return -ENOSYS;
+}
diff --git a/fs/fs.c b/fs/fs.c
index dd680f3..e4ad6bc 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -15,6 +15,7 @@
*/
#include config.h
+#include errno.h
#include common.h
#include part.h
#include ext4fs.h
@@ -67,6 +68,11 @@ static inline void fs_close_unsupported(void)
{
}
+static inline int fs_uuid_unsupported(char *uuid_str)
+{
+ return -1;
+}
+
struct fstype_info {
int fstype;
/*
@@ -86,6 +92,7 @@ struct fstype_info {
int (*read)(const char *filename, void *buf, int offset, int len);
int (*write)(const char *filename, void *buf, int offset, int len);
void (*close)(void);
+ int (*uuid)(char *uuid_str);
};
static struct fstype_info fstypes[] = {
@@ -100,6 +107,7 @@ static struct fstype_info fstypes[] = {
.size = fat_size,
.read = fat_read_file,
.write = fs_write_unsupported,
+ .uuid = fs_uuid_unsupported,
},
#endif
#ifdef CONFIG_FS_EXT4
@@ -113,6 +121,7 @@ static struct fstype_info fstypes[] = {
.size = ext4fs_size,
.read = ext4_read_file,
[U-Boot] [PATCH 2/2] mtd: denali: set some registers after nand_scan_ident()
Some but not all of implementations of the Denali NAND controller have hardware circuits to detect the device parameters such as page_size, erase_size, etc. Even on those SoCs with such hardware supported, the hardware is known to detect wrong parameters for some nasty (almost buggy) NAND devices. The device parameters detected during nand_scan_ident() are more trustworthy. This commit sets some hardware registers to mtd-pagesize, mtd-oobsize, etc. in the code between nand_scan_ident() and nand_scan_tail(). Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Cc: Scott Wood scottw...@freescale.com Cc: Chin Liang See cl...@altera.com --- drivers/mtd/nand/denali.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index a9838d8..a2b346e 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1209,6 +1209,17 @@ static int denali_init(struct denali_nand_info *denali) nand_oob.eccbytes = denali-nand.ecc.bytes; denali-nand.ecc.layout = nand_oob; + writel(denali-mtd-erasesize / denali-mtd-writesize, + denali-flash_reg + PAGES_PER_BLOCK); + writel(denali-nand.options NAND_BUSWIDTH_16 ? 1 : 0, + denali-flash_reg + DEVICE_WIDTH); + writel(denali-mtd-writesize, + denali-flash_reg + DEVICE_MAIN_AREA_SIZE); + writel(denali-mtd-oobsize, + denali-flash_reg + DEVICE_SPARE_AREA_SIZE); + if (readl(denali-flash_reg + DEVICES_CONNECTED) == 0) + writel(1, denali-flash_reg + DEVICES_CONNECTED); + /* override the default operations */ denali-nand.ecc.read_page = denali_read_page; denali-nand.ecc.read_page_raw = denali_read_page_raw; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] mtd: denali: Use SELF_INIT to fix up registers after nand_scan_ident()
This patch series is here because Scott Wood recommended me to use CONFIG_SYS_NAND_SELF_INIT to solve my problem: http://patchwork.ozlabs.org/patch/402462/ Masahiro Yamada (2): mtd: denali: use CONFIG_SYS_NAND_SELF_INIT mtd: denali: set some registers after nand_scan_ident() drivers/mtd/nand/Kconfig | 7 +++ drivers/mtd/nand/denali.c | 131 +- drivers/mtd/nand/denali.h | 5 +- 3 files changed, 103 insertions(+), 40 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] mtd: denali: use CONFIG_SYS_NAND_SELF_INIT
Some variants of the Denali NAND controller need some registers
set up based on the device information that has been detected during
nand_scan_ident().
CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between
nand_scan_ident() and nand_scan_tail(). It is also helpful to reduce
the difference between this driver and its Linux counterpart because
this driver was ported from Linux. Moreover, doc/README.nand recommends
to use CONFIG_SYS_NAND_SELF_INIT.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Scott Wood scottw...@freescale.com
Cc: Chin Liang See cl...@altera.com
---
drivers/mtd/nand/Kconfig | 7 +++
drivers/mtd/nand/denali.c | 120 --
drivers/mtd/nand/denali.h | 5 +-
3 files changed, 92 insertions(+), 40 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 75c2c06..c242214 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -1,9 +1,16 @@
menu NAND Device Support
+config SYS_NAND_SELF_INIT
+ bool
+ help
+ This option, if enabled, provides more flexible and linux-like
+ NAND initialization process.
+
if !SPL_BUILD
config NAND_DENALI
bool Support Denali NAND controller
+ select SYS_NAND_SELF_INIT
help
Enable support for the Denali NAND controller.
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 308b784..a9838d8 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -44,7 +44,7 @@ static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
* this macro allows us to convert from an MTD structure to our own
* device context (denali) structure.
*/
-#define mtd_to_denali(m) (((struct nand_chip *)mtd-priv)-priv)
+#define mtd_to_denali(m) container_of(m-priv, struct denali_nand_info, nand)
/* These constants are defined by the driver to enable common driver
* configuration options. */
@@ -1144,70 +1144,116 @@ static void denali_hw_init(struct denali_nand_info
*denali)
static struct nand_ecclayout nand_oob;
-static int denali_nand_init(struct nand_chip *nand)
+static int denali_init(struct denali_nand_info *denali)
{
- struct denali_nand_info *denali;
+ int ret;
- denali = malloc(sizeof(*denali));
- if (!denali)
- return -ENOMEM;
+ denali_hw_init(denali);
- nand-priv = denali;
+ denali-mtd-name = denali-nand;
+ denali-mtd-owner = THIS_MODULE;
+ denali-mtd-priv = denali-nand;
- denali-flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
- denali-flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+ /* register the driver with the NAND core subsystem */
+ denali-nand.select_chip = denali_select_chip;
+ denali-nand.cmdfunc = denali_cmdfunc;
+ denali-nand.read_byte = denali_read_byte;
+ denali-nand.read_buf = denali_read_buf;
+ denali-nand.waitfunc = denali_waitfunc;
+
+ /*
+* scan for NAND devices attached to the controller
+* this is the first stage in a two step process to register
+* with the nand subsystem
+*/
+ if (nand_scan_ident(denali-mtd, denali-max_banks, NULL)) {
+ ret = -ENXIO;
+ goto fail;
+ }
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
/* check whether flash got BBT table (located at end of flash). As we
* use NAND_BBT_NO_OOB, the BBT page will start with
* bbt_pattern. We will have mirror pattern too */
- nand-bbt_options |= NAND_BBT_USE_FLASH;
+ denali-nand.bbt_options |= NAND_BBT_USE_FLASH;
/*
* We are using main + spare with ECC support. As BBT need ECC support,
* we need to ensure BBT code don't write to OOB for the BBT pattern.
* All BBT info will be stored into data area with ECC support.
*/
- nand-bbt_options |= NAND_BBT_NO_OOB;
+ denali-nand.bbt_options |= NAND_BBT_NO_OOB;
#endif
- nand-ecc.mode = NAND_ECC_HW;
- nand-ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
- nand-ecc.read_oob = denali_read_oob;
- nand-ecc.write_oob = denali_write_oob;
- nand-ecc.read_page = denali_read_page;
- nand-ecc.read_page_raw = denali_read_page_raw;
- nand-ecc.write_page = denali_write_page;
- nand-ecc.write_page_raw = denali_write_page_raw;
+ denali-nand.ecc.mode = NAND_ECC_HW;
+ denali-nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
+
/*
* Tell driver the ecc strength. This register may be already set
* correctly. So we read this value out.
*/
- nand-ecc.strength = readl(denali-flash_reg + ECC_CORRECTION);
- switch (nand-ecc.size) {
+ denali-nand.ecc.strength = readl(denali-flash_reg + ECC_CORRECTION);
+ switch (denali-nand.ecc.size) {
case 512:
- nand-ecc.bytes = (nand-ecc.strength * 13 + 15) / 16 * 2;
+
Re: [U-Boot] [PATCH v2] mtd: nand: allow to skip BBT scanning during NAND inititialization
Hi Scott, On Tue, 4 Nov 2014 23:45:44 -0600 Scott Wood scottw...@freescale.com wrote: On Wed, 2014-11-05 at 12:39 +0900, Masahiro Yamada wrote: [2] There is no good place to insert a callback to an SoC file. I need to write parameters such as page_size to hardware registers. (You can see my code, nand_denali_fixup() in arch/arm/cpu/armv7/uniphier/board_late_init.c) The NAND init procedure of U-Boot is like this: (1) board_nand_init() (drivers/mtd/nand/denali.c) (2) nand_scan_ident() (drivers/mtd/nand/nand_base.c) (3) nand_scan_tail()(drivers/mtd/nand/nand_base.c) (2) detects the device size and set mtd-write_size, mtd-erase_size, mtd-oob_size. I need to set these values to the Denali hardware, but the Denali driver code is called at (1) which is called before the detection of the device size. In Linux, nand_scan_ident() and nand_scan_tail() are called from each of NAND drivers, so we can use the values which have been set during nand_scan_ident(). In U-Boot, I think it is impossible. If you use CONFIG_SYS_NAND_SELF_INIT you can insert code between nand_scan_ident() and nand_scan_tail(), just like in Linux. Thanks for your advice! I have posted patches: http://patchwork.ozlabs.org/patch/409429/ http://patchwork.ozlabs.org/patch/409428/ Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] omap_hsmmc: Board-specific TWL4030 MMC power initializations
Le mardi 11 novembre 2014 à 07:33 -0500, Tom Rini a écrit :
On Tue, Nov 11, 2014 at 12:57:45PM +0100, Paul Kocialkowski wrote:
Le lundi 10 novembre 2014 à 13:46 -0500, Tom Rini a écrit :
On Sat, Nov 08, 2014 at 10:29:24PM +0100, Paul Kocialkowski wrote:
Le samedi 08 novembre 2014 à 20:55 +0100, Paul Kocialkowski a écrit :
Boards using the TWL4030 regulator may not all use the LDOs the same
way
(e.g. MMC2 power can be controlled by another LDO than VMMC2).
This delegates TWL4030 MMC power initializations to board-specific
functions,
that may still call twl4030_power_mmc_init for the default behavior.
Signed-off-by: Paul Kocialkowski cont...@paulk.fr
---
board/comelit/dig297/dig297.c | 5 +
board/compulab/cm_t35/cm_t35.c | 7 +++
board/corscience/tricorder/tricorder.c | 7 +++
board/isee/igep00x0/igep00x0.c | 7 +++
board/logicpd/omap3som/omap3logic.c| 7 +++
board/logicpd/zoom1/zoom1.c| 5 +
board/matrix_vision/mvblx/mvblx.c | 6 ++
board/nokia/rx51/rx51.c| 6 ++
board/overo/overo.c| 7 +++
board/pandora/pandora.c| 5 +
board/technexion/tao3530/tao3530.c | 7 +++
board/ti/beagle/beagle.c | 7 +++
board/ti/evm/evm.c | 7 +++
board/ti/sdp3430/sdp.c | 5 +
board/timll/devkit8000/devkit8000.c| 7 +++
drivers/mmc/omap_hsmmc.c | 7 +--
16 files changed, 96 insertions(+), 6 deletions(-)
diff --git a/board/comelit/dig297/dig297.c
b/board/comelit/dig297/dig297.c
index 2b826df..9d4c41b 100644
--- a/board/comelit/dig297/dig297.c
+++ b/board/comelit/dig297/dig297.c
@@ -133,6 +133,11 @@ int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
I just figured, in the context of the SPL, board_mmc_init will be called
from omap3/board.c instead of the board file, so perhaps it would be
worth adding, in board_mmc_power_init: #ifdef CONFIG_SPL_BUILD and then
checking spl_boot_device to only enable the relevant LDO.
If we get to this point we can do the same thing we do for
board_mmc_init which is have one in say
arch/arm/cpu/armv7/omap-common/boot-common.c that checks
spl_boot_device()
That wouldn't work for my use case, on the Optimus Black, where
regulators are used in a non-standard way. The whole point of this to me
is to not have platform-common code to handle MMC regulators, because
the way those are wired to MMC devices is not the same for each
platform, but is instead board-specific.
Is there any objection to making a v5 that takes the SPL context in
account on each of those boards?
Oh that's right, hmm. I think the answer is that for the SPL case where
we _need_ to do something different, the board can already provide that
and do it, with v4. The general case is that ROM will have done what
needs doing for MMCSD load and in your case you can always go and turn
it on in the board code.
That should indeed cover most use cases. So let's let boards enable all
the regulators they may need for MMC in board_mmc_power_init.
I'm good with v4 then!
--
Paul Kocialkowski, Replicant developer
Replicant is a fully free Android distribution
Website: http://www.replicant.us/
Blog: http://blog.replicant.us/
Wiki/tracker/forums: http://redmine.replicant.us/
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[U-Boot] [PATCH 1/2] ARM: UniPhier: consolidate board_postclk_init() function
This commit merges
arch/arm/cpu/armv7/uniphier/ph1-*/board_postclk_init.c
to
arch/arm/cpu/armv7/uniphier/board_postclk_init.c
Because PH1-Pro4 does not have the BCU block, add __weak to
bcu_init().
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
arch/arm/cpu/armv7/uniphier/Makefile | 1 +
.../uniphier/{ph1-ld4 = }/board_postclk_init.c| 6 ++--
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 4 +--
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 4 +--
.../armv7/uniphier/ph1-pro4/board_postclk_init.c | 41 --
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 4 +--
.../armv7/uniphier/ph1-sld8/board_postclk_init.c | 1 -
7 files changed, 11 insertions(+), 50 deletions(-)
rename arch/arm/cpu/armv7/uniphier/{ph1-ld4 = }/board_postclk_init.c (90%)
delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c
delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile
b/arch/arm/cpu/armv7/uniphier/Makefile
index dd57469..0f64d25 100644
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += timer.o
obj-y += reset.o
obj-y += cache_uniphier.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
obj-y += dram_init.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c
b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c
similarity index 90%
rename from arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c
rename to arch/arm/cpu/armv7/uniphier/board_postclk_init.c
index 5bb8179..3db336f 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c
+++ b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c
@@ -5,11 +5,13 @@
* SPDX-License-Identifier:GPL-2.0+
*/
-#include common.h
+#include linux/compiler.h
#include asm/arch/led.h
#include asm/arch/board.h
-void bcu_init(void);
+void __weak bcu_init(void)
+{
+};
void sbc_init(void);
void sg_init(void);
void pll_init(void);
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index 1df0219..e9e9b32 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -6,6 +6,6 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
- sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += bcu_init.o sbc_init.o sg_init.o \
+ pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index 144e6fc..272fecc 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -6,6 +6,6 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
- sg_init.o pll_init.o clkrst_init.o pinctrl.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += sbc_init.o sg_init.o \
+ pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c
deleted file mode 100644
index 9a53743..000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada yamad...@jp.panasonic.com
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include common.h
-#include asm/arch/led.h
-#include asm/arch/board.h
-
-void sbc_init(void);
-void sg_init(void);
-void pll_init(void);
-void pin_init(void);
-void clkrst_init(void);
-
-int board_postclk_init(void)
-{
- sbc_init();
-
- sg_init();
-
- uniphier_board_reset();
-
- pll_init();
-
- uniphier_board_init();
-
- led_write(B, 1, , );
-
- clkrst_init();
-
- led_write(B, 2, , );
-
- pin_init();
-
- led_write(B, 3, , );
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
index 1df0219..e9e9b32 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -6,6 +6,6 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_DEBUG_LL) +=
[U-Boot] [PATCH 2/2] ARM: UniPhier: call pin_init() also in the normal boot
CONFIG_UNIPHIER_SERIAL has been moved to Kconfig and
it is defined in ./.config but not in spl/.config,
so pin_init() should be called from the normal image
so that UART works correctly.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
arch/arm/cpu/armv7/uniphier/Kconfig | 4
arch/arm/cpu/armv7/uniphier/board_postclk_init.c | 3 ++-
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 5 +++--
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile| 4 ++--
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile| 5 +++--
include/configs/uniphier-common.h| 4 ++--
6 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig
b/arch/arm/cpu/armv7/uniphier/Kconfig
index 011c6d9..36b7f11 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -32,6 +32,10 @@ config CMD_PINMON
The boot mode pins are latched when the system reset is deasserted
and determine which device the system should load a boot image from.
+config SOC_INIT
+ bool
+ default SPL_BUILD
+
config DRAM_INIT
bool
default SPL_BUILD
diff --git a/arch/arm/cpu/armv7/uniphier/board_postclk_init.c
b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c
index 3db336f..89e44bb 100644
--- a/arch/arm/cpu/armv7/uniphier/board_postclk_init.c
+++ b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c
@@ -20,6 +20,7 @@ void clkrst_init(void);
int board_postclk_init(void)
{
+#ifdef CONFIG_SOC_INIT
bcu_init();
sbc_init();
@@ -37,7 +38,7 @@ int board_postclk_init(void)
clkrst_init();
led_write(B, 2, , );
-
+#endif
pin_init();
led_write(B, 3, , );
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index e9e9b32..f0c66c6 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += bcu_init.o sbc_init.o sg_init.o \
- pll_init.o clkrst_init.o pinctrl.o
+obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
+ clkrst_init.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index 272fecc..0e8f4c5 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -6,6 +6,6 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += sbc_init.o sg_init.o \
- pll_init.o clkrst_init.o pinctrl.o
+obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
index e9e9b32..f0c66c6 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += bcu_init.o sbc_init.o sg_init.o \
- pll_init.o clkrst_init.o pinctrl.o
+obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
+ clkrst_init.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
diff --git a/include/configs/uniphier-common.h
b/include/configs/uniphier-common.h
index 45becc1..7c4dba0 100644
--- a/include/configs/uniphier-common.h
+++ b/include/configs/uniphier-common.h
@@ -248,9 +248,9 @@ are defined. Select only one of them.
#define CONFIG_SYS_TEXT_BASE 0x8400
-#if defined(CONFIG_SPL_BUILD)
#define CONFIG_BOARD_POSTCLK_INIT
-#else
+
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
--
1.9.1
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[U-Boot] [PATCH 0/2] ARM: UniPhier: some cleanups and bug fix
Masahiro Yamada (2):
ARM: UniPhier: consolidate board_postclk_init() function
ARM: UniPhier: call pin_init() also in the normal boot
arch/arm/cpu/armv7/uniphier/Kconfig| 4 +++
arch/arm/cpu/armv7/uniphier/Makefile | 1 +
.../uniphier/{ph1-ld4 = }/board_postclk_init.c| 9 +++--
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 5 +--
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 4 +--
.../armv7/uniphier/ph1-pro4/board_postclk_init.c | 41 --
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 5 +--
.../armv7/uniphier/ph1-sld8/board_postclk_init.c | 1 -
include/configs/uniphier-common.h | 4 +--
9 files changed, 21 insertions(+), 53 deletions(-)
rename arch/arm/cpu/armv7/uniphier/{ph1-ld4 = }/board_postclk_init.c (86%)
delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c
delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c
--
1.9.1
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[U-Boot] [PATCH V2] powerpc: remove orphaned boards mcc200 and prs200
mcc200 and prs200 are old and have no maintainer. Remove the boards. This also removes the mcc200 specific 1bpp BMP support from common/lcd.c Cc: Wolfgang Denk w...@denx.de Cc: Anatolij Gustschin ag...@denx.de Cc: Masahiro Yamada yamad...@jp.panasonic.com Cc: York Sun york...@freescale.com Signed-off-by: Nikita Kiryanov nik...@compulab.co.il --- Changes in V2: - Updated README.scrapyard in chronological order - Updated missing commit ids and dates of previous removals - Left removal date blank in mcc200 entry in README.scrapyard arch/powerpc/cpu/mpc5xxx/Kconfig | 4 - board/mcc200/Kconfig | 9 - board/mcc200/MAINTAINERS | 17 - board/mcc200/Makefile | 8 - board/mcc200/auto_update.c| 521 -- board/mcc200/lcd.c| 200 -- board/mcc200/mcc200.c | 314 board/mcc200/mt46v16m16-75.h | 16 - board/mcc200/mt48lc16m16a2-75.h | 14 - board/mcc200/mt48lc16m32s2-75.h | 14 - board/mcc200/mt48lc8m32b2-6-7.h | 12 - common/lcd.c | 24 +- configs/mcc200_COM12_SDRAM_defconfig | 4 - configs/mcc200_COM12_defconfig| 4 - configs/mcc200_COM12_highboot_SDRAM_defconfig | 4 - configs/mcc200_COM12_highboot_defconfig | 4 - configs/mcc200_SDRAM_defconfig| 4 - configs/mcc200_defconfig | 3 - configs/mcc200_highboot_SDRAM_defconfig | 4 - configs/mcc200_highboot_defconfig | 4 - configs/prs200_DDR_defconfig | 4 - configs/prs200_defconfig | 4 - configs/prs200_highboot_DDR_defconfig | 4 - configs/prs200_highboot_defconfig | 4 - doc/README.scrapyard | 8 +- include/configs/mcc200.h | 397 include/lcd.h | 2 +- 27 files changed, 7 insertions(+), 1600 deletions(-) delete mode 100644 board/mcc200/Kconfig delete mode 100644 board/mcc200/MAINTAINERS delete mode 100644 board/mcc200/Makefile delete mode 100644 board/mcc200/auto_update.c delete mode 100644 board/mcc200/lcd.c delete mode 100644 board/mcc200/mcc200.c delete mode 100644 board/mcc200/mt46v16m16-75.h delete mode 100644 board/mcc200/mt48lc16m16a2-75.h delete mode 100644 board/mcc200/mt48lc16m32s2-75.h delete mode 100644 board/mcc200/mt48lc8m32b2-6-7.h delete mode 100644 configs/mcc200_COM12_SDRAM_defconfig delete mode 100644 configs/mcc200_COM12_defconfig delete mode 100644 configs/mcc200_COM12_highboot_SDRAM_defconfig delete mode 100644 configs/mcc200_COM12_highboot_defconfig delete mode 100644 configs/mcc200_SDRAM_defconfig delete mode 100644 configs/mcc200_defconfig delete mode 100644 configs/mcc200_highboot_SDRAM_defconfig delete mode 100644 configs/mcc200_highboot_defconfig delete mode 100644 configs/prs200_DDR_defconfig delete mode 100644 configs/prs200_defconfig delete mode 100644 configs/prs200_highboot_DDR_defconfig delete mode 100644 configs/prs200_highboot_defconfig delete mode 100644 include/configs/mcc200.h diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index c1fb92a..bd64ea6 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -38,9 +38,6 @@ config TARGET_IPEK01 config TARGET_JUPITER bool Support jupiter -config TARGET_MCC200 - bool Support mcc200 - config TARGET_MOTIONPRO bool Support motionpro @@ -130,7 +127,6 @@ source board/jupiter/Kconfig source board/manroland/hmi1001/Kconfig source board/manroland/mucmc52/Kconfig source board/manroland/uc101/Kconfig -source board/mcc200/Kconfig source board/motionpro/Kconfig source board/munices/Kconfig source board/phytec/pcm030/Kconfig diff --git a/board/mcc200/Kconfig b/board/mcc200/Kconfig deleted file mode 100644 index 3b27eeb..000 --- a/board/mcc200/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MCC200 - -config SYS_BOARD - default mcc200 - -config SYS_CONFIG_NAME - default mcc200 - -endif diff --git a/board/mcc200/MAINTAINERS b/board/mcc200/MAINTAINERS deleted file mode 100644 index a59a498..000 --- a/board/mcc200/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -MCC200 BOARD -#M:- -S: Maintained -F: board/mcc200/ -F: include/configs/mcc200.h -F: configs/mcc200_defconfig -F: configs/mcc200_COM12_defconfig -F: configs/mcc200_COM12_highboot_defconfig -F: configs/mcc200_COM12_highboot_SDRAM_defconfig -F: configs/mcc200_COM12_SDRAM_defconfig -F: configs/mcc200_highboot_defconfig -F: configs/mcc200_highboot_SDRAM_defconfig -F: configs/mcc200_SDRAM_defconfig -F: configs/prs200_defconfig -F: configs/prs200_DDR_defconfig -F:
Re: [U-Boot] [PATCH] ot1200: fix card detect for usdhc4
Hi Christian,
On 11/11/2014 12:57, Christian Gmeiner wrote:
Today I got the final board and found out that a different
connector is used as the one on my development board. The
new connector has swaped pins for cd and wp.
It is always so..final board is different from development board ;-)
This change is tested on a production ready baord.
baord -- board
Maybe your disappointment in the commit message can be removed, and let
that the production board has swaped pins.
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
board/bachmann/ot1200/ot1200.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 2ed8cf7..007c1ef 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -159,8 +159,8 @@ int board_mmc_getcd(struct mmc *mmc)
gpio_direction_input(IMX_GPIO_NR(4, 5));
ret = gpio_get_value(IMX_GPIO_NR(4, 5));
} else {
- gpio_direction_input(IMX_GPIO_NR(1, 4));
- ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
+ gpio_direction_input(IMX_GPIO_NR(1, 5));
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
}
return ret;
Best regards,
Stefano Babic
--
=
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
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Re: [U-Boot] [PATCH v2 15/33] x86: Refactor PCI to permit alternate init
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.
Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/coreboot/pci.c | 22 --
arch/x86/cpu/pci.c | 26 ++
arch/x86/include/asm/pci.h | 11 +++
4 files changed, 46 insertions(+), 14 deletions(-)
create mode 100644 arch/x86/cpu/pci.c
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 9d38ef7..97f36d5 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -11,3 +11,4 @@
extra-y= start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
obj-y += interrupts.o cpu.o call64.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 33f16a3..130fd88 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -13,8 +13,6 @@
#include pci.h
#include asm/pci.h
-static struct pci_controller coreboot_hose;
-
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
{
@@ -31,19 +29,15 @@ static struct pci_config_table
pci_coreboot_config_table[] = {
{}
};
-void pci_init_board(void)
+void board_pci_setup_hose(struct pci_controller *hose)
{
- coreboot_hose.config_table = pci_coreboot_config_table;
- coreboot_hose.first_busno = 0;
- coreboot_hose.last_busno = 0;
-
- pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0x,
- PCI_REGION_MEM);
- coreboot_hose.region_count = 1;
-
- pci_setup_type1(coreboot_hose);
+ hose-config_table = pci_coreboot_config_table;
+ hose-first_busno = 0;
+ hose-last_busno = 0;
- pci_register_hose(coreboot_hose);
+ pci_set_region(hose-regions + 0, 0x0, 0x0, 0x,
+ PCI_REGION_MEM);
+ hose-region_count = 1;
- pci_hose_scan(coreboot_hose);
+ pci_setup_type1(hose);
Should pci_setup_type1(hose) be moved to arch/x86/cpu/pci.c?
}
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
new file mode 100644
index 000..030cbbc
--- /dev/null
+++ b/arch/x86/cpu/pci.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008,2009
+ * Graeme Russ, graeme.r...@gmail.com
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, dan...@omicron.se
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include pci.h
+#include asm/pci.h
+
+static struct pci_controller x86_hose;
+
+void pci_init_board(void)
+{
+ struct pci_controller *hose = x86_hose;
+
+ board_pci_setup_hose(hose);
+ pci_register_hose(hose);
+
+ pci_hose_scan(hose);
Should we save the return value of pci_hose_scan(hose) to
hose-last_busno? I noticed that coreboot/pci.c is doing this in the
config_device callback, but that callback causes infinite loop when I
tested that logic on the Crown Bay board.
+}
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 6b16188..c160707 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -12,5 +12,16 @@
#define DEFINE_PCI_DEVICE_TABLE(_table) \
const struct pci_device_id _table[]
+struct pci_controller;
+
void pci_setup_type1(struct pci_controller *hose);
+
+/**
+ * board_pci_setup_hose() - Set up the PCI hose
+ *
+ * This is called by the common x86 PCI code to set up the PCI controller
+ * hose. It may be called when no memory/BSS is available so should just
+ * store things in 'hose' and not in BSS variables.
+ */
+void board_pci_setup_hose(struct pci_controller *hose);
#endif
--
Regards,
Bin
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Re: [U-Boot] [PATCH v2 32/33] x86: ivybridge: Implement SDRAM init
Hi Simon, I am not sure if there is anything I missed but when I look at the u-boot-x86/working, the repo content does not match the patch v2 here. And seems you missed my previous comments @ http://u-boot.10912.n7.nabble.com/PATCH-0-39-x86-Add-support-for-running-on-bare-hardware-tp194993p195356.html [snip] Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Revert lib: bootm: add missing include
This reverts commit 1e96220a5687efae2aed45ce56e143336c40d0a7. Remove duplicated vxworks.h header. The same change was done by ARM: prevent compiler warnings from bootm.c (sha1: 8d196e52b58d1e50a80c2f5067b201cda521c75c) Signed-off-by: Michal Simek michal.si...@xilinx.com --- arch/arm/lib/bootm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index cdb197510588..4949d573af8c 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -15,7 +15,6 @@ #include common.h #include command.h #include image.h -#include vxworks.h #include u-boot/zlib.h #include asm/byteorder.h #include libfdt.h -- 1.8.2.3 pgpre6fYBwczX.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 34/39] x86: ivybridge: Add early init for PCH devices
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c | 142 +
arch/x86/cpu/ivybridge/early_init.c | 145
++
arch/x86/include/asm/arch-ivybridge/pch.h | 121 +-
arch/x86/include/asm/arch-ivybridge/sandybridge.h | 107
arch/x86/include/asm/global_data.h| 8 ++
arch/x86/include/asm/post.h | 2 +
7 files changed, 525 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/cpu/ivybridge/early_init.c
create mode 100644 arch/x86/include/asm/arch-ivybridge/sandybridge.h
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index a3ea566..4bfb03a 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -6,6 +6,7 @@
obj-y += car.o
obj-y += cpu.o
+obj-y += early_init.o
obj-y += lpc.o
obj-y += microcode_intel.o
obj-y += sdram.o
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index bd2660f..a435520 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -4,6 +4,7 @@
* Graeme Russ, graeme.r...@gmail.com.
*
* Some portions from coreboot src/mainboard/google/link/romstage.c
+ * and src/cpu/intel/model_206ax/bootblock.c
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 Google Inc.
*
@@ -16,11 +17,13 @@
#include asm/io.h
#include asm/msr.h
#include asm/mtrr.h
+#include asm/pci.h
#include asm/post.h
#include asm/processor.h
#include asm/arch/model_206ax.h
#include asm/arch/microcode.h
#include asm/arch/pch.h
+#include asm/arch/sandybridge.h
DECLARE_GLOBAL_DATA_PTR;
@@ -178,6 +181,83 @@ int arch_cpu_init(void)
return 0;
}
+static int enable_smbus(void)
+{
+ pci_dev_t dev;
+ uint16_t value;
+
+ /* Set the SMBus device statically. */
+ dev = PCI_BDF(0x0, 0x1f, 0x3);
+
+ /* Check to make sure we've got the right device. */
+ value = pci_read_config16(dev, 0x0);
+ if (value != 0x8086) {
+ printf(SMBus controller not found\n);
+ return -ENOSYS;
+ }
+
+ /* Set SMBus I/O base. */
+ pci_write_config32(dev, SMB_BASE,
+ SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+ /* Set SMBus enable. */
+ pci_write_config8(dev, HOSTC, HST_EN);
+
+ /* Set SMBus I/O space enable. */
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+ /* Disable interrupt generation. */
+ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+ /* Clear any lingering errors, so transactions can run. */
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+ debug(SMBus controller enabled\n);
+
+ return 0;
+}
+
+#define PCH_EHCI0_TEMP_BAR0 0xe800
+#define PCH_EHCI1_TEMP_BAR0 0xe8000400
+#define PCH_XHCI_TEMP_BAR0 0xe8001000
+
+/*
+ * Setup USB controller MMIO BAR to prevent the reference code from
+ * resetting the controller.
+ *
+ * The BAR will be re-assigned during device enumeration so these are only
+ * temporary.
+ *
+ * This is used to speed up the resume path.
+ */
+static void enable_usb_bar(void)
+{
+ pci_dev_t usb0 = PCH_EHCI1_DEV;
+ pci_dev_t usb1 = PCH_EHCI2_DEV;
+ pci_dev_t usb3 = PCH_XHCI_DEV;
+ u32 cmd;
+
+ /* USB Controller 1 */
+ pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
+ PCH_EHCI0_TEMP_BAR0);
+ cmd = pci_read_config32(usb0, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb0, PCI_COMMAND, cmd);
+
+ /* USB Controller 1 */
+ pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
+ PCH_EHCI1_TEMP_BAR0);
+ cmd = pci_read_config32(usb1, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb1, PCI_COMMAND, cmd);
+
+ /* USB3 Controller */
+ pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
+ PCH_XHCI_TEMP_BAR0);
+ cmd = pci_read_config32(usb3, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb3, PCI_COMMAND, cmd);
+}
+
static int report_bist_failure(void)
{
if (gd-arch.bist != 0) {
@@ -190,8 +270,11 @@ static int report_bist_failure(void)
int print_cpuinfo(void)
{
+ enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
char processor_name[CPU_MAX_NAME_LEN];
const char *name;
+ uint32_t pm1_cnt;
+ uint16_t pm1_sts;
int ret;
Re: [U-Boot] [PATCH] arm: imx: make bmode command work with SPL/U-Boot combo
Gentle ping.
On 10/29/2014 07:28 PM, Nikita Kiryanov wrote:
The bmode command forces the SoC to use a specific boot device
by writing its boot mode into SRC_GPR9, and notifying the SoC of
the change using SRC_GPR10[28] bit: if the bit is on, bootROM
uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine
the boot device.
SPL on the other hand is oblivious to this distinction, so once
the bootROM loads SPL from the device configured in SRC_GPR10,
SPL will attempt to load U-Boot from the device configured in
SRC_SMBR1, which is not updated by the bootROM to the value in
SRC_GPR9.
The result is that the selected boot device is not used across all
the boot stages.
Update spl_boot_device() to look at gpr9 when necessary.
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Troy Kisky troy.ki...@boundarydevices.com
Cc: Tim Harvey thar...@gateworks.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Heiko Schocher h...@denx.de
---
arch/arm/cpu/armv7/mx6/soc.c | 4 ++--
arch/arm/imx-common/spl.c| 5 +++--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index dd5aaa2..07ae79e 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -333,8 +333,8 @@ void boot_mode_apply(unsigned cfg_val)
/*
* cfg_val will be used for
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
- * to SBMR1, which will determine the boot device.
+ * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
+ * instead of SBMR1 to determine the boot device.
*/
const struct boot_mode soc_boot_modes[] = {
{normal,MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index 9d3c31a..477c38c 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -14,11 +14,12 @@
#include spl.h
#if defined(CONFIG_MX6)
-/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
u32 spl_boot_device(void)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(psrc-sbmr1);
+ unsigned int gpr10_boot = readl(psrc-gpr10) (1 28);
+ unsigned reg = gpr10_boot ? readl(psrc-gpr9) : readl(psrc-sbmr1);
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg 0x00FF) 4) {
--
Regards,
Nikita Kiryanov
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Re: [U-Boot] [PATCH] serial: UniPhier: borrow macros from linux/serial_reg.h
2014-10-30 12:11 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: The same bit-field macros are defined in include/linux/serial_reg.h so let's include it and delete duplicated defines. Also, remove unnecessary inclusion of common.h. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: UniPhier: reset on-board devices on start-up
2014-11-05 14:25 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: If a support card is attached to the main board, the on-board SMSC9118 LAN controller is available. It must be kept in reset state for a while on start-up. When the board is kicked via a debbuger rather than pushing the hardware reset button, on-board chips are not reset; in this case the reset signals should be asserted by software. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: UniPhier: move DDR related configuration to Kconfig
2014-11-06 20:16 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: UniPhier: add EHCI host pin settings for PH1-Pro4
2014-11-07 18:33 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: These IO pins are necessary for port power control and over current detect. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] EHCI support for Panasonic UniPhier SoCs
2014-11-07 18:48 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: This series includes both USB parts and Panasonic SoC-specific parts to resolve the patch dependency. Marek, please review at least 3/4 and issue your Ack if it is OK. After it is Ack'ed, I will apply this series to my repo. Masahiro Yamada (4): usb: add basic USB configs in Kconfig ARM: UniPhier: add MIO register file usb: UniPhier: add UniPhier on-chip EHCI host driver support ARM: UniPhier: enable USB features Series, applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: UniPhier: add set_pinsel macro for use in assembly code
2014-11-07 21:08 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: The function sg_set_pinsel is useful for switching I/O pins but it can be only used in C code. This commit adds a simple macro that is available in asm code. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: UniPhier: decrease pre-reloc malloc area size
2014-11-11 21:50 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: In the current implementation of the boot sequence of UniPhier platform, 32KB temporary RAM is available before relocation. The malloc area and the stack shares the 32KB area. With CONFIG_SYS_MALLOC_F_LEN set to 0x7000 (28KB), only 0x1000 (4KB) is left for the stack. In some use cases, the system hangs up with stack over-flow. Even with driver-model UART enabled, the malloc area of 0x2000 (8KB) should be enough. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] ARM: UniPhier: some cleanups and bug fix
2014-11-11 22:18 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: Masahiro Yamada (2): ARM: UniPhier: consolidate board_postclk_init() function ARM: UniPhier: call pin_init() also in the normal boot Series, applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 0/12] RFC: dm: Add I2C support
Hi Heiko, On 10 November 2014 00:16, Heiko Schocher h...@denx.de wrote: Hello Simon, sorry for the long delay... Am 13.10.2014 07:39, schrieb Simon Glass: (Note this is RFC since the uclass interface needs discussion and also because only sandbox is implemented so far. But I thought it best to get this out there as soon as I wrote it as it may influence the PMIC library, etc.) This series is an initial attempt to add I2C support to driver model. It has become apparent that this is a high priority as it is widely used. It follows along to some extent from the SPI conversion. Several changes are made from the original I2C implementations. Firstly It is not necessary to specify the chip address with every call, since each chip knows its own address - it is stored in struct dm_i2c_chip which is attached to each chip on the I2C bus. However, this information *is* passed to the driver since I presume most drivers need it and it would be cumbersome to look up in every call. Secondly there is no concept of a 'current' I2C bus so all associated logic is removed. With driver model i2c_set_bus_num() and i2c_get_bus_num() are not available. Since the chip device specifies both the bus and the chip address, there is no need for this concept. It also causes problems when one driver changes the current bus and forgets to change it back. Thirdly initialisation is handled by driver model's normal probe() method on each device so there should be no need for i2c_init_all(), i2c_init(), i2c_init_board(), i2c_board_late_init() and board_i2c_init(). Great! I2C muxes are not yet supported. To support these we will need to maintain state of the current mux settings to avoid resetting every mux every time. Probably we need to add a sandbox I2C mux driver to permit testing of this. This can probably be done later. Currently only the keymile boards really use i2c muxes, so I am fine with doing this in a second step. Platform data is not yet supported either, only device tree. The U_BOOT_I2C_MKENT_COMPLETE() and U_BOOT_I2C_ADAP_COMPLETE() macros are not used. Also struct i2c_adapter is not defined anymore. This will need to be addressed, perhaps as part of converting over a board that does not use device tree. Ok for this in the first step... The question raised if we only would support Device tree with DM ... so maybe we do not need to do this step. I am not really sure, if we should really support Device Tree only with DM, because: - do all archs switch to Device Tree in the near future? - in SPL we have really on some SoCs small memory (like I just work on some AT91 boards which have 4k only!) To get DM with Device Tree into 4k is a big challenge ... so in my opinion, it would be good to have the possibility of Platform data ... so we prevent to make dirty hacks for the SPL case (I hope) ... This series is available at u-boot-dm/i2c-working. Thanks for your great work. I looked through your patchset and have no real objection against it ... To the i2c deblocking subject ... we should add at least the deblock() in struct dm_i2c_ops and call it do_i2c_reset if defined ... beside of this, you can add my Acked-by: Heiko Schocher h...@denx.de to the hole series. Thanks for reviewing this. I have added the deblock() method and also the generic I2C support (allows you to use a device on the command line without it having a proper driver). There are a few changes so if you have time to take another look I will definitely add your Acked-by. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-uniphier/master
Hi Tom,
The following changes since commit 9906090f527153afddc5aa64d37cb5f89c6ee129:
Prepare v2015.01-rc1 (2014-11-10 16:25:29 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-uniphier.git master
for you to fetch changes up to b67932e3e72b6214cde75c7e2f796d0c70ff3ffb:
ARM: UniPhier: call pin_init() also in the normal boot (2014-11-12
00:31:01 +0900)
Masahiro Yamada (12):
serial: UniPhier: borrow macros from linux/serial_reg.h
ARM: UniPhier: reset on-board devices on start-up
ARM: UniPhier: move DDR related configuration to Kconfig
ARM: UniPhier: add EHCI host pin settings for PH1-Pro4
usb: add basic USB configs in Kconfig
ARM: UniPhier: add MIO register file
usb: UniPhier: add UniPhier on-chip EHCI host driver support
ARM: UniPhier: enable USB features
ARM: UniPhier: add set_pinsel macro for use in assembly code
ARM: UniPhier: decrease pre-reloc malloc area size
ARM: UniPhier: consolidate board_postclk_init() function
ARM: UniPhier: call pin_init() also in the normal boot
arch/arm/cpu/armv7/uniphier/Kconfig| 27
+++
arch/arm/cpu/armv7/uniphier/Makefile | 1 +
arch/arm/cpu/armv7/uniphier/{ph1-ld4 = }/board_postclk_init.c | 11 +--
arch/arm/cpu/armv7/uniphier/dram_init.c| 2 +-
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 8 ++---
arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c | 13
arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c | 4 ---
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 7 ++--
arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c | 39
--
arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c | 7
arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c | 10 ++
arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c| 4 ---
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 8 ++---
arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c | 1 -
arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c | 13
arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c| 4 ---
arch/arm/cpu/armv7/uniphier/reset.c| 3 --
arch/arm/include/asm/arch-uniphier/ehci-uniphier.h | 33
+++
arch/arm/include/asm/arch-uniphier/mio-regs.h | 20
arch/arm/include/asm/arch-uniphier/platdevice.h| 2 ++
arch/arm/include/asm/arch-uniphier/sg-regs.h | 13 +++-
configs/ph1_ld4_defconfig | 3 ++
configs/ph1_pro4_defconfig | 3 ++
configs/ph1_sld8_defconfig | 3 ++
drivers/serial/serial_uniphier.c | 15 ++---
drivers/usb/Kconfig| 46
++
drivers/usb/host/Kconfig | 56
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-uniphier.c | 39
++
include/configs/ph1_ld4.h | 2 --
include/configs/ph1_pro4.h | 2 --
include/configs/ph1_sld8.h | 2 --
include/configs/uniphier-common.h | 13 ++--
33 files changed, 321 insertions(+), 94 deletions(-)
rename arch/arm/cpu/armv7/uniphier/{ph1-ld4 = }/board_postclk_init.c (82%)
delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c
delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c
create mode 100644 arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
create mode 100644 arch/arm/include/asm/arch-uniphier/mio-regs.h
create mode 100644 drivers/usb/host/Kconfig
create mode 100644 drivers/usb/host/ehci-uniphier.c
--
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH] spl: Change debug to printf for Unsupported boot-device
We had the problem on an AM33xx platform, that SPL detected an unsupported boot-device. But since this message is a debug message it took a bit of time to really know, where the hangup in SPL resulted from. So let's change this debug message to a printf and also print the detected boot-device that is not supported. This makes debugging of such cases much easier. Signed-off-by: Stefan Roese s...@denx.de Cc: Tom Rini tr...@ti.com --- common/spl/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index d85bab3..1e5ee95 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -216,7 +216,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) break; #endif default: - debug(SPL: Un-supported Boot Device\n); + printf(SPL: Unsupported Boot Device %d\n, boot_device); hang(); } -- 2.1.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/4] x86: Do TSC MSR calibration only for known/supported CPUs
Hi Bin,
On 11 November 2014 01:25, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 2:54 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 9 November 2014 07:19, Bin Meng bmeng...@gmail.com wrote:
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
processors which do not have this MSR. Instead only doing the MSR
calibration for known/supported CPUs.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
arch/x86/lib/tsc_timer.c | 116
---
1 file changed, 109 insertions(+), 7 deletions(-)
Applied to u-boot-x86/master, thanks!
(Please see note below)
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index 8b38702..fafbbfc 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -1,6 +1,9 @@
/*
* Copyright (c) 2012 The Chromium OS Authors.
*
+ * TSC calibration codes are adapted from Linux kernel
+ * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
+ *
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -12,8 +15,108 @@
#include asm/msr.h
#include asm/u-boot-x86.h
+/* CPU reference clock frequency: in KHz */
+#define FREQ_8383200
+#define FREQ_100 99840
+#define FREQ_133 133200
+#define FREQ_166 166400
+
+#define MAX_NUM_FREQS 8
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * According to Intel 64 and IA-32 System Programming Guide,
+ * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
+ * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
+ * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
+ * so we need manually differentiate SoC families. This is what the
+ * field msr_plat does.
+ */
+struct freq_desc {
+ u8 x86_family; /* CPU family */
+ u8 x86_model; /* model */
+ u8 msr_plat;/* 1: use MSR_PLATFORM_INFO, 0:
MSR_IA32_PERF_STATUS */
+ u32 freqs[MAX_NUM_FREQS];
+};
+
+static struct freq_desc freq_desc_tables[] = {
+ /* PNW */
+ { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* CLV+ */
+ { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* TNG */
+ { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
+ /* VLV2 */
+ { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 }
},
+ /* ANN */
+ { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 }
},
+};
+
+static int match_cpu(u8 family, u8 model)
+{
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(freq_desc_tables); i++) {
+ if ((family == freq_desc_tables[i].x86_family)
+ (model == freq_desc_tables[i].x86_model))
+ return i;
+ }
+
+ return -1;
+}
+
+/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
+#define id_to_freq(cpu_index, freq_id) \
+ (freq_desc_tables[cpu_index].freqs[freq_id])
+
+/*
+ * Do MSR calibration only for known/supported CPUs.
+ *
+ * Returns the calibration value or 0 if MSR calibration failed.
+ */
+static unsigned long try_msr_calibrate_tsc(void)
+{
+ u32 lo, hi, ratio, freq_id, freq;
+ unsigned long res;
+ int cpu_index;
+
+ cpu_index = match_cpu(gd-arch.x86, gd-arch.x86_model);
+ if (cpu_index 0)
+ return 0;
+
+ if (freq_desc_tables[cpu_index].msr_plat) {
+ rdmsr(MSR_PLATFORM_INFO, lo, hi);
+ ratio = (lo 8) 0x1f;
+ } else {
+ rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ ratio = (hi 8) 0x1f;
+ }
+ debug(Maximum core-clock to bus-clock ratio: 0x%x\n, ratio);
+
+ if (!ratio)
+ goto fail;
+
+ /* Get FSB FREQ ID */
+ rdmsr(MSR_FSB_FREQ, lo, hi);
+ freq_id = lo 0x7;
+ freq = id_to_freq(cpu_index, freq_id);
+ debug(Resolved frequency ID: %u, frequency: %u KHz\n,
+ freq_id, freq);
+ if (!freq)
+ goto fail;
+
+ /* TSC frequency = maximum resolved freq * maximum resolved bus
ratio */
+ res = freq * ratio / 1000;
+ debug(TSC runs at %lu MHz\n, res);
+
+ return res;
+
+fail:
+ debug(Fast TSC calibration using MSR failed\n);
+ return 0;
+}
+
void timer_set_base(u64 base)
{
gd-arch.tsc_base = base;
@@ -34,17 +137,16 @@ u64 __attribute__((no_instrument_function))
get_ticks(void)
return now_tick - gd-arch.tsc_base;
}
-#define PLATFORM_INFO_MSR 0xce
-
/* Get the speed of the TSC timer in MHz */
unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
+ unsigned long fast_calibrate;
+
+
Re: [U-Boot] [PATCH v2 10/33] x86: Tidy up timer code for Intel core architecture
Hi Bin,
On 11 November 2014 03:05, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
We can use an MSR to obtain the time base. Add this back in and consolidate
the code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to tidy up timer code for Intel core architecture
arch/x86/cpu/interrupts.c | 28
arch/x86/lib/tsc_timer.c | 16 +++-
2 files changed, 15 insertions(+), 29 deletions(-)
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 51e2c59..4822c11 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -603,31 +603,3 @@ asm(.globl irq_common_entry\n \
DECLARE_INTERRUPT(253) \
DECLARE_INTERRUPT(254) \
DECLARE_INTERRUPT(255));
-
-#if defined(CONFIG_INTEL_CORE_ARCH)
-/*
- * Get the number of CPU time counter ticks since it was read first time
after
- * restart. This yields a free running counter guaranteed to take almost 6
- * years to wrap around even at 100GHz clock rate.
- */
-u64 get_ticks(void)
-{
- u64 now_tick = rdtsc();
-
- if (!gd-arch.tsc_base)
- gd-arch.tsc_base = now_tick;
-
- return now_tick - gd-arch.tsc_base;
-}
-
-#define PLATFORM_INFO_MSR 0xce
-
-unsigned long get_tbclk(void)
-{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
-
- ratio = (platform_info 8) 0xff;
- return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo
ratio */
-}
-#endif
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index f091c91..3936b36 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -180,6 +180,20 @@ static inline int pit_expect_msb(unsigned char val, u64
*tscp,
return count 5;
}
+#define PLATFORM_INFO_MSR 0xce
+
+/* Get the speed of the TSC timer in MHz */
+unsigned __attribute__((no_instrument_function))
+ long get_tbclk_mhz_from_msr(void)
+{
+ u32 ratio;
+ u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
+
+ /* 100MHz times Max Non Turbo ratio */
+ ratio = (platform_info 8) 0xff;
+ return 100 * ratio;
+}
+
/*
* How many MSB values do we want to see? We aim for
* a maximum error rate of 500ppm (in practice the
@@ -302,7 +316,7 @@ unsigned __attribute__((no_instrument_function)) long
get_tbclk_mhz(void)
fast_calibrate = quick_pit_calibrate();
if (!fast_calibrate)
- panic(TSC frequency is ZERO);
+ fast_calibrate = get_tbclk_mhz_from_msr();
gd-arch.tsc_mhz = fast_calibrate;
return fast_calibrate;
--
Adding MSR calibration back for Intel CORE this way is inconsistent
with the code logic. Can you please try adding the family number and
model number in the freq_desc_tables[]?
Yes, but I was hoping for something automatic rather than a list of
exceptions. What is the guaranteed way to do this calibration?
Regards,
Simon
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Re: [U-Boot] [PATCH 19/39] x86: Build a .rom file which can be flashed to an x86 machine
Hi Bin, On 11 November 2014 01:37, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Nov 11, 2014 at 8:28 AM, Simon Glass s...@chromium.org wrote: Hi Bin, [snip] + $(srctree)/board/$(BOARDDIR)/descriptor.bin I don't see where the descriptor.bin is created? This needs to be downloaded and provided, as with mrc.bin, etc. I thought the descriptor.bin is used to describe the u-boot.rom layout, but seems you are saying it is coming from Intel(?). Is the format defined by Intel so that all the BIOS for that platform (u-boot.rom in our case) has to obey? Yes, but only if there is a management engine (the CONFIG option you asked for). I think I will adjust it (later) so that it builds an empty u-boot.rom and prints a warning on stdout if the binaries are not available. That way the buildman build will still succeed, but the user will see the problem. It might also be useful to have U-Boot report missing binaries when it starts up. Sounds good. Regards, Bin Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 34/39] x86: ivybridge: Add early init for PCH devices
Hi Bin,
On 11 November 2014 07:52, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c | 142
+
arch/x86/cpu/ivybridge/early_init.c | 145
++
arch/x86/include/asm/arch-ivybridge/pch.h | 121 +-
arch/x86/include/asm/arch-ivybridge/sandybridge.h | 107
arch/x86/include/asm/global_data.h| 8 ++
arch/x86/include/asm/post.h | 2 +
7 files changed, 525 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/cpu/ivybridge/early_init.c
create mode 100644 arch/x86/include/asm/arch-ivybridge/sandybridge.h
diff --git a/arch/x86/cpu/ivybridge/Makefile
b/arch/x86/cpu/ivybridge/Makefile
index a3ea566..4bfb03a 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -6,6 +6,7 @@
obj-y += car.o
obj-y += cpu.o
+obj-y += early_init.o
obj-y += lpc.o
obj-y += microcode_intel.o
obj-y += sdram.o
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index bd2660f..a435520 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -4,6 +4,7 @@
* Graeme Russ, graeme.r...@gmail.com.
*
* Some portions from coreboot src/mainboard/google/link/romstage.c
+ * and src/cpu/intel/model_206ax/bootblock.c
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 Google Inc.
*
@@ -16,11 +17,13 @@
#include asm/io.h
#include asm/msr.h
#include asm/mtrr.h
+#include asm/pci.h
#include asm/post.h
#include asm/processor.h
#include asm/arch/model_206ax.h
#include asm/arch/microcode.h
#include asm/arch/pch.h
+#include asm/arch/sandybridge.h
DECLARE_GLOBAL_DATA_PTR;
@@ -178,6 +181,83 @@ int arch_cpu_init(void)
return 0;
}
+static int enable_smbus(void)
+{
+ pci_dev_t dev;
+ uint16_t value;
+
+ /* Set the SMBus device statically. */
+ dev = PCI_BDF(0x0, 0x1f, 0x3);
+
+ /* Check to make sure we've got the right device. */
+ value = pci_read_config16(dev, 0x0);
+ if (value != 0x8086) {
+ printf(SMBus controller not found\n);
+ return -ENOSYS;
+ }
+
+ /* Set SMBus I/O base. */
+ pci_write_config32(dev, SMB_BASE,
+ SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+ /* Set SMBus enable. */
+ pci_write_config8(dev, HOSTC, HST_EN);
+
+ /* Set SMBus I/O space enable. */
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+ /* Disable interrupt generation. */
+ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+ /* Clear any lingering errors, so transactions can run. */
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+ debug(SMBus controller enabled\n);
+
+ return 0;
+}
+
+#define PCH_EHCI0_TEMP_BAR0 0xe800
+#define PCH_EHCI1_TEMP_BAR0 0xe8000400
+#define PCH_XHCI_TEMP_BAR0 0xe8001000
+
+/*
+ * Setup USB controller MMIO BAR to prevent the reference code from
+ * resetting the controller.
+ *
+ * The BAR will be re-assigned during device enumeration so these are only
+ * temporary.
+ *
+ * This is used to speed up the resume path.
+ */
+static void enable_usb_bar(void)
+{
+ pci_dev_t usb0 = PCH_EHCI1_DEV;
+ pci_dev_t usb1 = PCH_EHCI2_DEV;
+ pci_dev_t usb3 = PCH_XHCI_DEV;
+ u32 cmd;
+
+ /* USB Controller 1 */
+ pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
+ PCH_EHCI0_TEMP_BAR0);
+ cmd = pci_read_config32(usb0, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb0, PCI_COMMAND, cmd);
+
+ /* USB Controller 1 */
+ pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
+ PCH_EHCI1_TEMP_BAR0);
+ cmd = pci_read_config32(usb1, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb1, PCI_COMMAND, cmd);
+
+ /* USB3 Controller */
+ pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
+ PCH_XHCI_TEMP_BAR0);
+ cmd = pci_read_config32(usb3, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb3, PCI_COMMAND, cmd);
+}
+
static int report_bist_failure(void)
{
if (gd-arch.bist != 0) {
@@ -190,8 +270,11 @@ static int report_bist_failure(void)
int print_cpuinfo(void)
{
+ enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
char processor_name[CPU_MAX_NAME_LEN];
const char
Re: [U-Boot] [PATCH] spl: Change debug to printf for Unsupported boot-device
On Tue, Nov 11, 2014 at 04:59:13PM +0100, Stefan Roese wrote: We had the problem on an AM33xx platform, that SPL detected an unsupported boot-device. But since this message is a debug message it took a bit of time to really know, where the hangup in SPL resulted from. So let's change this debug message to a printf and also print the detected boot-device that is not supported. This makes debugging of such cases much easier. Signed-off-by: Stefan Roese s...@denx.de Cc: Tom Rini tr...@ti.com Did you build all of ARM with this? I _think_ this may break the davinci/related boards that use SPL since they don't have printf due to size. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 32/33] x86: ivybridge: Implement SDRAM init
Hi Bin, On 11 November 2014 07:37, Bin Meng bmeng...@gmail.com wrote: Hi Simon, I am not sure if there is anything I missed but when I look at the u-boot-x86/working, the repo content does not match the patch v2 here. And seems you missed my previous comments @ http://u-boot.10912.n7.nabble.com/PATCH-0-39-x86-Add-support-for-running-on-bare-hardware-tp194993p195356.html OK, which ones have I missed? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spl: Change debug to printf for Unsupported boot-device
On 11.11.2014 17:16, Tom Rini wrote: On Tue, Nov 11, 2014 at 04:59:13PM +0100, Stefan Roese wrote: We had the problem on an AM33xx platform, that SPL detected an unsupported boot-device. But since this message is a debug message it took a bit of time to really know, where the hangup in SPL resulted from. So let's change this debug message to a printf and also print the detected boot-device that is not supported. This makes debugging of such cases much easier. Signed-off-by: Stefan Roese s...@denx.de Cc: Tom Rini tr...@ti.com Did you build all of ARM with this? I _think_ this may break the davinci/related boards that use SPL since they don't have printf due to size. Yes, might be the case. I'm running the build for all ARM board right now. Will let you know if this breaks anything. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 0/2] Fix SoC-specific exception handling
Short version: * this patch fixes exception handling on i.MX27 which was broken, probably from day one. * i.MX27-based board Maintainers please test this patch: make sure your board boots with it and make sure e.g. a write to address 0 causes U-Boot to signal a data abort. * i.MX custodian please review this patch and let me know if this should also be done for other i.MX SoCs as well. Long version: This patch was created after apf27 maintainer found out that the board did not boot any more. The root cause was that commit 3ff46cc4 would try and write into the exception vectors table, which i.MX27 has in ROM. This caused a data abort, and as the U-Boot vectors were not in place yet, this abort went to the ROM code which silently hung. Investigation led to a patch sent in 2009 to the list (but never applied) with a description of the i.MX27 exception handling: http://lists.denx.de/pipermail/u-boot/2009-October/062811.html By his own author's admission, this patch was not fit for inclusion in U-Boot, but it gave the technical information needed to produce this present patch set. The first patch is only cosmetic, fixing whitespace quirks which affect legibility or cause a warning in patman. The second patch moves vectors relocation out of the relocate_code routine and into its own relocate_vectors routine. This routine is made weak so that it can be replaced by a SoC-specific, strong one. Such a strong replacement is provided for i.MX27. Albert ARIBAUD (2): cosmetic: arm: fix whitespace in arch/arm/lib/relocate.S imx: fix exception vectors relocation in imx27 arch/arm/cpu/arm926ejs/mx27/Makefile | 4 ++ arch/arm/cpu/arm926ejs/mx27/relocate.S | 49 +++ arch/arm/lib/crt0.S| 5 +++ arch/arm/lib/relocate.S| 73 -- 4 files changed, 101 insertions(+), 30 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/mx27/relocate.S -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 1/2] cosmetic: arm: fix whitespace in arch/arm/lib/relocate.S
Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net
---
arch/arm/lib/relocate.S | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index b4a258c..6ede41c 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -74,8 +74,8 @@ fixnext:
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
andsr2, r2, #(1 13)
- ldreq r1, =0x /* If V=0 */
- ldrne r1, =0x /* If V=1 */
+ ldreq r1, =0x /* If V=0 */
+ ldrne r1, =0x /* If V=1 */
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
ldmia r0!, {r2-r8,r10}
@@ -96,9 +96,9 @@ relocate_done:
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__
- movpc, lr
+ mov pc, lr
#else
- bxlr
+ bx lr
#endif
ENDPROC(relocate_code)
--
2.1.0
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[U-Boot] [PATCH v1 2/2] imx: fix exception vectors relocation in i.MX27
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x) or
high (0x) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is ARM926E-JS, thus has only normal and
high options, but does not provide RAM at 0x
and has only ROM at 0x; it is therefore not
possible to move or change its exception vectors.
Besides, i.MX27 ROM code does provide an indirect
vectors table but at a non-standard address and with
the reset and reserved vectors missing.
Turn the current vector relocation code into a weak
routine called after relocate_code from crt0, and add
strong version for i.MX27.
Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net
---
arch/arm/cpu/arm926ejs/mx27/Makefile | 4 ++
arch/arm/cpu/arm926ejs/mx27/relocate.S | 49
arch/arm/lib/crt0.S| 5 +++
arch/arm/lib/relocate.S| 69 --
4 files changed, 99 insertions(+), 28 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/mx27/relocate.S
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile
b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 4976bbb..0edf144 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -5,3 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y = generic.o reset.o timer.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += relocate.o
+endif
diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S
b/arch/arm/cpu/arm926ejs/mx27/relocate.S
new file mode 100644
index 000..97003b3
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S
@@ -0,0 +1,49 @@
+/*
+ * relocate - i.MX27-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUD albert.u.b...@aribaud.net
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm-offsets.h
+#include config.h
+#include linux/linkage.h
+
+/*
+ * The i.MX27 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0x),
+ * thus only the low address (0x) is useable; but that is
+ * in ROM. Therefore, vectors cannot be changed at all.
+ *
+ * However, these ROM-based vectors actually just perform indirect
+ * calls through pointers located in RAM at SoC-specific addresses,
+ * as follows:
+ *
+ * Offset Exception Use by ROM code
+ * 0x reset indirect branch to [0x0014]
+ * 0x0004 undefined instruction indirect branch to [0xfef0]
+ * 0x0008 software interrupt indirect branch to [0xfef4]
+ * 0x000c prefetch abort indirect branch to [0xfef8]
+ * 0x0010 data abort indirect branch to [0xfefc]
+ * 0x0014 (reserved in ARMv5)vector to ROM reset: 0xc000
+ * 0x0018 IRQindirect branch to [0xff00]
+ * 0x001c FIQindirect branch to [0xff04]
+ *
+ * In order to initialize exceptions on i.MX27, we must copy U-Boot's
+ * indirect (not exception!) vector table into 0xfef0..0xff04
+ * taking care not to copy vectors 0x00 (reset) and 0x14 (reserved).
+ */
+
+ .section.text.relocate_vectors,ax,%progbits
+
+ENTRY(relocate_vectors)
+
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+ ldr r1, =0xFEF0
+ ldmia r0!, {r2-r8,r10} /* load all eight vectors */
+ stmia r1!, {r3-r6,r8,r10} /* only write supported vectors */
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 29cdad0..a33ad3e 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -104,6 +104,11 @@ clr_gd:
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
b relocate_code
here:
+/*
+ * now relocate vectors
+ */
+
+ bl relocate_vectors
/* Set up final (full) environment */
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 6ede41c..92f5314 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -11,6 +11,47 @@
#include linux/linkage.h
/*
+ * Default/weak exception vectors relocation routine
+ *
+ * This routine covers the standard ARM cases: normal (0x),
+ * high (0x) and VBAR. SoCs which do not comply with any of
+ * the standard cases must provide their own, strong, version.
+ */
+
+ .section.text.relocate_vectors,ax,%progbits
+ .weak relocate_vectors
+
+ENTRY(relocate_vectors)
+
+#ifdef CONFIG_HAS_VBAR
+ /*
+* If the ARM processor has the security extensions,
+* use VBAR to relocate the exception vectors.
+*/
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
+#else
+ /*
+* Copy the relocated exception vectors to the
+* correct address
+* CP15 c1 V bit
Re: [U-Boot] [PATCH v2] fs: make it possible to read the filesystem UUID
On 11/11/2014 05:55 AM, Christian Gmeiner wrote:
Some filesystems have a UUID stored in its superblock. To
allow using root=UUID=... for the kernel command line we
need a way to read-out the filesystem UUID.
Just one more nit below, otherwise,
Acked-by: Stephen Warren swar...@nvidia.com
(feel free to add that the patch description for any repost)
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
+int ext4fs_uuid(char *uuid_str)
+{
+ if (ext4fs_root == NULL)
+ return -1;
+
+#ifdef CONFIG_LIB_UUID
+ uuid_bin_to_str((unsigned char *)ext4fs_root-sblock.unique_id,
+ uuid_str, UUID_STR_FORMAT_STD);
+
+ return 0;
+#endif
+
+ return -ENOSYS;
+}
If CONFIG_LIB_UUID is defined, doesn't that generate an unreachable code
warning for the second return statement? I think you want a #if ...
#else ... #endif to avoid that.
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Re: [U-Boot] [PATCH v3 7/8] imx6: SPL support for iMX6 SabreSD
On Tue, Nov 11, 2014 at 12:44 AM, Stefano Babic sba...@denx.de wrote:
Hi John,
On 10/11/2014 01:23, John Tobias wrote:
Hi Stefano,
On Sun, Nov 9, 2014 at 1:16 PM, Stefano Babic sba...@denx.de wrote:
Hi John,
On 08/11/2014 22:27, John Tobias wrote:
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
---
board/freescale/mx6sabresd/mx6sabresd.c | 211
+++-
1 file changed, 209 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 3d81fff..f443337 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -55,8 +55,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
+ gd-ram_size = imx_ddr_size();
return 0;
}
@@ -607,3 +606,211 @@ int checkboard(void)
puts(Board: MX6-SabreSD\n);
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include spl.h
+#include libfdt.h
+
+#define BOOT_CFG 0x20D8004
+#define __REG(x)(*((volatile u32 *)(x)))
+
+struct fsl_esdhc_cfg spl_usdhc_cfg;
+/*
+ * Got it from mx6q_4x_mt41j128.cfg file
+ */
+void set_mt41j128_ddr(void)
+{
+ __REG(0x020e05a8) = 0x0028;
+ __REG(0x020e05b0) = 0x0028;
+ __REG(0x020e0524) = 0x0028;
+ __REG(0x020e051c) = 0x0028;
+
+ __REG(0x020e0518) = 0x0028;
+ __REG(0x020e050c) = 0x0028;
+ __REG(0x020e05b8) = 0x0028;
+ __REG(0x020e05c0) = 0x0028;
+
+ __REG(0x020e05ac) = 0x0028;
+ __REG(0x020e05b4) = 0x0028;
+ __REG(0x020e0528) = 0x0028;
+ __REG(0x020e0520) = 0x0028;
+
+ __REG(0x020e0514) = 0x0028;
+ __REG(0x020e0510) = 0x0028;
+ __REG(0x020e05bc) = 0x0028;
+ __REG(0x020e05c4) = 0x0028;
+
+ __REG(0x020e056c) = 0x0030;
+ __REG(0x020e0578) = 0x0030;
+ __REG(0x020e0588) = 0x0030;
+ __REG(0x020e0594) = 0x0030;
+
+ __REG(0x020e057c) = 0x0030;
+ __REG(0x020e0590) = 0x0030;
+ __REG(0x020e0598) = 0x0030;
+ __REG(0x020e058c) = 0x;
+
+ __REG(0x020e059c) = 0x3030;
+ __REG(0x020e05a0) = 0x3030;
+ __REG(0x020e0784) = 0x0028;
+ __REG(0x020e0788) = 0x0028;
+
+ __REG(0x020e0794) = 0x0028;
+ __REG(0x020e079c) = 0x0028;
+ __REG(0x020e07a0) = 0x0028;
+ __REG(0x020e07a4) = 0x0028;
+
+ __REG(0x020e07a8) = 0x0028;
+ __REG(0x020e0748) = 0x0028;
+ __REG(0x020e074c) = 0x0030;
+ __REG(0x020e0750) = 0x0002;
+
+ __REG(0x020e0758) = 0x;
+ __REG(0x020e0774) = 0x0002;
+ __REG(0x020e078c) = 0x0030;
+ __REG(0x020e0798) = 0x000C;
+
+ __REG(0x021b081c) = 0x;
+ __REG(0x021b0820) = 0x;
+ __REG(0x021b0824) = 0x;
+ __REG(0x021b0828) = 0x;
+
+ __REG(0x021b481c) = 0x;
+ __REG(0x021b4820) = 0x;
+ __REG(0x021b4824) = 0x;
+ __REG(0x021b4828) = 0x;
+
+ __REG(0x021b0018) = 0x1740;
+
+ __REG(0x021b001c) = 0x8000;
+ __REG(0x021b000c) = 0x8A8F7975;
+ __REG(0x021b0010) = 0xFF538E64;
+ __REG(0x021b0014) = 0x01FF00DB;
+ __REG(0x021b002c) = 0x26D2;
+
+ __REG(0x021b0030) = 0x008F0E21;
+ __REG(0x021b0008) = 0x09444040;
+ __REG(0x021b0004) = 0x00020036;
+ __REG(0x021b0040) = 0x0047;
+ __REG(0x021b) = 0x841A;
+
+ __REG(0x021b001c) = 0x04088032;
+ __REG(0x021b001c) = 0x8033;
+ __REG(0x021b001c) = 0x00428031;
+ __REG(0x021b001c) = 0x09408030;
+
+ __REG(0x021b001c) = 0x04008040;
+ __REG(0x021b0800) = 0xA1380003;
+ __REG(0x021b0020) = 0x5800;
+ __REG(0x021b0818) = 0x0007;
+ __REG(0x021b4818) = 0x0007;
+
+ /* Calibration values based on ARD and 528MHz */
+ __REG(0x021b083c) = 0x434B0358;
+ __REG(0x021b0840) = 0x033D033C;
+ __REG(0x021b483c) = 0x03520362;
+ __REG(0x021b4840) = 0x03480318;
+ __REG(0x021b0848) = 0x41383A3C;
+ __REG(0x021b4848) = 0x3F3C374A;
+ __REG(0x021b0850) = 0x4243;
+ __REG(0x021b4850) = 0x4932473A;
+
+ __REG(0x021b080c) = 0x001F001F;
+ __REG(0x021b0810) = 0x001F001F;
+
+ __REG(0x021b480c) = 0x001F001F;
+ __REG(0x021b4810) = 0x001F001F;
+
+ __REG(0x021b08b8) = 0x0800;
+ __REG(0x021b48b8) = 0x0800;
+
+ __REG(0x021b0404) = 0x00011006;
+ __REG(0x021b0004) = 0x00025576;
+
+ __REG(0x021b001c) = 0x;
+
+ __REG(0x020c4068) = 0x00C03F3F;
+ __REG(0x020c406c) = 0x0030FC00;
+ __REG(0x020c4070) = 0x0FFFC000;
+ __REG(0x020c4074) = 0x3FF0;
+ __REG(0x020c4078) = 0x00FFF300;
+ __REG(0x020c407c) = 0x0FC3;
+
[U-Boot] [PULL] u-boot-usb/master
Dangling PR, sorry it's late ... The following changes since commit 11ada9225a16ed2d8ddbf0715a2416245a777cbc: Merge branch 'rmobile' of git://www.denx.de/git/u-boot-sh (2014-11-05 13:11:18 -0500) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to 6a559bbe2f60ab64e28662f7ab52551a2eaa7163: usb_storage: blacklist Enclosure Service Devices (2014-11-08 12:03:35 +0100) Marek Vasut (5): usb: s3c-otg: Remove useless include usb: s3c-otg: Encapsulate PHY control usb: s3c-otg: Split out PHY control usb: s3c-otg: Allow custom gusbcfg arm: socfpga: Add example UDC config Masahiro Yamada (2): usb: ehci: fix Interrupt on Doorbell flag of USBCMD usb: include asm/cache.h and part.h from include/usb.h Nobuhiro Iwamatsu (1): usb: rmobile: Use ARRAY_SIZE(usb_base_address) instead of CONFIG_USB_MAX_CONTROLLER_COUNT Rene Griessl (1): usb: eth: fix Makefile Soeren Moch (1): usb_storage: blacklist Enclosure Service Devices board/altera/socfpga/socfpga_cyclone5.c | 21 common/usb_storage.c | 7 +-- drivers/usb/eth/Makefile | 4 +--- drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/s3c_udc_otg.c | 79 ++- drivers/usb/gadget/s3c_udc_otg_phy.c | 101 drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 2 +- drivers/usb/host/ehci-rmobile.c | 8 drivers/usb/host/ehci.h | 4 ++-- include/configs/exynos4-common.h | 1 + include/configs/s5p_goni.h| 1 + include/configs/s5pc210_universal.h | 1 + include/configs/smdkv310.h| 1 + include/configs/socfpga_common.h | 30 - include/usb.h | 2 ++ include/usb/s3c_udc.h | 1 + 16 files changed, 186 insertions(+), 78 deletions(-) create mode 100644 drivers/usb/gadget/s3c_udc_otg_phy.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PULL] u-boot-socfpga/master
Dangling PR, sorry it's late ... The following changes since commit 571bdf16a78e9e116a93d46f4809c4f8a3f2adb6: arm: interrupt_init: set sp in IRQ/FIQ modes (2014-10-29 09:03:28 -0400) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to a877bec3ecd7961211a59b2c130e055e0f771976: arm: socfpga: Add socfpga_spim_enable() to reset_manager.c (2014-11-07 16:09:10 +0100) Anatolij Gustschin (1): socfpga_cyclone5.h: fix kernel console argument in default environment Marek Vasut (1): arm: socfpga: Add example config entry for EPCS/EPCQ SPI Stefan Roese (4): arm: socfpga: Add I2C support to SoCFPGA arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target arm: socfpga: Add DW master SPI clock to clock_manager.c arm: socfpga: Add socfpga_spim_enable() to reset_manager.c arch/arm/cpu/armv7/socfpga/clock_manager.c| 14 ++ arch/arm/cpu/armv7/socfpga/misc.c | 6 + arch/arm/cpu/armv7/socfpga/reset_manager.c| 9 ++ arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga.dtsi | 755 arch/arm/dts/socfpga_cyclone5.dtsi| 51 ++ arch/arm/dts/socfpga_cyclone5_socrates.dts| 50 ++ arch/arm/include/asm/arch-socfpga/gpio.h | 10 ++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 3 + configs/socfpga_socrates_defconfig| 5 + include/configs/socfpga_common.h | 46 ++ include/configs/socfpga_cyclone5.h| 2 +- include/dt-bindings/reset/altr,rst-mgr.h | 90 +++ 13 files changed, 1042 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/socfpga.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates.dts create mode 100644 arch/arm/include/asm/arch-socfpga/gpio.h create mode 100644 configs/socfpga_socrates_defconfig create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] porting u-boot, few final questions
So the issues of the variables changing were due to me initializing everything in board_early_init_f(). I moved everything out of it except uart setup. If I setup the uart in board_init() instead of board_early_init_f() then the early cpu info stuff is missed. I guess there’s an opportunity for improvement there. I still have a question pertaining to the changing variables though. It has to do with pre and post relocation. Variables declared in functions pre-reloc will be different when used in functions post-reloc. For instance. If I set a variable in board_early_init_f() and then, without changing it, print it in board_late_init() then it will be different. So my question is how can I get around this? This is where I’m stuck… I’m trying to write the reset cause to SRAM in board_late_init(). The reset cause is printed early by default when defining CONFIG_DISPLAY_CPUINFO in the header file. When I access the register in board_late_init() it prints 0, which is wrong. I tried… and this(which is what arch/arm/imx-common/cpu.c uses to print reset cause)… All return 0 when called in board_late_init() even though at startup the correct reset cause is displayed, but I have to write it to SRAM later on. And by that time it's 0. I think this has to do with what Wolfgang said about ds, bss, and stack, but if someone can shed some light that would be great. :) Thanks -- View this message in context: http://u-boot.10912.n7.nabble.com/porting-u-boot-MMU-question-tp194761p195618.html Sent from the U-Boot mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 16/17] dm: i2c: Add tests for I2C
Add some basic tests to check that the system works as expected.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add a test for automatic binding of generic I2C devices
- Add a new asm/test.h header for tests in sandbox
arch/sandbox/include/asm/test.h | 15 ++
drivers/i2c/sandbox_i2c.c | 8 +++
test/dm/Makefile| 1 +
test/dm/i2c.c | 112
test/dm/test.dts| 17 ++
5 files changed, 153 insertions(+)
create mode 100644 arch/sandbox/include/asm/test.h
create mode 100644 test/dm/i2c.c
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
new file mode 100644
index 000..d7f7bb5
--- /dev/null
+++ b/arch/sandbox/include/asm/test.h
@@ -0,0 +1,15 @@
+/*
+ * Test-related constants for sandbox
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_TEST_H
+#define __ASM_TEST_H
+
+/* The sandbox driver always permits an I2C device with this address */
+#define SANDBOX_I2C_TEST_ADDR 0x59
+
+#endif
diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c
index 3beb0f9..6d7f114 100644
--- a/drivers/i2c/sandbox_i2c.c
+++ b/drivers/i2c/sandbox_i2c.c
@@ -11,6 +11,7 @@
#include errno.h
#include fdtdec.h
#include i2c.h
+#include asm/test.h
#include dm/lists.h
#include dm/device-internal.h
@@ -67,6 +68,10 @@ static int sandbox_i2c_probe_chip(struct udevice *bus, uint
chip_addr)
struct udevice *emul;
int ret;
+ /* Special test code to return success but with no emulation */
+ if (chip_addr == SANDBOX_I2C_TEST_ADDR)
+ return 0;
+
ret = get_emul(bus, chip_addr, emul, ops);
if (ret)
return ret;
@@ -129,6 +134,9 @@ static int sandbox_i2c_child_pre_probe(struct udevice *dev)
{
struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev);
+ /* Ignore our test address */
+ if (i2c_chip-chip_addr == SANDBOX_I2C_TEST_ADDR)
+ return 0;
return i2c_chip_ofdata_to_platdata(gd-fdt_blob, dev-of_offset,
i2c_chip);
}
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 75d3d41..612aa95 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -20,4 +20,5 @@ ifneq ($(CONFIG_SANDBOX),)
obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_SPI) += spi.o
obj-$(CONFIG_DM_SPI_FLASH) += sf.o
+obj-$(CONFIG_DM_I2C) += i2c.o
endif
diff --git a/test/dm/i2c.c b/test/dm/i2c.c
new file mode 100644
index 000..3d5d066
--- /dev/null
+++ b/test/dm/i2c.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include fdtdec.h
+#include i2c.h
+#include dm/device-internal.h
+#include dm/test.h
+#include dm/uclass-internal.h
+#include dm/ut.h
+#include dm/util.h
+#include asm/state.h
+#include asm/test.h
+
+static const int busnum;
+static const int chip = 0x2c;
+
+/* Test that we can find buses and chips */
+static int dm_test_i2c_find(struct dm_test_state *dms)
+{
+ struct udevice *bus, *dev;
+ const int no_chip = 0x10;
+
+ ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_I2C, busnum,
+ false, bus));
+
+ /*
+* i2c_post_bind() will bind devices to chip selects. Check this then
+* remove the emulation and the slave device.
+*/
+ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, bus));
+ ut_assertok(i2c_probe(bus, chip, dev));
+ ut_asserteq(-ENODEV, i2c_probe(bus, no_chip, dev));
+ ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_I2C, 1, bus));
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_find, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_i2c_read_write(struct dm_test_state *dms)
+{
+ struct udevice *bus, *dev;
+ uint8_t buf[5];
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, bus));
+ ut_assertok(i2c_get_chip(bus, chip, dev));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, \0\0\0\0\0, sizeof(buf)));
+ ut_assertok(i2c_write(dev, 2, (uint8_t *)AB, 2));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, \0\0AB\0, sizeof(buf)));
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_read_write, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_i2c_speed(struct dm_test_state *dms)
+{
+ struct udevice *bus, *dev;
+ uint8_t buf[5];
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, bus));
+ ut_assertok(i2c_get_chip(bus, chip, dev));
+ ut_assertok(i2c_set_bus_speed(bus, 10));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(i2c_set_bus_speed(bus, 40));
+ ut_asserteq(40, i2c_get_bus_speed(bus));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+
[U-Boot] [PATCH v2 01/17] dm: i2c: Move error reporting into a common function
Factor out the common code to make it easier to adjust it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add a suitable commit message
common/cmd_i2c.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 3a75f94..c266b88 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -198,6 +198,19 @@ static uint get_alen(char *arg)
return alen;
}
+enum i2c_err_op {
+ I2C_ERR_READ,
+ I2C_ERR_WRITE,
+};
+
+static int i2c_report_err(int ret, enum i2c_err_op op)
+{
+ printf(Error %s the chip: %d\n,
+ op == I2C_ERR_READ ? reading : writing, ret);
+
+ return CMD_RET_FAILURE;
+}
+
/**
* do_i2c_read() - Handle the i2c read command-line command
* @cmdtp: Command data struct pointer
@@ -245,7 +258,7 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv
memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
- puts (Error reading the chip.\n);
+ i2c_report_err(-1, I2C_ERR_READ);
return 1;
}
return 0;
@@ -286,8 +299,7 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[
while (length-- 0) {
if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
- puts(Error writing to the chip.\n);
- return 1;
+ return i2c_report_err(-1, I2C_ERR_WRITE);
}
/*
* No write delay with FRAM devices.
@@ -370,7 +382,7 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[]
linebytes = (nbytes DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
- puts (Error reading the chip.\n);
+ i2c_report_err(-1, I2C_ERR_READ);
else {
printf(%04x:, addr);
cp = linebuf;
@@ -452,7 +464,7 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[]
while (count-- 0) {
if (i2c_write(chip, addr++, alen, byte, 1) != 0)
- puts (Error writing the chip.\n);
+ i2c_report_err(-1, I2C_ERR_WRITE);
/*
* Wait for the write to complete. The write can take
* up to 10mSec (we allow a little more time).
@@ -528,7 +540,7 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[]
addr++;
}
if (err 0)
- puts (Error reading the chip,\n);
+ i2c_report_err(-1, I2C_ERR_READ);
else
printf (%08lx\n, crc);
@@ -601,7 +613,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int
argc, char * const arg
do {
printf(%08lx:, addr);
if (i2c_read(chip, addr, alen, (uchar *)data, size) != 0)
- puts (\nError reading the chip,\n);
+ i2c_report_err(-1, I2C_ERR_READ);
else {
data = cpu_to_be32(data);
if (size == 1)
@@ -644,7 +656,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int
argc, char * const arg
*/
bootretry_reset_cmd_timeout();
if (i2c_write(chip, addr, alen, (uchar *)data,
size) != 0)
- puts (Error writing the chip.\n);
+ i2c_report_err(-1, I2C_ERR_WRITE);
#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS *
1000);
#endif
@@ -783,7 +795,7 @@ static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[]
*/
while (1) {
if (i2c_read(chip, addr, alen, bytes, length) != 0)
- puts (Error reading the chip.\n);
+ i2c_report_err(-1, I2C_ERR_READ);
udelay(delay);
}
@@ -1341,7 +1353,7 @@ int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
chip = simple_strtoul(argv[1], NULL, 16);
if (i2c_read(chip, 0, 1, (uchar *)edid, sizeof(edid)) != 0) {
- puts(Error reading EDID content.\n);
+ i2c_report_err(-1, I2C_ERR_READ);
return 1;
}
--
2.1.0.rc2.206.gedb03e5
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 17/17] dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:
- CONFIG_SYS_I2C_INIT_BOARD
- CONFIG_I2C_MULTI_BUS
- CONFIG_SYS_MAX_I2C_BUS
- CONFIG_SYS_I2C_SPEED
- CONFIG_SYS_I2C
This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1
It has not been tested on Tegra 114 as I don't have that board.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Adjust tegra_i2c_child_pre_probe() to permit generic I2C devices
- Correct the compatible strings for I2C buses
- Don't init if the speed is 0, since this breaks the controller
- Expand coverage to all Tegra boards
arch/arm/cpu/tegra20-common/pmu.c | 21 +-
arch/arm/dts/tegra124-jetson-tk1.dts| 1 -
arch/arm/dts/tegra124-norrin.dts| 1 -
arch/arm/dts/tegra30-tec-ng.dts | 4 +
arch/arm/include/asm/arch-tegra/tegra_i2c.h | 2 +-
board/avionic-design/common/tamonten-ng.c | 12 +-
board/nvidia/cardhu/cardhu.c| 13 +-
board/nvidia/common/board.c | 4 -
board/nvidia/dalmore/dalmore.c | 21 +-
board/nvidia/whistler/whistler.c| 29 ++-
board/toradex/apalis_t30/apalis_t30.c | 19 +-
drivers/i2c/tegra_i2c.c | 320 +++-
drivers/power/tps6586x.c| 27 +--
include/configs/apalis_t30.h| 3 -
include/configs/beaver.h| 3 -
include/configs/cardhu.h| 5 -
include/configs/colibri_t30.h | 3 -
include/configs/dalmore.h | 5 -
include/configs/jetson-tk1.h| 5 -
include/configs/norrin.h| 5 -
include/configs/seaboard.h | 3 -
include/configs/tec-ng.h| 5 -
include/configs/tegra-common.h | 1 +
include/configs/tegra114-common.h | 3 -
include/configs/tegra124-common.h | 3 -
include/configs/tegra20-common.h| 3 -
include/configs/tegra30-common.h| 3 -
include/configs/trimslice.h | 3 -
include/configs/venice2.h | 5 -
include/configs/whistler.h | 3 -
include/tps6586x.h | 4 +-
31 files changed, 211 insertions(+), 328 deletions(-)
diff --git a/arch/arm/cpu/tegra20-common/pmu.c
b/arch/arm/cpu/tegra20-common/pmu.c
index c595f70..36a76a2 100644
--- a/arch/arm/cpu/tegra20-common/pmu.c
+++ b/arch/arm/cpu/tegra20-common/pmu.c
@@ -6,6 +6,7 @@
*/
#include common.h
+#include i2c.h
#include tps6586x.h
#include asm/io.h
#include asm/arch/tegra.h
@@ -23,9 +24,13 @@
#define VDD_TRANSITION_STEP0x06/* 150mv */
#define VDD_TRANSITION_RATE0x06/* 3.52mv/us */
+#define PMI_I2C_ADDRESS0x34/* chip requires this address */
+
int pmu_set_nominal(void)
{
- int core, cpu, bus;
+ struct udevice *bus, *dev;
+ int core, cpu;
+ int ret;
/* by default, the table has been filled with T25 settings */
switch (tegra_get_chip_sku()) {
@@ -42,12 +47,18 @@ int pmu_set_nominal(void)
return -1;
}
- bus = tegra_i2c_get_dvc_bus_num();
- if (bus == -1) {
+ ret = tegra_i2c_get_dvc_bus(bus);
+ if (ret) {
debug(%s: Cannot find DVC I2C bus\n, __func__);
- return -1;
+ return ret;
}
- tps6586x_init(bus);
+ ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, dev);
+ if (ret) {
+ debug(%s: Cannot find DVC I2C chip\n, __func__);
+ return ret;
+ }
+
+ tps6586x_init(dev);
tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
VDD_TRANSITION_RATE, VDD_RELATION);
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts
b/arch/arm/dts/tegra124-jetson-tk1.dts
index ffad116..f6fe9a0 100644
--- a/arch/arm/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -16,7 +16,6 @@
i2c2 = /i2c@7000c400;
i2c3 = /i2c@7000c500;
i2c4 = /i2c@7000c700;
- i2c5 = /i2c@7000d100;
sdhci0 = /sdhci@700b0600;
sdhci1 = /sdhci@700b0400;
spi0 = /spi@7000d400;
diff --git a/arch/arm/dts/tegra124-norrin.dts b/arch/arm/dts/tegra124-norrin.dts
index b07630c..2dbeab8 100644
--- a/arch/arm/dts/tegra124-norrin.dts
+++ b/arch/arm/dts/tegra124-norrin.dts
@@ -13,7 +13,6 @@
i2c2 = /i2c@7000c400;
i2c3 = /i2c@7000c500;
i2c4 = /i2c@7000c700;
- i2c5 = /i2c@7000d100;
sdhci0 = /sdhci@700b0600;
sdhci1 = /sdhci@700b0400;
spi0 = /spi@7000d400;
diff --git
[U-Boot] [PATCH v2 0/17] dm: Add I2C support and convert sandbox, tegra
This series adds I2C support to driver model. It has become apparent that this is a high priority as it is widely used. It follows along to some extent from the SPI conversion. Several changes are made from the original I2C implementations. Firstly it is not necessary to specify the chip address with every call, since each chip knows its own address - it is stored in struct dm_i2c_chip which is attached to each chip on the I2C bus. However, this information *is* passed to the driver since I presume most drivers need it and it would be cumbersome to look up in every call. Secondly there is no concept of a 'current' I2C bus so all associated logic is removed. With driver model i2c_set_bus_num() and i2c_get_bus_num() are not available. Since the chip device specifies both the bus and the chip address, there is no need for this concept. It also causes problems when one driver changes the current bus and forgets to change it back. Thirdly initialisation is handled by driver model's normal probe() method on each device so there should be no need for i2c_init_all(), i2c_init(), i2c_init_board(), i2c_board_late_init() and board_i2c_init(). I2C muxes are not yet supported. To support these we will need to maintain state of the current mux settings to avoid resetting every mux every time. Probably we need to add a sandbox I2C mux driver to permit testing of this. This can probably be done later. Platform data is not yet supported either, only device tree. The U_BOOT_I2C_MKENT_COMPLETE() and U_BOOT_I2C_ADAP_COMPLETE() macros are not used. Also struct i2c_adapter is not defined anymore. This will need to be addressed, perhaps as part of converting over a board that does not use device tree, assuming that we want to support this. The following I2C CONFIGs are no-longer needed when driver model is used: CONFIG_SYS_I2C_INIT_BOARD - each I2C bus is inited in its probe() method CONFIG_I2C_MULTI_BUS - we always support multi-bus with driver model CONFIG_SYS_MAX_I2C_BUS- the device tree aliases define available buses CONFIG_SYS_I2C_SPEED - the device tree specifies the speed for each bus CONFIG_SYS_I2C- this is the 'new old' API, now deprecated There are a few SPI patches included here due to a dependency on a new device binding function. This series is available at u-boot-dm/i2c-working. Changes in v2: - Add a suitable commit message - Add new patch to correct handling of aliases with embedded digits - Add new patch to add a function to bind a device by driver name - Add new patches to adjust SPI to use device_bind_driver() - Fix cihp typo - Implement generic I2C devices to allow 'i2c probe' on unknown devices - Return the probed device from i2c_probe() - Set the bus speed after the bus is probed - Add some debugging for generic I2C device binding - Add a 'deblock' method to recover an I2C bus stuck in mid-transaction - Add a helper function to find a chip on a particular bus number - Change alen to int so that it can be -1 (this was a bug) - Call the deblock() method for 'i2c reset' - Update commit message for EEPROM driver - Add a test for automatic binding of generic I2C devices - Add a new asm/test.h header for tests in sandbox - Adjust tegra_i2c_child_pre_probe() to permit generic I2C devices - Correct the compatible strings for I2C buses - Don't init if the speed is 0, since this breaks the controller - Expand coverage to all Tegra boards Simon Glass (17): dm: i2c: Move error reporting into a common function dm: core: Allow access to the device's driver_id data dm: core: Add functions to find parent and OF data dm: fdt: Correct handling of aliases with embedded digits dm: Add a function to bind a device by driver name dm: spi: Correct handling of SPI chip selects in sandbox dm: spi: Use device_bind_driver() instead of our own function dm: i2c: Add a uclass for I2C dm: i2c: Implement driver model support in the i2c command dm: i2c: Add I2C emulation driver for sandbox dm: i2c: Add a sandbox I2C driver dm: i2c: Add an I2C EEPROM simulator dm: i2c: config: Enable I2C for sandbox using driver model dm: i2c: dts: Add an I2C bus for sandbox dm: Add a simple EEPROM driver dm: i2c: Add tests for I2C dm: i2c: tegra: Convert to driver model arch/arm/cpu/tegra20-common/pmu.c | 21 +- arch/arm/dts/tegra124-jetson-tk1.dts| 1 - arch/arm/dts/tegra124-norrin.dts| 1 - arch/arm/dts/tegra30-tec-ng.dts | 4 + arch/arm/include/asm/arch-tegra/tegra_i2c.h | 2 +- arch/sandbox/dts/sandbox.dts| 17 ++ arch/sandbox/include/asm/test.h | 15 ++ board/avionic-design/common/tamonten-ng.c | 12 +- board/nvidia/cardhu/cardhu.c| 13 +- board/nvidia/common/board.c | 4 - board/nvidia/dalmore/dalmore.c | 21 +- board/nvidia/whistler/whistler.c| 29 ++- board/toradex/apalis_t30/apalis_t30.c | 19 +- common/cmd_i2c.c
[U-Boot] [PATCH v2 11/17] dm: i2c: Add a sandbox I2C driver
This driver includes some test features such as only supporting certain
bus speeds. It passes its I2C traffic through to an emulator.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/i2c/Makefile | 2 +-
drivers/i2c/sandbox_i2c.c | 148 ++
2 files changed, 149 insertions(+), 1 deletion(-)
create mode 100644 drivers/i2c/sandbox_i2c.c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 4c9db51..eba3a71 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
-obj-$(CONFIG_SYS_I2C_SANDBOX) += i2c-emul-uclass.o
+obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c
new file mode 100644
index 000..3beb0f9
--- /dev/null
+++ b/drivers/i2c/sandbox_i2c.c
@@ -0,0 +1,148 @@
+/*
+ * Simulate an I2C port
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include i2c.h
+#include dm/lists.h
+#include dm/device-internal.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dm_sandbox_i2c_emul_priv {
+ struct udevice *emul;
+};
+
+static int get_emul(struct udevice *bus, uint chip_addr, struct udevice **devp,
+ struct dm_i2c_ops **opsp)
+{
+ const void *blob = gd-fdt_blob;
+ struct dm_i2c_chip *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip(bus, chip_addr, dev);
+ if (ret)
+ return ret;
+ priv = dev_get_parentdata(dev);
+ if (!priv-emul) {
+ int node;
+
+ debug(Scanning i2c bus '%s' for devices\n, dev-name);
+ for (node = fdt_first_subnode(blob, dev-of_offset);
+ node = 0;
+ node = fdt_next_subnode(blob, node)) {
+ int ret;
+
+ ret = lists_bind_fdt(dev, blob, node, priv-emul);
+ if (ret)
+ return ret;
+ debug(Found emul '%s' for i2c device '%s'\n,
+ priv-emul-name, dev-name);
+ break;
+ }
+ }
+
+ if (!priv-emul)
+ return -ENODEV;
+ ret = device_probe(priv-emul);
+ if (ret)
+ return ret;
+ *devp = priv-emul;
+ *opsp = i2c_get_ops(priv-emul);
+
+ return 0;
+}
+
+static int sandbox_i2c_probe_chip(struct udevice *bus, uint chip_addr)
+{
+ struct dm_i2c_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ ret = get_emul(bus, chip_addr, emul, ops);
+ if (ret)
+ return ret;
+
+ return ops-probe(emul, chip_addr);
+}
+
+static int sandbox_i2c_read(struct udevice *bus, uint chip_addr, uint addr,
+ uint alen, uint8_t *buffer, int len)
+{
+ struct dm_i2c_bus *i2c = bus-uclass_priv;
+ struct dm_i2c_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ ret = get_emul(bus, chip_addr, emul, ops);
+ if (ret)
+ return ret;
+
+ /* For testing, don't allow reading above 400KHz */
+ if (i2c-speed_hz 40 || alen != 1)
+ return -EINVAL;
+ return ops-read(emul, chip_addr, addr, alen, buffer, len);
+}
+
+static int sandbox_i2c_write(struct udevice *bus, uint chip_addr, uint addr,
+uint alen, const uint8_t *buffer, int len)
+{
+ struct dm_i2c_bus *i2c = bus-uclass_priv;
+ struct dm_i2c_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ ret = get_emul(bus, chip_addr, emul, ops);
+ if (ret)
+ return ret;
+
+ /* For testing, don't allow writing above 100KHz */
+ if (i2c-speed_hz 10 || alen != 1)
+ return -EINVAL;
+ return ops-write(emul, chip_addr, addr, alen, buffer, len);
+}
+
+static int sandbox_i2c_set_addr_len(struct udevice *dev, uint addr_len)
+{
+ if (addr_len == 3)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops sandbox_i2c_ops = {
+ .probe = sandbox_i2c_probe_chip,
+ .read = sandbox_i2c_read,
+ .write = sandbox_i2c_write,
+ .set_addr_len = sandbox_i2c_set_addr_len,
+};
+
+static int sandbox_i2c_child_pre_probe(struct udevice *dev)
+{
+ struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev);
+
+ return i2c_chip_ofdata_to_platdata(gd-fdt_blob, dev-of_offset,
+ i2c_chip);
+}
+
+static const struct
[U-Boot] [PATCH v2 10/17] dm: i2c: Add I2C emulation driver for sandbox
In order to test I2C we need some sort of emulation interface. Add hooks
to allow a driver to emulate an I2C device for sandbox.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/i2c/Makefile | 1 +
drivers/i2c/i2c-emul-uclass.c | 14 ++
include/dm/uclass-id.h| 1 +
3 files changed, 16 insertions(+)
create mode 100644 drivers/i2c/i2c-emul-uclass.c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 25f0f19..4c9db51 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
+obj-$(CONFIG_SYS_I2C_SANDBOX) += i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
diff --git a/drivers/i2c/i2c-emul-uclass.c b/drivers/i2c/i2c-emul-uclass.c
new file mode 100644
index 000..aa89f95
--- /dev/null
+++ b/drivers/i2c/i2c-emul-uclass.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include i2c.h
+
+UCLASS_DRIVER(i2c_emul) = {
+ .id = UCLASS_I2C_EMUL,
+ .name = i2c_emul,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 43514bc..e9f6104 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -19,6 +19,7 @@ enum uclass_id {
UCLASS_TEST_FDT,
UCLASS_TEST_BUS,
UCLASS_SPI_EMUL,/* sandbox SPI device emulator */
+ UCLASS_I2C_EMUL,/* sandbox I2C device emulator */
UCLASS_SIMPLE_BUS,
/* U-Boot uclasses start here */
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 06/17] dm: spi: Correct handling of SPI chip selects in sandbox
This code was not updated when the chip select handling was adjusted. Fix
it to call the correct function.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/mtd/spi/sandbox.c | 2 +-
drivers/spi/spi-uclass.c | 11 +--
include/spi.h | 10 ++
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 1cf2f98..fecf6d4 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -602,7 +602,7 @@ static int sandbox_sf_bind_bus_cs(struct sandbox_state
*state, int busnum,
spec, ret);
return ret;
}
- ret = device_find_child_by_seq(bus, cs, true, slave);
+ ret = spi_find_chip_select(bus, cs, slave);
if (!ret) {
printf(Chip select %d already exists for spec '%s'\n, cs,
spec);
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 13c6b77..6bfc274 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -115,16 +115,7 @@ int spi_chip_select(struct udevice *dev)
return slave ? slave-cs : -ENOENT;
}
-/**
- * spi_find_chip_select() - Find the slave attached to chip select
- *
- * @bus: SPI bus to search
- * @cs:Chip select to look for
- * @devp: Returns the slave device if found
- * @return 0 if found, -ENODEV on error
- */
-static int spi_find_chip_select(struct udevice *bus, int cs,
- struct udevice **devp)
+int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp)
{
struct udevice *dev;
diff --git a/include/spi.h b/include/spi.h
index aa0a48e..5975cda 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -534,6 +534,16 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int
mode,
int spi_chip_select(struct udevice *slave);
/**
+ * spi_find_chip_select() - Find the slave attached to chip select
+ *
+ * @bus: SPI bus to search
+ * @cs:Chip select to look for
+ * @devp: Returns the slave device if found
+ * @return 0 if found, -ENODEV on error
+ */
+int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp);
+
+/**
* spi_bind_device() - bind a device to a bus's chip select
*
* This binds a new device to an given chip select (which must be unused).
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 04/17] dm: fdt: Correct handling of aliases with embedded digits
Since we scan from left to right looking for the first digit, i2c0 returns
2 instead of 0 for the alias number. Adjust the code to scan from right to
left instead.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to correct handling of aliases with embedded digits
lib/fdtdec.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 9714620..da6ef6b 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -355,9 +355,9 @@ int fdtdec_get_alias_seq(const void *blob, const char
*base, int offset,
slash = strrchr(prop, '/');
if (strcmp(slash + 1, find_name))
continue;
- for (p = name; *p; p++) {
- if (isdigit(*p)) {
- *seqp = simple_strtoul(p, NULL, 10);
+ for (p = name + strlen(name) - 1; p name; p--) {
+ if (!isdigit(*p)) {
+ *seqp = simple_strtoul(p + 1, NULL, 10);
debug(Found seq %d\n, *seqp);
return 0;
}
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 02/17] dm: core: Allow access to the device's driver_id data
When the device is created from a device tree node, it matches a compatible
string. Allow access to that string and the associated data.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/core/device.c | 5 +
drivers/core/lists.c | 17 -
include/dm/device.h | 11 +++
3 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 49faa29..0d84776 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -548,3 +548,8 @@ int device_find_next_child(struct udevice **devp)
return 0;
}
+
+ulong dev_get_of_data(struct udevice *dev)
+{
+ return dev-of_id-data;
+}
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 3a1ea85..9f33dde 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -89,22 +89,26 @@ int lists_bind_drivers(struct udevice *parent, bool
pre_reloc_only)
* tree error
*/
static int driver_check_compatible(const void *blob, int offset,
- const struct udevice_id *of_match)
+ const struct udevice_id *of_match,
+ const struct udevice_id **of_idp)
{
int ret;
+ *of_idp = NULL;
if (!of_match)
return -ENOENT;
while (of_match-compatible) {
ret = fdt_node_check_compatible(blob, offset,
of_match-compatible);
- if (!ret)
+ if (!ret) {
+ *of_idp = of_match;
return 0;
- else if (ret == -FDT_ERR_NOTFOUND)
+ } else if (ret == -FDT_ERR_NOTFOUND) {
return -ENODEV;
- else if (ret 0)
+ } else if (ret 0) {
return -EINVAL;
+ }
of_match++;
}
@@ -116,6 +120,7 @@ int lists_bind_fdt(struct udevice *parent, const void
*blob, int offset,
{
struct driver *driver = ll_entry_start(struct driver, driver);
const int n_ents = ll_entry_count(struct driver, driver);
+ const struct udevice_id *id;
struct driver *entry;
struct udevice *dev;
bool found = false;
@@ -127,7 +132,8 @@ int lists_bind_fdt(struct udevice *parent, const void
*blob, int offset,
if (devp)
*devp = NULL;
for (entry = driver; entry != driver + n_ents; entry++) {
- ret = driver_check_compatible(blob, offset, entry-of_match);
+ ret = driver_check_compatible(blob, offset, entry-of_match,
+ id);
name = fdt_get_name(blob, offset, NULL);
if (ret == -ENOENT) {
continue;
@@ -147,6 +153,7 @@ int lists_bind_fdt(struct udevice *parent, const void
*blob, int offset,
dm_warn(Error binding driver '%s'\n, entry-name);
return ret;
} else {
+ dev-of_id = id;
found = true;
if (devp)
*devp = dev;
diff --git a/include/dm/device.h b/include/dm/device.h
index 9ce95a8..287504c 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -47,6 +47,7 @@ struct driver_info;
* @name: Name of device, typically the FDT node name
* @platdata: Configuration data for this device
* @of_offset: Device tree node offset for this device (- for none)
+ * @of_id: Pointer to the udevice_id structure which created the device
* @parent: Parent of this device, or NULL for the top level device
* @priv: Private data for this device
* @uclass: Pointer to uclass for this device
@@ -65,6 +66,7 @@ struct udevice {
const char *name;
void *platdata;
int of_offset;
+ const struct udevice_id *of_id;
struct udevice *parent;
void *priv;
struct uclass *uclass;
@@ -206,6 +208,15 @@ void *dev_get_parentdata(struct udevice *dev);
void *dev_get_priv(struct udevice *dev);
/**
+ * dev_get_of_data() - get the device tree data used to bind a device
+ *
+ * When a device is bound using a device tree node, it matches a
+ * particular compatible string as in struct udevice_id. This function
+ * returns the associated data value for that compatible string
+ */
+ulong dev_get_of_data(struct udevice *dev);
+
+/**
* device_get_child() - Get the child of a device by index
*
* Returns the numbered child, 0 being the first. This does not use
--
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[U-Boot] [PATCH v2 05/17] dm: Add a function to bind a device by driver name
In some cases we need to manually bind a device to a particular driver.
Add a function to do this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to add a function to bind a device by driver name
drivers/core/lists.c | 21 +
include/dm/lists.h | 13 +
2 files changed, 34 insertions(+)
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 9f33dde..32f2242 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -77,6 +77,27 @@ int lists_bind_drivers(struct udevice *parent, bool
pre_reloc_only)
return result;
}
+int device_bind_driver(struct udevice *parent, const char *drv_name,
+ const char *dev_name, struct udevice **devp)
+{
+ struct driver *drv;
+ int ret;
+
+ drv = lists_driver_lookup_name(drv_name);
+ if (!drv) {
+ printf(Cannot find driver '%s'\n, drv_name);
+ return -ENOENT;
+ }
+ ret = device_bind(parent, drv, dev_name, NULL, -1, devp);
+ if (ret) {
+ printf(Cannot create device named '%s' (err=%d)\n,
+ dev_name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_OF_CONTROL
/**
* driver_check_compatible() - Check if a driver is compatible with this node
diff --git a/include/dm/lists.h b/include/dm/lists.h
index 704e33e..1b50af9 100644
--- a/include/dm/lists.h
+++ b/include/dm/lists.h
@@ -60,4 +60,17 @@ int lists_bind_drivers(struct udevice *parent, bool
pre_reloc_only);
int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
struct udevice **devp);
+/**
+ * device_bind_driver() - bind a device to a driver
+ *
+ * This binds a new device to a driver.
+ *
+ * @parent:Parent device
+ * @drv_name: Name of driver to attach to this parent
+ * @dev_name: Name of the new device thus created
+ * @devp: Returns the newly bound device
+ */
+int device_bind_driver(struct udevice *parent, const char *drv_name,
+ const char *dev_name, struct udevice **devp);
+
#endif
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 07/17] dm: spi: Use device_bind_driver() instead of our own function
The SPI function does the same thing, so we may as well just use the new
generic function. The 'cs' parameter was not actually used, so can be
dropped.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patches to adjust SPI to use device_bind_driver()
drivers/mtd/spi/sandbox.c | 2 +-
drivers/spi/spi-uclass.c | 23 +--
include/spi.h | 14 --
3 files changed, 2 insertions(+), 37 deletions(-)
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index fecf6d4..c6a5c4b 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -609,7 +609,7 @@ static int sandbox_sf_bind_bus_cs(struct sandbox_state
*state, int busnum,
return -EEXIST;
}
- ret = spi_bind_device(bus, cs, spi_flash_std, spec, slave);
+ ret = device_bind_driver(bus, spi_flash_std, spec, slave);
if (ret)
return ret;
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 6bfc274..64eb1f6 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -188,27 +188,6 @@ int spi_cs_info(struct udevice *bus, uint cs, struct
spi_cs_info *info)
return -ENODEV;
}
-int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
- const char *dev_name, struct udevice **devp)
-{
- struct driver *drv;
- int ret;
-
- drv = lists_driver_lookup_name(drv_name);
- if (!drv) {
- printf(Cannot find driver '%s'\n, drv_name);
- return -ENOENT;
- }
- ret = device_bind(bus, drv, dev_name, NULL, -1, devp);
- if (ret) {
- printf(Cannot create device named '%s' (err=%d)\n,
- dev_name, ret);
- return ret;
- }
-
- return 0;
-}
-
int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
struct udevice **devp)
{
@@ -255,7 +234,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int
mode,
if (ret == -ENODEV drv_name) {
debug(%s: Binding new device '%s', busnum=%d, cs=%d,
driver=%s\n,
__func__, dev_name, busnum, cs, drv_name);
- ret = spi_bind_device(bus, cs, drv_name, dev_name, dev);
+ ret = device_bind_driver(bus, drv_name, dev_name, dev);
if (ret)
return ret;
created = true;
diff --git a/include/spi.h b/include/spi.h
index 5975cda..5b78271 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -544,20 +544,6 @@ int spi_chip_select(struct udevice *slave);
int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp);
/**
- * spi_bind_device() - bind a device to a bus's chip select
- *
- * This binds a new device to an given chip select (which must be unused).
- *
- * @bus: SPI bus to search
- * @cs:Chip select to attach to
- * @drv_name: Name of driver to attach to this chip select
- * @dev_name: Name of the new device thus created
- * @devp: Returns the newly bound device
- */
-int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
- const char *dev_name, struct udevice **devp);
-
-/**
* spi_ofdata_to_platdata() - decode standard SPI platform data
*
* This decodes the speed and mode from a device tree node and puts it into
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 09/17] dm: i2c: Implement driver model support in the i2c command
The concept of a 'current bus' is now implemented in the command line
rather than in the uclass. Also the address length does not need to
be specified with each command - really we should consider dropping
this from most commands but it works OK for now.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Change alen to int so that it can be -1 (this was a bug)
- Call the deblock() method for 'i2c reset'
common/cmd_i2c.c | 336 ++-
1 file changed, 284 insertions(+), 52 deletions(-)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index c266b88..40495e1 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -69,8 +69,10 @@
#include bootretry.h
#include cli.h
#include command.h
+#include dm.h
#include edid.h
#include environment.h
+#include errno.h
#include i2c.h
#include malloc.h
#include asm/byteorder.h
@@ -117,6 +119,60 @@ static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
#define DISP_LINE_LEN 16
+/*
+ * Default for driver model is to use the chip's existing address length.
+ * For legacy code, this is not stored, so we need to use a suitable
+ * default.
+ */
+#ifdef CONFIG_DM_I2C
+#define DEFAULT_ADDR_LEN (-1)
+#else
+#define DEFAULT_ADDR_LEN 1
+#endif
+
+#ifdef CONFIG_DM_I2C
+static struct udevice *i2c_cur_bus;
+
+static int i2c_set_bus_num(unsigned int busnum)
+{
+ struct udevice *bus;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, bus);
+ if (ret) {
+ debug(%s: No bus %d\n, __func__, busnum);
+ return ret;
+ }
+ i2c_cur_bus = bus;
+
+ return 0;
+}
+
+static int i2c_get_cur_bus(struct udevice **busp)
+{
+ if (!i2c_cur_bus) {
+ puts(No I2C bus selected\n);
+ return -ENODEV;
+ }
+ *busp = i2c_cur_bus;
+
+ return 0;
+}
+
+static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
+{
+ struct udevice *bus;
+ int ret;
+
+ ret = i2c_get_cur_bus(bus);
+ if (ret)
+ return ret;
+
+ return i2c_get_chip(bus, chip_addr, devp);
+}
+
+#endif
+
/**
* i2c_init_board() - Board-specific I2C bus init
*
@@ -143,7 +199,7 @@ void i2c_init_board(void)
*
* Returns I2C bus speed in Hz.
*/
-#if !defined(CONFIG_SYS_I2C)
+#if !defined(CONFIG_SYS_I2C) !defined(CONFIG_DM_I2C)
/*
* TODO: Implement architecture-specific get/set functions
* Should go away, if we switched completely to new multibus support
@@ -182,12 +238,12 @@ int i2c_set_bus_speed(unsigned int speed)
*
* Returns the address length.
*/
-static uint get_alen(char *arg)
+static uint get_alen(char *arg, int default_len)
{
int j;
int alen;
- alen = 1;
+ alen = default_len;
for (j = 0; j 8; j++) {
if (arg[j] == '.') {
alen = arg[j+1] - '0';
@@ -227,8 +283,13 @@ static int i2c_report_err(int ret, enum i2c_err_op op)
static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const
argv[])
{
u_char chip;
- uintdevaddr, alen, length;
+ uintdevaddr, length;
+ int alen;
u_char *memaddr;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc != 5)
return CMD_RET_USAGE;
@@ -243,7 +304,7 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv
* 2 bytes long. Some day it might be 3 bytes long :-).
*/
devaddr = simple_strtoul(argv[2], NULL, 16);
- alen = get_alen(argv[2]);
+ alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
if (alen 3)
return CMD_RET_USAGE;
@@ -257,18 +318,31 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv
*/
memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
- if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
- i2c_report_err(-1, I2C_ERR_READ);
- return 1;
- }
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, dev);
+ if (!ret alen != -1)
+ ret = i2c_set_addr_len(dev, alen);
+ if (!ret)
+ ret = i2c_read(dev, devaddr, memaddr, length);
+#else
+ ret = i2c_read(chip, devaddr, alen, memaddr, length);
+#endif
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_READ);
+
return 0;
}
static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const
argv[])
{
u_char chip;
- uintdevaddr, alen, length;
+ uintdevaddr, length;
+ int alen;
u_char *memaddr;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc != 5)
return cmd_usage(cmdtp);
@@ -288,7 +362,7 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[
* 2 bytes long. Some
[U-Boot] [PATCH v2 03/17] dm: core: Add functions to find parent and OF data
Add dev_get_parent() as a convenience to obtain the parent of a device.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/core/device.c | 5 +
include/dm/device.h | 8
2 files changed, 13 insertions(+)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 0d84776..76b29fd 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -549,6 +549,11 @@ int device_find_next_child(struct udevice **devp)
return 0;
}
+struct udevice *dev_get_parent(struct udevice *child)
+{
+ return child-parent;
+}
+
ulong dev_get_of_data(struct udevice *dev)
{
return dev-of_id-data;
diff --git a/include/dm/device.h b/include/dm/device.h
index 287504c..13598a1 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -208,6 +208,14 @@ void *dev_get_parentdata(struct udevice *dev);
void *dev_get_priv(struct udevice *dev);
/**
+ * struct dev_get_parent() - Get the parent of a device
+ *
+ * @child: Child to check
+ * @return parent of child, or NULL if this is the root device
+ */
+struct udevice *dev_get_parent(struct udevice *child);
+
+/**
* dev_get_of_data() - get the device tree data used to bind a device
*
* When a device is bound using a device tree node, it matches a
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 08/17] dm: i2c: Add a uclass for I2C
The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:
- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Fix cihp typo
- Implement generic I2C devices to allow 'i2c probe' on unknown devices
- Return the probed device from i2c_probe()
- Set the bus speed after the bus is probed
- Add some debugging for generic I2C device binding
- Add a 'deblock' method to recover an I2C bus stuck in mid-transaction
- Add a helper function to find a chip on a particular bus number
drivers/i2c/Makefile | 1 +
drivers/i2c/i2c-uclass.c | 275 +++
include/config_fallbacks.h | 6 +
include/dm/uclass-id.h | 2 +
include/i2c.h | 288 +
5 files changed, 572 insertions(+)
create mode 100644 drivers/i2c/i2c-uclass.c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index d067897..25f0f19 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -4,6 +4,7 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_DM_I2C) += i2c-uclass.o
obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
new file mode 100644
index 000..9436dfa
--- /dev/null
+++ b/drivers/i2c/i2c-uclass.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include i2c.h
+#include malloc.h
+#include dm/device-internal.h
+#include dm/lists.h
+#include dm/root.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int i2c_read(struct udevice *dev, uint addr, uint8_t *buffer, int len)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+
+ if (!ops-read)
+ return -ENOSYS;
+
+ return ops-read(bus, chip-chip_addr, addr, chip-addr_len, buffer,
+len);
+}
+
+int i2c_write(struct udevice *dev, uint addr, const uint8_t *buffer, int len)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+
+ if (!ops-write)
+ return -ENOSYS;
+
+ return ops-write(bus, chip-chip_addr, addr, chip-addr_len, buffer,
+ len);
+}
+
+static int i2c_bind_driver(struct udevice *bus, uint chip_addr,
+ struct udevice **devp)
+{
+ struct dm_i2c_chip *chip;
+ char name[30], *str;
+ struct udevice *dev;
+ int ret;
+
+ snprintf(name, sizeof(name), generic_%x, chip_addr);
+ str = strdup(name);
+ ret = device_bind_driver(bus, i2c_generic_drv, str, dev);
+ debug(%s: device_bind_driver: ret=%d\n, __func__, ret);
+ if (ret)
+ goto err_bind;
+
+ /* Tell the device what we know about it */
+ chip = calloc(1, sizeof(struct dm_i2c_chip));
+ if (!chip) {
+ ret = -ENOMEM;
+ goto err_mem;
+ }
+ chip-chip_addr = chip_addr;
+ chip-addr_len = 1; /* we assume */
+ ret = device_probe_child(dev, chip);
+ debug(%s: device_probe_child: ret=%d\n, __func__, ret);
+ free(chip);
+ if (ret)
+ goto err_probe;
+
+ *devp = dev;
+ return 0;
+
+err_probe:
+err_mem:
+ device_unbind(dev);
+err_bind:
+ free(str);
+ return ret;
+}
+
+int i2c_get_chip(struct udevice *bus, uint chip_addr, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ debug(%s: Searching bus '%s' for address %02x: , __func__,
+ bus-name, chip_addr);
+ for (device_find_first_child(bus, dev); dev;
+ device_find_next_child(dev)) {
+ struct dm_i2c_chip store;
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ int ret;
+
+ if (!chip) {
+ chip = store;
+ i2c_chip_ofdata_to_platdata(gd-fdt_blob,
+ dev-of_offset, chip);
+ }
+ if (chip-chip_addr == chip_addr) {
+ ret = device_probe(dev);
+ debug(found, ret=%d\n, ret);
+ if (ret)
+ return ret;
+ *devp = dev;
+ return 0;
+ }
+ }
+ debug(not found\n);
+ return i2c_bind_driver(bus, chip_addr, devp);
+}
+
+int i2c_get_chip_for_busnum(int busnum, int chip_addr, struct udevice **devp)
+{
+ struct udevice
[U-Boot] [PATCH v2 13/17] dm: i2c: config: Enable I2C for sandbox using driver model
Enable the options to bring up I2C on sandbox. Also enable all the available I2C commands for testing purposes. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: None include/configs/sandbox.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index ee4b244..d4ebe6a 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -110,6 +110,12 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_DM_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_SANDBOX +#define CONFIG_I2C_EDID +#define CONFIG_I2C_EEPROM + /* Memory things - we don't really want a memory test */ #define CONFIG_SYS_LOAD_ADDR 0x #define CONFIG_SYS_MEMTEST_START 0x0010 -- 2.1.0.rc2.206.gedb03e5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 14/17] dm: i2c: dts: Add an I2C bus for sandbox
Add an I2C bus to the device tree, with an EEPROM emulator attached to one
of the addresses.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/sandbox/dts/sandbox.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 7614715..11748ae 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -134,6 +134,23 @@
num-gpios = 20;
};
+ i2c@0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+ compatible = sandbox,i2c;
+ clock-frequency = 40;
+ eeprom@2c {
+ reg = 0x2c;
+ compatible = i2c-eeprom;
+ emul {
+ compatible = sandbox,i2c-eeprom;
+ sandbox,filename = i2c.bin;
+ sandbox,size = 128;
+ };
+ };
+ };
+
spi@0 {
#address-cells = 1;
#size-cells = 0;
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 15/17] dm: Add a simple EEPROM driver
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update commit message for EEPROM driver
drivers/misc/Makefile | 1 +
drivers/misc/i2c_eeprom.c | 51 +++
include/dm/uclass-id.h| 1 +
include/i2c_eeprom.h | 19 ++
4 files changed, 72 insertions(+)
create mode 100644 drivers/misc/i2c_eeprom.c
create mode 100644 include/i2c_eeprom.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ff02184..6fa836f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_GPIO_LED) += gpio_led.o
+obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
new file mode 100644
index 000..d0548ec
--- /dev/null
+++ b/drivers/misc/i2c_eeprom.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include i2c.h
+#include i2c_eeprom.h
+
+static int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf,
+ int size)
+{
+ return -ENODEV;
+}
+
+static int i2c_eeprom_write(struct udevice *dev, int offset,
+ const uint8_t *buf, int size)
+{
+ return -ENODEV;
+}
+
+struct i2c_eeprom_ops i2c_eeprom_std_ops = {
+ .read = i2c_eeprom_read,
+ .write = i2c_eeprom_write,
+};
+
+int i2c_eeprom_std_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct udevice_id i2c_eeprom_std_ids[] = {
+ { .compatible = i2c-eeprom },
+ { }
+};
+
+U_BOOT_DRIVER(i2c_eeprom_std) = {
+ .name = i2c_eeprom,
+ .id = UCLASS_I2C_EEPROM,
+ .of_match = i2c_eeprom_std_ids,
+ .probe = i2c_eeprom_std_probe,
+ .priv_auto_alloc_size = sizeof(struct i2c_eeprom),
+ .ops= i2c_eeprom_std_ops,
+};
+
+UCLASS_DRIVER(i2c_eeprom) = {
+ .id = UCLASS_I2C_EEPROM,
+ .name = i2c_eeprom,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index e9f6104..7f7dcf7 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -31,6 +31,7 @@ enum uclass_id {
UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_I2C, /* I2C bus */
UCLASS_I2C_GENERIC, /* Generic I2C device */
+ UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_COUNT,
UCLASS_INVALID = -1,
diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h
new file mode 100644
index 000..ea6c962
--- /dev/null
+++ b/include/i2c_eeprom.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __I2C_EEPROM
+#define __I2C_EEPROM
+
+struct i2c_eeprom_ops {
+ int (*read)(struct udevice *dev, int offset, uint8_t *buf, int size);
+ int (*write)(struct udevice *dev, int offset, const uint8_t *buf,
+int size);
+};
+
+struct i2c_eeprom {
+};
+
+#endif
--
2.1.0.rc2.206.gedb03e5
___
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[U-Boot] [PATCH v2 12/17] dm: i2c: Add an I2C EEPROM simulator
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/misc/Makefile | 3 ++
drivers/misc/i2c_eeprom_emul.c | 108 +
2 files changed, 111 insertions(+)
create mode 100644 drivers/misc/i2c_eeprom_emul.c
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 2f2e48f..ff02184 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -20,6 +20,9 @@ obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_PDSP188x) += pdsp188x.o
+ifdef CONFIG_DM_I2C
+obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
+endif
obj-$(CONFIG_STATUS_LED) += status_led.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c
new file mode 100644
index 000..9a4c385
--- /dev/null
+++ b/drivers/misc/i2c_eeprom_emul.c
@@ -0,0 +1,108 @@
+/*
+ * Simulate an I2C eeprom
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include fdtdec.h
+#include i2c.h
+#include malloc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sandbox_i2c_flash_plat_data {
+ const char *filename;
+ int size;
+};
+
+struct sandbox_i2c_flash {
+ uint8_t *data;
+};
+
+static int sandbox_i2c_eprom_probe_chip(struct udevice *dev, uint chip)
+{
+ return 0;
+}
+
+static int sandbox_i2c_eprom_read(struct udevice *dev, uint chip_addr,
+ uint addr, uint alen, uint8_t *buffer,
+ int len)
+{
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_flash *priv = dev_get_priv(dev);
+
+ if (addr + len plat-size)
+ return -EINVAL;
+ memcpy(buffer, priv-data + addr, len);
+
+ return 0;
+}
+
+static int sandbox_i2c_eprom_write(struct udevice *dev, uint chip_addr,
+ uint addr, uint alen, const uint8_t *buffer,
+ int len)
+{
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_flash *priv = dev_get_priv(dev);
+
+ if (addr + len plat-size)
+ return -EINVAL;
+ memcpy(priv-data + addr, buffer, len);
+
+ return 0;
+}
+
+struct dm_i2c_ops sandbox_i2c_emul_ops = {
+ .probe = sandbox_i2c_eprom_probe_chip,
+ .read = sandbox_i2c_eprom_read,
+ .write = sandbox_i2c_eprom_write,
+};
+
+static int sandbox_i2c_eeprom_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+
+ plat-size = fdtdec_get_int(gd-fdt_blob, dev-of_offset,
+ sandbox,size, 32);
+ plat-filename = fdt_getprop(gd-fdt_blob, dev-of_offset,
+sandbox,filename, NULL);
+ if (!plat-filename) {
+ debug(%s: No filename for device '%s'\n, __func__,
+ dev-name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int sandbox_i2c_eeprom_probe(struct udevice *dev)
+{
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_flash *priv = dev_get_priv(dev);
+
+ priv-data = calloc(1, plat-size);
+ if (!priv-data)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static const struct udevice_id sandbox_i2c_ids[] = {
+ { .compatible = sandbox,i2c-eeprom },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_i2c_emul) = {
+ .name = sandbox_i2c_eeprom_emul,
+ .id = UCLASS_I2C_EMUL,
+ .of_match = sandbox_i2c_ids,
+ .ofdata_to_platdata = sandbox_i2c_eeprom_ofdata_to_platdata,
+ .probe = sandbox_i2c_eeprom_probe,
+ .priv_auto_alloc_size = sizeof(struct sandbox_i2c_flash),
+ .platdata_auto_alloc_size = sizeof(struct sandbox_i2c_flash_plat_data),
+ .ops= sandbox_i2c_emul_ops,
+};
--
2.1.0.rc2.206.gedb03e5
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Re: [U-Boot] [PATCH v1 2/2] imx: fix exception vectors relocation in i.MX27
On 11/11/14 17:46, Albert ARIBAUD wrote:
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x) or
high (0x) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is ARM926E-JS, thus has only normal and
high options, but does not provide RAM at 0x
and has only ROM at 0x; it is therefore not
possible to move or change its exception vectors.
Besides, i.MX27 ROM code does provide an indirect
vectors table but at a non-standard address and with
the reset and reserved vectors missing.
Turn the current vector relocation code into a weak
routine called after relocate_code from crt0, and add
strong version for i.MX27.
Signed-off-by: Albert ARIBAUDalbert.u.b...@aribaud.net
---
arch/arm/cpu/arm926ejs/mx27/Makefile | 4 ++
arch/arm/cpu/arm926ejs/mx27/relocate.S | 49
arch/arm/lib/crt0.S| 5 +++
arch/arm/lib/relocate.S| 69 --
4 files changed, 99 insertions(+), 28 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/mx27/relocate.S
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile
b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 4976bbb..0edf144 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -5,3 +5,7 @@
# SPDX-License-Identifier:GPL-2.0+
obj-y = generic.o reset.o timer.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += relocate.o
+endif
diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S
b/arch/arm/cpu/arm926ejs/mx27/relocate.S
new file mode 100644
index 000..97003b3
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S
@@ -0,0 +1,49 @@
+/*
+ * relocate - i.MX27-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUDalbert.u.b...@aribaud.net
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#includeasm-offsets.h
+#includeconfig.h
+#includelinux/linkage.h
+
+/*
+ * The i.MX27 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0x),
+ * thus only the low address (0x) is useable; but that is
+ * in ROM. Therefore, vectors cannot be changed at all.
+ *
+ * However, these ROM-based vectors actually just perform indirect
+ * calls through pointers located in RAM at SoC-specific addresses,
+ * as follows:
+ *
+ * Offset Exception Use by ROM code
+ * 0x reset indirect branch to [0x0014]
+ * 0x0004 undefined instruction indirect branch to [0xfef0]
+ * 0x0008 software interrupt indirect branch to [0xfef4]
+ * 0x000c prefetch abort indirect branch to [0xfef8]
+ * 0x0010 data abort indirect branch to [0xfefc]
+ * 0x0014 (reserved in ARMv5)vector to ROM reset: 0xc000
+ * 0x0018 IRQindirect branch to [0xff00]
+ * 0x001c FIQindirect branch to [0xff04]
+ *
+ * In order to initialize exceptions on i.MX27, we must copy U-Boot's
+ * indirect (not exception!) vector table into 0xfef0..0xff04
+ * taking care not to copy vectors 0x00 (reset) and 0x14 (reserved).
+ */
+
+ .section.text.relocate_vectors,ax,%progbits
+
+ENTRY(relocate_vectors)
+
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+ ldr r1, =0xFEF0
+ ldmia r0!, {r2-r8,r10} /* load all eight vectors */
+ stmia r1!, {r3-r6,r8,r10} /* only write supported vectors */
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 29cdad0..a33ad3e 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -104,6 +104,11 @@ clr_gd:
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
b relocate_code
here:
+/*
+ * now relocate vectors
+ */
+
+ bl relocate_vectors
/* Set up final (full) environment */
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 6ede41c..92f5314 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -11,6 +11,47 @@
#includelinux/linkage.h
/*
+ * Default/weak exception vectors relocation routine
+ *
+ * This routine covers the standard ARM cases: normal (0x),
+ * high (0x) and VBAR. SoCs which do not comply with any of
+ * the standard cases must provide their own, strong, version.
+ */
+
+ .section.text.relocate_vectors,ax,%progbits
+ .weak relocate_vectors
+
+ENTRY(relocate_vectors)
+
+#ifdef CONFIG_HAS_VBAR
+ /*
+* If the ARM processor has the security extensions,
+* use VBAR to relocate the exception vectors.
+*/
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
+#else
+ /*
+* Copy the relocated exception vectors to the
+*
[U-Boot] [PATCH v2] spl: Change debug to printf for Unsupported boot-device
We had the problem on an AM33xx platform, that SPL detected an unsupported boot-device. But since this message is a debug message it took a bit of time to really know, where the hangup in SPL resulted from. So let's change this debug message to a printf and also print the detected boot-device that is not supported. This makes debugging of such cases much easier. Signed-off-by: Stefan Roese s...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Tom Rini tr...@ti.com --- v2: - Added #if check so that the printf is only included when serial support is enabled. - Compile tested on all ARM boards common/spl/spl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index d85bab3..cef7bca 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -216,7 +216,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2) break; #endif default: - debug(SPL: Un-supported Boot Device\n); +#if defined(CONFIG_SPL_SERIAL_SUPPORT) defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + printf(SPL: Unsupported Boot Device %d\n, boot_device); +#endif hang(); } -- 2.1.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/2] imx: fix exception vectors relocation in i.MX27
Hello trem,
On Tue, 11 Nov 2014 19:02:21 +0100, trem trem...@yahoo.fr wrote:
On 11/11/14 17:46, Albert ARIBAUD wrote:
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x) or
high (0x) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is ARM926E-JS, thus has only normal and
high options, but does not provide RAM at 0x
and has only ROM at 0x; it is therefore not
possible to move or change its exception vectors.
Besides, i.MX27 ROM code does provide an indirect
vectors table but at a non-standard address and with
the reset and reserved vectors missing.
Turn the current vector relocation code into a weak
routine called after relocate_code from crt0, and add
strong version for i.MX27.
Signed-off-by: Albert ARIBAUDalbert.u.b...@aribaud.net
---
arch/arm/cpu/arm926ejs/mx27/Makefile | 4 ++
arch/arm/cpu/arm926ejs/mx27/relocate.S | 49
arch/arm/lib/crt0.S| 5 +++
arch/arm/lib/relocate.S| 69
--
4 files changed, 99 insertions(+), 28 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/mx27/relocate.S
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile
b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 4976bbb..0edf144 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -5,3 +5,7 @@
# SPDX-License-Identifier:GPL-2.0+
obj-y = generic.o reset.o timer.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += relocate.o
+endif
diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S
b/arch/arm/cpu/arm926ejs/mx27/relocate.S
new file mode 100644
index 000..97003b3
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S
@@ -0,0 +1,49 @@
+/*
+ * relocate - i.MX27-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUDalbert.u.b...@aribaud.net
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#includeasm-offsets.h
+#includeconfig.h
+#includelinux/linkage.h
+
+/*
+ * The i.MX27 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0x),
+ * thus only the low address (0x) is useable; but that is
+ * in ROM. Therefore, vectors cannot be changed at all.
+ *
+ * However, these ROM-based vectors actually just perform indirect
+ * calls through pointers located in RAM at SoC-specific addresses,
+ * as follows:
+ *
+ * Offset Exception Use by ROM code
+ * 0x reset indirect branch to [0x0014]
+ * 0x0004 undefined instruction indirect branch to [0xfef0]
+ * 0x0008 software interrupt indirect branch to [0xfef4]
+ * 0x000c prefetch abort indirect branch to [0xfef8]
+ * 0x0010 data abort indirect branch to [0xfefc]
+ * 0x0014 (reserved in ARMv5)vector to ROM reset: 0xc000
+ * 0x0018 IRQindirect branch to [0xff00]
+ * 0x001c FIQindirect branch to [0xff04]
+ *
+ * In order to initialize exceptions on i.MX27, we must copy U-Boot's
+ * indirect (not exception!) vector table into 0xfef0..0xff04
+ * taking care not to copy vectors 0x00 (reset) and 0x14 (reserved).
+ */
+
+ .section.text.relocate_vectors,ax,%progbits
+
+ENTRY(relocate_vectors)
+
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+ ldr r1, =0xFEF0
+ ldmia r0!, {r2-r8,r10} /* load all eight vectors */
+ stmia r1!, {r3-r6,r8,r10} /* only write supported vectors */
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 29cdad0..a33ad3e 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -104,6 +104,11 @@ clr_gd:
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
b relocate_code
here:
+/*
+ * now relocate vectors
+ */
+
+ bl relocate_vectors
/* Set up final (full) environment */
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 6ede41c..92f5314 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -11,6 +11,47 @@
#includelinux/linkage.h
/*
+ * Default/weak exception vectors relocation routine
+ *
+ * This routine covers the standard ARM cases: normal (0x),
+ * high (0x) and VBAR. SoCs which do not comply with any of
+ * the standard cases must provide their own, strong, version.
+ */
+
+ .section.text.relocate_vectors,ax,%progbits
+ .weak relocate_vectors
+
+ENTRY(relocate_vectors)
+
+#ifdef CONFIG_HAS_VBAR
+ /*
+* If the ARM
[U-Boot] [PATCH v2 0/2] Fix SoC-specific exception handling
Short version: * this patch fixes exception handling on i.MX27 which was broken, probably from day one. * i.MX27-based board Maintainers please test this patch: make sure your board boots with it and make sure e.g. a write to address 0 causes U-Boot to signal a data abort. * i.MX custodian please review this patch and let me know if this should also be done for other i.MX SoCs as well. Long version: This patch was created after apf27 maintainer found out that the board did not boot any more. The root cause was that commit 3ff46cc4 would try and write into the exception vectors table, which i.MX27 has in ROM. This caused a data abort, and as the U-Boot vectors were not in place yet, this abort went to the ROM code which silently hung. Investigation led to a patch sent in 2009 to the list (but never applied) with a description of the i.MX27 exception handling: http://lists.denx.de/pipermail/u-boot/2009-October/062811.html By his own author's admission, this patch was not fit for inclusion in U-Boot, but it gave the technical information needed to produce this present patch set. The first patch is only cosmetic, fixing whitespace quirks which affect legibility or cause a warning in patman. The second patch moves vectors relocation out of the relocate_code routine and into its own relocate_vectors routine. This routine is made weak so that it can be replaced by a SoC-specific, strong one. Such a strong replacement is provided for i.MX27. Changes in v2: - Fixed wrong i.MX27 vector relocation code Albert ARIBAUD (2): cosmetic: arm: fix whitespace in arch/arm/lib/relocate.S imx: fix exception vectors relocation in imx27 arch/arm/cpu/arm926ejs/mx27/Makefile | 4 ++ arch/arm/cpu/arm926ejs/mx27/relocate.S | 51 arch/arm/lib/crt0.S| 5 +++ arch/arm/lib/relocate.S| 73 -- 4 files changed, 103 insertions(+), 30 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/mx27/relocate.S -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] cosmetic: arm: fix whitespace in arch/arm/lib/relocate.S
Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net
---
Changes in v2: None
arch/arm/lib/relocate.S | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index b4a258c..6ede41c 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -74,8 +74,8 @@ fixnext:
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
andsr2, r2, #(1 13)
- ldreq r1, =0x /* If V=0 */
- ldrne r1, =0x /* If V=1 */
+ ldreq r1, =0x /* If V=0 */
+ ldrne r1, =0x /* If V=1 */
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
ldmia r0!, {r2-r8,r10}
@@ -96,9 +96,9 @@ relocate_done:
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__
- movpc, lr
+ mov pc, lr
#else
- bxlr
+ bx lr
#endif
ENDPROC(relocate_code)
--
2.1.0
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[U-Boot] [PATCH v2 2/2] imx: fix exception vectors relocation in imx27
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x) or
high (0x) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is ARM926E-JS, thus has only normal and
high options, but does not provide RAM at 0x
and has only ROM at 0x; it is therefore not
possible to move or change its exception vectors.
Besides, i.MX27 ROM code does provide an indirect
vectors table but at a non-standard address and with
the reset and reserved vectors missing.
Turn the current vector relocation code into a weak
routine called after relocate_code from crt0, and add
strong version for i.MX27.
Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net
---
Changes in v2:
- Fixed wrong i.MX27 vector relocation code
arch/arm/cpu/arm926ejs/mx27/Makefile | 4 ++
arch/arm/cpu/arm926ejs/mx27/relocate.S | 51 +
arch/arm/lib/crt0.S| 5 +++
arch/arm/lib/relocate.S| 69 --
4 files changed, 101 insertions(+), 28 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/mx27/relocate.S
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile
b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 4976bbb..0edf144 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -5,3 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y = generic.o reset.o timer.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += relocate.o
+endif
diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S
b/arch/arm/cpu/arm926ejs/mx27/relocate.S
new file mode 100644
index 000..4c39a5a
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S
@@ -0,0 +1,51 @@
+/*
+ * relocate - i.MX27-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUD albert.u.b...@aribaud.net
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm-offsets.h
+#include config.h
+#include linux/linkage.h
+
+/*
+ * The i.MX27 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0x),
+ * thus only the low address (0x) is useable; but that is
+ * in ROM. Therefore, vectors cannot be changed at all.
+ *
+ * However, these ROM-based vectors actually just perform indirect
+ * calls through pointers located in RAM at SoC-specific addresses,
+ * as follows:
+ *
+ * Offset Exception Use by ROM code
+ * 0x reset indirect branch to [0x0014]
+ * 0x0004 undefined instruction indirect branch to [0xfef0]
+ * 0x0008 software interrupt indirect branch to [0xfef4]
+ * 0x000c prefetch abort indirect branch to [0xfef8]
+ * 0x0010 data abort indirect branch to [0xfefc]
+ * 0x0014 (reserved in ARMv5)vector to ROM reset: 0xc000
+ * 0x0018 IRQindirect branch to [0xff00]
+ * 0x001c FIQindirect branch to [0xff04]
+ *
+ * In order to initialize exceptions on i.MX27, we must copy U-Boot's
+ * indirect (not exception!) vector table into 0xfef0..0xff04
+ * taking care not to copy vectors 0x00 (reset) and 0x14 (reserved).
+ */
+
+ .section.text.relocate_vectors,ax,%progbits
+
+ENTRY(relocate_vectors)
+
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+ ldr r1, =32 /* size of vector table */
+ add r0, r0, r1 /* skip to indirect table */
+ ldr r1, =0xFEF0 /* i.MX27 indirect table */
+ ldmia r0!, {r2-r8,r10}/* load all eight vectors */
+ stmia r1!, {r3-r6,r8,r10} /* only write certain vectors */
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 29cdad0..a33ad3e 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -104,6 +104,11 @@ clr_gd:
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
b relocate_code
here:
+/*
+ * now relocate vectors
+ */
+
+ bl relocate_vectors
/* Set up final (full) environment */
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 6ede41c..92f5314 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -11,6 +11,47 @@
#include linux/linkage.h
/*
+ * Default/weak exception vectors relocation routine
+ *
+ * This routine covers the standard ARM cases: normal (0x),
+ * high (0x) and VBAR. SoCs which do not comply with any of
+ * the standard cases must provide their own, strong, version.
+ */
+
+ .section.text.relocate_vectors,ax,%progbits
+ .weak relocate_vectors
+
+ENTRY(relocate_vectors)
+
+#ifdef CONFIG_HAS_VBAR
+ /*
+* If the ARM processor has the security extensions,
+* use VBAR to relocate the exception vectors.
+*/
+
Re: [U-Boot] [PATCH v2 06/17] dm: spi: Correct handling of SPI chip selects in sandbox
On 11 November 2014 23:16, Simon Glass s...@chromium.org wrote:
This code was not updated when the chip select handling was adjusted. Fix
it to call the correct function.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/mtd/spi/sandbox.c | 2 +-
drivers/spi/spi-uclass.c | 11 +--
include/spi.h | 10 ++
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 1cf2f98..fecf6d4 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -602,7 +602,7 @@ static int sandbox_sf_bind_bus_cs(struct sandbox_state
*state, int busnum,
spec, ret);
return ret;
}
- ret = device_find_child_by_seq(bus, cs, true, slave);
+ ret = spi_find_chip_select(bus, cs, slave);
if (!ret) {
printf(Chip select %d already exists for spec '%s'\n, cs,
spec);
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 13c6b77..6bfc274 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -115,16 +115,7 @@ int spi_chip_select(struct udevice *dev)
return slave ? slave-cs : -ENOENT;
}
-/**
- * spi_find_chip_select() - Find the slave attached to chip select
- *
- * @bus: SPI bus to search
- * @cs:Chip select to look for
- * @devp: Returns the slave device if found
- * @return 0 if found, -ENODEV on error
- */
-static int spi_find_chip_select(struct udevice *bus, int cs,
- struct udevice **devp)
+int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp)
{
struct udevice *dev;
diff --git a/include/spi.h b/include/spi.h
index aa0a48e..5975cda 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -534,6 +534,16 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed,
int mode,
int spi_chip_select(struct udevice *slave);
/**
+ * spi_find_chip_select() - Find the slave attached to chip select
+ *
+ * @bus: SPI bus to search
+ * @cs:Chip select to look for
+ * @devp: Returns the slave device if found
+ * @return 0 if found, -ENODEV on error
+ */
+int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp);
+
+/**
* spi_bind_device() - bind a device to a bus's chip select
*
* This binds a new device to an given chip select (which must be unused).
--
2.1.0.rc2.206.gedb03e5
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
thanks!
--
Jagan.
___
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Re: [U-Boot] [PATCH v2 05/17] dm: Add a function to bind a device by driver name
On 11 November 2014 23:16, Simon Glass s...@chromium.org wrote:
In some cases we need to manually bind a device to a particular driver.
Add a function to do this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to add a function to bind a device by driver name
drivers/core/lists.c | 21 +
include/dm/lists.h | 13 +
2 files changed, 34 insertions(+)
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 9f33dde..32f2242 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -77,6 +77,27 @@ int lists_bind_drivers(struct udevice *parent, bool
pre_reloc_only)
return result;
}
+int device_bind_driver(struct udevice *parent, const char *drv_name,
+ const char *dev_name, struct udevice **devp)
+{
+ struct driver *drv;
+ int ret;
+
+ drv = lists_driver_lookup_name(drv_name);
+ if (!drv) {
+ printf(Cannot find driver '%s'\n, drv_name);
+ return -ENOENT;
+ }
+ ret = device_bind(parent, drv, dev_name, NULL, -1, devp);
+ if (ret) {
+ printf(Cannot create device named '%s' (err=%d)\n,
+ dev_name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_OF_CONTROL
/**
* driver_check_compatible() - Check if a driver is compatible with this node
diff --git a/include/dm/lists.h b/include/dm/lists.h
index 704e33e..1b50af9 100644
--- a/include/dm/lists.h
+++ b/include/dm/lists.h
@@ -60,4 +60,17 @@ int lists_bind_drivers(struct udevice *parent, bool
pre_reloc_only);
int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
struct udevice **devp);
+/**
+ * device_bind_driver() - bind a device to a driver
+ *
+ * This binds a new device to a driver.
+ *
+ * @parent:Parent device
+ * @drv_name: Name of driver to attach to this parent
+ * @dev_name: Name of the new device thus created
+ * @devp: Returns the newly bound device
+ */
+int device_bind_driver(struct udevice *parent, const char *drv_name,
+ const char *dev_name, struct udevice **devp);
+
#endif
--
2.1.0.rc2.206.gedb03e5
___
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http://lists.denx.de/mailman/listinfo/u-boot
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
thanks!
--
Jagan.
___
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Re: [U-Boot] [PATCH v2 07/17] dm: spi: Use device_bind_driver() instead of our own function
On 11 November 2014 23:16, Simon Glass s...@chromium.org wrote:
The SPI function does the same thing, so we may as well just use the new
generic function. The 'cs' parameter was not actually used, so can be
dropped.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patches to adjust SPI to use device_bind_driver()
drivers/mtd/spi/sandbox.c | 2 +-
drivers/spi/spi-uclass.c | 23 +--
include/spi.h | 14 --
3 files changed, 2 insertions(+), 37 deletions(-)
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index fecf6d4..c6a5c4b 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -609,7 +609,7 @@ static int sandbox_sf_bind_bus_cs(struct sandbox_state
*state, int busnum,
return -EEXIST;
}
- ret = spi_bind_device(bus, cs, spi_flash_std, spec, slave);
+ ret = device_bind_driver(bus, spi_flash_std, spec, slave);
if (ret)
return ret;
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 6bfc274..64eb1f6 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -188,27 +188,6 @@ int spi_cs_info(struct udevice *bus, uint cs, struct
spi_cs_info *info)
return -ENODEV;
}
-int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
- const char *dev_name, struct udevice **devp)
-{
- struct driver *drv;
- int ret;
-
- drv = lists_driver_lookup_name(drv_name);
- if (!drv) {
- printf(Cannot find driver '%s'\n, drv_name);
- return -ENOENT;
- }
- ret = device_bind(bus, drv, dev_name, NULL, -1, devp);
- if (ret) {
- printf(Cannot create device named '%s' (err=%d)\n,
- dev_name, ret);
- return ret;
- }
-
- return 0;
-}
-
int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
struct udevice **devp)
{
@@ -255,7 +234,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int
mode,
if (ret == -ENODEV drv_name) {
debug(%s: Binding new device '%s', busnum=%d, cs=%d,
driver=%s\n,
__func__, dev_name, busnum, cs, drv_name);
- ret = spi_bind_device(bus, cs, drv_name, dev_name, dev);
+ ret = device_bind_driver(bus, drv_name, dev_name, dev);
if (ret)
return ret;
created = true;
diff --git a/include/spi.h b/include/spi.h
index 5975cda..5b78271 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -544,20 +544,6 @@ int spi_chip_select(struct udevice *slave);
int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp);
/**
- * spi_bind_device() - bind a device to a bus's chip select
- *
- * This binds a new device to an given chip select (which must be unused).
- *
- * @bus: SPI bus to search
- * @cs:Chip select to attach to
- * @drv_name: Name of driver to attach to this chip select
- * @dev_name: Name of the new device thus created
- * @devp: Returns the newly bound device
- */
-int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
- const char *dev_name, struct udevice **devp);
-
-/**
* spi_ofdata_to_platdata() - decode standard SPI platform data
*
* This decodes the speed and mode from a device tree node and puts it into
--
2.1.0.rc2.206.gedb03e5
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
thanks!
--
Jagan.
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[U-Boot] [PATCH v2] ARM: tegra: Add support for norrin board
From: Allen Martin amar...@nvidia.com
Norrin (PM370) is a Tegra124 clamshell board that is very similar to
venice2, but it has a different panel, the sdcard cd and wp sense are
flipped, and it has a different revision of the AS3722 PMIC. This
board is also refered to as nyan in the ChromeOS trees.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB).
Signed-off-by: Allen Martin amar...@nvidia.com
Signed-off-by: Simon Glass s...@chromium.org
(rebase, fix pinmux that resets norrin)
---
Changes in v2:
- Rebase and adjust for Kconfig
- Fix up pinmux that reset norrin
- Add note as to the Chromebook's retail name, since it is now released
arch/arm/cpu/armv7/tegra124/Kconfig| 11 ++
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra124-norrin.dts | 92 +
board/nvidia/norrin/Kconfig| 24 +++
board/nvidia/norrin/MAINTAINERS| 6 +
board/nvidia/norrin/Makefile | 9 +
board/nvidia/norrin/norrin.c | 29 +++
board/nvidia/norrin/pinmux-config-norrin.h | 290 +
board/nvidia/venice2/as3722_init.h | 2 +-
configs/norrin_defconfig | 5 +
include/configs/norrin.h | 76
11 files changed, 544 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/tegra124-norrin.dts
create mode 100644 board/nvidia/norrin/Kconfig
create mode 100644 board/nvidia/norrin/MAINTAINERS
create mode 100644 board/nvidia/norrin/Makefile
create mode 100644 board/nvidia/norrin/norrin.c
create mode 100644 board/nvidia/norrin/pinmux-config-norrin.h
create mode 100644 configs/norrin_defconfig
create mode 100644 include/configs/norrin.h
diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig
b/arch/arm/cpu/armv7/tegra124/Kconfig
index 6a1c83a..db17819 100644
--- a/arch/arm/cpu/armv7/tegra124/Kconfig
+++ b/arch/arm/cpu/armv7/tegra124/Kconfig
@@ -6,6 +6,16 @@ choice
config TARGET_JETSON_TK1
bool NVIDIA Tegra124 Jetson TK1 board
+config TARGET_NORRIN
+ bool NVIDIA Tegra124 Norrin
+ help
+ Norrin (PM370) is a Tegra124 clamshell board that is very similar
+ to venice2, but it has a different panel, the sdcard CD and WP
+ sense are flipped, and it has a different revision of the AS3722
+ PMIC. This board is also refered to as nyan in the Chrome OS
+ trees. The retail name is the Acer Chromebook 13 CB5-311-T7NN
+ (13.3-inch HD, NVIDIA Tegra K1, 2GB).
+
config TARGET_VENICE2
bool NVIDIA Tegra124 Venice2
@@ -15,6 +25,7 @@ config SYS_SOC
default tegra124
source board/nvidia/jetson-tk1/Kconfig
+source board/nvidia/norrin/Kconfig
source board/nvidia/venice2/Kconfig
endif
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 52f8926..aa1e81a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
+ tegra124-norrin.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
diff --git a/arch/arm/dts/tegra124-norrin.dts b/arch/arm/dts/tegra124-norrin.dts
new file mode 100644
index 000..b07630c
--- /dev/null
+++ b/arch/arm/dts/tegra124-norrin.dts
@@ -0,0 +1,92 @@
+/dts-v1/;
+
+#include tegra124.dtsi
+
+/ {
+ model = NVIDIA Norrin;
+ compatible = nvidia,norrin, nvidia,tegra124;
+
+ aliases {
+ console = uarta;
+ i2c0 = /i2c@7000d000;
+ i2c1 = /i2c@7000c000;
+ i2c2 = /i2c@7000c400;
+ i2c3 = /i2c@7000c500;
+ i2c4 = /i2c@7000c700;
+ i2c5 = /i2c@7000d100;
+ sdhci0 = /sdhci@700b0600;
+ sdhci1 = /sdhci@700b0400;
+ spi0 = /spi@7000d400;
+ spi1 = /spi@7000da00;
+ usb0 = /usb@7d00;
+ usb1 = /usb@7d008000;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x8000 0x8000;
+ };
+
+ i2c@7000c000 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c400 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c500 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c700 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ i2c@7000d100 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ spi@7000d400 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
+ spi@7000da00 {
+ status =
[U-Boot] [PATCH v2 2/2] ARM: bcm: Enable bcm11130 boards
bcm11130 bcm11130_nand Signed-off-by: Steve Rae s...@broadcom.com --- Changes in v2: - split from previous commit board/broadcom/bcm11130/MAINTAINERS | 6 ++ board/broadcom/bcm11130_nand/MAINTAINERS | 6 ++ configs/bcm11130_defconfig | 3 +++ configs/bcm11130_nand_defconfig | 3 +++ 4 files changed, 18 insertions(+) create mode 100644 board/broadcom/bcm11130/MAINTAINERS create mode 100644 board/broadcom/bcm11130_nand/MAINTAINERS create mode 100644 configs/bcm11130_defconfig create mode 100644 configs/bcm11130_nand_defconfig diff --git a/board/broadcom/bcm11130/MAINTAINERS b/board/broadcom/bcm11130/MAINTAINERS new file mode 100644 index 000..b22e86f --- /dev/null +++ b/board/broadcom/bcm11130/MAINTAINERS @@ -0,0 +1,6 @@ +BCM11130 BOARD +M: Steve Rae s...@broadcom.com +S: Maintained +F: board/broadcom/bcm28155_ap/ +F: include/configs/bcm_ep_board.h +F: configs/bcm11130_defconfig diff --git a/board/broadcom/bcm11130_nand/MAINTAINERS b/board/broadcom/bcm11130_nand/MAINTAINERS new file mode 100644 index 000..881db5b --- /dev/null +++ b/board/broadcom/bcm11130_nand/MAINTAINERS @@ -0,0 +1,6 @@ +BCM11130_NAND BOARD +M: Steve Rae s...@broadcom.com +S: Maintained +F: board/broadcom/bcm28155_ap/ +F: include/configs/bcm_ep_board.h +F: configs/bcm11130_nand_defconfig diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig new file mode 100644 index 000..f8c9f03 --- /dev/null +++ b/configs/bcm11130_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS=SYS_MMC_ENV_DEV=0 +CONFIG_ARM=y +CONFIG_TARGET_BCM28155_AP=y diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig new file mode 100644 index 000..39cb709 --- /dev/null +++ b/configs/bcm11130_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS=NAND +CONFIG_ARM=y +CONFIG_TARGET_BCM28155_AP=y -- 1.8.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] ARM: bcm: Enable five Cygnus boards
bcm911360_entphn
bcm911360_entphn-ns
bcm911360k
bcm958300k-ns
bcm958305k
- updates to support Cygnus and NSP board families better
- add functions so CONFIG_ARMV7_NONSEC can be enabled on Cygnus boards
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v2:
- split into two commits
arch/arm/Kconfig | 12 ++--
board/broadcom/bcm911360_entphn-ns/MAINTAINERS | 6 ++
board/broadcom/bcm911360_entphn/MAINTAINERS | 6 ++
board/broadcom/bcm911360k/MAINTAINERS| 6 ++
board/broadcom/bcm958300k-ns/MAINTAINERS | 6 ++
board/broadcom/bcm958300k/MAINTAINERS| 4 ++--
board/broadcom/bcm958305k/MAINTAINERS| 6 ++
board/broadcom/bcm958622hr/MAINTAINERS | 4 ++--
board/broadcom/bcm_ep/board.c| 14 ++
board/broadcom/{bcm958300k = bcmcygnus}/Kconfig | 2 +-
board/broadcom/{bcm958622hr = bcmnsp}/Kconfig | 2 +-
configs/bcm911360_entphn-ns_defconfig| 3 +++
configs/bcm911360_entphn_defconfig | 3 +++
configs/bcm911360k_defconfig | 3 +++
configs/bcm958300k-ns_defconfig | 3 +++
configs/bcm958300k_defconfig | 4 ++--
configs/bcm958305k_defconfig | 3 +++
configs/bcm958622hr_defconfig| 2 +-
18 files changed, 74 insertions(+), 15 deletions(-)
create mode 100644 board/broadcom/bcm911360_entphn-ns/MAINTAINERS
create mode 100644 board/broadcom/bcm911360_entphn/MAINTAINERS
create mode 100644 board/broadcom/bcm911360k/MAINTAINERS
create mode 100644 board/broadcom/bcm958300k-ns/MAINTAINERS
create mode 100644 board/broadcom/bcm958305k/MAINTAINERS
rename board/broadcom/{bcm958300k = bcmcygnus}/Kconfig (88%)
rename board/broadcom/{bcm958622hr = bcmnsp}/Kconfig (88%)
create mode 100644 configs/bcm911360_entphn-ns_defconfig
create mode 100644 configs/bcm911360_entphn_defconfig
create mode 100644 configs/bcm911360k_defconfig
create mode 100644 configs/bcm958300k-ns_defconfig
create mode 100644 configs/bcm958305k_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22eb2d5..0da7068 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -508,12 +508,12 @@ config TARGET_BCM28155_AP
bool Support bcm28155_ap
select CPU_V7
-config TARGET_BCM958300K
- bool Support bcm958300k
+config TARGET_BCMCYGNUS
+ bool Support bcmcygnus
select CPU_V7
-config TARGET_BCM958622HR
- bool Support bcm958622hr
+config TARGET_BCMNSP
+ bool Support bcmnsp
select CPU_V7
config ARCH_EXYNOS
@@ -842,8 +842,8 @@ source board/bluegiga/apx4devkit/Kconfig
source board/bluewater/snapper9260/Kconfig
source board/boundary/nitrogen6x/Kconfig
source board/broadcom/bcm28155_ap/Kconfig
-source board/broadcom/bcm958300k/Kconfig
-source board/broadcom/bcm958622hr/Kconfig
+source board/broadcom/bcmcygnus/Kconfig
+source board/broadcom/bcmnsp/Kconfig
source board/calao/sbc35_a9g20/Kconfig
source board/calao/tny_a9260/Kconfig
source board/calao/usb_a9263/Kconfig
diff --git a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
new file mode 100644
index 000..b5f0207
--- /dev/null
+++ b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360_ENTPHN-NS BOARD
+M: Steve Rae s...@broadcom.com
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360_entphn-ns_defconfig
diff --git a/board/broadcom/bcm911360_entphn/MAINTAINERS
b/board/broadcom/bcm911360_entphn/MAINTAINERS
new file mode 100644
index 000..fb7ee2b
--- /dev/null
+++ b/board/broadcom/bcm911360_entphn/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360_ENTPHN BOARD
+M: Steve Rae s...@broadcom.com
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360_entphn_defconfig
diff --git a/board/broadcom/bcm911360k/MAINTAINERS
b/board/broadcom/bcm911360k/MAINTAINERS
new file mode 100644
index 000..754a15f
--- /dev/null
+++ b/board/broadcom/bcm911360k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360K BOARD
+M: Steve Rae s...@broadcom.com
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360k_defconfig
diff --git a/board/broadcom/bcm958300k-ns/MAINTAINERS
b/board/broadcom/bcm958300k-ns/MAINTAINERS
new file mode 100644
index 000..763401a
--- /dev/null
+++ b/board/broadcom/bcm958300k-ns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958300K-NS BOARD
+M: Steve Rae s...@broadcom.com
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958300k-ns_defconfig
diff --git a/board/broadcom/bcm958300k/MAINTAINERS
b/board/broadcom/bcm958300k/MAINTAINERS
index f75ee6e..8afc728 100644
--- a/board/broadcom/bcm958300k/MAINTAINERS
+++ b/board/broadcom/bcm958300k/MAINTAINERS
[U-Boot] [PATCH 2/2] sandbox: Fix warnings in cpu.c and os.c
This fixes the following two problems:
cppcheck reports:
[arch/sandbox/cpu/start.c:132]: (error) Uninitialized variable: err
[arch/sandbox/cpu/os.c:371]: (error) Memory leak: fname
Signed-off-by: Simon Glass s...@chromium.org
Reported-by: Wolfgang Denk w...@denx.de
---
arch/sandbox/cpu/os.c| 1 +
arch/sandbox/cpu/start.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 1c4aa3f..f572cae 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -367,6 +367,7 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node
**headp)
done:
closedir(dir);
+ free(fname);
return ret;
}
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 53a99ae..656bd75 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -130,7 +130,8 @@ static int sandbox_cmdline_cb_memory(struct sandbox_state
*state,
state-write_ram_buf = true;
state-ram_buf_fname = arg;
- if (os_read_ram_buf(arg)) {
+ err = os_read_ram_buf(arg);
+ if (err) {
printf(Failed to read RAM buffer\n);
return err;
}
--
2.1.0.rc2.206.gedb03e5
___
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