Re: [U-Boot] [PATCH v2 1/2] ns16550: replace with binding files from Linux kernel

[Thomas Chou]

On 2015年12月15日 01:03, Stephen Warren wrote:

On 12/14/2015 05:45 AM, Thomas Chou wrote:

Replace ns16550.txt with binding files from Linux kernel. As suggested
by Stephen Warren, we should keep the directory structure, filenames,
and file content identical to the bindings in the Linux kernel.


Acked-by: Stephen Warren 

(I assume that the new files are identical to the kernel versions,
although I didn't validate this)



Yes, they are exactly identical to the kernel versions.


(Or, I'd give my ack to simply deleting doc/device-tree-bindings/ so the
redundant copy doesn't have to be maintained).



Best regards,
Thomas
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Re: [U-Boot] [PATCH 2/5] usb: dwc2: Use shared wait_for_bit

[Marek Vasut]

On Tuesday, December 15, 2015 at 01:09:24 AM, Mateusz Kulikowski wrote:
> Use existing library function to poll bit(s).
> Update configs using dwc2.
> 
> Signed-off-by: Mateusz Kulikowski 
> ---

[...]

> diff --git a/include/configs/hikey.h b/include/configs/hikey.h
> index 796861e..4e3bfec 100644
> --- a/include/configs/hikey.h
> +++ b/include/configs/hikey.h
> @@ -66,6 +66,7 @@
> 
>  #define CONFIG_CMD_USB
>  #ifdef CONFIG_CMD_USB
> +#define CONFIG_LIB_WAIT_BIT

Just enable this stuff by default (ie. dont introduce new config option,
just use obj-y in lib/Makefile). The compiler will throw the function away
if it's not used.

>  #define CONFIG_USB_DWC2
>  #define CONFIG_USB_DWC2_REG_ADDR 0xF72C
>  /*#define CONFIG_DWC2_DFLT_SPEED_FULL*/

[...]

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 5/5] move erratum a008336 and a008514 to soc specific file

[York Sun]

On 12/05/2015 02:59 PM, Yuan Yao wrote:
> As the errata A008336 and A008514 do not apply to all LS series SoCs
> (such as LS1021A, LS1043A) we move them to an soc specific file
> 
> Signed-off-by: Yuan Yao 
> ---
> Changed in v3:
>   Fix a typo issue.
>   In function "erratum_a008514"
>   "#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR" should be
>   "#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR"
> Changed in v2:
>   Update the patch commit message.
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

[York Sun]

On 12/05/2015 02:59 PM, Yuan Yao wrote:
> This is a workaround for hardware erratum.
> Write the value of 63b2_0042h to EDDRTQCFG will optimal the
> memory controller performance.
> 
> The value: 63b2_0042h comes from the hardware team.
> 
> Signed-off-by: Yuan Yao 
> ---
> Changed in v2:
>   Update the write value to 63b2_0042h;
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Chin Liang See]

On Tue, 2015-12-15 at 01:32 +0100, Marek Vasut wrote:
> On Monday, December 14, 2015 at 04:22:57 PM, Chin Liang See wrote:
> > On Mon, 2015-12-14 at 02:25 +0100, Marek Vasut wrote:
> > > On Monday, December 14, 2015 at 02:22:32 AM, Chin Liang See 
> > > wrote:

[...]

> > 
> > Yeah, I can successfully mounted with ubifs :)
> > 
> > Just that I still have the issue with U-Boot ubifsmount although I
> > already applied the patch for cache ARMV7. I will take a look into
> > ubi
> > code as I suspect its due to eraseblock size issue.
> 
> Keep looking, good luck.

Yup, will compare the UBI code with the Linux one.

> 
> The armv7 cache issue is more serious than I thought, I am starting
> to suspect
> there is some problem with the L3 interconnect, but I cannot put my
> finger on
> it yet.

Hmmm... I can try to help. 

FYI, I was trying to understand how the code error in cache-cp15 will
cause the misbehave. One thing I am suspecting it might due to mismatch
of cache policy for the memory that store the page table and
translation page walk mechanism. But with your fix, it should be good
as they are matching now.

Thanks
Chin Liang


> 
> Best regards,
> Marek Vasut
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[U-Boot] [PATCH 1/5] lib: Add wait_for_bit

[Mateusz Kulikowski]

Add function to poll register waiting for specific bit(s).
Similar functions are implemented in few drivers - they are almost
identical and can be generalized.
Signed-off-by: Mateusz Kulikowski 
---

 include/wait_bit.h | 34 ++
 lib/Kconfig|  4 
 lib/Makefile   |  1 +
 lib/wait_bit.c | 44 
 4 files changed, 83 insertions(+)
 create mode 100644 include/wait_bit.h
 create mode 100644 lib/wait_bit.c

diff --git a/include/wait_bit.h b/include/wait_bit.h
new file mode 100644
index 000..7dbfa1a
--- /dev/null
+++ b/include/wait_bit.h
@@ -0,0 +1,34 @@
+/*
+ * Wait for bit with timeout and ctrlc
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __WAIT_BIT_H
+#define __WAIT_BIT_H
+
+/**
+ * wait_for_bit()  waits for bit set/cleared in register
+ *
+ * Function polls register waiting for specific bit(s) change
+ * (either 0->1 or 1->0). It can fail under two conditions:
+ * - Timeout
+ * - User interaction (CTRL-C)
+ * Function succeeds only if all bits of masked register are set/cleared
+ * (depending on set option).
+ *
+ * @param prefix   Prefix added to timeout messagge (message visible only
+ * with debug enabled)
+ * @param reg  Register that will be read (using readl())
+ * @param mask Bit(s) of register that must be active
+ * @param set  Selects wait condition (bit set or clear)
+ * @param timeout  Timeout (in miliseconds)
+ * @param breakableEnables CTRL-C interruption
+ * @return 0 on success, -ETIMEDOUT or -EINTR on failure
+ */
+int wait_for_bit(const char *prefix, u32 *reg, const u32 mask, bool set,
+unsigned int timeout, bool breakable);
+
+#endif
diff --git a/lib/Kconfig b/lib/Kconfig
index 9d580e4..5977fc6 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -137,6 +137,10 @@ config ERRNO_STR
  - if errno is null or positive number - a pointer to "Success" message
  - if errno is negative - a pointer to errno related message
 
+config LIB_WAIT_BIT
+   bool
+   default n
+
 source lib/efi/Kconfig
 
 endmenu
diff --git a/lib/Makefile b/lib/Makefile
index 1f1ff6f..437f937 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -81,6 +81,7 @@ obj-y += time.o
 obj-$(CONFIG_TRACE) += trace.o
 obj-$(CONFIG_LIB_UUID) += uuid.o
 obj-$(CONFIG_LIB_RAND) += rand.o
+obj-$(CONFIG_LIB_WAIT_BIT) += wait_bit.o
 
 ifdef CONFIG_SPL_BUILD
 # SPL U-Boot may use full-printf, tiny-printf or none at all
diff --git a/lib/wait_bit.c b/lib/wait_bit.c
new file mode 100644
index 000..3c78eac
--- /dev/null
+++ b/lib/wait_bit.c
@@ -0,0 +1,44 @@
+/*
+ * Wait for bit interruptible by timeout or ctrlc
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int wait_for_bit(const char *prefix, u32 *reg, const u32 mask, bool set,
+unsigned int timeout, bool breakable)
+{
+   u32 val;
+   unsigned long start = get_timer(0);
+
+   while (1) {
+   val = readl(reg);
+
+   if (!set)
+   val = ~val;
+
+   if ((val & mask) == mask)
+   return 0;
+
+   if (get_timer(start) > timeout)
+   break;
+
+   if (breakable && ctrlc()) {
+   puts("Abort\n");
+   return -EINTR;
+   }
+
+   udelay(1);
+   }
+
+   debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg, mask,
+ set);
+
+   return -ETIMEDOUT;
+}
-- 
2.5.0

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[U-Boot] [PATCH 3/5] usb: ohci-lpc32xx: Use shared wait_for_bit

[Mateusz Kulikowski]

Use existing library function to poll bit(s).
No config files are updated, as there is no board using this driver.

Signed-off-by: Mateusz Kulikowski 
---

 drivers/usb/host/ohci-lpc32xx.c | 36 ++--
 1 file changed, 10 insertions(+), 26 deletions(-)

diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index 48d338e..1101f6f 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -10,6 +10,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -80,29 +81,9 @@ struct otg_regs {
 static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
 static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
 
-static int wait_for_bit(void *reg, const u32 mask, bool set)
-{
-   u32 val;
-   unsigned long start = get_timer(0);
-
-   while (1) {
-   val = readl(reg);
-   if (!set)
-   val = ~val;
-
-   if ((val & mask) == mask)
-   return 0;
-
-   if (get_timer(start) > CONFIG_SYS_HZ)
-   break;
-
-   udelay(1);
-   }
-
-   error("Timeout (reg=%p mask=%08x wait_set=%i)\n", reg, mask, set);
-
-   return -ETIMEDOUT;
-}
+#ifndef CONFIG_LIB_WAIT_BIT
+#error CONFIG_LIB_WAIT_BIT is required for ohci-lpc32xx driver
+#endif
 
 static int isp1301_set_value(int reg, u8 value)
 {
@@ -158,7 +139,8 @@ static int usbpll_setup(void)
setbits_le32(_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01));
setbits_le32(_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP);
 
-   ret = wait_for_bit(_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS, 1);
+   ret = wait_for_bit(__func__, _pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
+  true, CONFIG_SYS_HZ, false);
if (ret)
return ret;
 
@@ -183,7 +165,8 @@ int usb_cpu_init(void)
 
/* enable I2C clock */
writel(OTG_CLK_I2C_EN, >otg_clk_ctrl);
-   ret = wait_for_bit(>otg_clk_sts, OTG_CLK_I2C_EN, 1);
+   ret = wait_for_bit(__func__, >otg_clk_sts, OTG_CLK_I2C_EN, true,
+  CONFIG_SYS_HZ, false);
if (ret)
return ret;
 
@@ -203,7 +186,8 @@ int usb_cpu_init(void)
 OTG_CLK_I2C_EN | OTG_CLK_HOST_EN;
writel(mask, >otg_clk_ctrl);
 
-   ret = wait_for_bit(>otg_clk_sts, mask, 1);
+   ret = wait_for_bit(__func__, >otg_clk_sts, mask, true,
+  CONFIG_SYS_HZ, false);
if (ret)
return ret;
 
-- 
2.5.0

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[U-Boot] [PATCH 0/5] Add wait_for_bit()

[Mateusz Kulikowski]

This series add generic function to poll register waiting for
one or more bits to change.

Very similar function was used in several drivers:
- dwc2
- ohci-lp32xx
- ehci-mx6
- zynq_gem

First patch adds function, following patches update drivers and
board config files / defconfigs.

This series was compile-tested with buildman for ~50 boards
(most or even all boards affected by change)

Code was also run-tested on ehci-msm driver (not yet in mainline)

There is single difference in behavior: ohci-lp32xx driver will
not print "Timeout..." message with debug disabled.
I think it's not a big issue as this driver seems unused, but
if it's an issue - please drop that patch.


Mateusz Kulikowski (5):
  lib: Add wait_for_bit
  usb: dwc2: Use shared wait_for_bit
  usb: ohci-lpc32xx: Use shared wait_for_bit
  usb: ehci-mx6: Use shared wait_for_bit
  net: zynq_gem: Use shared wait_for_bit

 drivers/net/Kconfig   |  1 +
 drivers/net/zynq_gem.c| 35 ++--
 drivers/usb/host/dwc2.c   | 43 +-
 drivers/usb/host/ehci-mx6.c   | 37 +++--
 drivers/usb/host/ohci-lpc32xx.c   | 36 
 include/configs/aristainetos-common.h |  1 +
 include/configs/cgtqmx6eval.h |  1 +
 include/configs/embestmx6boards.h |  1 +
 include/configs/gw_ventana.h  |  1 +
 include/configs/hikey.h   |  1 +
 include/configs/mx6cuboxi.h   |  1 +
 include/configs/mx6qarm2.h|  1 +
 include/configs/mx6qsabreauto.h   |  1 +
 include/configs/mx6sabresd.h  |  1 +
 include/configs/mx6slevk.h|  1 +
 include/configs/mx6sxsabresd.h|  1 +
 include/configs/mx6ul_14x14_evk.h |  1 +
 include/configs/nitrogen6x.h  |  1 +
 include/configs/novena.h  |  1 +
 include/configs/ot1200.h  |  1 +
 include/configs/platinum.h|  1 +
 include/configs/rpi-common.h  |  1 +
 include/configs/socfpga_common.h  |  1 +
 include/configs/tbs2910.h |  1 +
 include/configs/titanium.h|  1 +
 include/configs/tqma6.h   |  1 +
 include/configs/wandboard.h   |  1 +
 include/configs/warp.h|  1 +
 include/wait_bit.h| 34 +++
 lib/Kconfig   |  4 
 lib/Makefile  |  1 +
 lib/wait_bit.c| 44 +++
 32 files changed, 144 insertions(+), 114 deletions(-)
 create mode 100644 include/wait_bit.h
 create mode 100644 lib/wait_bit.c

-- 
2.5.0

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[U-Boot] [PATCH 2/5] usb: dwc2: Use shared wait_for_bit

[Mateusz Kulikowski]

Use existing library function to poll bit(s).
Update configs using dwc2.

Signed-off-by: Mateusz Kulikowski 
---

 drivers/usb/host/dwc2.c  | 43 +++-
 include/configs/hikey.h  |  1 +
 include/configs/rpi-common.h |  1 +
 include/configs/socfpga_common.h |  1 +
 4 files changed, 19 insertions(+), 27 deletions(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 541c0f9..d1c9c45 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "dwc2.h"
@@ -52,27 +53,10 @@ static struct dwc2_priv local;
 /*
  * DWC2 IP interface
  */
-static int wait_for_bit(void *reg, const uint32_t mask, bool set)
-{
-   unsigned int timeout = 100;
-   uint32_t val;
-
-   while (--timeout) {
-   val = readl(reg);
-   if (!set)
-   val = ~val;
-
-   if ((val & mask) == mask)
-   return 0;
-
-   udelay(1);
-   }
-
-   debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
- __func__, reg, mask, set);
 
-   return -ETIMEDOUT;
-}
+#ifndef CONFIG_LIB_WAIT_BIT
+#error CONFIG_LIB_WAIT_BIT is required for dwc2 driver
+#endif
 
 /*
  * Initializes the FSLSPClkSel field of the HCFG register
@@ -117,7 +101,8 @@ static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs 
*regs, const int num)
 
writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
   >grstctl);
-   ret = wait_for_bit(>grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
+   ret = wait_for_bit(__func__, >grstctl, DWC2_GRSTCTL_TXFFLSH,
+  false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
 
@@ -135,7 +120,8 @@ static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs 
*regs)
int ret;
 
writel(DWC2_GRSTCTL_RXFFLSH, >grstctl);
-   ret = wait_for_bit(>grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
+   ret = wait_for_bit(__func__, >grstctl, DWC2_GRSTCTL_RXFFLSH,
+  false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
 
@@ -152,13 +138,15 @@ static void dwc_otg_core_reset(struct dwc2_core_regs 
*regs)
int ret;
 
/* Wait for AHB master IDLE state. */
-   ret = wait_for_bit(>grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
+   ret = wait_for_bit(__func__, >grstctl, DWC2_GRSTCTL_AHBIDLE,
+  true, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
 
/* Core Soft Reset */
writel(DWC2_GRSTCTL_CSFTRST, >grstctl);
-   ret = wait_for_bit(>grstctl, DWC2_GRSTCTL_CSFTRST, 0);
+   ret = wait_for_bit(__func__, >grstctl, DWC2_GRSTCTL_CSFTRST,
+  false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
 
@@ -243,8 +231,8 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs 
*regs)
clrsetbits_le32(>hc_regs[i].hcchar,
DWC2_HCCHAR_EPDIR,
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
-   ret = wait_for_bit(>hc_regs[i].hcchar,
-  DWC2_HCCHAR_CHEN, 0);
+   ret = wait_for_bit(__func__, >hc_regs[i].hcchar,
+  DWC2_HCCHAR_CHEN, false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
}
@@ -737,7 +725,8 @@ int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t 
*sub, int *toggle,
int ret;
uint32_t hcint, hctsiz;
 
-   ret = wait_for_bit(_regs->hcint, DWC2_HCINT_CHHLTD, true);
+   ret = wait_for_bit(__func__, _regs->hcint, DWC2_HCINT_CHHLTD, true,
+  1000, false);
if (ret)
return ret;
 
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 796861e..4e3bfec 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -66,6 +66,7 @@
 
 #define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
+#define CONFIG_LIB_WAIT_BIT
 #define CONFIG_USB_DWC2
 #define CONFIG_USB_DWC2_REG_ADDR 0xF72C
 /*#define CONFIG_DWC2_DFLT_SPEED_FULL*/
diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 1b83eb3..70d6123 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -78,6 +78,7 @@
 
 #define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
+#define CONFIG_LIB_WAIT_BIT
 #define CONFIG_USB_DWC2
 #ifdef CONFIG_BCM2836
 #define CONFIG_USB_DWC2_REG_ADDR 0x3f98
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index b3f65b6..47062cd 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -227,6 +227,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * USB
  */
 #ifdef CONFIG_CMD_USB
+#define 

Re: [U-Boot] [PATCH] eeprom: fix eeprom write procedure

[Marek Vasut]

On Monday, December 14, 2015 at 04:45:34 PM, Alexey Brodkin wrote:
> This fixes commit 1a37889b0ad084a740b4f785031d7ae9955d947b:
> --->8
> eeprom: Pull out the RW loop
> 
> Unify the code for doing read/write into single function, since the
> code for both the read and write is almost identical. This again
> trims down the code duplication.
> --->8
> 
> where the same one routine is utilized for both EEPROM writing and
> reading. The only difference was supposed to be a "read" flag which
> in both cases was set with 1 somehow.
> 
> That lead to a missing delay in case of writing which lead to write
> failure (in my case no data was written).
> 
> Signed-off-by: Alexey Brodkin 
> Cc: Marek Vasut 
> Cc: Simon Glass 
> Cc: Tom Rini 
> Cc: Heiko Schocher 

Obviously correct,

Acked-by: Marek Vasut 

Thanks for spotting this, nice!

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 3/3] fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

[York Sun]

On 11/20/2015 03:52 PM, Shengzhou Liu wrote:
> DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
> T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
> LS102x Rev2.
> 
> Signed-off-by: Shengzhou Liu 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York

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Re: [U-Boot] [PATCH] Enable console log from earlyconsole in Linux bootargs

[York Sun]

On 10/31/2015 06:20 PM, Pratiyush Mohan Srivastava wrote:
> Remove 115200 from "earlycon" to avoid loss of initial
> log messages during linux kernel 4.1  bootup
> 
> Signed-off-by: Pratiyush Mohan Srivastava 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York

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Re: [U-Boot] [PATCH 2/5] arm: ls102xa: enable all the snoop signal for masters.

[York Sun]

On 12/05/2015 02:59 PM, Yuan Yao wrote:
> Enable the IP feature's snoop signal to support
> hardware snoop for cache coherence.
> 
> SNPCNFGCR contains the bits to drive snoop signal
> for various masters.
> 
> Signed-off-by: Yuan Yao 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York
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[U-Boot] Please pull u-boot-fsl-qoriq master

[York Sun]

Tom,

The following changes since commit 5076c64a08d2083af5a7761b12a30116ef0da967:

  Merge branch 'master' of git://git.denx.de/u-boot-spi (2015-12-11 15:07:44 
-0500)

are available in the git repository at:


  git://git.denx.de/u-boot-fsl-qoriq.git master

for you to fetch changes up to 989c5f0a8f8694ac92eb0d6cff8745ae8659364f:

  armv8: Add sata support on Layerscape ARMv8 board (2015-12-15 08:57:35 +0800)


Alexander Stein (1):
  fsl_qspi: Pet the watchdog while reading/writing

Aneesh Bansal (5):
  armv8: define usec2ticks function
  armv8: Make SEC read/write as snoopable for LS1043
  include/linux: move typdef for uintptr_t
  armv8/ls1043ardb: add SECURE BOOT target for NOR
  drivers/crypto/fsl: fix endianness issue in RNG

Pratiyush Mohan Srivastava (1):
  Enable console log from earlyconsole in Linux bootargs

Shaohui Xie (2):
  freescale: fman: make sure phy-handle property is big endian
  armv8/ls1043ardb: Add support for >2GB memory

Shengzhou Liu (3):
  arm: ls102x: add get_svr and IS_SVR_REV helper
  fsl/errata: move fsl_errata.h to common directory
  fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

Tang Yuantian (1):
  armv8: Add sata support on Layerscape ARMv8 board

Tom Rini (2):
  fsl_*_serdes.c: Modify memset call in serdes_init
  qbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submit

Yao Yuan (5):
  arm: ls1021a: merge SoC specific code in a separate file
  arm: ls102xa: enable all the snoop signal for masters.
  armv7: ls102xa: cci-400: Enable snoop and DVM message requests.
  armv7/fsl-ls102xa: Workaround for DDR erratum A008514
  move erratum a008336 and a008514 to soc specific file

York Sun (11):
  driver/ddr/fsl: Update DDR4 RTT values
  driver/ddr/fsl: Update DDR4 MR6 for Vref range
  driver/ddr/fsl: Update MR5 RTT park
  driver/ddr/fsl: Update workaround for A008511 for vref range
  driver/ddr/fsl: Update timing config for heavy load
  armv8/ls2080aqds: Update DDR settings for four chip-select case
  armv8/ls2080ardb: Update DDR settings for four chip-select case
  Reserve secure memory
  armv8: fsl-layerscape: Make DDR non secure in MMU tables
  common: Rewrite hiding the end of memory
  armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server

 README |   14 +-
 arch/arm/cpu/armv7/ls102xa/Makefile|1 +
 arch/arm/cpu/armv7/ls102xa/cpu.c   |8 +
 arch/arm/cpu/armv7/ls102xa/soc.c   |   90 
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  142 ++--
 .../cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c|2 +-
 .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|2 +-
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   85 +++
 arch/arm/cpu/armv8/generic_timer.c |   11 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |   14 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   14 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |2 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   31 +++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h  |   13 +-
 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h|   12 +
 arch/arm/include/asm/fsl_secure_boot.h |6 +-
 arch/powerpc/cpu/mpc85xx/cmd_errata.c  |2 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c|2 +-
 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c |4 +-
 arch/powerpc/include/asm/config_mpc85xx.h  |2 +
 board/freescale/common/fman.c  |2 +
 board/freescale/common/fsl_validate.c  |   34 ++-
 board/freescale/ls1021aqds/ls1021aqds.c|   49 +---
 board/freescale/ls1021atwr/ls1021atwr.c|   42 +---
 board/freescale/ls1043aqds/ddr.c   |9 +
 board/freescale/ls1043ardb/MAINTAINERS |5 +
 board/freescale/ls1043ardb/ddr.c   |   24 +-
 board/freescale/ls1043ardb/ls1043ardb.c|   28 ++-
 board/freescale/ls2080a/ddr.c  |   15 ++
 board/freescale/ls2080a/ls2080a.c  |   17 --
 board/freescale/ls2080aqds/ddr.c   |   31 ++-
 board/freescale/ls2080aqds/ls2080aqds.c|   17 --
 board/freescale/ls2080ardb/ddr.c   |   31 ++-
 board/freescale/ls2080ardb/ls2080ardb.c|   17 --
 common/board_f.c   |   32 ++-
 common/cmd_bdinfo.c|6 +
 common/cmd_blob.c  |6 +-
 configs/ls1043ardb_SECURE_BOOT_defconfig   |9 +
 drivers/crypto/fsl/jr.c|8 +-
 drivers/ddr/fsl/ctrl_regs.c|   48 +++-

[U-Boot] [PATCH 4/5] usb: ehci-mx6: Use shared wait_for_bit

[Mateusz Kulikowski]

Use existing library function to poll bit(s).
Update configs using ehci-mx6.

Signed-off-by: Mateusz Kulikowski 
---

 drivers/usb/host/ehci-mx6.c   | 37 +--
 include/configs/aristainetos-common.h |  1 +
 include/configs/cgtqmx6eval.h |  1 +
 include/configs/embestmx6boards.h |  1 +
 include/configs/gw_ventana.h  |  1 +
 include/configs/mx6cuboxi.h   |  1 +
 include/configs/mx6qarm2.h|  1 +
 include/configs/mx6qsabreauto.h   |  1 +
 include/configs/mx6sabresd.h  |  1 +
 include/configs/mx6slevk.h|  1 +
 include/configs/mx6sxsabresd.h|  1 +
 include/configs/mx6ul_14x14_evk.h |  1 +
 include/configs/nitrogen6x.h  |  1 +
 include/configs/novena.h  |  1 +
 include/configs/ot1200.h  |  1 +
 include/configs/platinum.h|  1 +
 include/configs/tbs2910.h |  1 +
 include/configs/titanium.h|  1 +
 include/configs/tqma6.h   |  1 +
 include/configs/wandboard.h   |  1 +
 include/configs/warp.h|  1 +
 21 files changed, 29 insertions(+), 28 deletions(-)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 2666351..ed269be 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -57,6 +58,11 @@
 #define UCMD_RESET (1 << 1) /* controller reset */
 
 #if defined(CONFIG_MX6)
+
+#ifndef CONFIG_LIB_WAIT_BIT
+#error CONFIG_LIB_WAIT_BIT is required for ehci-mx6 driver
+#endif
+
 static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
USB_PHY1_BASE_ADDR,
@@ -117,32 +123,6 @@ static void usb_power_config(int index)
 pll_480_ctrl_set);
 }
 
-static int wait_for_bit(u32 *reg, const u32 mask, bool set)
-{
-   u32 val;
-   const unsigned int timeout = 1;
-   unsigned long start = get_timer(0);
-
-   while(1) {
-   val = readl(reg);
-   if (!set)
-   val = ~val;
-
-   if ((val & mask) == mask)
-   return 0;
-
-   if (get_timer(start) > timeout)
-   break;
-
-   udelay(1);
-   }
-
-   debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
-   __func__, reg, mask, set);
-
-   return -ETIMEDOUT;
-}
-
 /* Return 0 : host node, <>0 : device mode */
 static int usb_phy_enable(int index, struct usb_ehci *ehci)
 {
@@ -160,12 +140,13 @@ static int usb_phy_enable(int index, struct usb_ehci 
*ehci)
 
/* Stop then Reset */
clrbits_le32(usb_cmd, UCMD_RUN_STOP);
-   ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0);
+   ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 1,
+  false);
if (ret)
return ret;
 
setbits_le32(usb_cmd, UCMD_RESET);
-   ret = wait_for_bit(usb_cmd, UCMD_RESET, 0);
+   ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 1, false);
if (ret)
return ret;
 
diff --git a/include/configs/aristainetos-common.h 
b/include/configs/aristainetos-common.h
index 0b97ccc..c97c352 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -218,6 +218,7 @@
 /* USB Configs */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
+#define CONFIG_LIB_WAIT_BIT
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 487c011..380e1c8 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -75,6 +75,7 @@
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
 #define CONFIG_USB_EHCI
+#define CONFIG_LIB_WAIT_BIT
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/embestmx6boards.h 
b/include/configs/embestmx6boards.h
index 90cd959..feaa78e 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -41,6 +41,7 @@
 /* USB Configs */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
+#define CONFIG_LIB_WAIT_BIT
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index b7b9c78..b672aab 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -178,6 +178,7 @@
 /* USB Configs */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
+#define CONFIG_LIB_WAIT_BIT
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 4feb121..8363b27 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -58,6 +58,7 

[U-Boot] [PATCH 5/5] net: zynq_gem: Use shared wait_for_bit

[Mateusz Kulikowski]

Use existing library function to poll bit(s).
Signed-off-by: Mateusz Kulikowski 
---

 drivers/net/Kconfig|  1 +
 drivers/net/zynq_gem.c | 35 ++-
 2 files changed, 3 insertions(+), 33 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6905cc0..890e6c1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -103,6 +103,7 @@ config PCH_GBE
 
 config ZYNQ_GEM
depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP)
+   select LIB_WAIT_BIT
bool "Xilinx Ethernet GEM"
help
  This MAC is presetn in Xilinx Zynq and ZynqMP SoCs.
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 0a41281..430c2a4 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -452,38 +453,6 @@ static int zynq_gem_init(struct udevice *dev)
return 0;
 }
 
-static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
-   bool set, unsigned int timeout)
-{
-   u32 val;
-   unsigned long start = get_timer(0);
-
-   while (1) {
-   val = readl(reg);
-
-   if (!set)
-   val = ~val;
-
-   if ((val & mask) == mask)
-   return 0;
-
-   if (get_timer(start) > timeout)
-   break;
-
-   if (ctrlc()) {
-   puts("Abort\n");
-   return -EINTR;
-   }
-
-   udelay(1);
-   }
-
-   debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
- func, reg, mask, set);
-
-   return -ETIMEDOUT;
-}
-
 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 {
u32 addr, size;
@@ -525,7 +494,7 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, 
int len)
printf("TX buffers exhausted in mid frame\n");
 
return wait_for_bit(__func__, >txsr, ZYNQ_GEM_TSR_DONE,
-   true, 2);
+   true, 2, true);
 }
 
 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
-- 
2.5.0

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Re: [U-Boot] [PATCH 1/5] lib: Add wait_for_bit

[Marek Vasut]

On Tuesday, December 15, 2015 at 01:09:23 AM, Mateusz Kulikowski wrote:
> Add function to poll register waiting for specific bit(s).
> Similar functions are implemented in few drivers - they are almost
> identical and can be generalized.
> Signed-off-by: Mateusz Kulikowski 
> ---

Excellent !

>  include/wait_bit.h | 34 ++
>  lib/Kconfig|  4 
>  lib/Makefile   |  1 +
>  lib/wait_bit.c | 44 
>  4 files changed, 83 insertions(+)
>  create mode 100644 include/wait_bit.h
>  create mode 100644 lib/wait_bit.c

[...]

> +int wait_for_bit(const char *prefix,

const u32 *

> u32 *reg, const u32 mask,

const bool, const unsigned int , const bool ;-)

> bool set,
> +  unsigned int timeout, bool breakable)

> +{
> + u32 val;
> + unsigned long start = get_timer(0);
> +
> + while (1) {
> + val = readl(reg);
> +
> + if (!set)
> + val = ~val;
> +
> + if ((val & mask) == mask)
> + return 0;
> +
> + if (get_timer(start) > timeout)
> + break;
> +
> + if (breakable && ctrlc()) {
> + puts("Abort\n");
> + return -EINTR;
> + }
> +
> + udelay(1);
> + }
> +
> + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg, mask,
> +   set);
> +
> + return -ETIMEDOUT;
> +}

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

[York Sun]

On 11/05/2015 02:03 AM, York Sun wrote:
> This patch set revises the DDR driver to support higher speed for DDR4
> under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
> Single quad-rank DIMM is not supported yet.
> 
> 
> York Sun (7):
>   driver/ddr/fsl: Update DDR4 RTT values
>   driver/ddr/fsl: Update DDR4 MR6 for Vref range
>   driver/ddr/fsl: Update MR5 RTT park
>   driver/ddr/fsl: Update workaround for A008511 for vref range
>   driver/ddr/fsl: Update timing config for heavy load
>   armv8/ls2085aqds: Update DDR settings for four chip-select case
>   armv8/ls2085ardb: Update DDR settings for four chip-select case
> 
>  board/freescale/ls2085aqds/ddr.c |   16 ++-
>  board/freescale/ls2085ardb/ddr.c |   16 ++-
>  drivers/ddr/fsl/ctrl_regs.c  |   48 +++-
>  drivers/ddr/fsl/fsl_ddr_gen4.c   |   22 ++--
>  drivers/ddr/fsl/options.c|  237 
> +-
>  include/fsl_ddr_sdram.h  |9 ++
>  6 files changed, 325 insertions(+), 23 deletions(-)
> 

Changed subject from ls2085a to ls2080a.
Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH] freescale: fman: make sure phy-handle property is big endian

[York Sun]

On 11/10/2015 07:20 PM, shh@gmail.com wrote:
> From: Shaohui Xie 
> 
> When creating phy-handle property, an unsigned int value is created by
> fdt_create_phandle, and memcpy is used to get the value, since DTS is
> big endian, the value cannot be used directly on little endian SoCs,
> it should be converted by cpu_to_fdt32.
> 
> Signed-off-by: Shaohui Xie 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York

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Re: [U-Boot] [PATCH 1/5] arm: ls1021a: merge SoC specific code in a separate file

[York Sun]

On 12/05/2015 02:59 PM, Yuan Yao wrote:
> Create a soc.c file to put the code for soc special settings.
> 
> Signed-off-by: Yuan Yao 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York
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[U-Boot] [PATCH 2/5] nios2: Up the monitor size to 512kiB

[Marek Vasut]

The monitor is growing much larger with various additions, like fitImage,
command line completion, UBI etc. Make the monitor area larger so these
features can be safely added.

Signed-off-by: Marek Vasut 
Cc: Thomas Chou 
---
 include/configs/10m50_devboard.h | 2 +-
 include/configs/3c120_devboard.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index c99177c..68ef6e5 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -63,7 +63,7 @@
 #define CONFIG_SYS_SDRAM_SIZE  0x0800
 #define CONFIG_NR_DRAM_BANKS   1
 #define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x4 /* Reserve 256k */
+#define CONFIG_SYS_MONITOR_LEN 0x8 /* Reserve 512k */
 #define CONFIG_SYS_MONITOR_BASE(CONFIG_SYS_SDRAM_BASE + \
 CONFIG_SYS_SDRAM_SIZE - \
 CONFIG_SYS_MONITOR_LEN)
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index 0f494e5..00e8374 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -66,7 +66,7 @@
 #define CONFIG_SYS_SDRAM_SIZE  0x0800
 #define CONFIG_NR_DRAM_BANKS   1
 #define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x4 /* Reserve 256k */
+#define CONFIG_SYS_MONITOR_LEN 0x8 /* Reserve 512k */
 #define CONFIG_SYS_MONITOR_BASE(CONFIG_SYS_SDRAM_BASE + \
 CONFIG_SYS_SDRAM_SIZE - \
 CONFIG_SYS_MONITOR_LEN)
-- 
2.1.4

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Re: [U-Boot] [PATCH] armv8/ls1043ardb: Add support for >2GB memory

[York Sun]

On 11/23/2015 03:23 PM, Mingkai Hu wrote:
> From: Shaohui Xie 
> 
> This patch also expose the complete DDR region(s) to Linux.
> 
> Signed-off-by: Shaohui Xie 
> Signed-off-by: Mingkai Hu 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York

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Re: [U-Boot] [PATCH 1/3] arm: ls102x: add get_svr and IS_SVR_REV helper

[York Sun]

On 11/20/2015 03:52 PM, Shengzhou Liu wrote:
> Signed-off-by: Shengzhou Liu 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York

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Re: [U-Boot] [PATCH 2/3] fsl/errata: move fsl_errata.h to common directory

[York Sun]

On 11/20/2015 03:52 PM, Shengzhou Liu wrote:
> move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
> to make it public for both ARM and POWER SoCs.
> 
> Signed-off-by: Shengzhou Liu 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York

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Re: [U-Boot] [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.

[York Sun]

On 12/05/2015 02:59 PM, Yuan Yao wrote:
> Signed-off-by: Yuan Yao 
> ---
> 
>  arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 

Modified subject, added commit message.
Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH 1/1] fsl_qspi: Pet the watchdog while reading/writing

[York Sun]

On 11/04/2015 04:19 PM, Alexander Stein wrote:
> When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
> timeout might occur meanwhile. So pet the watchdog while operating on
> the flash.
> 
> Signed-off-by: Alexander Stein 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH 4/5][v5] armv8/ls1043ardb: add SECURE BOOT target for NOR

[York Sun]

On 12/08/2015 04:24 PM, Aneesh Bansal wrote:
> LS1043ARDB Secure Boot Target from NOR has been added.
> - Configs defined to enable esbc_validate.
> - ESBC Address in header is made 64 bit.
> - SMMU is re-configured in Bypass mode.
> 
> Signed-off-by: Aneesh Bansal 
> ---
> Changes in v5:
> - Commit Subject modified
> - Call to sec_init() placed under CONFIG_FSL_CAAM
> 
> Changes in v4:
> - Fixed compilation break for LS1021AQDS
> 
> Changes in v3:
> - Enabled CONFIG_SYS_NS16550=y, CONFIF_DM=y and other options
>   similar to ls1043ardb_defconfig.
> - fsl_secure_boot.h is included outside of ifdef in file
>   include/configs/ls1043ardb.h
> 
> Changes in v2:
> - New Patch set created with an additional patch
> - Pointers typecasted to uintptr_t to remove compiler warnings
> 

Applied to fsl-qoriq master. Awaiting upstream.

York
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[U-Boot] [PATCH 1/5] nios2: Calculate the env position from monitor size

[Marek Vasut]

Reorder the 10m50 and 3c120 config files such, that the environment
position can be calculated from the monitor size. The environment is
placed right after the monitor. This removes one more ad-hoc variable.

Signed-off-by: Marek Vasut 
Cc: Thomas Chou 
---
 include/configs/10m50_devboard.h | 26 +-
 include/configs/3c120_devboard.h | 26 +-
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index 8a91cdb..c99177c 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -54,19 +54,6 @@
 #define CONFIG_LMB
 
 /*
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- */
-#define CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_SIZE0x1 /* 64k, 1 sector */
-#define CONFIG_ENV_OVERWRITE   /* Serial change Ok */
-#define CONFIG_ENV_ADDR0xf404
-
-/*
  * MEMORY ORGANIZATION
  * -Monitor at top of sdram.
  * -The heap is placed below the monitor
@@ -83,6 +70,19 @@
 #define CONFIG_SYS_MALLOC_LEN  0x2
 
 /*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE0x1 /* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE   /* Serial change Ok */
+#define CONFIG_ENV_ADDR(0xf400 + 
CONFIG_SYS_MONITOR_LEN)
+
+/*
  * MISC
  */
 #define CONFIG_SYS_LONGHELP/* Provide extended help */
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index 2ecdd5d..0f494e5 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -57,19 +57,6 @@
 #define CONFIG_LMB
 
 /*
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- */
-#define CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_SIZE0x2 /* 128k, 1 sector */
-#define CONFIG_ENV_OVERWRITE   /* Serial change Ok */
-#define CONFIG_ENV_ADDR0xe284
-
-/*
  * MEMORY ORGANIZATION
  * -Monitor at top of sdram.
  * -The heap is placed below the monitor
@@ -86,6 +73,19 @@
 #define CONFIG_SYS_MALLOC_LEN  0x2
 
 /*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE0x2 /* 128k, 1 sector */
+#define CONFIG_ENV_OVERWRITE   /* Serial change Ok */
+#define CONFIG_ENV_ADDR(0xe280 + 
CONFIG_SYS_MONITOR_LEN)
+
+/*
  * MISC
  */
 #define CONFIG_SYS_LONGHELP/* Provide extended help */
-- 
2.1.4

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[U-Boot] [PATCH 3/5] nios2: Preconfigure $loadaddr variable

[Marek Vasut]

Preset the $loadaddr environment variable to some sane default, let's
say half of the RAM. This variable is where the kernel is loaded using
all sorts of .*load commands, so it's convenient to have it set.

Signed-off-by: Marek Vasut 
Cc: Thomas Chou 
---
 include/configs/10m50_devboard.h | 3 ++-
 include/configs/3c120_devboard.h | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index 68ef6e5..608127f 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -92,7 +92,8 @@
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + \
 16)/* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR   CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_LOAD_ADDR   0xcc00  /* Half of RAM */
+#define CONFIG_LOADADDRCONFIG_SYS_LOAD_ADDR
 #define CONFIG_SYS_MEMTEST_START   CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
 CONFIG_ENV_SIZE - \
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index 00e8374..6c9dc3f 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -95,7 +95,8 @@
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + \
 16)/* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR   CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_LOAD_ADDR   0xd400  /* Half of RAM */
+#define CONFIG_LOADADDRCONFIG_SYS_LOAD_ADDR
 #define CONFIG_SYS_MEMTEST_START   CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
 CONFIG_ENV_SIZE - \
-- 
2.1.4

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[U-Boot] [PATCH 4/5] nios2: Enable support for fitImage

[Marek Vasut]

The uImage format is legacy for years now, enable support for the
fitImage format, which allows combining multiple files (kernel and
dtb) into a single file, offers better protection of the payload
and so on.

Signed-off-by: Marek Vasut 
Cc: Thomas Chou 
---
 include/configs/10m50_devboard.h | 2 ++
 include/configs/3c120_devboard.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index 608127f..0aa79f7 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -14,6 +14,8 @@
  */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_OF_LIBFDT
+#define CONFIG_FIT
 
 /*
  * SERIAL
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index 6c9dc3f..0054d8b 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -14,6 +14,8 @@
  */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_OF_LIBFDT
+#define CONFIG_FIT
 
 /*
  * SERIAL
-- 
2.1.4

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[U-Boot] [PATCH 5/5] nios2: Soup up the shell experience

[Marek Vasut]

Enable command auto completion and enable $version variable. This makes
working with U-Boot far more enjoyable.

Signed-off-by: Marek Vasut 
Cc: Thomas Chou 
---
 include/configs/10m50_devboard.h | 3 +++
 include/configs/3c120_devboard.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index 0aa79f7..72d455f0 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -101,6 +101,9 @@
 CONFIG_ENV_SIZE - \
 CONFIG_SYS_MALLOC_LEN -\
 0x1)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index 0054d8b..ed30d6f 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -104,6 +104,9 @@
 CONFIG_ENV_SIZE - \
 CONFIG_SYS_MALLOC_LEN -\
 0x1)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 #endif /* __CONFIG_H */
-- 
2.1.4

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Re: [U-Boot] [PATCH 3/5][v5] include/linux: move typdef for uintptr_t

[York Sun]

On 12/08/2015 04:24 PM, Aneesh Bansal wrote:
> uintptr_t which is a typdef for unsigned long is needed for creating
> pointers (32 or 64 bit depending on Core) from 32 bit variables
> storing the address.
> If a 32 bit variable (u32) is typecasted to a pointer (void *),
> compiler gives a warning in case size of pointer on the core is 64 bit.
> 
> The typdef has been moved from include/compiler.h to include/linux/types.h
> 
> Signed-off-by: Aneesh Bansal 
> ---
> Changes in v5:
> New patch instead of http://patchwork.ozlabs.org/patch/546319/
> 
> Changes in v4: None
> 
> Changes in v3: None
> 
> Changes in v2: None
> 

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH 1/5][v5] armv8: define usec2ticks function

[York Sun]

On 12/08/2015 04:24 PM, Aneesh Bansal wrote:
> usec2ticks() function has been defined for ARMv8 which will
> be used by SEC Driver.
> 
> Signed-off-by: Aneesh Bansal 
> ---
> Changes in v5:
> - Commit Subject modified
> 
> Changes in v4: None
> 
> Changes in v3: None
> 
> Changes in v2: None (New Patch set created with an additional patch)
> 

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH 2/5][v5] armv8: Make SEC read/write as snoopable for LS1043

[York Sun]

On 12/08/2015 04:24 PM, Aneesh Bansal wrote:
> For LS1043, SEC read/writes are made snoopable by setting
> the corresponding bits in SCFG to avoid coherency issues.
> 
> Signed-off-by: Aneesh Bansal 
> ---
> Changes in v5: None
> 
> Changes in v4: None
> 
> Changes in v3: None
> 
> Changes in v2: 
> New Patch set created with an additional patch
> Commit Subject modified

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Marek Vasut]

On Tuesday, December 15, 2015 at 02:09:42 AM, Chin Liang See wrote:
> On Tue, 2015-12-15 at 01:32 +0100, Marek Vasut wrote:
> > On Monday, December 14, 2015 at 04:22:57 PM, Chin Liang See wrote:
> > > On Mon, 2015-12-14 at 02:25 +0100, Marek Vasut wrote:
> > > > On Monday, December 14, 2015 at 02:22:32 AM, Chin Liang See
> 
> > > > wrote:
> [...]
> 
> > > Yeah, I can successfully mounted with ubifs :)
> > > 
> > > Just that I still have the issue with U-Boot ubifsmount although I
> > > already applied the patch for cache ARMV7. I will take a look into
> > > ubi
> > > code as I suspect its due to eraseblock size issue.
> > 
> > Keep looking, good luck.
> 
> Yup, will compare the UBI code with the Linux one.
> 
> > The armv7 cache issue is more serious than I thought, I am starting
> > to suspect
> > there is some problem with the L3 interconnect, but I cannot put my
> > finger on
> > it yet.
> 
> Hmmm... I can try to help.
> 
> FYI, I was trying to understand how the code error in cache-cp15 will
> cause the misbehave. One thing I am suspecting it might due to mismatch
> of cache policy for the memory that store the page table and
> translation page walk mechanism. But with your fix, it should be good
> as they are matching now.

I would suggest to move this to the thread below the CPU_V7 patch.

btw. the L2 cache is not enabled on SoCFPGA at all :-( I have a patch to fix
it, but this doesn't help us. I suspect there might be some synchronisation
or timing issue with accesses through the L3 interconnect, which would point
to NIC301 misconfiguration, but that's purely hypothetical. Do you have some
hardware-level or RTL-level/simulation tool to debug such issues at Altera ?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/6] dm: x86: Create a driver for x86 interrupts

[Bin Meng]

Hi Simon,

On Tue, Dec 15, 2015 at 6:14 AM, Simon Glass  wrote:
> Hi Bin,
>
> On 13 December 2015 at 23:05, Bin Meng  wrote:
>> Hi Simon,
>>
>> On Tue, Dec 1, 2015 at 12:46 PM, Simon Glass  wrote:
>>> It seems likely that at some point we will want a generic interrupt uclass.
>>> But this is a big undertaking as it involves unifying code across multiple
>>> architectures.
>>>
>>> As a first step, create a simple IRQ uclass and a driver for x86. This can
>>> be generalised later as required.
>>>
>>> Adjust pirq_init() to probe this driver, which has the effect of creating
>>> routing tables and setting up the interrupt routing. This is a start
>>> towards making interrupts fit better with driver model.
>>>
>>> Signed-off-by: Simon Glass 
>>> ---
>>>
>>
>> Reviewed-by: Bin Meng 
>>
>> I will test this series when all previous DM changes are applied.
>
> Do you mean the series that I just pushed to dm/next. or something else?
>

Yes, I mean all previous DM changes as I suspect this series has some
dependency on previous series. I will apply this series on top of
dm/next and test there.

Regards,
Bin
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Re: [U-Boot] [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.

[Yao Yuan]

Hi York,

Thanks for your review and modified.

Best Regards,
Yuan Yao

> -Original Message-
> From: Sun York-R58495
> Sent: Tuesday, December 15, 2015 9:00 AM
> To: Yuan Yao-B46683 
> Cc: Wang Huan-B18965 ; u-boot@lists.denx.de
> Subject: Re: [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.
> 
> 
> 
> On 12/05/2015 02:59 PM, Yuan Yao wrote:
> > Signed-off-by: Yuan Yao 
> > ---
> >
> >  arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
> >
> 
> Modified subject, added commit message.
> Applied to fsl-qoriq master. Awaiting upstream.
> 
> York
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Re: [U-Boot] [PATCH] powerpc: mpc85xx: Move set_liodns, setup_portals to common boot seq

[York Sun]

On 11/06/2015 04:44 PM, Prabhakar Kushwaha wrote:
> Users migrating Freescale's PowerPC SoC U-Boot code to their custom
> board, often overlook the need to execute set_liodns() and
> setup_portals() being called by platform files.
> 
> So Move set_liodns() and setup_portals() to common u-boot boot
> sequence
> 
> Signed-off-by: Prabhakar Kushwaha 
> ---
>  arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++
>  board/freescale/b4860qds/b4860qds.c | 5 -
>  board/freescale/corenet_ds/corenet_ds.c | 6 --
>  board/freescale/p2041rdb/p2041rdb.c | 3 ---
>  board/freescale/t102xqds/t102xqds.c | 5 -
>  board/freescale/t102xrdb/t102xrdb.c | 5 -
>  board/freescale/t1040qds/t1040qds.c | 5 -
>  board/freescale/t104xrdb/t104xrdb.c | 6 --
>  board/freescale/t208xqds/t208xqds.c | 6 --
>  board/freescale/t208xrdb/t208xrdb.c | 6 --
>  board/freescale/t4qds/t4240emu.c| 6 --
>  board/freescale/t4qds/t4240qds.c| 6 --
>  board/freescale/t4rdb/t4240rdb.c| 6 --
>  13 files changed, 7 insertions(+), 65 deletions(-)

Prabhakar,

This change is not good. You presume set_liodns() is available for all 85xx.
Putting the call into cpu_init.c caused compiling error for non-corenet SoCs.

Please update and make sure you run buildman on powerpc.

York

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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Marek Vasut]

On Monday, December 14, 2015 at 04:22:57 PM, Chin Liang See wrote:
> On Mon, 2015-12-14 at 02:25 +0100, Marek Vasut wrote:
> > On Monday, December 14, 2015 at 02:22:32 AM, Chin Liang See wrote:
> [...]
> 
> > > > > and rethinking, we can have 2 MTD_PARTITION
> > > > > where one for backward compatiblity (supporting raw) while
> > > > > another
> > > > > for
> > > > > UBI.
> > > > > 
> > > > > MTDPARTS_RAW
> > > > > 256k(spl),
> > > > > 256k(env),
> > > > > 15872k(boot),
> > > > > -(rootfs)
> > > > > 
> > > > > MTDPARTS_UBI
> > > > > 256k(spl),
> > > > > 256k(env),
> > > > > -(UBI)
> > > > > 
> > > > > We should make UBI as default then. If user care about backward
> > > > > compatiblity, they shall use the MTDPARTS_RAW then.
> > > > 
> > > > Try this:
> > > > 
> > > > mtdparts=1m(u
> > > > -boot),256k(env1),256k(env2),14848k(boot),112m(root),
> > > > -@1536k(UBI)
> > > > 
> > > > This will create overlapping partitions "boot,root" and "UBI" .
> > > 
> > > Nice, let me give it a try.
> > 
> > Make sure to test it in Linux too ;-)
> 
> Yeah, I can successfully mounted with ubifs :)
> 
> Just that I still have the issue with U-Boot ubifsmount although I
> already applied the patch for cache ARMV7. I will take a look into ubi
> code as I suspect its due to eraseblock size issue.

Keep looking, good luck.

The armv7 cache issue is more serious than I thought, I am starting to suspect
there is some problem with the L3 interconnect, but I cannot put my finger on
it yet.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 2/4] fsl_*_serdes.c: Modify memset call in serdes_init

[York Sun]

On 11/28/2015 09:04 PM, Tom Rini wrote:
> GCC 5.x does not like sizeof(array_variable) and errors out.  Change these
> calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
> SERDES_PRCTL_COUNT (the number of array elements).
> 
> Cc: York Sun 
> Signed-off-by: Tom Rini 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York

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Re: [U-Boot] [PATCH 3/4] qbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submit

[York Sun]

On 11/28/2015 09:04 PM, Tom Rini wrote:
> With gcc-5.x we get a warning about the ambiguity of BUG_ON(!a != b) and
> becomes BUG_ON((!a) != b).  In this case reading of the function leads to
> us wanting to rewrite this as BUG_ON(a != b).
> 
> Cc: Prabhakar Kushwaha 
> Cc: Geoff Thorpe 
> Cc: Haiying Wang 
> Cc: Roy Pledge 
> Cc: York Sun 
> Signed-off-by: Tom Rini 
> ---

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH v5 2/2] armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server

[York Sun]

On 12/08/2015 05:37 AM, York Sun wrote:
> MC and debug server are not board-specific. Move reserving memory to SoC
> file, using the new board_reserve_ram_top function. Reduce debug server
> memory by 2MB to make room for secure memory.
> 
> In the system with MC and debug server, the top of u-boot memory
> is not the end of memory. PRAM is not used for this reservation.
> 
> Signed-off-by: York Sun 
> 
> ---
> 
> Changes in v5:
>   Separated changes in board_f.c
> 
> Changes in v4:
>   Rebase to current master branch
> 
> Changes in v3:
>   Rename CONFIG_SYS_MC_RESERV_MEM_ALIGN to CONFIG_SYS_MC_RSV_MEM_ALIGN
>   Check for unused CONFIG_SYS_MEM_TOP_HIDE if board_reserve_ram_top is used
>   Use gd->ram_size = board_reserve_ram_top(gd->ram_size) format
>   Use phys_size_t instead of ulong for ram_size calculation
> 
> Changes in v2:
>   Revise commit message.

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH v7 1/2] Reserve secure memory

[York Sun]

On 12/05/2015 03:57 AM, York Sun wrote:
> Secure memory is at the end of memory, separated and reserved
> from OS, tracked by gd->secure_ram. Secure memory can host
> MMU tables, security monitor, etc. This is different from PRAM
> used to reserve private memory. PRAM offers memory at the top
> of u-boot memory, not necessarily the real end of memory for
> systems with very large DDR. Using the end of memory simplifies
> MMU setup and avoid memory fragmentation.
> 
> "bdinfo" command shows gd->secure_ram value if this memory is
> marked as secured.
> 
> Signed-off-by: York Sun 
> 
> ---
> 
> Changes in v7: None
> Changes in v6:
>   Move cmd_bdinfo change into this patch
>   Move flag macros and comments of secure_ram into this patch
> 
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
>   Put ifdef around secure_ram
>   Move defining CONFIG_SYS_MEM_RESERVE_SECURE to patch 2/2
> 
> Changes in v2:
>   Do not use CONFIG_SYS_MEM_TOP_HIDE mechanism
> 
> Changes in v1:
>   Initial patch.
>   Depends on http://patchwork.ozlabs.org/patch/540248/
> 

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH v7 2/2] armv8: fsl-layerscape: Make DDR non secure in MMU tables

[York Sun]

On 12/05/2015 03:57 AM, York Sun wrote:
> DDR has been set as secure in MMU tables. Non-secure master such
> as SDHC DMA cannot access data correctly. Mixing secure and non-
> secure MMU entries requirs the MMU tables themselves in secure
> memory. This patch moves MMU tables into a secure DDR area.
> 
> Early MMU tables are changed to set DDR as non-secure. A new
> table is added into final MMU tables so secure memory can have
> 2MB granuality.
> 
> gd->secure_ram tracks the location of this secure memory. For
> ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
> banks. gd->secure_ram needs to be maintained before using. This
> maintenance is board-specific, depending on the SoC and memory
> bank of the secure memory falls into.
> 
> Signed-off-by: York Sun 
> 
> ---
> 
> Changes in v7:
>   Rebase to recent master
>   Update ls1043ardb ddr.c
>   Add change to ls1043qds ddr.c
>   Check exception level before setting secure memory
>   Leave gd->arch.tlb_addr unused if secure memory is setup
> 
> Changes in v6:
>   Move cmd_bdinfo change to 1st patch in this set
>   Rearrange #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
> 
> Changes in v5:
>   Put ifdef where gd->secure_ram is used
> 
> Changes in v4:
>   Drop RFC from patch prefix
>   Drop excessive mmu table for secure ram for early MMU
>   Update commit message accordingly
>   Mark QBMan cacheable portal memory non-secure
> 
> Changes in v3:
>   Replace CONFIG_FSL_PPA_RESERVED_DRAM_SIZE with CONFIG_SYS_MEM_RESERVE_SECURE
>   Sanity check gd->secure_ram before using
>   Define CONFIG_SYS_MEM_RESERVE_SECURE in SoC header file
>   Include ls1043ardb
>   Modified commit message.
> 
> Changes in v2:
>   Move gd->arch.secure_ram to gd->secure_ram.
>   Change the calculation of gd->secure_ram accordingly.
>   Chnage commit message slightly accordingly.
> 
> Changes in v1: None
> 

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH v5 1/2] common: Rewrite hiding the end of memory

[York Sun]

On 12/08/2015 05:37 AM, York Sun wrote:
> As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves
> some memory from the end of ram, tracked by gd->ram_size. It is not
> always the top of u-boot visible memory. Rewrite the macro with a
> weak function to provide flexibility for complex calcuation. Legacy
> use of this macro is still supported.
> 
> Signed-off-by: York Sun 
> 
> ---
> 
> Changes in v5:
>   Separated as a new patch
> 
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH 5/5][v5] drivers/crypto/fsl: fix endianness issue in RNG

[York Sun]

On 12/08/2015 04:24 PM, Aneesh Bansal wrote:
> For Setting and clearing the bits in SEC Block registers
> sec_clrbits32() and sec_setbits32() are used which work as
> per endianness of CAAM block.
> So these must be used with SEC register address as argument.
> If the value is read in a local variable, then the functions
> will not behave correctly where endianness of CAAM and core is
> different.
> 
> Signed-off-by: Aneesh Bansal 
> CC: Alex Porosanu 
> ---
> Changes in v5: None
> 
> Changes in v4: None
> 
> Changes in v3: None
> 
> Changes in v2: None (New Patch set created with an additional patch)

Applied to fsl-qoriq master. Awaiting upstream.

York
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Re: [U-Boot] [PATCH v6] arm: Add sata support on Layerscape ARMv8 board

[York Sun]

On 12/09/2015 03:32 PM, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian 
> 
> Freescale ARM-based Layerscape contains a SATA controller
> which comply with the serial ATA 3.0 specification and the
> AHCI 1.3 specification.
> This patch adds SATA feature on ls2080aqds, ls2080ardb and
> ls1043aqds boards.
> 
> Signed-off-by: Tang Yuantian 
> ---
> v6:
>   - update rx watermark from 0x25 to 0x29 to improve
>   compatibility
> v5:
>   - re-organize the code
> v4:
>   - rebase to lastest git tree
>   - add another ARMv8 platform which is ls1043aqds
> v3:
>   - rename ls2085a to ls2080a
>   - rebase to the latest git tree
>   - replace the magic number with micro variable
> v2:
>   - rebase to the latest git tree
> 

Applied to fsl-qoriq master. Awaiting upstream.

York
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[U-Boot] [PATCH 1/3] spi: fsl_qspi: fix an error of using GENMASK

[Gong Qianyu]

This commit fixes the change of bad490a24212c068c5b718b9189f47ea4075d078.

Signed-off-by: Gong Qianyu 
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ed39114..d8d37cd 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX_BUFFER_SIZE 0x40
 #endif
 
-#define OFFSET_BITS_MASK   GENMASK(24, 0)
+#define OFFSET_BITS_MASK   GENMASK(23, 0)
 
 #define FLASH_STATUS_WEL   0x02
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/3] spi: fsl_qspi: fix compile warning for 64-bit platform

[Gong Qianyu]

This patch fixes the following compile warning:
drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe':
drivers/spi/fsl_qspi.c:937:15:
  warning: cast to pointer from integer of different size
 [-Wint-to-pointer-cast]
  priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
   ^
Signed-off-by: Gong Qianyu 

Signed-off-by: Gong Qianyu 
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index d8d37cd..755cc27 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -931,7 +931,7 @@ static int fsl_qspi_probe(struct udevice *bus)
 
dm_spi_bus->max_hz = plat->speed_hz;
 
-   priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
+   priv->regs = (struct fsl_qspi_regs *)(unsigned long)plat->reg_base;
priv->flags = plat->flags;
 
priv->speed_hz = plat->speed_hz;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 3/3] spi: fsl_quadspi: Fix qspi_op_rdid memcpy issue

[Gong Qianyu]

In current driver everytime we memcpy 4 bytes to the dest memory
regardless of the remaining length.
This patch add checking the remaining length before memcpy.
If the length is shorter than 4 bytes, memcpy the actual length of data
to the dest memory.

Signed-off-by: Gong Qianyu 
---
 drivers/spi/fsl_qspi.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 755cc27..b41b226 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -499,7 +499,10 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 
*rxbuf, u32 len)
if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, >rbdr[i]);
data = qspi_endian_xchg(data);
-   memcpy(rxbuf, , 4);
+   if (size < 4)
+   memcpy(rxbuf, , size);
+   else
+   memcpy(rxbuf, , 4);
rxbuf++;
size -= 4;
i++;
-- 
2.1.0.27.g96db324

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Re: [U-Boot] ARMv7 MMU shareability issue

[Marek Vasut]

On Monday, December 14, 2015 at 08:48:16 AM, Pavel Machek wrote:
> Hi!
> 
> > This patch has several effects:
> > 
> > - it selects proper ARMv7 translation table level 1 bit definitions;
> > - it provides proper ARMv7 definitions for WT/WB/WA;
> > - it selects proper ARMv7 settings for TTBR0.
> > 
> > All these are correct as per the docs I have (although I may have missed
> > something during the readings (and cross-readings with Marek) of these
> > last hours/days.
> > 
> > Now, one specific effect goes against performance, and it is the
> > setting of bit S in all TT entries. This bit makes the corresponding
> > region shareable, but for all I know, in U-Boot we don't have more than
> > one core accessing the same memory or registers sets so -- at least for
> > the major part of its execution -- there is no reason for any region to
> > be shareable.
> 
> Well, I'm currently working on AMP patch, which will mean two
> processors at the same time in u-boot.
> 
> Also... we provide memory modify operations for the user. User may
> be trying to communicate with second core.

You have a special usecase, so you should tweak your U-Boot for that using
some sort of config option.

> > /That/ effect I certainly don't want.
> 
> How big is the slowdown from S bit?

30-40% .

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Marek Vasut]

On Monday, December 14, 2015 at 08:54:38 AM, Pavel Machek wrote:
> (Please, trim your emails when replying)
> 
> On Mon 2015-12-14 01:58:04, Marek Vasut wrote:
> > On Monday, December 14, 2015 at 01:43:58 AM, Chin Liang See wrote:
> > > On Mon, 2015-12-14 at 01:22 +0100, Marek Vasut wrote:
> > > > On Monday, December 14, 2015 at 01:11:27 AM, Chin Liang See wrote:
> > > > > On Sun, 2015-12-13 at 16:42 +0100, Marek Vasut wrote:
> > > > > > On Sunday, December 13, 2015 at 02:03:02 PM, Chin Liang See
> > > 
> > > After grabbing a coffee
> > 
> > That's a good idea, though I think I will make do with a green tea (抹茶).
> > 
> > > and rethinking, we can have 2 MTD_PARTITION
> > > where one for backward compatiblity (supporting raw) while another for
> > > UBI.
> > > 
> > > MTDPARTS_RAW
> > > 256k(spl),
> > > 256k(env),
> > > 15872k(boot),
> > > -(rootfs)
> > > 
> > > MTDPARTS_UBI
> > > 256k(spl),
> > > 256k(env),
> > > -(UBI)
> > > 
> > > We should make UBI as default then. If user care about backward
> > > compatiblity, they shall use the MTDPARTS_RAW then.
> > 
> > Try this:
> > 
> > mtdparts=1m(u-boot),256k(env1),256k(env2),14848k(boot),112m(root),-@1536k
> > (UBI)
> > 
> > This will create overlapping partitions "boot,root" and "UBI" .
> 
> Just because you can does not mean that you should. This looks like a
> nasty trap for a user.

Please explain in detail why do you think so.

Best regards,
Marek Vasut
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[U-Boot] [PATCH] sata: Add SATA driver with DMA support for Marvell Kirkwood and Armada XP

[Stefan Roese]

From: Tor Krill 

This patch adds a new SATA driver for the Marvell Kirkwood and Armada
370 / XP SoC's.

This driver supports the SATA controller of some Mavell SoC's.
Here a (most likely incomplete) list of the supported SoC's:
- Kirkwood
- Armada 370
- Armada XP

This driver implementation is an alternative to the already available
driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
But this driver only supports PIO mode and as this new driver also
supports transfer via DMA, its much faster.

Please note, that the newer SoC's (e.g. Armada 38x) are not supported
by this driver. As they have an AHCI compatible SATA controller
integrated.

The original version of this driver was sent by Tor Krill to the U-Boot
list a few years ago. Here the link:

http://lists.denx.de/pipermail/u-boot/2010-June/073147.html

Changes by Stefan:
- Coding-style cleanup
- Support for Armada XP added
- MBUS window setup added
- D-cache flush and invalidation added - works with dcache enabled on
  Armada XP
- Removed mdelay() from ata_wait_register() and add timer based timeout
  detection to speed up the transfer

Signed-off-by: Tor Krill 
Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
Cc: Tom Rini 
---
 drivers/block/Makefile  |1 +
 drivers/block/sata_mv.c | 1045 +++
 2 files changed, 1046 insertions(+)
 create mode 100644 drivers/block/sata_mv.c

diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index f161c01..eb8bda9 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
 obj-$(CONFIG_MX51_PATA) += mxc_ata.o
 obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
 obj-$(CONFIG_SATA_DWC) += sata_dwc.o
+obj-$(CONFIG_SATA_MV) += sata_mv.o
 obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
 obj-$(CONFIG_SATA_SIL) += sata_sil.o
 obj-$(CONFIG_IDE_SIL680) += sil680.o
diff --git a/drivers/block/sata_mv.c b/drivers/block/sata_mv.c
new file mode 100644
index 000..8824934
--- /dev/null
+++ b/drivers/block/sata_mv.c
@@ -0,0 +1,1045 @@
+/*
+ * Copyright (C) Excito Elektronik i Skåne AB, 2010.
+ * Author: Tor Krill 
+ *
+ * Copyright (C) 2015 Stefan Roese 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * This driver supports the SATA controller of some Mavell SoC's.
+ * Here a (most likely incomplete) list of the supported SoC's:
+ * - Kirkwood
+ * - Armada 370
+ * - Armada XP
+ *
+ * This driver implementation is an alternative to the already available
+ * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
+ * But this driver only supports PIO mode and as this new driver also
+ * supports transfer via DMA, its much faster.
+ *
+ * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
+ * by this driver. As they have an AHCI compatible SATA controller
+ * integrated.
+ */
+
+/*
+ * TODO:
+ * Better error recovery
+ * No support for using PRDs (Thus max 64KB transfers)
+ * No NCQ support
+ * No port multiplier support
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_KIRKWOOD)
+#include 
+#define SATAHC_BASEKW_SATA_BASE
+#else
+#include 
+#define SATAHC_BASEMVEBU_AXP_SATA_BASE
+#endif
+
+#define SATA0_BASE (SATAHC_BASE + 0x2000)
+#define SATA1_BASE (SATAHC_BASE + 0x4000)
+
+/* EDMA registers */
+#define EDMA_CFG   0x000
+#define EDMA_CFG_NCQ   (1 << 5)
+#define EDMA_CFG_EQUE  (1 << 9)
+#define EDMA_TIMER 0x004
+#define EDMA_IECR  0x008
+#define EDMA_IEMR  0x00c
+#define EDMA_RQBA_HI   0x010
+#define EDMA_RQIPR 0x014
+#define EDMA_RQIPR_IPMASK  (0x1f << 5)
+#define EDMA_RQIPR_IPSHIFT 5
+#define EDMA_RQOPR 0x018
+#define EDMA_RQOPR_OPMASK  (0x1f << 5)
+#define EDMA_RQOPR_OPSHIFT 5
+#define EDMA_RSBA_HI   0x01c
+#define EDMA_RSIPR 0x020
+#define EDMA_RSIPR_IPMASK  (0x1f << 3)
+#define EDMA_RSIPR_IPSHIFT 3
+#defineEDMA_RSOPR  0x024
+#define EDMA_RSOPR_OPMASK  (0x1f << 3)
+#define EDMA_RSOPR_OPSHIFT 3
+#define EDMA_CMD   0x028
+#define EDMA_CMD_ENEDMA(0x01 << 0)
+#define EDMA_CMD_DISEDMA   (0x01 << 1)
+#define EDMA_CMD_ATARST(0x01 << 2)
+#define EDMA_CMD_FREEZE(0x01 << 4)
+#define EDMA_TEST_CTL  0x02c
+#define EDMA_STATUS0x030
+#define EDMA_IORTO 0x034
+#define EDMA_CDTR  0x040
+#define EDMA_HLTCND0x060
+#define EDMA_NTSR  0x094
+
+/* Basic DMA registers */
+#define BDMA_CMD   0x224
+#define BDMA_STATUS0x228
+#define BDMA_DTLB  0x22c
+#define BDMA_DTHB  0x230
+#define BDMA_DRL   0x234

Re: [U-Boot] [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.

[Yao Yuan]

Hi York,

I'm sorry I'm late replies.

Thanks for reminding me.
We have some investigates and then depend on the document we think both snoop 
request and DVM are supported on those port.
So we think the setting should be ok in here.

Best Regards,
Yuan Yao

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Tuesday, December 08, 2015 12:58 AM
> To: Yuan Yao-B46683 
> Cc: Wang Huan-B18965 ; u-boot@lists.denx.de
> Subject: Re: [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.
> 
> 
> 
> On 12/04/2015 10:59 PM, Yuan Yao wrote:
> > Signed-off-by: Yuan Yao 
> > ---
> >
> >  arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c
> > b/arch/arm/cpu/armv7/ls102xa/soc.c
> > index 6036473..97ba6d5 100644
> > --- a/arch/arm/cpu/armv7/ls102xa/soc.c
> > +++ b/arch/arm/cpu/armv7/ls102xa/soc.c
> > @@ -40,8 +40,14 @@ int arch_soc_init(void)
> >
> > /*
> >  * Enable snoop requests and DVM message requests for
> > -* Slave insterface S4 (A7 core cluster)
> > +* All the slave insterfaces.
> >  */
> > +   out_le32(>slave[0].snoop_ctrl,
> > +CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
> > +   out_le32(>slave[1].snoop_ctrl,
> > +CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
> > +   out_le32(>slave[2].snoop_ctrl,
> > +CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
> > out_le32(>slave[4].snoop_ctrl,
> >  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
> >
> >
> 
> Yuan,
> 
> I'm not sure both snoop request and DVM are supported on every port. Do you
> need to check them before setting?
> 
> York
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[U-Boot] [PATCH 1/3] spi: fsl_qspi: fix an error of using GENMASK

[Gong Qianyu]

This commit fixes the change of bad490a24212c068c5b718b9189f47ea4075d078.

Signed-off-by: Gong Qianyu 
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ed39114..d8d37cd 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX_BUFFER_SIZE 0x40
 #endif
 
-#define OFFSET_BITS_MASK   GENMASK(24, 0)
+#define OFFSET_BITS_MASK   GENMASK(23, 0)
 
 #define FLASH_STATUS_WEL   0x02
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/3] spi: fsl_qspi: fix compile warning for 64-bit platform

[Gong Qianyu]

This patch fixes the following compile warning:
drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe':
drivers/spi/fsl_qspi.c:937:15:
  warning: cast to pointer from integer of different size
 [-Wint-to-pointer-cast]
  priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
   ^
Signed-off-by: Gong Qianyu 

Signed-off-by: Gong Qianyu 
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index d8d37cd..755cc27 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -931,7 +931,7 @@ static int fsl_qspi_probe(struct udevice *bus)
 
dm_spi_bus->max_hz = plat->speed_hz;
 
-   priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
+   priv->regs = (struct fsl_qspi_regs *)(unsigned long)plat->reg_base;
priv->flags = plat->flags;
 
priv->speed_hz = plat->speed_hz;
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 00/11] Add support for Synology DS414 and some related fixes

[Stefan Roese]

Hi Phil,

(added Dennis, as he is also interested in this new git branch)

On 14.12.2015 12:26, Phil Sutter wrote:
> On Mon, Dec 14, 2015 at 08:38:06AM +0100, Stefan Roese wrote:
>> On 13.12.2015 01:29, Phil Sutter wrote:
>>> This patch series ultimately adds support for Synology DS414 NAS after a
>>> few fixes:
>>> * Patches 1-3 and 5 fix various files for enabled debugging.
>>> * Patch 4 updates the board porting guide in README file.
>>> * Patches 6-8 hold crucial fixes necessary for DS414 support.
>>> * Patches 9 and 10 contain the actual board support, split into a generic
>>> part for MV78230 SoC and a board specific part for clarity.
>>> * Patch 11 adds a new command to deal with Synology specialties.
>>>
>>> In case you would like me to split this into multiple series, just let me
>>> know and I will resend.
>>
>> Very nice to see other Armada XP based boards getting supported
>> in mainline U-Boot. I'm currently also working on a new XP board
>> based on the MV78260. And stumbled over a few of the problems
>> you have met in your Armada XP support as well.
>>
>> Since I'm currently preparing a new patchset for all this,
>> including the full DM SPL support as well, perhaps it would
>> be best, if you base your MV78230 work in top of my new
>> patches. I will send the new patches to the list later today.
>> And will also publish a git branch for easier work with it.
>> Since there are some dependencies with other patches as well.
> 
> Sounds very good, I'm looking forward to seeing how you solved things
> and how that combines with my stuff.
> 
>> BTW: With this work you should be able to drop all those
>> "non-DM" patches from your series.
> 
> Nice!
> 
>> PS: Please keep Luka and me on Cc on all mvebu related patches.
> 
> Will do.

Thanks.

Okay. I've sent the new patches to the list. And also added a branch
to the "u-boot-a38x.git" gitlab repository. You can find a full
working version in this branch now "mvebu-dm-spl-2015-12-14":

https://gitlab.denx.de/sr/u-boot-a38x/commits/mvebu-dm-spl-2015-12-14

Please base your work on top of this branch if possible. Adding
support for your MV78230 should be quite straight forward now.

Just let me know if you have any questions.

@ Dennis:
This branch also includes the latest version for the ClearFog.
Please take a look at it and let me know if it works for you.

Thanks,
Stefan

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Re: [U-Boot] ARMv7 MMU shareability issue

[Albert ARIBAUD]

Hello Pavel,

On Mon, 14 Dec 2015 08:48:16 +0100, Pavel Machek  wrote:
> Hi!
> 
> > This patch has several effects:
> > 
> > - it selects proper ARMv7 translation table level 1 bit definitions;
> > - it provides proper ARMv7 definitions for WT/WB/WA;
> > - it selects proper ARMv7 settings for TTBR0.
> > 
> > All these are correct as per the docs I have (although I may have missed
> > something during the readings (and cross-readings with Marek) of these
> > last hours/days.
> > 
> > Now, one specific effect goes against performance, and it is the
> > setting of bit S in all TT entries. This bit makes the corresponding
> > region shareable, but for all I know, in U-Boot we don't have more than
> > one core accessing the same memory or registers sets so -- at least for
> > the major part of its execution -- there is no reason for any region to
> > be shareable.
> 
> Well, I'm currently working on AMP patch, which will mean two
> processors at the same time in u-boot.

Will they share memory or will they use another mechanism for sync?

> Also... we provide memory modify operations for the user. User may
> be trying to communicate with second core.
> 
> > /That/ effect I certainly don't want.
> 
> How big is the slowdown from S bit?

A 4MB memory-to-memory transfer goes from instantaneous to 2-3 seconds;
Ethernet performance drops by 40%.

> Best regards,

Amicalement,
-- 
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Pavel Machek]

On Mon 2015-12-14 12:09:08, Marek Vasut wrote:
> On Monday, December 14, 2015 at 08:54:38 AM, Pavel Machek wrote:
> > (Please, trim your emails when replying)

> > > Try this:
> > > 
> > > mtdparts=1m(u-boot),256k(env1),256k(env2),14848k(boot),112m(root),-@1536k
> > > (UBI)
> > > 
> > > This will create overlapping partitions "boot,root" and "UBI" .
> > 
> > Just because you can does not mean that you should. This looks like a
> > nasty trap for a user.
> 
> Please explain in detail why do you think so.

Please make a 200 page study of human psychology explaining that noone
would ever be confused by two overlapping partitions :-).

Pavel
-- 
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(cesky, pictures) 
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Re: [U-Boot] [PATCH 00/11] Add support for Synology DS414 and some related fixes

[Phil Sutter]

Hi Stefan,

On Mon, Dec 14, 2015 at 08:38:06AM +0100, Stefan Roese wrote:
> On 13.12.2015 01:29, Phil Sutter wrote:
> > This patch series ultimately adds support for Synology DS414 NAS after a
> > few fixes:
> > * Patches 1-3 and 5 fix various files for enabled debugging.
> > * Patch 4 updates the board porting guide in README file.
> > * Patches 6-8 hold crucial fixes necessary for DS414 support.
> > * Patches 9 and 10 contain the actual board support, split into a generic
> >part for MV78230 SoC and a board specific part for clarity.
> > * Patch 11 adds a new command to deal with Synology specialties.
> >
> > In case you would like me to split this into multiple series, just let me
> > know and I will resend.
> 
> Very nice to see other Armada XP based boards getting supported
> in mainline U-Boot. I'm currently also working on a new XP board
> based on the MV78260. And stumbled over a few of the problems
> you have met in your Armada XP support as well.
> 
> Since I'm currently preparing a new patchset for all this,
> including the full DM SPL support as well, perhaps it would
> be best, if you base your MV78230 work in top of my new
> patches. I will send the new patches to the list later today.
> And will also publish a git branch for easier work with it.
> Since there are some dependencies with other patches as well.

Sounds very good, I'm looking forward to seeing how you solved things
and how that combines with my stuff.

> BTW: With this work you should be able to drop all those
> "non-DM" patches from your series.

Nice!

> PS: Please keep Luka and me on Cc on all mvebu related patches.

Will do.

Thanks, Phil
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Pavel Machek]

On Mon 2015-12-14 12:31:32, Marek Vasut wrote:
> On Monday, December 14, 2015 at 12:26:39 PM, Pavel Machek wrote:
> > On Mon 2015-12-14 12:09:08, Marek Vasut wrote:
> > > On Monday, December 14, 2015 at 08:54:38 AM, Pavel Machek wrote:
> > > > (Please, trim your emails when replying)
> > > > 
> > > > > Try this:
> > > > > 
> > > > > mtdparts=1m(u-boot),256k(env1),256k(env2),14848k(boot),112m(root),-@1
> > > > > 536k (UBI)
> > > > > 
> > > > > This will create overlapping partitions "boot,root" and "UBI" .
> > > > 
> > > > Just because you can does not mean that you should. This looks like a
> > > > nasty trap for a user.
> > > 
> > > Please explain in detail why do you think so.
> > 
> > Please make a 200 page study of human psychology explaining that noone
> > would ever be confused by two overlapping partitions :-).
> 
> Add a comment explaining the situation and reasoning behind that, problem 
> solved.

We do partitions so that people don't overwrite data by
mistake. Having overlapping partitions kind of defeats the purpose.

Just because trap is documented does not mean that it is not
nasty. 199.95 pages to go.

Pavel
-- 
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(cesky, pictures) 
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Re: [U-Boot] [PATCH] include: Correct "requset" typoes in misc.h

[Thomas Chou]

Hi Robert,

On 2015年12月14日 19:28, Robert P. J. Day wrote:


Signed-off-by: Robert P. J. Day 

---

diff --git a/include/misc.h b/include/misc.h
index 7e9badf..2b78814 100644
--- a/include/misc.h
+++ b/include/misc.h
@@ -32,7 +32,7 @@ int misc_write(struct udevice *dev, int offset, void *buf, 
int size);
   *
   * @dev: the device
   * @request: command to be sent to the device
- * @buf: pointer to buffer related to the requset
+ * @buf: pointer to buffer related to the request
   * @return: 0 if OK, -ve on error
   */
  int misc_ioctl(struct udevice *dev, unsigned long request, void *buf);
@@ -70,7 +70,7 @@ struct misc_ops {
 *
 * @dev: the device
 * @request: command to be sent to the device
-* @buf: pointer to buffer related to the requset
+* @buf: pointer to buffer related to the request
 * @return: 0 if OK, -ve on error
 */
int (*ioctl)(struct udevice *dev, unsigned long request, void *buf);



Acked-by: Thomas Chou 
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[U-Boot] [PATCH v2 1/2] ns16550: replace with binding files from Linux kernel

[Thomas Chou]

Replace ns16550.txt with binding files from Linux kernel. As suggested
by Stephen Warren, we should keep the directory structure, filenames,
and file content identical to the bindings in the Linux kernel.

Signed-off-by: Thomas Chou 
---
 doc/device-tree-bindings/serial/8250.txt   | 66 +++
 doc/device-tree-bindings/serial/ns16550.txt| 10 ---
 doc/device-tree-bindings/serial/omap_serial.txt| 33 ++
 .../serial/snps-dw-apb-uart.txt| 76 ++
 4 files changed, 175 insertions(+), 10 deletions(-)
 create mode 100644 doc/device-tree-bindings/serial/8250.txt
 delete mode 100644 doc/device-tree-bindings/serial/ns16550.txt
 create mode 100644 doc/device-tree-bindings/serial/omap_serial.txt
 create mode 100644 doc/device-tree-bindings/serial/snps-dw-apb-uart.txt

diff --git a/doc/device-tree-bindings/serial/8250.txt 
b/doc/device-tree-bindings/serial/8250.txt
new file mode 100644
index 000..91d5ab0
--- /dev/null
+++ b/doc/device-tree-bindings/serial/8250.txt
@@ -0,0 +1,66 @@
+* UART (Universal Asynchronous Receiver/Transmitter)
+
+Required properties:
+- compatible : one of:
+   - "ns8250"
+   - "ns16450"
+   - "ns16550a"
+   - "ns16550"
+   - "ns16750"
+   - "ns16850"
+   - For Tegra20, must contain "nvidia,tegra20-uart"
+   - For other Tegra, must contain '"nvidia,-uart",
+ "nvidia,tegra20-uart"' where  is tegra30, tegra114, tegra124,
+ tegra132, or tegra210.
+   - "nxp,lpc3220-uart"
+   - "ralink,rt2880-uart"
+   - "ibm,qpace-nwp-serial"
+   - "altr,16550-FIFO32"
+   - "altr,16550-FIFO64"
+   - "altr,16550-FIFO128"
+   - "fsl,16550-FIFO64"
+   - "fsl,ns16550"
+   - "serial" if the port type is unknown.
+- reg : offset and length of the register set for the device.
+- interrupts : should contain uart interrupt.
+- clock-frequency : the input clock frequency for the UART
+or
+  clocks phandle to refer to the clk used as per Documentation/devicetree
+  /bindings/clock/clock-bindings.txt
+
+Optional properties:
+- current-speed : the current active speed of the UART.
+- reg-offset : offset to apply to the mapbase from the start of the registers.
+- reg-shift : quantity to shift the register offsets by.
+- reg-io-width : the size (in bytes) of the IO accesses that should be
+  performed on the device.  There are some systems that require 32-bit
+  accesses to the UART (e.g. TI davinci).
+- used-by-rtas : set to indicate that the port is in use by the OpenFirmware
+  RTAS and should not be registered.
+- no-loopback-test: set to indicate that the port does not implements loopback
+  test mode
+- fifo-size: the fifo size of the UART.
+- auto-flow-control: one way to enable automatic flow control support. The
+  driver is allowed to detect support for the capability even without this
+  property.
+
+Note:
+* fsl,ns16550:
+  
+  Freescale DUART is very similar to the PC16552D (and to a
+  pair of NS16550A), albeit with some nonstandard behavior such as
+  erratum A-004737 (relating to incorrect BRK handling).
+
+  Represents a single port that is compatible with the DUART found
+  on many Freescale chips (examples include mpc8349, mpc8548,
+  mpc8641d, p4080 and ls2085a).
+
+Example:
+
+   uart@8023 {
+   compatible = "ns8250";
+   reg = <0x8023 0x100>;
+   clock-frequency = <3686400>;
+   interrupts = <10>;
+   reg-shift = <2>;
+   };
diff --git a/doc/device-tree-bindings/serial/ns16550.txt 
b/doc/device-tree-bindings/serial/ns16550.txt
deleted file mode 100644
index ef0b9ae..000
--- a/doc/device-tree-bindings/serial/ns16550.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-NS16550 UART
-
-This UART driver supports many chip variants and is used in mamy SoCs.
-
-Required properties:
-- compatible: "ns16550" or "nvidia,tegra20-uart"
-- reg: start address and size of registers
-- reg-shift: shift value indicating register size: 0=byte, 1=16bit,2=32bit etc.
-- clock-frequency: input clock frequency for the UART (used to calculate the
-baud rate divisor)
diff --git a/doc/device-tree-bindings/serial/omap_serial.txt 
b/doc/device-tree-bindings/serial/omap_serial.txt
new file mode 100644
index 000..7a71b5d
--- /dev/null
+++ b/doc/device-tree-bindings/serial/omap_serial.txt
@@ -0,0 +1,33 @@
+OMAP UART controller
+
+Required properties:
+- compatible : should be "ti,omap2-uart" for OMAP2 controllers
+- compatible : should be "ti,omap3-uart" for OMAP3 controllers
+- compatible : should be "ti,omap4-uart" for OMAP4 controllers
+- compatible : should be "ti,am4372-uart" for AM437x controllers
+- compatible : should be "ti,am3352-uart" for AM335x controllers
+- compatible : should be "ti,dra742-uart" for DRA7x controllers
+- reg : address and length of the register space
+- interrupts or interrupts-extended : Should contain the uart interrupt
+   

[U-Boot] [PATCH v2 2/2] ns16550: zap the rockchip serial compatible string

[Thomas Chou]

Zap the rockchip serial compatible string, because rockchip
serial has "snps,dw-apb-uart" compatible string in the dts.

Signed-off-by: Thomas Chou 
---
 drivers/serial/ns16550.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3fab3f1..06ac005 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -424,11 +424,15 @@ const struct dm_serial_ops ns16550_serial_ops = {
 };
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
+/*
+ * Please consider existing compatible strings before adding a new
+ * one to keep this table compact. Or you may add a generic "ns16550"
+ * compatible string to your dts.
+ */
 static const struct udevice_id ns16550_serial_ids[] = {
{ .compatible = "ns16550" },
{ .compatible = "ns16550a" },
{ .compatible = "nvidia,tegra20-uart" },
-   { .compatible = "rockchip,rk3036-uart" },
{ .compatible = "snps,dw-apb-uart" },
{ .compatible = "ti,omap2-uart" },
{ .compatible = "ti,omap3-uart" },
-- 
2.5.0

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[U-Boot] [PATCH] i2c: mxc: allow executing the code that only applies to i.MX platforms

[Gong Qianyu]

The bus_i2c_init() is called before relocation and will assgin
value to a static variable. If U-Boot is then still running in a
flash device, it's theoretically not allowed to write data to flash
without an erasing operation. For i.MX platforms, the U-Boot is
always running in DDR.

Actually it causes asynchronous error when the ARM64 system error report
is enabled and the flash write protect is set.

Signed-off-by: Gong Qianyu 
---
 drivers/i2c/mxc_i2c.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index fa4c82f..4dddb83 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -581,8 +581,11 @@ void bus_i2c_init(int index, int speed, int unused,
return;
}
 
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
+   defined(CONFIG_MX6) || defined(CONFIG_MX7)
mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
+#endif
 
ret = enable_i2c_clk(1, index);
if (ret < 0) {
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH] i2c: mxc: allow executing the code that only applies to i.MX platforms

[York Sun]

On 12/14/2015 06:23 PM, Gong Qianyu wrote:
> The bus_i2c_init() is called before relocation and will assgin
> value to a static variable. If U-Boot is then still running in a
> flash device, it's theoretically not allowed to write data to flash
> without an erasing operation. For i.MX platforms, the U-Boot is
> always running in DDR.
> 
> Actually it causes asynchronous error when the ARM64 system error report
> is enabled and the flash write protect is set.
> 
> Signed-off-by: Gong Qianyu 
> ---
>  drivers/i2c/mxc_i2c.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
> index fa4c82f..4dddb83 100644
> --- a/drivers/i2c/mxc_i2c.c
> +++ b/drivers/i2c/mxc_i2c.c
> @@ -581,8 +581,11 @@ void bus_i2c_init(int index, int speed, int unused,
>   return;
>   }
>  
> +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
> + defined(CONFIG_MX6) || defined(CONFIG_MX7)
>   mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
>   mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
> +#endif
>  

I also think using variable mxc_i2c_buses is problematic. But using ifdef
doesn't look like a solution. I think this variable should be put into stack, or
use malloc. It works with execution-in-place in read-only space.

York

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Re: [U-Boot] [PATCH] i2c: mxc: allow executing the code that only applies to i.MX platforms

[York Sun]

On 12/14/2015 07:03 PM, Gong Qianyu-B52263 wrote:
> 
>> -Original Message-
>> From: Sun York-R58495
>> Sent: Monday, December 14, 2015 6:37 PM
>> To: Gong Qianyu-B52263; u-boot@lists.denx.de
>> Cc: Hu Mingkai-B21284; Sun York-R58495; Fan Peng-B51431
>> Subject: Re: [PATCH] i2c: mxc: allow executing the code that only applies
>> to i.MX platforms
>>
>>
>>
>> On 12/14/2015 06:23 PM, Gong Qianyu wrote:
>>> The bus_i2c_init() is called before relocation and will assgin value
>>> to a static variable. If U-Boot is then still running in a flash
>>> device, it's theoretically not allowed to write data to flash without
>>> an erasing operation. For i.MX platforms, the U-Boot is always running
>>> in DDR.
>>>
>>> Actually it causes asynchronous error when the ARM64 system error
>>> report is enabled and the flash write protect is set.
>>>
>>> Signed-off-by: Gong Qianyu 
>>> ---
>>>  drivers/i2c/mxc_i2c.c | 3 +++
>>>  1 file changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index
>>> fa4c82f..4dddb83 100644
>>> --- a/drivers/i2c/mxc_i2c.c
>>> +++ b/drivers/i2c/mxc_i2c.c
>>> @@ -581,8 +581,11 @@ void bus_i2c_init(int index, int speed, int unused,
>>> return;
>>> }
>>>
>>> +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
>>> +   defined(CONFIG_MX6) || defined(CONFIG_MX7)
>>> mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
>>> mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
>>> +#endif
>>>
>>
>> I also think using variable mxc_i2c_buses is problematic. But using ifdef
>> doesn't look like a solution. I think this variable should be put into
>> stack, or use malloc. It works with execution-in-place in read-only space.
>>
>> York
> 
> But we don't know if the stack will be enough before relocation. For SD boot 
> of LS1043A, 
> 
> there is now only 4KB for it and if the spl image is bigger in the future, 
> the stack is 
> 
> smaller. So isn't leaving more stack(if possible) for necessary code better? 

This array is small. The size of stack depends on the deepest one in all
functions. I don't think this driver use deep stack. I remember Linux has a tool
to calculate the stack. You can try it to examine the stack depth.

York

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[U-Boot] [PATCH 14/14] arm: mvebu: Make serdes setup on Armada XP less noisy

[Stefan Roese]

Change some of the PEX configuration output lines from always output to
only ouput upon specific debug enabling.

This changes the SPL output from:

U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42)
High speed PHY - Version: 2.1.5 (COM-PHY-V20)
Update Device ID PEX0782611ab
Update Device ID PEX1782611ab
Update Device ID PEX2782611ab
Update Device ID PEX3782611ab
Update Device ID PEX8782611ab
Update PEX Device ID 0x78260
High speed PHY - Ended Successfully
DDR3 Training Sequence - Ver 5.7.4
DDR3 Training Sequence - Ended Successfully

to:

U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04)
High speed PHY - Version: 2.1.5 (COM-PHY-V20)
High speed PHY - Ended Successfully
DDR3 Training Sequence - Ver 5.7.4
DDR3 Training Sequence - Ended Successfully

Resulting in a little faster bootup time.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
---
 arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c 
b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
index 9762971..bfa7f13 100644
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
@@ -1376,19 +1376,19 @@ int serdes_phy_config(void)
 pex_if, 
PEX_DEVICE_AND_VENDOR_ID));
devId &= 0x;
devId |= ((ctrl_mode << 16) & 0x);
-   DEBUG_INIT_S("Update Device ID PEX");
-   DEBUG_INIT_D(pex_if, 1);
-   DEBUG_INIT_D(devId, 8);
-   DEBUG_INIT_S("\n");
+   DEBUG_INIT_FULL_S("Update Device ID PEX");
+   DEBUG_INIT_FULL_D(pex_if, 1);
+   DEBUG_INIT_FULL_D(devId, 8);
+   DEBUG_INIT_FULL_S("\n");
reg_write(PEX_CFG_DIRECT_ACCESS
  (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
if ((pex_if < 8) &&
(info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
pex_if += 3;
}
-   DEBUG_INIT_S("Update PEX Device ID 0x");
-   DEBUG_INIT_D(ctrl_mode, 4);
-   DEBUG_INIT_S("0\n");
+   DEBUG_INIT_FULL_S("Update PEX Device ID 0x");
+   DEBUG_INIT_FULL_D(ctrl_mode, 4);
+   DEBUG_INIT_FULL_S("0\n");
}
tmp = reg_read(PEX_DBG_STATUS_REG(0));
DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
-- 
2.6.4

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[U-Boot] [PATCH 06/14] arm: mvebu: Don't call arch_cpu_init() from SPL at all

[Stefan Roese]

This patch removes the call to arch_cpu_init() in the SPL U-Boot version.
As SPL does not need all the configuration done in this function. And
also does not need the reconfiguration of the internal register
address to 0xf100. This will be done by the main U-Boot later on.

This also fixes a problem with the timer not beeing initialized on AXP,
as needed for the mdelay in the setup_usb_phys(). This will now only
be called once in main U-Boot.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
---
 arch/arm/mach-mvebu/cpu.c  |  7 +++
 arch/arm/mach-mvebu/include/mach/soc.h |  9 +
 arch/arm/mach-mvebu/spl.c  | 13 -
 3 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index fd56c99..071b13b 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -220,9 +220,11 @@ static void setup_usb_phys(void)
}
 }
 
+/*
+ * This function is not called from the SPL U-Boot version
+ */
 int arch_cpu_init(void)
 {
-#if !defined(CONFIG_SPL_BUILD)
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
@@ -233,13 +235,11 @@ int arch_cpu_init(void)
 * still locked to cache.
 */
mmu_disable();
-#endif
 
/* Linux expects the internal registers to be at 0xf100 */
writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
set_cbar(SOC_REGS_PHY_BASE + 0xC000);
 
-#if !defined(CONFIG_SPL_BUILD)
/*
 * From this stage on, the SoC detection is working. As we have
 * configured the internal register base to the value used
@@ -253,7 +253,6 @@ int arch_cpu_init(void)
icache_disable();
dcache_disable();
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-#endif
 
/*
 * We need to call mvebu_mbus_probe() before calling
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h 
b/arch/arm/mach-mvebu/include/mach/soc.h
index 2be8cba..b78da25 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -33,10 +33,11 @@
 #define INTREG_BASE_ADDR_REG   (INTREG_BASE + 0x20080)
 #if defined(CONFIG_SPL_BUILD)
 /*
- * On A38x switching the regs base address without running from
- * SDRAM doesn't seem to work. So let the SPL still use the
- * default base address and switch to the new address in the
- * main u-boot later.
+ * The SPL U-Boot version still runs with the default
+ * address for the internal registers, configured by
+ * the BootROM. Only the main U-Boot version uses the
+ * new internal register base address, that also is
+ * required for the Linux kernel.
  */
 #define SOC_REGS_PHY_BASE  0xd000
 #else
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 4eeef2d..832df0a 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -36,19 +36,6 @@ void board_init_f(ulong dummy)
 {
int ret;
 
-#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT
-   /*
-* Only call arch_cpu_init() when not returning to the
-* Marvell BootROM, which is done when booting via
-* the xmodem protocol (kwboot tool). Otherwise the
-* internal register will get remapped and the BootROM
-* can't continue to run correctly.
-*/
-
-   /* Linux expects the internal registers to be at 0xf100 */
-   arch_cpu_init();
-#endif
-
/*
 * Pin muxing needs to be done before UART output, since
 * on A38x the UART pins need some re-muxing for output
-- 
2.6.4

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[U-Boot] [PATCH 13/14] arm: mvebu: Don't include "netdev.h" in cpu.c

[Stefan Roese]

This is not needed any more since the switch to DM / DTS network
initialization on MVEBU. Lets remove it, as it otherwise leads
to compilation warning when CONFIG_NET is not enabled.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
---
 arch/arm/mach-mvebu/cpu.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 1095f69..c9b9c77 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -5,7 +5,6 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
-- 
2.6.4

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[U-Boot] [PATCH 08/14] arm: mvebu: Don't disable cache at startup on Armada XP at all

[Stefan Roese]

This patch leaces the cache configuration untouched for the AXP in the
setup done by the BootROM. Resulting in the cache still being enabled
at the startup of U-Boot. This leads to a slightly faster boot to the
U-Boot prompt (or Linux of course).

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
---
 arch/arm/mach-mvebu/cpu.c | 25 +
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 071b13b..6c11609 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -246,13 +246,15 @@ int arch_cpu_init(void)
 * in the macros / defines in the U-Boot header (soc.h).
 */
 
-   /*
-* To fully release / unlock this area from cache, we need
-* to flush all caches and disable the L2 cache.
-*/
-   icache_disable();
-   dcache_disable();
-   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+   /*
+* To fully release / unlock this area from cache, we need
+* to flush all caches and disable the L2 cache.
+*/
+   icache_disable();
+   dcache_disable();
+   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   }
 
/*
 * We need to call mvebu_mbus_probe() before calling
@@ -399,14 +401,13 @@ void enable_caches(void)
 
 void v7_outer_cache_enable(void)
 {
-   struct pl310_regs *const pl310 =
-   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-
-   /* The L2 cache is already disabled at this point */
-
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+   struct pl310_regs *const pl310 =
+   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
u32 u;
 
+   /* The L2 cache is already disabled at this point */
+
/*
 * For Aurora cache in no outer mode, enable via the CP15
 * coprocessor broadcasting of cache commands to L2.
-- 
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[U-Boot] [PATCH 05/14] arm: mvebu: Add v7_outer_cache_disable function for AXP & A38x

[Stefan Roese]

Add functionality to correctly disable the L2 cache on the Armada XP
and 38x platforms.

Without this, booting into Linux on ClearFog (A38x) results in a hangup
without any output on the serial console at all. Even with earlyprintk
enabled.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
---
 arch/arm/mach-mvebu/cpu.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 74087e2..fd56c99 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -422,3 +422,11 @@ void v7_outer_cache_enable(void)
setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
}
 }
+
+void v7_outer_cache_disable(void)
+{
+   struct pl310_regs *const pl310 =
+   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
-- 
2.6.4

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[U-Boot] [PATCH v2] dm: core: Add option to configure an offset for the address translation

[Stefan Roese]

Some platforms need to ability to configure an offset to the standard
addresses extracted from the device-tree. This patch allows this by
adding a function to DM to configure this offset (if needed).

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
---
v2:
- Change translation_offset type from u32 to fdt_addr_t
- Add comments to function declarations

 drivers/core/device.c | 33 +
 drivers/core/root.c   | 32 
 include/dm/device.h   | 21 +
 3 files changed, 74 insertions(+), 12 deletions(-)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 758f390..41fbbc6 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -597,22 +597,31 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
 * Use the full-fledged translate function for complex
 * bus setups.
 */
-   return fdt_translate_address((void *)gd->fdt_blob,
+   addr = fdt_translate_address((void *)gd->fdt_blob,
 dev->of_offset, reg);
+   } else {
+   /*
+* Use the "simple" translate function for less complex
+* bus setups.
+*/
+   addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+   dev->parent->of_offset,
+   dev->of_offset, "reg",
+   0, NULL);
+   if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
+   if (device_get_uclass_id(dev->parent) ==
+   UCLASS_SIMPLE_BUS)
+   addr = simple_bus_translate(dev->parent, addr);
+   }
}
 
/*
-* Use the "simple" translate function for less complex
-* bus setups.
-*/
-   addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
-   dev->parent->of_offset,
-   dev->of_offset, "reg",
-   0, NULL);
-   if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
-   if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
-   addr = simple_bus_translate(dev->parent, addr);
-   }
+* Some platforms need a special address translation. Those
+* platforms (e.g. mvebu in SPL) can configure a translation
+* offset in the DM by calling dm_set_translation_offset() that
+* will get added to all addresses returned by dev_get_addr().
+*/
+   addr += dm_get_translation_offset();
 
return addr;
 #else
diff --git a/drivers/core/root.c b/drivers/core/root.c
index e7b1f24..bbf0d72 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -23,6 +23,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct root_priv {
+   fdt_addr_t translation_offset;
+};
+
 static const struct driver_info root_info = {
.name   = "root_driver",
 };
@@ -37,6 +41,33 @@ struct udevice *dm_root(void)
return gd->dm_root;
 }
 
+fdt_addr_t dm_get_translation_offset(void)
+{
+   struct udevice *root;
+
+   root = dm_root();
+   if (root) {
+   struct root_priv *priv = dev_get_priv(root);
+
+   return priv->translation_offset;
+   }
+
+   /* No offset as default */
+   return 0;
+}
+
+void dm_set_translation_offset(fdt_addr_t offs)
+{
+   struct udevice *root;
+
+   root = dm_root();
+   if (root) {
+   struct root_priv *priv = dev_get_priv(root);
+
+   priv->translation_offset = offs;
+   }
+}
+
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
 void fix_drivers(void)
 {
@@ -228,6 +259,7 @@ int dm_init_and_scan(bool pre_reloc_only)
 U_BOOT_DRIVER(root_driver) = {
.name   = "root_driver",
.id = UCLASS_ROOT,
+   .priv_auto_alloc_size = sizeof(struct root_priv),
 };
 
 /* This is the root uclass */
diff --git a/include/dm/device.h b/include/dm/device.h
index 7fb9935..d9fc7fb 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -776,4 +776,25 @@ static inline void devm_kfree(struct udevice *dev, void 
*ptr)
 
 #endif /* ! CONFIG_DEVRES */
 
+/**
+ * dm_set_translation_offset() - Set translation offset
+ * @offs: Translation offset
+ *
+ * Some platforms need a special address translation. Those
+ * platforms (e.g. mvebu in SPL) can configure a translation
+ * offset in the DM by calling this function. It will be
+ * added to all addresses returned in dev_get_addr().
+ */
+void dm_set_translation_offset(fdt_addr_t offs);
+
+/**
+ * dm_get_translation_offset() - Get translation offset
+ *
+ * This function returns the translation offset that can
+ * be configured by calling 

Re: [U-Boot] [PATCH V2] arm: novena: Switch novena to config_distro_bootcmd

[Stefano Babic]

Hi Vagrant,

On 13/12/2015 00:16, Vagrant Cascadian wrote:
> On 2015-11-24, Marek Vasut  wrote:
>> From: Vagrant Cascadian 
>>
>> Switch Novena to distro bootcmd
> 
> Anything remaining on this? Can we hope to see it in 2016.01?
> 
> 
>> so it can be used with debian easily.
> 
> I suspect other distros would appreciate this too. :)
> 

It was missed because it was assigned to Albert - I have picked it up.

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Marek Vasut]

On Monday, December 14, 2015 at 12:26:39 PM, Pavel Machek wrote:
> On Mon 2015-12-14 12:09:08, Marek Vasut wrote:
> > On Monday, December 14, 2015 at 08:54:38 AM, Pavel Machek wrote:
> > > (Please, trim your emails when replying)
> > > 
> > > > Try this:
> > > > 
> > > > mtdparts=1m(u-boot),256k(env1),256k(env2),14848k(boot),112m(root),-@1
> > > > 536k (UBI)
> > > > 
> > > > This will create overlapping partitions "boot,root" and "UBI" .
> > > 
> > > Just because you can does not mean that you should. This looks like a
> > > nasty trap for a user.
> > 
> > Please explain in detail why do you think so.
> 
> Please make a 200 page study of human psychology explaining that noone
> would ever be confused by two overlapping partitions :-).

Add a comment explaining the situation and reasoning behind that, problem 
solved.

Best regards,
Marek Vasut
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[U-Boot] [PATCH 04/14] arm: mvebu: Enable L2 cache on Armada XP

[Stefan Roese]

Until now, the L2 cache was never enabled again in U-Boot. To get
even better performance (bootup time), lets enable the L2 cache
in U-Boot. This code was taken from the Linux kernel.

A performance gain was measured on the DB-MV784MP-GP board by testing
with tftpboot and sata commands.

This patch also cleans up the L2 cache related code. And makes sure that
the L2 cache is only disabled once.

Please note that A38x still runs with L2 cache disabled. And needs
to be enabled for this SoC in a separate patch if needed or desired.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
---
 arch/arm/mach-mvebu/cpu.c | 34 +-
 1 file changed, 25 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 751dabc..74087e2 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -389,20 +389,36 @@ void scsi_init(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
-   struct pl310_regs *const pl310 =
-   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-
-   /* First disable L2 cache - may still be enable from BootROM */
-   if (mvebu_soc_family() == MVEBU_SOC_A38X)
-   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
 
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
 }
-#endif
+
+void v7_outer_cache_enable(void)
+{
+   struct pl310_regs *const pl310 =
+   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+   /* The L2 cache is already disabled at this point */
+
+   if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+   u32 u;
+
+   /*
+* For Aurora cache in no outer mode, enable via the CP15
+* coprocessor broadcasting of cache commands to L2.
+*/
+   asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
+   u |= BIT(8);/* Set the FW bit */
+   asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
+
+   isb();
+
+   /* Enable the L2 cache */
+   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   }
+}
-- 
2.6.4

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[U-Boot] [PATCH 01/14] arm: mvebu: db-mv784mp-gp: Switch from IDE to SATA support

[Stefan Roese]

Enable the newly introduced SATA driver for the Marvell AXP with DMA
support instead of the PIO-only IDE driver. This increases the
transfer speed. And is also more in-line with the Armada 38x
ports, which also use a SATA driver (AHCI) and the "sata" U-Boot
commands.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
---
 include/configs/db-mv784mp-gp.h | 34 +++---
 1 file changed, 7 insertions(+), 27 deletions(-)

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 886f313..65e78b8 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Stefan Roese 
+ * Copyright (C) 2014-2015 Stefan Roese 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -30,10 +30,10 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_SATA
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_TFTPPUT
@@ -67,32 +67,12 @@
 #define CONFIG_SYS_ALT_MEMTEST
 
 /* SATA support */
-#ifdef CONFIG_CMD_IDE
-#define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE
-
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
-
-#define CONFIG_SYS_ATA_REG_OFFSET  0x0100 /* Offset for register access */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_ALT_OFFSET  0x0100
-
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE  4
-
-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS  2
-#define CONFIG_SYS_IDE_MAXDEVICE   CONFIG_SYS_IDE_MAXBUS
-
-/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR   MVEBU_AXP_SATA_BASE
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
-
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA_MV
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_EFI_PARTITION
 #define CONFIG_DOS_PARTITION
-#endif /* CONFIG_CMD_IDE */
 
 /* PCIe support */
 #ifndef CONFIG_SPL_BUILD
-- 
2.6.4

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[U-Boot] [PATCH 03/14] arm: mvebu: db-mv784mp-gp: Enable cache command

[Stefan Roese]

Th cache command can be useful sometimes. So lets enable it on the
AXP eval board.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
---
 include/configs/db-mv784mp-gp.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 3fb0cfb..e988f02 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -27,6 +27,7 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH/* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_EXT2
-- 
2.6.4

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Re: [U-Boot] [U-Boot, v2, 6/7] mtd/st_smi: Use page sizes respective to flash

[Heiko Schocher]

Hello Vipin,

Am 06.12.2012 um 09:47 schrieb Vipin Kumar:

The page size is a flash dependent property and the driver was using a macro in
place of page size. This patch uses the proper page size wrt the flash device
connected on board

Signed-off-by: Vipin Kumar 
Acked-by: Stefan Roese 
---
  drivers/mtd/st_smi.c   | 41 +
  include/linux/mtd/st_smi.h |  1 -
  2 files changed, 33 insertions(+), 9 deletions(-)


I just stumbled over this old patch, it is in your patchserie:

[U-Boot] [PATCH resend 0/7] mtd/st_smi: Add fixes for smi driver
http://lists.denx.de/pipermail/u-boot/2012-December/141796.html

I just tried to apply this serie, but this patch fails. Is
the problem it fixes still existing? If so, could you please
rebase it and resend it?

Thanks! And sorry for the looong delay ...

bye,
Heiko


diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 5f67807..0ed6c0d 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -96,6 +96,25 @@ static struct flash_device flash_devices[] = {
  };

  /*
+ * get_flash_device - Return flash_device pointer for a particular device id
+ * @id: Device id
+ *
+ * Return flash_device pointer for a particular device id
+ */
+static struct flash_device *get_flash_device(u32 id)
+{
+   struct flash_device *flash_dev_p = _devices[0];
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(flash_devices); i++, flash_dev_p++) {
+   if (flash_dev_p->device_id == id)
+   return flash_dev_p;
+   }
+
+   return NULL;
+}
+
+/*
   * smi_wait_xfer_finish - Wait until TFF is set in status register
   * @timeout:   timeout in milliseconds
   *
@@ -361,20 +380,27 @@ static int smi_sector_erase(flash_info_t *info, unsigned 
int sector)

  /*
   * smi_write - Write to SMI flash
+ * @info:   flash info structure
   * @src_addr:  source buffer
   * @dst_addr:  destination buffer
   * @length:length to write in bytes
- * @bank:   bank base address
   *
   * Write to SMI flash
   */
-static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
-unsigned int length, ulong bank_addr)
+static int smi_write(flash_info_t *info, unsigned char *src_addr,
+   unsigned char *dst_addr, unsigned int length)
  {
+   struct flash_device *flash_device_p = get_flash_device(info->flash_id);
+   u32 page_size;
int banknum;
int issue_we;

-   switch (bank_addr) {
+   if (!flash_device_p)
+   return -EIO;
+
+   page_size = flash_device_p->pagesize;
+
+   switch (info->start[0]) {
case SMIBANK0_BASE:
banknum = BANK0;
break;
@@ -400,9 +426,9 @@ static int smi_write(unsigned char *src_addr, unsigned char 
*dst_addr,
/* Perform the write command */
while (length) {
int k;
-   unsigned int wlen = min(SFLASH_PAGE_SIZE, length);
+   unsigned int wlen = min(page_size, length);

-   if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
+   if (issue_we || (((ulong)(dst_addr) % page_size) == 0)) {
issue_we = 0;

if (smi_wait_till_ready(banknum,
@@ -444,8 +470,7 @@ static int smi_write(unsigned char *src_addr, unsigned char 
*dst_addr,
   */
  int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
  {
-   return smi_write(src, (unsigned char *)dest_addr, length,
-   info->start[0]);
+   return smi_write(info, src, (unsigned char *)dest_addr, length);
  }

  /*
diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h
index 04f81ea..5837493 100644
--- a/include/linux/mtd/st_smi.h
+++ b/include/linux/mtd/st_smi.h
@@ -108,7 +108,6 @@ struct flash_dev {
ushort sector_count;
  };

-#define SFLASH_PAGE_SIZE   0x100   /* flash page size */
  #define XFER_FINISH_TOUT  15  /* xfer finish timeout(in ms) */
  #define WMODE_TOUT15  /* write enable timeout(in ms) */




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Re: [U-Boot] [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.

[York Sun]

On 12/14/2015 06:35 PM, Yuan Yao-B46683 wrote:
> Hi York,
> 
> I'm sorry I'm late replies.
> 
> Thanks for reminding me.
> We have some investigates and then depend on the document we think both snoop 
> request and DVM are supported on those port.
> So we think the setting should be ok in here.
> 

I think your conclusion is correct but not your reasoning. I did some digging
myself. These registers (snoop control) have top two bits indicating if a slave
interface supports snoop and/or DVM messages. If the feature is disabled,
writing the enabling bit is ignored.

No more action for you.

York
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Re: [U-Boot] [PATCH] i2c: mxc: allow executing the code that only applies to i.MX platforms

[Gong Q . Y .]

> -Original Message-
> From: Sun York-R58495
> Sent: Monday, December 14, 2015 6:37 PM
> To: Gong Qianyu-B52263; u-boot@lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Fan Peng-B51431
> Subject: Re: [PATCH] i2c: mxc: allow executing the code that only applies
> to i.MX platforms
> 
> 
> 
> On 12/14/2015 06:23 PM, Gong Qianyu wrote:
> > The bus_i2c_init() is called before relocation and will assgin value
> > to a static variable. If U-Boot is then still running in a flash
> > device, it's theoretically not allowed to write data to flash without
> > an erasing operation. For i.MX platforms, the U-Boot is always running
> > in DDR.
> >
> > Actually it causes asynchronous error when the ARM64 system error
> > report is enabled and the flash write protect is set.
> >
> > Signed-off-by: Gong Qianyu 
> > ---
> >  drivers/i2c/mxc_i2c.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index
> > fa4c82f..4dddb83 100644
> > --- a/drivers/i2c/mxc_i2c.c
> > +++ b/drivers/i2c/mxc_i2c.c
> > @@ -581,8 +581,11 @@ void bus_i2c_init(int index, int speed, int unused,
> > return;
> > }
> >
> > +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
> > +   defined(CONFIG_MX6) || defined(CONFIG_MX7)
> > mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
> > mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
> > +#endif
> >
> 
> I also think using variable mxc_i2c_buses is problematic. But using ifdef
> doesn't look like a solution. I think this variable should be put into
> stack, or use malloc. It works with execution-in-place in read-only space.
> 
> York

But we don't know if the stack will be enough before relocation. For SD boot of 
LS1043A, 

there is now only 4KB for it and if the spl image is bigger in the future, the 
stack is 

smaller. So isn't leaving more stack(if possible) for necessary code better? 

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Re: [U-Boot] [PATCH V2 1/1] Revert "spi: fsl_qspi: Use GENMASK"

[Stefano Babic]

Hi Jagan, Marek, Troy,

On 11/12/2015 16:24, Marek Vasut wrote:
> On Friday, December 11, 2015 at 03:59:14 PM, Jagan Teki wrote:
>> On 11 December 2015 at 02:57, Troy Kisky  
> wrote:
>>> If GENMASK is REALLY desired, it should be GENMASK(23,0)
>>> But since GENMASK is obviously more confusing, let's just revert.
>>>
>>> This reverts commit bad490a24212c068c5b718b9189f47ea4075d078.
>>
>> Sorry, just fix genmask why revert? because driver author has no
>> complaint on this, please don't just say simply "more confusing" more
>> over I usually prefer reverting bug fix patches.
> 
> I also agree this GENMASK() crap is confusing.
> 

IMHO it is easier for me to check directly the mask, as relying to a
macro. But this is only my personal opinion.

On the other side, the GENMASK macro is taken from the kernel and it is
used by several SOCs, in U-Boot too. Maybe we like to see directly the
mask, but several users like use it and I should accept it. Both
solutions (fixing GENMASK or revert it) are fine with me.

Today a new patch was sent :

http://patchwork.ozlabs.org/patch/556361/

same issue, fixing the GENMASK().

Troy's patch was assigned to me, but it belongs to SPI's custodian, so I
move it to Jagan.


Best regards,
Stefano Babic

>>> Reviewed-by: Fabio Estevam 
>>> Signed-off-by: Troy Kisky 
>>>
>>> ---
>>> v2: add sign off/ reviewed by
>>> ---
>>>
>>>  drivers/spi/fsl_qspi.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
>>> index ed39114..dd7048a 100644
>>> --- a/drivers/spi/fsl_qspi.c
>>> +++ b/drivers/spi/fsl_qspi.c
>>> @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
>>>
>>>  #define TX_BUFFER_SIZE 0x40
>>>  #endif
>>>
>>> -#define OFFSET_BITS_MASK   GENMASK(24, 0)
>>> +#define OFFSET_BITS_MASK   0x00ff
>>>
>>>  #define FLASH_STATUS_WEL   0x02
>>>
>>> --
>>> 2.5.0
>>
>> thanks!
> 
> Best regards,
> Marek Vasut
> 


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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Marek Vasut]

On Monday, December 14, 2015 at 12:51:16 PM, Pavel Machek wrote:
> On Mon 2015-12-14 12:31:32, Marek Vasut wrote:
> > On Monday, December 14, 2015 at 12:26:39 PM, Pavel Machek wrote:
> > > On Mon 2015-12-14 12:09:08, Marek Vasut wrote:
> > > > On Monday, December 14, 2015 at 08:54:38 AM, Pavel Machek wrote:
> > > > > (Please, trim your emails when replying)
> > > > > 
> > > > > > Try this:
> > > > > > 
> > > > > > mtdparts=1m(u-boot),256k(env1),256k(env2),14848k(boot),112m(root)
> > > > > > ,-@1 536k (UBI)
> > > > > > 
> > > > > > This will create overlapping partitions "boot,root" and "UBI" .
> > > > > 
> > > > > Just because you can does not mean that you should. This looks like
> > > > > a nasty trap for a user.
> > > > 
> > > > Please explain in detail why do you think so.
> > > 
> > > Please make a 200 page study of human psychology explaining that noone
> > > would ever be confused by two overlapping partitions :-).
> > 
> > Add a comment explaining the situation and reasoning behind that, problem
> > solved.
> 
> We do partitions so that people don't overwrite data by
> mistake. Having overlapping partitions kind of defeats the purpose.

I'd expect that in case you are fiddling with MTD on a bootloader level, you
have at least a vague idea of what you are doing.

> Just because trap is documented does not mean that it is not
> nasty. 199.95 pages to go.

Do you have a better idea how to satisfy both sets of people, ones which want
kernel on a separate partition and ones which want to use single UBI volume
then ?

Best regards,
Marek Vasut
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[U-Boot] [PATCH 1/3] spi: fsl_qspi: fix an error of using GENMASK

[Gong Qianyu]

This commit fixes the change of bad490a24212c068c5b718b9189f47ea4075d078.

Signed-off-by: Gong Qianyu 
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ed39114..d8d37cd 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX_BUFFER_SIZE 0x40
 #endif
 
-#define OFFSET_BITS_MASK   GENMASK(24, 0)
+#define OFFSET_BITS_MASK   GENMASK(23, 0)
 
 #define FLASH_STATUS_WEL   0x02
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] include: Correct "requset" typoes in misc.h

[Robert P. J. Day]

Signed-off-by: Robert P. J. Day 

---

diff --git a/include/misc.h b/include/misc.h
index 7e9badf..2b78814 100644
--- a/include/misc.h
+++ b/include/misc.h
@@ -32,7 +32,7 @@ int misc_write(struct udevice *dev, int offset, void *buf, 
int size);
  *
  * @dev: the device
  * @request: command to be sent to the device
- * @buf: pointer to buffer related to the requset
+ * @buf: pointer to buffer related to the request
  * @return: 0 if OK, -ve on error
  */
 int misc_ioctl(struct udevice *dev, unsigned long request, void *buf);
@@ -70,7 +70,7 @@ struct misc_ops {
 *
 * @dev: the device
 * @request: command to be sent to the device
-* @buf: pointer to buffer related to the requset
+* @buf: pointer to buffer related to the request
 * @return: 0 if OK, -ve on error
 */
int (*ioctl)(struct udevice *dev, unsigned long request, void *buf);

-- 


Robert P. J. Day Ottawa, Ontario, CANADA
http://crashcourse.ca

Twitter:   http://twitter.com/rpjday
LinkedIn:   http://ca.linkedin.com/in/rpjday


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Re: [U-Boot] [PATCH] x86: Clean up SPI flash drivers in defconfig

[Bin Meng]

Hi Jagan,

On Tue, Dec 15, 2015 at 1:51 PM, Jagan Teki  wrote:
> Hi Bin,
>
> On 15 December 2015 at 10:48, Bin Meng  wrote:
>> Hi Jagan, Simon,
>>
>> On Tue, Dec 8, 2015 at 11:44 PM, Jagan Teki  wrote:
>>> On 8 December 2015 at 17:27, Bin Meng  wrote:
 Hi Jagan,

 On Fri, Dec 4, 2015 at 2:57 AM, Simon Glass  wrote:
> Hi,
>
> On 3 December 2015 at 06:27, Bin Meng  wrote:
>> Hi Jagan,
>>
>> On Thu, Dec 3, 2015 at 6:24 PM, Jagan Teki  wrote:
>>> Hi Bin,
>>>
>>> On 3 December 2015 at 10:14, Bin Meng  wrote:
 Hi Simon,

 On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass  wrote:
> +Jagan
>
> Hi Bin,
>
> On 1 December 2015 at 18:41, Bin Meng  wrote:
>>
>> Hi Simon,
>>
>> On Wed, Dec 2, 2015 at 12:32 AM, Simon Glass  
>> wrote:
>> > Hi Bin,
>> >
>> > On 28 November 2015 at 05:45, Bin Meng  wrote:
>> >> Every board has one dedicated type of SPI flash, hence it is
>> >> unnecessary to include multiple SPI flash drivers.
>> >>
>> >> For QEMU and coreboot (default build of coreboot is also QEMU),
>> >> SPI flash is not supported. Remove those SPI flash drivers.
>> >>
>> >> Signed-off-by: Bin Meng 
>> >> ---
>> >>
>> >>  configs/bayleybay_defconfig | 2 --
>> >>  configs/chromebook_link_defconfig   | 2 --
>> >>  configs/chromebox_panther_defconfig | 2 --
>> >>  configs/coreboot-x86_defconfig  | 4 
>> >>  configs/crownbay_defconfig  | 3 ---
>> >>  configs/galileo_defconfig   | 2 --
>> >>  configs/minnowmax_defconfig | 3 ---
>> >>  configs/qemu-x86_defconfig  | 4 
>> >>  8 files changed, 22 deletions(-)
>> >
>> > What is the benefit of this? I see it removes a few lines in a data
>> > table. Does it matter?
>>
>> Maybe we should ask the other way around, why do we create so many
>> flash driver Kconfig option? I believe the intention was footprint.
>> Besides the footprint issue, having just one flash driver in each
>> board makes it very clear instead of causing confusion. Looks other
>> board defconfig files only select one.
>>>
>>> Are you talking about flash vendor config or CONFIG_SPI_FLASH?
>>>
>>
>> Flash vendor config, as you see in this patch.
>>
>
> They are a hangover from when we had a separate driver for each one.
> Jagan put a lot of effort into removing all the semi-duplicated code.
>
> Maybe we should prune down these options?
>

 But if we already spent a lot of effort into removing all the
 semi-duplicated code, we should not have converted those flash driver
 to Kconfig options before.

 See commit d5af92315bb48740f16bf8817f38e227d3076905 "sf: kconfig: add
 kconfig options for spi flashes"

 I suspect we may remove most of these SPI flash macros, but at least
 SST flash macro should be kept since right now it is mixed in the
 generic driver with a special byte program and word program which is
 incompatible with other vendors' flashes.
>>>
>>> But there is some flash vendor specific code like quad enable bit,
>>> locking ops and finally about spi_flash_params table.
>>>
>>
>> I know. That's probably why adding all these SPI flash drivers don't
>> help at all because only one code path will take effect. And what I
>> did in this patch is to select one type of flash per board.
>
> So how about we group together 3-4 of the common ones, with no special
> features, into a 'CONFIG_SPI_FLASH_GENERIC'?
>

 Can you comment on this CONFIG_SPI_FLASH_GENERIC as Simon suggested?
>>>
>>> Good idea, but if we don't find enough foot-print difference on no
>>> feature flags may be we can remove those config items and I have a
>>> plan to re-arrange the sf_param_table which suits Linux may be I will
>>> come back about these things.
>>>
>>
>> Can you please suggest which way should we go for this patch? I still
>> prefer one board with one SPI flash macro.
>
> Sorry, I didn't get you what do you mean by one board with one SPI
> flash macro? Suppose if board have one controller connected with micro
> flash then the board file include CONFIG_SPI_FLASH_STMICRO and if
> another board having two controllers one connected with spansion and
> other connected with micro then the board file include
> CONFIG_SPI_FLASH_STMICRO, 

Re: [U-Boot] [PATCH] x86: Clean up SPI flash drivers in defconfig

[Bin Meng]

Hi Jagan,

On Tue, Dec 15, 2015 at 2:15 PM, Jagan Teki  wrote:
> Hi Bin,
>
>
> On Tuesday 15 December 2015 11:37 AM, Bin Meng wrote:
>>
>> Hi Jagan,
>>
>> On Tue, Dec 15, 2015 at 1:51 PM, Jagan Teki  wrote:
>>>
>>> Hi Bin,
>>>
>>> On 15 December 2015 at 10:48, Bin Meng  wrote:

 Hi Jagan, Simon,

 On Tue, Dec 8, 2015 at 11:44 PM, Jagan Teki  wrote:
>
> On 8 December 2015 at 17:27, Bin Meng  wrote:
>>
>> Hi Jagan,
>>
>> On Fri, Dec 4, 2015 at 2:57 AM, Simon Glass  wrote:
>>>
>>> Hi,
>>>
>>> On 3 December 2015 at 06:27, Bin Meng  wrote:

 Hi Jagan,

 On Thu, Dec 3, 2015 at 6:24 PM, Jagan Teki 
 wrote:
>
> Hi Bin,
>
> On 3 December 2015 at 10:14, Bin Meng  wrote:
>>
>> Hi Simon,
>>
>> On Thu, Dec 3, 2015 at 5:05 AM, Simon Glass 
>> wrote:
>>>
>>> +Jagan
>>>
>>> Hi Bin,
>>>
>>> On 1 December 2015 at 18:41, Bin Meng  wrote:


 Hi Simon,

 On Wed, Dec 2, 2015 at 12:32 AM, Simon Glass 
 wrote:
>
> Hi Bin,
>
> On 28 November 2015 at 05:45, Bin Meng 
> wrote:
>>
>> Every board has one dedicated type of SPI flash, hence it is
>> unnecessary to include multiple SPI flash drivers.
>>
>> For QEMU and coreboot (default build of coreboot is also
>> QEMU),
>> SPI flash is not supported. Remove those SPI flash drivers.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>   configs/bayleybay_defconfig | 2 --
>>   configs/chromebook_link_defconfig   | 2 --
>>   configs/chromebox_panther_defconfig | 2 --
>>   configs/coreboot-x86_defconfig  | 4 
>>   configs/crownbay_defconfig  | 3 ---
>>   configs/galileo_defconfig   | 2 --
>>   configs/minnowmax_defconfig | 3 ---
>>   configs/qemu-x86_defconfig  | 4 
>>   8 files changed, 22 deletions(-)
>
>
> What is the benefit of this? I see it removes a few lines in a
> data
> table. Does it matter?


 Maybe we should ask the other way around, why do we create so
 many
 flash driver Kconfig option? I believe the intention was
 footprint.
 Besides the footprint issue, having just one flash driver in
 each
 board makes it very clear instead of causing confusion. Looks
 other
 board defconfig files only select one.
>
>
> Are you talking about flash vendor config or CONFIG_SPI_FLASH?
>

 Flash vendor config, as you see in this patch.

>>>
>>> They are a hangover from when we had a separate driver for each
>>> one.
>>> Jagan put a lot of effort into removing all the semi-duplicated
>>> code.
>>>
>>> Maybe we should prune down these options?
>>>
>>
>> But if we already spent a lot of effort into removing all the
>> semi-duplicated code, we should not have converted those flash
>> driver
>> to Kconfig options before.
>>
>> See commit d5af92315bb48740f16bf8817f38e227d3076905 "sf: kconfig:
>> add
>> kconfig options for spi flashes"
>>
>> I suspect we may remove most of these SPI flash macros, but at
>> least
>> SST flash macro should be kept since right now it is mixed in the
>> generic driver with a special byte program and word program which
>> is
>> incompatible with other vendors' flashes.
>
>
> But there is some flash vendor specific code like quad enable bit,
> locking ops and finally about spi_flash_params table.
>

 I know. That's probably why adding all these SPI flash drivers don't
 help at all because only one code path will take effect. And what I
 did in this patch is to select one type of flash per board.
>>>
>>>
>>> So how about we group together 3-4 of the common ones, with no
>>> special
>>> features, into a 'CONFIG_SPI_FLASH_GENERIC'?
>>>
>>
>> Can you comment on this CONFIG_SPI_FLASH_GENERIC as Simon suggested?
>
>
> Good idea, but if we 

Re: [U-Boot] [PATCH 2/3] sf: Use BIT macro

[Jagan Teki]

On 15 December 2015 at 09:48, Bin Meng  wrote:
> On Tue, Dec 15, 2015 at 1:03 AM, Jagan Teki  wrote:
>> Used BIT macro like 1 << nr as BIT(nr) where nr is 0...n
>>
>> Cc: Bin Meng 
>> Signed-off-by: Jagan Teki 
>> ---
>
> Reviewed-by: Bin Meng 

Applied to u-boot-spi/master

thanks!
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Re: [U-Boot] [PATCH v2 3/3] sf: Remove spi_flash_remove

[Jagan Teki]

On 5 November 2015 at 23:55, Simon Glass  wrote:
> On 23 October 2015 at 21:54, Jagan Teki  wrote:
>> Use direct call to device_remove instead of exctra
>> spi_flash_remove defination.
>>
>> Cc: Simon Glass 
>> Signed-off-by: Jagan Teki 
>> ---
>> Changes for v2:
>> - none
>>
>>  drivers/mtd/spi/sf-uclass.c | 7 +--
>>  include/spi_flash.h | 2 --
>>  2 files changed, 1 insertion(+), 8 deletions(-)
>>
>
> Reviewed-by: Simon Glass 

Applied to u-boot-spi/master

thanks!
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Re: [U-Boot] [PATCH 2/2] sf: Rename bank_end to bar_end in read_bar

[Jagan Teki]

On 13 December 2015 at 23:17, Jagan Teki  wrote:
> bar_end gives more meaningfull compared to bank_end and
> spi_flash_write_bar uses bar_end so replaced bank_end with
> bar_end in spi_flash_read_bar
>
> Signed-off-by: Jagan Teki 
> ---

Applied to u-boot-spi/master

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Re: [U-Boot] [PATCH 2/3] serial: uartlite: Add support for debug console

[Michal Simek]

Hi,

On 14.12.2015 14:14, Thomas Chou wrote:
> Hi Michal,
> 
> On 2015年12月11日 19:54, Michal Simek wrote:
>> Signed-off-by: Michal Simek 
>> ---
>>
>>   drivers/serial/Kconfig|  7 +++
>>   drivers/serial/serial_xuartlite.c | 23 +++
>>   2 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>> index 1fc287ee98ec..f1e221799b81 100644
>> --- a/drivers/serial/Kconfig
>> +++ b/drivers/serial/Kconfig
>> @@ -92,6 +92,13 @@ config DEBUG_UART_S5P
>> will need to provide parameters to make this work. The driver
>> will
>> be available until the real driver-model serial is running.
>>
>> +config DEBUG_UART_UARTLITE
>> +bool "Xilinx Uartlite"
>> +help
>> +  Select this to enable a debug UART using the serial_uartlite
>> driver.
>> +  You will need to provide parameters to make this work. The
>> driver will
>> +  be available until the real driver-model serial is running.
>> +
>>   config DEBUG_UART_ZYNQ
>>   bool "Xilinx Zynq"
>>   help
>> diff --git a/drivers/serial/serial_xuartlite.c
>> b/drivers/serial/serial_xuartlite.c
>> index 10089f5a34b5..fe87b515d902 100644
>> --- a/drivers/serial/serial_xuartlite.c
>> +++ b/drivers/serial/serial_xuartlite.c
>> @@ -120,3 +120,26 @@ U_BOOT_DRIVER(serial_uartlite) = {
>>   .ops= _serial_ops,
>>   .flags = DM_FLAG_PRE_RELOC,
>>   };
>> +
>> +#ifdef CONFIG_DEBUG_UART_UARTLITE
> 
> Better move the "#include " here.

This is the patch I sent some days ago about removing it from this
location and it was Reviewed twice.
http://lists.denx.de/pipermail/u-boot/2015-December/236341.html

> 
>> +void _debug_uart_init(void)
> 
> Please add "static inline" to void _debug_uart_init(void).

Ok. Will fix this for uartlite and zynq uart in follow up patch.


>> +{
>> +struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
>> +
>> +out_be32(>control, 0);
>> +out_be32(>control, ULITE_CONTROL_RST_RX |
>> ULITE_CONTROL_RST_TX);
>> +in_be32(>control);
>> +}
>> +
>> +static inline void _debug_uart_putc(int ch)
>> +{
>> +struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
>> +
>> +while (in_be32(>status) & SR_TX_FIFO_FULL)
>> +WATCHDOG_RESET();
> 
> WATCHDOG_RESET() is not really needed for debug serial output.

TBH I don't think so. There could be watchdog running from early
bootloader and needs to be service even for debugging purpose.

Thanks,
Michal
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Re: [U-Boot] [PATCH 1/3] serial: uartlite: Move driver to DM

[Michal Simek]

On 14.12.2015 15:47, Thomas Chou wrote:
> Hi Michal,
> 
> On 2015年12月11日 19:54, Michal Simek wrote:
>> Enable SPL DM too.
>>
>> Signed-off-by: Michal Simek 
>> ---
>>
>>   arch/microblaze/Kconfig  |   1 +
>>   configs/microblaze-generic_defconfig |   2 +
>>   doc/driver-model/serial-howto.txt|   1 -
>>   drivers/serial/serial_xuartlite.c| 176
>> ++-
>>   4 files changed, 71 insertions(+), 109 deletions(-)
>>
>> diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
>> index 604f6815af5b..30ea484f48aa 100644
>> --- a/arch/microblaze/Kconfig
>> +++ b/arch/microblaze/Kconfig
>> @@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC
>>   select SUPPORT_SPL
>>   select OF_CONTROL
>>   select DM
>> +select DM_SERIAL
>>
>>   endchoice
>>
>> diff --git a/configs/microblaze-generic_defconfig
>> b/configs/microblaze-generic_defconfig
>> index 54aa3ef3d26f..5df080b6a87c 100644
>> --- a/configs/microblaze-generic_defconfig
>> +++ b/configs/microblaze-generic_defconfig
>> @@ -1,9 +1,11 @@
>>   CONFIG_MICROBLAZE=y
>>   CONFIG_SPL_SYS_MALLOC_SIMPLE=y
>> +CONFIG_SPL_DM=y
>>   CONFIG_TARGET_MICROBLAZE_GENERIC=y
>>   CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
>>   CONFIG_SPL=y
>>   CONFIG_SYS_PROMPT="U-Boot-mONStR> "
>>   CONFIG_CMD_GPIO=y
>>   # CONFIG_CMD_SETEXPR is not set
>> +CONFIG_SPL_OF_CONTROL=y
>>   CONFIG_OF_EMBED=y
>> diff --git a/doc/driver-model/serial-howto.txt
>> b/doc/driver-model/serial-howto.txt
>> index 60483a4c49bc..6688abc4d9e3 100644
>> --- a/doc/driver-model/serial-howto.txt
>> +++ b/doc/driver-model/serial-howto.txt
>> @@ -19,7 +19,6 @@ is time for maintainers to start converting over the
>> remaining serial drivers:
>>  serial_s3c24x0.c
>>  serial_sa1100.c
>>  serial_stm32.c
>> -   serial_xuartlite.c
>>  usbtty.c
>>
>>   You should complete this by the end of January 2016.
>> diff --git a/drivers/serial/serial_xuartlite.c
>> b/drivers/serial/serial_xuartlite.c
>> index 988438e75471..10089f5a34b5 100644
>> --- a/drivers/serial/serial_xuartlite.c
>> +++ b/drivers/serial/serial_xuartlite.c
>> @@ -1,5 +1,5 @@
>>   /*
>> - * (C) Copyright 2008-2011 Michal Simek 
>> + * (C) Copyright 2008 - 2015 Michal Simek 
>>* Clean driver and add xilinx constant from header file
>>*
>>* (C) Copyright 2004 Atmark Techno, Inc.
>> @@ -10,11 +10,17 @@
>>
>>   #include 
>>   #include 
>> +#include 
> 
> Move to debug uart section.
> 
>> +#include 
>>   #include 
>>   #include 
>>   #include 
>> +#include 
> 
> watchdog.h is not needed.

ok these two should be added when debug_uart is added.
The rest is in the second reply.

> 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>>
>>   #define SR_TX_FIFO_FULL0x08 /* transmit FIFO full */
>> +#define SR_TX_FIFO_EMPTY0x04 /* transmit FIFO empty */
>>   #define SR_RX_FIFO_VALID_DATA0x01 /* data in receive FIFO */
>>   #define SR_RX_FIFO_FULL0x02 /* receive FIFO full */
>>
>> @@ -28,135 +34,89 @@ struct uartlite {
>>   unsigned int control;
>>   };
>>
>> -static struct uartlite *userial_ports[4] = {
>> -#ifdef XILINX_UARTLITE_BASEADDR
>> -[0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
>> -#endif
>> -#ifdef XILINX_UARTLITE_BASEADDR1
>> -[1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
>> -#endif
>> -#ifdef XILINX_UARTLITE_BASEADDR2
>> -[2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
>> -#endif
>> -#ifdef XILINX_UARTLITE_BASEADDR3
>> -[3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
>> -#endif
>> +struct uartlite_priv {
>> +struct uartlite *regs;
>>   };
>>
>> -static void uartlite_serial_putc(const char c, const int port)
>> +static int uartlite_serial_putc(struct udevice *dev, const char ch)
>>   {
>> -struct uartlite *regs = userial_ports[port];
>> +struct uartlite_priv *priv = dev_get_priv(dev);
>> +struct uartlite *regs = priv->regs;
>>
>> -if (c == '\n')
>> -uartlite_serial_putc('\r', port);
>> +if (in_be32(>status) & SR_TX_FIFO_FULL)
>> +return -EAGAIN;
>>
>> -while (in_be32(>status) & SR_TX_FIFO_FULL)
>> -;
>> -out_be32(>tx_fifo, c & 0xff);
>> -}
>> +out_be32(>tx_fifo, ch & 0xff);
>>
>> -static void uartlite_serial_puts(const char *s, const int port)
>> -{
>> -while (*s)
>> -uartlite_serial_putc(*s++, port);
>> +return 0;
>>   }
>>
>> -static int uartlite_serial_getc(const int port)
>> +static int uartlite_serial_getc(struct udevice *dev)
>>   {
>> -struct uartlite *regs = userial_ports[port];
>> +struct uartlite_priv *priv = dev_get_priv(dev);
>> +struct uartlite *regs = priv->regs;
>> +
>> +if (!(in_be32(>status) & SR_RX_FIFO_VALID_DATA))
>> +return -EAGAIN;
>>
>> -while (!(in_be32(>status) & SR_RX_FIFO_VALID_DATA))
>> -;
>>   return in_be32(>rx_fifo) & 0xff;
>>   }
>>
>> -static int uartlite_serial_tstc(const int port)
>> +static int 

Re: [U-Boot] [PATCH v3 2/5] spi: make mode visible to both dm and non-dm

[Bin Meng]

Hi Jagan,

On Mon, Dec 14, 2015 at 4:49 PM, Jagan Teki  wrote:
> Couldn't find the exact reason to define 'mode' for dm,
> probably it is not using in non-dm drivers but it need
> to visible both dm and non-dm as mode data is getting
> dereferred in spi flash core ie common to both.
>
> Cc: Bin Meng 
> Cc: Simon Glass 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3: make mode as uint
> Changes for v2: none
>
>  include/spi.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/spi.h b/include/spi.h
> index b4d2723..05202d0 100644
> --- a/include/spi.h
> +++ b/include/spi.h
> @@ -99,13 +99,13 @@ struct dm_spi_slave_platdata {
>   *
>   * @dev:   SPI slave device
>   * @max_hz:Maximum speed for this slave
> - * @mode:  SPI mode to use for this slave (see SPI mode flags)
>   * @speed: Current bus speed. This is 0 until the bus is first
>   * claimed.
>   * @bus:   ID of the bus that the slave is attached to. For
>   * driver model this is the sequence number of the SPI
>   * bus (bus->seq) so does not need to be stored
>   * @cs:ID of the chip select connected to the slave.
> + * @mode:  SPI mode to use for this slave (see SPI mode flags)
>   * @op_mode_rx:SPI RX operation mode.
>   * @op_mode_tx:SPI TX operation mode.
>   * @wordlen:   Size of SPI word in number of bits
> @@ -120,11 +120,11 @@ struct spi_slave {
> struct udevice *dev;/* struct spi_slave is dev->parentdata */
> uint max_hz;
> uint speed;
> -   uint mode;
>  #else
> unsigned int bus;
> unsigned int cs;
>  #endif
> +   uint mode;
> u8 op_mode_rx;
> u8 op_mode_tx;
> unsigned int wordlen;
> --

Can you please send all v3? I see you used to send just partial patch
series to the mailing list, but I don't think that's good for people
to test the whole series, especially for those who have not been
tracking the series from the beginning.

For this case, after I applied the v3 2/5 patch, then applied the v2
3/5 patch, I got:

Applying: spi: Use mode instead of op_mode_tx
error: patch failed: include/spi.h:126
error: include/spi.h: patch does not apply
Patch failed at 0001 spi: Use mode instead of op_mode_tx
The copy of the patch that failed is found in:
   ~/work/git/u-boot/.git/rebase-apply/patch
When you have resolved this problem, run "git am --resolved".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Regards,
Bin
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[U-Boot] [PATCH 2/3] spi: fsl_qspi: fix compile warning for 64-bit platform

[Gong Qianyu]

This patch fixes the following compile warning:
drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe':
drivers/spi/fsl_qspi.c:937:15:
  warning: cast to pointer from integer of different size
 [-Wint-to-pointer-cast]
  priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
   ^
Signed-off-by: Gong Qianyu 

Signed-off-by: Gong Qianyu 
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index d8d37cd..755cc27 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -931,7 +931,7 @@ static int fsl_qspi_probe(struct udevice *bus)
 
dm_spi_bus->max_hz = plat->speed_hz;
 
-   priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
+   priv->regs = (struct fsl_qspi_regs *)(unsigned long)plat->reg_base;
priv->flags = plat->flags;
 
priv->speed_hz = plat->speed_hz;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3] dm: core: Add option to configure an offset for the address translation

[Stefan Roese]

Some platforms need to ability to configure an offset to the standard
addresses extracted from the device-tree. This patch allows this by
adding a function to DM to configure this offset (if needed).

Signed-off-by: Stefan Roese 
Acked-by: Simon Glass 
Cc: Simon Glass 
---
v3:
- Add comment to variable desclaration
- Remove unnecessary checks for "!root"

v2:
- Change translation_offset type from u32 to fdt_addr_t
- Add comments to function declarations

 drivers/core/device.c | 33 +
 drivers/core/root.c   | 21 +
 include/dm/device.h   | 21 +
 3 files changed, 63 insertions(+), 12 deletions(-)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 758f390..41fbbc6 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -597,22 +597,31 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
 * Use the full-fledged translate function for complex
 * bus setups.
 */
-   return fdt_translate_address((void *)gd->fdt_blob,
+   addr = fdt_translate_address((void *)gd->fdt_blob,
 dev->of_offset, reg);
+   } else {
+   /*
+* Use the "simple" translate function for less complex
+* bus setups.
+*/
+   addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+   dev->parent->of_offset,
+   dev->of_offset, "reg",
+   0, NULL);
+   if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
+   if (device_get_uclass_id(dev->parent) ==
+   UCLASS_SIMPLE_BUS)
+   addr = simple_bus_translate(dev->parent, addr);
+   }
}
 
/*
-* Use the "simple" translate function for less complex
-* bus setups.
-*/
-   addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
-   dev->parent->of_offset,
-   dev->of_offset, "reg",
-   0, NULL);
-   if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
-   if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
-   addr = simple_bus_translate(dev->parent, addr);
-   }
+* Some platforms need a special address translation. Those
+* platforms (e.g. mvebu in SPL) can configure a translation
+* offset in the DM by calling dm_set_translation_offset() that
+* will get added to all addresses returned by dev_get_addr().
+*/
+   addr += dm_get_translation_offset();
 
return addr;
 #else
diff --git a/drivers/core/root.c b/drivers/core/root.c
index e7b1f24..13c2713 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -23,6 +23,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct root_priv {
+   fdt_addr_t translation_offset;  /* optional translation offset */
+};
+
 static const struct driver_info root_info = {
.name   = "root_driver",
 };
@@ -37,6 +41,22 @@ struct udevice *dm_root(void)
return gd->dm_root;
 }
 
+fdt_addr_t dm_get_translation_offset(void)
+{
+   struct udevice *root = dm_root();
+   struct root_priv *priv = dev_get_priv(root);
+
+   return priv->translation_offset;
+}
+
+void dm_set_translation_offset(fdt_addr_t offs)
+{
+   struct udevice *root = dm_root();
+   struct root_priv *priv = dev_get_priv(root);
+
+   priv->translation_offset = offs;
+}
+
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
 void fix_drivers(void)
 {
@@ -228,6 +248,7 @@ int dm_init_and_scan(bool pre_reloc_only)
 U_BOOT_DRIVER(root_driver) = {
.name   = "root_driver",
.id = UCLASS_ROOT,
+   .priv_auto_alloc_size = sizeof(struct root_priv),
 };
 
 /* This is the root uclass */
diff --git a/include/dm/device.h b/include/dm/device.h
index 7fb9935..d9fc7fb 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -776,4 +776,25 @@ static inline void devm_kfree(struct udevice *dev, void 
*ptr)
 
 #endif /* ! CONFIG_DEVRES */
 
+/**
+ * dm_set_translation_offset() - Set translation offset
+ * @offs: Translation offset
+ *
+ * Some platforms need a special address translation. Those
+ * platforms (e.g. mvebu in SPL) can configure a translation
+ * offset in the DM by calling this function. It will be
+ * added to all addresses returned in dev_get_addr().
+ */
+void dm_set_translation_offset(fdt_addr_t offs);
+
+/**
+ * dm_get_translation_offset() - Get translation offset
+ *
+ * This function returns the translation offset that can
+ * be configured by calling dm_set_translation_offset().
+ *
+ * @return 

Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Chin Liang See]

On Mon, 2015-12-14 at 02:25 +0100, Marek Vasut wrote:
> On Monday, December 14, 2015 at 02:22:32 AM, Chin Liang See wrote:
> 

[...]

> > > > and rethinking, we can have 2 MTD_PARTITION
> > > > where one for backward compatiblity (supporting raw) while
> > > > another
> > > > for
> > > > UBI.
> > > > 
> > > > MTDPARTS_RAW
> > > > 256k(spl),
> > > > 256k(env),
> > > > 15872k(boot),
> > > > -(rootfs)
> > > > 
> > > > MTDPARTS_UBI
> > > > 256k(spl),
> > > > 256k(env),
> > > > -(UBI)
> > > > 
> > > > We should make UBI as default then. If user care about backward
> > > > compatiblity, they shall use the MTDPARTS_RAW then.
> > > 
> > > Try this:
> > > 
> > > mtdparts=1m(u
> > > -boot),256k(env1),256k(env2),14848k(boot),112m(root),
> > > -@1536k(UBI)
> > > 
> > > This will create overlapping partitions "boot,root" and "UBI" .
> > 
> > Nice, let me give it a try.
> 
> Make sure to test it in Linux too ;-)
> 

Yeah, I can successfully mounted with ubifs :)

Just that I still have the issue with U-Boot ubifsmount although I
already applied the patch for cache ARMV7. I will take a look into ubi
code as I suspect its due to eraseblock size issue.

Thanks
Chin Liang

> Best regards,
> Marek Vasut
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[U-Boot] [PATCH] serial: Use static inline for _debug_uart_init()

[Michal Simek]

Reported-by: Thomas Chou 
Signed-off-by: Michal Simek 
---

 drivers/serial/serial_xuartlite.c | 2 +-
 drivers/serial/serial_zynq.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial_xuartlite.c 
b/drivers/serial/serial_xuartlite.c
index fe87b515d902..0238a52380c7 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -122,7 +122,7 @@ U_BOOT_DRIVER(serial_uartlite) = {
 };
 
 #ifdef CONFIG_DEBUG_UART_UARTLITE
-void _debug_uart_init(void)
+static inline void _debug_uart_init(void)
 {
struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
 
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index b2b98dea1561..3430482f8d8b 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -192,7 +192,7 @@ U_BOOT_DRIVER(serial_zynq) = {
 };
 
 #ifdef CONFIG_DEBUG_UART_ZYNQ
-void _debug_uart_init(void)
+static inline void _debug_uart_init(void)
 {
struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
 
-- 
1.9.1

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Re: [U-Boot] [PATCH 3/3] serial: uartlite: Add uartlite to Kconfig

[Michal Simek]

On 14.12.2015 15:35, Thomas Chou wrote:
> Hi Michal,
> 
> On 2015年12月11日 19:54, Michal Simek wrote:
>> - Move config option out of board file.
>> - Remove uartlite address from config file
>>
>> Signed-off-by: Michal Simek 
>> ---
>>
>>   board/xilinx/microblaze-generic/xparameters.h | 4 
>>   configs/microblaze-generic_defconfig  | 1 +
>>   drivers/serial/Kconfig| 7 +++
>>   include/configs/microblaze-generic.h  | 7 +--
>>   4 files changed, 9 insertions(+), 10 deletions(-)
>>
>> diff --git a/board/xilinx/microblaze-generic/xparameters.h
>> b/board/xilinx/microblaze-generic/xparameters.h
>> index 8ba146cb88db..11b3c9a4846e 100644
>> --- a/board/xilinx/microblaze-generic/xparameters.h
>> +++ b/board/xilinx/microblaze-generic/xparameters.h
>> @@ -28,10 +28,6 @@
>>   #define XILINX_TIMER_BASEADDR0x41c0
>>   #define XILINX_TIMER_IRQ0
>>
>> -/* Uart pheriphery is RS232_Uart */
>> -#define XILINX_UARTLITE_BASEADDR0x4060
>> -#define XILINX_UARTLITE_BAUDRATE115200
>> -
>>   /* IIC pheriphery is IIC_EEPROM */
>>   #define XILINX_IIC_0_BASEADDR0x4080
>>   #define XILINX_IIC_0_FREQ10
>> diff --git a/configs/microblaze-generic_defconfig
>> b/configs/microblaze-generic_defconfig
>> index 5df080b6a87c..9a7bb915466f 100644
>> --- a/configs/microblaze-generic_defconfig
>> +++ b/configs/microblaze-generic_defconfig
>> @@ -9,3 +9,4 @@ CONFIG_CMD_GPIO=y
>>   # CONFIG_CMD_SETEXPR is not set
>>   CONFIG_SPL_OF_CONTROL=y
>>   CONFIG_OF_EMBED=y
>> +CONFIG_XILINX_UARTLITE=y
>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>> index f1e221799b81..ddf49ba9cef3 100644
>> --- a/drivers/serial/Kconfig
>> +++ b/drivers/serial/Kconfig
>> @@ -230,4 +230,11 @@ config UNIPHIER_SERIAL
>> If you have a UniPhier based board and want to use the on-chip
>> serial ports, say Y to this option. If unsure, say N.
>>
>> +config XILINX_UARTLITE
>> +bool "Xilinx Uarlite support"
>> +depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
>> +help
>> +  If you have a Xilinx based board and want to use the uartlite
>> +  serial ports, say Y to this option. If unsure, say N.
>> +
>>   endmenu
> 
> Kconfig should be with the driver 1/3. Others are boards related.

It can be. Adding Kconfig fragment can be separate patch out of move to
DM. There is no connection too.
My intention was to show all related changes which are done by this one
step.

Thanks,
Michal



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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Chin Liang See]

On Mon, 2015-12-14 at 14:34 +0100, Marek Vasut wrote:
> On Monday, December 14, 2015 at 01:53:53 PM, Pavel Machek wrote:
> > On Mon 2015-12-14 13:20:28, Marek Vasut wrote:
> > > On Monday, December 14, 2015 at 12:51:16 PM, Pavel Machek wrote:

[..]

> I sense the overlapping partitions are a matter of taste here.
> 
> > > > Just because trap is documented does not mean that it is not
> > > > nasty. 199.95 pages to go.
> > > 
> > > Do you have a better idea how to satisfy both sets of people,
> > > ones which
> > > want kernel on a separate partition and ones which want to use
> > > single
> > > UBI volume then ?
> > 
> > If you expect people to read a comments explaining a situation, you
> > can easily add an explanation and (commented out) alternative
> > configutation that can be used.
> 
> I do not want to maintain multiple configurations, especially is
> there is
> known working alternative which covers all the usecases.
> 

I believe the boot command will abstract these different use cases. We
will have different command for qspiload_raw and qspiload which is the
default that utilize ubifsload. 

Thanks
Chin Liang

> Best regards,
> Marek Vasut
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[U-Boot] [PATCH] eeprom: fix eeprom write procedure

[Alexey Brodkin]

This fixes commit 1a37889b0ad084a740b4f785031d7ae9955d947b:
--->8
eeprom: Pull out the RW loop

Unify the code for doing read/write into single function, since the
code for both the read and write is almost identical. This again
trims down the code duplication.
--->8

where the same one routine is utilized for both EEPROM writing and
reading. The only difference was supposed to be a "read" flag which
in both cases was set with 1 somehow.

That lead to a missing delay in case of writing which lead to write
failure (in my case no data was written).

Signed-off-by: Alexey Brodkin 
Cc: Marek Vasut 
Cc: Simon Glass 
Cc: Tom Rini 
Cc: Heiko Schocher 
---
 common/cmd_eeprom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index 6eab1ea..571240a 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -197,7 +197,7 @@ int eeprom_write(unsigned dev_addr, unsigned offset,
 * We must write the address again when changing pages
 * because the address counter only increments within a page.
 */
-   ret = eeprom_rw(dev_addr, offset, buffer, cnt, 1);
+   ret = eeprom_rw(dev_addr, offset, buffer, cnt, 0);
 
eeprom_write_enable(dev_addr, 0);
return ret;
-- 
2.4.3

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