[U-Boot] Problem of git clone with http

[Jaehoon Chung]

Hi all,

I have fetched the u-boot/master with http, not git.
url = http://git.denx.de/u-boot.git

When i saw the gitweb, it seems that v2016.03 was released..
But i can't pull and fetch anything with http..

$ git pull
Already up-to-date.

$ git show origin/master
commit 077678eb0c226e52a1f90edabd3369ab26065b32
Merge: e69514c ab971e1
Author: Tom Rini 
Date:   Tue Jan 12 18:12:42 2016 -0500

Merge git://git.denx.de/u-boot-dm

$ git describe
v2016.01-39-g077678e

But on gitweb

Merge branch 'master' of git://git.denx.de/u-boot-tegra master
author  Tom Rini    
Wed, 30 Mar 2016 02:33:13 +0900 (13:33 -0400)
committer   Tom Rini    
Wed, 30 Mar 2016 02:33:13 +0900 (13:33 -0400)
commit  080c499df689e8c42df70de44502c0d71533dda8


There is difference..Does anybody know this problem?
Now, i can't use git protocol. So i need to use the "http".

I didn't test with "git"

Best Regards,
Jaehoon Chung
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[U-Boot] [PATCH v4 20/21] board: Add Qualcomm Dragonboard 410C support

[Mateusz Kulikowski]

This commit add support for 96Boards Dragonboard410C.
It is board based on APQ8016 Qualcomm SoC, complying with
96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC

U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.

Signed-off-by: Mateusz Kulikowski 
Tested-by: Simon Glass 

---

Changes in v4:
- Move CONFIG_OF_LIBFDT to defconfig and cleaned it up with savedefconfig

Changes in v3:
- readme: Added info on how to enter fastboot mode and that
  dtbTool is also part of skales. Added more explanation
  on image generation.
- head: Add comment why it's needed, drop MZ EFI signature
  that makes no sense on this particular SoC, fix confusing
  entry point name (+update .lds file)

Changes in v2:
- Renamed CONFIG_DM_SPMI -> CONFIG_SPMI
- Removed extra enter in dragonboard file
- Added ULPI* to defconfig
- Added MAINTAINERS to board
- Cleaned up config file - use distro defaults/environment:
  - Dropped multiple CONFIG_CMD* and other CONFIG_*
  - Added distro env/config
  - Dropped old boot commands
- Split dts - pm8916_gpio entries are taken directly from
  Linux Dragonboard dts; Add handles for u-boot in -uboot.dtsi;
  They will be removed once gpio drivers are converted to pinctrl.
- Renamed some pmic nodes, fixed dragonboard.c to find them properly.
- Added header and converted comments to c98-style in head.S
- Print error if pmic gpio node is not found.

Changes in v1:
- Add better help for dragonboard
- Move static structures to board_prepare_usb
- Add DM_SPMI to defconfig

 arch/arm/dts/Makefile|   2 +
 arch/arm/dts/dragonboard410c-uboot.dtsi  |  28 +
 arch/arm/dts/dragonboard410c.dts | 148 ++
 arch/arm/mach-snapdragon/Kconfig |  20 +++
 board/qualcomm/dragonboard410c/Kconfig   |  15 +++
 board/qualcomm/dragonboard410c/MAINTAINERS   |   6 +
 board/qualcomm/dragonboard410c/Makefile  |   8 ++
 board/qualcomm/dragonboard410c/dragonboard410c.c | 131 
 board/qualcomm/dragonboard410c/head.S|  34 +
 board/qualcomm/dragonboard410c/readme.txt|  71 +++
 board/qualcomm/dragonboard410c/u-boot.lds|  90 ++
 configs/dragonboard410c_defconfig|  26 
 include/configs/dragonboard410c.h| 150 +++
 13 files changed, 729 insertions(+)
 create mode 100644 arch/arm/dts/dragonboard410c-uboot.dtsi
 create mode 100644 arch/arm/dts/dragonboard410c.dts
 create mode 100644 board/qualcomm/dragonboard410c/Kconfig
 create mode 100644 board/qualcomm/dragonboard410c/MAINTAINERS
 create mode 100644 board/qualcomm/dragonboard410c/Makefile
 create mode 100644 board/qualcomm/dragonboard410c/dragonboard410c.c
 create mode 100644 board/qualcomm/dragonboard410c/head.S
 create mode 100644 board/qualcomm/dragonboard410c/readme.txt
 create mode 100644 board/qualcomm/dragonboard410c/u-boot.lds
 create mode 100644 configs/dragonboard410c_defconfig
 create mode 100644 include/configs/dragonboard410c.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 50bcc0b..5bd4b02 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -107,6 +107,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb
 
+dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
+
 dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi 
b/arch/arm/dts/dragonboard410c-uboot.dtsi
new file mode 100644
index 000..cc2c175
--- /dev/null
+++ b/arch/arm/dts/dragonboard410c-uboot.dtsi
@@ -0,0 +1,28 @@
+/*
+ * U-Boot addition to handle Dragonboard 410c pins
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+_gpios {
+   usb_hub_reset_pm {
+   gpios = <_gpios 2 0>;
+   };
+
+   usb_sw_sel_pm {
+   gpios = <_gpios 3 0>;
+   };
+};
+
+
+_pon {
+   key_vol_down {
+   gpios = <_pon 1 0>;
+   };
+
+   key_power {
+   gpios = <_pon 0 0>;
+   };
+};
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
new file mode 100644
index 000..7746622
--- /dev/null
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -0,0 +1,148 @@
+/*
+ * Qualcomm APQ8016 based Dragonboard 410C board device tree source
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+
+/ {
+   model = 

[U-Boot] [PATCH v4 19/21] arm: Add support for Qualcomm Snapdragon family

[Mateusz Kulikowski]

First supported chip is APQ8016 (that is compatible with MSM8916).
Drivers in SoC code:
- Reset controller (PSHOLD)
- Clock controller (very simple clock configuration for MMC and UART)

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 
---

Changes in v4:
- Add sysmap for apq8016 (required to enable MMU)

Changes in v3: None
Changes in v2:
- Rename DM_SPMI -> SPMI
- Make MND divider comments more compact :)
- p -> priv
- Add reviewed-by
- Reordered Kconfig to keep alphabetical order
- Renamed reset_sandbox -> msm_reset (typo in reset.c)

Changes in v1:
- Fix include order
- Cleanup defines (added spaces for readibility)
- Base address is integer to avoid casting
- Use setbits_* family where possible
- Drop unneded comments, added newlines where needed
- Check return value of dev_get_addr
- Add binding for apq8016
- Cleaned up divider calculation
- Drop most of gpio.h (only empty file is needed)

 arch/arm/Kconfig   |  12 +
 arch/arm/Makefile  |   1 +
 arch/arm/mach-snapdragon/Kconfig   |   6 +
 arch/arm/mach-snapdragon/Makefile  |   9 +
 arch/arm/mach-snapdragon/clock-apq8016.c   | 262 +
 arch/arm/mach-snapdragon/include/mach/gpio.h   |   9 +
 .../mach-snapdragon/include/mach/sysmap-apq8016.h  |  14 ++
 arch/arm/mach-snapdragon/reset.c   |  40 
 arch/arm/mach-snapdragon/sysmap-apq8016.c  |  30 +++
 9 files changed, 383 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/Kconfig
 create mode 100644 arch/arm/mach-snapdragon/Makefile
 create mode 100644 arch/arm/mach-snapdragon/clock-apq8016.c
 create mode 100644 arch/arm/mach-snapdragon/include/mach/gpio.h
 create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
 create mode 100644 arch/arm/mach-snapdragon/reset.c
 create mode 100644 arch/arm/mach-snapdragon/sysmap-apq8016.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9851065..fc0c03f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -511,6 +511,16 @@ config RMOBILE
bool "Renesas ARM SoCs"
select CPU_V7
 
+config ARCH_SNAPDRAGON
+   bool "Qualcomm Snapdragon SoCs"
+   select ARM64
+   select DM
+   select DM_GPIO
+   select DM_SERIAL
+   select SPMI
+   select OF_CONTROL
+   select OF_SEPARATE
+
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
@@ -774,6 +784,8 @@ source "arch/arm/mach-rockchip/Kconfig"
 
 source "arch/arm/mach-s5pc1xx/Kconfig"
 
+source "arch/arm/mach-snapdragon/Kconfig"
+
 source "arch/arm/mach-socfpga/Kconfig"
 
 source "arch/arm/mach-stm32/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6defdfb..bb2666c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -54,6 +54,7 @@ machine-$(CONFIG_ARCH_MVEBU)  += mvebu
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
 machine-$(CONFIG_ORION5X)  += orion5x
 machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
+machine-$(CONFIG_ARCH_SNAPDRAGON)  += snapdragon
 machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
 machine-$(CONFIG_ARCH_ROCKCHIP)+= rockchip
 machine-$(CONFIG_STM32)+= stm32
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
new file mode 100644
index 000..156e733
--- /dev/null
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -0,0 +1,6 @@
+if ARCH_SNAPDRAGON
+
+config SYS_SOC
+   default "snapdragon"
+
+endif
diff --git a/arch/arm/mach-snapdragon/Makefile 
b/arch/arm/mach-snapdragon/Makefile
new file mode 100644
index 000..4735844
--- /dev/null
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2015 Mateusz Kulikowski 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clock-apq8016.o
+obj-y += sysmap-apq8016.o
+obj-y += reset.o
diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c 
b/arch/arm/mach-snapdragon/clock-apq8016.c
new file mode 100644
index 000..d548d75
--- /dev/null
+++ b/arch/arm/mach-snapdragon/clock-apq8016.c
@@ -0,0 +1,262 @@
+/*
+ * Clock drivers for Qualcomm APQ8016
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * Based on Little Kernel driver, simplified
+ *
+ * SPDX-License-Identifier:BSD-3-Clause
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* GPLL0 clock control registers */
+#define GPLL0_STATUS0x2101C
+#define GPLL0_STATUS_ACTIVE BIT(17)
+
+#define APCS_GPLL_ENA_VOTE  0x45000
+#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
+
+/* vote reg for blsp1 clock */
+#define APCS_CLOCK_BRANCH_ENA_VOTE  0x45004
+#define APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1 BIT(10)
+
+/* SDC(n) clock control registers; n=1,2 */
+
+/* block control register */
+#define SDCC_BCR(n) ((n * 0x1000) + 

[U-Boot] [PATCH v4 21/21] Add myself as Snapdragon and SPMI maintainer

[Mateusz Kulikowski]

- Update MAINTAINERS
- Update git-mailrc

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch

Changes in v1: None

 MAINTAINERS| 11 +++
 doc/git-mailrc |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 32f97b2..6061139 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -125,6 +125,11 @@ F: arch/arm/mach-s5pc1xx/
 F: arch/arm/cpu/armv7/s5p-common/
 F: arch/arm/include/asm/arch-s3c24x0/
 
+ARM SNAPDRAGON
+M: Mateusz Kulikowski 
+S: Maintained
+F: arch/arm/mach-snapdragon/
+
 ARM STM SPEAR
 #M:Vipin Kumar 
 S: Orphaned (Since 2016-02)
@@ -396,6 +401,12 @@ F: drivers/mtd/spi/
 F: drivers/spi/
 F: include/spi*
 
+SPMI
+M: Mateusz Kulikowski 
+S: Maintained
+F: drivers/spmi/
+F: include/spmi/
+
 TQ GROUP
 #M:Martin Krause 
 S: Orphaned (Since 2016-02)
diff --git a/doc/git-mailrc b/doc/git-mailrc
index ced7085..1201d4a 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -33,6 +33,7 @@ alias lukma  Lukasz Majewski 
 alias macpaulMacpaul Lin 
 alias marex  Marek Vasut 
 alias masahiro   Masahiro Yamada 
+alias mateuszMateusz Kulikowski 
 alias monstr Michal Simek 
 alias panto  Pantelis Antoniou 
 alias prafulla   Prafulla Wadaskar 
@@ -67,6 +68,7 @@ alias rmobileuboot, iwamatsu
 alias s3csamsung
 alias s5pc   samsung
 alias samsunguboot, prom
+alias snapdragon uboot, mateusz
 alias socfpgauboot, marex, Dinh Nguyen 
 alias sunxi  uboot, ijc, jwrdegoede
 alias tegra  uboot, sjg, Tom Warren , Stephen 
Warren 
@@ -127,6 +129,7 @@ alias nand   uboot, scottwood
 alias netuboot, jhersh
 alias phyuboot, jhersh
 alias spiuboot, jagan
+alias spmi   uboot, mateusz
 alias ubiuboot, hs
 alias usbuboot, marex
 alias video  uboot, ag
-- 
2.5.0

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[U-Boot] [PATCH v4 17/21] pmic: Add support for Qualcomm PM8916 PMIC

[Mateusz Kulikowski]

This PMIC is connected on SPMI bus so needs SPMI support enabled.

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Add reviewed-by
- Reordered Kconfig & Makefile (to keep alphabetical ordering)
- Added link to dt binding @ help

Changes in v1:
- Added dt bindings
- Reoder includes
- Replaced extract_* macros with ordinary shift/mask
- Added error checking and whitespaces in probe

 doc/device-tree-bindings/pmic/pm8916.txt | 18 ++
 drivers/power/pmic/Kconfig   | 16 ++
 drivers/power/pmic/Makefile  |  1 +
 drivers/power/pmic/pm8916.c  | 96 
 4 files changed, 131 insertions(+)
 create mode 100644 doc/device-tree-bindings/pmic/pm8916.txt
 create mode 100644 drivers/power/pmic/pm8916.c

diff --git a/doc/device-tree-bindings/pmic/pm8916.txt 
b/doc/device-tree-bindings/pmic/pm8916.txt
new file mode 100644
index 000..15c598b
--- /dev/null
+++ b/doc/device-tree-bindings/pmic/pm8916.txt
@@ -0,0 +1,18 @@
+Qualcomm pm8916 PMIC
+
+This PMIC is connected using SPMI bus so should be child of SPMI bus 
controller.
+
+Required properties:
+- compatible: "qcom,spmi-pmic";
+- reg: SPMI Slave ID, size (ignored)
+- #address-cells: 0x1 (peripheral ID)
+- #size-cells: 0x1 (size of peripheral register space)
+
+Example:
+
+pm8916@0 {
+   compatible = "qcom,spmi-pmic";
+   reg = <0x0 0x1>;
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+};
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 7f69ae1..69f8d51 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -54,6 +54,22 @@ config DM_PMIC_MAX77686
This config enables implementation of driver-model pmic uclass features
for PMIC MAX77686. The driver implements read/write operations.
 
+config PMIC_PM8916
+   bool "Enable Driver Model for Qualcomm PM8916 PMIC"
+   depends on DM_PMIC
+   ---help---
+   The PM8916 is a PMIC connected to one (or several) processors
+   with SPMI bus. It has 2 slaves with several peripherals:
+   - 18x LDO
+   - 4x GPIO
+   - Power and Reset buttons
+   - Watchdog
+   - RTC
+   - Vibrator drivers
+   - Others
+
+   Driver binding info: doc/device-tree-bindings/pmic/pm8916.txt
+
 config PMIC_RK808
bool "Enable support for Rockchip PMIC RK808"
depends on DM_PMIC
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index c6e8d0c..52b4f71 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_PMIC_ACT8846) += act8846.o
+obj-$(CONFIG_PMIC_PM8916) += pm8916.o
 obj-$(CONFIG_PMIC_RK808) += rk808.o
 obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
diff --git a/drivers/power/pmic/pm8916.c b/drivers/power/pmic/pm8916.c
new file mode 100644
index 000..9acf5f5
--- /dev/null
+++ b/drivers/power/pmic/pm8916.c
@@ -0,0 +1,96 @@
+/*
+ * Qualcomm pm8916 pmic driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PID_SHIFT 8
+#define PID_MASK (0xFF << PID_SHIFT)
+#define REG_MASK 0xFF
+
+struct pm8916_priv {
+   uint16_t usid; /* Slave ID on SPMI bus */
+};
+
+static int pm8916_reg_count(struct udevice *dev)
+{
+   return 0x;
+}
+
+static int pm8916_write(struct udevice *dev, uint reg, const uint8_t *buff,
+   int len)
+{
+   struct pm8916_priv *priv = dev_get_priv(dev);
+
+   if (len != 1)
+   return -EINVAL;
+
+   return spmi_reg_write(dev->parent, priv->usid,
+ (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK,
+ *buff);
+}
+
+static int pm8916_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+   struct pm8916_priv *priv = dev_get_priv(dev);
+   int val;
+
+   if (len != 1)
+   return -EINVAL;
+
+   val = spmi_reg_read(dev->parent, priv->usid,
+   (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK);
+
+   if (val < 0)
+   return val;
+   *buff = val;
+   return 0;
+}
+
+static struct dm_pmic_ops pm8916_ops = {
+   .reg_count = pm8916_reg_count,
+   .read = pm8916_read,
+   .write = pm8916_write,
+};
+
+static const struct udevice_id pm8916_ids[] = {
+   { .compatible = "qcom,spmi-pmic" },
+   { }
+};
+
+static int pm8916_probe(struct udevice *dev)
+{
+   struct pm8916_priv *priv = dev_get_priv(dev);
+
+   priv->usid = dev_get_addr(dev);
+
+   

[U-Boot] [PATCH v4 15/21] spmi: Add sandbox test driver

[Mateusz Kulikowski]

This patch adds emulated spmi bus controller with part of
pm8916 pmic on it to sandbox and tests validating SPMI uclass.

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3:
- Updated test.dts to include SPMI like sandbox.dts does

Changes in v2:
- Rename CONFIG_DM_SPMI -> CONFIG_SPMI
- Rename r -> regs, p -> priv
- Add reviewed-by
- Update binding doc (drop unused bindig)

Changes in v1: None

 arch/sandbox/dts/sandbox.dts   |  20 
 arch/sandbox/dts/test.dts  |  20 
 configs/sandbox_defconfig  |   4 +
 doc/device-tree-bindings/spmi/spmi-sandbox.txt |  31 +
 drivers/spmi/Kconfig   |   8 ++
 drivers/spmi/Makefile  |   1 +
 drivers/spmi/spmi-sandbox.c| 157 +
 test/dm/Makefile   |   1 +
 test/dm/spmi.c | 115 ++
 9 files changed, 357 insertions(+)
 create mode 100644 doc/device-tree-bindings/spmi/spmi-sandbox.txt
 create mode 100644 drivers/spmi/spmi-sandbox.c
 create mode 100644 test/dm/spmi.c

diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index e3f02bf..2ae4014 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -240,6 +240,26 @@
status = "disabled";
};
 
+   spmi: spmi@0 {
+   compatible = "sandbox,spmi";
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+   pm8916@0 {
+   compatible = "qcom,spmi-pmic";
+   reg = <0x0 0x1>;
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+
+   spmi_gpios: gpios@c000 {
+   compatible = "qcom,pm8916-gpio";
+   reg = <0xc000 0x400>;
+   gpio-controller;
+   gpio-count = <4>;
+   #gpio-cells = <2>;
+   gpio-bank-name="spmi";
+   };
+   };
+   };
 };
 
 #include "cros-ec-keyboard.dtsi"
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 9b8d658..8930009 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -351,6 +351,26 @@
status = "disabled";
};
 
+   spmi: spmi@0 {
+   compatible = "sandbox,spmi";
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+   pm8916@0 {
+   compatible = "qcom,spmi-pmic";
+   reg = <0x0 0x1>;
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+
+   spmi_gpios: gpios@c000 {
+   compatible = "qcom,pm8916-gpio";
+   reg = <0xc000 0x400>;
+   gpio-controller;
+   gpio-count = <4>;
+   #gpio-cells = <2>;
+   gpio-bank-name="spmi";
+   };
+   };
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index d69c9fc..bfc8b61 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -31,6 +31,7 @@ CONFIG_ADC_SANDBOX=y
 CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_SANDBOX_GPIO=y
+CONFIG_PM8916_GPIO=y
 CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_LED=y
@@ -59,6 +60,9 @@ CONFIG_PINCONF=y
 CONFIG_PINCTRL_SANDBOX=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_SANDBOX=y
+CONFIG_PMIC_PM8916=y
+CONFIG_SPMI=y
+CONFIG_SPMI_SANDBOX=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_SANDBOX=y
 CONFIG_RAM=y
diff --git a/doc/device-tree-bindings/spmi/spmi-sandbox.txt 
b/doc/device-tree-bindings/spmi/spmi-sandbox.txt
new file mode 100644
index 000..8569a1a
--- /dev/null
+++ b/doc/device-tree-bindings/spmi/spmi-sandbox.txt
@@ -0,0 +1,31 @@
+Sandbox SPMI emulated arbiter.
+
+This is bus driver for Sandbox. It includes part of emulated pm8916 pmic.
+
+Required properties:
+- compatible: "sandbox,spmi"
+- #address-cells: 0x1 - childs slave ID address
+- #size-cells: 0x1
+
+Example:
+
+spmi: spmi@0 {
+   compatible = "sandbox,spmi";
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+   pm8916@0 {
+   compatible = "qcom,spmi-pmic";
+   reg = <0x0 0x1>;
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+
+   spmi_gpios: gpios@c000 {
+   compatible = "qcom,pm8916-gpio";
+   reg = <0xc000 0x400>;
+   gpio-controller;
+   gpio-count = <4>;
+   #gpio-cells = <2>;
+  

[U-Boot] [PATCH v4 18/21] gpio: Add support for Qualcomm PM8916 gpios

[Mateusz Kulikowski]

This driver supports GPIOs present on PM8916 PMIC.
There are 2 device drivers inside:
- GPIO driver (4 "generic" GPIOs)
- Keypad driver that presents itself as GPIO with 2 inputs (power and reset)

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Add Reviewed-by

Changes in v1:
- Add binding doc
- Fixed inlcude ordering
- Merged direction_input and direction_output functions
- gpio_get: use switch instead of stacked if
- use pmic_clrsetbits
- add possibility to change prwkey bank name
- Handle invalid bindings
- Sanity HW check (i.e. check type/subtype registers)

 doc/device-tree-bindings/gpio/pm8916_gpio.txt |  48 
 drivers/gpio/Kconfig  |  10 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/pm8916_gpio.c| 302 ++
 4 files changed, 361 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/pm8916_gpio.txt
 create mode 100644 drivers/gpio/pm8916_gpio.c

diff --git a/doc/device-tree-bindings/gpio/pm8916_gpio.txt 
b/doc/device-tree-bindings/gpio/pm8916_gpio.txt
new file mode 100644
index 000..58185b8
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/pm8916_gpio.txt
@@ -0,0 +1,48 @@
+Driver for part of pm8916 PMIC - gpio and power/reset keys
+
+This device should be child of SPMI pmic.
+
+1) GPIO driver
+
+Required properties:
+- compatible: "qcom,pm8916-gpio"
+- reg: peripheral ID, size of register block
+- gpio-controller
+- gpio-count: number of GPIOs
+- #gpio-cells: 2
+
+Optional properties:
+- gpio-bank-name: name of bank (as default "pm8916" is used)
+
+Example:
+
+pmic_gpios: gpios@c000 {
+   compatible = "qcom,pm8916-gpio";
+   reg = <0xc000 0x400>;
+   gpio-controller;
+   gpio-count = <4>;
+   #gpio-cells = <2>;
+   gpio-bank-name="pmic";
+};
+
+
+2) Power/Reset key driver
+
+Required properties:
+- compatible: "qcom,pm8916-pwrkey"
+- reg: peripheral ID, size of register block
+- gpio-controller
+- #gpio-cells: 2
+
+Optional properties:
+- gpio-bank-name: name of bank (as default "pm8916_key" is used)
+
+
+Example:
+
+pmic_pon: pon@800 {
+   compatible = "qcom,pm8916-pwrkey";
+   reg = <0x800 0x96>;
+   #gpio-cells = <2>;
+   gpio-controller;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 4d9e74c..f56a606 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -69,6 +69,16 @@ config MSM_GPIO
  - APQ8016
  - MSM8916
 
+config PM8916_GPIO
+   bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
+   depends on DM_GPIO && PMIC_PM8916
+   help
+ Support for GPIO pins and power/reset buttons found on
+ Qualcomm PM8916 PMIC.
+ Default name for GPIO bank is "pm8916".
+ Power and reset buttons are placed in "pm8916_key" bank and
+  have gpio numbers 0 and 1 respectively.
+
 config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4162c3c..4f071c4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_HIKEY_GPIO)  += hi6220_gpio.o
 obj-$(CONFIG_PIC32_GPIO)   += pic32_gpio.o
 obj-$(CONFIG_MVEBU_GPIO)   += mvebu_gpio.o
 obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
+obj-$(CONFIG_PM8916_GPIO)  += pm8916_gpio.o
diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/pm8916_gpio.c
new file mode 100644
index 000..1abab7f
--- /dev/null
+++ b/drivers/gpio/pm8916_gpio.c
@@ -0,0 +1,302 @@
+/*
+ * Qualcomm pm8916 pmic gpio driver - part of Qualcomm PM8916 PMIC
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offset for each gpio */
+#define REG_OFFSET(x)  ((x) * 0x100)
+
+/* Register maps */
+
+/* Type and subtype are shared for all pm8916 peripherals */
+#define REG_TYPE   0x4
+#define REG_SUBTYPE0x5
+
+#define REG_STATUS 0x08
+#define REG_STATUS_VAL_MASK0x1
+
+/* MODE_CTL */
+#define REG_CTL   0x40
+#define REG_CTL_MODE_MASK   0x70
+#define REG_CTL_MODE_INPUT  0x00
+#define REG_CTL_MODE_INOUT  0x20
+#define REG_CTL_MODE_OUTPUT 0x10
+#define REG_CTL_OUTPUT_MASK 0x0F
+
+#define REG_DIG_VIN_CTL0x41
+#define REG_DIG_VIN_VIN0   0
+
+#define REG_DIG_PULL_CTL   0x42
+#define REG_DIG_PULL_NO_PU 0x5
+
+#define REG_DIG_OUT_CTL0x45
+#define REG_DIG_OUT_CTL_CMOS   (0x0 << 4)
+#define REG_DIG_OUT_CTL_DRIVE_L 0x1
+
+#define REG_EN_CTL 0x46
+#define REG_EN_CTL_ENABLE  (1 << 7)
+
+struct pm8916_gpio_bank {
+   uint16_t pid; /* Peripheral ID on SPMI bus */
+};
+
+static int 

[U-Boot] [PATCH v4 14/21] drivers: Add SPMI bus uclass

[Mateusz Kulikowski]

Qualcom processors use proprietary bus to talk with PMIC devices -
SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's
multi-master and has simple autodetection capabilities.
This commit adds simple uclass that provides bus read/write interface.

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Use proper  entry order in Kconfig
- Rename CONFIG_DM_SPMI -> CONFIG_SPMI
- Fix header ordering
- Add reviewed-by

Changes in v1:
- Reorder includes
- Add read/write arguments documentation

 drivers/Kconfig|  2 ++
 drivers/Makefile   |  1 +
 drivers/spmi/Kconfig   | 10 ++
 drivers/spmi/Makefile  |  7 +++
 drivers/spmi/spmi-uclass.c | 48 ++
 include/dm/uclass-id.h |  1 +
 include/spmi/spmi.h| 47 +
 7 files changed, 116 insertions(+)
 create mode 100644 drivers/spmi/Kconfig
 create mode 100644 drivers/spmi/Makefile
 create mode 100644 drivers/spmi/spmi-uclass.c
 create mode 100644 include/spmi/spmi.h

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 70993fd..c82a94b 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -60,6 +60,8 @@ source "drivers/sound/Kconfig"
 
 source "drivers/spi/Kconfig"
 
+source "drivers/spmi/Kconfig"
+
 source "drivers/thermal/Kconfig"
 
 source "drivers/timer/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index e7eab66..6900097 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -54,6 +54,7 @@ obj-y += dfu/
 obj-$(CONFIG_X86) += pch/
 obj-y += rtc/
 obj-y += sound/
+obj-y += spmi/
 obj-y += timer/
 obj-y += tpm/
 obj-y += twserial/
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
new file mode 100644
index 000..0b9bd31
--- /dev/null
+++ b/drivers/spmi/Kconfig
@@ -0,0 +1,10 @@
+menu "SPMI support"
+
+config SPMI
+   bool "Enable SPMI bus support"
+   depends on DM
+   ---help---
+ Select this to enable to support SPMI bus.
+ SPMI (System Power Management Interface) bus is used
+ to connect PMIC devices on various SoCs.
+endmenu
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
new file mode 100644
index 000..99092eb
--- /dev/null
+++ b/drivers/spmi/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Mateusz Kulikowski 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPMI)  += spmi-uclass.o
diff --git a/drivers/spmi/spmi-uclass.c b/drivers/spmi/spmi-uclass.c
new file mode 100644
index 000..4ddd51b
--- /dev/null
+++ b/drivers/spmi/spmi-uclass.c
@@ -0,0 +1,48 @@
+/*
+ * SPMI bus uclass driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg)
+{
+   const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
+
+   if (!ops || !ops->read)
+   return -ENOSYS;
+
+   return ops->read(dev, usid, pid, reg);
+}
+
+int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
+  uint8_t value)
+{
+   const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
+
+   if (!ops || !ops->write)
+   return -ENOSYS;
+
+   return ops->write(dev, usid, pid, reg, value);
+}
+
+static int spmi_post_bind(struct udevice *dev)
+{
+   return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+UCLASS_DRIVER(spmi) = {
+   .id = UCLASS_SPMI,
+   .name   = "spmi",
+   .post_bind  = spmi_post_bind,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 37c4176..cbf9b2c 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -66,6 +66,7 @@ enum uclass_id {
UCLASS_RTC, /* Real time clock device */
UCLASS_SERIAL,  /* Serial UART */
UCLASS_SPI, /* SPI bus */
+   UCLASS_SPMI,/* System Power Management Interface bus */
UCLASS_SPI_FLASH,   /* SPI flash */
UCLASS_SPI_GENERIC, /* Generic SPI flash target */
UCLASS_SYSCON,  /* System configuration device */
diff --git a/include/spmi/spmi.h b/include/spmi/spmi.h
new file mode 100644
index 000..65a49bd
--- /dev/null
+++ b/include/spmi/spmi.h
@@ -0,0 +1,47 @@
+#ifndef _SPMI_SPMI_H
+#define _SPMI_SPMI_H
+
+/**
+ * struct dm_spmi_ops - SPMI device I/O interface
+ *
+ * Should be implemented by UCLASS_SPMI device drivers. The standard
+ * device operations provides the I/O interface for it's childs.
+ *
+ * @read:  read register 'reg' of slave 'usid' and peripheral 'pid'
+ * @write: write register 'reg' 

[U-Boot] [PATCH v4 16/21] drivers: spmi: Add support for Qualcomm SPMI bus driver

[Mateusz Kulikowski]

Support SPMI arbiter on Qualcomm Snapdragon devices.

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Rename DM_SPMI -> SPMI
- Rename p -> priv (in write/read)
- Fix header ordering (again)
- Add reviewed-by

Changes in v1:
- add binding documentation and better Kconfig help
- Changed a bit mapping
- Change include order
- Use clrsetbits* where possible
- Add one more supported dts id
- Handle missing fields in dt properly

 doc/device-tree-bindings/spmi/spmi-msm.txt |  26 
 drivers/spmi/Kconfig   |   7 +-
 drivers/spmi/Makefile  |   1 +
 drivers/spmi/spmi-msm.c| 189 +
 4 files changed, 222 insertions(+), 1 deletion(-)
 create mode 100644 doc/device-tree-bindings/spmi/spmi-msm.txt
 create mode 100644 drivers/spmi/spmi-msm.c

diff --git a/doc/device-tree-bindings/spmi/spmi-msm.txt 
b/doc/device-tree-bindings/spmi/spmi-msm.txt
new file mode 100644
index 000..ae47673
--- /dev/null
+++ b/doc/device-tree-bindings/spmi/spmi-msm.txt
@@ -0,0 +1,26 @@
+Qualcomm SPMI arbiter/bus driver
+
+This is bus driver for Qualcomm chips that use SPMI to communicate with PMICs.
+
+Required properties:
+- compatible: "qcom,spmi-pmic-arb"
+- reg: Register block adresses and sizes for various parts of device:
+   1) PMIC arbiter channel mapping base (PMIC_ARB_REG_CHNLn)
+   2) SPMI write command (master) registers (PMIC_ARB_CORE_SW_DEC_CHANNELS)
+   3) SPMI read command (observer) registers (PMIC_ARB_CORE_REGISTERS_OBS)
+
+Optional properties (if not set by parent):
+- #address-cells: 0x1 - childs slave ID address
+- #size-cells: 0x1
+
+All PMICs should be placed as a child nodes of bus arbiter.
+Automatic detection of childs is currently not supported.
+
+Example:
+
+spmi@200f000 {
+   compatible = "qcom,spmi-pmic-arb";
+   reg = <0x200f800 0x200 0x240 0x40 0x2c0 0x40>;
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+};
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index c70d675..8d25b45 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -8,11 +8,16 @@ config SPMI
  SPMI (System Power Management Interface) bus is used
  to connect PMIC devices on various SoCs.
 
+config SPMI_MSM
+   boolean "Support Qualcomm SPMI bus"
+   depends on SPMI
+   ---help---
+ Support SPMI bus implementation found on Qualcomm Snapdragon SoCs.
+
 config SPMI_SANDBOX
boolean "Support for Sandbox SPMI bus"
depends on SPMI
---help---
  Demo SPMI bus implementation. Emulates part of PM8916 as single
   slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3.
-
 endmenu
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
index 4ca65a9..c0b1220 100644
--- a/drivers/spmi/Makefile
+++ b/drivers/spmi/Makefile
@@ -5,4 +5,5 @@
 #
 
 obj-$(CONFIG_SPMI)  += spmi-uclass.o
+obj-$(CONFIG_SPMI_MSM) += spmi-msm.o
 obj-$(CONFIG_SPMI_SANDBOX) += spmi-sandbox.o
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
new file mode 100644
index 000..0cef505
--- /dev/null
+++ b/drivers/spmi/spmi-msm.c
@@ -0,0 +1,189 @@
+/*
+ * Qualcomm SPMI bus driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * Loosely based on Little Kernel driver
+ *
+ * SPDX-License-Identifier:BSD-3-Clause
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARB_CHANNEL_OFFSET(n)  (0x4 * (n))
+#define SPMI_CH_OFFSET(chnl)   ((chnl) * 0x8000)
+
+#define SPMI_REG_CMD0  0x0
+#define SPMI_REG_CONFIG0x4
+#define SPMI_REG_STATUS0x8
+#define SPMI_REG_WDATA 0x10
+#define SPMI_REG_RDATA 0x18
+
+#define SPMI_CMD_OPCODE_SHIFT  27
+#define SPMI_CMD_SLAVE_ID_SHIFT20
+#define SPMI_CMD_ADDR_SHIFT12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
+#define SPMI_CMD_BYTE_CNT_SHIFT0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG0x00
+#define SPMI_CMD_EXT_REG_READ_LONG 0x01
+
+#define SPMI_STATUS_DONE   0x1
+
+#define SPMI_MAX_CHANNELS  128
+#define SPMI_MAX_SLAVES16
+#define SPMI_MAX_PERIPH256
+
+struct msm_spmi_priv {
+   phys_addr_t arb_chnl; /* ARB channel mapping base */
+   phys_addr_t spmi_core; /* SPMI core */
+   phys_addr_t spmi_obs; /* SPMI observer */
+   /* SPMI channel map */
+   uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+};
+
+static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
+ uint8_t val)
+{
+   struct msm_spmi_priv *priv = dev_get_priv(dev);
+   unsigned channel;
+   uint32_t reg = 0;
+
+   if 

[U-Boot] [PATCH v4 10/21] usb: Rename ehci-fsl.h to ehci-ci.h

[Mateusz Kulikowski]

Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.

This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).

Signed-off-by: Mateusz Kulikowski 
Acked-by: Marek Vasut 
Tested-by: Simon Glass 
---

Changes in v4:
- Add missing renames (arch/* and board/*)

Changes in v3: None
Changes in v2:
- Add acked-by

Changes in v1: None

 arch/powerpc/cpu/mpc83xx/cpu_init.c   | 2 +-
 board/boundary/nitrogen6x/nitrogen6x.c| 2 +-
 board/denx/m53evk/m53evk.c| 2 +-
 board/freescale/mx51evk/mx51evk.c | 2 +-
 board/freescale/mx6slevk/mx6slevk.c   | 2 +-
 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c   | 2 +-
 board/freescale/mx6sxsabresd/mx6sxsabresd.c   | 2 +-
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 +-
 board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +-
 board/solidrun/mx6cuboxi/mx6cuboxi.c  | 2 +-
 drivers/usb/host/ehci-fsl.c   | 2 +-
 drivers/usb/host/ehci-mpc512x.c   | 2 +-
 drivers/usb/host/ehci-mx5.c   | 2 +-
 drivers/usb/host/ehci-mx6.c   | 2 +-
 drivers/usb/host/ehci-mxc.c   | 2 +-
 drivers/usb/host/ehci-vf.c| 2 +-
 drivers/usb/host/ehci-zynq.c  | 2 +-
 include/usb/{ehci-fsl.h => ehci-ci.h} | 6 +++---
 18 files changed, 20 insertions(+), 20 deletions(-)
 rename include/usb/{ehci-fsl.h => ehci-ci.h} (99%)

diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c 
b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 00572de..0791043 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -9,7 +9,7 @@
 #include 
 #include 
 #ifdef CONFIG_USB_EHCI_FSL
-#include 
+#include 
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c 
b/board/boundary/nitrogen6x/nitrogen6x.c
index 104d71f..a3a56ca 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -31,7 +31,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c
index 5dd6cdd..934f009 100644
--- a/board/denx/m53evk/m53evk.c
+++ b/board/denx/m53evk/m53evk.c
@@ -22,7 +22,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/board/freescale/mx51evk/mx51evk.c 
b/board/freescale/mx51evk/mx51evk.c
index c7c21f3..2ea5346 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -20,7 +20,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/mx6slevk/mx6slevk.c 
b/board/freescale/mx6slevk/mx6slevk.c
index f440ce6..f1915a8 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -28,7 +28,7 @@
 #include 
 #include "../common/pfuze.h"
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c 
b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index a240982..886373c 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -28,7 +28,7 @@
 #include 
 #include "../common/pfuze.h"
 #include 
-#include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 41319c6..25e009e 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -27,7 +27,7 @@
 #include 
 #include "../common/pfuze.h"
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c 
b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 98d5675..88d3fbd 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -27,7 +27,7 @@
 #include 
 #include "../common/pfuze.h"
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c 
b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 4d0b195..c3062f1 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -24,7 +24,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c 
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 823b70f..bcc9729 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -33,7 +33,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 

[U-Boot] [PATCH v4 13/21] ehci: Add support for Qualcomm EHCI

[Mateusz Kulikowski]

This driver is able to reconfigure OTG controller into HOST mode.
Board can add board-specific initialization as board_prepare_usb().
It requires USB_ULPI_VIEWPORT enabled in board configuration.

Signed-off-by: Mateusz Kulikowski 
Acked-by: Marek Vasut 
Tested-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Use PORT_... macro to write to portsc
- Remove extra whitespace in probe()
- Add acked-by

Changes in v1:
- Reordered header files
- Removed braces around constant
- Added more verbose help to KConfig
- Added ULPI dependency to Kconfig
- Drop register #defines - use ehci-ci.h instead
- Create fixed ulpi viewport for device
- Use setbits/clearbits where possible
- Use wait_for_bit to reset controller
- Add dt binding documents

 doc/device-tree-bindings/usb/ehci-msm.txt |  10 ++
 drivers/usb/host/Kconfig  |  11 ++
 drivers/usb/host/Makefile |   1 +
 drivers/usb/host/ehci-msm.c   | 178 ++
 4 files changed, 200 insertions(+)
 create mode 100644 doc/device-tree-bindings/usb/ehci-msm.txt
 create mode 100644 drivers/usb/host/ehci-msm.c

diff --git a/doc/device-tree-bindings/usb/ehci-msm.txt 
b/doc/device-tree-bindings/usb/ehci-msm.txt
new file mode 100644
index 000..205bb07
--- /dev/null
+++ b/doc/device-tree-bindings/usb/ehci-msm.txt
@@ -0,0 +1,10 @@
+Chipidea EHCI controller (part of OTG controller) used on Qualcomm devices.
+
+Required properties:
+- compatible: must be "qcom,ehci-host"
+- reg: start address and size of the registers
+
+ehci@78d9000 {
+   compatible = "qcom,ehci-host";
+   reg = <0x78d9000 0x400>;
+};
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 9332374..d2363c8 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -74,6 +74,17 @@ config USB_EHCI_MX6
---help---
  Enables support for the on-chip EHCI controller on i.MX6 SoCs.
 
+config USB_EHCI_MSM
+   bool "Support for Qualcomm on-chip EHCI USB controller"
+   depends on DM_USB
+   select USB_ULPI_VIEWPORT
+   default n
+   ---help---
+ Enables support for the on-chip EHCI controller on Qualcomm
+ Snapdragon SoCs.
+ This driver supports combination of Chipidea USB controller
+ and Synapsys USB PHY in host mode only.
+
 config USB_EHCI_GENERIC
bool "Support for generic EHCI USB controller"
depends on OF_CONTROL
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 9a87d2b..507519e 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx6.o
 obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
 obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
+obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
 obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
 obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
new file mode 100644
index 000..6484c1c
--- /dev/null
+++ b/drivers/usb/host/ehci-msm.c
@@ -0,0 +1,178 @@
+/*
+ * Qualcomm EHCI driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * Based on Linux driver
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "ehci.h"
+
+/* PHY viewport regs */
+#define ULPI_MISC_A_READ 0x96
+#define ULPI_MISC_A_SET  0x97
+#define ULPI_MISC_A_CLEAR0x98
+#define ULPI_MISC_A_VBUSVLDEXTSEL(1 << 1)
+#define ULPI_MISC_A_VBUSVLDEXT   (1 << 0)
+
+#define GEN2_SESS_VLD_CTRL_EN (1 << 7)
+
+#define SESS_VLD_CTRL (1 << 25)
+
+struct msm_ehci_priv {
+   struct ehci_ctrl ctrl; /* Needed by EHCI */
+   struct usb_ehci *ehci; /* Start of IP core*/
+   struct ulpi_viewport ulpi_vp; /* ULPI Viewport */
+};
+
+int __weak board_prepare_usb(enum usb_init_type type)
+{
+   return 0;
+}
+
+static void setup_usb_phy(struct msm_ehci_priv *priv)
+{
+   /* Select and enable external configuration with USB PHY */
+   ulpi_write(>ulpi_vp, (u8 *)ULPI_MISC_A_SET,
+  ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
+}
+
+static void reset_usb_phy(struct msm_ehci_priv *priv)
+{
+   /* Disable VBUS mimicing in the controller. */
+   ulpi_write(>ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR,
+  ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
+}
+
+
+static int msm_init_after_reset(struct ehci_ctrl *dev)
+{
+   struct msm_ehci_priv *p = container_of(dev, struct msm_ehci_priv, ctrl);
+   struct usb_ehci *ehci = p->ehci;
+
+   /* select ULPI phy */
+   writel(PORT_PTS_ULPI, >portsc);
+   setup_usb_phy(p);
+
+   /* Enable sess_vld */
+ 

[U-Boot] [PATCH v4 11/21] usb: ehci-ci: Add missing registers.

[Mateusz Kulikowski]

Some registers of usb_ehci were marked as reserved.
This may be true for some variants of Chipidea USB core, but they have
meaning on other devices.

The following registers were added:
sbusstatus/sbusmode: AHB-related registers
genconfig*: Auxiluary IP core configuration registers.

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Marek Vasut 
Tested-by: Simon Glass 

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Add reviewed-by

Changes in v1: None

 include/usb/ehci-ci.h | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index 725aec5..305b180 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -191,7 +191,11 @@ struct usb_ehci {
u32 gptimer1_ld;/* 0x088 - General Purpose Timer 1 load value */
u32 gptimer1_ctrl;  /* 0x08C - General Purpose Timer 1 control */
u32 sbuscfg;/* 0x090 - System Bus Interface Control */
-   u8  res2[0x6C];
+   u32 sbusstatus; /* 0x094 - System Bus Interface Status */
+   u32 sbusmode;   /* 0x098 - System Bus Interface Mode */
+   u32 genconfig;  /* 0x09C - USB Core Configuration */
+   u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */
+   u8  res2[0x5c];
u8  caplength;  /* 0x100 - Capability Register Length */
u8  res3[0x1];
u16 hciversion; /* 0x102 - Host Interface Version */
-- 
2.5.0

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[U-Boot] [PATCH v4 09/21] eth: asix88179: Print packet length properly

[Mateusz Kulikowski]

Debug printf used '%u' to print size_t variable.
This caused warnings on 64-bit machines.

Signed-off-by: Mateusz Kulikowski 
Acked-by: Marek Vasut 
Acked-by: Joe Hershberger 
---

Changes in v4:
- Add Ack from Marek and Joe

Changes in v3:
- New patch

Changes in v2: None
Changes in v1: None

 drivers/usb/eth/asix88179.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c
index cf4085d..5e1ea86 100644
--- a/drivers/usb/eth/asix88179.c
+++ b/drivers/usb/eth/asix88179.c
@@ -497,7 +497,7 @@ static int asix_send(struct eth_device *eth, void *packet, 
int length)
length + sizeof(packet_len) + sizeof(tx_hdr2),
_len,
USB_BULK_SEND_TIMEOUT);
-   debug("Tx: len = %u, actual = %u, err = %d\n",
+   debug("Tx: len = %zu, actual = %u, err = %d\n",
  length + sizeof(packet_len), actual_len, err);
 
return err;
-- 
2.5.0

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[U-Boot] [PATCH v4 12/21] ehci-ci.h: drop generic USBCMD fields

[Mateusz Kulikowski]

Use definitions from ehci.h instead.

Signed-off-by: Mateusz Kulikowski 
Acked-by: Marek Vasut 
Tested-by: Simon Glass 

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Add Acked-by

Changes in v1: None

 drivers/usb/host/ehci-mpc512x.c | 4 ++--
 include/usb/ehci-ci.h   | 4 
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index 4b50ac8..bb4f461 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -93,7 +93,7 @@ static int reset_usb_controller(volatile struct usb_ehci 
*ehci)
unsigned int i;
 
/* Command a reset of the USB Controller */
-   out_be32(&(ehci->usbcmd), EHCI_FSL_USBCMD_RST);
+   out_be32(&(ehci->usbcmd), CMD_RESET);
 
/* Wait for the reset process to finish */
for (i = 65535 ; i > 0 ; i--) {
@@ -101,7 +101,7 @@ static int reset_usb_controller(volatile struct usb_ehci 
*ehci)
 * The host will set this bit to zero once the
 * reset process is complete
 */
-   if ((in_be32(&(ehci->usbcmd)) & EHCI_FSL_USBCMD_RST) == 0)
+   if ((in_be32(&(ehci->usbcmd)) & CMD_RESET) == 0)
return 0;
}
 
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index 305b180..586d32a 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -97,10 +97,6 @@
 #define INTR_DATA_PULSING_EN   (0x1<<30)
 #define INTSTS_MASK(0x00ff)
 
-/* USBCMD Bits of interest */
-#define EHCI_FSL_USBCMD_RST(1 <<  1)
-#define EHCI_FSL_USBCMD_RS (1 <<  0)
-
 #define  INTERRUPT_ENABLE_BITS_MASK  \
(INTR_USB_ID_EN | \
INTR_1MS_TIMER_EN   | \
-- 
2.5.0

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[U-Boot] [PATCH v4 07/21] usb: ulpi: Fix viewport_addr type

[Mateusz Kulikowski]

viewport_addr is address of memory mapped ULPI viewport.
It is used only as argument to readl/writel later
causing compile warnings on 64-bit devices.

This fix changes its type to match pointer size.

Signed-off-by: Mateusz Kulikowski 
Acked-by: Marek Vasut 
---

Changes in v4:
- Add Ack from Marek

Changes in v3:
- New patch

Changes in v2: None
Changes in v1: None

 include/usb/ulpi.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h
index 4fa765b..dfea395 100644
--- a/include/usb/ulpi.h
+++ b/include/usb/ulpi.h
@@ -32,7 +32,7 @@
  * be extended from this structure
  */
 struct ulpi_viewport {
-   u32 viewport_addr;
+   uintptr_t viewport_addr;
u32 port_num;
 };
 
-- 
2.5.0

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[U-Boot] [PATCH v4 08/21] usb: ulpi: Fix compile warning in read/write on 64-bit machines.

[Mateusz Kulikowski]

ulpi_read and ulpi_write are used to read/write registers via ULPI bus.
Code generates compilation warnings on 64-bit machines where pointer
is cast to u32.

This patch drops all but last 8 bits of register address.
It is possible, because addresses on ULPI bus are 6- or 8-bit.

It is not possible (according to ULPI 1.1 spec) to have more
than 8-bit addressing.

This patch should not cause regressions as all calls to
ulpi_read/write use either structure pointer (@ address 0) or integer
offsets cast to pointer - addresses requested are way below 8-bit range.

Signed-off-by: Mateusz Kulikowski 
Acked-by: Marek Vasut 
---

Changes in v4:
- Add Ack from Marek

Changes in v3:
- New patch

Changes in v2: None
Changes in v1: None

 drivers/usb/ulpi/ulpi-viewport.c | 5 +++--
 include/usb/ulpi.h   | 2 ++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/ulpi/ulpi-viewport.c b/drivers/usb/ulpi/ulpi-viewport.c
index 72a06de..d111680 100644
--- a/drivers/usb/ulpi/ulpi-viewport.c
+++ b/drivers/usb/ulpi/ulpi-viewport.c
@@ -92,7 +92,8 @@ static int ulpi_request(struct ulpi_viewport *ulpi_vp, u32 
value)
 
 int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value)
 {
-   u32 val = ULPI_RWRUN | ULPI_RWCTRL | ((u32)reg << 16) | (value & 0xff);
+   u32 addr = (uintptr_t)reg & 0xFF;
+   u32 val = ULPI_RWRUN | ULPI_RWCTRL | addr << 16 | (value & 0xff);
 
val |= (ulpi_vp->port_num & 0x7) << 24;
return ulpi_request(ulpi_vp, val);
@@ -101,7 +102,7 @@ int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 
value)
 u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg)
 {
int err;
-   u32 val = ULPI_RWRUN | ((u32)reg << 16);
+   u32 val = ULPI_RWRUN | ((uintptr_t)reg & 0xFF) << 16;
 
val |= (ulpi_vp->port_num & 0x7) << 24;
err = ulpi_request(ulpi_vp, val);
diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h
index dfea395..747fb0a 100644
--- a/include/usb/ulpi.h
+++ b/include/usb/ulpi.h
@@ -123,6 +123,7 @@ int ulpi_reset(struct ulpi_viewport *ulpi_vp);
 /*
  * Write to the ULPI PHY register via the viewport.
  * @reg- the ULPI register (one of the fields in struct 
ulpi_regs).
+ *   Due to ULPI design, only 8 lsb of address are used.
  * @value  - the value - only 8 lower bits are used, others ignored.
  *
  * returns 0 on success, ULPI_ERROR on failure.
@@ -132,6 +133,7 @@ int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 
value);
 /*
  * Read the ULPI PHY register content via the viewport.
  * @reg- the ULPI register (one of the fields in struct 
ulpi_regs).
+ *   Due to ULPI design, only 8 lsb of address are used.
  *
  * returns register content on success, ULPI_ERROR on failure.
  */
-- 
2.5.0

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[U-Boot] [PATCH v4 06/21] Migrate CONFIG_ULPI* to Kconfig

[Mateusz Kulikowski]

Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it.
Also - add CONFIG_USB where necesarry - all boards use it,
but some are not defining it explicitly.

Affected boards:
colibri_t20, harmony, mcx, mt_ventoux, twister,
zynq_(picozed, zc702, zc706, zed, zybo)

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch, independent of the rest
- Should compile cleanly on all affected platforms
- Is orthogonal to series (i.e. if get's NAK will not break rest of series)

Changes in v1: None

 configs/colibri_t20_defconfig| 2 ++
 configs/harmony_defconfig| 2 ++
 configs/mcx_defconfig| 3 +++
 configs/mt_ventoux_defconfig | 3 +++
 configs/twister_defconfig| 3 +++
 configs/zynq_picozed_defconfig   | 2 ++
 configs/zynq_zc702_defconfig | 2 ++
 configs/zynq_zc706_defconfig | 2 ++
 configs/zynq_zed_defconfig   | 2 ++
 configs/zynq_zybo_defconfig  | 2 ++
 include/configs/colibri_t20.h| 3 +--
 include/configs/harmony.h| 2 --
 include/configs/mcx.h| 2 --
 include/configs/tam3517-common.h | 2 --
 include/configs/zynq-common.h| 2 --
 15 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index c36967d..3813e96 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -21,4 +21,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index c150f6e..d4aafe9 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -21,4 +21,6 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index a25ffcf..9c9d51a 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -12,3 +12,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index c537440..45913d4 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -10,3 +10,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 06c98eb..064cf91 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -10,3 +10,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 67e38e5..c730f3c 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -14,3 +14,5 @@ CONFIG_ZYNQ_SDHCI=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index d1740a7..e8d28e4 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -26,3 +26,5 @@ CONFIG_DEBUG_UART_CLOCK=5000
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index d3ae438..d19108f 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -23,3 +23,5 @@ CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 9ad33ff..b13de10 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -23,3 +23,5 @@ CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 470c9cb..4a59890 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -24,3 +24,5 @@ CONFIG_DEBUG_UART_CLOCK=5000
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index b7ad189..e97e5a1 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -36,8 +36,7 @@
 /* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT3
 #define CONFIG_USB_STORAGE
 

[U-Boot] [PATCH v4 05/21] usb: ulpi: Add Kconfig options for ULPI

[Mateusz Kulikowski]

The following options can be now enabled via defconfig:
- CONFIG_USB_ULPI
- CONFIG_USB_ULPI_VIEWPORT
- CONFIG_USB_ULPI_VIEWPORT_OMAP

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
Acked-by: Marek Vasut 
---

Changes in v4:
- Add Ack from Marek

Changes in v3: None
Changes in v2:
- Add better (any) descriptions for Kconfig items.

Changes in v1: None

 drivers/usb/Kconfig  |  2 ++
 drivers/usb/ulpi/Kconfig | 33 +
 2 files changed, 35 insertions(+)
 create mode 100644 drivers/usb/ulpi/Kconfig

diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 7fa99c6..bccf43e 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -53,6 +53,8 @@ source "drivers/usb/musb-new/Kconfig"
 
 source "drivers/usb/emul/Kconfig"
 
+source "drivers/usb/ulpi/Kconfig"
+
 comment "USB peripherals"
 
 config USB_STORAGE
diff --git a/drivers/usb/ulpi/Kconfig b/drivers/usb/ulpi/Kconfig
new file mode 100644
index 000..329d2df
--- /dev/null
+++ b/drivers/usb/ulpi/Kconfig
@@ -0,0 +1,33 @@
+comment "ULPI drivers"
+
+choice
+   prompt "ULPI Viewport type"
+   optional
+   default n
+   help
+ Select ULPI viewport (SoC-side interface to ULPI) implementation
+ appropriate for the device if you want to communicate with
+ UTMI (USB PHY) via ULPI interface.
+
+config USB_ULPI_VIEWPORT
+   bool "Generic ULPI Viewport"
+   help
+ Support generic ULPI Viewport implementation that is used on
+ some Tegra and Snapdragon devices.
+
+config USB_ULPI_VIEWPORT_OMAP
+   bool "OMAP ULPI Viewport"
+   help
+ Support ULPI Viewport implementation that is used on OMAP devices.
+
+endchoice
+
+config USB_ULPI
+   bool "ULPI support"
+   depends on (USB_ULPI_VIEWPORT || USB_ULPI_VIEWPORT_OMAP)
+   help
+ Select to commnicate with USB PHY via ULPI interface.
+ ULPI is wrapper on UTMI+ core that is used as
+ PHY Transreceiver for USB controllers.
+
+ This driver uses ULPI viewports that are specific for each SoC.
-- 
2.5.0

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[U-Boot] [PATCH v4 03/21] mmc: Add support for Qualcomm SDHCI controller

[Mateusz Kulikowski]

Add support for SD/eMMC controller present on some Qualcomm Snapdragon
devices. This controller implements SDHCI 2.0 interface but requires
vendor-specific initialization.
Driver works in PIO mode as ADMA is not supported by U-Boot (yet).

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Add reviewed-by

Changes in v1:
- Added commit message
- Added DT binding documentation
- Added Kconfig help
- Reordered includes
- Dropped redundant fields from msm_sdhc
- Cleaned up clock init code (+ added error handling)
- Dropped mdelay - use wait_for_bit instead in reset code
- Added missing newline after declarations
- Added error handling if "reg" is missing
- Converted base address to pointer

 doc/device-tree-bindings/mmc/msm_sdhci.txt |  25 
 drivers/mmc/Kconfig|   9 ++
 drivers/mmc/Makefile   |   1 +
 drivers/mmc/msm_sdhci.c| 180 +
 4 files changed, 215 insertions(+)
 create mode 100644 doc/device-tree-bindings/mmc/msm_sdhci.txt
 create mode 100644 drivers/mmc/msm_sdhci.c

diff --git a/doc/device-tree-bindings/mmc/msm_sdhci.txt 
b/doc/device-tree-bindings/mmc/msm_sdhci.txt
new file mode 100644
index 000..08a290c
--- /dev/null
+++ b/doc/device-tree-bindings/mmc/msm_sdhci.txt
@@ -0,0 +1,25 @@
+Qualcomm Snapdragon SDHCI controller
+
+Required properties:
+- compatible : "qcom,sdhci-msm-v4"
+- reg: Base address and length of registers:
+   - Host controller registers (SDHCI)
+   - SD Core registers
+- clock: interface clock (must accept SD bus clock as a frequency)
+
+Optional properties:
+- index: If there is more than one controller - controller index (required
+   by generic SDHCI code).
+- bus_width: Width of SD/eMMC bus (default 4)
+- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
+
+Example:
+
+sdhci@07864000 {
+   compatible = "qcom,sdhci-msm-v4";
+   reg = <0x7864900 0x11c 0x7864000 0x800>;
+   index = <0x1>;
+   bus-width = <0x4>;
+   clock = < 1>;
+   clock-frequency = <2>;
+};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index dc8532f..4d3df11 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -16,6 +16,15 @@ config DM_MMC
  appear as block devices in U-Boot and can support filesystems such
  as EXT4 and FAT.
 
+config MSM_SDHCI
+   bool "Qualcomm SDHCI controller"
+   depends on DM_MMC
+   help
+ Enables support for SDHCI 2.0 controller present on some Qualcomm
+  Snapdragon devices. This device is compatible with eMMC v4.5 and
+  SD 3.0 specifications. Both SD and eMMC devices are supported.
+ Card-detect gpios are not supported.
+
 config ROCKCHIP_DWMMC
bool "Rockchip SD/MMC controller support"
depends on DM_MMC && OF_CONTROL
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index b85e4bf..585aaf3 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -50,3 +50,4 @@ else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
 obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
+obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
new file mode 100644
index 000..1e2a29b
--- /dev/null
+++ b/drivers/mmc/msm_sdhci.c
@@ -0,0 +1,180 @@
+/*
+ * Qualcomm SDHCI driver - SD/eMMC controller
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * Based on Linux driver
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Non-standard registers needed for SDHCI startup */
+#define SDCC_MCI_POWER   0x0
+#define SDCC_MCI_POWER_SW_RST BIT(7)
+
+/* This is undocumented register */
+#define SDCC_MCI_VERSION 0x50
+#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
+#define SDCC_MCI_VERSION_MAJOR_MASK  (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
+#define SDCC_MCI_VERSION_MINOR_MASK  0xff
+
+#define SDCC_MCI_STATUS2 0x6C
+#define SDCC_MCI_STATUS2_MCI_ACT 0x1
+#define SDCC_MCI_HC_MODE 0x78
+
+/* Offset to SDHCI registers */
+#define SDCC_SDHCI_OFFSET 0x900
+
+/* Non standard (?) SDHCI register */
+#define SDHCI_VENDOR_SPEC_CAPABILITIES0  0x11c
+
+struct msm_sdhc {
+   struct sdhci_host host;
+   void *base;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int msm_sdc_clk_init(struct udevice *dev)
+{
+   uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+   "clock-frequency", 40);
+   uint clkd[2]; /* clk_id and clk_no */
+   int clk_offset;
+   struct udevice *clk;
+   int ret;
+
+   ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
+  2);
+   if (ret)
+   return ret;
+
+   clk_offset = 

[U-Boot] [PATCH v4 02/21] gpio: Add support for Qualcomm gpio controller

[Mateusz Kulikowski]

Add support for gpio controllers on Qualcomm Snapdragon devices.
This devices are usually called Top Level Mode Multiplexing in
Qualcomm documentation.

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Reordered includes (again)
- Added newlines between returns
- Fixed error handling in msm_gpio_probe
- Added reviewed-by

Changes in v1:
- Added dt binding documentation
- Added help to KConfig
- Use clrsetbits() to switch direction
- Fixed include order
- Added #defines for registers/register fields
- Added secondary compatible string

 doc/device-tree-bindings/gpio/gpio-msm.txt |  22 +
 drivers/gpio/Kconfig   |  14 +++
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/msm_gpio.c| 135 +
 4 files changed, 172 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt
 create mode 100644 drivers/gpio/msm_gpio.c

diff --git a/doc/device-tree-bindings/gpio/gpio-msm.txt 
b/doc/device-tree-bindings/gpio/gpio-msm.txt
new file mode 100644
index 000..966ce0a
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/gpio-msm.txt
@@ -0,0 +1,22 @@
+Qualcomm Snapdragon GPIO controller
+
+Required properties:
+- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
+- reg : Physical base address and length of the controller's registers.
+   This controller is called "Top Level Mode Multiplexing" in
+   Qualcomm documentation.
+- #gpio-cells : Should be one (pin number).
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-count: Number of GPIO pins.
+- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
+
+Example:
+
+soc_gpios: pinctrl@100 {
+   compatible = "qcom,msm8916-pinctrl";
+   reg = <0x100 0x30>;
+   gpio-controller;
+   gpio-count = <122>;
+   gpio-bank-name="soc";
+   #gpio-cells = <1>;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2311309..4d9e74c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -55,6 +55,20 @@ config LPC32XX_GPIO
help
  Support for the LPC32XX GPIO driver.
 
+config MSM_GPIO
+   bool "Qualcomm GPIO driver"
+   depends on DM_GPIO
+   default n
+   help
+ Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
+ This controller have single bank (default name "soc"), every
+ gpio has it's own set of registers.
+ Only simple GPIO operations are supported (get/set, change of
+ direction and checking pin function).
+ Supported devices:
+ - APQ8016
+ - MSM8916
+
 config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ea6e2ed..4162c3c 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -50,3 +50,4 @@ obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)   += hi6220_gpio.o
 obj-$(CONFIG_PIC32_GPIO)   += pic32_gpio.o
 obj-$(CONFIG_MVEBU_GPIO)   += mvebu_gpio.o
+obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
new file mode 100644
index 000..950f309
--- /dev/null
+++ b/drivers/gpio/msm_gpio.c
@@ -0,0 +1,135 @@
+/*
+ * Qualcomm GPIO driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offsets */
+#define GPIO_CONFIG_OFF(no) ((no) * 0x1000)
+#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4)
+
+/* OE */
+#define GPIO_OE_DISABLE  (0x0 << 9)
+#define GPIO_OE_ENABLE   (0x1 << 9)
+#define GPIO_OE_MASK (0x1 << 9)
+
+/* GPIO_IN_OUT register shifts. */
+#define GPIO_IN  0
+#define GPIO_OUT 1
+
+struct msm_gpio_bank {
+   phys_addr_t base;
+};
+
+static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+   struct msm_gpio_bank *priv = dev_get_priv(dev);
+   phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+   /* Disable OE bit */
+   clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
+
+   return 0;
+}
+
+static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
+{
+   struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+   value = !!value;
+   /* set value */
+   writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+
+   return 0;
+}
+
+static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
+int value)
+{
+   struct msm_gpio_bank *priv = dev_get_priv(dev);
+   phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+   value = !!value;
+   

[U-Boot] [PATCH v4 04/21] ehci-hcd: Add init_after_reset

[Mateusz Kulikowski]

Some host controllers need addidional initialization after ehci_reset()
In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET.
This patch adds similar option to ehci drivers using dm.

Signed-off-by: Mateusz Kulikowski 
Acked-by: Marek Vasut 
Reviewed-by: Tom Rini 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Add Reviewed-by (sjg)

Changes in v1:
- No changes, just added Acked-by, Reviewed-by

 drivers/usb/host/ehci-hcd.c | 6 ++
 drivers/usb/host/ehci.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 0113c6c..598f444 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1615,6 +1615,12 @@ int ehci_register(struct udevice *dev, struct ehci_hccr 
*hccr,
if (ret)
goto err;
 
+   if (ops->init_after_reset) {
+   ret = ops->init_after_reset(ctrl);
+   if (ret)
+   goto err;
+   }
+
ret = ehci_common_init(ctrl, tweaks);
if (ret)
goto err;
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 826b3fe..734d7f0 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -240,6 +240,7 @@ struct ehci_ops {
void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
  uint32_t *reg);
uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
+   int (*init_after_reset)(struct ehci_ctrl *ctrl);
 };
 
 struct ehci_ctrl {
-- 
2.5.0

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[U-Boot] [PATCH v4 01/21] serial: Add support for Qualcomm serial port

[Mateusz Kulikowski]

This driver works in "new" Data Mover UART mode, so
will be compatible with modern Qualcomm chips only.

Signed-off-by: Mateusz Kulikowski 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 
---

Changes in v4: None
Changes in v3:
- Add msm_serial_fetch that tries to fetch characters from FIFO
- Decrease no of characters requested in RX transaction
- Try to fetch characters from FIFO when tstc()/pending() is called

Changes in v2:
- Added newline before return... (globally)
- Renamed p to priv (priv data) - it required some rewrapping
- Added Reviewed-by

Changes in v1:
- Added (better) help to KConfig
- Added dt binding documentation
- Fixed include ordering
- Reworked msm_serial_getc
- Added error handling to msm_uart_clk_init (that is ignored later for now)
- Dropped unneeded DM_FLAG_PRE_RELOC

 doc/device-tree-bindings/serial/msm-serial.txt |   6 +
 drivers/serial/Kconfig |   8 +
 drivers/serial/Makefile|   1 +
 drivers/serial/serial_msm.c| 217 +
 4 files changed, 232 insertions(+)
 create mode 100644 doc/device-tree-bindings/serial/msm-serial.txt
 create mode 100644 drivers/serial/serial_msm.c

diff --git a/doc/device-tree-bindings/serial/msm-serial.txt 
b/doc/device-tree-bindings/serial/msm-serial.txt
new file mode 100644
index 000..48b8428
--- /dev/null
+++ b/doc/device-tree-bindings/serial/msm-serial.txt
@@ -0,0 +1,6 @@
+Qualcomm UART (Data Mover mode)
+
+Required properties:
+- compatible: must be "qcom,msm-uartdm-v1.4"
+- reg: start address and size of the registers
+- clock: interface clock (must accept baudrate as a frequency)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 2a770a1..a9a5d47 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -320,4 +320,12 @@ config XILINX_UARTLITE
  If you have a Xilinx based board and want to use the uartlite
  serial ports, say Y to this option. If unsure, say N.
 
+config MSM_SERIAL
+   bool "Qualcomm on-chip UART"
+   depends on DM_SERIAL
+   help
+ Support Data Mover UART used on Qualcomm Snapdragon SoCs.
+ It should support all Qualcomm devices with UARTDM version 1.4,
+ for example APQ8016 and MSM8916.
+ Single baudrate is supported in current implementation (115200).
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index ee7147a..b0ac9d8 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
 obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
 obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
 obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
+obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
new file mode 100644
index 000..80fb89e
--- /dev/null
+++ b/drivers/serial/serial_msm.c
@@ -0,0 +1,217 @@
+/*
+ * Qualcomm UART driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski 
+ *
+ * UART will work in Data Mover mode.
+ * Based on Linux driver.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Serial registers - this driver works in uartdm mode*/
+
+#define UARTDM_DMRX 0x34 /* Max RX transfer length */
+#define UARTDM_NCF_TX   0x40 /* Number of chars to TX */
+
+#define UARTDM_RXFS 0x50 /* RX channel status register */
+#define UARTDM_RXFS_BUF_SHIFT   0x7  /* Number of bytes in the packing buffer 
*/
+#define UARTDM_RXFS_BUF_MASK0x7
+
+#define UARTDM_SR0xA4 /* Status register */
+#define UARTDM_SR_RX_READY   (1 << 0) /* Word is the receiver FIFO */
+#define UARTDM_SR_TX_EMPTY   (1 << 3) /* Transmitter underrun */
+#define UARTDM_SR_UART_OVERRUN   (1 << 4) /* Receive overrun */
+
+#define UARTDM_CR 0xA8 /* Command register */
+#define UARTDM_CR_CMD_RESET_ERR   (3 << 4) /* Clear overrun error */
+#define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */
+#define UARTDM_CR_CMD_RESET_TX_READY  (3 << 8) /* Clears TX Ready irq*/
+#define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */
+#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
+
+#define UARTDM_IMR0xB0 /* Interrupt mask register */
+#define UARTDM_ISR0xB4 /* Interrupt status register */
+#define UARTDM_ISR_TX_READY   0x80 /* TX FIFO empty */
+
+#define UARTDM_TF   0x100 /* UART Transmit FIFO register */
+#define UARTDM_RF   0x140 /* UART Receive FIFO register */
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct msm_serial_data {
+   phys_addr_t base;
+   unsigned chars_cnt; /* number of buffered 

[U-Boot] [PATCH v4 00/21] Add support for 96boards Dragonboard410C board

[Mateusz Kulikowski]

Hi All,

This is next last version of Dragonboard410c series ;)
It should apply cleanly to latest master (080c499d).

I welcome all improvement ideas but please bear in mind I will
probably implement them after this series is merged.

Very little updates this time:
- Added ACKs
- Added MMU configuration (I did that in mach code as 
it's shared for all devices using this SoC)
- Fixed missing renames (ehci-fsl.h -> ehci-ci.h) - sorry for that!
- Moved CONFIG_OF_LIBFDT to defconfig and cleaned it up with savedefconfig

As for testing - I've manually tested it on dragonboard and
did buildman test for all ARM targets (~540 boards, hopefuly I catched all 
that are affected by this series in any way).

@Marek, Joe, Tom: thanks for the input!

Regards,
Mateusz

V3 cover contents:

Sorry for longer delay, but I had too many things to do recently.

As always - for "simplicity" this series is available on my github:
https://github.com/hallor/u-boot/tree/dragonboard-for-mainline-v3

There are almost no changes + one bugfix:
- Bugfix: small rework of serial driver - U-Boot was interrupted
  when no serial converter was attached.
- Updated dragonboard readme.txt with info on how to stop @ fastboot
- Added SPMI entries into test.dts (so automatic DM tests would not fail)
- Added Tested-by and Reviewed-by Simon (from v2 comments)
- Rebased to recent master
- Fixed warnings in ASIX and ULPI code
- Added comments to head.S, little updates suggested by Daniel

@Simon: Thanks for the tests of v2!

Daniel Glöckner, Tom Rini, Jagan Teki: Thanks for the comments!

V2 cover contents:

This is updated series. 99% of review changes are applied,
specific changes are (as always) include in each patch.

You can find this series on my github (if anyone just want to
try it - that branch has also wait_for_bit applied):
https://github.com/hallor/u-boot/tree/dragonboard-for-mainline-v2

I did target tests on Dragonboard410c, and build tested
platforms that may be affected by ULPI changes.

@Simon:
I decided not to rewrite pm8916_gpio for now, but for sake of
"cleannes" moved offending bindings to separate file (and
they are now properly childs of pm8916_gpio).
I will update it during rework of SoC gpio driver
(I will have to create proper pinmux/pinctrl drivers to
get rid of Little Kernel eventually).

This series still needs wait_for_bit series that is not
included (yet).

V1 cover contents:

I finally managed to cleanup RFC for submission. I've included changes in
each patch, there is a bit of them, but all are needed :)

This series requires wait_for_bit patch that I send few days ago:
https://patchwork.ozlabs.org/patch/561185/

RFC cover contents:
http://lists.denx.de/pipermail/u-boot/2015-December/237365.html

Changes in v4:
- Add Ack from Marek
- Add Ack from Marek
- Add Ack from Marek
- Add Ack from Marek and Joe
- Add missing renames (arch/* and board/*)
- Add sysmap for apq8016 (required to enable MMU)
- Move CONFIG_OF_LIBFDT to defconfig and cleaned it up with savedefconfig

Changes in v3:
- Add msm_serial_fetch that tries to fetch characters from FIFO
- Decrease no of characters requested in RX transaction
- Try to fetch characters from FIFO when tstc()/pending() is called
- New patch
- New patch
- New patch
- Updated test.dts to include SPMI like sandbox.dts does
- readme: Added info on how to enter fastboot mode and that
  dtbTool is also part of skales. Added more explanation
  on image generation.
- head: Add comment why it's needed, drop MZ EFI signature
  that makes no sense on this particular SoC, fix confusing
  entry point name (+update .lds file)

Changes in v2:
- Added newline before return... (globally)
- Renamed p to priv (priv data) - it required some rewrapping
- Added Reviewed-by
- Reordered includes (again)
- Added newlines between returns
- Fixed error handling in msm_gpio_probe
- Added reviewed-by
- Add reviewed-by
- Add Reviewed-by (sjg)
- Add better (any) descriptions for Kconfig items.
- New patch, independent of the rest
- Should compile cleanly on all affected platforms
- Is orthogonal to series (i.e. if get's NAK will not break rest of series)
- Add acked-by
- Add reviewed-by
- Add Acked-by
- Use PORT_... macro to write to portsc
- Remove extra whitespace in probe()
- Add acked-by
- Use proper  entry order in Kconfig
- Rename CONFIG_DM_SPMI -> CONFIG_SPMI
- Fix header ordering
- Add reviewed-by
- Rename CONFIG_DM_SPMI -> CONFIG_SPMI
- Rename r -> regs, p -> priv
- Add reviewed-by
- Update binding doc (drop unused bindig)
- Rename DM_SPMI -> SPMI
- Rename p -> priv (in write/read)
- Fix header ordering (again)
- Add reviewed-by
- Add reviewed-by
- Reordered Kconfig & Makefile (to keep alphabetical ordering)
- Added link to dt binding @ help
- Add Reviewed-by
- Rename DM_SPMI -> SPMI
- Make MND divider comments more compact :)
- p -> priv
- Add reviewed-by
- Reordered Kconfig to keep alphabetical order
- Renamed reset_sandbox -> msm_reset (typo in reset.c)
- Renamed CONFIG_DM_SPMI -> CONFIG_SPMI
- 

[U-Boot] [PATCH 5/7] ARM: rmobile: Add support R8A7795

[Nobuhiro Iwamatsu]

Renesas R8A7795 is CPU with Cortex-a57.
This supports the basic register definition and GPIO and
framework of PFC.

Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Makefile|1 +
 arch/arm/mach-rmobile/include/mach/gpio.h |3 +
 arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h |  988 +
 arch/arm/mach-rmobile/include/mach/r8a7795.h  |   36 +
 arch/arm/mach-rmobile/include/mach/rmobile.h  |2 +
 arch/arm/mach-rmobile/pfc-r8a7795.c   | 4844 +
 include/sh_pfc.h  |3 +
 7 files changed, 5877 insertions(+)
 create mode 100644 arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
 create mode 100644 arch/arm/mach-rmobile/include/mach/r8a7795.h
 create mode 100644 arch/arm/mach-rmobile/pfc-r8a7795.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index d793616..a598cf9 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -15,5 +15,6 @@ obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o 
pfc-r8a7790.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
 obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
 obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
+obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o
 obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h 
b/arch/arm/mach-rmobile/include/mach/gpio.h
index 93b20af..d8703f5 100644
--- a/arch/arm/mach-rmobile/include/mach/gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/gpio.h
@@ -19,6 +19,9 @@ void r8a7793_pinmux_init(void);
 #elif defined(CONFIG_R8A7794)
 #include "r8a7794-gpio.h"
 void r8a7794_pinmux_init(void);
+#elif defined(CONFIG_R8A7795)
+#include "r8a7795-gpio.h"
+void r8a7795_pinmux_init(void);
 #endif
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h 
b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
new file mode 100644
index 000..63e156d
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
@@ -0,0 +1,988 @@
+/*
+ * arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h
+ * This file defines pin function control of gpio.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef __ASM_R8A7795_GPIO_H__
+#define __ASM_R8A7795_GPIO_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+   GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+   GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+   GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+   GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+
+   GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+   GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+   GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+   GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+   GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+   GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+   GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
+
+   GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+   GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+   GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+   GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14,
+
+   GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+   GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+   GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+   GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+
+   GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+   GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+   GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+   GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+   GPIO_GP_4_16, GPIO_GP_4_17,
+
+   GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+   GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+   GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+   GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+   GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+   GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+   GPIO_GP_5_24, GPIO_GP_5_25,
+
+   GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+   GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+   GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
+   GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
+   GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
+   

[U-Boot] [PATCH] arm: socfpga: Nuke useless include

[Marek Vasut]

The dwmmc.h include was forgotten during the migration of dwmmc
probing to DM. Since the shiny DM is in place now, remove this
relic of the past.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
---
 arch/arm/mach-socfpga/misc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ce3ff0a..ebaa736 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -16,7 +16,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
-- 
2.7.0

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Re: [U-Boot] [PATCH] dm: gpio: handle GPIO_ACTIVE_LOW flag in DT

[Eric Nelson]

Hi Peng,

On 03/28/2016 09:57 PM, Peng Fan wrote:
> Hi Eric,
> 
> On Fri, Mar 25, 2016 at 01:12:11PM -0700, Eric Nelson wrote:
>> Device tree parsing of GPIO nodes is currently ignoring flags.
>>
>> Add support for GPIO_ACTIVE_LOW by checking for the presence
>> of the flag and setting the desc->flags field to the driver
>> model constant GPIOD_ACTIVE_LOW.
> 
> You may need to try this: https://patchwork.ozlabs.org/patch/597363/
> 
Thanks for pointing this out.

This patch also works, but it has me confused.

How/why is parsing the ACTIVE_LOW flag specific to MXC?

This is a general-purpose flag in the kernel, not something machine-
specific.

It also appears that there are a bunch of other copies
of this same bit of code in the various mach_xlate() routines:

desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;

If it's done in gpio-uclass, this isn't needed and xlate can
be removed from mxc-gpio and quite a few other architectures.

Please advise,


Eric
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Re: [U-Boot] [PATCH V3 1/3] drivers: block: add block device cache

[Eric Nelson]

Hi Stephen,

On 03/30/2016 02:57 PM, Stephen Warren wrote:
> On 03/30/2016 11:34 AM, Eric Nelson wrote:
>> Thanks again for the detailed review, Stephen.
>>
>> On 03/30/2016 07:36 AM, Stephen Warren wrote:
>>> On 03/28/2016 11:05 AM, Eric Nelson wrote:
 Add a block device cache to speed up repeated reads of block devices by
 various filesystems.
 diff --git a/disk/part.c b/disk/part.c
>>>
 @@ -268,6 +268,8 @@ void part_init(struct blk_desc *dev_desc)
const int n_ents = ll_entry_count(struct part_driver,
 part_driver);
struct part_driver *entry;

 +blkcache_invalidate(dev_desc->if_type, dev_desc->devnum);
>>>
>>> Doesn't this invalidate the cache far too often? I expect that function
>>> is called for command the user executes from the command-line, whereas
>>> it'd be nice if the cache persisted across commands. I suppose this is a
>>> reasonable (and very safe) first implementation though, and saves having
>>> to go through each storage provider type and find out the right place to
>>> detect media changes.
>>
>> I'm not sure it does. I traced through the mmc initialization and it's
>> only called when the card itself is initialized.
> 
> I don't believe U-Boot caches the partition structure across user
> commands. Doesn't each user command (e.g. part list, ls, load, save)
> first look up the block device, then scan the partition table, then
> "mount" the filesystem, then perform its action, then throw all that
> state away? Conversely, "mmc rescan" only happens under explicit user
> control. Still as I said, the current implementation is probably fine to
> start with, and at least is safe.
> 

At least for MMC, this isn't the case. Various filesystem commands
operate without calling part_init.

 diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c
>>>
 +struct block_cache_node {
 +struct list_head lh;
 +int iftype;
 +int devnum;
 +lbaint_t start;
 +lbaint_t blkcnt;
 +unsigned long blksz;
 +char *cache;
 +};
 +
 +static LIST_HEAD(block_cache);
 +
 +static struct block_cache_stats _stats = {
 +.max_blocks_per_entry = 2,
 +.max_entries = 32
 +};
>>>
>>> Now is a good time to mention another reason why I don't like using a
>>> dynamically allocated linked list for this: Memory fragmentation. By
>>> dynamically allocating the cache, we could easily run into a situation
>>> where the user runs a command that allocates memory and also adds to the
>>> block cache, then most of that memory gets freed when U-Boot returns to
>>> the command prompt, then the user runs the command again but it fails
>>> since it can't allocate the memory due to fragmentation of the heap.
>>> This is a real problem I've seen e.g. with the "ums" and "dfu" commands,
>>> since they might initialize the USB controller the first time they're
>>> run, which allocates some new memory. Statically allocation would avoid
>>> this.
>>
>> We're going to allocate a block or set of blocks every time we allocate
>> a new node for the list, so having the list in an array doesn't fix the
>> problem.
> 
> We could allocate the data storage for the block cache at the top of RAM
> before relocation, like many other things are allocated, and hence not
> use malloc() for that.
> 

Hmmm. We seem to have gone from a discussion about data structures to
type of allocation.

I'm interested in seeing how that works. Can you provide hints about
what's doing this now?

>> While re-working the code, I also thought more about using an array and
>> still don't see how the implementation doesn't get more complex.
>>
>> The key bit is that the list is implemented in MRU order so
>> invalidating the oldest is trivial.
> 
> Yes, the MRU logic would make it more complex. Is that particularly
> useful, i.e. is it an intrinsic part of the speedup?

It's not a question of speed with small numbers of entries. The code
to handle eviction would just be more complex.

Given that the command "blkcache configure 0 0" will discard all
cache and since both dfu and ums should properly have the cache
disabled, I'd like to proceed as-is with the list and heap approach.

A follow-up change to use another form of allocation is unlikely to
change the primary interfaces, though I can't be sure until I
understand how these allocation(s) would occur.

I have a V3 prepped that addresses your other comments.

To reiterate the impact of this code, I have use cases where file
loading takes minutes when it should take seconds and suspect that
others have been seeing the same for quite some time.

Let me know your thoughts.

Regards,


Eric
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[U-Boot] [PATCH v3 0/2] net: phy: mv88e61xx: Revise as a PHY driver

[Kevin Smith]

The previous version of this driver implemented a shell command to manually
comfigure the switch.  It did not integrate with the PHY infrastructure to
allow a MAC to use it as its PHY.  This is a complete rewrite to allow this
switch to function as a driver.  Since none of the original driver remains, the
old driver is first removed and the new PHY driver is added.

This version configures the switch to have a CPU connected over an MII
interface.  It will enable PHY interfaces based on the MV88E61XX_PHY_PORTS
macro.  The switch is configured to allow PHY ports to only communicate to the
CPU.  This allows the switch to be used as a basic PHY on any/all ports.

This was developed on a board with an mv88e6176 connected over SGMII.  It is
intended to work with other configurations, but these could not be tested.  Any
testing on other configurations or with other mv88e61xx chips is appreciated.

Changes in v3:
* Clean up chip register accessor functions to be more clear.
* Support multi-chip addressing mode in the way that Linux DSA does
* Detect hardware strap configuration for CPU port settings like Linux DSA does
* Remove some unnecessary serdes settings
* Use functions in bitfield.h to clean up bit operations
* Use correct error return codes
* Comment/code formatting improvements and clarifications

Signed-off-by: Kevin Smith 
Acked-by: Prafulla Wadaskar 
Cc: Albert ARIBAUD 
Cc: Joe Hershberger 
Cc: Stefan Roese 
Cc: Marek Vasut 

Kevin Smith (2):
  net: Remove unused mv88e61xx switch driver
  net: phy: Add PHY driver for mv88e61xx switches

 drivers/net/phy/mv88e61xx.c | 1322 +--
 drivers/net/phy/mv88e61xx.h |   61 --
 drivers/net/phy/phy.c   |3 +
 include/netdev.h|   58 --
 include/phy.h   |1 +
 5 files changed, 905 insertions(+), 540 deletions(-)
 delete mode 100644 drivers/net/phy/mv88e61xx.h

-- 
2.1.4
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[U-Boot] [PATCH v3 2/2] net: phy: Add PHY driver for mv88e61xx switches

[Kevin Smith]

The previous mv88e61xx driver was a driver for configuring the
switch, but did not integrate with the PHY/networking system, so
it could not be used as a PHY by U-boot.  This is a complete
rework to support this device as a PHY.

Signed-off-by: Kevin Smith 
Acked-by: Prafulla Wadaskar 
Cc: Albert ARIBAUD 
Cc: Joe Hershberger 
Cc: Stefan Roese 
Cc: Marek Vasut 
---
 drivers/net/phy/mv88e61xx.c | 1017 +++
 drivers/net/phy/phy.c   |3 +
 include/phy.h   |1 +
 3 files changed, 1021 insertions(+)
 create mode 100644 drivers/net/phy/mv88e61xx.c

diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
new file mode 100644
index 000..74d5609
--- /dev/null
+++ b/drivers/net/phy/mv88e61xx.c
@@ -0,0 +1,1017 @@
+/*
+ * (C) Copyright 2015
+ * Elecsys Corporation 
+ * Kevin Smith 
+ *
+ * Original driver:
+ * (C) Copyright 2009
+ * Marvell Semiconductor 
+ * Prafulla Wadaskar 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * PHY driver for mv88e61xx ethernet switches.
+ *
+ * This driver configures the mv88e61xx for basic use as a PHY.  The switch
+ * supports a VLAN configuration that determines how traffic will be routed
+ * between the ports.  This driver uses a simple configuration that routes
+ * traffic from each PHY port only to the CPU port, and from the CPU port to
+ * any PHY port.
+ *
+ * The configuration determines which PHY ports to activate using the
+ * CONFIG_MV88E61XX_PHY_PORTS bitmask.  Setting bit 0 will activate port 0, bit
+ * 1 activates port 1, etc.  Do not set the bit for the port the CPU is
+ * connected to unless it is connected over a PHY interface (not MII).
+ *
+ * This driver was written for and tested on the mv88e6176 with an SGMII
+ * connection.  Other configurations should be supported, but some additions or
+ * changes may be required.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PHY_AUTONEGOTIATE_TIMEOUT  5000
+
+#define PORT_COUNT 7
+#define PORT_MASK  ((1 << PORT_COUNT) - 1)
+
+/* Device addresses */
+#define DEVADDR_PHY(p) (p)
+#define DEVADDR_PORT(p)(0x10 + (p))
+#define DEVADDR_SERDES 0x0F
+#define DEVADDR_GLOBAL_1   0x1B
+#define DEVADDR_GLOBAL_2   0x1C
+
+/* SMI indirection registers for multichip addressing mode */
+#define SMI_CMD_REG0x00
+#define SMI_DATA_REG   0x01
+
+/* Global registers */
+#define GLOBAL1_STATUS 0x00
+#define GLOBAL1_CTRL   0x04
+#define GLOBAL1_MON_CTRL   0x1A
+
+/* Global 2 registers */
+#define GLOBAL2_REG_PHY_CMD0x18
+#define GLOBAL2_REG_PHY_DATA   0x19
+
+/* Port registers */
+#define PORT_REG_STATUS0x00
+#define PORT_REG_PHYS_CTRL 0x01
+#define PORT_REG_SWITCH_ID 0x03
+#define PORT_REG_CTRL  0x04
+#define PORT_REG_VLAN_MAP  0x06
+#define PORT_REG_VLAN_ID   0x07
+
+/* Phy registers */
+#define PHY_REG_CTRL1  0x10
+#define PHY_REG_STATUS10x11
+#define PHY_REG_PAGE   0x16
+
+/* Serdes registers */
+#define SERDES_REG_CTRL_1  0x10
+
+/* Phy page numbers */
+#define PHY_PAGE_COPPER0
+#define PHY_PAGE_SERDES1
+
+/* Register fields */
+#define GLOBAL1_CTRL_SWRESET   BIT(15)
+
+#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
+#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
+
+#define PORT_REG_STATUS_LINK   BIT(11)
+#define PORT_REG_STATUS_DUPLEX BIT(10)
+
+#define PORT_REG_STATUS_SPEED_SHIFT8
+#define PORT_REG_STATUS_SPEED_WIDTH2
+#define PORT_REG_STATUS_SPEED_10   0
+#define PORT_REG_STATUS_SPEED_100  1
+#define PORT_REG_STATUS_SPEED_1000 2
+
+#define PORT_REG_STATUS_CMODE_MASK 0xF
+#define PORT_REG_STATUS_CMODE_100BASE_X0x8
+#define PORT_REG_STATUS_CMODE_1000BASE_X   0x9
+#define PORT_REG_STATUS_CMODE_SGMII0xa
+
+#define PORT_REG_PHYS_CTRL_LINK_VALUE  BIT(5)
+#define PORT_REG_PHYS_CTRL_LINK_FORCE  BIT(4)
+
+#define PORT_REG_CTRL_PSTATE_SHIFT 0
+#define PORT_REG_CTRL_PSTATE_WIDTH 2
+
+#define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
+#define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
+
+#define PORT_REG_VLAN_MAP_TABLE_SHIFT  0
+#define PORT_REG_VLAN_MAP_TABLE_WIDTH  11
+
+#define SERDES_REG_CTRL_1_FORCE_LINK   BIT(10)
+
+#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8
+#define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2
+
+/* Field values */
+#define PORT_REG_CTRL_PSTATE_DISABLED  0
+#define PORT_REG_CTRL_PSTATE_FORWARD   3
+
+#define PHY_REG_CTRL1_ENERGY_DET_OFF   0
+#define 

[U-Boot] [PATCH v3 1/2] net: Remove unused mv88e61xx switch driver

[Kevin Smith]

No boards are using this driver.  Remove in preparation for a new
driver with integrated PHY support.

Signed-off-by: Kevin Smith 
Acked-by: Joe Hershberger 
Cc: Prafulla Wadaskar 
Cc: Albert ARIBAUD 
Cc: Stefan Roese 
Cc: Marek Vasut 
---
 drivers/net/phy/mv88e61xx.c | 537 
 drivers/net/phy/mv88e61xx.h |  61 -
 include/netdev.h|  58 -
 3 files changed, 656 deletions(-)
 delete mode 100644 drivers/net/phy/mv88e61xx.c
 delete mode 100644 drivers/net/phy/mv88e61xx.h

diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
deleted file mode 100644
index 302abe8..000
--- a/drivers/net/phy/mv88e61xx.c
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor 
- * Prafulla Wadaskar 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include "mv88e61xx.h"
-
-/*
- * Uncomment either of the following line for local debug control;
- * otherwise global debug control will apply.
- */
-
-/* #undef DEBUG */
-/* #define DEBUG */
-
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-/* Chip Address mode
- * The Switch support two modes of operation
- * 1. single chip mode and
- * 2. Multi-chip mode
- * Refer section 9.2 &9.3 in chip datasheet-02 for more details
- *
- * By default single chip mode is configured
- * multichip mode operation can be configured in board header
- */
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
-{
-   u16 reg = 0;
-   u32 timeout = MV88E61XX_PHY_TIMEOUT;
-
-   /* Poll till SMIBusy bit is clear */
-   do {
-   miiphy_read(name, devaddr, 0x0, );
-   if (timeout-- == 0) {
-   printf("SMI busy timeout\n");
-   return -1;
-   }
-   } while (reg & (1 << 15));
-   return 0;
-}
-
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
-   u32 reg_ofs, u16 data)
-{
-   u16 mii_dev_addr;
-
-   /* command to read PHY dev address */
-   if (miiphy_read(name, 0xEE, 0xEE, _dev_addr)) {
-   printf("Error..could not read PHY dev address\n");
-   return;
-   }
-   mv88e61xx_busychk_multic(name, mii_dev_addr);
-   /* Write data to Switch indirect data register */
-   miiphy_write(name, mii_dev_addr, 0x1, data);
-   /* Write command to Switch indirect command register (write) */
-   miiphy_write(name, mii_dev_addr, 0x0,
-reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
-15));
-}
-
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
-   u32 reg_ofs, u16 *data)
-{
-   u16 mii_dev_addr;
-
-   /* command to read PHY dev address */
-   if (miiphy_read(name, 0xEE, 0xEE, _dev_addr)) {
-   printf("Error..could not read PHY dev address\n");
-   return;
-   }
-   mv88e61xx_busychk_multic(name, mii_dev_addr);
-   /* Write command to Switch indirect command register (read) */
-   miiphy_write(name, mii_dev_addr, 0x0,
-reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
-15));
-   mv88e61xx_busychk_multic(name, mii_dev_addr);
-   /* Read data from Switch indirect data register */
-   miiphy_read(name, mii_dev_addr, 0x1, data);
-}
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
-
-/*
- * Convenience macros for switch device/port reads/writes
- * These macros output valid 'mv88e61xx' U_BOOT_CMDs
- */
-
-#ifndef DEBUG
-#define WR_SWITCH_REG wr_switch_reg
-#define RD_SWITCH_REG rd_switch_reg
-#define WR_SWITCH_PORT_REG(n, p, r, d) \
-   WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#define RD_SWITCH_PORT_REG(n, p, r, d) \
-   RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#else
-static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
-{
-   printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
-   name, dev_adr, reg_ofs, data);
-   wr_switch_reg(name, dev_adr, reg_ofs, data);
-}
-static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
-{
-   rd_switch_reg(name, dev_adr, reg_ofs, data);
-   printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
-   name, dev_adr, reg_ofs, *data);
-}
-static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
-   u16 data)
-{
-   printf("mv88e61xx %s port %02x reg %02x write %04x\n",
-   name, prt_adr, reg_ofs, data);
-   wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
-}
-static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
-   u16 *data)
-{
-   rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
- 

Re: [U-Boot] [PATCH 0/6] Add Pine64 support

[Hans de Goede]

Hi,

On 31-03-16 21:22, Hans de Goede wrote:

Hi,

On 31-03-16 21:15, Alexander Graf wrote:




Am 31.03.2016 um 20:53 schrieb Hans de Goede :

Hi,


On 29-03-16 18:08, Alexander Graf wrote:



On 29.03.16 17:45, Hans de Goede wrote:
Hi,


On 03/29/2016 05:29 PM, Alexander Graf wrote:
The Pine64 is a kickstarter backed SBC that runs on the Allwinner A64
SoC.
This SoC can run AArch64 code, so this patch set lifts all arm version
indepenent sunxi code into a mach directory and builds the A64 code
as armv8 (aarch64) code.

With these patches applied, I can successfully boot my 1GB Pine64+ board
with an openSUSE EFI image.


Can you provide some quick instructions on how to test this ? Bonus
point for a link to a boot0.bin which I can dd to a sdcard and use
with a u-boot.bin build with these patches.


Sure. Grab these all the files in this directory:

   http://csgraf.de/agraf/pine64

Then do

   $ gcc pine64_image.c -o pine64_image
   $ cat bl31.bin /u-boot.bin > bl31uboot.bin
   $ ./pine64_image scp.bin bl31uboot.bin u-boot.img
   $ dd if=boot0.bin of=/dev/mmcblk0 seek=16
   $ dd if=u-boot.img of=/dev/mmcblk0 seek=80

That should give you a working system. The scp.bin and boot0.bin are
from the Allwinner binary distribution. ATF (bl31.bin) is built from
these sources:


https://build.opensuse.org/package/show/devel:ARM:Factory:Contrib:Pine64/firmware-pine64


Enjoy,


Thanks, works like a charm.

I've applied the entire series to my tree, except for
"[PATCH 3/6] arm: Allow u32 as addrs for readX/writeX"
instead I've added 2 extra casts to your
"[PATCH 4/6] sunxi: Explicitly cast u32 pointer conversions"
patch, which is enough to build warning free for me.

I still have some other patches to process, I'll send a pull-req
tomorrow morning.


Thanks :)



Note I've squashed the following fixes into
"[PATCH 5/6] sunxi: Add support for Allwinner A64 SoCs" :

--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -352,10 +352,10 @@ struct sunxi_ccm_reg {

#if defined(CONFIG_MACH_SUN50I)
#define MBUS_CLK_DEFAULT   0x8102 /* PLL6x2 / 3 */
-#elif !defined(CONFIG_MACH_SUN8I)
-#define MBUS_CLK_DEFAULT   0x8101 /* PLL6 / 2 */
-#else
+#elif defined(CONFIG_MACH_SUN8I)
#define MBUS_CLK_DEFAULT   0x8103 /* PLL6 / 4 */
+#else
+#define MBUS_CLK_DEFAULT 0x8101 /* PLL6 / 2 */
#endif
#define MBUS_CLK_GATE  (0x1 << 31)


--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -92,12 +92,6 @@ static inline unsigned long read_mpidr(void)

#define BSP_COREID 0

-static inline void sdelay(unsigned long n)
-{
-   int i;
-   for (i = 0; i < n; i++) asm volatile("");
-}
-


How did you manage to build without sdelay? The sun6i clock code used it, no? 
Or is something there guarded with CONFIG_SPL_BUILD?


The code in question is #ifdef CONFIG_SPL_BUILD I guess we will need to
fix this somehow when we get SPL support, I'm pretty sure the above
is not the right solution.


p.s.

This patchset broke every other sunxi board! 2 very minor issues, already
fixed up in my tree. I always build all sunxi builds before sending
out a pull-req :)

Regards,

Hans

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Re: [U-Boot] [PATCH 0/6] Add Pine64 support

[Hans de Goede]

Hi,

On 31-03-16 21:15, Alexander Graf wrote:




Am 31.03.2016 um 20:53 schrieb Hans de Goede :

Hi,


On 29-03-16 18:08, Alexander Graf wrote:



On 29.03.16 17:45, Hans de Goede wrote:
Hi,


On 03/29/2016 05:29 PM, Alexander Graf wrote:
The Pine64 is a kickstarter backed SBC that runs on the Allwinner A64
SoC.
This SoC can run AArch64 code, so this patch set lifts all arm version
indepenent sunxi code into a mach directory and builds the A64 code
as armv8 (aarch64) code.

With these patches applied, I can successfully boot my 1GB Pine64+ board
with an openSUSE EFI image.


Can you provide some quick instructions on how to test this ? Bonus
point for a link to a boot0.bin which I can dd to a sdcard and use
with a u-boot.bin build with these patches.


Sure. Grab these all the files in this directory:

   http://csgraf.de/agraf/pine64

Then do

   $ gcc pine64_image.c -o pine64_image
   $ cat bl31.bin /u-boot.bin > bl31uboot.bin
   $ ./pine64_image scp.bin bl31uboot.bin u-boot.img
   $ dd if=boot0.bin of=/dev/mmcblk0 seek=16
   $ dd if=u-boot.img of=/dev/mmcblk0 seek=80

That should give you a working system. The scp.bin and boot0.bin are
from the Allwinner binary distribution. ATF (bl31.bin) is built from
these sources:


https://build.opensuse.org/package/show/devel:ARM:Factory:Contrib:Pine64/firmware-pine64


Enjoy,


Thanks, works like a charm.

I've applied the entire series to my tree, except for
"[PATCH 3/6] arm: Allow u32 as addrs for readX/writeX"
instead I've added 2 extra casts to your
"[PATCH 4/6] sunxi: Explicitly cast u32 pointer conversions"
patch, which is enough to build warning free for me.

I still have some other patches to process, I'll send a pull-req
tomorrow morning.


Thanks :)



Note I've squashed the following fixes into
"[PATCH 5/6] sunxi: Add support for Allwinner A64 SoCs" :

--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -352,10 +352,10 @@ struct sunxi_ccm_reg {

#if defined(CONFIG_MACH_SUN50I)
#define MBUS_CLK_DEFAULT   0x8102 /* PLL6x2 / 3 */
-#elif !defined(CONFIG_MACH_SUN8I)
-#define MBUS_CLK_DEFAULT   0x8101 /* PLL6 / 2 */
-#else
+#elif defined(CONFIG_MACH_SUN8I)
#define MBUS_CLK_DEFAULT   0x8103 /* PLL6 / 4 */
+#else
+#define MBUS_CLK_DEFAULT 0x8101 /* PLL6 / 2 */
#endif
#define MBUS_CLK_GATE  (0x1 << 31)


--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -92,12 +92,6 @@ static inline unsigned long read_mpidr(void)

#define BSP_COREID 0

-static inline void sdelay(unsigned long n)
-{
-   int i;
-   for (i = 0; i < n; i++) asm volatile("");
-}
-


How did you manage to build without sdelay? The sun6i clock code used it, no? 
Or is something there guarded with CONFIG_SPL_BUILD?


The code in question is #ifdef CONFIG_SPL_BUILD I guess we will need to
fix this somehow when we get SPL support, I'm pretty sure the above
is not the right solution.

Regards,

Hans
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Re: [U-Boot] [PATCH 0/6] Add Pine64 support

[Alexander Graf]

> Am 31.03.2016 um 20:53 schrieb Hans de Goede :
> 
> Hi,
> 
>> On 29-03-16 18:08, Alexander Graf wrote:
>> 
>> 
>>> On 29.03.16 17:45, Hans de Goede wrote:
>>> Hi,
>>> 
 On 03/29/2016 05:29 PM, Alexander Graf wrote:
 The Pine64 is a kickstarter backed SBC that runs on the Allwinner A64
 SoC.
 This SoC can run AArch64 code, so this patch set lifts all arm version
 indepenent sunxi code into a mach directory and builds the A64 code
 as armv8 (aarch64) code.
 
 With these patches applied, I can successfully boot my 1GB Pine64+ board
 with an openSUSE EFI image.
>>> 
>>> Can you provide some quick instructions on how to test this ? Bonus
>>> point for a link to a boot0.bin which I can dd to a sdcard and use
>>> with a u-boot.bin build with these patches.
>> 
>> Sure. Grab these all the files in this directory:
>> 
>>   http://csgraf.de/agraf/pine64
>> 
>> Then do
>> 
>>   $ gcc pine64_image.c -o pine64_image
>>   $ cat bl31.bin /u-boot.bin > bl31uboot.bin
>>   $ ./pine64_image scp.bin bl31uboot.bin u-boot.img
>>   $ dd if=boot0.bin of=/dev/mmcblk0 seek=16
>>   $ dd if=u-boot.img of=/dev/mmcblk0 seek=80
>> 
>> That should give you a working system. The scp.bin and boot0.bin are
>> from the Allwinner binary distribution. ATF (bl31.bin) is built from
>> these sources:
>> 
>> 
>> https://build.opensuse.org/package/show/devel:ARM:Factory:Contrib:Pine64/firmware-pine64
>> 
>> 
>> Enjoy,
> 
> Thanks, works like a charm.
> 
> I've applied the entire series to my tree, except for
> "[PATCH 3/6] arm: Allow u32 as addrs for readX/writeX"
> instead I've added 2 extra casts to your
> "[PATCH 4/6] sunxi: Explicitly cast u32 pointer conversions"
> patch, which is enough to build warning free for me.
> 
> I still have some other patches to process, I'll send a pull-req
> tomorrow morning.

Thanks :)

> 
> Note I've squashed the following fixes into
> "[PATCH 5/6] sunxi: Add support for Allwinner A64 SoCs" :
> 
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -352,10 +352,10 @@ struct sunxi_ccm_reg {
> 
> #if defined(CONFIG_MACH_SUN50I)
> #define MBUS_CLK_DEFAULT   0x8102 /* PLL6x2 / 3 */
> -#elif !defined(CONFIG_MACH_SUN8I)
> -#define MBUS_CLK_DEFAULT   0x8101 /* PLL6 / 2 */
> -#else
> +#elif defined(CONFIG_MACH_SUN8I)
> #define MBUS_CLK_DEFAULT   0x8103 /* PLL6 / 4 */
> +#else
> +#define MBUS_CLK_DEFAULT 0x8101 /* PLL6 / 2 */
> #endif
> #define MBUS_CLK_GATE  (0x1 << 31)
> 
> 
> --- a/arch/arm/include/asm/system.h
> +++ b/arch/arm/include/asm/system.h
> @@ -92,12 +92,6 @@ static inline unsigned long read_mpidr(void)
> 
> #define BSP_COREID 0
> 
> -static inline void sdelay(unsigned long n)
> -{
> -   int i;
> -   for (i = 0; i < n; i++) asm volatile("");
> -}
> -

How did you manage to build without sdelay? The sun6i clock code used it, no? 
Or is something there guarded with CONFIG_SPL_BUILD?

Alex

> void __asm_flush_dcache_all(void);
> void __asm_invalidate_dcache_all(void);
> void __asm_flush_dcache_range(u64 start, u64 end);
> 
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -76,10 +76,7 @@ DECLARE_GLOBAL_DATA_PTR;
> /* add board specific code here */
> int board_init(void)
> {
> -#ifndef CONFIG_ARM64
> -   int id_pfr1;
> -#endif
> -   int ret;
> +   __maybe_unused int id_pfr1, ret;
> 
>gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
> 
> Regards,
> 
> Hans

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Re: [U-Boot] [PATCH 0/6] Add Pine64 support

[Hans de Goede]

Hi,

On 29-03-16 18:08, Alexander Graf wrote:



On 29.03.16 17:45, Hans de Goede wrote:

Hi,

On 03/29/2016 05:29 PM, Alexander Graf wrote:

The Pine64 is a kickstarter backed SBC that runs on the Allwinner A64
SoC.
This SoC can run AArch64 code, so this patch set lifts all arm version
indepenent sunxi code into a mach directory and builds the A64 code
as armv8 (aarch64) code.

With these patches applied, I can successfully boot my 1GB Pine64+ board
with an openSUSE EFI image.


Can you provide some quick instructions on how to test this ? Bonus
point for a link to a boot0.bin which I can dd to a sdcard and use
with a u-boot.bin build with these patches.


Sure. Grab these all the files in this directory:

   http://csgraf.de/agraf/pine64

Then do

   $ gcc pine64_image.c -o pine64_image
   $ cat bl31.bin /u-boot.bin > bl31uboot.bin
   $ ./pine64_image scp.bin bl31uboot.bin u-boot.img
   $ dd if=boot0.bin of=/dev/mmcblk0 seek=16
   $ dd if=u-boot.img of=/dev/mmcblk0 seek=80

That should give you a working system. The scp.bin and boot0.bin are
from the Allwinner binary distribution. ATF (bl31.bin) is built from
these sources:


https://build.opensuse.org/package/show/devel:ARM:Factory:Contrib:Pine64/firmware-pine64


Enjoy,


Thanks, works like a charm.

I've applied the entire series to my tree, except for
"[PATCH 3/6] arm: Allow u32 as addrs for readX/writeX"
instead I've added 2 extra casts to your
"[PATCH 4/6] sunxi: Explicitly cast u32 pointer conversions"
patch, which is enough to build warning free for me.

I still have some other patches to process, I'll send a pull-req
tomorrow morning.

Note I've squashed the following fixes into
"[PATCH 5/6] sunxi: Add support for Allwinner A64 SoCs" :

--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -352,10 +352,10 @@ struct sunxi_ccm_reg {

 #if defined(CONFIG_MACH_SUN50I)
 #define MBUS_CLK_DEFAULT   0x8102 /* PLL6x2 / 3 */
-#elif !defined(CONFIG_MACH_SUN8I)
-#define MBUS_CLK_DEFAULT   0x8101 /* PLL6 / 2 */
-#else
+#elif defined(CONFIG_MACH_SUN8I)
 #define MBUS_CLK_DEFAULT   0x8103 /* PLL6 / 4 */
+#else
+#define MBUS_CLK_DEFAULT 0x8101 /* PLL6 / 2 */
 #endif
 #define MBUS_CLK_GATE  (0x1 << 31)


--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -92,12 +92,6 @@ static inline unsigned long read_mpidr(void)

 #define BSP_COREID 0

-static inline void sdelay(unsigned long n)
-{
-   int i;
-   for (i = 0; i < n; i++) asm volatile("");
-}
-
 void __asm_flush_dcache_all(void);
 void __asm_invalidate_dcache_all(void);
 void __asm_flush_dcache_range(u64 start, u64 end);

--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -76,10 +76,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* add board specific code here */
 int board_init(void)
 {
-#ifndef CONFIG_ARM64
-   int id_pfr1;
-#endif
-   int ret;
+   __maybe_unused int id_pfr1, ret;

gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);

Regards,

Hans
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[U-Boot] [PATCH 6/7] ARM: rmobile: Add support salvator-x board

[Nobuhiro Iwamatsu]

Salvator-x is an entry level development board based on
R-Car H3 SoC (R8A7795). This commit supports SCIF only.

Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Kconfig.64  |  16 +
 board/renesas/salvator-x/Kconfig  |  15 +
 board/renesas/salvator-x/MAINTAINERS  |   6 ++
 board/renesas/salvator-x/Makefile |   9 +++
 board/renesas/salvator-x/salvator-x.c | 120 ++
 configs/salvator-x_defconfig  |   4 ++
 include/configs/rcar-gen3-common.h| 105 +
 include/configs/salvator-x.h  |  54 +++
 8 files changed, 329 insertions(+)
 create mode 100644 board/renesas/salvator-x/Kconfig
 create mode 100644 board/renesas/salvator-x/MAINTAINERS
 create mode 100644 board/renesas/salvator-x/Makefile
 create mode 100644 board/renesas/salvator-x/salvator-x.c
 create mode 100644 configs/salvator-x_defconfig
 create mode 100644 include/configs/rcar-gen3-common.h
 create mode 100644 include/configs/salvator-x.h

diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index af1a76a..2a7eeba 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -1,12 +1,28 @@
 if RCAR_GEN3
 
+config R8A7795
+   bool
+
 choice
prompt "Renesus ARM64 SoCs board select"
optional
 
+config TARGET_SALVATOR_X
+   bool "Salvator-X board"
+   select R8A7795
+   help
+  Support for Renesas R-Car Gen3 R8a7795 platform
+
 endchoice
 
 config SYS_SOC
default "rmobile"
 
+config RCAR_GEN3_EXTRAM_BOOT
+   bool "Enable boot from RAM"
+   depends on TARGET_SALVATOR_X
+   default n
+
+source "board/renesas/salvator-x/Kconfig"
+
 endif
diff --git a/board/renesas/salvator-x/Kconfig b/board/renesas/salvator-x/Kconfig
new file mode 100644
index 000..ed4c479
--- /dev/null
+++ b/board/renesas/salvator-x/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SALVATOR_X
+
+config SYS_SOC
+   default "rmobile"
+
+config SYS_BOARD
+   default "salvator-x"
+
+config SYS_VENDOR
+   default "renesas"
+
+config SYS_CONFIG_NAME
+   default "salvator-x"
+
+endif
diff --git a/board/renesas/salvator-x/MAINTAINERS 
b/board/renesas/salvator-x/MAINTAINERS
new file mode 100644
index 000..abd05c8
--- /dev/null
+++ b/board/renesas/salvator-x/MAINTAINERS
@@ -0,0 +1,6 @@
+SALVATOR_X BOARD
+M: Nobuhiro Iwamatsu 
+S: Maintained
+F: board/renesas/salvator-x/
+F: include/configs/salvator-x.h
+F: configs/salvator-x_defconfig
diff --git a/board/renesas/salvator-x/Makefile 
b/board/renesas/salvator-x/Makefile
new file mode 100644
index 000..61b0d06
--- /dev/null
+++ b/board/renesas/salvator-x/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/salvator-x/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := salvator-x.o ../rcar-common/common.o
diff --git a/board/renesas/salvator-x/salvator-x.c 
b/board/renesas/salvator-x/salvator-x.c
new file mode 100644
index 000..47242c6
--- /dev/null
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -0,0 +1,120 @@
+/*
+ * board/renesas/salvator-x/salvator-x.c
+ * This file is Salvator-X board support.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Nobuhiro Iwamatsu 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR0xE6150904
+#define CPGWPR  0xE615090C
+
+#define CLK2MHZ(clk)   (clk / 1000 / 1000)
+void s_init(void)
+{
+   struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+   struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+   /* Watchdog init */
+   writel(0xA5A5A500, >rwtcsra);
+   writel(0xA5A5A500, >swtcsra);
+
+   writel(0xA5A5, CPGWPCR);
+   writel(0x, CPGWPR);
+}
+
+#define GSX_MSTP112(1 << 12)   /* 3DG */
+#define TMU0_MSTP125   (1 << 25)   /* secure */
+#define TMU1_MSTP124   (1 << 24)   /* non-secure */
+#define SCIF2_MSTP310  (1 << 10)   /* SCIF2 */
+
+int board_early_init_f(void)
+{
+   /* TMU0,1 *//* which use ? */
+   mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
+   /* SCIF2 */
+   mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
+
+   return 0;
+}
+
+/* SYSC */
+/* R/- 32 Power status register 2(3DG) */
+#defineSYSC_PWRSR2 0xE6180100
+/* -/W 32 Power resume control register 2 (3DG) */
+#defineSYSC_PWRONCR2   0xE618010C
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+   /* adress of boot parameters */
+   gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 

[U-Boot] [PATCH 3/7] ARM: rmobile: Move rcar-gen2-common to rcar-common

[Nobuhiro Iwamatsu]

To common use of rcar-gen2-common directory in the R-Car SoCs, and change from
rcar-gen2-common to rcar-common.

Signed-off-by: Nobuhiro Iwamatsu 
---
 board/renesas/alt/Makefile  |  2 +-
 board/renesas/gose/Makefile |  2 +-
 board/renesas/koelsch/Makefile  |  2 +-
 board/renesas/porter/Makefile   |  2 +-
 board/renesas/rcar-common/common.c  | 59 +
 board/renesas/rcar-gen2-common/common.c | 59 -
 board/renesas/silk/Makefile |  2 +-
 board/renesas/stout/Makefile|  2 +-
 8 files changed, 65 insertions(+), 65 deletions(-)
 create mode 100644 board/renesas/rcar-common/common.c
 delete mode 100644 board/renesas/rcar-gen2-common/common.c

diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile
index 6904e39..22ab1f4 100644
--- a/board/renesas/alt/Makefile
+++ b/board/renesas/alt/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := alt.o qos.o ../rcar-gen2-common/common.o
+obj-y  := alt.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile
index 2dac748..e09ae1e 100644
--- a/board/renesas/gose/Makefile
+++ b/board/renesas/gose/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := gose.o qos.o ../rcar-gen2-common/common.o
+obj-y  := gose.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile
index c10bba5..15f111c 100644
--- a/board/renesas/koelsch/Makefile
+++ b/board/renesas/koelsch/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := koelsch.o qos.o ../rcar-gen2-common/common.o
+obj-y  := koelsch.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/porter/Makefile b/board/renesas/porter/Makefile
index dbf32e9..09c07ef 100644
--- a/board/renesas/porter/Makefile
+++ b/board/renesas/porter/Makefile
@@ -7,4 +7,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := porter.o qos.o ../rcar-gen2-common/common.o
+obj-y  := porter.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/rcar-common/common.c 
b/board/renesas/rcar-common/common.c
new file mode 100644
index 000..be2b945
--- /dev/null
+++ b/board/renesas/rcar-common/common.c
@@ -0,0 +1,59 @@
+/*
+ * board/renesas/rcar-common/common.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu 
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define TSTR0  0x04
+#define TSTR0_STR0 0x01
+
+static struct mstp_ctl mstptbl[] = {
+   { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
+   RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
+   { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
+   RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
+   { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
+   RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
+   { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
+   RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
+   { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
+   RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
+   { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
+   RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
+   /* No MSTP6 */
+   { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
+   RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
+   { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
+   RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
+   { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
+   RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
+   { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
+RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
+   { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
+RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
+};
+
+void arch_preboot_os(void)
+{
+   int i;
+
+   /* stop TMU0 */
+   mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
+
+   /* Stop module clock */
+   for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
+   mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
+mstptbl[i].s_ena);
+   mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
+mstptbl[i].r_ena);
+   }
+}
diff --git a/board/renesas/rcar-gen2-common/common.c 
b/board/renesas/rcar-gen2-common/common.c
deleted file mode 100644
index 0103f42..000
--- a/board/renesas/rcar-gen2-common/common.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * board/renesas/rcar-gen2-common/common.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013 Nobuhiro Iwamatsu 
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define TSTR0

[U-Boot] [PATCH 4/7] ARM: rmobile: Add support R-Car Generation 3

[Nobuhiro Iwamatsu]

This adds supporting R-Car Generation 3 (Gen3) as Renesas ARM64 SoC.

Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Kconfig  |   5 ++
 arch/arm/mach-rmobile/Kconfig.64   |  12 +++
 .../arm/mach-rmobile/include/mach/rcar-gen3-base.h | 100 +
 arch/arm/mach-rmobile/lowlevel_init_gen3.S |  76 
 board/renesas/rcar-common/common.c |   6 +-
 5 files changed, 198 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-rmobile/Kconfig.64
 create mode 100644 arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
 create mode 100644 arch/arm/mach-rmobile/lowlevel_init_gen3.S

diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 56c3f68..4b05d78 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -8,8 +8,13 @@ config RCAR_32
bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
select CPU_V7
 
+config RCAR_GEN3
+   bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
+   select ARM64
+
 endchoice
 
 source "arch/arm/mach-rmobile/Kconfig.32"
+source "arch/arm/mach-rmobile/Kconfig.64"
 
 endif
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
new file mode 100644
index 000..af1a76a
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -0,0 +1,12 @@
+if RCAR_GEN3
+
+choice
+   prompt "Renesus ARM64 SoCs board select"
+   optional
+
+endchoice
+
+config SYS_SOC
+   default "rmobile"
+
+endif
diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h 
b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
new file mode 100644
index 000..fbd87c4
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
@@ -0,0 +1,100 @@
+/*
+ * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_RCAR_GEN3_BASE_H
+#define __ASM_ARCH_RCAR_GEN3_BASE_H
+
+/*
+ * R-Car (R8A7750) I/O Addresses
+ */
+#define RWDT_BASE  0xE602
+#define SWDT_BASE  0xE603
+#define LBSC_BASE  0xEE220200
+#define TMU_BASE   0xE61E
+#define GPIO5_BASE 0xE6055000
+
+/* SCIF */
+#define SCIF0_BASE 0xE6E6
+#define SCIF1_BASE 0xE6E68000
+#define SCIF2_BASE 0xE6E88000
+#define SCIF3_BASE 0xE6C5
+#define SCIF4_BASE 0xE6C4
+#define SCIF5_BASE 0xE6F3
+
+/* Module stop status register */
+#define MSTPSR00xE6150030
+#define MSTPSR10xE6150038
+#define MSTPSR20xE6150040
+#define MSTPSR30xE6150048
+#define MSTPSR40xE615004C
+#define MSTPSR50xE615003C
+#define MSTPSR60xE61501C0
+#define MSTPSR70xE61501C4
+#define MSTPSR80xE61509A0
+#define MSTPSR90xE61509A4
+#define MSTPSR10   0xE61509A8
+#define MSTPSR11   0xE61509AC
+
+/* Realtime module stop control register */
+#define RMSTPCR0   0xE6150110
+#define RMSTPCR1   0xE6150114
+#define RMSTPCR2   0xE6150118
+#define RMSTPCR3   0xE615011C
+#define RMSTPCR4   0xE6150120
+#define RMSTPCR5   0xE6150124
+#define RMSTPCR6   0xE6150128
+#define RMSTPCR7   0xE615012C
+#define RMSTPCR8   0xE6150980
+#define RMSTPCR9   0xE6150984
+#define RMSTPCR10  0xE6150988
+#define RMSTPCR11  0xE615098C
+
+/* System module stop control register */
+#define SMSTPCR0   0xE6150130
+#define SMSTPCR1   0xE6150134
+#define SMSTPCR2   0xE6150138
+#define SMSTPCR3   0xE615013C
+#define SMSTPCR4   0xE6150140
+#define SMSTPCR5   0xE6150144
+#define SMSTPCR6   0xE6150148
+#define SMSTPCR7   0xE615014C
+#define SMSTPCR8   0xE6150990
+#define SMSTPCR9   0xE6150994
+#define SMSTPCR10  0xE6150998
+#define SMSTPCR11  0xE615099C
+
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI0_BASE   0xEE10
+#define CONFIG_SYS_SH_SDHI1_BASE   0xEE12
+#define CONFIG_SYS_SH_SDHI2_BASE   0xEE14
+#define CONFIG_SYS_SH_SDHI3_BASE   0xEE16
+
+/* PFC */
+#define PFC_PUEN6   0xE6060418
+#define PUEN_USB1_OVC   (1 << 2)
+#define PUEN_USB1_PWEN  (1 << 1)
+
+#ifndef __ASSEMBLY__
+#include 
+
+/* RWDT */
+struct rcar_rwdt {
+   u32 rwtcnt;
+   u32 rwtcsra;
+   u32 rwtcsrb;
+};
+
+/* SWDT */
+struct rcar_swdt {
+   u32 swtcnt;
+   u32 swtcsra;
+   u32 swtcsrb;
+};
+#endif
+
+#endif /* 

[U-Boot] [PATCH 7/7] ARM: rmobile: rcar-common: Fix warning of type difference

[Nobuhiro Iwamatsu]

Signed-off-by: Nobuhiro Iwamatsu 
---
 board/renesas/rcar-common/common.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/renesas/rcar-common/common.c 
b/board/renesas/rcar-common/common.c
index d6144c2..33c1726 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -55,9 +55,11 @@ void arch_preboot_os(void)
 
/* Stop module clock */
for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
-   mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
+   mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr,
+mstptbl[i].s_dis,
 mstptbl[i].s_ena);
-   mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
+   mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr,
+mstptbl[i].r_dis,
 mstptbl[i].r_ena);
}
 }
-- 
2.8.0.rc3

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[U-Boot] [PATCH 1/7] serial: sh: Add support R8A7795

[Nobuhiro Iwamatsu]

From: Hiroyuki Yokoyama 

This can be used in the same way as other R-CAR serial setting.

Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Nobuhiro Iwamatsu 
---
 drivers/serial/serial_sh.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index cbc2929..a95684b 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -225,7 +225,8 @@ struct uart_port {
 # define SCIF_ORER 0x0001  /* Overrun error bit */
 # define SCSCR_INIT(port)  0x38/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-   defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+   defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \
+   defined(CONFIG_R8A7795)
 # if defined(CONFIG_SCIF_A)
 #  define SCIF_ORER0x0200
 # else
-- 
2.8.0.rc3

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[U-Boot] [PATCH 2/7] ARM: rmobile: Create R-Car 32bit (Gen1 and Gen2) for Kconfig

[Nobuhiro Iwamatsu]

This creates Kconfig of R-Car 32bit for Kconfig of R-Car 64bit (Gen3).

Signed-off-by: Nobuhiro Iwamatsu 
---
 arch/arm/Kconfig |  1 -
 arch/arm/mach-rmobile/Kconfig| 87 +++---
 arch/arm/mach-rmobile/Kconfig.32 | 90 
 3 files changed, 96 insertions(+), 82 deletions(-)
 create mode 100644 arch/arm/mach-rmobile/Kconfig.32

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dafb98f..8d719a3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -502,7 +502,6 @@ config OMAP54XX
 
 config ARCH_RMOBILE
bool "Renesas ARM SoCs"
-   select CPU_V7
 
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 5915768..56c3f68 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -1,90 +1,15 @@
 if ARCH_RMOBILE
 
 choice
-   prompt "Renesus ARM SoCs board select"
-   optional
+   prompt "Target Renesas SoC select"
+   default RCAR_32
 
-config TARGET_ARMADILLO_800EVA
-   bool "armadillo 800 eva board"
-
-config TARGET_GOSE
-   bool "Gose board"
-   select DM
-   select DM_SERIAL
-
-config TARGET_KOELSCH
-   bool "Koelsch board"
-   select DM
-   select DM_SERIAL
-
-config TARGET_LAGER
-   bool "Lager board"
-   select DM
-   select DM_SERIAL
-
-config TARGET_KZM9G
-   bool "KZM9D board"
-
-config TARGET_ALT
-   bool "Alt board"
-   select DM
-   select DM_SERIAL
-
-config TARGET_SILK
-   bool "Silk board"
-   select DM
-   select DM_SERIAL
-
-config TARGET_PORTER
-   bool "Porter board"
-   select DM
-   select DM_SERIAL
-
-config TARGET_STOUT
-   bool "Stout board"
-   select DM
-   select DM_SERIAL
-
-endchoice
-
-config SYS_SOC
-   default "rmobile"
-
-config RMOBILE_EXTRAM_BOOT
-   bool "Enable boot from RAM"
-   depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || 
TARGET_PORTER || TARGET_SILK || TARGET_STOUT
-   default n
-
-choice
-   prompt "Qos setting primary"
-   depends on TARGET_ALT || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
-   default QOS_PRI_NORMAL
-
-config QOS_PRI_NORMAL
-   bool "Non primary"
-   help
-  Select normal mode for QoS setting.
-
-config QOS_PRI_MEDIA
-   bool "Media primary"
-   help
-  Select multimedia primary mode for QoS setting.
-
-config QOS_PRI_GFX
-   bool "GFX primary"
-   help
-  Select GFX(graphics) primary mode for QoS setting.
+config RCAR_32
+   bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
+   select CPU_V7
 
 endchoice
 
-source "board/atmark-techno/armadillo-800eva/Kconfig"
-source "board/renesas/gose/Kconfig"
-source "board/renesas/koelsch/Kconfig"
-source "board/renesas/lager/Kconfig"
-source "board/kmc/kzm9g/Kconfig"
-source "board/renesas/alt/Kconfig"
-source "board/renesas/silk/Kconfig"
-source "board/renesas/porter/Kconfig"
-source "board/renesas/stout/Kconfig"
+source "arch/arm/mach-rmobile/Kconfig.32"
 
 endif
diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
new file mode 100644
index 000..b485953
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -0,0 +1,90 @@
+if RCAR_32
+
+choice
+   prompt "Renesus ARM SoCs board select"
+   optional
+
+config TARGET_ARMADILLO_800EVA
+   bool "armadillo 800 eva board"
+
+config TARGET_GOSE
+   bool "Gose board"
+   select DM
+   select DM_SERIAL
+
+config TARGET_KOELSCH
+   bool "Koelsch board"
+   select DM
+   select DM_SERIAL
+
+config TARGET_LAGER
+   bool "Lager board"
+   select DM
+   select DM_SERIAL
+
+config TARGET_KZM9G
+   bool "KZM9D board"
+
+config TARGET_ALT
+   bool "Alt board"
+   select DM
+   select DM_SERIAL
+
+config TARGET_SILK
+   bool "Silk board"
+   select DM
+   select DM_SERIAL
+
+config TARGET_PORTER
+   bool "Porter board"
+   select DM
+   select DM_SERIAL
+
+config TARGET_STOUT
+   bool "Stout board"
+   select DM
+   select DM_SERIAL
+
+endchoice
+
+config SYS_SOC
+   default "rmobile"
+
+config RMOBILE_EXTRAM_BOOT
+   bool "Enable boot from RAM"
+   depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || 
TARGET_PORTER || TARGET_SILK || TARGET_STOUT
+   default n
+
+choice
+   prompt "Qos setting primary"
+   depends on TARGET_ALT || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
+   default QOS_PRI_NORMAL
+
+config QOS_PRI_NORMAL
+   bool "Non primary"
+   help
+  Select normal mode for QoS setting.
+
+config QOS_PRI_MEDIA
+   bool "Media primary"
+   help
+  Select multimedia primary mode for QoS setting.
+
+config QOS_PRI_GFX
+   bool "GFX primary"
+   help
+  Select GFX(graphics) primary mode for QoS setting.
+
+endchoice
+
+source 

[U-Boot] [PATCH v3 0/1] Use LS2080A as the only SoC name

[York Sun]

Not long ago, a change was made in U-Boot to switch the primary SoC from
LS2085A to LS2080A. SoC name and board names were changed. It turns out
the same board support both SoCs with a socket. It is possible to swtich
SoC. In this case, using one unified image is more appropriate. If future
SoC can be hosted on the same boards, they should be added.

At this moment, the board name remains LS2080ARDB and LS2080AQDS. They
don't match the labels on the boards. Should this become a concern, we
can rename the boards in a separated patch.

Tested on LS2085ARDB with both personalities.

Changes in v3:
Fix checking AIOP. Tested on LS2080ARDB.

Changes in v2:
Add checking for SVR before starting AIOP
Drop RFC from subject

York Sun (1):
  armv8: LS2080A: Consolidate LS2080A and LS2085A

 arch/arm/cpu/armv8/fsl-layerscape/Makefile |4 ---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|9 ---
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c |6 -
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |2 +-
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   26 ++-
 arch/arm/cpu/armv8/fsl-layerscape/spl.c|4 +--
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |9 ++-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |2 +-
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |2 +-
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |3 +++
 board/freescale/ls2080a/ddr.c  |   27 +++-
 board/freescale/ls2080a/ls2080a.c  |2 +-
 board/freescale/ls2080aqds/MAINTAINERS |2 --
 board/freescale/ls2080aqds/ddr.c   |   27 +++-
 board/freescale/ls2080aqds/ls2080aqds.c|2 +-
 board/freescale/ls2080ardb/MAINTAINERS |2 --
 board/freescale/ls2080ardb/ddr.c   |   27 +++-
 board/freescale/ls2080ardb/ls2080ardb.c|2 +-
 configs/ls2085aqds_defconfig   |   19 --
 configs/ls2085aqds_nand_defconfig  |   14 --
 configs/ls2085ardb_defconfig   |   19 --
 configs/ls2085ardb_nand_defconfig  |   14 --
 drivers/net/fsl-mc/mc.c|4 +++
 drivers/net/ldpaa_eth/Makefile |1 -
 include/configs/ls2080a_common.h   |7 +
 include/configs/ls2080a_emu.h  |7 -
 include/configs/ls2080a_simu.h |7 -
 include/linux/usb/xhci-fsl.h   |2 +-
 28 files changed, 100 insertions(+), 152 deletions(-)
 delete mode 100644 configs/ls2085aqds_defconfig
 delete mode 100644 configs/ls2085aqds_nand_defconfig
 delete mode 100644 configs/ls2085ardb_defconfig
 delete mode 100644 configs/ls2085ardb_nand_defconfig

-- 
1.7.9.5

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[U-Boot] [PATCH] imx: mx6var_som: Add support for Variscite mx6 boards

[Eran Matityahu]

Add support for Variscite VAR-SOM-MX6 / DART-MX6 / VAR-SOM-SOLO/DUAL boards 
with features:
PMIC, NAND flash, SD/MMC, USB, Ethernet, I2C, LVDS, HDMI.

Signed-off-by: Eran Matityahu 
---
 arch/arm/cpu/armv7/mx6/Kconfig|7 +
 board/variscite/mx6var_som/Kconfig|   12 +
 board/variscite/mx6var_som/MAINTAINERS|8 +
 board/variscite/mx6var_som/Makefile   |9 +
 board/variscite/mx6var_som/addresses.inc  |   38 +
 board/variscite/mx6var_som/imximage.cfg   |   13 +
 board/variscite/mx6var_som/mx6var_eeprom.c|  320 +
 board/variscite/mx6var_som/mx6var_eeprom.h|   88 ++
 board/variscite/mx6var_som/mx6var_eeprom_v2.c |  231 
 board/variscite/mx6var_som/mx6var_eeprom_v2.h |   55 +
 board/variscite/mx6var_som/mx6var_som.c   | 1587 +
 board/variscite/mx6var_som/u-boot-spl.lds |   59 +
 board/variscite/mx6var_som/values.inc |   39 +
 configs/mx6var_som_nand_defconfig |7 +
 configs/mx6var_som_sd_defconfig   |7 +
 include/configs/mx6var_som.h  |  419 +++
 include/configs/mx6var_spl.h  |   81 ++
 tools/logos/variscite.bmp |  Bin 0 -> 15414 bytes
 18 files changed, 2980 insertions(+)
 create mode 100644 board/variscite/mx6var_som/Kconfig
 create mode 100644 board/variscite/mx6var_som/MAINTAINERS
 create mode 100644 board/variscite/mx6var_som/Makefile
 create mode 100644 board/variscite/mx6var_som/addresses.inc
 create mode 100644 board/variscite/mx6var_som/imximage.cfg
 create mode 100644 board/variscite/mx6var_som/mx6var_eeprom.c
 create mode 100644 board/variscite/mx6var_som/mx6var_eeprom.h
 create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v2.c
 create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v2.h
 create mode 100644 board/variscite/mx6var_som/mx6var_som.c
 create mode 100644 board/variscite/mx6var_som/u-boot-spl.lds
 create mode 100644 board/variscite/mx6var_som/values.inc
 create mode 100644 configs/mx6var_som_nand_defconfig
 create mode 100644 configs/mx6var_som_sd_defconfig
 create mode 100644 include/configs/mx6var_som.h
 create mode 100644 include/configs/mx6var_spl.h
 create mode 100644 tools/logos/variscite.bmp

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index c72a150..146c152 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -115,6 +115,12 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
 
+config TARGET_MX6VAR_SOM
+   bool "mx6var_som"
+   select SUPPORT_SPL
+   select DM
+   select DM_THERMAL
+
 config TARGET_NITROGEN6X
bool "nitrogen6x"
 
@@ -180,6 +186,7 @@ source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/udoo/Kconfig"
+source "board/variscite/mx6var_som/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
 
diff --git a/board/variscite/mx6var_som/Kconfig 
b/board/variscite/mx6var_som/Kconfig
new file mode 100644
index 000..0b82df7
--- /dev/null
+++ b/board/variscite/mx6var_som/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6VAR_SOM
+
+config SYS_BOARD
+   default "mx6var_som"
+
+config SYS_VENDOR
+   default "variscite"
+
+config SYS_CONFIG_NAME
+   default "mx6var_som"
+
+endif
diff --git a/board/variscite/mx6var_som/MAINTAINERS 
b/board/variscite/mx6var_som/MAINTAINERS
new file mode 100644
index 000..f3f81dd
--- /dev/null
+++ b/board/variscite/mx6var_som/MAINTAINERS
@@ -0,0 +1,8 @@
+MX6VAR_SOM BOARD
+M: Eran Matityahu 
+S: Maintained
+F: board/variscite/mx6var_som/
+F: include/configs/mx6var_som.h
+F: include/configs/mx6var_spl.h
+F: configs/mx6var_som_nand_defconfig
+F: configs/mx6var_som_sd_defconfig
diff --git a/board/variscite/mx6var_som/Makefile 
b/board/variscite/mx6var_som/Makefile
new file mode 100644
index 000..efa90e2
--- /dev/null
+++ b/board/variscite/mx6var_som/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski 
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := mx6var_som.o mx6var_eeprom.o mx6var_eeprom_v2.o
diff --git a/board/variscite/mx6var_som/addresses.inc 
b/board/variscite/mx6var_som/addresses.inc
new file mode 100644
index 000..3aaea54
--- /dev/null
+++ b/board/variscite/mx6var_som/addresses.inc
@@ -0,0 +1,38 @@
+0x, 0x020C4068, 0x020C406C, 0x020C4070,
+0x020C4074, 0x020C4078, 0x020C407C, 0x020C4080,
+0x020C4084, 0x020E0464, 0x020E0470, 0x020E0474,
+0x020E0478, 0x020E047C, 0x020E0480, 0x020E0484,
+0x020E0488, 0x020E048C, 0x020E0490, 0x020E0494,
+0x020E04A0, 0x020E04AC, 0x020E04B0, 0x020E04B4,
+0x020E04B8, 0x020E04BC, 0x020E04C0, 0x020E04C4,
+0x020E04C8, 0x020E04CC, 0x020E04D0, 0x020E04D4,
+0x020E04D8, 0x020E050C, 0x020E0510, 0x020E0514,

[U-Boot] [PATCH v3] armv8: LS2080A: Consolidate LS2080A and LS2085A

[York Sun]

LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun 
CC: Prabhakar Kushwaha 

---

Changes in v3:
Fix checking AIOP. Tested on LS2080ARDB.

Changes in v2:
Add checking for SVR before starting AIOP
Drop RFC from subject

 arch/arm/cpu/armv8/fsl-layerscape/Makefile |4 ---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|9 ---
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c |6 -
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |2 +-
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   26 ++-
 arch/arm/cpu/armv8/fsl-layerscape/spl.c|4 +--
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |9 ++-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |2 +-
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |2 +-
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |3 +++
 board/freescale/ls2080a/ddr.c  |   27 +++-
 board/freescale/ls2080a/ls2080a.c  |2 +-
 board/freescale/ls2080aqds/MAINTAINERS |2 --
 board/freescale/ls2080aqds/ddr.c   |   27 +++-
 board/freescale/ls2080aqds/ls2080aqds.c|2 +-
 board/freescale/ls2080ardb/MAINTAINERS |2 --
 board/freescale/ls2080ardb/ddr.c   |   27 +++-
 board/freescale/ls2080ardb/ls2080ardb.c|2 +-
 configs/ls2085aqds_defconfig   |   19 --
 configs/ls2085aqds_nand_defconfig  |   14 --
 configs/ls2085ardb_defconfig   |   19 --
 configs/ls2085ardb_nand_defconfig  |   14 --
 drivers/net/fsl-mc/mc.c|4 +++
 drivers/net/ldpaa_eth/Makefile |1 -
 include/configs/ls2080a_common.h   |7 +
 include/configs/ls2080a_emu.h  |7 -
 include/configs/ls2080a_simu.h |7 -
 include/linux/usb/xhci-fsl.h   |2 +-
 28 files changed, 100 insertions(+), 152 deletions(-)
 delete mode 100644 configs/ls2085aqds_defconfig
 delete mode 100644 configs/ls2085aqds_nand_defconfig
 delete mode 100644 configs/ls2085ardb_defconfig
 delete mode 100644 configs/ls2085ardb_nand_defconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index cce7405..5f86ef9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -25,10 +25,6 @@ ifneq ($(CONFIG_LS2080A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
 endif
 
-ifneq ($(CONFIG_LS2085A),)
-obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
-endif
-
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 4b9e209..d939900 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -538,12 +538,12 @@ int print_cpuinfo(void)
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
-   u32 type, rcw;
+   u32 type, rcw, svr = gur_in32(>svr);
 
puts("SoC: ");
 
cpu_name(buf);
-   printf(" %s (0x%x)\n", buf, gur_in32(>svr));
+   printf(" %s (0x%x)\n", buf, svr);
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
get_sys_info();
puts("Clock Configuration:");
@@ -564,7 +564,10 @@ int print_cpuinfo(void)
printf("  FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 #endif
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-   printf(" DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+   if (soc_has_dp_ddr()) {
+   printf(" DP-DDR:   %-4s MT/s",
+  strmhz(buf, sysinfo.freq_ddrbus2));
+   }
 #endif
puts("\n");
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 81cf470..d580a43 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -97,9 +97,13 @@ void get_sys_info(struct sys_info *sys_info)
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-   sys_info->freq_ddrbus2 *= (gur_in32(>rcwsr[0]) >>
+   if (soc_has_dp_ddr()) {
+   sys_info->freq_ddrbus2 *= (gur_in32(>rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &

[U-Boot] [PATCHv2] sf: params: Add support for n25q016a

[Moritz Fischer]

This commits adds support for the N25Q016A, a 16Mbit
serial NOR flash from Micron.

Signed-off-by: Moritz Fischer 
---
Changes from v1:

* RD_FULL
* WR_QPP as suggested by Marek

 drivers/mtd/spi/sf_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..44881b6 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -83,6 +83,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"M25P64", 0x202017, 0x0,   64 * 1024,   128, RD_NORM,  
  0},
{"M25P128",0x202018, 0x0,  256 * 1024,64, RD_NORM,  
  0},
{"M25PX64",0x207117, 0x0,   64 * 1024,   128, RD_NORM,  
SECT_4K},
+   {"N25Q016A",   0x20bb15, 0x1000,64 * 1024,32, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q32", 0x20ba16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q32A",0x20bb16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q64", 0x20ba17, 0x0,   64 * 1024,   128, RD_FULL,  
   WR_QPP | SECT_4K},
-- 
2.5.5

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Re: [U-Boot] [RFC PATCH 1/2] net: phy: ti: Allow the driver to be more configurable

[Dan Murphy]

Tom

On 03/31/2016 10:42 AM, Tom Rini wrote:
> On Thu, Mar 31, 2016 at 10:27:31AM -0500, Dan Murphy wrote:
>> Tom
>>
>> On 03/31/2016 09:11 AM, Tom Rini wrote:
>>> On Thu, Mar 31, 2016 at 07:42:39AM -0500, Dan Murphy wrote:
>>>
 Not all devices use the same internal delay or fifo depth.
 Add the ability to set the internal delay for rx or tx and the
 fifo depth via the config file.  If the value is not set in the
 config file then set the delay to the default.

 Signed-off-by: Dan Murphy 
 ---
  drivers/net/phy/ti.c | 71 
 
  include/dt-bindings/net/ti-dp83867.h | 35 ++
>>> I don't think this is taking things down the right path.  If it's a DT
>>> binding, it comes from the device tree (which is fine and good!) but
>>> that means the binding needs to meet the usual reviews and not just come
>>> in via U-Boot like this.  We really don't want to add a DT binding that
>>> gets values from the config.h file.
>>>
>> This binding file I created that is already part of the Mainline kernel.
>> I just brought it in to use #defines and once the drivers are ported to use
>> DT then the bindings will already be available.
>>
>> And the config.h should be getting its values from the dt-binding.
> OK.  Then lets bring in the whole binding as its own patch.  And
> Mugunthan made cpsw do DM_ETH I see drivers/net/phy/micrel.c talks
> DM_ETH and DT so lets get this PHY driver updated and then get this
> additional bit from the DT.  Thanks!
>
Thanks for the DT pointer I will look at it.  What about platforms that do not 
use DT yet?
Well maybe the more appropriate question is are there any platforms that still 
use the config file?

Dan

-- 
--
Dan Murphy

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Re: [U-Boot] [PATCH 00/10] driver model bring-up of dwc3 usb peripheral

[Marek Vasut]

On 03/31/2016 05:11 PM, Tom Rini wrote:
> On Thu, Mar 31, 2016 at 04:10:49PM +0200, Michal Simek wrote:
>> Hi Tom,
>>
>> On 15.3.2016 13:14, Mugunthan V N wrote:
>>> This patch series enables dwc3 usb driver to adopt driver model.
>>> This has been tested on AM437x evm sk (logs [1]) by loading
>>> kernel through usb ether
>>>
>>> Also pushed a branch for testing [2]
>>>
>>> [1] - http://pastebin.ubuntu.com/15391169/
>>> [2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-dwc3
>>>
>>> Kishon Vijay Abraham I (1):
>>>   configs: am43xx: Add am43xx_evm_usbspl_defconfig
>>>
>>> Mugunthan V N (8):
>>>   drivers: usb: dwc3: remove devm_zalloc from linux_compact
>>>   drivers: usb: dwc3-omap: move usb_gadget_handle_interrupts from board
>>> files to drivers
>>>   am437x: board: do not register usb devices when CONFIG_DM_USB is
>>> defined
>>>   dra7xx: board: do not register usb devices when CONFIG_DM_USB is
>>> defined
>>>   drivers: usb: dwc3: add ti dwc3 misc driver for wrapper
>>>   drivers: usb: common: add support to get maximum speed from dt
>>>   drivers: usb: dwc3: add ti dwc3 peripheral driver with driver model
>>> support
>>>   defconfig: am437x_sk_evm: enable usb driver model
>>>
>>> Tom Rini (1):
>>>   am43xx: Add USB device boot support to SPL
>>>
>>>  board/ti/am43xx/MAINTAINERS |   1 +
>>>  board/ti/am43xx/board.c |  52 +---
>>>  board/ti/am57xx/board.c |  11 --
>>>  board/ti/dra7xx/evm.c   |  13 +-
>>>  configs/am437x_sk_evm_defconfig |   4 +
>>>  configs/am43xx_evm_usbspl_defconfig |   9 ++
>>>  drivers/Makefile|   2 +
>>>  drivers/usb/common/common.c |  29 +
>>>  drivers/usb/dwc3/core.c |  64 +-
>>>  drivers/usb/dwc3/core.h |   6 +
>>>  drivers/usb/dwc3/dwc3-omap.c| 230 
>>> +++-
>>>  drivers/usb/dwc3/gadget.c   |   2 +-
>>>  drivers/usb/dwc3/linux-compat.h |   5 -
>>>  drivers/usb/dwc3/ti_usb_phy.c   |   1 +
>>>  drivers/usb/gadget/gadget_chips.h   |   2 +
>>>  include/configs/am43xx_evm.h|  13 ++
>>>  include/linux/usb/otg.h |   9 ++
>>>  17 files changed, 406 insertions(+), 47 deletions(-)
>>>  create mode 100644 configs/am43xx_evm_usbspl_defconfig
>>>
>>
>> Are you going to take this directly or this should go via USB tree?
> 
> Marek, do you want this?  Or want me to?
> 
That is Lukasz.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] board: ti: DRA7: Add DP83867 TI phy for rev c

[Tom Rini]

On Wed, Mar 30, 2016 at 12:58:37PM -0500, Dan Murphy wrote:

> Enable the TI DP83867 Giga bit phy on the
> dra7 rev c board.  The rx and tx internal
> delays are need for this board so the usage
> of RGMII_ID is required.
> 
> Signed-off-by: Dan Murphy 

Reviewed-by: Tom Rini 

-- 
Tom


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Re: [U-Boot] [PATCH] test/py: Add support for loading image via tftp to specified location

[Stephen Warren]

On 03/31/2016 02:32 AM, Michal Simek wrote:

For example this setting:

env__net_tftp_readable_file = {
 "fn": "ep108/image.ub",
 "addr": "0x1000",


Why not remove the quotes, so the value is an integer already...

Could you please add the "addr" field into the example at the top of 
test_net.py too?



diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py



+addr = int(addr,16)


There should be a space after the comma.

... but removing the quotes as I mentioned above would allow removing 
this int() call altogether.

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[U-Boot] pull request: u-boot-uniphier/master

[Masahiro Yamada]

Hi Tom,


Please pull u-boot-uniphier once again for u-boot-2016.05-rc1.
Mostly driver updates for UniPhier ARMv8 SoC support,
plus misc fixes.


The following changes since commit 080c499df689e8c42df70de44502c0d71533dda8:

  Merge branch 'master' of git://git.denx.de/u-boot-tegra (2016-03-29
13:33:13 -0400)

are available in the git repository at:


  git://git.denx.de/u-boot-uniphier.git master

for you to fetch changes up to 7f5b1e9bd952ebdac917264f03522371a473b60c:

  ARM: uniphier: remove CONFIG_ARP_TIMEOUT define (2016-04-01 00:59:47 +0900)


Graham Moore (1):
  mtd: nand: denali: max_banks calculation changed in revision 5.1

Masahiro Yamada (21):
  ARM: uniphier: make u-boot-with-spl.bin really available
  ARM: uniphier: add sramupdate command
  serial: uniphier: use devm_get_addr() to get base address
  clk: uniphier: use devm_get_addr() to get base address
  i2c: uniphier: use devm_get_addr() to get base address
  gpio: uniphier: use devm_get_addr() to get base address
  mmc: uniphier: use devm_get_addr() to get base address
  pinctrl: uniphier: use devm_get_addr() to get base address
  pinctrl: uniphier: introduce capability flag
  pinctrl: uniphier: support per-pin input enable for new SoCs
  pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver
  pinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driver
  ARM: dts: uniphier: add clock-frequency to serial nodes of LD11/LD20
  ARM: dts: uniphier: add NAND pinmux node
  ARM: uniphier: drop unneeded defines related to legacy serial driver
  ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64
  ARM: uniphier: enable eMMC on PH1-sLD3 reference board
  ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3
  ARM: uniphier: rename function names ph1_* to uniphier_*
  cosmetic: Fix typos "privide"
  ARM: uniphier: remove CONFIG_ARP_TIMEOUT define

 arch/arm/dts/uniphier-ph1-ld11.dtsi   |   4 +
 arch/arm/dts/uniphier-ph1-ld20.dtsi   |   4 +
 arch/arm/dts/uniphier-ph1-sld3-ref.dts|   4 +
 arch/arm/dts/uniphier-pinctrl.dtsi|   5 ++
 arch/arm/mach-uniphier/arm32/debug_ll.S   |  28 +++
 arch/arm/mach-uniphier/bcu/bcu-ld4.c  |   2 +-
 arch/arm/mach-uniphier/bcu/bcu-sld3.c |   2 +-
 arch/arm/mach-uniphier/board_early_init_f.c   |  28 +++
 arch/arm/mach-uniphier/boards.c   |  34 
 arch/arm/mach-uniphier/boot-mode/boot-device.h|  16 ++--
 arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c  |   4 +-
 arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c |   4 +-
 arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c |   4 +-
 arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c |   4 +-
 arch/arm/mach-uniphier/boot-mode/boot-mode.c  |   8 +-
 arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c |   8 +-
 arch/arm/mach-uniphier/clk/clk-ld4.c  |   4 +-
 arch/arm/mach-uniphier/clk/clk-pro4.c |   4 +-
 arch/arm/mach-uniphier/clk/clk-pro5.c |   4 +-
 arch/arm/mach-uniphier/clk/clk-pxs2.c |   4 +-
 arch/arm/mach-uniphier/dram/ddrphy-ld4.c  |   3 +-
 arch/arm/mach-uniphier/dram/ddrphy-regs.h |   3 +-
 arch/arm/mach-uniphier/dram/umc-ld4.c |   4 +-
 arch/arm/mach-uniphier/dram/umc-pro4.c|   4 +-
 arch/arm/mach-uniphier/dram/umc-pxs2.c|   2 +-
 arch/arm/mach-uniphier/dram/umc-sld8.c|   4 +-
 arch/arm/mach-uniphier/dram_init.c|  45 ---
 arch/arm/mach-uniphier/early-clk/early-clk-ld4.c  |   4 +-
 arch/arm/mach-uniphier/early-clk/early-clk-pro5.c |   4 +-
 arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c |   4 +-
 arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c |   2 +-
 arch/arm/mach-uniphier/init.h |  94
+++---
 arch/arm/mach-uniphier/init/init-ld4.c|  14 ++--
 arch/arm/mach-uniphier/init/init-pro4.c   |  12 +--
 arch/arm/mach-uniphier/init/init-pro5.c   |   6 +-
 arch/arm/mach-uniphier/init/init-pxs2.c   |  10 +--
 arch/arm/mach-uniphier/init/init-sld3.c   |  16 ++--
 arch/arm/mach-uniphier/init/init-sld8.c   |  14 ++--
 arch/arm/mach-uniphier/init/init.c|  12 +--
 arch/arm/mach-uniphier/memconf/memconf-pxs2.c |   2 +-
 arch/arm/mach-uniphier/memconf/memconf-sld3.c |   2 +-
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c  |   2 +-
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c |   2 +-

Re: [U-Boot] [PATCH 00/10] ARM: uniphier: driver updates for ARMv8 SoCs support

[Masahiro Yamada]

2016-03-24 22:32 GMT+09:00 Masahiro Yamada :
>
>
>
> Masahiro Yamada (10):
>   serial: uniphier: use devm_get_addr() to get base address
>   clk: uniphier: use devm_get_addr() to get base address
>   i2c: uniphier: use devm_get_addr() to get base address
>   gpio: uniphier: use devm_get_addr() to get base address
>   mmc: uniphier: use devm_get_addr() to get base address
>   pinctrl: uniphier: use devm_get_addr() to get base address
>   pinctrl: uniphier: introduce quirks flags
>   pinctrl: uniphier: support per-pin input enable quirk for new SoCs
>   pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver
>   pinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driver
>


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [RFC v1 PATCH 1/1] mpc85xx: Enable pre-relocation malloc for MPC85xx

[York Sun]

On 03/30/2016 11:29 PM, Mario Six wrote:
> 
> Quoting York Sun :
> 
>> On 03/29/2016 11:53 PM, Mario Six wrote:
>>> To enable DM on MPC85xx, we need pre-relocation malloc, which is
>>> implemented in this patch.
>>>
>>> Signed-off-by: Mario Six 
>>> Cc: York Sun 
>>> Cc: Simon Glass 
>>> ---
>>>  arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 
>>>  arch/powerpc/cpu/mpc85xx/start.S  | 28 
>>>  2 files changed, 28 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c  
>>> b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
>>> index 235a635..e6e1688 100644
>>> --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
>>> +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
>>> @@ -82,7 +82,6 @@ void setup_ifc(void)
>>>  void cpu_init_early_f(void *fdt)
>>>  {
>>> u32 mas0, mas1, mas2, mas3, mas7;
>>> -   int i;
>>>  #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
>>> ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
>>>  #endif
>>> @@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
>>> /* Pointer is writable since we allocated a register for it */
>>> gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
>>>
>>> -   /*
>>> -* Clear initial global data
>>> -*   we don't use memset so we can share this code with NAND_SPL
>>> -*/
>>> -   for (i = 0; i < sizeof(gd_t); i++)
>>> -   ((char *)gd)[i] = 0;
>>> -
>>>  #ifdef CONFIG_QEMU_E500
>>> /*
>>>  * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
>>> diff --git a/arch/powerpc/cpu/mpc85xx/start.S  
>>> b/arch/powerpc/cpu/mpc85xx/start.S
>>> index d867e2a..e6b5203 100644
>>> --- a/arch/powerpc/cpu/mpc85xx/start.S
>>> +++ b/arch/powerpc/cpu/mpc85xx/start.S
>>> @@ -1152,6 +1152,34 @@ _start_cont:
>>> /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
>>> lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
>>> ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
>>> +
>>> +#ifdef CONFIG_SYS_MALLOC_F_LEN
>>> +   /* Leave 16+ byte for back chain termination and NULL return address */
>>> +   subir3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
>>> +
>>> +   /* End of RAM */
>>> +   lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
>>> +   ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
>>> +
>>> +   li  r0,0
>>> +
>>> +1: subir4,r4,4
>>> +   stw r0,0(r4)
>>> +   cmplw   r4,r3
>>> +   bne 1b
>>> +
>>> +   lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
>>> +   ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
>>> +
>>> +   addir3,r3,16/* Pre-relocation malloc area */
>>> +   stw r3,GD_MALLOC_BASE(r4)
>>> +   subir3,r3,16
>>> +
>>> +   /* Fix issue with exception handler alignment */
>>> +   nop
>>> +   nop
>>> +   nop
>>
>> Why do you need this? Does the code get too long and enters  
>> exception handler space?
>>
> 
> Those are the reason I sent the patch as RFC: There seems to be some kind of
> alignment issue with the exception vectors. If the nops are not there, the
> board crashes as soon as the timer_interrupt is raised for the first  
> time.  The
> commit 96d2bb952bbf2e5a14f6ad668312cbce3cc4485a (powerpc/mpc85xx: Don't
> relocate exception vectors), among other things, removed the explicit  
> alignment
> of the vectors for E500. If you add those back in (and remove the nops), the
> code works too. So maybe some kind of alignment for the vectors is  
> needed after
> all?

There is requirement for alignment. For e500 core, the interrupt vector offset
registers (IVORs) have lowest 4 bit cleared. So the vectors must be aligned to
16 bytes. For legacy cores, the exception vectors are fixed. You have to make
sure the vectors are exactly where they should be.

I think you can use .align 4. Try it.

> 
>>> +#endif
>>> li  r0,0
>>> stw r0,0(r3)/* Terminate Back Chain */
>>> stw r0,+4(r3)   /* NULL return address. */
>>> --
>>
>> This patch presumes stack is right under GD, which is OK. But
>> CONFIG_SYS_MALLOC_F_LEN has not been used by powerpc. Presumption of
>> (CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE) <  
>> CONFIG_SYS_INIT_RAM_SIZE
>> may not be true. Would it be better to check at compiling time to  
>> make sure we
>> have enough init ram for the malloc len?
>>
> 
> Yes, good idea; I'll add an appropriate check in v2 of the patch. Maybe
> something like
> 
> #if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE + 0x80 >  
> CONFIG_SYS_INIT_RAM_SIZE
> #error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
> #endif
> 
> to ensure we leave at least a minimum of ~128 byte stack space, too?
> 

I don't think so. We know the size of GD, and we know the size of MALLOC_LEN.
But we don't know the depth of stack until we compile it. I would put GD on top,
followed by MALLOC, and leave the rest to stack. I know the DDR driver we use
needs way 

Re: [U-Boot] [PATCH] ARM: uniphier: rename function names ph1_* to uniphier_*

[Masahiro Yamada]

2016-03-30 20:17 GMT+09:00 Masahiro Yamada :
> Eliminate the "ph1"_ prefixes from function names because "uniphier_"
> describes the SoC familiy better.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [linux-sunxi] [PATCH RFC 00/17] sunxi: more AXP818 and A83T USB support

[Chen-Yu Tsai]

On Thu, Mar 31, 2016 at 10:59 PM, Hans de Goede  wrote:
> Hi,
>
> On 29-03-16 18:26, Chen-Yu Tsai wrote:
>>
>> Hi everyone,
>>
>> This series adds more support for axp818 regulators, and USB support
>> for A83T. Normal EHCI/OHCI USB works, and so does OTG host mode.
>
>
> Cool, thanks for working on this!
>
>> I couldn't get my Cubietruck Plus to work in gadget mode though.
>> No USB device appears on the host end when it enters fastboot.
>
>
> Did you change CONFIG_USB_MUSB_HOST=y to CONFIG_USB_MUSB_GADGET=y ?
> currently we support building either one or the other.

I did, but I didn't want to send a non-working defconfig. I'm
certain musb was compiled in gadget mode, just that nothing was
happening.

> I would certainly welcome patches to make things more dynamic,
> you could replace the
>
> #ifdef CONFIG_USB_MUSB_HOST
> #else
> #endif
>
> construct in drivers/usb/musb-new/sunxi.c: sunxi_musb_board_init()
> with an id=pin check (but only when both CONFIG_USB_MUSB_HOST and
> CONFIG_USB_MUSB_GADGET are defined, on some boards the port is
> hardwired for a certain use).
>
> If you take a shot at this, do not forget to also update musb_plat
> dynamically, currently that is statically initialized depending
> on CONFIG_USB_MUSB_HOST being defined.
>
> You probably also want to check other places for
> #ifdef CONFIG_USB_MUSB_HOST / #ifdef CONFIG_USB_MUSB_GADGET,
> but I'm reasonably sure that defining both at the same time
> should _mostly_ work, just as long as you only register either
> the host or gadget part from sunxi_musb_board_init() (which
> means that the right cable needs to be plugged in before
> u-boot starts).

I'm probably not going to spend much more time on this, at least
not soon. The host ports working should be enough for normal use.

> ###
>
> I've applied patches 1-12 to my tree, and I plan to include
> these in my next pull-req I've not added 13-14 to give
> you some time to figure out what todo with the otg, I guess
> that on the h8_homlet_v2 you can just leave it as
> CONFIG_USB_MUSB_HOST=y since it is wired to an USB A female
> connector.

That is what I intended.

> On the cubietruck you may want to make it CONFIG_USB_MUSB_GADGET=y
> since the most likely use there is using it in gadget mode (for host
> mode it has normal ports).

Right. Except I couldn't get it to work.

> About patches 15-17 you've tagged these as "[DO NOT MERGE]" I understand
> that the devicetree bits which will eventually go upstream will look
> differently, but as long as the compatible and the base-address will
> not change, we can pretty merge them in u-boot already, u-boot's dts
> copy is only used internally and not passed to the kernel.
>
> I will not merge them if you do not want me too, but we could have
> these minimal nodes for now to get things to work. These can then
> eventually be replaced with the real kernel dts when that is upstream.

If you aren't concerned with them looking different than the kernel
ones, I have no problem with merging them. Just wanted to be sure
before you do so. :)


Regards
ChenYu

P.S. I'll be at ELC next week.

>> Patch 1 removes axp818_init() from the header file, as it is undefined
>> and unused.
>>
>> Patch 2 fixes axp818's DCDC5 default voltage. DCDC5 normally supplies
>> DRAM. This changes the default to match DDR3 DRAM.
>>
>> Patch 3 adds support for axp818's FLDOs, one of which powers the HSIC
>> PHY.
>>
>> Patch 4 raises the DCDC1 voltage on h8_homlet_v2 to 3.3V, the default
>> value.
>>
>> Patch 5 enables and sets DLDO4 to 3.3V on h8_homlet_v2. This powers
>> the AC200 chip, which among other things, is the ethernet PHY.
>>
>> Patch 6 adds support for the USB PHYs on A83T.
>>
>> Patch 7 fixes some clock macros related to USB PHYs for A83T.
>>
>> Patch 8 & 9 add A83T compatible strings to sunxi EHCI & OHCI.
>>
>> Patch 10 adds support for A83T to musb sunxi glue.
>>
>> Patch 11 generalizes the VBUS function related macros for AXP PMICs.
>>
>> Patch 12 adds support for VBUS drive on AXP818.
>>
>> Patch 13 enables USB Kconfig options in h8_homlet_v2_defconfig.
>>
>> Patch 14 enables USB Kconfig options in Cubietruck_plus_defconfig.
>>
>> Patch 15 ~ 17 is the minimal changes needed to enable USB on the
>> A83T boards I have. They are not the same as the kernel changes
>> I will submit, and should not be merged without discussion.
>>
>> Regards
>> ChenYu
>>
>>
>> Chen-Yu Tsai (17):
>>power: axp818: Remove undefined axp818_init()
>>power: axp818: Fix DCDC5 default voltage
>>power: axp818: Add support for FLDOs
>>sunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V)
>>sunxi: h8_homlet_v2: Set DLDO4 to 3.3V
>>sunxi: usb_phy: Add support for A83T USB PHYs
>>sunxi: clk: Fix USB PHY clock macros for A83T
>>sunxi: ehci: Add A83T compatible
>>sunxi: ohci: Add A83T compatible
>>musb: sunxi: Add support for A83T
>>sunxi: axp: Generalize register macros for VBUS drive GPIO
>>sunxi: axp: Support VBUS drive 

Re: [U-Boot] [PATCH] ARM: uniphier: drop unneeded defines related to legacy serial driver

[Masahiro Yamada]

2016-03-29 20:12 GMT+09:00 Masahiro Yamada :
> These defined were used for pre-DM ns16550 serial driver.  They are
> unneeded because UniPhier SoCs now use DM serial.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.



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Re: [U-Boot] [PATCH] ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64

[Masahiro Yamada]

2016-03-29 20:18 GMT+09:00 Masahiro Yamada :
> Currently, these functions assume #address-cells and #size-cells are
> both one.  Fix them to support 64bit DTB.
>
> Also, I am fixing a buffer overrun bug while I am here.  The array
> size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS.  The number of
> iteration in the loop should be limited by that CONFIG.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.

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Re: [U-Boot] [PATCH] ARM: uniphier: enable eMMC on PH1-sLD3 reference board

[Masahiro Yamada]

2016-03-30 10:52 GMT+09:00 Masahiro Yamada :
> On PH1-sLD3, eMMC and NAND are assigned to different I/O pins.
> Both devices can be enabled at the same time.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [PATCH] ARM: dts: uniphier: add clock-frequency for LD11/LD20 DTSI

[Masahiro Yamada]

2016-03-28 21:39 GMT+09:00 Masahiro Yamada :
> Since no clock driver is implemented for peripherals in U-Boot yet,
> this property is needed for the serial driver to set up the divisor
> register.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [PATCH] ARM: uniphier: remove CONFIG_ARP_TIMEOUT define

[Masahiro Yamada]

2016-03-30 20:45 GMT+09:00 Masahiro Yamada :
> I no longer see the problem claimed in the comment block.  Rather,
> the 0.5 msec timeout seems too short for some TFTP servers.
>
> Drop the CONFIG_ARM_TIMEOUT to fall back to the 5 sec timeout.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [PATCH] cosmetic: Fix typos "privide"

[Masahiro Yamada]

2016-03-30 20:17 GMT+09:00 Masahiro Yamada :
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [PATCH] ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3

[Masahiro Yamada]

2016-03-30 10:53 GMT+09:00 Masahiro Yamada :
> Signed-off-by: Masahiro Yamada 
>

Applied to u-boot-uniphier/master.


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Re: [U-Boot] [PATCH] ARM: dts: uniphier: add NAND pinmux node

[Masahiro Yamada]

2016-03-28 21:41 GMT+09:00 Masahiro Yamada :
> This will be used to set up pin-muxing for the NAND controller.
>
> Signed-off-by: Masahiro Yamada 

Applied to u-boot-uniphier/master.

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Re: [U-Boot] [PATCH] ARM: uniphier: add sramupdate command

[Masahiro Yamada]

2016-03-24 22:23 GMT+09:00 Masahiro Yamada :
> This command would be useful to update U-Boot images in SRAM.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [RFC PATCH 1/2] net: phy: ti: Allow the driver to be more configurable

[Tom Rini]

On Thu, Mar 31, 2016 at 10:27:31AM -0500, Dan Murphy wrote:
> Tom
> 
> On 03/31/2016 09:11 AM, Tom Rini wrote:
> > On Thu, Mar 31, 2016 at 07:42:39AM -0500, Dan Murphy wrote:
> >
> >> Not all devices use the same internal delay or fifo depth.
> >> Add the ability to set the internal delay for rx or tx and the
> >> fifo depth via the config file.  If the value is not set in the
> >> config file then set the delay to the default.
> >>
> >> Signed-off-by: Dan Murphy 
> >> ---
> >>  drivers/net/phy/ti.c | 71 
> >> 
> >>  include/dt-bindings/net/ti-dp83867.h | 35 ++
> > I don't think this is taking things down the right path.  If it's a DT
> > binding, it comes from the device tree (which is fine and good!) but
> > that means the binding needs to meet the usual reviews and not just come
> > in via U-Boot like this.  We really don't want to add a DT binding that
> > gets values from the config.h file.
> >
> 
> This binding file I created that is already part of the Mainline kernel.
> I just brought it in to use #defines and once the drivers are ported to use
> DT then the bindings will already be available.
> 
> And the config.h should be getting its values from the dt-binding.

OK.  Then lets bring in the whole binding as its own patch.  And
Mugunthan made cpsw do DM_ETH I see drivers/net/phy/micrel.c talks
DM_ETH and DT so lets get this PHY driver updated and then get this
additional bit from the DT.  Thanks!

-- 
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Re: [U-Boot] [RFC PATCH 1/2] net: phy: ti: Allow the driver to be more configurable

[Dan Murphy]

Tom

On 03/31/2016 09:11 AM, Tom Rini wrote:
> On Thu, Mar 31, 2016 at 07:42:39AM -0500, Dan Murphy wrote:
>
>> Not all devices use the same internal delay or fifo depth.
>> Add the ability to set the internal delay for rx or tx and the
>> fifo depth via the config file.  If the value is not set in the
>> config file then set the delay to the default.
>>
>> Signed-off-by: Dan Murphy 
>> ---
>>  drivers/net/phy/ti.c | 71 
>> 
>>  include/dt-bindings/net/ti-dp83867.h | 35 ++
> I don't think this is taking things down the right path.  If it's a DT
> binding, it comes from the device tree (which is fine and good!) but
> that means the binding needs to meet the usual reviews and not just come
> in via U-Boot like this.  We really don't want to add a DT binding that
> gets values from the config.h file.
>

This binding file I created that is already part of the Mainline kernel.
I just brought it in to use #defines and once the drivers are ported to use
DT then the bindings will already be available.

And the config.h should be getting its values from the dt-binding.

Dan

-- 
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Dan Murphy

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Re: [U-Boot] [PATCH] ARM: uniphier: make u-boot-with-spl.bin really available

[Masahiro Yamada]

2016-03-24 22:22 GMT+09:00 Masahiro Yamada :
> Commit d085ecd61b99 ("ARM: uniphier: switch to raw U-Boot image")
> claimed that u-boot-with-spl.bin would be useful in its commit log,
> but it was not available because the commit missed to define
> CONFIG_SPL_MAX_SIZE.  Without it, CONFIG_SPL_PAD_TO is not defined
> either (see include/config_fallbacks.h).  So, the SPL image is not
> padded correctly.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.



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Re: [U-Boot] [PATCH] mtd: nand: denali: max_banks calculation changed in revision 5.1

[Masahiro Yamada]

2016-03-24 22:14 GMT+09:00 Masahiro Yamada :
> From: Graham Moore 
>
> Read Denali hardware revision number and use it to
> calculate max_banks,  The encoding of max_banks changed
> in Denali revision 5.1.
>
> [ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ]
>
> Signed-off-by: Graham Moore 
> [Brian: parentheses around macro arg]
> Signed-off-by: Brian Norris 
> [Masahiro: import from Linux and adjust ioread32() to readl() ]
> Signed-off-by: Masahiro Yamada 
>
> ---


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [PATCH 00/10] driver model bring-up of dwc3 usb peripheral

[Tom Rini]

On Thu, Mar 31, 2016 at 04:10:49PM +0200, Michal Simek wrote:
> Hi Tom,
> 
> On 15.3.2016 13:14, Mugunthan V N wrote:
> > This patch series enables dwc3 usb driver to adopt driver model.
> > This has been tested on AM437x evm sk (logs [1]) by loading
> > kernel through usb ether
> > 
> > Also pushed a branch for testing [2]
> > 
> > [1] - http://pastebin.ubuntu.com/15391169/
> > [2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-dwc3
> > 
> > Kishon Vijay Abraham I (1):
> >   configs: am43xx: Add am43xx_evm_usbspl_defconfig
> > 
> > Mugunthan V N (8):
> >   drivers: usb: dwc3: remove devm_zalloc from linux_compact
> >   drivers: usb: dwc3-omap: move usb_gadget_handle_interrupts from board
> > files to drivers
> >   am437x: board: do not register usb devices when CONFIG_DM_USB is
> > defined
> >   dra7xx: board: do not register usb devices when CONFIG_DM_USB is
> > defined
> >   drivers: usb: dwc3: add ti dwc3 misc driver for wrapper
> >   drivers: usb: common: add support to get maximum speed from dt
> >   drivers: usb: dwc3: add ti dwc3 peripheral driver with driver model
> > support
> >   defconfig: am437x_sk_evm: enable usb driver model
> > 
> > Tom Rini (1):
> >   am43xx: Add USB device boot support to SPL
> > 
> >  board/ti/am43xx/MAINTAINERS |   1 +
> >  board/ti/am43xx/board.c |  52 +---
> >  board/ti/am57xx/board.c |  11 --
> >  board/ti/dra7xx/evm.c   |  13 +-
> >  configs/am437x_sk_evm_defconfig |   4 +
> >  configs/am43xx_evm_usbspl_defconfig |   9 ++
> >  drivers/Makefile|   2 +
> >  drivers/usb/common/common.c |  29 +
> >  drivers/usb/dwc3/core.c |  64 +-
> >  drivers/usb/dwc3/core.h |   6 +
> >  drivers/usb/dwc3/dwc3-omap.c| 230 
> > +++-
> >  drivers/usb/dwc3/gadget.c   |   2 +-
> >  drivers/usb/dwc3/linux-compat.h |   5 -
> >  drivers/usb/dwc3/ti_usb_phy.c   |   1 +
> >  drivers/usb/gadget/gadget_chips.h   |   2 +
> >  include/configs/am43xx_evm.h|  13 ++
> >  include/linux/usb/otg.h |   9 ++
> >  17 files changed, 406 insertions(+), 47 deletions(-)
> >  create mode 100644 configs/am43xx_evm_usbspl_defconfig
> > 
> 
> Are you going to take this directly or this should go via USB tree?

Marek, do you want this?  Or want me to?

-- 
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Re: [U-Boot] [linux-sunxi] [PATCH RFC 06/17] sunxi: usb_phy: Add support for A83T USB PHYs

[Hans de Goede]

Hi,

On 29-03-16 18:26, Chen-Yu Tsai wrote:

The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host,
1 for USB HSIC.

Signed-off-by: Chen-Yu Tsai 


Note, I've made some minor changes to this one to reduce the amount of
#ifdef-s it introduces.

Regards,

Hans




---
  arch/arm/cpu/armv7/sunxi/usb_phy.c | 48 ++
  include/configs/sun8i.h|  2 ++
  2 files changed, 50 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c 
b/arch/arm/cpu/armv7/sunxi/usb_phy.c
index 0749fbd..4ac532a 100644
--- a/arch/arm/cpu/armv7/sunxi/usb_phy.c
+++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c
@@ -34,6 +34,16 @@
  #define REG_PHY_UNK_H30x420
  #define REG_PMU_UNK_H30x810

+/* A83T specific control bits for PHY0 */
+#define SUNXI_PHY_CTL_VBUSVLDEXT   BIT(5)
+#define SUNXI_PHY_CTL_SIDDQBIT(3)
+
+/* A83T HSIC specific bits */
+#define SUNXI_EHCI_HS_FORCEBIT(20)
+#define SUNXI_EHCI_CONNECT_DET BIT(17)
+#define SUNXI_EHCI_CONNECT_INT BIT(16)
+#define SUNXI_EHCI_HSICBIT(1)
+
  static struct sunxi_usb_phy {
int usb_rst_mask;
int gpio_vbus;
@@ -55,6 +65,14 @@ static struct sunxi_usb_phy {
.base = SUNXI_USB1_BASE,
},
  #if CONFIG_SUNXI_USB_PHYS >= 3
+#ifdef CONFIG_MACH_SUN8I_A83T
+   {
+   .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
+   CCM_USB_CTRL_12M_CLK,
+   .id = 2,
+   .base = SUNXI_USB2_BASE,
+   }
+#else
{
.usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
.id = 2,
@@ -68,6 +86,7 @@ static struct sunxi_usb_phy {
.base = SUNXI_USB3_BASE,
}
  #endif
+#endif
  };

  static int get_vbus_gpio(int index)
@@ -97,6 +116,7 @@ static int get_id_detect_gpio(int index)
return -EINVAL;
  }

+#ifndef CONFIG_MACH_SUN8I_A83T
  static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
  int data, int len)
  {
@@ -161,6 +181,7 @@ static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
return;
  }
  #endif
+#endif

  static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
  {
@@ -174,6 +195,13 @@ static void sunxi_usb_phy_passby(struct sunxi_usb_phy 
*phy, int enable)
SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
SUNXI_EHCI_ULPI_BYPASS_EN;

+#ifdef CONFIG_MACH_SUN8I_A83T
+   if (phy->id == 2)
+   bits |= SUNXI_EHCI_HS_FORCE |
+   SUNXI_EHCI_CONNECT_INT |
+   SUNXI_EHCI_HSIC;
+#endif
+
if (enable)
setbits_le32(addr, bits);
else
@@ -184,9 +212,11 @@ static void sunxi_usb_phy_passby(struct sunxi_usb_phy 
*phy, int enable)

  void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
  {
+#ifndef CONFIG_MACH_SUN8I_A83T
struct sunxi_usb_phy *phy = _usb_phy[index];

usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
+#endif
  }

  void sunxi_usb_phy_init(int index)
@@ -200,10 +230,21 @@ void sunxi_usb_phy_init(int index)

setbits_le32(>usb_clk_cfg, phy->usb_rst_mask);

+#ifndef CONFIG_MACH_SUN8I_A83T
sunxi_usb_phy_config(phy);
+#endif

if (phy->id != 0)
sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
+
+#ifdef CONFIG_MACH_SUN8I_A83T
+   if (phy->id == 0) {
+   setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
+SUNXI_PHY_CTL_VBUSVLDEXT);
+   clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
+SUNXI_PHY_CTL_SIDDQ);
+   }
+#endif
  }

  void sunxi_usb_phy_exit(int index)
@@ -218,6 +259,13 @@ void sunxi_usb_phy_exit(int index)
if (phy->id != 0)
sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);

+#ifdef CONFIG_MACH_SUN8I_A83T
+   if (phy->id == 0) {
+   setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
+SUNXI_PHY_CTL_SIDDQ);
+   }
+#endif
+
clrbits_le32(>usb_clk_cfg, phy->usb_rst_mask);
  }

diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index 7c0ab1e..eb5db4e 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -20,6 +20,8 @@

  #ifdef CONFIG_MACH_SUN8I_H3
#define CONFIG_SUNXI_USB_PHYS   4
+#elif defined CONFIG_MACH_SUN8I_A83T
+   #define CONFIG_SUNXI_USB_PHYS   3
  #else
#define CONFIG_SUNXI_USB_PHYS   2
  #endif


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Re: [U-Boot] [linux-sunxi] [PATCH RFC 00/17] sunxi: more AXP818 and A83T USB support

[Hans de Goede]

Hi,

On 29-03-16 18:26, Chen-Yu Tsai wrote:

Hi everyone,

This series adds more support for axp818 regulators, and USB support
for A83T. Normal EHCI/OHCI USB works, and so does OTG host mode.


Cool, thanks for working on this!


I couldn't get my Cubietruck Plus to work in gadget mode though.
No USB device appears on the host end when it enters fastboot.


Did you change CONFIG_USB_MUSB_HOST=y to CONFIG_USB_MUSB_GADGET=y ?
currently we support building either one or the other.

I would certainly welcome patches to make things more dynamic,
you could replace the

#ifdef CONFIG_USB_MUSB_HOST
#else
#endif

construct in drivers/usb/musb-new/sunxi.c: sunxi_musb_board_init()
with an id=pin check (but only when both CONFIG_USB_MUSB_HOST and
CONFIG_USB_MUSB_GADGET are defined, on some boards the port is
hardwired for a certain use).

If you take a shot at this, do not forget to also update musb_plat
dynamically, currently that is statically initialized depending
on CONFIG_USB_MUSB_HOST being defined.

You probably also want to check other places for
#ifdef CONFIG_USB_MUSB_HOST / #ifdef CONFIG_USB_MUSB_GADGET,
but I'm reasonably sure that defining both at the same time
should _mostly_ work, just as long as you only register either
the host or gadget part from sunxi_musb_board_init() (which
means that the right cable needs to be plugged in before
u-boot starts).

###

I've applied patches 1-12 to my tree, and I plan to include
these in my next pull-req I've not added 13-14 to give
you some time to figure out what todo with the otg, I guess
that on the h8_homlet_v2 you can just leave it as
CONFIG_USB_MUSB_HOST=y since it is wired to an USB A female
connector.

On the cubietruck you may want to make it CONFIG_USB_MUSB_GADGET=y
since the most likely use there is using it in gadget mode (for host
mode it has normal ports).

About patches 15-17 you've tagged these as "[DO NOT MERGE]" I understand
that the devicetree bits which will eventually go upstream will look
differently, but as long as the compatible and the base-address will
not change, we can pretty merge them in u-boot already, u-boot's dts
copy is only used internally and not passed to the kernel.

I will not merge them if you do not want me too, but we could have
these minimal nodes for now to get things to work. These can then
eventually be replaced with the real kernel dts when that is upstream.

Regards,

Hans




Patch 1 removes axp818_init() from the header file, as it is undefined
and unused.

Patch 2 fixes axp818's DCDC5 default voltage. DCDC5 normally supplies
DRAM. This changes the default to match DDR3 DRAM.

Patch 3 adds support for axp818's FLDOs, one of which powers the HSIC
PHY.

Patch 4 raises the DCDC1 voltage on h8_homlet_v2 to 3.3V, the default
value.

Patch 5 enables and sets DLDO4 to 3.3V on h8_homlet_v2. This powers
the AC200 chip, which among other things, is the ethernet PHY.

Patch 6 adds support for the USB PHYs on A83T.

Patch 7 fixes some clock macros related to USB PHYs for A83T.

Patch 8 & 9 add A83T compatible strings to sunxi EHCI & OHCI.

Patch 10 adds support for A83T to musb sunxi glue.

Patch 11 generalizes the VBUS function related macros for AXP PMICs.

Patch 12 adds support for VBUS drive on AXP818.

Patch 13 enables USB Kconfig options in h8_homlet_v2_defconfig.

Patch 14 enables USB Kconfig options in Cubietruck_plus_defconfig.

Patch 15 ~ 17 is the minimal changes needed to enable USB on the
A83T boards I have. They are not the same as the kernel changes
I will submit, and should not be merged without discussion.

Regards
ChenYu


Chen-Yu Tsai (17):
   power: axp818: Remove undefined axp818_init()
   power: axp818: Fix DCDC5 default voltage
   power: axp818: Add support for FLDOs
   sunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V)
   sunxi: h8_homlet_v2: Set DLDO4 to 3.3V
   sunxi: usb_phy: Add support for A83T USB PHYs
   sunxi: clk: Fix USB PHY clock macros for A83T
   sunxi: ehci: Add A83T compatible
   sunxi: ohci: Add A83T compatible
   musb: sunxi: Add support for A83T
   sunxi: axp: Generalize register macros for VBUS drive GPIO
   sunxi: axp: Support VBUS drive GPIO on AXP818
   sunxi: h8_homlet_v2: Enable USB Kconfig options in defconfig
   sunxi: Cubietruck Plus: Enable USB Kconfig options in defconfig
   [DO NOT MERGE] sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi
   [DO NOT MERGE] sunxi: Enable USB on Cubietruck Plus
   [DO NOT MERGE] sunxi: Enable USB nodes for H8Homlet v2

  arch/arm/cpu/armv7/sunxi/usb_phy.c | 48 ++
  arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  | 12 ++
  arch/arm/dts/sun8i-a83t-cubietruck-plus.dts| 12 ++
  arch/arm/dts/sun8i-a83t.dtsi   | 34 +++
  arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h |  6 +--
  board/sunxi/board.c|  6 +++
  configs/Cubietruck_plus_defconfig  | 10 -
  configs/h8_homlet_v2_defconfig | 

Re: [U-Boot] [PATCH V4 2/3] mx7: psci: add basic psci support

[Gary Bisson]

Hi Peng,

On Thu, Mar 31, 2016 at 3:33 PM, Peng Fan  wrote:
> Hi Gary,
>
> On Thu, Mar 31, 2016 at 01:17:07PM +0200, Gary Bisson wrote:
>>Hi all,
>>
>>Sorry to revive an old thread but I have some questions about thit patch.
>>
>>On Fri, Oct 23, 2015 at 10:13:04AM +0800, Peng Fan wrote:
>>> 1. add basic psci support for imx7 chip.
>>> 2. support cpu_on and cpu_off.
>>> 3. switch to non-secure mode when boot linux kernel.
>>> 4. set csu allow accessing all peripherial register in non-secure mode.
>>>
>>> Signed-off-by: Frank Li 
>>> Signed-off-by: Peng Fan 
>>> Cc: Stefano Babic 
>>> Cc: Fabio Estevam 
>>> ---
>>> [snip]
>>> diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h 
>>> b/arch/arm/include/asm/arch-mx7/imx-regs.h
>>> index 4dc11ee..9213374 100644
>>> --- a/arch/arm/include/asm/arch-mx7/imx-regs.h
>>> +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
>>> @@ -866,6 +866,9 @@ struct cspi_regs {
>>>  ECSPI3_BASE_ADDR, \
>>>  ECSPI4_BASE_ADDR
>>>
>>> +#define CSU_INIT_SEC_LEVEL0 0x00FF00FF
>>> +#define CSU_NUM_REGS64
>>
>>In the security documentation (revA) it is said that there are 40 CSL,
>>why is it 64 here?
>>
>>Also, although this seems to work, later on when the kernel boots I get
>>the following CAAM errors:
>>caam 3090.caam: failed to acquire DECO 0
>>...
>>caam 3090.caam: failed to acquire DECO 0
>>caam 3090.caam: failed to instantiate RNG
>>caam: probe of 3090.caam failed with error -11
>
> This patch will let SoC switch to non sec mode. I have little knowledge
> of CAAM, I guess it works in sec mode. So when kernel boots up, it will
> complains a lot...

Seems like a safe assumption to say CAAM requires to be run in secure mode.

>>If I revert this patch and therefore leave the CSU to its default state
>>at bootup the above CAAM issue disappears, do you have any idea why?
>
>
> Revert this patch, then all code runs in sec mode.
>
>>
>>As a FYI, I am using U-Boot v2016.03 + a few patches that adds support
>>for our i.MX7 Nitrogen7 board. You can find the repo here:
>>https://github.com/boundarydevices/u-boot-imx6/tree/boundary-v2016.03
>>
>>Also, if I base U-Boot on top of NXP repo it works too since this csu/psci
>>support isn't there:
>>http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/?id=rel_imx_3.14.52_1.1.0_ga
>
> Yeah. NXP code not switch to non sec mode.
>
> You can revert this patch in your vendor tree. I am not sure whether you
> have tested linux upstream tree, or you use caam code from NXP vendor
> tree. If you use NXP vendor tree, and use uboot upstream code, sure
> caam will complain errros. We would like to use PSCI and work in
> non-sec mode, but still some works need to be done.

Thanks for your feedback. We are using our own tree based on NXP
vendor one (3.14.52_1.1.0_ga).

We usually use upstream U-Boot with this kernel tree. I guess the
easiest option here is actually to add CONFIG_MX7_SEC to our board
config, this avoids to revert the patches.

Thanks,
Gary
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Re: [U-Boot] [PATCH 00/10] driver model bring-up of dwc3 usb peripheral

[Michal Simek]

Hi Tom,

On 15.3.2016 13:14, Mugunthan V N wrote:
> This patch series enables dwc3 usb driver to adopt driver model.
> This has been tested on AM437x evm sk (logs [1]) by loading
> kernel through usb ether
> 
> Also pushed a branch for testing [2]
> 
> [1] - http://pastebin.ubuntu.com/15391169/
> [2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-dwc3
> 
> Kishon Vijay Abraham I (1):
>   configs: am43xx: Add am43xx_evm_usbspl_defconfig
> 
> Mugunthan V N (8):
>   drivers: usb: dwc3: remove devm_zalloc from linux_compact
>   drivers: usb: dwc3-omap: move usb_gadget_handle_interrupts from board
> files to drivers
>   am437x: board: do not register usb devices when CONFIG_DM_USB is
> defined
>   dra7xx: board: do not register usb devices when CONFIG_DM_USB is
> defined
>   drivers: usb: dwc3: add ti dwc3 misc driver for wrapper
>   drivers: usb: common: add support to get maximum speed from dt
>   drivers: usb: dwc3: add ti dwc3 peripheral driver with driver model
> support
>   defconfig: am437x_sk_evm: enable usb driver model
> 
> Tom Rini (1):
>   am43xx: Add USB device boot support to SPL
> 
>  board/ti/am43xx/MAINTAINERS |   1 +
>  board/ti/am43xx/board.c |  52 +---
>  board/ti/am57xx/board.c |  11 --
>  board/ti/dra7xx/evm.c   |  13 +-
>  configs/am437x_sk_evm_defconfig |   4 +
>  configs/am43xx_evm_usbspl_defconfig |   9 ++
>  drivers/Makefile|   2 +
>  drivers/usb/common/common.c |  29 +
>  drivers/usb/dwc3/core.c |  64 +-
>  drivers/usb/dwc3/core.h |   6 +
>  drivers/usb/dwc3/dwc3-omap.c| 230 
> +++-
>  drivers/usb/dwc3/gadget.c   |   2 +-
>  drivers/usb/dwc3/linux-compat.h |   5 -
>  drivers/usb/dwc3/ti_usb_phy.c   |   1 +
>  drivers/usb/gadget/gadget_chips.h   |   2 +
>  include/configs/am43xx_evm.h|  13 ++
>  include/linux/usb/otg.h |   9 ++
>  17 files changed, 406 insertions(+), 47 deletions(-)
>  create mode 100644 configs/am43xx_evm_usbspl_defconfig
> 

Are you going to take this directly or this should go via USB tree?

Thanks,
Michal


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Maintainer of Linux kernel - Xilinx Zynq ARM architecture
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Re: [U-Boot] [RFC PATCH 1/2] net: phy: ti: Allow the driver to be more configurable

[Tom Rini]

On Thu, Mar 31, 2016 at 07:42:39AM -0500, Dan Murphy wrote:

> Not all devices use the same internal delay or fifo depth.
> Add the ability to set the internal delay for rx or tx and the
> fifo depth via the config file.  If the value is not set in the
> config file then set the delay to the default.
> 
> Signed-off-by: Dan Murphy 
> ---
>  drivers/net/phy/ti.c | 71 
> 
>  include/dt-bindings/net/ti-dp83867.h | 35 ++

I don't think this is taking things down the right path.  If it's a DT
binding, it comes from the device tree (which is fine and good!) but
that means the binding needs to meet the usual reviews and not just come
in via U-Boot like this.  We really don't want to add a DT binding that
gets values from the config.h file.

-- 
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Re: [U-Boot] [RFC PATCH 1/2] net: phy: ti: Allow the driver to be more configurable

[Dan Murphy]

On 03/31/2016 07:42 AM, Dan Murphy wrote:
> Not all devices use the same internal delay or fifo depth.
> Add the ability to set the internal delay for rx or tx and the
> fifo depth via the config file.  If the value is not set in the
> config file then set the delay to the default.

This patch also aligns the uboot driver with the kernel driver.
And when DTS data is added the data_init api can be used
to populate the DTS data to the data structure.

>
> Signed-off-by: Dan Murphy 
> ---
>  drivers/net/phy/ti.c | 71 
> 
>  include/dt-bindings/net/ti-dp83867.h | 35 ++
>  2 files changed, 98 insertions(+), 8 deletions(-)
>  create mode 100644 include/dt-bindings/net/ti-dp83867.h
>
> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
> index c3912d5..6da0523 100644
> --- a/drivers/net/phy/ti.c
> +++ b/drivers/net/phy/ti.c
> @@ -6,6 +6,9 @@
>   */
>  #include 
>  #include 
> +#include 
> +
> +#include 
>  
>  /* TI DP83867 */
>  #define DP83867_DEVADDR  0x1f
> @@ -57,6 +60,17 @@
>  #define MII_MMD_CTRL_INCR_RDWT   0x8000 /* post increment on reads & 
> writes */
>  #define MII_MMD_CTRL_INCR_ON_WT  0xC000 /* post increment on writes only 
> */
>  
> +/* User setting - can be taken from DTS */
> +#define DEFAULT_RX_ID_DELAY  8
> +#define DEFAULT_TX_ID_DELAY  0xa
> +#define DEFAULT_FIFO_DEPTH   1
> +
> +struct dp83867_private {
> + int rx_id_delay;
> + int tx_id_delay;
> + int fifo_depth;
> +};
> +
>  /**
>   * phy_read_mmd_indirect - reads data from the MMD registers
>   * @phydev: The PHY device bus
> @@ -134,16 +148,53 @@ static inline bool phy_interface_is_rgmii(struct 
> phy_device *phydev)
>   phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
>  }
>  
> -/* User setting - can be taken from DTS */
> -#define RX_ID_DELAY  8
> -#define TX_ID_DELAY  0xa
> -#define FIFO_DEPTH   1

Probably should use the #defines here instead of magic numbers.

> +/**
> + * dp83867_data_init - Convenience function for setting PHY specific data
> + * @phydev: the phy_device struct
> + */
> +static int dp83867_data_init(struct phy_device *phydev)
> +{
> + struct dp83867_private *dp83867 = phydev->priv;
> +
> +#ifdef CONFIG_RGMII_RX_ID
> + dp83867->rx_id_delay = CONFIG_RGMII_RX_ID;
> +#else
> + dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
> +#endif
> +
> +#ifdef CONFIG_RGMII_TX_ID
> + dp83867->tx_id_delay = CONFIG_RGMII_TX_ID;
> +#else
> + dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
> +#endif
> +
> +#ifdef CONFIG_FIFO_DEPTH
> + dp83867->fifo_depth = CONFIG_FIFO_DEPTH;
> +#else
> + dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
> +#endif
> + return 0;
> +}
>  
>  static int dp83867_config(struct phy_device *phydev)
>  {
> + struct dp83867_private *dp83867;
>   unsigned int val, delay;
>   int ret;
>  
> + if (!phydev->priv) {
> + dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
> + if (!dp83867)
> + return -ENOMEM;
> +
> + phydev->priv = dp83867;
> + ret = dp83867_data_init(phydev);
> + if (ret)
> + goto dp83867_write_error;
> + } else {
> + dp83867 = (struct dp83867_private *)phydev->priv;
> + }
> +
>   /* Restart the PHY.  */
>   val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
>   phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
> @@ -152,9 +203,9 @@ static int dp83867_config(struct phy_device *phydev)
>   if (phy_interface_is_rgmii(phydev)) {
>   ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
>   (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
> - (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
> + (dp83867->fifo_depth << 
> DP83867_PHYCR_FIFO_DEPTH_SHIFT));
>   if (ret)
> - return ret;
> + goto dp83867_write_error;
>   }
>  
>   if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
> @@ -175,8 +226,8 @@ static int dp83867_config(struct phy_device *phydev)
>   phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
>  DP83867_DEVADDR, phydev->addr, val);
>  
> - delay = (RX_ID_DELAY |
> -  (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
> + delay = (dp83867->rx_id_delay |
> +  (dp83867->tx_id_delay << 
> DP83867_RGMII_TX_CLK_DELAY_SHIFT));
>  
>   phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
>  DP83867_DEVADDR, phydev->addr, delay);
> @@ -184,6 +235,10 @@ static int dp83867_config(struct phy_device *phydev)
>  
>   genphy_config_aneg(phydev);
>   return 0;
> +
> +dp83867_write_error:
> + free(dp83867);
> + return ret;
>  }
>  
>  static struct phy_driver DP83867_driver = {
> diff 

Re: [U-Boot] [PATCH V4 2/3] mx7: psci: add basic psci support

[Peng Fan]

Hi Gary,

On Thu, Mar 31, 2016 at 01:17:07PM +0200, Gary Bisson wrote:
>Hi all,
>
>Sorry to revive an old thread but I have some questions about thit patch.
>
>On Fri, Oct 23, 2015 at 10:13:04AM +0800, Peng Fan wrote:
>> 1. add basic psci support for imx7 chip.
>> 2. support cpu_on and cpu_off.
>> 3. switch to non-secure mode when boot linux kernel.
>> 4. set csu allow accessing all peripherial register in non-secure mode.
>> 
>> Signed-off-by: Frank Li 
>> Signed-off-by: Peng Fan 
>> Cc: Stefano Babic 
>> Cc: Fabio Estevam 
>> ---
>> [snip]
>> diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h 
>> b/arch/arm/include/asm/arch-mx7/imx-regs.h
>> index 4dc11ee..9213374 100644
>> --- a/arch/arm/include/asm/arch-mx7/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
>> @@ -866,6 +866,9 @@ struct cspi_regs {
>>  ECSPI3_BASE_ADDR, \
>>  ECSPI4_BASE_ADDR
>>  
>> +#define CSU_INIT_SEC_LEVEL0 0x00FF00FF
>> +#define CSU_NUM_REGS64
>
>In the security documentation (revA) it is said that there are 40 CSL,
>why is it 64 here?
>
>Also, although this seems to work, later on when the kernel boots I get
>the following CAAM errors:
>caam 3090.caam: failed to acquire DECO 0
>...
>caam 3090.caam: failed to acquire DECO 0
>caam 3090.caam: failed to instantiate RNG
>caam: probe of 3090.caam failed with error -11

This patch will let SoC switch to non sec mode. I have little knowledge
of CAAM, I guess it works in sec mode. So when kernel boots up, it will
complains a lot...

>
>If I revert this patch and therefore leave the CSU to its default state
>at bootup the above CAAM issue disappears, do you have any idea why?


Revert this patch, then all code runs in sec mode.

>
>As a FYI, I am using U-Boot v2016.03 + a few patches that adds support
>for our i.MX7 Nitrogen7 board. You can find the repo here:
>https://github.com/boundarydevices/u-boot-imx6/tree/boundary-v2016.03
>
>Also, if I base U-Boot on top of NXP repo it works too since this csu/psci
>support isn't there:
>http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/?id=rel_imx_3.14.52_1.1.0_ga

Yeah. NXP code not switch to non sec mode.

You can revert this patch in your vendor tree. I am not sure whether you
have tested linux upstream tree, or you use caam code from NXP vendor
tree. If you use NXP vendor tree, and use uboot upstream code, sure
caam will complain errros. We would like to use PSCI and work in
non-sec mode, but still some works need to be done.

Regards,
Peng.

>
>Regards,
>Gary
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[U-Boot] [PATCH] spi: Support 4 byte address only SPI flash

[Tim Chick]

Add support to use 4 byte addresses for SPI flash, configured with
SPI_FLASH_USE_4B_ADDR. The Macronix MX25L25735F only supports 4 byte addresses,
but has the same ID as the MX25L25635E, which supports 3 and 4 byte address
modes. When using the MX25L25735F, flash reads and writes were corrupted with
no notification to the user. When in 4 byte mode, SPI_FLASH_BAR is not required.

CONFIG_SPI_FLASH_USE_4B_ADDR - use 4 byte addresses for all SPI flash data
read, write and erase operations.

CONFIG_SPI_FLASH_LARGE_NONE - dummy option if SPI_FLASH_BAR and
SPI_FLASH_USE_4B_ADDR are not selected

Signed-off-by: Tim Chick 
---

 drivers/mtd/spi/Kconfig   | 34 ++
 drivers/mtd/spi/sf_internal.h |  5 +
 drivers/mtd/spi/spi_flash.c   | 11 +--
 3 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 3f7433c..70d73d47 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -34,6 +34,24 @@ config SPI_FLASH
 
  If unsure, say N
 
+choice
+   prompt "Large SPI flash support"
+   default SPI_FLASH_LARGE_NONE
+   help
+ Large SPI flash support
+
+ Choose scheme to use SPI flash chip larger than 16MBytes.
+ SPI flash normally uses 3 bytes of addressing, limit the
+  directly addressable flash size to 16MBytes.
+config SPI_FLASH_LARGE_NONE
+   bool "None"
+   depends on SPI_FLASH
+   help
+ For SPI flash chips 16MByte or smaller
+
+  This is a dummy option, and no special method is used to
+  address large flash chips. Only the bottom 16MByte of
+  any flash chip will be addressable.
 config SPI_FLASH_BAR
bool "SPI flash Bank/Extended address register support"
depends on SPI_FLASH
@@ -42,6 +60,22 @@ config SPI_FLASH_BAR
  Bank/Extended address registers are used to access the flash
  which has size > 16MiB in 3-byte addressing.
 
+config SPI_FLASH_USE_4B_ADDR
+   bool "Use 4 byte flash address instead of 3 bytes"
+   depends on SPI_FLASH
+   help
+  Some SPI flash chips only support 4 byte addresses. Always use
+ 4-byte addresses. SPI_FLASH_BAR should be turned off, as 4 byte
+ address allows 4GB of flash space.
+
+ Selecting this option for a flash chip which is not 4 byte address
+  only will cause flash reads and writes to be corrupted. Most flash
+  chips support 3 byte mode.
+
+ If unsure, say N
+
+endchoice
+
 if SPI_FLASH
 
 config SPI_FLASH_ATMEL
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 007a5a0..4d05a7b 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -54,7 +54,12 @@ enum spi_nor_option_flags {
 };
 
 #define SPI_FLASH_3B_ADDR_LEN  3
+#define SPI_FLASH_4B_ADDR_LEN  4
+#ifdef CONFIG_SPI_FLASH_USE_4B_ADDR
+#define SPI_FLASH_CMD_LEN  (1 + SPI_FLASH_4B_ADDR_LEN)
+#else
 #define SPI_FLASH_CMD_LEN  (1 + SPI_FLASH_3B_ADDR_LEN)
+#endif
 #define SPI_FLASH_16MB_BOUN0x100
 
 /* CFI Manufacture ID's */
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 44d9e9b..10594cc 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -25,9 +25,16 @@ DECLARE_GLOBAL_DATA_PTR;
 static void spi_flash_addr(u32 addr, u8 *cmd)
 {
/* cmd[0] is actual command */
+#ifdef CONFIG_SPI_FLASH_USE_4B_ADDR
+   cmd[1] = addr >> 24;
+   cmd[2] = addr >> 16;
+   cmd[3] = addr >> 8;
+   cmd[4] = addr >> 0;
+#else
cmd[1] = addr >> 16;
cmd[2] = addr >> 8;
cmd[3] = addr >> 0;
+#endif
 }
 
 static int read_sr(struct spi_flash *flash, u8 *rs)
@@ -1180,13 +1187,13 @@ int spi_flash_scan(struct spi_flash *flash)
puts("\n");
 #endif
 
-#ifndef CONFIG_SPI_FLASH_BAR
+#if !(defined CONFIG_SPI_FLASH_BAR) && !(defined CONFIG_SPI_FLASH_USE_4B_ADDR)
if (((flash->dual_flash == SF_SINGLE_FLASH) &&
 (flash->size > SPI_FLASH_16MB_BOUN)) ||
 ((flash->dual_flash > SF_SINGLE_FLASH) &&
 (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
puts("SF: Warning - Only lower 16MiB accessible,");
-   puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
+   puts(" Full access #define CONFIG_SPI_FLASH_BAR or 
CONFIG_SPI_FLASH_USE_4B_ADDR\n");
}
 #endif
 
-- 
2.1.4

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[U-Boot] [PATCH] mips: Report reloc information in bdinfo

[tim.chick]

Signed-off-by: tim.chick 
---

 cmd/bdinfo.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 8eda68b..1c4bed9 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -341,6 +341,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
printf("baudrate= %u bps\n", gd->baudrate);
+   print_num("relocaddr", gd->relocaddr);
+   print_num("reloc off", gd->reloc_off);
 
return 0;
 }
-- 
2.1.4

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[U-Boot] [RFC PATCH 2/2] board: ti: DRA7: Add in RGMII parameters for rev c

[Dan Murphy]

Add in the rx/tx delay as well as the fifo depth
for the dra7 evm rev c board.

Signed-off-by: Dan Murphy 
---
 include/configs/dra7xx_evm.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 7734e8d..0b20b6d 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -157,6 +157,10 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_TI
 
+#define CONFIG_RGMII_RX_ID DP83867_RGMIIDCTL_2_00_NS
+#define CONFIG_RGMII_TX_ID DP83867_RGMIIDCTL_1_NS
+#define CONFIG_FIFO_DEPTH  DP83867_PHYCR_FIFO_DEPTH_8_B_NIB
+
 /* SPI */
 #undef CONFIG_OMAP3_SPI
 #define CONFIG_CMD_SF
-- 
2.8.0.rc3

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[U-Boot] [RFC PATCH 1/2] net: phy: ti: Allow the driver to be more configurable

[Dan Murphy]

Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the config file.  If the value is not set in the
config file then set the delay to the default.

Signed-off-by: Dan Murphy 
---
 drivers/net/phy/ti.c | 71 
 include/dt-bindings/net/ti-dp83867.h | 35 ++
 2 files changed, 98 insertions(+), 8 deletions(-)
 create mode 100644 include/dt-bindings/net/ti-dp83867.h

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index c3912d5..6da0523 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -6,6 +6,9 @@
  */
 #include 
 #include 
+#include 
+
+#include 
 
 /* TI DP83867 */
 #define DP83867_DEVADDR0x1f
@@ -57,6 +60,17 @@
 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
 #define MII_MMD_CTRL_INCR_ON_WT0xC000 /* post increment on writes only 
*/
 
+/* User setting - can be taken from DTS */
+#define DEFAULT_RX_ID_DELAY8
+#define DEFAULT_TX_ID_DELAY0xa
+#define DEFAULT_FIFO_DEPTH 1
+
+struct dp83867_private {
+   int rx_id_delay;
+   int tx_id_delay;
+   int fifo_depth;
+};
+
 /**
  * phy_read_mmd_indirect - reads data from the MMD registers
  * @phydev: The PHY device bus
@@ -134,16 +148,53 @@ static inline bool phy_interface_is_rgmii(struct 
phy_device *phydev)
phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 }
 
-/* User setting - can be taken from DTS */
-#define RX_ID_DELAY8
-#define TX_ID_DELAY0xa
-#define FIFO_DEPTH 1
+/**
+ * dp83867_data_init - Convenience function for setting PHY specific data
+ * @phydev: the phy_device struct
+ */
+static int dp83867_data_init(struct phy_device *phydev)
+{
+   struct dp83867_private *dp83867 = phydev->priv;
+
+#ifdef CONFIG_RGMII_RX_ID
+   dp83867->rx_id_delay = CONFIG_RGMII_RX_ID;
+#else
+   dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
+#endif
+
+#ifdef CONFIG_RGMII_TX_ID
+   dp83867->tx_id_delay = CONFIG_RGMII_TX_ID;
+#else
+   dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
+#endif
+
+#ifdef CONFIG_FIFO_DEPTH
+   dp83867->fifo_depth = CONFIG_FIFO_DEPTH;
+#else
+   dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
+#endif
+   return 0;
+}
 
 static int dp83867_config(struct phy_device *phydev)
 {
+   struct dp83867_private *dp83867;
unsigned int val, delay;
int ret;
 
+   if (!phydev->priv) {
+   dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
+   if (!dp83867)
+   return -ENOMEM;
+
+   phydev->priv = dp83867;
+   ret = dp83867_data_init(phydev);
+   if (ret)
+   goto dp83867_write_error;
+   } else {
+   dp83867 = (struct dp83867_private *)phydev->priv;
+   }
+
/* Restart the PHY.  */
val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
@@ -152,9 +203,9 @@ static int dp83867_config(struct phy_device *phydev)
if (phy_interface_is_rgmii(phydev)) {
ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
-   (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+   (dp83867->fifo_depth << 
DP83867_PHYCR_FIFO_DEPTH_SHIFT));
if (ret)
-   return ret;
+   goto dp83867_write_error;
}
 
if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
@@ -175,8 +226,8 @@ static int dp83867_config(struct phy_device *phydev)
phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
   DP83867_DEVADDR, phydev->addr, val);
 
-   delay = (RX_ID_DELAY |
-(TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+   delay = (dp83867->rx_id_delay |
+(dp83867->tx_id_delay << 
DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 
phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
   DP83867_DEVADDR, phydev->addr, delay);
@@ -184,6 +235,10 @@ static int dp83867_config(struct phy_device *phydev)
 
genphy_config_aneg(phydev);
return 0;
+
+dp83867_write_error:
+   free(dp83867);
+   return ret;
 }
 
 static struct phy_driver DP83867_driver = {
diff --git a/include/dt-bindings/net/ti-dp83867.h 
b/include/dt-bindings/net/ti-dp83867.h
new file mode 100644
index 000..5c592fb
--- /dev/null
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -0,0 +1,35 @@
+/*
+ * TI DP83867 PHY drivers
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ *
+ */
+
+#ifndef _DT_BINDINGS_TI_DP83867_H
+#define _DT_BINDINGS_TI_DP83867_H
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB   0x00
+#define 

Re: [U-Boot] [PATCH v5 0/3] net: phy: Force master mode for RTL8211C on some boards

[Hans de Goede]

Hi,

On 25-03-16 18:22, Michael Haas wrote:

This patch is required to get reliable 1000BASE-T operation on some
boards using the RTL8211C(L) PHY.

Following discussions on v2 of this patch, I have removed the incorrect
check for the RTL8211C(L). Affected boards now have to define
CONFIG_RTL8211X_PHY_FORCE_MASTER to benefit from the fix.

Note that this patch requires Karsten Merkers '[PATCH] net: phy: Realtek
RTL8211B/C PHY ID fix' as well as Hans de Goede's recent u-boot-sunxi
pull request, specifically 1eae8f66ff749409eb96e2f3f3387c56232d0b8a and
fc8991c61c393ce6a9d3dfc97cb56dbbd9e8cbba.

Michael


Thanks, I've applied this series to my tree, and it will be part of
the next u-boot-sunxi pull-req.

Regards,

Hans





Changes in v5:
  - Improve formatting of Kconfig help text. No content change. Change
suggested by Karsten Merker.
  - Fix order of defconfig entry (suggested by Karsten Marker)
Series-changes: 4
  - Changed commit summary according to Chen-Yu Tsai's suggestion,
modified to fit the 70 character limit
  - Fix order of defconfig entry (suggested by Karsten Marker)

Changes in v4:
  - Squashed previously separate commit introducing KCONFIG variable
into commit containing main code change (Hans de Goede's suggestion)
  - Changed KCONFIG description according to Karsten Merker's suggestions
plus some clarification of my own
  - Changed commit message according to Karsten Merker's suggestions
  - Changed commit summary according to Chen-Yu Tsai's suggestion,
modified to fit the 70 character limit

Changes in v3:
  - Remove incorrect detection of RTL8211CL and use #ifdef instead
(thanks to Karsten Merker)
  - Introduced constants for register bits

Changes in v2:
  - Removed accidental inclusion of Karsten's patch in my first submission of 
this series.
  - Fix a typo in the code: 6 -> &

Michael Haas (3):
   net: phy: Optionally force master mode for RTL PHY
   sunxi: A20-Olimex-SOM-EVB: Force 8211CL to master
   sunxi: A20-OLinuXino-Lime2: Force 8211CL to master

  configs/A20-OLinuXino-Lime2_defconfig |  1 +
  configs/A20-Olimex-SOM-EVB_defconfig  |  1 +
  drivers/net/Kconfig   | 21 +
  drivers/net/phy/realtek.c | 13 -
  4 files changed, 35 insertions(+), 1 deletion(-)


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Re: [U-Boot] [PATCH V4 2/3] mx7: psci: add basic psci support

[Gary Bisson]

Hi all,

Sorry to revive an old thread but I have some questions about thit patch.

On Fri, Oct 23, 2015 at 10:13:04AM +0800, Peng Fan wrote:
> 1. add basic psci support for imx7 chip.
> 2. support cpu_on and cpu_off.
> 3. switch to non-secure mode when boot linux kernel.
> 4. set csu allow accessing all peripherial register in non-secure mode.
> 
> Signed-off-by: Frank Li 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> ---
> [snip]
> diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h 
> b/arch/arm/include/asm/arch-mx7/imx-regs.h
> index 4dc11ee..9213374 100644
> --- a/arch/arm/include/asm/arch-mx7/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
> @@ -866,6 +866,9 @@ struct cspi_regs {
>   ECSPI3_BASE_ADDR, \
>   ECSPI4_BASE_ADDR
>  
> +#define CSU_INIT_SEC_LEVEL0  0x00FF00FF
> +#define CSU_NUM_REGS 64

In the security documentation (revA) it is said that there are 40 CSL,
why is it 64 here?

Also, although this seems to work, later on when the kernel boots I get
the following CAAM errors:
caam 3090.caam: failed to acquire DECO 0
...
caam 3090.caam: failed to acquire DECO 0
caam 3090.caam: failed to instantiate RNG
caam: probe of 3090.caam failed with error -11

If I revert this patch and therefore leave the CSU to its default state
at bootup the above CAAM issue disappears, do you have any idea why?

As a FYI, I am using U-Boot v2016.03 + a few patches that adds support
for our i.MX7 Nitrogen7 board. You can find the repo here:
https://github.com/boundarydevices/u-boot-imx6/tree/boundary-v2016.03

Also, if I base U-Boot on top of NXP repo it works too since this csu/psci
support isn't there:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/?id=rel_imx_3.14.52_1.1.0_ga

Regards,
Gary
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Re: [U-Boot] [PATCH] dm: ns16550: Add support for reg-offset property

[Michal Simek]

Hi Simon,


>> diff --git a/include/ns16550.h b/include/ns16550.h
>> index 5eeacd6..1311f4c 100644
>> --- a/include/ns16550.h
>> +++ b/include/ns16550.h
>> @@ -54,9 +54,9 @@
>>   */
>>  struct ns16550_platdata {
>> unsigned long base;
>> -   int reg_offset;
>> int reg_shift;
>> int clock;
>> +   int reg_offset;
>>  };
>>
>>  struct udevice;
>>
> 
> I picked up Alexander's suggestion: Still, we should fix everything up
> to use member names.
> 
> Applied to u-boot-dm/next, thanks!

I can't see this patch applied to your next branch.
Can you please check it?

Thanks,
Michal





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[U-Boot] [PATCH] ARM64: zynqmp: Enable EFI partition support

[Michal Simek]

Enable EFI partition support for ZynqMP.

Signed-off-by: Michal Simek 

---

 include/configs/xilinx_zynqmp.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 8c760967f6d6..8cea61080d49 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -71,6 +71,7 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
 #define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
 #define CONFIG_MP
 
 #define CONFIG_CMD_MII
-- 
1.9.1

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[U-Boot] [PATCH 2/2] net: zynq_gem: Add SGMII support for zynqMP

[Michal Simek]

From: Siva Durga Prasad Paladugu 

PCS auto negotaiation bit should be enabled
along with SGMII autonegotation enabled
in phy.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 drivers/net/zynq_gem.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 52a8f2760012..aec8077f10b3 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -93,6 +93,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define ZYNQ_GEM_TSR_DONE  0x0020 /* Tx done mask */
 
+#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
+
 /* Use MII register 1 (MII status register) to detect PHY */
 #define PHY_DETECT_REG  1
 
@@ -139,7 +141,9 @@ struct zynq_gem_regs {
u32 reserved6[18];
 #define STAT_SIZE  44
u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
-   u32 reserved7[164];
+   u32 reserved9[20];
+   u32 pcscntrl;
+   u32 reserved7[143];
u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
u32 reserved8[15];
u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
@@ -432,9 +436,14 @@ static int zynq_gem_init(struct udevice *dev)
 
nwconfig = ZYNQ_GEM_NWCFG_INIT;
 
-   if (priv->interface == PHY_INTERFACE_MODE_SGMII)
+   if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
ZYNQ_GEM_NWCFG_PCS_SEL;
+#ifdef CONFIG_ARM64
+   writel(readl(>pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+  >pcscntrl);
+#endif
+   }
 
switch (priv->phydev->speed) {
case SPEED_1000:
-- 
1.9.1

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[U-Boot] [PATCH 1/2] net: phy: Add SGMII support for TI phy

[Michal Simek]

From: Siva Durga Prasad Paladugu 

Add support of SGMII to TI phy dp838367
Enable the SGMII and PCS settings in phy
control, CFG2 and BIST registers

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 drivers/net/phy/ti.c | 39 ++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index c3912d52f320..937426bc8565 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -12,6 +12,8 @@
 
 #define MII_DP83867_PHYCTRL0x10
 #define MII_DP83867_MICR   0x12
+#define MII_DP83867_CFG2   0x14
+#define MII_DP83867_BISCR  0x16
 #define DP83867_CTRL   0x1f
 
 /* Extended Registers */
@@ -43,10 +45,22 @@
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
 #define DP83867_MDI_CROSSOVER  5
 #define DP83867_MDI_CROSSOVER_AUTO 2
+#define DP83867_MDI_CROSSOVER_MDIX 2
+#define DP83867_PHYCTRL_SGMIIEN0x0800
+#define DP83867_PHYCTRL_RXFIFO_SHIFT   12
+#define DP83867_PHYCTRL_TXFIFO_SHIFT   14
 
 /* RGMIIDCTL bits */
 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT   4
 
+/* CFG2 bits */
+#define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
+#define MII_DP83867_CFG2_SGMII_AUTONEGEN   0x0080
+#define MII_DP83867_CFG2_SPEEDOPT_ENH  0x0100
+#define MII_DP83867_CFG2_SPEEDOPT_CNT  0x0800
+#define MII_DP83867_CFG2_SPEEDOPT_INTLOW   0x2000
+#define MII_DP83867_CFG2_MASK  0x003F
+
 #define MII_MMD_CTRL   0x0d /* MMD Access Control Register */
 #define MII_MMD_DATA   0x0e /* MMD Access Data Register */
 
@@ -141,7 +155,7 @@ static inline bool phy_interface_is_rgmii(struct phy_device 
*phydev)
 
 static int dp83867_config(struct phy_device *phydev)
 {
-   unsigned int val, delay;
+   unsigned int val, delay, cfg2;
int ret;
 
/* Restart the PHY.  */
@@ -155,6 +169,29 @@ static int dp83867_config(struct phy_device *phydev)
(FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
if (ret)
return ret;
+   } else {
+   phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
+ (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
+
+   cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
+   cfg2 &= MII_DP83867_CFG2_MASK;
+   cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
+MII_DP83867_CFG2_SGMII_AUTONEGEN |
+MII_DP83867_CFG2_SPEEDOPT_ENH |
+MII_DP83867_CFG2_SPEEDOPT_CNT |
+MII_DP83867_CFG2_SPEEDOPT_INTLOW);
+   phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
+
+   phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
+  DP83867_DEVADDR, phydev->addr, 0x0);
+
+   phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
+ DP83867_PHYCTRL_SGMIIEN |
+ (DP83867_MDI_CROSSOVER_MDIX <<
+ DP83867_MDI_CROSSOVER) |
+ (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
+ (FIFO_DEPTH  << DP83867_PHYCTRL_TXFIFO_SHIFT));
+   phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
}
 
if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
-- 
1.9.1

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[U-Boot] [PATCH] net: zynq_gem: Return error incase of invalid phy address

[Michal Simek]

From: Siva Durga Prasad Paladugu 

Return error from probe in case of invalid phy address.
This fixes the issue of uboot crash if phy is not detected.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 drivers/net/zynq_gem.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 103ed6169c0f..52a8f2760012 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -638,9 +638,7 @@ static int zynq_gem_probe(struct udevice *dev)
if (ret)
return ret;
 
-   zynq_phy_init(dev);
-
-   return 0;
+   return zynq_phy_init(dev);
 }
 
 static int zynq_gem_remove(struct udevice *dev)
-- 
1.9.1

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[U-Boot] [PATCH 1/2] ARM: zynq: Enable FLASH_BAR for microzed and zybo

[Michal Simek]

Enable FLASH_BAR for these targets to be in sync with all zynq boards.

Signed-off-by: Michal Simek 
---

 configs/zynq_microzed_defconfig | 1 +
 configs/zynq_zybo_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 4c5152fa73e7..1d70e43df0c8 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -15,6 +15,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 470c9cbb1252..ee7e23b36fca 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -15,6 +15,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART=y
-- 
1.9.1

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[U-Boot] [PATCH 2/2] ARM: zynq: Add uEnv.txt support

[Michal Simek]

From: Michal Simek 

preboot macro load the uEnv.txt from mmc 0 when bootmode is mmc. uenvcmd is
executed after load of uEnv.txt if it is defined in the uEnv.txt env text
file.

The default importbootenv macro reads the uEnv.txt from mmc.

Additional to this, usb_loadbootenv is added to support loading uEnv.txt
from usb dev 0.

Signed-off-by: Jason Wu 
Signed-off-by: Michal Simek 
---

 include/configs/zynq-common.h | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 25ca4769b1ae..d7189d3e123e 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -205,6 +205,9 @@
 # define CONFIG_ENV_OFFSET 0xE
 #endif
 
+/* enable preboot to be loaded before CONFIG_BOOTDELAY */
+#define CONFIG_PREBOOT
+
 /* Default environment */
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS  \
@@ -215,6 +218,29 @@
"nor_flash_off=0xE210\0"\
"fdt_high=0x2000\0" \
"initrd_high=0x2000\0"  \
+   "loadbootenv_addr=0x200\0" \
+   "bootenv=uEnv.txt\0" \
+   "bootenv_dev=mmc\0" \
+   "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
+   "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
+   "env import -t ${loadbootenv_addr} $filesize\0" \
+   "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
+   "setbootenv=if env run bootenv_existence_test; then " \
+   "if env run loadbootenv; then " \
+   "env run importbootenv; " \
+   "fi; " \
+   "fi; \0" \
+   "sd_loadbootenv=set bootenv_dev mmc && " \
+   "run setbootenv \0" \
+   "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" 
\
+   "preboot=if test $modeboot = sdboot; then " \
+   "run sd_loadbootenv; " \
+   "echo Checking if uenvcmd is set ...; " \
+   "if test -n $uenvcmd; then " \
+   "echo Running uenvcmd ...; " \
+   "run uenvcmd; " \
+   "fi; " \
+   "fi; \0" \
"norboot=echo Copying FIT from NOR flash to RAM... && " \
"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
"bootm ${load_addr}\0" \
-- 
1.9.1

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[U-Boot] [PATCH] block: Add support for Ceva sata

[Michal Simek]

Initial Ceva Sata init code.

Signed-off-by: Michal Simek 
---

 board/xilinx/zynqmp/zynqmp.c|   4 ++
 drivers/block/Makefile  |   1 +
 drivers/block/sata_ceva.c   | 113 
 include/configs/xilinx_zynqmp.h |   2 +-
 4 files changed, 119 insertions(+), 1 deletion(-)
 create mode 100644 drivers/block/sata_ceva.c

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 0f44b04c1efa..087578cb6b9c 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -7,6 +7,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -185,6 +186,9 @@ void reset_cpu(ulong addr)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 void scsi_init(void)
 {
+#if defined(CONFIG_SATA_CEVA)
+   init_sata(0);
+#endif
ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
scsi_scan(1);
 }
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index b5c7ae1124d1..57bff5f9de26 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_LIBATA) += libata.o
 obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
 obj-$(CONFIG_MX51_PATA) += mxc_ata.o
 obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
+obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
 obj-$(CONFIG_SATA_DWC) += sata_dwc.o
 obj-$(CONFIG_SATA_MV) += sata_mv.o
 obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
diff --git a/drivers/block/sata_ceva.c b/drivers/block/sata_ceva.c
new file mode 100644
index ..dcc3b90b17f1
--- /dev/null
+++ b/drivers/block/sata_ceva.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2015 - 2016 Xilinx, Inc.
+ * Michal Simek 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* Vendor Specific Register Offsets */
+#define AHCI_VEND_PCFG  0xA4
+#define AHCI_VEND_PPCFG 0xA8
+#define AHCI_VEND_PP2C  0xAC
+#define AHCI_VEND_PP3C  0xB0
+#define AHCI_VEND_PP4C  0xB4
+#define AHCI_VEND_PP5C  0xB8
+#define AHCI_VEND_PAXIC 0xC0
+#define AHCI_VEND_PTC   0xC8
+
+/* Vendor Specific Register bit definitions */
+#define PAXIC_ADBW_BW64 0x1
+#define PAXIC_MAWIDD   (1 << 8)
+#define PAXIC_MARIDD   (1 << 16)
+#define PAXIC_OTL  (0x4 << 20)
+
+#define PCFG_TPSS_VAL  (0x32 << 16)
+#define PCFG_TPRS_VAL  (0x2 << 12)
+#define PCFG_PAD_VAL   0x2
+
+#define PPCFG_TTA  0x1FFFE
+#define PPCFG_PSSO_EN  (1 << 28)
+#define PPCFG_PSS_EN   (1 << 29)
+#define PPCFG_ESDF_EN  (1 << 31)
+
+#define PP2C_CIBGMN0x0F
+#define PP2C_CIBGMX(0x25 << 8)
+#define PP2C_CIBGN (0x18 << 16)
+#define PP2C_CINMP (0x29 << 24)
+
+#define PP3C_CWBGMN0x04
+#define PP3C_CWBGMX(0x0B << 8)
+#define PP3C_CWBGN (0x08 << 16)
+#define PP3C_CWNMP (0x0F << 24)
+
+#define PP4C_BMX   0x0a
+#define PP4C_BNM   (0x08 << 8)
+#define PP4C_SFD   (0x4a << 16)
+#define PP4C_PTST  (0x06 << 24)
+
+#define PP5C_RIT   0x60216
+#define PP5C_RCT   (0x7f0 << 20)
+
+#define PTC_RX_WM_VAL  0x40
+#define PTC_RSVD   (1 << 27)
+
+#define PORT0_BASE 0x100
+#define PORT1_BASE 0x180
+
+/* Port Control Register Bit Definitions */
+#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
+#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
+#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
+#define PORT_SCTL_IPM  (0x3 << 8)
+
+#define PORT_BASE  0x100
+#define PORT_OFFSET0x80
+#define NR_PORTS   2
+#define DRV_NAME   "ahci-ceva"
+#define CEVA_FLAG_BROKEN_GEN2  1
+
+int init_sata(int dev)
+{
+   ulong tmp;
+   ulong mmio = ZYNQMP_SATA_BASEADDR;
+   int i;
+
+   /*
+* AXI Data bus width to 64
+* Set Mem Addr Read, Write ID for data transfers
+* Transfer limit to 72 DWord
+*/
+   tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+   writel(tmp, mmio + AHCI_VEND_PAXIC);
+
+   /* Set AHCI Enable */
+   tmp = readl(mmio + HOST_CTL);
+   tmp |= HOST_AHCI_EN;
+   writel(tmp, mmio + HOST_CTL);
+
+   for (i = 0; i < NR_PORTS; i++) {
+   /* TPSS TPRS scalars, CISE and Port Addr */
+   tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
+   writel(tmp, mmio + AHCI_VEND_PCFG);
+
+   /* Port Phy Cfg register enables */
+   tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
+   writel(tmp, mmio + AHCI_VEND_PPCFG);
+
+   /* Rx Watermark setting  */
+   tmp = PTC_RX_WM_VAL | PTC_RSVD;
+   writel(tmp, mmio + AHCI_VEND_PTC);
+
+   /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
+   tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
+   writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
+   }
+   return 0;
+}
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 4062e01824e3..8c760967f6d6 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ 

[U-Boot] [PATCH 2/6] ARM64: zynqmp: Enable FAT write and EXT4 write for USB too

[Michal Simek]

From: Michal Simek 

Enabling writing files to FAT and EXT4 for USB.

Signed-off-by: Michal Simek 
---

 include/configs/xilinx_zynqmp.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index b60239614fad..0ecdc13bfa8e 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -93,6 +93,9 @@
 # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
 #  define CONFIG_ZYNQ_SDHCI_MAX_FREQ   2
 # endif
+#endif
+
+#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQMP_USB)
 # define CONFIG_FAT_WRITE
 # define CONFIG_CMD_EXT4_WRITE
 #endif
-- 
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[U-Boot] [PATCH 6/6] ARM64: zynqmp: Simplify MAINTAINERS file to support more boards

[Michal Simek]

Handle all Xilinx ZynqMP boards with one fragment.

Signed-off-by: Michal Simek 
---

 board/xilinx/zynqmp/MAINTAINERS | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index 20ca6522e570..69edbf21f91c 100644
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -1,7 +1,6 @@
-XILINX_ZYNQMP_EP BOARD
+XILINX_ZYNQMP BOARDS
 M: Michal Simek 
 S: Maintained
 F: board/xilinx/zynqmp/
-F: include/configs/xilinx_zynqmp.h
-F: include/configs/xilinx_zynqmp_ep.h
-F: configs/xilinx_zynqmp_ep_defconfig
+F: include/configs/xilinx_zynqmp*
+F: configs/xilinx_zynqmp*
-- 
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[U-Boot] [PATCH 5/6] ARM64: zynqmp: Read RAM information from DT

[Michal Simek]

Read information about memory from DT. This patch simplify life with
synchronization between DT and board files.

dram_init() only needs maximum RAM size below 4GB that's why please sort
banks in memory node.
dram_init_banksize() copies memory setup to bi_dram[].
This will avoid reading information from DT twice.

Memory test start/end were changed to DDR location to let memtest still
compiled.

Signed-off-by: Michal Simek 
---

 board/xilinx/zynqmp/zynqmp.c   | 121 +
 include/configs/xilinx_zynqmp.h|   9 ++-
 include/configs/xilinx_zynqmp_ep.h |   5 --
 3 files changed, 127 insertions(+), 8 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 44d347ed3bf0..0f44b04c1efa 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -50,12 +50,133 @@ int board_early_init_r(void)
return 0;
 }
 
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+  const u32 *cell, int n)
+{
+   int i = 0, b, banks;
+   int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+   int address_cells = fdt_address_cells(fdt, parent_offset);
+   int size_cells = fdt_size_cells(fdt, parent_offset);
+   char *p = buf;
+   phys_addr_t val;
+   phys_size_t vals;
+
+   debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+ __func__, address_cells, size_cells, buf, cell);
+
+   /* Check memory bank setup */
+   banks = n % (address_cells + size_cells);
+   if (banks)
+   panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+ n, address_cells, size_cells);
+
+   banks = n / (address_cells + size_cells);
+
+   for (b = 0; b < banks; b++) {
+   debug("%s: Bank #%d:\n", __func__, b);
+   if (address_cells == 2) {
+   val = cell[i + 1];
+   val <<= 32;
+   val |= cell[i];
+   val = fdt64_to_cpu(val);
+   debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+ __func__, val, p, [i]);
+   *(phys_addr_t *)p = val;
+   } else {
+   debug("%s: addr32=%x, ptr=%p\n",
+ __func__, fdt32_to_cpu(cell[i]), p);
+   *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+   }
+   p += sizeof(phys_addr_t);
+   i += address_cells;
+
+   debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+ sizeof(phys_addr_t));
+
+   if (size_cells == 2) {
+   vals = cell[i + 1];
+   vals <<= 32;
+   vals |= cell[i];
+   vals = fdt64_to_cpu(vals);
+
+   debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+ __func__, vals, p, [i]);
+   *(phys_size_t *)p = vals;
+   } else {
+   debug("%s: size32=%x, ptr=%p\n",
+ __func__, fdt32_to_cpu(cell[i]), p);
+   *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+   }
+   p += sizeof(phys_size_t);
+   i += size_cells;
+
+   debug("%s: ps=%p, i=%x, size=%zu\n",
+ __func__, p, i, sizeof(phys_size_t));
+   }
+
+   /* Return the first address size */
+   return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE  sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+   int bank;
+
+   memcpy(>bd->bi_dram[0], , sizeof(tmp));
+
+   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+   debug("Bank #%d: start %llx\n", bank,
+ (unsigned long long)gd->bd->bi_dram[bank].start);
+   debug("Bank #%d: size %llx\n", bank,
+ (unsigned long long)gd->bd->bi_dram[bank].size);
+   }
+}
+
+int dram_init(void)
+{
+   int node, len;
+   const void *blob = gd->fdt_blob;
+   const u32 *cell;
+
+   memset(, 0, sizeof(tmp));
+
+   /* find or create "/memory" node. */
+   node = fdt_subnode_offset(blob, 0, "memory");
+   if (node < 0) {
+   printf("%s: Can't get memory node\n", __func__);
+   return node;
+   }
+
+   /* Get pointer to cells and lenght of it */
+   cell = fdt_getprop(blob, node, "reg", );
+   if (!cell) {
+   printf("%s: Can't get reg property\n", __func__);
+   return -1;
+   }
+
+   gd->ram_size = 

[U-Boot] [PATCH 4/6] ARM64: Move HUSH enabling from board file to defconfig

[Michal Simek]

Simplify board config file.

Signed-off-by: Michal Simek 
---

 configs/xilinx_zynqmp_ep_defconfig | 1 +
 include/configs/xilinx_zynqmp.h| 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/xilinx_zynqmp_ep_defconfig 
b/configs/xilinx_zynqmp_ep_defconfig
index a1f3580f8d01..91ae10ab211b 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 0ecdc13bfa8e..ed47283c1766 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -184,7 +184,6 @@
 #define CONFIG_SYS_CBSIZE  2048
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
-- 
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[U-Boot] [PATCH 3/6] ARM64: zynqmp: Select SYS_CONFIG_NAME via Kconfig

[Michal Simek]

This option enable adding new platform suport just by adding defconfig
and DTS file which will target generic configuration for SoC.
Make no sense to extend Kconfig just create a pointer between DTS and
configuration file.

Signed-off-by: Michal Simek 
---

 arch/arm/cpu/armv8/zynqmp/Kconfig  | 15 ++-
 configs/xilinx_zynqmp_ep_defconfig |  1 +
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig 
b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 9a19dfa77f79..6c71d7840eb5 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -1,13 +1,5 @@
 if ARCH_ZYNQMP
 
-choice
-   prompt "Xilinx ZynqMP board select"
-
-config TARGET_ZYNQMP_EP
-   bool "ZynqMP EP Board"
-
-endchoice
-
 config SYS_BOARD
default "zynqmp"
 
@@ -18,7 +10,12 @@ config SYS_SOC
default "zynqmp"
 
 config SYS_CONFIG_NAME
-   default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
+   string "Board configuration name"
+   default "xilinx_zynqmp"
+   help
+ This option contains information about board configuration name.
+ Based on this option include/configs/.h header
+ will be used for board configuration.
 
 config ZYNQMP_USB
bool "Configure ZynqMP USB"
diff --git a/configs/xilinx_zynqmp_ep_defconfig 
b/configs/xilinx_zynqmp_ep_defconfig
index 33f29afab88c..a1f3580f8d01 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x800
-- 
1.9.1

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[U-Boot] [PATCH 1/6] ARM64: zynqmp: Decrease boot delay

[Michal Simek]

From: Soren Brinkmann 

Synchronize it with zynq platform.

Signed-off-by: Soren Brinkmann 
Signed-off-by: Michal Simek 
---

 include/configs/xilinx_zynqmp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 4e066cdfd233..b60239614fad 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -168,7 +168,7 @@
 
 #define CONFIG_PREBOOT "run bootargs"
 #define CONFIG_BOOTCOMMAND "run $modeboot"
-#define CONFIG_BOOTDELAY   5
+#define CONFIG_BOOTDELAY   3
 
 #define CONFIG_BOARD_LATE_INIT
 
-- 
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[U-Boot] [PATCH] net: axi_emac: Report phy-node error message permanently

[Michal Simek]

Do not use debug() when printing error message. Use printf instead.

Signed-off-by: Michal Simek 
---

 drivers/net/xilinx_axi_emac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 3d69bed3093c..5de06ef01e8d 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -715,7 +715,7 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev)
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
-   debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+   printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
-- 
1.9.1

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[U-Boot] [PATCH 2/2] microblaze: Remove !OF_CONTROL code for timer and interrupt

[Michal Simek]

OF_CONTROL is enabled by default that's why this is dead code.

Signed-off-by: Michal Simek 
---

 arch/microblaze/cpu/interrupts.c  |  9 +
 arch/microblaze/cpu/timer.c   | 14 --
 board/xilinx/microblaze-generic/xparameters.h | 11 ---
 include/configs/microblaze-generic.h  | 12 
 4 files changed, 1 insertion(+), 45 deletions(-)

diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index e5d8894f5447..010ca4a02c49 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -115,8 +115,6 @@ static void intc_init(void)
 int interrupt_init(void)
 {
int i;
-
-#ifdef CONFIG_OF_CONTROL
const void *blob = gd->fdt_blob;
int node = 0;
 
@@ -136,12 +134,7 @@ int interrupt_init(void)
} else {
return node;
}
-#else
-#if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
-   intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR;
-   irq_no = CONFIG_SYS_INTC_0_NUM;
-#endif
-#endif
+
if (irq_no) {
vecs = calloc(1, sizeof(struct irq_action) * irq_no);
if (vecs == NULL) {
diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c
index c0fc7c0f3ca1..8845e07d0e8b 100644
--- a/arch/microblaze/cpu/timer.c
+++ b/arch/microblaze/cpu/timer.c
@@ -31,11 +31,6 @@ void __udelay(unsigned long usec)
i = get_timer(0);
while ((get_timer(0) - i) < (usec / 1000))
;
-   } else {
-#ifndef CONFIG_OF_CONTROL
-   for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 1000); i++)
-   ;
-#endif
}
 }
 
@@ -51,8 +46,6 @@ int timer_init (void)
int irq = -1;
u32 preload = 0;
u32 ret = 0;
-
-#ifdef CONFIG_OF_CONTROL
const void *blob = gd->fdt_blob;
int node = 0;
u32 cell[2];
@@ -83,13 +76,6 @@ int timer_init (void)
return node;
}
 
-#else
-#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
-   preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ;
-   irq = CONFIG_SYS_TIMER_0_IRQ;
-   tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
-#endif
-#endif
if (tmr && preload && irq >= 0) {
tmr->loadreg = preload;
tmr->control = TIMER_INTERRUPT | TIMER_RESET;
diff --git a/board/xilinx/microblaze-generic/xparameters.h 
b/board/xilinx/microblaze-generic/xparameters.h
index ccb528ed9266..dc5645bd1461 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -13,21 +13,10 @@
 
 #define XILINX_BOARD_NAME  microblaze-generic
 
-/* System Clock Frequency */
-#define XILINX_CLOCK_FREQ  1
-
 /* Microblaze is microblaze_0 */
 #define XILINX_USE_MSR_INSTR   1
 #define XILINX_FSL_NUMBER  3
 
-/* Interrupt controller is opb_intc_0 */
-#define XILINX_INTC_BASEADDR   0x4120
-#define XILINX_INTC_NUM_INTR_INPUTS6
-
-/* Timer pheriphery is opb_timer_1 */
-#define XILINX_TIMER_BASEADDR  0x41c0
-#define XILINX_TIMER_IRQ   0
-
 /* GPIO is LEDs_4Bit*/
 #define XILINX_GPIO_BASEADDR   0x4000
 
diff --git a/include/configs/microblaze-generic.h 
b/include/configs/microblaze-generic.h
index 27668f2a891c..09bfabcfdf11 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -47,18 +47,6 @@
 #endif
 #define CONFIG_BOARD_LATE_INIT
 
-/* interrupt controller */
-#ifdef XILINX_INTC_BASEADDR
-# define CONFIG_SYS_INTC_0_ADDRXILINX_INTC_BASEADDR
-# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
-#endif
-
-/* timer */
-#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
-#  define CONFIG_SYS_TIMER_0_ADDR  XILINX_TIMER_BASEADDR
-#  define CONFIG_SYS_TIMER_0_IRQ   XILINX_TIMER_IRQ
-#endif
-
 /* watchdog */
 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
 # define CONFIG_WATCHDOG_BASEADDR  XILINX_WATCHDOG_BASEADDR
-- 
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[U-Boot] [PATCH 1/2] microblaze: Read information about timer/interrupts from DT

[Michal Simek]

Read information about timer and interrupts from DT. This is the first
small step to move timer and intc to DM.

Signed-off-by: Michal Simek 
---

 arch/microblaze/cpu/interrupts.c | 25 +
 arch/microblaze/cpu/timer.c  | 39 ++-
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index b6d6610f2fd7..e5d8894f5447 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -10,10 +10,13 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void enable_interrupts(void)
 {
debug("Enable interrupts for the whole CPU\n");
@@ -113,10 +116,32 @@ int interrupt_init(void)
 {
int i;
 
+#ifdef CONFIG_OF_CONTROL
+   const void *blob = gd->fdt_blob;
+   int node = 0;
+
+   debug("INTC: Initialization\n");
+
+   node = fdt_node_offset_by_compatible(blob, node,
+   "xlnx,xps-intc-1.00.a");
+   if (node != -1) {
+   fdt_addr_t base = fdtdec_get_addr(blob, node, "reg");
+   if (base == FDT_ADDR_T_NONE)
+   return -1;
+
+   debug("INTC: Base addr %lx\n", base);
+   intc = (microblaze_intc_t *)base;
+   irq_no = fdtdec_get_int(blob, node, "xlnx,num-intr-inputs", 0);
+   debug("INTC: IRQ NO %x\n", irq_no);
+   } else {
+   return node;
+   }
+#else
 #if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR;
irq_no = CONFIG_SYS_INTC_0_NUM;
 #endif
+#endif
if (irq_no) {
vecs = calloc(1, sizeof(struct irq_action) * irq_no);
if (vecs == NULL) {
diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c
index 3960bbb08a84..c0fc7c0f3ca1 100644
--- a/arch/microblaze/cpu/timer.c
+++ b/arch/microblaze/cpu/timer.c
@@ -7,9 +7,12 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 volatile int timestamp = 0;
 microblaze_timer_t *tmr;
 
@@ -29,8 +32,10 @@ void __udelay(unsigned long usec)
while ((get_timer(0) - i) < (usec / 1000))
;
} else {
+#ifndef CONFIG_OF_CONTROL
for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 1000); i++)
;
+#endif
}
 }
 
@@ -47,12 +52,44 @@ int timer_init (void)
u32 preload = 0;
u32 ret = 0;
 
+#ifdef CONFIG_OF_CONTROL
+   const void *blob = gd->fdt_blob;
+   int node = 0;
+   u32 cell[2];
+
+   debug("TIMER: Initialization\n");
+
+   node = fdt_node_offset_by_compatible(blob, node,
+   "xlnx,xps-timer-1.00.a");
+   if (node != -1) {
+   fdt_addr_t base = fdtdec_get_addr(blob, node, "reg");
+   if (base == FDT_ADDR_T_NONE)
+   return -1;
+
+   debug("TIMER: Base addr %lx\n", base);
+   tmr = (microblaze_timer_t *)base;
+
+   ret = fdtdec_get_int_array(blob, node, "interrupts",
+   cell, ARRAY_SIZE(cell));
+   if (ret)
+   return ret;
+
+   irq = cell[0];
+   debug("TIMER: IRQ %x\n", irq);
+
+   preload = fdtdec_get_int(blob, node, "clock-frequency", 0);
+   preload /= CONFIG_SYS_HZ;
+   } else {
+   return node;
+   }
+
+#else
 #if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ;
irq = CONFIG_SYS_TIMER_0_IRQ;
tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
 #endif
-
+#endif
if (tmr && preload && irq >= 0) {
tmr->loadreg = preload;
tmr->control = TIMER_INTERRUPT | TIMER_RESET;
-- 
1.9.1

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[U-Boot] [PATCH] ARM: zynq: Fix default ps7_init_gpl.c/h for ZYBO

[Michal Simek]

From: Michal Simek 

There is incorrect setting for USB which didn't work with origin
ps7_init_gpl.X files.
Use default setting for Digilent Zybo projects with HDMI in PL.

Signed-off-by: Michal Simek 
Signed-off-by: Michal Simek 
---

 board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c | 1581 +
 board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h |9 +-
 2 files changed, 1344 insertions(+), 246 deletions(-)

diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c 
b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
index 2c0fecac43f3..83daf7bf15b8 100644
--- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
@@ -310,11 +310,11 @@ unsigned long ps7_clock_init_data_3_0[] = {
/* .. SRCSEL = 0x0 */
/* .. ==> 0XF8000154[5:4] = 0xU */
/* .. ==> MASK : 0x0030UVAL : 0xU */
-   /* .. DIVISOR = 0x14 */
-   /* .. ==> 0XF8000154[13:8] = 0x0014U */
-   /* .. ==> MASK : 0x3F00UVAL : 0x1400U */
+   /* .. DIVISOR = 0xa */
+   /* .. ==> 0XF8000154[13:8] = 0x000AU */
+   /* .. ==> MASK : 0x3F00UVAL : 0x0A00U */
/* .. */
-   EMIT_MASKWRITE(0XF8000154, 0x3F33U, 0x1402U),
+   EMIT_MASKWRITE(0XF8000154, 0x3F33U, 0x0A02U),
/* .. .. START: TRACE CLOCK */
/* .. .. FINISH: TRACE CLOCK */
/* .. .. CLKACT = 0x1 */
@@ -339,39 +339,39 @@ unsigned long ps7_clock_init_data_3_0[] = {
/* .. .. ==> MASK : 0x03F0UVAL : 0x0010U */
/* .. .. */
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
-   /* .. .. SRCSEL = 0x3 */
-   /* .. .. ==> 0XF8000180[5:4] = 0x0003U */
-   /* .. .. ==> MASK : 0x0030UVAL : 0x0030U */
-   /* .. .. DIVISOR0 = 0x6 */
-   /* .. .. ==> 0XF8000180[13:8] = 0x0006U */
-   /* .. .. ==> MASK : 0x3F00UVAL : 0x0600U */
+   /* .. .. SRCSEL = 0x0 */
+   /* .. .. ==> 0XF8000180[5:4] = 0xU */
+   /* .. .. ==> MASK : 0x0030UVAL : 0xU */
+   /* .. .. DIVISOR0 = 0x7 */
+   /* .. .. ==> 0XF8000180[13:8] = 0x0007U */
+   /* .. .. ==> MASK : 0x3F00UVAL : 0x0700U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF8000180[25:20] = 0x0001U */
/* .. .. ==> MASK : 0x03F0UVAL : 0x0010U */
/* .. .. */
-   EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
-   /* .. .. SRCSEL = 0x2 */
-   /* .. .. ==> 0XF8000190[5:4] = 0x0002U */
-   /* .. .. ==> MASK : 0x0030UVAL : 0x0020U */
-   /* .. .. DIVISOR0 = 0x35 */
-   /* .. .. ==> 0XF8000190[13:8] = 0x0035U */
-   /* .. .. ==> MASK : 0x3F00UVAL : 0x3500U */
-   /* .. .. DIVISOR1 = 0x2 */
-   /* .. .. ==> 0XF8000190[25:20] = 0x0002U */
-   /* .. .. ==> MASK : 0x03F0UVAL : 0x0020U */
-   /* .. .. */
-   EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+   EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+   /* .. .. SRCSEL = 0x0 */
+   /* .. .. ==> 0XF8000190[5:4] = 0xU */
+   /* .. .. ==> MASK : 0x0030UVAL : 0xU */
+   /* .. .. DIVISOR0 = 0x5 */
+   /* .. .. ==> 0XF8000190[13:8] = 0x0005U */
+   /* .. .. ==> MASK : 0x3F00UVAL : 0x0500U */
+   /* .. .. DIVISOR1 = 0x1 */
+   /* .. .. ==> 0XF8000190[25:20] = 0x0001U */
+   /* .. .. ==> MASK : 0x03F0UVAL : 0x0010U */
+   /* .. .. */
+   EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
/* .. .. SRCSEL = 0x0 */
/* .. .. ==> 0XF80001A0[5:4] = 0xU */
/* .. .. ==> MASK : 0x0030UVAL : 0xU */
-   /* .. .. DIVISOR0 = 0xa */
-   /* .. .. ==> 0XF80001A0[13:8] = 0x000AU */
-   /* .. .. ==> MASK : 0x3F00UVAL : 0x0A00U */
+   /* .. .. DIVISOR0 = 0x14 */
+   /* .. .. ==> 0XF80001A0[13:8] = 0x0014U */
+   /* .. .. ==> MASK : 0x3F00UVAL : 0x1400U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF80001A0[25:20] = 0x0001U */
/* .. .. ==> MASK : 0x03F0UVAL : 0x0010U */
/* .. .. */
-   EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+   EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
/* .. .. CLK_621_TRUE = 0x1 */
/* .. .. ==> 0XF80001C4[0:0] = 0x0001U */
/* .. .. ==> MASK : 0x0001UVAL : 0x0001U */
@@ -667,9 +667,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
/* .. .. reg_ddrc_burst_rdwr = 0x4 */
/* .. .. ==> 0XF8006034[3:0] = 0x0004U */
/* .. .. ==> MASK : 0x000FUVAL : 0x0004U */
-   /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
-   

[U-Boot] [PATCH] test/py: Add support for loading image via tftp to specified location

[Michal Simek]

For example this setting:

env__net_tftp_readable_file = {
"fn": "ep108/image.ub",
"addr": "0x1000",
"size": 25846296,
"crc32": "b726f9de",
}

Signed-off-by: Michal Simek 
---

 test/py/tests/test_net.py | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index 07393eb1fdf8..4c578273aee3 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -135,7 +135,12 @@ def test_net_tftpboot(u_boot_console):
 if not f:
 pytest.skip('No TFTP readable file to read')
 
-addr = u_boot_utils.find_ram_base(u_boot_console)
+addr = f.get('addr', None)
+if addr:
+addr = int(addr,16)
+else:
+addr = u_boot_utils.find_ram_base(u_boot_console)
+
 fn = f['fn']
 output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
 expected_text = 'Bytes transferred = '
-- 
1.9.1

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[U-Boot] [PATCH] ARM: zynq: zybo: Enabling reading MAC address from EEPROM

[Michal Simek]

From: Michal Simek 

Zybo has on board I2C EEPROM which contains preprogrammed MAC address.

Signed-off-by: Michal Simek 
Signed-off-by: Michal Simek 
---

 include/configs/zynq_zybo.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h
index 0882fe36bd82..637b1c5ffe91 100644
--- a/include/configs/zynq_zybo.h
+++ b/include/configs/zynq_zybo.h
@@ -17,6 +17,9 @@
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_I2C1
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR0x50
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA
 #define CONFIG_DISPLAY
 #define CONFIG_I2C_EDID
 
-- 
1.9.1

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