[U-Boot] [PATCH 1/3 v2] fsl/ddr: Revise erratum a009942 and clean related erratum

[Shengzhou Liu]

- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu 
---
v2: fix a typo

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   |   7 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |   6 +-
 arch/powerpc/include/asm/config_mpc85xx.h |   2 -
 board/freescale/ls1021aqds/ls1021aqds.c   |   6 +-
 drivers/ddr/fsl/ctrl_regs.c   | 104 +-
 drivers/ddr/fsl/fsl_ddr_gen4.c|  23 ---
 drivers/ddr/fsl/mpc85xx_ddr_gen3.c|   3 -
 include/fsl_ddr.h |   2 +
 include/fsl_ddr_sdram.h   |   3 +-
 9 files changed, 121 insertions(+), 35 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index b7a2e0c..19de15e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -25,6 +25,9 @@
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
 #endif
+#ifdef CONFIG_SYS_FSL_DDR
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -400,7 +403,9 @@ int arch_early_init_r(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
erratum_a009635();
 #endif
-
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
+   erratum_a009942_check_cpo();
+#endif
 #ifdef CONFIG_MP
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
/* Check the psci version to determine if the psci is supported */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 53b3729..c1dbd9c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -45,7 +45,7 @@
 #include 
 #include 
 #endif
-
+#include 
 #include "../../../../drivers/block/fsl_sata.h"
 #ifdef CONFIG_U_QE
 #include 
@@ -947,6 +947,10 @@ int cpu_init_r(void)
 
 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+   erratum_a009942_check_cpo();
+#endif
+
 #ifdef CONFIG_FMAN_ENET
fman_enet_init();
 #endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 6d845e8..1e62a9c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -681,7 +681,6 @@
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186
@@ -720,7 +719,6 @@
 #define CONFIG_SYS_FSL_TBCLK_DIV   16
 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index 4eb38a7..79078d2 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -22,7 +22,7 @@
 #include 
 #include 
 #include 
-
+#include 
 #include "../common/sleep.h"
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
@@ -433,7 +433,9 @@ int board_init(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
 #endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+   erratum_a009942_check_cpo();
+#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 24fd366..656de2c 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -5,14 +5,14 @@
  */
 
 /*
- * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
+ * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
  * Based on code from spd_sdram.c
  * Author: James Yang [at freescale.com]
  */
 
 #include 
 #include 
-
+#include 
 #include 
 #include 
 #include 
@@ -2305,6 +2305,9 @@ compute_fsl_memctl_config_regs(const unsigned int 
ctrl_num,
unsigned int wrlvl_en;
unsigned int ip_rev = 0;
unsigned int unq_mrs_en = 0;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+   unsigned int ddr_freq;
+#endif
int cs_en = 1;
 
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
@@ -2526,5 +2529,102 @@ compute_fsl_memctl_config_regs(const unsigned int 
ctrl_num,
ddr->debug[2] |= 0x0200;/* set bit 22 */
 #endif
 
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) 

Re: [U-Boot] [PATCH v2 1/1] cmd: pci: add option to parse and display BAR information

[Stefan Roese]

On 06.11.2016 15:31, yehu...@marvell.com wrote:
> From: Yehuda Yitschak 
> 
> Currently the PCI command only allows to see the BAR register
> values but not the size and actual base address.
> This little extension parses the BAR registers and displays
> the base, size and type of each BAR.
> 
> Signed-off-by: Yehuda Yitschak 

I've tested this patch on a DM based PCI driver. And it looks 
good so far:

=> pci bar 0.0.0  
ID   BaseSizeWidth  Type
--
 0   0xf900  0x0010  32 MEM   
=> pci bar 0.0.1
No such device
=> pci bar 1.0.0
ID   BaseSizeWidth  Type
--
 0   0xf800  0x0002  32 MEM   
 1   0xf802  0x0002  32 MEM   
 2   0xffe0  0x0020  32 I/O 

So:

Tested-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/3] fsl/ddr: Revise erratum a009942 and clean related erratum

[Shengzhou Liu]

> -Original Message-
> From: york sun
> Sent: Friday, November 04, 2016 11:20 PM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/3] fsl/ddr: Revise erratum a009942 and clean related
> erratum
> 
> On 11/04/2016 04:18 AM, Shengzhou Liu wrote:
> > - add additional function erratum_a009942_check_cpo to check if the
> >   board needs tuning CPO calibration for optimal setting.
> > - move ERRATUM_A009942(with revision to check cpo_sample option)
> from
> >   fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
> > - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
> > - remove obsolete ERRATUM_A004934 which is replaced with
> ERRATUM_A009942.
> 
> Shengzhou,
> 
> There is an issue for moving the erratum 9942 workaround to ctrl_regs.c.
> This workaround requires setting debug register in a read-modify-write
> fashion. You won't be able to read the debug register in ctrl_regs.c file.
> 
> York

York,

This change(moving to ctrl_regs.c) has the same effect as 
read-modify-write(done in fsl_ddr_gen4.c) before MEM_EN is enabled for DDRC.
As I commented in code with "the POR value of debug_29 register is zero" for 
A009942 workaround when moving it to ctrl_regs.c,
Actually only A008378 changes debug_29[8:11] bits to 9 from original POR value 
0  before the implementing of A009942, and A009942 overrides debug_29[8:11] set 
by A008378.
So we can set debug_29 in ctrl_regs.c, it doesn't break anything.

-Shengzhou

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[U-Boot] [PATCH v3 4/5] ARMv8: Setup PSCI memory and device tree

[macro . wave . z]

From: Hongbo Zhang 

The newly added ARMv8 PSCI needs to be initialized, be copied or reserved in
right place, this patch does all the setup steps.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/cpu-dt.c   |  8 
 arch/arm/cpu/armv8/cpu.c  | 22 ++
 arch/arm/include/asm/secure.h |  2 +-
 arch/arm/include/asm/system.h | 11 +++
 arch/arm/lib/bootm.c  |  3 +++
 arch/arm/lib/psci-dt.c|  2 +-
 6 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 9ffb49c..f227a10 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
 #endif
@@ -25,6 +26,13 @@ int psci_update_dt(void *fdt)
return 0;
 #endif
fdt_psci(fdt);
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+   /* secure code lives in RAM, keep it alive */
+   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+   __secure_end - __secure_start);
+#endif
+
 #endif
 #endif
return 0;
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index e06c3cc..5dcb5e2 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 int cleanup_before_linux(void)
@@ -41,3 +42,24 @@ int cleanup_before_linux(void)
 
return 0;
 }
+
+#ifdef CONFIG_ARMV8_PSCI
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+   size_t sz = __secure_end - __secure_start;
+
+   memcpy((void *)CONFIG_ARMV8_SECURE_BASE, __secure_start, sz);
+   flush_dcache_range(CONFIG_ARMV8_SECURE_BASE,
+  CONFIG_ARMV8_SECURE_BASE + sz + 1);
+   invalidate_icache_all();
+#endif
+}
+
+void armv8_setup_psci(void)
+{
+   relocate_secure_section();
+   secure_ram_addr(psci_setup_vectors)();
+   secure_ram_addr(psci_arch_init)();
+}
+#endif
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 5a403bc..d23044a 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,7 +6,7 @@
 #define __secure __attribute__ ((section ("._secure.text")))
 #define __secure_data __attribute__ ((section ("._secure.data")))
 
-#ifdef CONFIG_ARMV7_SECURE_BASE
+#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
 /*
  * Warning, horror ahead.
  *
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index b928bd8..9064e6b 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -118,6 +118,17 @@ void smc_call(struct pt_regs *args);
 void __noreturn psci_system_reset(void);
 void __noreturn psci_system_off(void);
 
+#ifdef CONFIG_ARMV8_PSCI
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+void armv8_setup_psci(void);
+void psci_setup_vectors(void);
+void psci_arch_init(void);
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #else /* CONFIG_ARM64 */
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 53c3141..9fe1a5f 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -291,6 +291,9 @@ static void boot_jump_linux(bootm_headers_t *images, int 
flag)
announce_and_cleanup(fake);
 
if (!fake) {
+#ifdef CONFIG_ARMV8_PSCI
+   armv8_setup_psci();
+#endif
do_nonsec_virt_switch();
kernel_entry(images->ft_addr, NULL, NULL, NULL);
}
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index baf6d70..a70f3d3 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -65,7 +65,7 @@ int fdt_psci(void *fdt)
 init_psci_node:
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
psci_ver = sec_firmware_support_psci_version();
-#elif defined(CONFIG_ARMV7_PSCI_1_0)
+#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
 #endif
switch (psci_ver) {
-- 
2.1.4

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[U-Boot] [PATCH v3 5/5] ARMv8: LS1043A: Enable LS1043A default PSCI support

[macro . wave . z]

From: Hongbo Zhang 

A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile   |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 
 board/freescale/ls1043ardb/Kconfig   |  9 +
 configs/ls1043ardb_defconfig |  3 +++
 4 files changed, 33 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 51c1cee..423b4b3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,6 +28,7 @@ endif
 
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
 endif
 
 ifneq ($(CONFIG_ARCH_LS1012A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
new file mode 100644
index 000..86045ac
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include 
+#include 
+#include 
+
+   .pushsection ._secure.text, "ax"
+
+.globl psci_version
+psci_version:
+   ldr w0, =0x0001 /* PSCI v1.0 */
+   ret
+
+   .popsection
diff --git a/board/freescale/ls1043ardb/Kconfig 
b/board/freescale/ls1043ardb/Kconfig
index 51818ec..0c596f9 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -13,4 +13,13 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1043ardb"
 
+config SYS_HAS_ARMV8_SECURE_BASE
+   bool "Enable secure RAM for PSCI image"
+   depends on ARMV8_PSCI
+   default y
+   help
+ PSCI image can be re-located to secure RAM.
+ If enabled, please also define the value for ARMV8_SECURE_BASE,
+ for LS1043ARDB, it is address in OCRAM.
+
 endif
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 79a4eb2..cb189f3 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -28,3 +28,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_ARMV8_PSCI=y
+CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
+CONFIG_ARMV8_SECURE_BASE=0x1001
-- 
2.1.4

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[U-Boot] [PATCH v3 2/5] ARMv8: Add secure sections for PSCI text and data

[macro . wave . z]

From: Hongbo Zhang 

This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.

Signed-off-by: Hongbo Zhang 
Reviewed-by: Tom Rini 
---
 arch/arm/config.mk|  3 ++-
 arch/arm/cpu/armv8/Kconfig| 31 +++
 arch/arm/cpu/armv8/u-boot.lds | 57 +++
 3 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 542b897..112e334 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -118,7 +118,8 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+   -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index cd2d9bb..f2a43b8 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -39,4 +39,35 @@ config PSCI_RESET
 
  Select Y here to make use of PSCI calls for system reset
 
+config ARMV8_PSCI
+   bool "Enable PSCI support" if EXPERT
+   default n
+   help
+ PSCI is Power State Coordination Interface defined by ARM.
+ The PSCI in U-boot provides a general framework and each platform
+ can implement their own specific PSCI functions.
+ Say Y here to enable PSCI support on ARMv8 platform.
+
+config ARMV8_PSCI_NR_CPUS
+   int "Maximum supported CPUs for PSCI"
+   depends on ARMV8_PSCI
+   default 4
+   help
+ The maximum number of CPUs supported in the PSCI firmware.
+ It is no problem to set a larger value than the number of CPUs in
+ the actual hardware implementation.
+
+if SYS_HAS_ARMV8_SECURE_BASE
+
+config ARMV8_SECURE_BASE
+   hex "Secure address for PSCI image"
+   depends on ARMV8_PSCI
+   help
+ Address for placing the PSCI text, data and stack sections.
+ If not defined, the PSCI sections are placed together with the u-boot
+ but platform can choose to place PSCI code image separately in other
+ places such as some secure RAM built-in SOC etc.
+
+endif
+
 endif
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fd15ad5..22195b8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -8,11 +8,17 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#include 
+#include 
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", 
"elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
 ENTRY(_start)
 SECTIONS
 {
+#ifdef CONFIG_ARMV8_SECURE_BASE
+   /DISCARD/ : { *(.rela._secure*) }
+#endif
. = 0x;
 
. = ALIGN(8);
@@ -23,6 +29,57 @@ SECTIONS
*(.text*)
}
 
+#ifdef CONFIG_ARMV8_PSCI
+   .__secure_start :
+#ifndef CONFIG_ARMV8_SECURE_BASE
+   ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+   {
+   KEEP(*(.__secure_start))
+   }
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_PSCI_STACK_IN_RAM
+#endif
+   .secure_text CONFIG_ARMV8_SECURE_BASE :
+   AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+   {
+   *(._secure.text)
+   }
+
+   .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+   {
+   *(._secure.data)
+   }
+
+   .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+   CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV8_PSCI_STACK_IN_RAM
+   AT(ADDR(.secure_stack))
+#else
+   AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+   {
+   KEEP(*(.__secure_stack_start))
+
+   . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+   . = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+   KEEP(*(.__secure_stack_end))
+   }
+
+#ifndef __ARMV8_PSCI_STACK_IN_RAM
+   . = LOADADDR(.secure_stack);
+#endif
+
+   .__secure_end : AT(ADDR(.__secure_end)) {
+   KEEP(*(.__secure_end))
+   LONG(0x1d1071c);/* Must output something to reset LMA */
+   }
+#endif
+
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
 
-- 
2.1.4

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[U-Boot] [PATCH v3 3/5] ARMv8: Add basic PSCI framework

[macro . wave . z]

From: Hongbo Zhang 

This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/Kconfig  |  10 ++
 arch/arm/cpu/armv8/Makefile |   1 +
 arch/arm/cpu/armv8/psci.S   | 286 
 arch/arm/include/asm/psci.h |  15 +++
 4 files changed, 312 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/psci.S

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index f2a43b8..173950d 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -57,6 +57,16 @@ config ARMV8_PSCI_NR_CPUS
  It is no problem to set a larger value than the number of CPUs in
  the actual hardware implementation.
 
+config ARMV8_PSCI_CPUS_PER_CLUSTER
+   int "Number of CPUs per cluster"
+   depends on ARMV8_PSCI
+   default 0
+   help
+ The number of CPUs per cluster, suppose each cluster has same number
+ of CPU cores, platforms with asymmetric clusters don't apply here.
+ A value 0 or no definition of it works for single cluster system.
+ System with multi-cluster should difine their own exact value.
+
 if SYS_HAS_ARMV8_SECURE_BASE
 
 config ARMV8_SECURE_BASE
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dea1465..28ba786 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
new file mode 100644
index 000..43d5d6b
--- /dev/null
+++ b/arch/arm/cpu/armv8/psci.S
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include 
+#include 
+#include 
+
+/* Default PSCI function, return -1, Not Implemented */
+#define PSCI_DEFAULT(__fn) \
+   ENTRY(__fn); \
+   mov w0, #ARM_PSCI_RET_NI; \
+   ret; \
+   ENDPROC(__fn); \
+   .weak __fn
+
+/* PSCI function and ID table definition*/
+#define PSCI_TABLE(__id, __fn) \
+   .word __id; \
+   .word __fn
+
+.pushsection ._secure.text, "ax"
+
+/* 32 bits PSCI default functions */
+PSCI_DEFAULT(psci_version)
+PSCI_DEFAULT(psci_cpu_suspend)
+PSCI_DEFAULT(psci_cpu_off)
+PSCI_DEFAULT(psci_cpu_on)
+PSCI_DEFAULT(psci_affinity_info)
+PSCI_DEFAULT(psci_migrate)
+PSCI_DEFAULT(psci_migrate_info_type)
+PSCI_DEFAULT(psci_migrate_info_up_cpu)
+PSCI_DEFAULT(psci_system_off)
+PSCI_DEFAULT(psci_system_reset)
+PSCI_DEFAULT(psci_features)
+PSCI_DEFAULT(psci_cpu_freeze)
+PSCI_DEFAULT(psci_cpu_default_suspend)
+PSCI_DEFAULT(psci_node_hw_state)
+PSCI_DEFAULT(psci_system_suspend)
+PSCI_DEFAULT(psci_set_suspend_mode)
+PSCI_DEFAULT(psi_stat_residency)
+PSCI_DEFAULT(psci_stat_count)
+
+.align 3
+_psci_32_table:
+PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
+PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
+PSCI_TABLE(0, 0)
+
+/* 64 bits PSCI default functions */
+PSCI_DEFAULT(psci_cpu_suspend_64)
+PSCI_DEFAULT(psci_cpu_on_64)
+PSCI_DEFAULT(psci_affinity_info_64)
+PSCI_DEFAULT(psci_migrate_64)
+PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
+PSCI_DEFAULT(psci_cpu_default_suspend_64)
+PSCI_DEFAULT(psci_node_hw_state_64)
+PSCI_DEFAULT(psci_system_suspend_64)
+PSCI_DEFAULT(psci_stat_residency_64)
+PSCI_DEFAULT(psci_stat_count_64)
+

[U-Boot] [PATCH v3 0/5] Add ARMv8 PSCI framework

[macro . wave . z]

From: Hongbo Zhang 

v2-v3 changes:
 - Drop the previous 1/6, since the previous CONFIG_ARMV8_PSCI in common parts
of codes also work for generic PSCI framework, so there are 5 patches in this
iteration.
 - Add "Reviewed-by: Tom Rini " for patches 1/5 and 2/5,
which were 2/6 and 3/6.
 - Move config values for ls1043 from armv8/Kconfig to s1043ardb_defconfig.

v1-v2 changes:
 - The new config options are introduced in Kconfig when used for first time
 - Introduce new config options in armv8/Kconfig instead of LS1043 platform
 - Move previous patch 5/6 to current 2/6 place

v1 notes:

This patch set introduces ARMv8 PSCI framework, all the PSCI functions are
implemented a default dummy one, it is up to each platform to implement their
own specific ones.

The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI.
Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up.
The last 6/6 adds a most simple implementation on NXP LS1043 platform, to
verify this framework.

This patch set mainly introduces ARMv8 PSCI framework, for easier review and
merge, further PSCI implementation on LS1043 is coming later.

Hongbo Zhang (5):
  ARMv8: Enable SMC instruction
  ARMv8: Add secure sections for PSCI text and data
  ARMv8: Add basic PSCI framework
  ARMv8: Setup PSCI memory and device tree
  ARMv8: LS1043A: Enable LS1043A default PSCI support

 arch/arm/config.mk   |   3 +-
 arch/arm/cpu/armv8/Kconfig   |  41 
 arch/arm/cpu/armv8/Makefile  |   1 +
 arch/arm/cpu/armv8/cpu-dt.c  |   8 +
 arch/arm/cpu/armv8/cpu.c |  22 ++
 arch/arm/cpu/armv8/fsl-layerscape/Makefile   |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S |  20 ++
 arch/arm/cpu/armv8/psci.S| 286 +++
 arch/arm/cpu/armv8/u-boot.lds|  57 +
 arch/arm/include/asm/macro.h |   2 +-
 arch/arm/include/asm/psci.h  |  15 ++
 arch/arm/include/asm/secure.h|   2 +-
 arch/arm/include/asm/system.h|  11 +
 arch/arm/lib/bootm.c |   3 +
 arch/arm/lib/psci-dt.c   |   2 +-
 board/freescale/ls1043ardb/Kconfig   |   9 +
 configs/ls1043ardb_defconfig |   3 +
 17 files changed, 482 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
 create mode 100644 arch/arm/cpu/armv8/psci.S

-- 
2.1.4

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[U-Boot] [PATCH v3 1/5] ARMv8: Enable SMC instruction

[macro . wave . z]

From: Hongbo Zhang 

PSCI implementation needs the SMC instruction to be enabled.
Following the legacy codes pattern, no bit macro definition and bit operation
are used, only the immediate data used in line is changed.

Signed-off-by: Hongbo Zhang 
Reviewed-by: Tom Rini 
---
 arch/arm/include/asm/macro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 9bb0efa..35ea002 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -137,7 +137,7 @@ lr  .reqx30
 
 .macro armv8_switch_to_el2_m, xreg1
/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
-   mov \xreg1, #0x5b1
+   mov \xreg1, #0x531
msr scr_el3, \xreg1
msr cptr_el3, xzr   /* Disable coprocessor traps to EL3 */
mov \xreg1, #0x33ff
-- 
2.1.4

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Re: [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

[Keerthy]

On Sunday 30 October 2016 05:30 PM, Marek Vasut wrote:

On 10/30/2016 02:59 AM, Keerthy wrote:



On Saturday 29 October 2016 11:19 PM, Marek Vasut wrote:

On 10/29/2016 07:47 PM, Tom Rini wrote:

On Sat, Oct 29, 2016 at 07:44:34PM +0200, Marek Vasut wrote:

On 10/29/2016 07:41 PM, Tom Rini wrote:

On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:


While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random
speculative
fetches in random memory regions which was eventually caught by
kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy 
Reviewed-by: Alexander Graf 


Reviewed-by: Tom Rini 


Isn't this patch exactly undoing the following one ?

commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
Author: Marek Vasut <>
Date:   Tue Dec 29 19:44:02 2015 +0100

arm: Remove S bit from MMU section entry

Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.


Is it?  I guess perhaps you and Keerthy need to chat then as there's
some other problem they're addressing.


U, wait a second, I think this one adds XN bit and the previous one
removed S bit. I think I was wrong, but please double-check this. I
recall we had some odd cache issues on V7 back then.


Marek,

First and foremost if we git blame on the file:
arch/arm/include/asm/system.h

your commit:
8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc

arm: Remove S bit from MMU section entry

It is removing S bit under
#elif defined(CONFIG_CPU_V7)

I am adding the missing XN bit under:
#ifdef CONFIG_ARMV7_LPAE

So we are dealing with different modes.

In a nutshell your patch removes S bit from MMU section entry for
non-LPAE cases for ARMV7 and mine adds XN bit for LPAE cases.

Hope this clears out the confusion.


Yeah, it does, thanks.



I hope this patch can be pulled if there are no further concerns.

Thanks,
Keerthy
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Re: [U-Boot] Rockchip USB driver

[Simon Glass]

Hi Kever,

On 3 November 2016 at 18:56, Kever Yang  wrote:
> Hi Doug,
>
> Do you mean usb gadget driver or usb host driver?

I mean USB host.

>
> The usb controller for rk3288 is very similar to rk3036, I though the driver
> are working on upstream.
> Let me double check.

OK, thanks. I don't see it.

- Simon

>
> Thanks,
> - Kever
>
> On 11/02/2016 09:04 AM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> Do you have a USB driver for RK3288 that you could upstream please?
>>
>> Regards,
>> Simon
>>
>
>
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Re: [U-Boot] [PATCH v7 1/2] armv8: Support loading 32-bit OS in AArch32 execution state

[Alison Wang]

> On 11/04/2016 10:12 AM, Alexander Graf wrote:
> >
> >
> > On 04/11/2016 17:08, york sun wrote:
> >> On 11/04/2016 09:53 AM, Alexander Graf wrote:
> >>>
> >>>
> >>> On 04/11/2016 16:43, york sun wrote:
>  On 11/04/2016 09:32 AM, Ryan Harkin wrote:
> >>>
> >>> Yes, with the attached patch on top of your original 2 patches,
> >>> everything works again.  I tested on FVP Foundation and AEMv8
> >>> models and Juno R0, R1 and R2.
> >>>
> >>> I don't think it would be good to stack these three patches the
> >>> way they are presented in the upstream tree because it would
> not
> >>> be bisect-able.  Some re-work or re-ordering would be needed.
> >>>
> >>> Note: I haven't attempted to understand what any of this code
> is
> >>> doing, I'm just testing it with my standard boot flow to make
> >>> sure nothing is broken for me.
> >>
> >> Ryan,
> >>
> >> I support Alison's patch order for her 32-bit patch sets. This
> >> feature doesn't exist before her first set. It is functional if
> >> you run U-Boot at EL3 after the first patch.
> >
> > Which I don't do.  I follow the boot flow recommended by ARM and
> > it doesn't work for that setup, which I don't think is the right
> > thing to do.
> >
> >
> >> It gets EL2 working after the 2nd set. If there is room to
> >> clarify in the commit message, please kindly suggest.
> >>
> >
> > Well, I'm not the maintainer of the tree, but I wouldn't want to
> > have a tree that wasn't bootable at any point in the patch
> sequence.
> > That's generally unacceptable on most projects I work on.
> Keeping
> > the tree bisect-able to prove which commit caused a problem is
> > considered to be a valuable tool.
> >
> 
>  Ryan,
> 
>  Thanks for sharing your concern. I support git-bisect. It is
>  valuable, no doubt. Let me try to understand the issue here.
>  Without Alison's patches, everything boots OK. With her first set,
> does something break?
> >>>
> >>> Yes, with the patches booting 64bit Linux with U-Boot running in
> EL2
> >>> breaks according to Ryan.
> >>>
>  My understanding is 32-bit OS can boot. If existing 64-bit OS
>  fails, then she needs to fix it.
> >>>
> >>> That's his point :). And I concur.
> >>
> >> Thanks for the confirmation.
> >>
> >>>
> >>> (btw, you guys really should start thinking about following the ARM
> >>> recommended boot model. It's pretty cumbersome to do everything
> >>> different just for NXP)
> >>
> >> If you are referring the trusted firmware, we are following that
> >> direction. Just not fully up yet on some platform.
> >>
> >> It is definitely not our intention to be cumbersome. Please point
> out
> >> where it went sideway beside the trusted firmware.
> >
> > Basically it boils down to the fact that you are the only platform
> > that runs U-Boot in EL3 :).
> >
> > If you want to keep the memory initialization inside of U-Boot, I
> > think that's great. But you could either split that into SPL/EL2 or
> > degrade yourself into EL2 as soon as possible by calling into an EL3
> firmware.
> > Whether you build that firmware as part of U-Boot (the stock one
> could
> > be very trivial) or externally is not really too much of a problem.
> >
> > Things like Alison's patches could then do a simple PSCI call into
> > said
> > EL3 firmware to call into 32bit code in EL2 for example.
> >
> 
> Basically I agree with you. U-Boot will run at EL2 as soon as we have
> the trusted firmware in place.
> 
[Alison Wang] Thanks for all your comments.

For the issue about the tree would not be bisect-able, I have
a solution. Actually it is the root cause that 64-bit kernel could not boot
up when U-Boot is running in EL2. I will move these codes from the third patch
to the first patch.

ENTRY(armv8_switch_to_el2)
switch_el x5, 1f, 0f, 0f
-0: ret
+   /*
+* x3 is kernel entry point or switch_to_el1
+ * if CONFIG_ARMV8_SWITCH_TO_EL1 is defined.
+ * When running in EL2 now, jump to the
+ * address saved in x3.
+*/
+0: br x3
 1: armv8_switch_to_el2_m x3, x4, x5
 ENDPROC(armv8_switch_to_el2)

 ENTRY(armv8_switch_to_el1)
  switch_el x5, 0f, 1f, 0f
-0: ret
+
+   /*
+ * x3 is kernel entry point. When running in EL1
+ * now, jump to the address saved in x3.
+*/
+0: br x3
 1: armv8_switch_to_el1_m x3, x4, x5
 ENDPROC(armv8_switch_to_el1)

With this re-order, the bitsect issue will be fixed and there is not a point
that kernel could not boot up.

If you all agree with this re-order, I will send out the v8 patch includes the
first, second and third patches.


Best Regards,
Alison Wang
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Re: [U-Boot] [PATCH 2/4] mmc: sunxi: Enable 8bits bus width for sun8i

[Chen-Yu Tsai]

On Mon, Nov 7, 2016 at 1:15 AM, Maxime Ripard
 wrote:
> On Sat, Nov 05, 2016 at 09:34:25AM +0800, Chen-Yu Tsai wrote:
>> On Fri, Nov 4, 2016 at 11:18 PM, Maxime Ripard
>>  wrote:
>> > The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the
>> > support for those too.
>> >
>> > Signed-off-by: Maxime Ripard 
>> > ---
>> >  drivers/mmc/sunxi_mmc.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
>> > index 6953accce123..b8716c93cb06 100644
>> > --- a/drivers/mmc/sunxi_mmc.c
>> > +++ b/drivers/mmc/sunxi_mmc.c
>> > @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>> >
>> > cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
>> > cfg->host_caps = MMC_MODE_4BIT;
>> > -#ifdef CONFIG_MACH_SUN50I
>> > +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
>>
>> 8 come before 50. :)
>
> But 5 comes before 8, and 0 before i :)

Indeed, though 8 and 50 are akin to a generation number, so
it makes sense to sort them in natural order. :)

ChenYu

>
>> Otherwise,
>>
>> Reviewed-by: Chen-Yu Tsai 
>
> Thanks,
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
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Re: [U-Boot] travis-ci: Try harder to build all ARM targets

[Tom Rini]

On Sat, Nov 05, 2016 at 07:34:49PM -0400, Tom Rini wrote:

> The way that we have things broken down currently allows for some
> combinations of vendor or CPU to not be built.  To fix this, create a
> new catch-all job that excludes everything we've built elsewhere.  For
> the sake of simplicity we are allowing for the possibility of some
> overlap between the vendor-based jobs and the CPU-based jobs.  While
> we're in here, make a failed build provide the summary of failure.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] buildman: Fix building based on 'options' field

[Tom Rini]

On Fri, Nov 04, 2016 at 10:59:45PM -0400, Tom Rini wrote:

> The README for buildman says that we can use any field in boards.cfg to
> decide what to build.  However, we were not saving the options field
> correctly.
> 
> Cc: Simon Glass 
> Signed-off-by: Tom Rini 
> Acked-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] mkimage: Allow including a ramdisk in FIT auto mode

[Tom Rini]

On Fri, Nov 04, 2016 at 02:22:15PM +0100, Tomeu Vizoso wrote:

> Adds -i option that allows specifying a ramdisk file to be added to the
> FIT image when we are using the automatic FIT mode (no ITS file).
> 
> This makes adding Depthcharge support to LAVA much more convenient, as
> no additional configuration files need to be kept around in the machine
> that dispatches jobs to the boards.
> 
> Signed-off-by: Tomeu Vizoso 
> Cc: Simon Glass 
> Cc: Matt Hart 
> Cc: Neil Williams 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] wandboard: Make Ethernet functional again

[Tom Rini]

On Tue, Nov 01, 2016 at 02:58:16PM -0200, Fabio Estevam wrote:

> Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate
> config for AR8031") ethernet does not work on mx6sabresd.
> 
> This commit correctly assigns ar8031_config() as the configuration
> function for AR8031 in the same way as done in the Linux kernel.
> 
> However, on wandboard design we need some additional configuration,
> such as enabling the 125 MHz AR8031 output that needs to be done
> in the board file.
> 
> This also aligns with the same method that the kernel performs
> the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c.
> 
> Signed-off-by: Fabio Estevam 
> Acked-by: Joe Hershberger 

Applied to u-boot/master, thanks!

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Re: [U-Boot] tools: imximage: check return value when open the plugin file

[Tom Rini]

On Fri, Nov 04, 2016 at 10:33:15AM +0800, Peng Fan wrote:

> Check return value when open the plugin file.
> 
> Coverity report:
> ** CID 153926:  Error handling issues  (NEGATIVE_RETURNS)
> /tools/imximage.c: 542 in copy_plugin_code()
> 
>ifd = open(plugin_file, O_RDONLY|O_BINARY);
> >>>  CID 153926:  Error handling issues  (NEGATIVE_RETURNS)
> >>> "ifd" is passed to a parameter that cannot be negative.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Tom Rini 
> Reported-by: Coverity (CID: 153926)
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] doc: update README.arm64

[Tom Rini]

On Thu, Nov 03, 2016 at 01:01:50AM +, Andre Przywara wrote:

> This file apparently hasn't seen an update in a while, so just sync
> it with reality.
> 
> Signed-off-by: Andre Przywara 

Applied to u-boot/master, thanks!

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Re: [U-Boot] armv8: define get_ticks() for the ARMv8 Generic Timer

[Tom Rini]

On Thu, Nov 03, 2016 at 12:56:25AM +, Andre Przywara wrote:

> For 64-bit ARM systems we provide just a timer_read_counter()
> implementation and rely on the generic non-uclass get_ticks() function
> in lib/time.c to call the former.
> However this function is actually not 64-bit safe, as it assumes a
> "long" to be 32-bit. Beside the fact that the resulting uint64_t
> isn't bigger than "long" on 64-bit architectures and thus combining two
> counters makes no sense, we get all kind of weird results when we try
> to OR in the high value shifted by _32_ bits.
> So let's avoid that function at all and provide a straight forward
> get_ticks() implementation for ARMv8, which also is in line with ARMv7.
> 
> This fixes occasional immediate time-out expiration issues I see on the
> Pine64 board. The root cause of this needs to be investigated, but this
> fix looks like the right thing anyway.
> 
> Signed-off-by: Andre Przywara 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v4, 2/2] image: Protect against overflow in unknown_msg()

[Tom Rini]

On Mon, Oct 31, 2016 at 10:21:09AM -0600, Simon Glass wrote:

> Coverity complains that this can overflow. If we later increase the size
> of one of the strings in the table, it could happen.
> 
> Adjust the code to protect against this.
> 
> Signed-off-by: Simon Glass 
> Reported-by: Coverity (CID: 150964)

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 3/4] colibri_pxa270: drop lzma support for space reason

[Tom Rini]

On Fri, Oct 28, 2016 at 10:50:23PM +0200, Marcel Ziswiler wrote:

> As the upcoming driver model integration takes up some more precious flash
> space first make sure to drop expensive LZMA support.
> 
> Signed-off-by: Marcel Ziswiler 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 1/1] ARM: ts4600: add basic board support

[Fabio Estevam]

Hi Sebastien,

On Thu, Nov 3, 2016 at 5:20 PM, Sebastien Bourdelin
 wrote:

> +/* Extra Environment */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +   "fdt_addr=0x4100\0" \
> +   "loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \
> +   "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ts4600.dtb\0" \

Not related to this patch: do you plan to submit ts4600.dts for
mainline inclusion as well?

Regards,

Fabio Estevam
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[U-Boot] [PATCH v2 1/2] ext4: Allow reading files with non-zero offset, clamp read len

[Stefan Brüns]

Support was already implemented, but not hooked up. This fixes several
fails in the test cases.

Signed-off-by: Stefan Brüns 
---
v2:
 - update ext4fs_read(...) calls from spl_ext.c
 - move clamping to ext4fs_read_file(...), i.e. correct the check
   for offset != 0

 common/spl/spl_ext.c |  8 
 fs/ext4/ext4fs.c | 17 ++---
 include/ext4fs.h |  2 +-
 3 files changed, 11 insertions(+), 16 deletions(-)

diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index b93e1ea..1b8e15e 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -42,7 +42,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
puts("spl: ext4fs_open failed\n");
goto end;
}
-   err = ext4fs_read((char *)header, sizeof(struct image_header), );
+   err = ext4fs_read((char *)header, 0, sizeof(struct image_header), 
);
if (err < 0) {
puts("spl: ext4fs_read failed\n");
goto end;
@@ -54,7 +54,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
goto end;
}
 
-   err = ext4fs_read((char *)spl_image->load_addr, filelen, );
+   err = ext4fs_read((char *)spl_image->load_addr, 0, filelen, );
 
 end:
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -97,7 +97,7 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image,
puts("spl: ext4fs_open failed\n");
goto defaults;
}
-   err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, 
);
+   err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, filelen, 
);
if (err < 0) {
printf("spl: error reading image %s, err - %d, falling 
back to default\n",
   file, err);
@@ -127,7 +127,7 @@ defaults:
if (err < 0)
puts("spl: ext4fs_open failed\n");
 
-   err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, );
+   err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, filelen, 
);
if (err < 0) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 3078737..7187dcf 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -65,8 +65,8 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
short status;
 
/* Adjust len so it we can't read past the end of the file. */
-   if (len > filesize)
-   len = filesize;
+   if (len + pos > filesize)
+   len = (filesize - pos);
 
blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize);
 
@@ -190,12 +190,12 @@ int ext4fs_size(const char *filename, loff_t *size)
return ext4fs_open(filename, size);
 }
 
-int ext4fs_read(char *buf, loff_t len, loff_t *actread)
+int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread)
 {
if (ext4fs_root == NULL || ext4fs_file == NULL)
-   return 0;
+   return -1;
 
-   return ext4fs_read_file(ext4fs_file, 0, len, buf, actread);
+   return ext4fs_read_file(ext4fs_file, offset, len, buf, actread);
 }
 
 int ext4fs_probe(struct blk_desc *fs_dev_desc,
@@ -217,11 +217,6 @@ int ext4_read_file(const char *filename, void *buf, loff_t 
offset, loff_t len,
loff_t file_len;
int ret;
 
-   if (offset != 0) {
-   printf("** Cannot support non-zero offset **\n");
-   return -1;
-   }
-
ret = ext4fs_open(filename, _len);
if (ret < 0) {
printf("** File not found %s **\n", filename);
@@ -231,7 +226,7 @@ int ext4_read_file(const char *filename, void *buf, loff_t 
offset, loff_t len,
if (len == 0)
len = file_len;
 
-   return ext4fs_read(buf, len, len_read);
+   return ext4fs_read(buf, offset, len, len_read);
 }
 
 int ext4fs_uuid(char *uuid_str)
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 965cd9e..bb55639 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -135,7 +135,7 @@ int ext4_write_file(const char *filename, void *buf, loff_t 
offset, loff_t len,
 
 struct ext_filesystem *get_fs(void);
 int ext4fs_open(const char *filename, loff_t *len);
-int ext4fs_read(char *buf, loff_t len, loff_t *actread);
+int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread);
 int ext4fs_mount(unsigned part_length);
 void ext4fs_close(void);
 void ext4fs_reinit_global(void);
-- 
2.10.1

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Re: [U-Boot] [PATCH 2/4] mmc: sunxi: Enable 8bits bus width for sun8i

[Maxime Ripard]

On Sat, Nov 05, 2016 at 09:34:25AM +0800, Chen-Yu Tsai wrote:
> On Fri, Nov 4, 2016 at 11:18 PM, Maxime Ripard
>  wrote:
> > The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the
> > support for those too.
> >
> > Signed-off-by: Maxime Ripard 
> > ---
> >  drivers/mmc/sunxi_mmc.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> > index 6953accce123..b8716c93cb06 100644
> > --- a/drivers/mmc/sunxi_mmc.c
> > +++ b/drivers/mmc/sunxi_mmc.c
> > @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
> >
> > cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
> > cfg->host_caps = MMC_MODE_4BIT;
> > -#ifdef CONFIG_MACH_SUN50I
> > +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
> 
> 8 come before 50. :)

But 5 comes before 8, and 0 before i :)

> Otherwise,
> 
> Reviewed-by: Chen-Yu Tsai 

Thanks,
Maxime

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Re: [U-Boot] [PATCH 1/2] ext4: Allow reading files with non-zero offset, clamp read len

[Stefan Bruens]

On Samstag, 5. November 2016 21:22:43 CET Stephen Warren wrote:
> On 11/05/2016 06:32 PM, Stefan Brüns wrote:
> > Support was already implemented, but not hooked up. This fixes several
> > fails in the test cases.
> > 
> > diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
> > 
> > @@ -217,21 +217,16 @@ int ext4_read_file(const char *filename, void *buf,
> > loff_t offset, loff_t len,
> > 
> > -   if (len == 0)
> > -   len = file_len;
> > +   if ((len == 0) || (offset + len > file_len))
> > +   len = (file_len - offset);
> 
> Isn't (offset + len > file_len) an error? It seems find to "read to EOF"
> if the caller specified len==0, but if they specified a specific len,
> then isn't it an error if len+offset exceeds the length of the file?
> 
> On the other hand, if this is how other filesystems work in U-Boot, it's
> fine. I suppose this is consistent with how POSIX read() works.

It matches behaviour of POSIX read() and u-boot's FAT implementation, and 
there is also the actread parameter the caller could/should check. 

> > diff --git a/include/ext4fs.h b/include/ext4fs.h
> > 
> > -int ext4fs_read(char *buf, loff_t len, loff_t *actread);
> > +int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread);
> 
> Don't you need to update all callers of this function in this patch so
> the build doesn't break?

Missed the calls from spl_ext.c, will send v2.

Kind regards,

Stefan

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Re: [U-Boot] [PATCH v2 0/7] imx6: icorem6: Add framebuffer and I2C support

[Jagan Teki]

Hi Stefano,

On Fri, Oct 28, 2016 at 7:27 PM, Jagan Teki  wrote:
> From: Jagan Teki 
>
> This series support framebuffer and I2C on top of u-boot-imx.git with
> latest u-boot.git merge.
>
> Changes for v2:
> - Rebase on u-boot-imx.git and u-boot.git
>
> Jagan Teki (7):
>   video: Kconfig: Add VIDEO_IPV3 entry
>   imx6: icorem6: Add framebuffer support
>   imx6: icorem6: Add custom splashscreen support
>   i2c: Kconfig: Add SYS_I2C_MXC entry
>   i2c: mxc: Print hex instead of decimal for bus address
>   i2c: mxc: Make 'no gpio pinctrl state' print as debug
>   imx6: icorem6: Add I2C support
>
>  arch/arm/cpu/armv7/mx6/Kconfig   |   1 +
>  board/engicam/icorem6/icorem6.c  | 113 
> +++
>  configs/imx6qdl_icore_mmc_defconfig  |   5 +-
>  configs/imx6qdl_icore_nand_defconfig |   5 +-
>  drivers/i2c/Kconfig  |   8 +++
>  drivers/i2c/mxc_i2c.c|   2 +-
>  drivers/video/Kconfig|   8 +++
>  include/configs/imx6qdl_icore.h  |  14 +
>  tools/logos/engicam.bmp  | Bin 0 -> 60214 bytes
>  9 files changed, 153 insertions(+), 3 deletions(-)
>  create mode 100755 tools/logos/engicam.bmp

Any comments?

thanks!
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Re: [U-Boot] [PATCH v7 0/5] net: fec_mxc: Convert to DM

[Jagan Teki]

Hi Stefano,

On Thu, Oct 20, 2016 at 11:29 AM, Jagan Teki  wrote:
> Hi Stefano,
>
> On Wed, Oct 19, 2016 at 4:53 PM, Jagan Teki  wrote:
>> From: Jagan Teki 
>>
>> This series convert fec_mxc to DM and tested both dm and
>> non-dm code and it is on top of [1] with u-boot-imx/master
>> branch.
>>
>> Changes for v7:
>> - Remove fec_set_dev_name in dm probe
>>
>> Changes for v6:
>> - Add Acked-by tags in commit message
>>
>> Changes for v5:
>> - Add stub fec calls to minimize the #ifdef's
>> - Use same func names on eth_ops
>> - Remove reset_gpio in fec_mxc.h
>> - Add new patches, for cleanup driver
>>
>> Changes for v4:
>> - rebase to u-boot-imx/master
>>
>> Changes for v3:
>> - Add ARM: dts: imx6qdl-icore: Add FEC support
>> - icorem6: Use CONFIG_DM_ETH support
>>
>> Changes for v2:
>> - Add TODO for implementing the enet reset code
>>
>> [1] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support
>>
>> Jagan Teki (5):
>>   net: fec_mxc: Remove unneeded eth_device arg from fec_get_hwaddr
>>   net: fec_mxc: Convert into driver model
>>   net: fec_mxc: Driver cleanups
>>   ARM: dts: imx6qdl-icore: Add FEC support
>>   icorem6: Use CONFIG_DM_ETH support
>>
>>  arch/arm/cpu/armv7/mx6/Kconfig   |   1 +
>>  arch/arm/dts/imx6qdl-icore.dtsi  |  24 ++
>>  board/engicam/icorem6/icorem6.c  |  71 -
>>  configs/imx6qdl_icore_mmc_defconfig  |   1 -
>>  configs/imx6qdl_icore_nand_defconfig |   1 -
>>  drivers/net/fec_mxc.c| 516 
>> +++
>>  drivers/net/fec_mxc.h|  31 +--
>>  7 files changed, 378 insertions(+), 267 deletions(-)
>
> Please apply this series along with [1]

Can you please apply.

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[U-Boot] [PATCH v2 5/5] Makefile: preserve output for images that can contain HAB Blocks

[Sven Ebenfeld]

To being able to sign created binaries, we need to know the HAB Blocks
for that image. Especially for the imximage type the HAB Blocks are
only available during creation of the image. We want to preserve the
information until we get to sign the files.
In the verbose case we still get them printed out instead of writing
to log files.

Cc: sba...@denx.de

v2-Changes:
 - No usage of MKIMAGEOUTPUT_$(@F) macro.
 - Predefine default value /dev/null in every involved Makefile.

Signed-off-by: Sven Ebenfeld 
---
 .gitignore   | 2 +-
 Makefile | 6 +-
 arch/arm/imx-common/Makefile | 4 
 doc/README.imx6  | 3 ++-
 scripts/Makefile.lib | 3 ++-
 scripts/Makefile.spl | 4 +++-
 6 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/.gitignore b/.gitignore
index 33abbd3..7fac5b3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -31,7 +31,7 @@
 # Top-level generic files
 #
 /MLO*
-/SPL
+/SPL*
 /System.map
 /u-boot*
 /boards.cfg
diff --git a/Makefile b/Makefile
index 15151ff..1c19627 100644
--- a/Makefile
+++ b/Makefile
@@ -804,9 +804,11 @@ cmd_zobjcopy = $(OBJCOPY) $(OBJCOPYFLAGS) 
$(OBJCOPYFLAGS_$(@F)) $< $@
 quiet_cmd_efipayload = OBJCOPY $@
 cmd_efipayload = $(OBJCOPY) -I binary -O $(EFIPAYLOAD_BFDTARGET) -B 
$(EFIPAYLOAD_BFDARCH) $< $@
 
+MKIMAGEOUTPUT ?= /dev/null
+
 quiet_cmd_mkimage = MKIMAGE $@
 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-   $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+   $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
 
 quiet_cmd_cat = CAT $@
 cmd_cat = cat $(filter-out $(PHONY), $^) > $@
@@ -928,6 +930,8 @@ MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O 
u-boot \
 MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
+u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
+CLEAN_FILES += u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log
 endif
 
 MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 03b3c12..da53f62 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -68,6 +68,7 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE
 
 MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T 
imximage \
-e $(CONFIG_SYS_TEXT_BASE)
+u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log
 
 u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
@@ -75,6 +76,7 @@ u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
 ifeq ($(CONFIG_OF_SEPARATE),y)
 MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T 
imximage \
-e $(CONFIG_SYS_TEXT_BASE)
+u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log
 
 u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
@@ -83,6 +85,8 @@ endif
 MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE)
 
+SPL: MKIMAGEOUTPUT = SPL.log
+
 SPL: spl/u-boot-spl.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
 
diff --git a/doc/README.imx6 b/doc/README.imx6
index add1d80..0e00968 100644
--- a/doc/README.imx6
+++ b/doc/README.imx6
@@ -150,7 +150,8 @@ CONFIG_SECURE_BOOT is needed to build those two binaries.
 After building, you need to create a command sequence file and use
 Freescales Code Signing Tool to sign both binaries. After creation,
 the mkimage tool outputs the required information about the HAB Blocks
-parameter for the CSF.
+parameter for the CSF. During the build, the information is preserved
+in log files named as the binaries. (SPL.log and u-boot-ivt.log).
 
 More information about the CSF and HAB can be found in the AN4581.
 https://cache.freescale.com/files/32bit/doc/app_note/AN4581.pdf
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 45a0e1d..fb69438 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -431,6 +431,7 @@ cmd_xzmisc = (cat $(filter-out FORCE,$^) | \
 #
 # mkimage
 # ---
+MKIMAGEOUTPUT ?= /dev/null
 quiet_cmd_mkimage = MKIMAGE $@
 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-   $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+   $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index e8cf9f3..04f90e4 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -122,9 +122,11 @@ LDPPFLAGS += \
$(shell $(LD) --version | \
  sed -ne 's/GNU ld version 
\([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
 
+MKIMAGEOUTPUT ?= /dev/null
+
 quiet_cmd_mkimage = MKIMAGE $@
 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-   $(if 

[U-Boot] [PATCH v2 4/5] doc: imx6: add section for secure boot with SPL

[Sven Ebenfeld]

Cc: sba...@denx.de

Signed-off-by: Sven Ebenfeld 
---
 doc/README.imx6 | 48 
 1 file changed, 48 insertions(+)

diff --git a/doc/README.imx6 b/doc/README.imx6
index 73b8b0b..add1d80 100644
--- a/doc/README.imx6
+++ b/doc/README.imx6
@@ -138,3 +138,51 @@ c
 The last "c" command tells kermit (from ckermit package in most distros)
 to switch from command line mode to communication mode, and when the
 script is finished, the U-Boot prompt is shown in the same shell.
+
+3. Using Secure Boot on i.MX6 machines with SPL support
+---
+
+This version of U-Boot is able to build a signable version of the SPL
+as well as a signable version of the U-Boot image. The signature can
+be verified through High Assurance Boot (HAB).
+
+CONFIG_SECURE_BOOT is needed to build those two binaries.
+After building, you need to create a command sequence file and use
+Freescales Code Signing Tool to sign both binaries. After creation,
+the mkimage tool outputs the required information about the HAB Blocks
+parameter for the CSF.
+
+More information about the CSF and HAB can be found in the AN4581.
+https://cache.freescale.com/files/32bit/doc/app_note/AN4581.pdf
+
+We don't want to explain how to create a PKI tree or SRK table as
+this is well explained in the Application Note.
+
+Example Output of the SPL (imximage) creation:
+ Image Type:   Freescale IMX Boot Image
+ Image Ver:2 (i.MX53/6/7 compatible)
+ Mode: DCD
+ Data Size:61440 Bytes = 60.00 kB = 0.06 MB
+ Load Address: 00907420
+ Entry Point:  00908000
+ HAB Blocks:   00907400  cc00
+
+Example Output of the u-boot-ivt.img (firmware_ivt) creation:
+ Image Name:   U-Boot 2016.11-rc1-31589-g2a4411
+ Created:  Sat Nov  5 21:53:28 2016
+ Image Type:   ARM U-Boot Firmware with HABv4 IVT (uncompressed)
+ Data Size:352192 Bytes = 343.94 kB = 0.34 MB
+ Load Address: 1780
+ Entry Point:  
+ HAB Blocks:   0x177fffc0   0x   0x00054020
+
+The CST (Code Signing Tool) can be downloaded from NXP.
+# Compile CSF and create signature
+./cst --o csf-u-boot.bin < command_sequence_uboot.csf
+./cst --o csf-SPL.bin < command_sequence_spl.csf
+# Append compiled CSF to Binary
+cat SPL csf-SPL.bin > SPL-signed
+cat u-boot-ivt.img csf-u-boot.bin > u-boot-signed.img
+
+These two signed binaries can be used on an i.MX6 in closed
+configuration when the according SRK Table Hash has been flashed.
\ No newline at end of file
-- 
2.7.4

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[U-Boot] [PATCH v2 2/5] arm: imx: add HAB authentication of image to SPL boot

[Sven Ebenfeld]

When using HAB as secure boot mechanism on Wandboard, the chain of
trust breaks immediately after the SPL. As this is not checking
the authenticity of the loaded image before jumping to it.

The HAB status output will not be implemented in SPL as it adds
a lot of strings that are only required in debug cases. With those
it exceeds the maximum size of the available OCRAM (69 KiB).

The SPL MISC driver support must be enabled, so that the driver can use OTP fuse
to check if HAB is enabled.

Cc: sba...@denx.de

v2-Changes: None

Signed-off-by: Sven Ebenfeld 
---
 arch/arm/imx-common/hab.c | 129 ++
 arch/arm/imx-common/spl.c |  25 +++
 arch/arm/imx-common/spl_sd.cfg|  10 +++
 arch/arm/include/asm/imx-common/hab.h |   2 +
 include/configs/mx6_common.h  |   3 +
 5 files changed, 110 insertions(+), 59 deletions(-)

diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index 6731825..7449487 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -110,6 +110,10 @@
  * ++ + CSF_PAD_SIZE
  */
 
+static bool is_hab_enabled(void);
+
+#if !defined(CONFIG_SPL_BUILD)
+
 #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
 
 struct record {
@@ -257,22 +261,6 @@ uint8_t hab_engines[16] = {
-1
 };
 
-bool is_hab_enabled(void)
-{
-   struct imx_sec_config_fuse_t *fuse =
-   (struct imx_sec_config_fuse_t *)_sec_config_fuse;
-   uint32_t reg;
-   int ret;
-
-   ret = fuse_read(fuse->bank, fuse->word, );
-   if (ret) {
-   puts("\nSecure boot fuse read error\n");
-   return ret;
-   }
-
-   return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
-}
-
 static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
 {
uint8_t idx = 0;
@@ -359,6 +347,68 @@ int get_hab_status(void)
return 0;
 }
 
+int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   if ((argc != 1)) {
+   cmd_usage(cmdtp);
+   return 1;
+   }
+
+   get_hab_status();
+
+   return 0;
+}
+
+static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
+   char * const argv[])
+{
+   ulong   addr, ivt_offset;
+   int rcode = 0;
+
+   if (argc < 3)
+   return CMD_RET_USAGE;
+
+   addr = simple_strtoul(argv[1], NULL, 16);
+   ivt_offset = simple_strtoul(argv[2], NULL, 16);
+
+   rcode = authenticate_image(addr, ivt_offset);
+
+   return rcode;
+}
+
+U_BOOT_CMD(
+   hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
+   "display HAB status",
+   ""
+ );
+
+U_BOOT_CMD(
+   hab_auth_img, 3, 0, do_authenticate_image,
+   "authenticate image via HAB",
+   "addr ivt_offset\n"
+   "addr - image hex address\n"
+   "ivt_offset - hex offset of IVT in the image"
+ );
+
+
+#endif /* !defined(CONFIG_SPL_BUILD) */
+
+static bool is_hab_enabled(void)
+{
+   struct imx_sec_config_fuse_t *fuse =
+   (struct imx_sec_config_fuse_t *)_sec_config_fuse;
+   uint32_t reg;
+   int ret;
+
+   ret = fuse_read(fuse->bank, fuse->word, );
+   if (ret) {
+   puts("\nSecure boot fuse read error\n");
+   return ret;
+   }
+
+   return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
+}
+
 uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 {
uint32_t load_addr = 0;
@@ -400,7 +450,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t 
image_size)
 (void *)(ddr_start + ivt_offset+IVT_SIZE),
 4, 0x10, 0);
 
+#if  !defined(CONFIG_SPL_BUILD)
get_hab_status();
+#endif
 
puts("\nCalling authenticate_image in ROM\n");
printf("\tivt_offset = 0x%x\n", ivt_offset);
@@ -449,7 +501,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t 
image_size)
 
hab_caam_clock_enable(0);
 
+#if !defined(CONFIG_SPL_BUILD)
get_hab_status();
+#endif
} else {
puts("hab fuse not enabled\n");
}
@@ -459,46 +513,3 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t 
image_size)
 
return result;
 }
-
-int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-   if ((argc != 1)) {
-   cmd_usage(cmdtp);
-   return 1;
-   }
-
-   get_hab_status();
-
-   return 0;
-}
-
-static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
-   char * const argv[])
-{
-   ulong   addr, ivt_offset;
-   int rcode = 0;
-
-   if (argc < 3)
-   return CMD_RET_USAGE;
-
-   addr = simple_strtoul(argv[1], NULL, 16);
-

[U-Boot] [PATCH v2 3/5] tools: mkimage: add firmware-ivt image type for HAB verification

[Sven Ebenfeld]

When we want to use Secure Boot with HAB from SPL over U-Boot.img,
we need to append the IVT to the image and leave space for the CSF.
Images generated as firmware_ivt can directly be signed using the
Freescale code signing tool. For creation of a CSF, mkimage outputs
the correct HAB Blocks for the image.
The changes to the usual firmware image class are quite small,
that is why I implemented that directly into the default_image.

Cc: sba...@denx.de

v2-Changes: None

Signed-off-by: Sven Ebenfeld 
---
 Makefile  |  9 -
 common/image.c|  6 ++
 include/image.h   |  1 +
 tools/default_image.c | 10 --
 tools/mkimage.c   | 32 
 5 files changed, 55 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index dcba7db..15151ff 100644
--- a/Makefile
+++ b/Makefile
@@ -754,7 +754,11 @@ ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
 endif
 endif
 ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
+ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy)
+ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
+else
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
+endif
 ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
 ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb
 ifeq ($(CONFIG_SPL_FRAMEWORK),y)
@@ -921,6 +925,9 @@ else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
+MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
+   -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+   -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 endif
 
 MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
@@ -934,7 +941,7 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n 
$(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
-u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl: \
+u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin 
dts/dt.dtb,u-boot.bin) FORCE
$(call if_changed,mkimage)
 
diff --git a/common/image.c b/common/image.c
index 0e86c13..01e1dea 100644
--- a/common/image.c
+++ b/common/image.c
@@ -165,6 +165,7 @@ static const table_entry_t uimage_type[] = {
{   IH_TYPE_ZYNQIMAGE,  "zynqimage",  "Xilinx Zynq Boot Image" },
{   IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" 
},
{   IH_TYPE_FPGA,   "fpga",   "FPGA Image" },
+   {   IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" 
},
{   -1, "",   "",   },
 };
 
@@ -364,6 +365,11 @@ void image_print_contents(const void *ptr)
printf("%sOffset = 0x%08lx\n", p, data);
}
}
+   } else if (image_check_type(hdr, IH_TYPE_FIRMWARE_IVT)) {
+   printf("HAB Blocks:   0x%08x   0x   0x%08x\n",
+   image_get_load(hdr) - image_get_header_size(),
+   image_get_size(hdr) + image_get_header_size()
+   - 0x1FE0);
}
 }
 
diff --git a/include/image.h b/include/image.h
index 2b1296c..14d0a3d 100644
--- a/include/image.h
+++ b/include/image.h
@@ -279,6 +279,7 @@ enum {
IH_TYPE_ZYNQMPIMAGE,/* Xilinx ZynqMP Boot Image */
IH_TYPE_FPGA,   /* FPGA Image */
IH_TYPE_VYBRIDIMAGE,/* VYBRID .vyb Image */
+   IH_TYPE_FIRMWARE_IVT,   /* Firmware Image with HABv4 IVT */
 
IH_TYPE_COUNT,  /* Number of image types */
 };
diff --git a/tools/default_image.c b/tools/default_image.c
index 6e4ae14..4e5568e 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -25,7 +25,7 @@ static image_header_t header;
 static int image_check_image_types(uint8_t type)
 {
if (((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT)) ||
-   (type == IH_TYPE_KERNEL_NOLOAD))
+   (type == IH_TYPE_KERNEL_NOLOAD) || (type == IH_TYPE_FIRMWARE_IVT))
return EXIT_SUCCESS;
else
return EXIT_FAILURE;
@@ -89,6 +89,7 @@ static void image_set_header(void *ptr, struct stat *sbuf, 
int ifd,
 {
uint32_t checksum;
time_t time;
+   uint32_t imagesize;
 
image_header_t * hdr = (image_header_t *)ptr;
 
@@ -98,11 +99,16 @@ static void image_set_header(void *ptr, struct stat *sbuf, 
int ifd,
sbuf->st_size - sizeof(image_header_t));
 
time = imagetool_get_source_date(params, sbuf->st_mtime);
+   if (params->type == IH_TYPE_FIRMWARE_IVT)
+   /* Add size of CSF minus IVT */
+   imagesize = sbuf->st_size - sizeof(image_header_t) + 0x1FE0;
+  

[U-Boot] [PATCH v2 1/5] arm: imx: remove bmode , hdmidet and dek commands from SPL

[Sven Ebenfeld]

These files are blowing up the SPL and should not be required
there as the SPL delivers no command console. Because building fails
for mx27 and mx31 machines with SPL build, we remove the linker flag
for them from the Makefile. Nothing is built for them to be linked
in that directory.

Cc: sba...@denx.de

v2 Changes:
 - Remove mx27 and mx31 from Makefile during SPL build as nothing is built for
   them in that directory. And removing the commands with the libs-y directive
   lead to linker failures. e.g. "armv5te-ld.bfd: cannot find 
arch/arm/imx-common/built-in.o: No such file or directory)"

Signed-off-by: Sven Ebenfeld 
---
 arch/arm/Makefile| 2 +-
 arch/arm/imx-common/Makefile | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 42093c2..6faf29e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -93,7 +93,7 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 
mx5 mx6 mx7 mx31 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 
mx6 mx7 mx35))
 libs-y += arch/arm/imx-common/
 endif
 else
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 1873185..03b3c12 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -34,9 +34,11 @@ endif
 ifeq ($(SOC),$(filter $(SOC),vf610))
 obj-y += ddrmc-vf610.o
 endif
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
 obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
+endif
 
 PLUGIN = board/$(BOARDDIR)/plugin
 
-- 
2.7.4

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[U-Boot] [PATCH v2 0/5] arm: imx6: Enable Secure Boot (HAB) with SPL Builds

[Sven Ebenfeld]

When trying to build U-Boot for Wandboard with Secure Boot, the build fails
because it tries to compile the dekblob commands within the SPL. The dekblob
command depends on the CAAM driver, which is also not required in the SPL. 
Additionally, this blows the SPL up to a size beyond the limit of 69KiB in
i.MX6DL OCRAM. Therefore I deactivate building the commands during SPL build.

Next I implemented HAB verification before jumping to the loaded image. To
create images that are HAB compatible, I updated the mkimage tool and added some
documentation. At last I try to make the signing process easier as the output of
the mkimage tool will be preserverd within the build dir. The output contains
information required to correctly sign HAB images.

Cc: sba...@denx.de

v2 Changes:
 - Repair build failures in many SPLs due to incorrect variable assignment.
 - Repair mx31 and mx27 builds without imx-common libs (nothing is built there
   for them.

Sven Ebenfeld (5):
  arm: imx: remove bmode , hdmidet and dek commands from SPL
  arm: imx: add HAB authentication of image to SPL boot
  tools: mkimage: add firmware-ivt image type for HAB verification
  doc: imx6: add section for secure boot with SPL
  Makefile: preserve output for images that can contain HAB Blocks

 .gitignore|   2 +-
 Makefile  |  15 +++-
 arch/arm/Makefile |   2 +-
 arch/arm/imx-common/Makefile  |   6 ++
 arch/arm/imx-common/hab.c | 129 ++
 arch/arm/imx-common/spl.c |  25 +++
 arch/arm/imx-common/spl_sd.cfg|  10 +++
 arch/arm/include/asm/imx-common/hab.h |   2 +
 common/image.c|   6 ++
 doc/README.imx6   |  49 +
 include/configs/mx6_common.h  |   3 +
 include/image.h   |   1 +
 scripts/Makefile.lib  |   3 +-
 scripts/Makefile.spl  |   4 +-
 tools/default_image.c |  10 ++-
 tools/mkimage.c   |  32 +
 16 files changed, 232 insertions(+), 67 deletions(-)

-- 
2.7.4

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[U-Boot] [PATCH v2 0/1] cmd: pci: add option to parse and display BAR information

[yehuday]

From: Yehuda Yitschak 

Updates to initial patch following comments from Stephan Rose
I don't have access to a board with DM_PCI support so I tested only on
non DM_PCI. Appreciate if someone can test on DM_PCI

v1->v2:
 - Added support for DM_PCI
 - Added print of memory type and prefetchable flag
 - Skipped printing of disabled BARs

Yehuda Yitschak (1):
  cmd: pci: add option to parse and display BAR information

 cmd/pci.c | 95 +++
 1 file changed, 95 insertions(+)

-- 
1.9.1

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[U-Boot] [PATCH v2 1/1] cmd: pci: add option to parse and display BAR information

[yehuday]

From: Yehuda Yitschak 

Currently the PCI command only allows to see the BAR register
values but not the size and actual base address.
This little extension parses the BAR registers and displays
the base, size and type of each BAR.

Signed-off-by: Yehuda Yitschak 
---
 cmd/pci.c | 95 +++
 1 file changed, 95 insertions(+)

diff --git a/cmd/pci.c b/cmd/pci.c
index 2f4978a..51eb536 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -92,6 +92,96 @@ static void pci_show_regs(pci_dev_t dev, struct pci_reg_info 
*regs)
 }
 #endif
 
+#ifdef CONFIG_DM_PCI
+int pci_bar_show(struct udevice *dev)
+#else
+int pci_bar_show(pci_dev_t dev)
+#endif
+{
+   u8 header_type;
+   int bar_cnt, bar_id, is_64, is_io, mem_type;
+   u32 base_low, base_high;
+   u32 size_low, size_high;
+   u64 base, size;
+   u32 reg_addr;
+   int prefetchable;
+
+#ifdef CONFIG_DM_PCI
+   dm_pci_read_config8(dev, PCI_HEADER_TYPE, _type);
+#else
+   pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
+#endif
+
+   if (header_type == PCI_HEADER_TYPE_CARDBUS) {
+   printf("CardBus doesn't support BARs\n");
+   return -1;
+   }
+
+   bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
+
+   printf("ID   BaseSizeWidth  Type\n");
+   printf("--\n");
+
+   bar_id = 0;
+   reg_addr = PCI_BASE_ADDRESS_0;
+   while (bar_cnt) {
+#ifdef CONFIG_DM_PCI
+   dm_pci_read_config32(dev, reg_addr, _low);
+   dm_pci_write_config32(dev, reg_addr, 0x);
+   dm_pci_read_config32(dev, reg_addr, _low);
+   dm_pci_write_config32(dev, reg_addr, base_low);
+#else
+   pci_read_config_dword(dev, reg_addr, _low);
+   pci_write_config_dword(dev, reg_addr, 0x);
+   pci_read_config_dword(dev, reg_addr, _low);
+   pci_write_config_dword(dev, reg_addr, base_low);
+#endif
+   reg_addr += 4;
+
+   base = base_low & ~0xF;
+   size = size_low & ~0xF;
+   base_high = 0x0;
+   size_high = 0x;
+   is_64 = 0;
+   prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
+   is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
+   mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
+
+   if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
+#ifdef CONFIG_DM_PCI
+   dm_pci_read_config32(dev, reg_addr, _high);
+   dm_pci_write_config32(dev, reg_addr, 0x);
+   dm_pci_read_config32(dev, reg_addr, _high);
+   dm_pci_write_config32(dev, reg_addr, base_high);
+#else
+   pci_read_config_dword(dev, reg_addr, _high);
+   pci_write_config_dword(dev, reg_addr, 0x);
+   pci_read_config_dword(dev, reg_addr, _high);
+   pci_write_config_dword(dev, reg_addr, base_high);
+#endif
+   bar_cnt--;
+   reg_addr += 4;
+   is_64 = 1;
+   }
+
+   base = base | ((u64)base_high << 32);
+   size = size | ((u64)size_high << 32);
+
+   if ((!is_64 && size_low) || (is_64 && size)) {
+   size = ~size + 1;
+   printf(" %d   0x%016llx  0x%016llx  %d %s   %s\n",
+  bar_id, base, size, is_64 ? 64 : 32,
+  is_io ? "I/O" : "MEM",
+  prefetchable ? "Prefetchable" : "");
+   }
+
+   bar_id++;
+   bar_cnt--;
+   }
+
+   return 0;
+}
+
 static struct pci_reg_info regs_start[] = {
{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
@@ -573,6 +663,7 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
if (argc > 4)
value = simple_strtoul(argv[4], NULL, 16);
case 'h':   /* header */
+   case 'b':   /* bars */
if (argc < 3)
goto usage;
if ((bdf = get_pci_dev(argv[2])) == -1)
@@ -641,6 +732,8 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
ret = pci_cfg_write(dev, addr, size, value);
 #endif
break;
+   case 'b':   /* bars */
+   return pci_bar_show(dev);
default:
ret = CMD_RET_USAGE;
break;
@@ -663,6 +756,8 @@ static char pci_help_text[] =
 #endif
"pci header b.d.f\n"
"- show header of PCI device 'bus.device.function'\n"
+   "pci 

Re: [U-Boot] [PATCH] wandboard: Make Ethernet functional again

[Fabio Estevam]

Hi Tom,

On Tue, Nov 1, 2016 at 2:58 PM, Fabio Estevam  wrote:
> Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate
> config for AR8031") ethernet does not work on mx6sabresd.
>
> This commit correctly assigns ar8031_config() as the configuration
> function for AR8031 in the same way as done in the Linux kernel.
>
> However, on wandboard design we need some additional configuration,
> such as enabling the 125 MHz AR8031 output that needs to be done
> in the board file.
>
> This also aligns with the same method that the kernel performs
> the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c.
>
> Signed-off-by: Fabio Estevam 

As you picked the similiar patch for sabresd, could you please take
this one too?
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Re: [U-Boot] mx6sabresd: Make Ethernet functional again

[Tom Rini]

On Mon, Oct 24, 2016 at 10:22:06AM -0200, Fabio Estevam wrote:

> From: Fabio Estevam 
> 
> Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate
> config for AR8031") ethernet does not work on mx6sabresd.
> 
> This commit correctly assigns ar8031_config() as the configuration
> function for AR8031 in the same way as done in the Linux kernel.
> 
> However, on mx6sabresd design we need some additional configuration,
> such as enabling the 125 MHz AR8031 output that needs to be done
> in the board file.
> 
> This also aligns with the same method that the kernel performs
> the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c.
> 
> Signed-off-by: Fabio Estevam 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 1/2] rpi: save firmware provided boot param for later use

[Jonathan Liu]

Hi Cédric,

On 6 November 2016 at 21:06, Cédric Schieli  wrote:
>
> 2016-11-06 1:36 GMT+01:00 Jonathan Liu :
>>
>> I did a similar patch without noticing you already submitted this series.
>> The save_boot_params function can be written in C instead of assembly
>> and placed in rpi.c.
>> See
>> https://lists.yoctoproject.org/pipermail/yocto/2016-November/032934.html
>> for how to write save_boot_params in C as this can simplify your
>> patch. It also has a U-Boot script for using the FDT provided by the
>> firmware, though you would need to change ${fdt_addr_r} to
>> ${fw_fdt_addr} for it to work with your patch series.
>
>
> I do not have a strong opinion on wether save_boot_params should be C or
> assembly code. I'll opt for what the maintainers prefer here.
>
> Regarding the script, I'll include a example in my next version. I don't
> like the idea to hijack ${fdt_addr_r} as it is documented as a pointer to
> where one can manually load a custom FDT blob. If we make it points to the
> firmware provided one and the user manually loads a bigger blob, unexpected
> results may happen.

Yes, I prefer your method of storing it in a separate environment variable.

Regards,
Jonathan
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Re: [U-Boot] [PATCH] mx6sabresd: Make Ethernet functional again

[Stefano Babic]

Hi Tom,

On 05/11/2016 18:41, Stefano Babic wrote:
> 
> 
> On 05/11/2016 17:35, Fabio Estevam wrote:
>> Hi Stefano,
>>
>> On Mon, Oct 24, 2016 at 10:22 AM, Fabio Estevam  wrote:
>>> From: Fabio Estevam 
>>>
>>> Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate
>>> config for AR8031") ethernet does not work on mx6sabresd.
>>>
>>> This commit correctly assigns ar8031_config() as the configuration
>>> function for AR8031 in the same way as done in the Linux kernel.
>>>
>>> However, on mx6sabresd design we need some additional configuration,
>>> such as enabling the 125 MHz AR8031 output that needs to be done
>>> in the board file.
>>>
>>> This also aligns with the same method that the kernel performs
>>> the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c.
>>>
>>> Signed-off-by: Fabio Estevam 
>>
>> This one (and the similar patch for wandboard) is a regression fix, so
>> hopefully it can reach 2016.11 release.
> 
> I pick it up
> 

As you are already picking Jagan's patch, can you take this one from
Fabio, too ? Or do you prefer a PR from me ?

Thanks,
Stefano

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Re: [U-Boot] [PATCH v3 1/3] ARM: bcm283x: Implement EFI RTS reset_system

[Alexander Graf]

On 05/11/2016 23:01, Stephen Warren wrote:

On 11/02/2016 03:36 AM, Alexander Graf wrote:

The rpi has a pretty simple way of resetting the whole system. All it
takes
is to poke a few registers at a well defined location in MMIO space.

This patch adds support for the EFI loader implementation to allow an
OS to
reset and power off the system when we're outside of boot time.


(As an aside, I'm not sure why someone wanting EFI wouldn't just use a
complete EFI implementation such as TianoCore.)


Sorry, I didn't reply to this part earlier.

If you have a TianoCore port, using that is almost always a better idea. 
I'd compare it to wine vs native Windows. With native Windows, you get 
guaranteed compatibility, wine only tries really hard :).


However, if you compare the size of this patch set to a TianoCore port, 
the rationale becomes pretty clear I guess. Porting a system that is 
already U-Boot enabled to be RTS enabled is a matter of a day of work. 
Non-RTS EFI enablement comes for free in U-Boot.


Porting TianoCore to a new platform takes slightly longer. And you have 
to embrace CamelCase.



Alex
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Re: [U-Boot] [PATCH v3 3/3] bcm2835: Reserve the spin table in efi memory map

[Alexander Graf]

On 05/11/2016 23:07, Stephen Warren wrote:

On 11/02/2016 03:36 AM, Alexander Graf wrote:

Firmware provides a spin table on the raspberry pi. This table shouldn't
get overwritten by payloads, so we need to mark it as reserved.


This is probably fine for now so,
Acked-by: Stephen Warren 

However in the long term I wonder if U-Boot shouldn't find out the spin
table address from the FW-provided DTB, then boot all CPUs into a
spin-table implementation that's provided by U-Boot. That would avoid
having to hard-code the address/size of the spin table code/data in
U-Boot, which in theory at least could change to an arbitrary location
in a future FW release.


I think in the long term, it would make much more sense to use PSCI on 
the RPi3. Then we wouldn't have to worry about any of the above, except 
for an EL3 reserved memory region that we could also enquire using PSCI.


For 32bit systems, yes, probably :).


Alex
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Re: [U-Boot] [PATCH v3 1/3] ARM: bcm283x: Implement EFI RTS reset_system

[Alexander Graf]

On 05/11/2016 23:01, Stephen Warren wrote:

On 11/02/2016 03:36 AM, Alexander Graf wrote:

The rpi has a pretty simple way of resetting the whole system. All it
takes
is to poke a few registers at a well defined location in MMIO space.

This patch adds support for the EFI loader implementation to allow an
OS to
reset and power off the system when we're outside of boot time.


(As an aside, I'm not sure why someone wanting EFI wouldn't just use a
complete EFI implementation such as TianoCore.)


diff --git a/arch/arm/mach-bcm283x/reset.c
b/arch/arm/mach-bcm283x/reset.c



+__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
+(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
+
+void __efi_runtime reset_cpu(ulong addr)
 {
-struct bcm2835_wdog_regs *regs =
-(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;


I'm not sure why that change is required. The value of the variable is
the same in both cases?


Take a look a few lines down in the patch:


+void efi_reset_system_init(void)
+{
+   efi_add_runtime_mmio(_regs, sizeof(*wdog_regs));
+}


What this does is register a *pointer* as run time service pointer. What 
does that mean?


When we enter RTS, Linux can map any region in the EFI memory map into a 
different place in its own virtual memory map. So any pointers we use 
inside RTS have to be relocated to the new locations.


For normal relocations, we move the relocations from linker time to run 
time, so that we can relocate ourselves when Linux does the switch-over 
to a new address space.


However, for MMIO that's trickier. That's where the 
efi_add_runtime_mmio() function comes into play. It takes care of adding 
the page around the references address to the EFI memory map as RTS MMIO 
and relocates the pointer when Linux switches us into the new address space.


Does that explain why we need to move from an inline address to an 
address stored in a memory location?



Perhaps it's trying to ensure that if this gets compiled into an ldr
instruction, the referenced data value is in a linker section that's
still around when EFI runs? If so fine, but how is that ensured for all
the other constants that this code uses, and if that happens
automatically due to the __efi_runtime marker above, why doesn't it work
for this one constant?

Does U-Boot have a halt/poweroff/shutdown shell command? If so, it might
be nice to enable it as part of this series, since the code to perform
that operation is now present.


That's what I originally wanted, yes :). Unfortunately due to the 
relocation explained above, it's basically impossible for any reset 
function that calls into MMIO space.


However, we do have it now for PSCI. If you have a PSCI enabled system, 
we don't need to call into MMIO space and thus make the common reset 
function available as RTS.



Alex
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Re: [U-Boot] [PATCH 1/2] rpi: save firmware provided boot param for later use

[Cédric Schieli]

2016-11-06 3:48 GMT+01:00 Stephen Warren :

> On 11/02/2016 12:06 PM, Cédric Schieli wrote:
>
>> At U-Boot entry point, the r2 register holds the address of the
>> firmware provided boot param. Let's save it for further processing.
>>
>
> diff --git a/board/raspberrypi/rpi/lowlevel_init.S
>> b/board/raspberrypi/rpi/lowlevel_init.S
>>
>
> +.global fw_boot_param
>> +fw_boot_param:
>> +   .word 0x
>>
>
> fw_dtb_pointer might be a better name; there are multiple different
> registers set up by the FW in some cases; best to be explicit about what
> kind of parameter is being saved.
>

I did not want to use a DT oriented naming because of the possibility to
pass a ATAG instead. But I can change it if you prefer.


> See the note later about the size/alignment requirements for this value.
>
> +/*
>> + * Routine: save_boot_params (called after reset from start.S)
>> + * Description: save ATAG/FDT address provided by the firmware at boot
>> time
>> + */
>> +
>> +.global save_boot_params
>> +save_boot_params:
>> +
>> +   /* The firmware provided ATAG/FDT address can be found in r2 */
>> +   str r2, fw_boot_param
>>
>
> For the 64-bit RPi builds, you need to save x0 not r2. The assembly above
> doesn't compile since r2 isn't a valid register (it's named x2 on 64-bit),
> plus the DTB pointer is actually in x0 not x2.
>

Noted. I'll address all the 64-bit issues in the next round.


>
> +   /* Returns */
>> +   b   save_boot_params_ret
>>
>
> With these patches applied, the build of rpi_defconfig fails since the
> ARM1176 CPU startup file doesn't define that symbol.
>
> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
>>
>
> +#ifndef __ASSEMBLY__
>> +/* Firmware provided boot param */
>> +extern const void *fw_boot_param;
>> +#endif
>>
>
This issue will go away with the next round as the extern declaration will
be moved to the rpi.c file, or simply removed if the save_boot_params code
is converted to C.

Regards,
Cédric
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Re: [U-Boot] [PATCH 1/2] rpi: save firmware provided boot param for later use

[Cédric Schieli]

2016-11-06 1:36 GMT+01:00 Jonathan Liu :

> I did a similar patch without noticing you already submitted this series.
> The save_boot_params function can be written in C instead of assembly
> and placed in rpi.c.
> See https://lists.yoctoproject.org/pipermail/yocto/2016-
> November/032934.html
> for how to write save_boot_params in C as this can simplify your
> patch. It also has a U-Boot script for using the FDT provided by the
> firmware, though you would need to change ${fdt_addr_r} to
> ${fw_fdt_addr} for it to work with your patch series.
>

I do not have a strong opinion on wether save_boot_params should be C or
assembly code. I'll opt for what the maintainers prefer here.

Regarding the script, I'll include a example in my next version. I don't
like the idea to hijack ${fdt_addr_r} as it is documented as a pointer to
where one can manually load a custom FDT blob. If we make it points to the
firmware provided one and the user manually loads a bigger blob, unexpected
results may happen.

Regards,
Cédric
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