[U-Boot] [PATCH] serial, ns16550: bugfix: ns16550 fifo not enabled

[Heiko Schocher]

commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor"
breaks u-boot commandline working with long commands
sending to the board.

Since the above patch, you have to setup the fcr register.

For board/archs which enable OF_PLATDATA, the new field
fcr in struct ns16550_platdata is not filled with a
default value ...

This leads in not setting up the uarts fifo, which ends
in problems, when you send long commands to u-boots
commandline.

Detected this issue with automated tbot tests on am335x
based shc board.

The error does not popup, if you type commands. You need
to copy a long command to u-boots commandshell
(or send a long command with tbot)

Possible boards/plattforms with problems:
./arch/arm/cpu/arm926ejs/lpc32xx/devices.c
./arch/arm/mach-tegra/board.c
./board/isee/igep00x0/igep00x0.c
./board/overo/overo.c
./board/quipos/cairo/cairo.c
./board/logicpd/omap3som/omap3logic.c
./board/logicpd/zoom1/zoom1.c
./board/timll/devkit8000/devkit8000.c
./board/lg/sniper/sniper.c
./board/ti/beagle/beagle.c
./drivers/serial/serial_rockchip.c

This patch fixes only:
./arch/arm/mach-omap2/am33xx/board.c

Signed-off-by: Heiko Schocher 
---

 arch/arm/mach-omap2/am33xx/board.c | 23 +--
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/am33xx/board.c 
b/arch/arm/mach-omap2/am33xx/board.c
index 581c0ab..a0ce62c 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -39,15 +39,26 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
+/* Clear & enable FIFOs */
+#define UART_FCRVAL (UART_FCR_FIFO_EN |\
+UART_FCR_RXSR |\
+UART_FCR_TXSR)
+
 static const struct ns16550_platdata am33xx_serial[] = {
-   { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = 
CONFIG_SYS_NS16550_CLK },
+   { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL },
 # ifdef CONFIG_SYS_NS16550_COM2
-   { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = 
CONFIG_SYS_NS16550_CLK },
+   { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL },
 #  ifdef CONFIG_SYS_NS16550_COM3
-   { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = 
CONFIG_SYS_NS16550_CLK },
-   { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = 
CONFIG_SYS_NS16550_CLK },
-   { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = 
CONFIG_SYS_NS16550_CLK },
-   { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = 
CONFIG_SYS_NS16550_CLK },
+   { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL },
+   { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL },
+   { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL },
+   { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL },
 #  endif
 # endif
 };
-- 
2.7.4

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[U-Boot] [PATCH][v2] driver: net: fsl-mc: Use aligned address for MC FW load

[Priyanka Jain]

Firmware of Management Complex (MC) should be loaded at 512MB aligned
address. So,
-mc_ram_addr address calculation in mc_get_dram_addr() is updated to
 fetch aligned address
-calculate_mc_private_ram_params() is removed as it is no longer required
-num_256mb_blocks calculation is moved to mc_init()

Signed-off-by: Priyanka Jain 
---
Changes for v2:
 Update mc_get_dram_addr() logic for adress calculation instead of
 updating variable mc_ram_addr

 drivers/net/fsl-mc/mc.c |   87 ++-
 1 files changed, 33 insertions(+), 54 deletions(-)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 46b8a6b..06d373d 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -41,6 +41,7 @@ struct fsl_dpbp_obj *dflt_dpbp = NULL;
 struct fsl_dpio_obj *dflt_dpio = NULL;
 struct fsl_dpni_obj *dflt_dpni = NULL;
 static u64 mc_lazy_dpl_addr;
+u64 mc_ram_addr = 0;
 
 #ifdef DEBUG
 void dump_ram_words(const char *title, void *addr)
@@ -153,48 +154,6 @@ int parse_mc_firmware_fit_image(u64 mc_fw_addr,
 }
 #endif
 
-/*
- * Calculates the values to be used to specify the address range
- * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
- * It returns the highest 512MB-aligned address within the given
- * address range, in '*aligned_base_addr', and the number of 256 MiB
- * blocks in it, in 'num_256mb_blocks'.
- */
-static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
-  size_t mc_ram_size,
-  u64 *aligned_base_addr,
-  u8 *num_256mb_blocks)
-{
-   u64 addr;
-   u16 num_blocks;
-
-   if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
-   printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
-  mc_ram_size);
-   return -EINVAL;
-   }
-
-   num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
-   if (num_blocks < 1 || num_blocks > 0xff) {
-   printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
-  mc_ram_size);
-   return -EINVAL;
-   }
-
-   addr = (mc_private_ram_start_addr + mc_ram_size - 1) &
-   MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
-
-   if (addr < mc_private_ram_start_addr) {
-   printf("fsl-mc: ERROR: bad start address %#llx\n",
-  mc_private_ram_start_addr);
-   return -EFAULT;
-   }
-
-   *aligned_base_addr = addr;
-   *num_256mb_blocks = num_blocks;
-   return 0;
-}
-
 static int mc_fixup_dpc(u64 dpc_addr)
 {
void *blob = (void *)dpc_addr;
@@ -443,7 +402,6 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
int error = 0;
int portal_id = 0;
struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
-   u64 mc_ram_addr = mc_get_dram_addr();
u32 reg_gsr;
u32 reg_mcfbalr;
 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
@@ -451,17 +409,18 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
size_t raw_image_size = 0;
 #endif
struct mc_version mc_ver_info;
-   u64 mc_ram_aligned_base_addr;
u8 mc_ram_num_256mb_blocks;
size_t mc_ram_size = mc_get_dram_block_size();
 
 
-   error = calculate_mc_private_ram_params(mc_ram_addr,
-   mc_ram_size,
-   _ram_aligned_base_addr,
-   _ram_num_256mb_blocks);
-   if (error != 0)
+   mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
+   if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) {
+   printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
+  mc_ram_size);
goto out;
+   }
+
+   mc_ram_addr = mc_get_dram_addr();
 
/*
 * Management Complex cores should be held at reset out of POR.
@@ -503,11 +462,11 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
/*
 * Tell MC what is the address range of the DRAM block assigned to it:
 */
-   reg_mcfbalr = (u32)mc_ram_aligned_base_addr |
+   reg_mcfbalr = (u32)mc_ram_addr |
  (mc_ram_num_256mb_blocks - 1);
out_le32(_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
out_le32(_ccsr_regs->reg_mcfbahr,
-(u32)(mc_ram_aligned_base_addr >> 32));
+(u32)(mc_ram_addr >> 32));
out_le32(_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
 
/*
@@ -615,20 +574,40 @@ int get_dpl_apply_status(void)
  */
 u64 mc_get_dram_addr(void)
 {
-   u64 mc_ram_addr;
+   u64 mc_private_ram_start_addr;
+   size_t mc_ram_size = mc_get_dram_block_size();
 
/*
 * The MC private DRAM block was already carved at the end of DRAM
 * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
 */
 

Re: [U-Boot] [PATCH v2 0/7] mmc: more Kconfig conversion, MMC related clean-up

[Jaehoon Chung]

Hi Masahiro,

On 01/10/2017 01:32 PM, Masahiro Yamada wrote:
> This series is based on commit 3d3a74cc8c.
> Each git-log describes how to re-generate it.
> Buildman test passed.
> 
> 
> Changes in v2:
>   - Re-generate based on v2017.01
> 
> Masahiro Yamada (7):
>   ARM: socfpga: remove unused CONFIG option and cleanup README.socfpga
>   mmc: rename CONFIG_ROCKCHIP_DWMMC to CONFIG_MMC_DW_ROCKCHIP
>   mmc: move CONFIG_DWMMC to Kconfig, renaming to CONFIG_MMC_DW
>   mmc: move DesignWare-based drivers to Kconfig
>   ARM: davinci: remove unused CONFIG_DAVINCI_MMC_SD1
>   mmc: move more driver config options to Kconfig
>   ARM: sunxi: remove bare default for CONFIG_MMC

Applied on u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

> 

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[U-Boot] [GIT PULL] Please pull u-boot-mmc master

[Jaehoon Chung]

Dear Tom,

Could you pull these patches on your master branch?
If there is an issue, let me know, plz.(Buildman was passed.)

The following changes since commit a705ebc81b7f91bbd0ef7c634284208342901149:

  Prepare v2017.01 (2017-01-09 11:57:05 -0500)

are available in the git repository at:

  http://git.denx.de/u-boot-mmc.git master

for you to fetch changes up to e20dd3f86f05227e75d979f100559cfdace2816b:

  ARM: sunxi: remove bare default for CONFIG_MMC (2017-01-10 14:08:23 +0900)


Jaehoon Chung (12):
  mmc: sdhci: disable the 8bit mode when host doesn't support it
  mmc: sdhci: add the get_cd callback function in sdhci_ops
  mmc: sdhci: remove the unused code about testing Card detect
  mmc: pic32_sdhci: move the code to pic32_sdhci.c
  mmc: sdhci: remove the SDHCI_QUIRK_NO_CD
  mmc: change the set_ios return type from void to int
  mmc: s5p_sdhci: add the s5p_set_clock function
  mmc: sdhci: move the callback function into sdhci_ops
  mmc: sdhci: use the bitops APIs in sdhci.h
  mmc: sdhci: remove the SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
  mmc: sdhci: combine the Host controller v3.0 feature into one condition
  power: change from meaningless value to error number

Masahiro Yamada (9):
  mmc: sdhci-cadence: add Cadence SD4HC support
  mmc: uniphier-sd: fix Kconfig dependency
  ARM: socfpga: remove unused CONFIG option and cleanup README.socfpga
  mmc: rename CONFIG_ROCKCHIP_DWMMC to CONFIG_MMC_DW_ROCKCHIP
  mmc: move CONFIG_DWMMC to Kconfig, renaming to CONFIG_MMC_DW
  mmc: move DesignWare-based drivers to Kconfig
  ARM: davinci: remove unused CONFIG_DAVINCI_MMC_SD1
  mmc: move more driver config options to Kconfig
  ARM: sunxi: remove bare default for CONFIG_MMC

 arch/arm/cpu/arm926ejs/mx27/generic.c  |   8 +-
 arch/arm/include/asm/arch-mx27/imx-regs.h  |   4 +-
 arch/arm/mach-davinci/da830_pinmux.c   |   2 +-
 arch/arm/mach-omap2/am33xx/board.c |   2 +-
 arch/arm/mach-tegra/board2.c   |   2 +-
 board/armadeus/apf27/apf27.c   |   2 +-
 board/avionic-design/common/tamonten.c |   2 +-
 board/compal/paz00/paz00.c |   2 +-
 board/davinci/da8xxevm/da850evm.c  |  12 +--
 board/davinci/da8xxevm/omapl138_lcdk.c |  10 +--
 board/hisilicon/hikey/hikey.c  |   2 +-
 board/htkw/mcx/mcx.c   |   2 +-
 board/lego/ev3/legoev3.c   |   4 +-
 board/nvidia/cardhu/cardhu.c   |   2 +-
 board/nvidia/dalmore/dalmore.c |   2 +-
 board/nvidia/harmony/harmony.c |   2 +-
 board/nvidia/seaboard/seaboard.c   |   2 +-
 board/nvidia/whistler/whistler.c   |   2 +-
 board/samsung/common/board.c   |   2 +-
 board/sunxi/Kconfig|   4 -
 board/technexion/twister/twister.c |   2 +-
 board/teejet/mt_ventoux/mt_ventoux.c   |   2 +-
 board/toradex/colibri_t20/colibri_t20.c|   2 +-
 configs/am335x_baltos_defconfig|   1 +
 configs/am335x_boneblack_defconfig |   1 +
 configs/am335x_boneblack_vboot_defconfig   |   1 +
 configs/am335x_evm_defconfig   |   1 +
 configs/am335x_evm_nor_defconfig   |   1 +
 configs/am335x_evm_norboot_defconfig   |   1 +
 configs/am335x_evm_spiboot_defconfig   |   1 +
 configs/am335x_evm_usbspl_defconfig|   1 +
 configs/am335x_igep0033_defconfig  |   1 +
 configs/am335x_shc_defconfig   |   1 +
 configs/am335x_shc_ict_defconfig   |   1 +
 configs/am335x_shc_netboot_defconfig   |   1 +
 configs/am335x_shc_prompt_defconfig|   1 +
 configs/am335x_shc_sdboot_defconfig|   1 +
 configs/am335x_shc_sdboot_prompt_defconfig |   1 +
 configs/am335x_sl50_defconfig  |   1 +
 configs/am3517_crane_defconfig |   1 +
 configs/am3517_evm_defconfig   |   1 +
 configs/am43xx_evm_defconfig   |   1 +
 configs/am43xx_evm_ethboot_defconfig   |   1 +
 configs/am43xx_evm_qspiboot_defconfig  |   1 +
 configs/am43xx_evm_usbhost_boot_defconfig  |   1 +
 configs/am43xx_hs_evm_defconfig|   1 +
 configs/am57xx_evm_defconfig   |   1 +
 configs/am57xx_evm_nodt_defconfig  |   1 +
 configs/am57xx_hs_evm_defconfig|   1 +
 configs/apf27_defconfig|   1 +
 configs/apx4devkit_defconfig   |   1 +
 configs/arndale_defconfig  |   1 +
 configs/axs101_defconfig   |   1 +
 configs/axs103_defconfig   |   1 +
 configs/birdland_bav335a_defconfig |   1 +
 configs/birdland_bav335b_defconfig |   1 +
 configs/brppt1_mmc_defconfig   |   1 +
 configs/brppt1_spi_defconfig   |   1 +
 configs/brxre1_defconfig   |   1 +
 configs/cairo_defconfig|   1 +
 

[U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/clock_manager.c  | 752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 954 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * 

[U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/clock_manager.c  | 752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 954 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * 

[U-Boot] [PATCH v4 27/28] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

[Chee Tien Fong]

From: Tien Fong Chee 

This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/spl.c | 79 +++--
 1 file changed, 76 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..d381904 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -19,37 +19,58 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define BOOTINFO_BSEL_SHIFT0
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define BOOTINFO_BSEL_SHIFT12
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(_regs->bootinfo);
 
-   switch (bsel & 0x7) {
+   switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
case 0x2:   /* NAND Flash (1.8V) */
case 0x3:   /* NAND Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
return BOOT_DEVICE_NAND;
case 0x4:   /* SD/MMC External Transceiver (1.8V) */
case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+#endif
return BOOT_DEVICE_MMC1;
case 0x6:   /* QSPI Flash (1.8V) */
case 0x7:   /* QSPI Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+#endif
return BOOT_DEVICE_SPI;
default:
printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -68,6 +89,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, _regs->lwhps2fpgaregs);
@@ -182,3 +204,54 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+   memset(__bss_start, 0, __bss_end - __bss_start);
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+   /* We need to access to FDT as this stage */
+   /* FDT is at end of image */
+   gd->fdt_blob = (void *)(__bss_end);
+   /* Check whether we have a valid FDT or not. */
+   if (fdtdec_prepare_fdt()) {
+   panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+   "doc/README.fdt-control");
+   }
+#endif /* CONFIG_OF_CONTROL */
+
+   /* Initialize the timer */
+   timer_init();
+
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   reset_deassert_uart();
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+#endif
-- 
2.2.0

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[U-Boot] [PATCH v4 28/28] arm: socfpga: arria10: Enable fpga driver build for SPL.

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa14..c15796b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)PINCTRL)+= pinctrl/
 obj-$(CONFIG_$(SPL_)RAM)   += ram/
 
 ifdef CONFIG_SPL_BUILD
-
+obj-$(CONFIG_FPGA) += fpga/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-- 
2.2.0

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[U-Boot] [PATCH v4 26/28] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/pinmux.h |  17 +
 arch/arm/mach-socfpga/pinmux.c  | 104 
 2 files changed, 121 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux.c

diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..ff54caa
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_PINMUX_H_
+#define_PINMUX_H_
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c
new file mode 100644
index 000..d45722f
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux.c
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+static int __do_pinctr_pins(const void *blob, int child, const char 
*node_name);
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name);
+
+static int __do_pinctr_pins(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", );
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins",
+   );
+   if (cell != NULL) {
+   debug("%p %d\n", cell, len);
+   for (;len > 0; len -= (2*sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   }
+   return 1;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return 2;
+
+   node_name = fdt_get_name(blob, child, );
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name)) {
+   __do_pinctr_pins(blob, child, node_name);
+   return(0);
+   }
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, );
+   }
+
+   return 1;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return 2;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return 3;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return 2;
+
+   return 0;
+}
-- 
2.2.0

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[U-Boot] [PATCH v4 22/28] arm: socfpga: arria10: Added support for Arria 10 socdk

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/system_manager.c  |  4 ++-
 drivers/fpga/socfpga.c  |  7 +++--
 include/configs/socfpga_arria10_socdk.h | 56 -
 include/configs/socfpga_common.h| 33 ---
 4 files changed, 71 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 9e1c3fd..e1f0082 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -11,8 +11,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index bfefafd..7fd922e 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
}
 
/* Prior programming the FPGA, all bridges need to be shut off */
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Disable all signals from hps peripheral controller to fpga */
writel(0, _regs->fpgaintfgrp_module);
+#endif
 
/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
index 577f60f..105c4c0 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2015 Altera Corporation 
+ *  Copyright (C) 2015-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0
  */
@@ -8,31 +8,20 @@
 #define __CONFIG_SOCFGPA_ARRIA10_H__
 
 #include 
+
 /* U-Boot Commands */
-#define CONFIG_SYS_NO_FLASH
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
 
-/*
- * Memory configurations
- */
-#define PHYS_SDRAM_1_SIZE  0x200
-
 /* Booting Linux */
-#define CONFIG_BOOTDELAY   3
 #define CONFIG_BOOTFILE"zImage"
 #define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
@@ -40,24 +29,30 @@
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /*
- * Display CPU and Board Info
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
+/*
+ * U-Boot console configurations
  */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DOS_PARTITION
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x8000
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9031
-
 #endif
 
+/*
+ * U-Boot environment configurations
+ */
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
-#define CONFIG_ENV_OFFSET  512/* just after the MBR */
 
 /*
  * arguments passed to the bootz command. The value of
@@ -89,6 +84,23 @@
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
"bootm ${loadaddr} - ${fdt_addr}\0"
 
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/*
+ * 

[U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/clock_manager.c  | 752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 954 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * 

[U-Boot] [PATCH v4 24/28] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile|   6 +-
 arch/arm/mach-socfpga/include/mach/misc.h |  32 ++
 arch/arm/mach-socfpga/misc.c  | 427 +-
 arch/arm/mach-socfpga/misc_arria10.c  | 255 +++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c} | 232 ++
 5 files changed, 337 insertions(+), 615 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (66%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b8fcf6e..1ab68be 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,9 +9,11 @@
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o 
\
+   clock_manager_arria10.o pinmux.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
-   reset_manager_gen5.o
+   reset_manager_gen5.o misc_gen5.o \
+   clock_manager_gen5.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..045268d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define_MISC_H_
+
+extern void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode);
+
+struct bsel{
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+extern void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 510aa1d..7fd5c0e 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,45 +7,33 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#include 
-#else
-#include 
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#else
-static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
-   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
-static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
-   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
-#endif
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bselbsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -84,219 +72,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id,
-const u32 phymode)
-{
-   

[U-Boot] [PATCH v4 23/28] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee Tien Fong]

From: Tien Fong Chee 

Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile |  16 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 155 ++--
 arch/arm/mach-socfpga/reset_manager.c  | 112 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 407 +
 .../{reset_manager.c => reset_manager_gen5.c}  |  94 ++---
 5 files changed, 570 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b8fcf6e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,21 +2,27 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2016 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+   reset_manager_gen5.o
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
+   wrap_pinmux_config.o wrap_sdram_config.o
+endif
 
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6225118..13f9731 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,15 +7,27 @@
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_
 
+/* Common function prototypes */
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
 void socfpga_bridges_reset(int enable);
-
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+void reset_deassert_peripherals_handoff(void);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+void reset_assert_uart(void);
+void reset_deassert_uart(void);
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -29,40 +41,40 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
-   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
-   u32 brg_mod_reset;
-   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
-   u32 coldmodrst;
-   u32 nrstmodrst;
-   u32 dbgmodrst;
-   u32 mpuwarmmask;
-   u32 per0warmmask;
-   u32 per1warmmask;
-   u32 brgwarmmask;
-   u32 syswarmmask;
-   u32 nrstwarmmask;
-   u32 l3warmmask;
-   u32 tststa;
-   u32 tstscratch;
-   u32 hdsktimeout;
-   u32 hmcintr;
-   u32 

[U-Boot] [PATCH v4 19/28] arm: socfpga: arria10: Enable SPL for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

This patch enables SPL build and implementation for Arria 10.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80c5992..0ed36cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+   select SUPPORT_SPL
select OF_CONTROL
-   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+   select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
-- 
2.2.0

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[U-Boot] [PATCH v4 18/28] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

[Chee Tien Fong]

From: Tien Fong Chee 

This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_arria10.dtsi  | 859 +
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 479 
 4 files changed, 1370 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3ee608b..024aa5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -137,7 +137,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_arria10_socdk_sdmmc.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
new file mode 100644
index 000..f63c4b4
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -0,0 +1,859 @@
+/*
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   ethernet2 = 
+   serial0 = 
+   serial1 = 
+   timer0 = 
+   timer1 = 
+   timer2 = 
+   timer3 = 
+   spi0 = 
+   spi1 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: intc@d000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <>;
+   ranges;
+
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   pdma: pdma@ffda1000 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda1000 0x1000>;
+   interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+<0 84 IRQ_TYPE_LEVEL_HIGH>,
+<0 85 IRQ_TYPE_LEVEL_HIGH>,
+<0 86 IRQ_TYPE_LEVEL_HIGH>,
+<0 87 IRQ_TYPE_LEVEL_HIGH>,
+<0 88 IRQ_TYPE_LEVEL_HIGH>,
+<0 89 IRQ_TYPE_LEVEL_HIGH>,
+<0 90 IRQ_TYPE_LEVEL_HIGH>,
+<0 91 IRQ_TYPE_LEVEL_HIGH>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clocks = <_main_clk>;
+   clock-names = "apb_pclk";
+   };
+   };
+
+   clkmgr@ffd04000 {
+   compatible = "altr,clk-mgr";
+   reg = <0xffd04000 0x1000>;
+   reg-names = 

[U-Boot] [PATCH v4 21/28] arm: socfpga: arria10: Added some hardware base address for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 902c321..2d66580 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -36,10 +36,13 @@
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
-- 
2.2.0

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[U-Boot] [PATCH v4 20/28] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee Tien Fong]

From: Tien Fong Chee 

These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/fdtdec.h | 8 
 lib/fdtdec.c | 8 
 2 files changed, 16 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..73e3a46 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,14 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_SUNXI_NAND,  /* SUNXI NAND controller */
+   COMPAT_ALTERA_SOCFPGA_CLK,  /* SoCFPGA Clock initialization */
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,   /* pinctrl-single */
+   COMPAT_ALTERA_SOCFPGA_H2F_BRG,  /* Arria10 hps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 lwhps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_F2H_BRG,  /* Arria10 fpga2hps bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR0,   /* Arria10 fpga2SDRAM0 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR1,   /* Arria10 fpga2SDRAM1 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR2,   /* Arria10 fpga2SDRAM2 bridge */
 
COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 81f47ef..ebe4a9a 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+   COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+   COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+   COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
2.2.0

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[U-Boot] [PATCH v4 17/28] arm: socfpga: arria10: update dwmac reset function to support Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.

Update the dwmac_deassert_reset function to support both GEN5 and Arria10
devices.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/system_manager.h |  4 +---
 arch/arm/mach-socfpga/misc.c| 14 ++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 9ca889a..831ba4a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -133,9 +133,7 @@ struct socfpga_system_manager {
u32  usb0_l3master;
u32  usb1_l3master;
u32  emac_global;
-   u32  emac0;
-   u32  emac1;
-   u32  emac2;
+   u32  emac[3];
u32  _pad_0x50_0x5f[4];
u32  fpgaintf_en_global;
u32  fpgaintf_en_0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c97caea..510aa1d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -21,7 +21,11 @@
 #include 
 #include 
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#else
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
} else if (of_reset_id == EMAC1_RESET) {
physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
reset = SOCFPGA_RESET(EMAC1);
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+#endif
} else {
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
return;
}
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* configure to PHY interface select choosed */
clrsetbits_le32(_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
phymode << physhift);
+#else
+   clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+#endif
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
2.2.0

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[U-Boot] [PATCH v4 16/28] arm: socfpga: add reset manager defines for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.

[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++
 1 file changed, 103 insertions(+)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h 
b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 000..7619ca2
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET  2
+#define SCUPER_RESET   3
+
+/* PER0MODRST */
+#define EMAC0_RESET32
+#define EMAC1_RESET33
+#define EMAC2_RESET34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET39
+#define EMAC0_OCP_RESET40
+#define EMAC1_OCP_RESET41
+#define EMAC2_OCP_RESET42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET47
+#define DMA_RESET  48
+#define SPIM0_RESET49
+#define SPIM1_RESET50
+#define SPIS0_RESET51
+#define SPIS1_RESET52
+#define DMA_OCP_RESET  53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET   56
+#define DMAIF1_RESET   57
+#define DMAIF2_RESET   58
+#define DMAIF3_RESET   59
+#define DMAIF4_RESET   60
+#define DMAIF5_RESET   61
+#define DMAIF6_RESET   62
+#define DMAIF7_RESET   63
+
+/* PER1MODRST */
+#define L4WD0_RESET64
+#define L4WD1_RESET65
+#define L4SYSTIMER0_RESET  66
+#define L4SYSTIMER1_RESET  67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET80
+#define UART1_RESET81
+/* 82-87 is reserved */
+#define GPIO0_RESET88
+#define GPIO1_RESET89
+#define GPIO2_RESET90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET   97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET99
+#define F2SSDRAM1_RESET100
+#define F2SSDRAM2_RESET101
+#define DDRSCH_RESET   102
+
+/* SYSMODRST*/
+#define ROM_RESET  128
+#define OCRAM_RESET129
+/* 130 is reserved */
+#define FPGAMGR_RESET  131
+#define S2F_RESET  132
+#define SYSDBG_RESET   133
+#define OCRAM_OCP_RESET134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET   160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET  163
+#define TIMESTAMPCOLD_RESET164
+#define TAPCOLD_RESET  165
+#define HMCCOLD_RESET  166
+#define IOMGRCOLD_RESET167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET192
+
+/* DBGMODRST */
+#define DBG_RESET  224
+#endif
-- 
2.2.0

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[U-Boot] [PATCH v4 14/28] arm: socfpga: arria10: remove board_init and s_init

[Chee Tien Fong]

From: Tien Fong Chee 

These functions are already in arch/arm/mach-socfpga/board.c

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 board/altera/arria10-socdk/socfpga.c | 17 -
 1 file changed, 17 deletions(-)

diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
index abedc22..8516633 100644
--- a/board/altera/arria10-socdk/socfpga.c
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -5,20 +5,3 @@
  */
 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void)
-{
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-   /* Address of boot parameters for ATAG (if ATAG is used) */
-   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-   return 0;
-}
-- 
2.2.0

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[U-Boot] [PATCH v4 15/28] arm: socfpga: combine clrbits/setbits into a single clrsetbits

[Chee Tien Fong]

From: Tien Fong Chee 

There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/misc.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 2645129..c97caea 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
return;
}
 
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
/* configure to PHY interface select choosed */
-   setbits_le32(_regs->emacgrp_ctrl,
-phymode << physhift);
+   clrsetbits_le32(_regs->emacgrp_ctrl,
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
+   phymode << physhift);
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
2.2.0

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[U-Boot] [PATCH v4 13/28] arm: socfpga: arria10 fpga does not have bridges mapped

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10 device, the bridges are not mapped through the interconnect.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/fpga/socfpga.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..bfefafd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset(1);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Unmap the bridges from NIC-301 */
writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
 
/* Initialize the FPGA Manager */
status = fpgamgr_program_init();
-- 
2.2.0

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[U-Boot] [PATCH v4 12/28] arm: socfpga: arria10: don't build GEN5 sdram for arria10

[Chee Tien Fong]

From: Tien Fong Chee 

The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/Kconfig  | 2 ++
 drivers/ddr/Kconfig  | 1 +
 drivers/ddr/altera/Kconfig   | 6 ++
 include/configs/socfpga_common.h | 5 -
 4 files changed, 9 insertions(+), 5 deletions(-)
 create mode 100644 drivers/ddr/Kconfig
 create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 0e5d97d..3e6bbac 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/ddr/fsl/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 000..b764add
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 000..9554da7
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,6 @@
+config ALTERA_SDRAM
+   bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
+   default y if TARGET_SOCFPGA_GEN5
+   help
+ This is for building the SDRAM controller for the Arria5/Cyclone5
+ devices.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 31f1338..bbbde1e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -77,11 +77,6 @@
 #define CONFIG_SYS_PL310_BASE  SOCFPGA_MPUL2_ADDRESS
 
 /*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
  * EPCS/EPCQx1 Serial Flash Controller
  */
 #ifdef CONFIG_ALTERA_SPI
-- 
2.2.0

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[U-Boot] [PATCH v4 09/28] arm: socfpga: add define for bootinfo bsel bit shift

[Chee Tien Fong]

From: Tien Fong Chee 

On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.

Suggested-by: Marek Vasut 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++
 arch/arm/mach-socfpga/misc.c| 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e688c50..9ca889a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -203,8 +203,10 @@ struct socfpga_system_manager {
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
 #else
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
 #endif
 
 #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c1e5969..2645129 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+   const u32 bsel = (readl(_regs->bootinfo) >>
+ SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-   const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
 #else
-   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
puts("CPU:   Altera SoCFPGA Arria 10\n");
 #endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
-- 
2.2.0

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[U-Boot] [PATCH v4 11/28] arm: socfpga: wrap system manager functions for A5/C5 devices

[Chee Tien Fong]

From: Tien Fong Chee 

The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/system_manager.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 75a65f3..9e1c3fd 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs =
  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void populate_sysmgr_fpgaintf_module(void)
 {
uint32_t handoff_val = 0;
@@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable)
clrbits_le32(_regs->romcodegrp_ctrl,
 SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
2.2.0

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[U-Boot] [PATCH v4 08/28] arm: socfpga: arria10: add config option build for arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/Kconfig  |  4 ++--
 arch/arm/mach-socfpga/Kconfig | 10 ++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0ed36cd..80c5992 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL
+   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
-   select SPL_OF_CONTROL
+   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
select DM
select DM_SPI_FLASH
select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6991af8..d9a5178 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+   bool
+
 config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_DENX_MCVEVK
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -86,6 +93,7 @@ endchoice
 
 config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -98,6 +106,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -111,6 +120,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
-- 
2.2.0

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[U-Boot] [PATCH v4 10/28] arm: socfpga: arria10: add reset manager for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++
 arch/arm/mach-socfpga/reset_manager.c  | 24 +++-
 2 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..6225118 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
+#else
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
+   u32 brg_mod_reset;
+   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -75,6 +113,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c 
b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..d0ff6c4 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base 
=
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
 void socfpga_per_reset(u32 reset, int set)
 {
const void *reg;
@@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
  */
 void 

[U-Boot] [PATCH v4 06/28] arm: socfpga: arria10: add socfpga_arria10_socdk config

[Chee Tien Fong]

From: Tien Fong Chee 

Add config for the Arria10 SoC Development Kit.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Acked-by: Marek Vasut 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/configs/socfpga_arria10_socdk.h | 94 +
 1 file changed, 94 insertions(+)
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 000..577f60f
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include 
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1_SIZE  0x200
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY   3
+#define CONFIG_BOOTFILE"zImage"
+#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR0x0100
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
+#define CONFIG_ENV_OFFSET  512/* just after the MBR */
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "verify=n\0" \
+   "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "bootimage=zImage\0" \
+   "fdt_addr=100\0" \
+   "fdtimage=socfpga.dtb\0" \
+   "fsloadcmd=ext2load\0" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "mmcroot=/dev/mmcblk0p2\0" \
+   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${mmcroot} rw rootwait;" \
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "mmcload=mmc rescan;" \
+   "load mmc 0:1 ${loadaddr} ${bootimage};" \
+   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+   "qspiroot=/dev/mtdblock0\0" \
+   "qspirootfstype=jffs2\0" \
+   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+   "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include 
+#endif /* __CONFIG_H */
-- 
2.2.0

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[U-Boot] [PATCH v4 07/28] arm: socfpga: arria10: add socfpga_arria10_defconfig

[Chee Tien Fong]

From: Tien Fong Chee 

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Acked-by: Marek Vasut 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 configs/socfpga_arria10_defconfig | 24 
 1 file changed, 24 insertions(+)
 create mode 100644 configs/socfpga_arria10_defconfig

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
new file mode 100644
index 000..755bb66
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
2.2.0

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[U-Boot] [PATCH v4 04/28] arm: socfpga: arria10: add system manager defines

[Chee Tien Fong]

From: Tien Fong Chee 

Add system manager defines for Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 .../arm/mach-socfpga/include/mach/system_manager.h | 122 +
 1 file changed, 122 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..e688c50 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable);
 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_system_manager {
/* System Manager Module */
u32 siliconid1; /* 0x00 */
@@ -115,6 +116,77 @@ struct socfpga_system_manager {
u32 _pad_0x734;
u32 spim0usefpga;   /* 0x738 */
 };
+#else /* Arria10 System Manager */
+struct socfpga_system_manager {
+   u32  siliconid1;
+   u32  siliconid2;
+   u32  wddbg;
+   u32  bootinfo;
+   u32  mpu_ctrl_l2_ecc;
+   u32  _pad_0x14_0x1f[3];
+   u32  dma;
+   u32  dma_periph;
+   u32  sdmmcgrp_ctrl;
+   u32  sdmmc_l3master;
+   u32  nand_bootstrap;
+   u32  nand_l3master;
+   u32  usb0_l3master;
+   u32  usb1_l3master;
+   u32  emac_global;
+   u32  emac0;
+   u32  emac1;
+   u32  emac2;
+   u32  _pad_0x50_0x5f[4];
+   u32  fpgaintf_en_global;
+   u32  fpgaintf_en_0;
+   u32  fpgaintf_en_1;
+   u32  fpgaintf_en_2;
+   u32  fpgaintf_en_3;
+   u32  _pad_0x74_0x7f[3];
+   u32  noc_addr_remap_value;
+   u32  noc_addr_remap_set;
+   u32  noc_addr_remap_clear;
+   u32  _pad_0x8c_0x8f;
+   u32  ecc_intmask_value;
+   u32  ecc_intmask_set;
+   u32  ecc_intmask_clr;
+   u32  ecc_intstatus_serr;
+   u32  ecc_intstatus_derr;
+   u32  mpu_status_l2_ecc;
+   u32  mpu_clear_l2_ecc;
+   u32  mpu_status_l1_parity;
+   u32  mpu_clear_l1_parity;
+   u32  mpu_set_l1_parity;
+   u32  _pad_0xb8_0xbf[2];
+   u32  noc_timeout;
+   u32  noc_idlereq_set;
+   u32  noc_idlereq_clr;
+   u32  noc_idlereq_value;
+   u32  noc_idleack;
+   u32  noc_idlestatus;
+   u32  fpga2soc_ctrl;
+   u32  _pad_0xdc_0xff[9];
+   u32  tsmc_tsel_0;
+   u32  tsmc_tsel_1;
+   u32  tsmc_tsel_2;
+   u32  tsmc_tsel_3;
+   u32  _pad_0x110_0x200[60];
+   u32  romhw_ctrl;
+   u32  romcode_ctrl;
+   u32  romcode_cpu1startaddr;
+   u32  romcode_initswstate;
+   u32  romcode_initswlastld;
+   u32  _pad_0x214_0x217;
+   u32  warmram_enable;
+   u32  warmram_datastart;
+   u32  warmram_length;
+   u32  warmram_execution;
+   u32  warmram_crc;
+   u32  _pad_0x22c_0x22f;
+   u32  isw_handoff[8];
+   u32  romcode_bootromswstate[8];
+};
+#endif
 
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1)
@@ -146,4 +218,54 @@ struct socfpga_system_manager {
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V   0x1
+#define VOLTAGE_SEL_2P5V   0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE  0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V   2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE  0
+#define WK_PU_ENABLE   1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT  PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT  PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT0x10
+#define PD_DRV_STRG_DEFAULT0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB0
+#define PD_SLW_RT_LSB  5
+#define PU_DRV_STRG_LSB8
+#define PU_SLW_RT_LSB  13
+#define WK_PU_LSB  16
+#define INPUT_BUF_LSB  17
+#define BIAS_TRIM_LSB  19
+#define VOLTAGE_SEL_LSB0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK   0x0010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK  0x0001
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK  0x0010
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK  0x0100

[U-Boot] [PATCH v4 03/28] arm: socfpga: arria10: add board files for the Arria10 SoCDK

[Chee Tien Fong]

From: Tien Fong Chee 

Add minimal support for the Arria10 SoCDK.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 board/altera/arria10-socdk/Kconfig   | 18 ++
 board/altera/arria10-socdk/Makefile  |  7 +++
 board/altera/arria10-socdk/socfpga.c | 24 
 3 files changed, 49 insertions(+)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig 
b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+   default "armv7"
+
+config SYS_BOARD
+   default "socfpga_arria10"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile 
b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000..abedc22
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+   /* Address of boot parameters for ATAG (if ATAG is used) */
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+   return 0;
+}
-- 
2.2.0

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[U-Boot] [PATCH v4 02/28] arm: socfpga: arria10: add sdram defines for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the structures for the SDRAM controller on Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 +
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
new file mode 100644
index 000..0403531
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SOCFPGA_SDRAM_A10_H_
+#define_SOCFPGA_SDRAM_A10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 caltiming4;
+   

[U-Boot] [PATCH v4 05/28] arm: socfpga: arria10: add misc functions for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/misc.c | 51 
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..c1e5969 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#else
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
@@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
+#else
+   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
+   puts("CPU:   Altera SoCFPGA Arria 10\n");
+#endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
return 0;
 }
@@ -338,6 +351,7 @@ int arch_cpu_init(void)
return 0;
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
@@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 
return 0;
 }
+#else
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+   /* Put OCRAM in non-secure */
+   writel(0x003f, _fw_ocram_base->region0);
+   writel(0x1, _fw_ocram_base->enable);
+
+   /* Put DDR in non-secure */
+   writel(0x, _fw_ddr_l3_base->hpsregion0addr);
+   writel(0x1, _fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+   initialize_security_policies();
+
+   /* Configure the L2 controller to make SDRAM start at 0 */
+   writel(0x1, >pl310_addr_filter_start);
+
+   /* assert reset to all except L4WD0 and L4TIMER0 */
+   socfpga_per_reset_all();
+
+   /* configuring the clock based on handoff */
+   /* TODO: Add call to cm_basic_init() */
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
+   return 0;
+}
+#endif
 
 U_BOOT_CMD(
bridge, 2, 1, do_bridge,
-- 
2.2.0

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[U-Boot] [PATCH v4 01/28] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add remaining 3 I2C base addresses for the Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Reviewed-by: Stefan Roese 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..902c321 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -29,6 +29,9 @@
 #define SOCFPGA_MPUL2_ADDRESS  0xf000
 #define SOCFPGA_I2C0_ADDRESS   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
-- 
2.2.0

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[U-Boot] [PATCH v4 00/28] *** SUBJECT HERE ***

[Chee Tien Fong]

From: Tien Fong Chee 

*** BLURB HERE ***

Tien Fong Chee (28):
  arm: socfpga: arria10: add additional i2c nodes for Arria10
  arm: socfpga: arria10: add sdram defines for Arria10
  arm: socfpga: arria10: add board files for the Arria10 SoCDK
  arm: socfpga: arria10: add system manager defines
  arm: socfpga: arria10: add misc functions for Arria10
  arm: socfpga: arria10: add socfpga_arria10_socdk config
  arm: socfpga: arria10: add socfpga_arria10_defconfig
  arm: socfpga: arria10: add config option build for arria10
  arm: socfpga: add define for bootinfo bsel bit shift
  arm: socfpga: arria10: add reset manager for Arria10
  arm: socfpga: wrap system manager functions for A5/C5 devices
  arm: socfpga: arria10: don't build GEN5 sdram for arria10
  arm: socfpga: arria10 fpga does not have bridges mapped
  arm: socfpga: arria10: remove board_init and s_init
  arm: socfpga: combine clrbits/setbits into a single clrsetbits
  arm: socfpga: add reset manager defines for Arria10
  arm: socfpga: arria10: update dwmac reset function to support Arria10
  ARM:dts: Added device tree for socfpga arria10 development kit sdmmc
  arm: socfpga: arria10: Enable SPL for Arria 10
  arm: socfpga: arria10: Added clock manager and pin mux compat macro
  arm: socfpga: arria10: Added some hardware base address for Arria 10
  arm: socfpga: arria10: Added support for Arria 10 socdk
  arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
  arm: socfpga: arria10: Added miscellaneous drivers for Arria 10
  arm: socfpga: arria10: Added drivers for Arria10 clock manager
  arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins
configuration
  arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
  arm: socfpga: arria10: Enable fpga driver build for SPL.

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_arria10.dtsi  | 859 +++
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 479 +++
 arch/arm/mach-socfpga/Kconfig  |  10 +
 arch/arm/mach-socfpga/Makefile |  18 +-
 arch/arm/mach-socfpga/clock_manager.c  | 752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 954 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   8 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
 arch/arm/mach-socfpga/include/mach/misc.h  |  32 +
 arch/arm/mach-socfpga/include/mach/pinmux.h|  17 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 152 +++-
 arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 
 .../arm/mach-socfpga/include/mach/system_manager.h | 122 +++
 arch/arm/mach-socfpga/misc.c   | 367 +---
 arch/arm/mach-socfpga/misc_arria10.c   | 255 ++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c}  | 178 +---
 arch/arm/mach-socfpga/pinmux.c | 104 +++
 arch/arm/mach-socfpga/reset_manager.c  |  90 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 407 +
 .../{reset_manager.c => reset_manager_gen5.c}  |  82 +-
 arch/arm/mach-socfpga/spl.c|  79 +-
 arch/arm/mach-socfpga/system_manager.c |   6 +-
 board/altera/arria10-socdk/Kconfig |  18 +
 board/altera/arria10-socdk/Makefile|   7 +
 board/altera/arria10-socdk/socfpga.c   |   7 +
 configs/socfpga_arria10_defconfig  |  24 +
 drivers/Kconfig|   2 +
 drivers/Makefile   |   2 +-
 drivers/ddr/Kconfig|   1 +
 drivers/ddr/altera/Kconfig |   6 +
 drivers/fpga/socfpga.c |   9 +-
 include/configs/socfpga_arria10_socdk.h| 106 +++
 include/configs/socfpga_common.h   |  38 +-
 include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 +++
 include/fdtdec.h   |   8 +
 lib/fdtdec.c   |   8 +
 39 files changed, 4937 insertions(+), 1382 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (73%)
 create mode 

Re: [U-Boot] [PATCH 7/7] sunxi: remove bare default for CONFIG_MMC

[Masahiro Yamada]

Hi Jaehoon,


2017-01-10 10:41 GMT+09:00 Jaehoon Chung :
> Hi Masahiro,
>
> On 01/10/2017 10:32 AM, Masahiro Yamada wrote:
>> Hi Jaehoon,
>>
>>
>> 2017-01-10 9:55 GMT+09:00 Jaehoon Chung :
>>> Hi Jagan,
>>>
>>> On 01/01/2017 09:11 PM, Masahiro Yamada wrote:
 The bare default entry is wrong.  Just remove it since the (real)
 entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX".
>>>
>>> Do you have any opinion about this patch?
>>> I want to know your ack or review.
>>> If there is no objection, i will pick this patch on my repository.
>>>
>>> Best Regards,
>>> Jaehoon Chung
>>
>> If you are going to pick up this series,
>> please be careful with invisible conflicts.
>> Applying the series as-is will cause misconversion
>> because it is already outdated.
>>
>> You can re-generate the series with commands in each commit-log,
>> or I can re-send the series based on the v2017.01 tag if requested.
>
> Yes, i'm running buildman with these patches on v2017.01 tag.
> If you can resend the patches, it's more helpful to me with Marek's 
> reviewed-tag.
> To prevent the conflict, i think it's good to apply ASAP.
>
> Best Regards,
> Jaehoon Chung
>


I re-generated the entire series on top of the v2017.01 tag.


The difference from the v1 was only
configs/cl-som-am57x_defconfig




-- 
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH v2 5/7] ARM: davinci: remove unused CONFIG_DAVINCI_MMC_SD1

[Masahiro Yamada]

This CONFIG is not referenced from anywhere.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Marek Vasut 
---

Changes in v2: None

 include/configs/da850evm.h | 1 -
 include/configs/legoev3.h  | 1 -
 2 files changed, 2 deletions(-)

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index ceb9cea..2eabc00 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -313,7 +313,6 @@
 
 /* SD/MMC configuration */
 #ifndef CONFIG_USE_NOR
-#define CONFIG_DAVINCI_MMC_SD1
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DAVINCI_MMC
 #endif
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 3b118bb..fab1831 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -215,7 +215,6 @@
 #define CONFIG_ENV_SIZE(16 << 10)
 
 /* SD/MMC configuration */
-#define CONFIG_DAVINCI_MMC_SD1
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DAVINCI_MMC
 
-- 
2.7.4

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[U-Boot] [PATCH v2 1/7] ARM: socfpga: remove unused CONFIG option and cleanup README.socfpga

[Masahiro Yamada]

CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH is defined in the socfpga_common.h,
but not referenced at all.  Remove.

Also, clean-up the README.socfpga.  CONFIG_MMC should not be defined
in the header since it was moved to Kconfig by commit c27269953b94
("mmc: complete unfinished move of CONFIG_MMC").  I see no grep hit
for the others.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Marek Vasut 
---

Changes in v2: None

 doc/README.socfpga   | 26 --
 include/configs/socfpga_common.h |  1 -
 2 files changed, 27 deletions(-)

diff --git a/doc/README.socfpga b/doc/README.socfpga
index cfcbbfe..92942c9 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -14,12 +14,6 @@ socfpga_dw_mmc
 Here are macro and detailed configuration required to enable DesignWare SDMMC
 controller support within SOCFPGA
 
-#define CONFIG_MMC
--> To enable the SD MMC framework support
-
-#define CONFIG_SDMMC_BASE  (SOCFPGA_SDMMC_ADDRESS)
--> The base address of CSR register for DesignWare SDMMC controller
-
 #define CONFIG_GENERIC_MMC
 -> Enable the generic MMC driver
 
@@ -31,23 +25,3 @@ controller support within SOCFPGA
 
 #define CONFIG_SOCFPGA_DWMMC
 -> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
-
-#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH1024
--> The FIFO depth for SOCFPGA DesignWare SDMMC controller
-
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL3
--> Phase-shifted clock of sdmmc_clk for controller to drive command and data to
-the card to meet hold time requirements. SD clock is running at 50MHz and
-drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time
-is 135 / 360 * 20ns = 7.5ns.
-
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL0
--> Phase-shifted clock of sdmmc_clk used to sample the command and data from
-the card
-
-#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4
--> Bus width of data line which either 1, 4 or 8 and based on board routing.
-
-#define CONFIG_SOCFPGA_DWMMC_BUS_HZ5000
--> The clock rate to controller. Do note the controller have a wrapper which
-divide the clock from PLL by 4.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 31f1338..dda1159 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -146,7 +146,6 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DWMMC
 #define CONFIG_SOCFPGA_DWMMC
-#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH1024
 /* FIXME */
 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256 /* FIXME -- SPL only? */
-- 
2.7.4

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[U-Boot] [PATCH v2 0/7] mmc: more Kconfig conversion, MMC related clean-up

[Masahiro Yamada]

This series is based on commit 3d3a74cc8c.
Each git-log describes how to re-generate it.
Buildman test passed.


Changes in v2:
  - Re-generate based on v2017.01

Masahiro Yamada (7):
  ARM: socfpga: remove unused CONFIG option and cleanup README.socfpga
  mmc: rename CONFIG_ROCKCHIP_DWMMC to CONFIG_MMC_DW_ROCKCHIP
  mmc: move CONFIG_DWMMC to Kconfig, renaming to CONFIG_MMC_DW
  mmc: move DesignWare-based drivers to Kconfig
  ARM: davinci: remove unused CONFIG_DAVINCI_MMC_SD1
  mmc: move more driver config options to Kconfig
  ARM: sunxi: remove bare default for CONFIG_MMC

 arch/arm/cpu/arm926ejs/mx27/generic.c  |  8 +--
 arch/arm/include/asm/arch-mx27/imx-regs.h  |  4 +-
 arch/arm/mach-davinci/da830_pinmux.c   |  2 +-
 arch/arm/mach-omap2/am33xx/board.c |  2 +-
 arch/arm/mach-tegra/board2.c   |  2 +-
 board/armadeus/apf27/apf27.c   |  2 +-
 board/avionic-design/common/tamonten.c |  2 +-
 board/compal/paz00/paz00.c |  2 +-
 board/davinci/da8xxevm/da850evm.c  | 12 ++--
 board/davinci/da8xxevm/omapl138_lcdk.c | 10 ++--
 board/hisilicon/hikey/hikey.c  |  2 +-
 board/htkw/mcx/mcx.c   |  2 +-
 board/lego/ev3/legoev3.c   |  4 +-
 board/nvidia/cardhu/cardhu.c   |  2 +-
 board/nvidia/dalmore/dalmore.c |  2 +-
 board/nvidia/harmony/harmony.c |  2 +-
 board/nvidia/seaboard/seaboard.c   |  2 +-
 board/nvidia/whistler/whistler.c   |  2 +-
 board/samsung/common/board.c   |  2 +-
 board/sunxi/Kconfig|  4 --
 board/technexion/twister/twister.c |  2 +-
 board/teejet/mt_ventoux/mt_ventoux.c   |  2 +-
 board/toradex/colibri_t20/colibri_t20.c|  2 +-
 configs/am335x_baltos_defconfig|  1 +
 configs/am335x_boneblack_defconfig |  1 +
 configs/am335x_boneblack_vboot_defconfig   |  1 +
 configs/am335x_evm_defconfig   |  1 +
 configs/am335x_evm_nor_defconfig   |  1 +
 configs/am335x_evm_norboot_defconfig   |  1 +
 configs/am335x_evm_spiboot_defconfig   |  1 +
 configs/am335x_evm_usbspl_defconfig|  1 +
 configs/am335x_igep0033_defconfig  |  1 +
 configs/am335x_shc_defconfig   |  1 +
 configs/am335x_shc_ict_defconfig   |  1 +
 configs/am335x_shc_netboot_defconfig   |  1 +
 configs/am335x_shc_prompt_defconfig|  1 +
 configs/am335x_shc_sdboot_defconfig|  1 +
 configs/am335x_shc_sdboot_prompt_defconfig |  1 +
 configs/am335x_sl50_defconfig  |  1 +
 configs/am3517_crane_defconfig |  1 +
 configs/am3517_evm_defconfig   |  1 +
 configs/am43xx_evm_defconfig   |  1 +
 configs/am43xx_evm_ethboot_defconfig   |  1 +
 configs/am43xx_evm_qspiboot_defconfig  |  1 +
 configs/am43xx_evm_usbhost_boot_defconfig  |  1 +
 configs/am43xx_hs_evm_defconfig|  1 +
 configs/am57xx_evm_defconfig   |  1 +
 configs/am57xx_evm_nodt_defconfig  |  1 +
 configs/am57xx_hs_evm_defconfig|  1 +
 configs/apf27_defconfig|  1 +
 configs/apx4devkit_defconfig   |  1 +
 configs/arndale_defconfig  |  1 +
 configs/axs101_defconfig   |  1 +
 configs/axs103_defconfig   |  1 +
 configs/birdland_bav335a_defconfig |  1 +
 configs/birdland_bav335b_defconfig |  1 +
 configs/brppt1_mmc_defconfig   |  1 +
 configs/brppt1_spi_defconfig   |  1 +
 configs/brxre1_defconfig   |  1 +
 configs/cairo_defconfig|  1 +
 configs/chromebit_mickey_defconfig |  3 +-
 configs/chromebook_jerry_defconfig |  3 +-
 configs/chromebook_minnie_defconfig|  3 +-
 configs/cl-som-am57x_defconfig |  1 +
 configs/cm_t335_defconfig  |  1 +
 configs/cm_t3517_defconfig |  1 +
 configs/cm_t35_defconfig   |  1 +
 configs/cm_t43_defconfig   |  1 +
 configs/cm_t54_defconfig   |  1 +
 configs/devkit8000_defconfig   |  1 +
 configs/dra7xx_evm_defconfig   |  1 +
 configs/dra7xx_hs_evm_defconfig|  1 +
 configs/draco_defconfig|  1 +
 configs/duovero_defconfig  |  1 +
 configs/eco5pk_defconfig   |  1 +
 configs/etamin_defconfig   |  1 +
 configs/evb-rk3036_defconfig   |  3 +-
 configs/evb-rk3288_defconfig   |  3 +-
 configs/evb-rk3399_defconfig   |  3 +-
 configs/fennec-rk3288_defconfig|  3 +-
 configs/firefly-rk3288_defconfig   |  3 +-
 configs/hikey_defconfig|  2 +
 configs/igep0020_defconfig |  1 +
 configs/igep0030_defconfig |  1 +
 configs/igep0032_defconfig |  1 +
 configs/k2g_evm_defconfig  |  

[U-Boot] [PATCH v2 3/7] mmc: move CONFIG_DWMMC to Kconfig, renaming to CONFIG_MMC_DW

[Masahiro Yamada]

This commit was created as follows:

[1] Rename the option with the following command:
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e 's/CONFIG_DWMMC/CONFIG_MMC_DW/g'

[2] create the entry for MMC_DW in drivers/mmc/Kconfig
(the prompt and help were copied from Linux)

[3] run "tools/moveconfig.py -y MMC_DW"

[4] add "depends on MMC_DW" to the MMC_DW_ROCKCHIP entry

[5] Clean-up doc/README.socfpga by hand

Signed-off-by: Masahiro Yamada 
Reviewed-by: Marek Vasut 
---

Changes in v2: None

 board/hisilicon/hikey/hikey.c  | 2 +-
 board/samsung/common/board.c   | 2 +-
 configs/arndale_defconfig  | 1 +
 configs/axs101_defconfig   | 1 +
 configs/axs103_defconfig   | 1 +
 configs/chromebit_mickey_defconfig | 1 +
 configs/chromebook_jerry_defconfig | 1 +
 configs/chromebook_minnie_defconfig| 1 +
 configs/evb-rk3036_defconfig   | 1 +
 configs/evb-rk3288_defconfig   | 1 +
 configs/evb-rk3399_defconfig   | 1 +
 configs/fennec-rk3288_defconfig| 1 +
 configs/firefly-rk3288_defconfig   | 1 +
 configs/hikey_defconfig| 1 +
 configs/kylin-rk3036_defconfig | 1 +
 configs/miniarm-rk3288_defconfig   | 1 +
 configs/odroid-xu3_defconfig   | 1 +
 configs/odroid_defconfig   | 1 +
 configs/origen_defconfig   | 1 +
 configs/peach-pi_defconfig | 1 +
 configs/peach-pit_defconfig| 1 +
 configs/popmetal-rk3288_defconfig  | 1 +
 configs/rock2_defconfig| 1 +
 configs/s5pc210_universal_defconfig| 1 +
 configs/smdk5250_defconfig | 1 +
 configs/smdk5420_defconfig | 1 +
 configs/smdkv310_defconfig | 1 +
 configs/snow_defconfig | 1 +
 configs/socfpga_arria5_defconfig   | 1 +
 configs/socfpga_cyclone5_defconfig | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de1_soc_defconfig  | 1 +
 configs/socfpga_mcvevk_defconfig   | 1 +
 configs/socfpga_sockit_defconfig   | 1 +
 configs/socfpga_socrates_defconfig | 1 +
 configs/socfpga_sr1500_defconfig   | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 configs/spring_defconfig   | 1 +
 configs/trats2_defconfig   | 1 +
 configs/trats_defconfig| 1 +
 doc/README.socfpga | 3 ---
 drivers/mmc/Kconfig| 8 
 drivers/mmc/Makefile   | 2 +-
 include/configs/axs10x.h   | 1 -
 include/configs/exynos-common.h| 1 -
 include/configs/hikey.h| 1 -
 include/configs/rk3036_common.h| 1 -
 include/configs/rk3288_common.h| 1 -
 include/configs/rk3399_common.h| 1 -
 include/configs/socfpga_common.h   | 1 -
 50 files changed, 49 insertions(+), 13 deletions(-)

diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 72d6334..df3b5e7 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -347,7 +347,7 @@ static int init_dwmmc(void)
 {
int ret;
 
-#ifdef CONFIG_DWMMC
+#ifdef CONFIG_MMC_DW
 
/* mmc0 clocks are already configured by ATF */
ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 522e0cd..ba928e0 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -260,7 +260,7 @@ static int init_mmc(void)
 
 static int init_dwmmc(void)
 {
-#ifdef CONFIG_DWMMC
+#ifdef CONFIG_MMC_DW
return exynos_dwmmc_init(gd->fdt_blob);
 #else
return 0;
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index cdfb739..2298def 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -22,6 +22,7 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_DW=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S5P=y
 CONFIG_SOUND=y
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 04f5ffe..3793c42 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_SYS_I2C_DW=y
+CONFIG_MMC_DW=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 54fad6d..30a4021 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_SYS_I2C_DW=y
+CONFIG_MMC_DW=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/chromebit_mickey_defconfig 
b/configs/chromebit_mickey_defconfig
index 8c65ecf..8b66d6c 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -50,6 +50,7 @@ CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 

[U-Boot] [PATCH v2 7/7] ARM: sunxi: remove bare default for CONFIG_MMC

[Masahiro Yamada]

The bare default entry is wrong.  Just remove it since the (real)
entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX".

Signed-off-by: Masahiro Yamada 
Reviewed-by: Marek Vasut 
---

Changes in v2: None

 board/sunxi/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index e1d4ab1..11eb82a 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -291,10 +291,6 @@ config OLD_SUNXI_KERNEL_COMPAT
Set this to enable various workarounds for old kernels, this results in
sub-optimal settings for newer kernels, only enable if needed.
 
-config MMC
-   depends on !UART0_PORT_F
-   default y if ARCH_SUNXI
-
 config MMC0_CD_PIN
string "Card detect pin for mmc0"
default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
-- 
2.7.4

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[U-Boot] [PATCH v2 6/7] mmc: move more driver config options to Kconfig

[Masahiro Yamada]

Move (and rename) the following CONFIG options to Kconfig:

  CONFIG_DAVINCI_MMC  (renamed to CONFIG_MMC_DAVINCI)
  CONFIG_OMAP_HSMMC   (renamed to CONFIG_MMC_OMAP_HS)
  CONFIG_MXC_MMC  (renamed to CONFIG_MMC_MXC)
  CONFIG_MXS_MMC  (renamed to CONFIG_MMC_MXS)
  CONFIG_TEGRA_MMC(renamed to CONFIG_MMC_SDHCI_TEGRA)
  CONFIG_SUNXI_MMC(renamed to CONFIG_MMC_SUNXI)

They are the same option names as used in Linux.

This commit was created as follows:

[1] Rename the options with the following command:

find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_DAVINCI_MMC/CONFIG_MMC_DAVINCI/g
s/CONFIG_OMAP_HSMMC/CONFIG_MMC_OMAP_HS/g
s/CONFIG_MXC_MMC/CONFIG_MMC_MXC/g
s/CONFIG_MXS_MMC/CONFIG_MMC_MXS/g
s/CONFIG_TEGRA_MMC/CONFIG_MMC_SDHCI_TEGRA/g
s/CONFIG_SUNXI_MMC/CONFIG_MMC_SUNXI/g
'

[2] Commit the changes

[3] Create entries in driver/mmc/Kconfig.
(copied from Linux)

[4] Move the options with the following command
tools/moveconfig.py -y -r HEAD \
MMC_DAVINCI MMC_OMAP_HS MMC_MXC MMC_MXS MMC_SDHCI_TEGRA MMC_SUNXI

[5] Sort and align drivers/mmc/Makefile for readability

Signed-off-by: Masahiro Yamada 
Reviewed-by: Marek Vasut 
---

Changes in v2:
  - Re-generate based on v2017.01

 arch/arm/cpu/arm926ejs/mx27/generic.c  |  8 ++---
 arch/arm/include/asm/arch-mx27/imx-regs.h  |  4 +--
 arch/arm/mach-davinci/da830_pinmux.c   |  2 +-
 arch/arm/mach-omap2/am33xx/board.c |  2 +-
 arch/arm/mach-tegra/board2.c   |  2 +-
 board/armadeus/apf27/apf27.c   |  2 +-
 board/avionic-design/common/tamonten.c |  2 +-
 board/compal/paz00/paz00.c |  2 +-
 board/davinci/da8xxevm/da850evm.c  | 12 +++
 board/davinci/da8xxevm/omapl138_lcdk.c | 10 +++---
 board/htkw/mcx/mcx.c   |  2 +-
 board/lego/ev3/legoev3.c   |  4 +--
 board/nvidia/cardhu/cardhu.c   |  2 +-
 board/nvidia/dalmore/dalmore.c |  2 +-
 board/nvidia/harmony/harmony.c |  2 +-
 board/nvidia/seaboard/seaboard.c   |  2 +-
 board/nvidia/whistler/whistler.c   |  2 +-
 board/technexion/twister/twister.c |  2 +-
 board/teejet/mt_ventoux/mt_ventoux.c   |  2 +-
 board/toradex/colibri_t20/colibri_t20.c|  2 +-
 configs/am335x_baltos_defconfig|  1 +
 configs/am335x_boneblack_defconfig |  1 +
 configs/am335x_boneblack_vboot_defconfig   |  1 +
 configs/am335x_evm_defconfig   |  1 +
 configs/am335x_evm_nor_defconfig   |  1 +
 configs/am335x_evm_norboot_defconfig   |  1 +
 configs/am335x_evm_spiboot_defconfig   |  1 +
 configs/am335x_evm_usbspl_defconfig|  1 +
 configs/am335x_igep0033_defconfig  |  1 +
 configs/am335x_shc_defconfig   |  1 +
 configs/am335x_shc_ict_defconfig   |  1 +
 configs/am335x_shc_netboot_defconfig   |  1 +
 configs/am335x_shc_prompt_defconfig|  1 +
 configs/am335x_shc_sdboot_defconfig|  1 +
 configs/am335x_shc_sdboot_prompt_defconfig |  1 +
 configs/am335x_sl50_defconfig  |  1 +
 configs/am3517_crane_defconfig |  1 +
 configs/am3517_evm_defconfig   |  1 +
 configs/am43xx_evm_defconfig   |  1 +
 configs/am43xx_evm_ethboot_defconfig   |  1 +
 configs/am43xx_evm_qspiboot_defconfig  |  1 +
 configs/am43xx_evm_usbhost_boot_defconfig  |  1 +
 configs/am43xx_hs_evm_defconfig|  1 +
 configs/am57xx_evm_defconfig   |  1 +
 configs/am57xx_evm_nodt_defconfig  |  1 +
 configs/am57xx_hs_evm_defconfig|  1 +
 configs/apf27_defconfig|  1 +
 configs/apx4devkit_defconfig   |  1 +
 configs/birdland_bav335a_defconfig |  1 +
 configs/birdland_bav335b_defconfig |  1 +
 configs/brppt1_mmc_defconfig   |  1 +
 configs/brppt1_spi_defconfig   |  1 +
 configs/brxre1_defconfig   |  1 +
 configs/cairo_defconfig|  1 +
 configs/cl-som-am57x_defconfig |  1 +
 configs/cm_t335_defconfig  |  1 +
 configs/cm_t3517_defconfig |  1 +
 configs/cm_t35_defconfig   |  1 +
 configs/cm_t43_defconfig   |  1 +
 configs/cm_t54_defconfig   |  1 +
 configs/devkit8000_defconfig   |  1 +
 configs/dra7xx_evm_defconfig   |  1 +
 configs/dra7xx_hs_evm_defconfig|  1 +
 configs/draco_defconfig|  1 +
 configs/duovero_defconfig  |  1 +
 configs/eco5pk_defconfig   |  1 +
 configs/etamin_defconfig   |  1 +
 configs/igep0020_defconfig |  1 +
 configs/igep0030_defconfig |  1 +
 configs/igep0032_defconfig |  1 +
 configs/k2g_evm_defconfig  |  1 +
 configs/kc1_defconfig 

[U-Boot] [PATCH v2 2/7] mmc: rename CONFIG_ROCKCHIP_DWMMC to CONFIG_MMC_DW_ROCKCHIP

[Masahiro Yamada]

I am trying to make all DesignWare-based driver options prefixed
with CONFIG_MMC_DW_.

This commit was generated as follows:

find . -name .git -prune -o -type f -print | \
xargs sed -i -e 's/ROCKCHIP_DWMMC/MMC_DW_ROCKCHIP/g'

Signed-off-by: Masahiro Yamada 
Reviewed-by: Marek Vasut 
---

Changes in v2: None

 configs/chromebit_mickey_defconfig  | 2 +-
 configs/chromebook_jerry_defconfig  | 2 +-
 configs/chromebook_minnie_defconfig | 2 +-
 configs/evb-rk3036_defconfig| 2 +-
 configs/evb-rk3288_defconfig| 2 +-
 configs/evb-rk3399_defconfig| 2 +-
 configs/fennec-rk3288_defconfig | 2 +-
 configs/firefly-rk3288_defconfig| 2 +-
 configs/kylin-rk3036_defconfig  | 2 +-
 configs/miniarm-rk3288_defconfig| 2 +-
 configs/popmetal-rk3288_defconfig   | 2 +-
 configs/rock2_defconfig | 2 +-
 drivers/mmc/Kconfig | 2 +-
 drivers/mmc/Makefile| 2 +-
 14 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/configs/chromebit_mickey_defconfig 
b/configs/chromebit_mickey_defconfig
index 9203f73..8c65ecf 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -50,7 +50,7 @@ CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 95e5f57..5bb9a99 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -51,7 +51,7 @@ CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
diff --git a/configs/chromebook_minnie_defconfig 
b/configs/chromebook_minnie_defconfig
index 49cd640..d4ec2bd 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -51,7 +51,7 @@ CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 6546db9..f4ee5b9 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -29,7 +29,7 @@ CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 CONFIG_ROCKCHIP_RK3036_PINCTRL=y
 CONFIG_RAM=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index e5e550c..0bfb0dd 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -43,7 +43,7 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SPL_PINCTRL=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 6c27104..68de631 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -20,7 +20,7 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ROCKCHIP_SDHCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_PINCTRL=y
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index eff5e15..b76297c 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -42,7 +42,7 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SPL_PINCTRL=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 4910c80..3e55a84 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -43,7 +43,7 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index a4281c9..3e8fba2 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -30,7 +30,7 @@ CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 CONFIG_ROCKCHIP_RK3036_PINCTRL=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/miniarm-rk3288_defconfig b/configs/miniarm-rk3288_defconfig
index 1e273a6..7d3e65e 100644
--- a/configs/miniarm-rk3288_defconfig
+++ b/configs/miniarm-rk3288_defconfig
@@ -42,7 +42,7 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y

[U-Boot] [PATCH v2 4/7] mmc: move DesignWare-based drivers to Kconfig

[Masahiro Yamada]

Move (and rename) the following CONFIG options to Kconfig:

  CONFIG_EXYNOS_DWMMC  (renamed to CONFIG_MMC_DW_EXYNOS)
  CONFIG_HIKEY_DWMMC   (renamed to CONFIG_MMC_DW_K3)
  CONFIG_SOCFPGA_DWMMC (renamed to CONFIG_MMC_DW_SOCFPGA)

The "HIKEY" is a board name, so it is not suitable for the MMC
controller name.  I am following the name used in Linux.

This commit was generated as follows:

[1] Rename the config options with the following command:
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_EXYNOS_DWMMC/CONFIG_MMC_DW_EXYNOS/g
s/CONFIG_HIKEY_DWMMC/CONFIG_MMC_DW_K3/g
s/CONFIG_SOCFPGA_DWMMC/CONFIG_MMC_DW_SOCFPGA/g
'

[2] Commit the changes

[3] Create the entries in drivers/mmc/Kconfig
(with default y for EXYNOS and SOCFPGA)

[4] Run the following:
tools/moveconfig.py -y -r HEAD MMC_DW_EXYNOS MMC_DW_K3 MMC_DW_SOCFPGA

[5] Sort and align drivers/mmc/Makefile for readability

[6] Clean-up doc/README.socfpga by hand

Signed-off-by: Masahiro Yamada 
Reviewed-by: Marek Vasut 
---

Changes in v2: None

 configs/hikey_defconfig  |  1 +
 doc/README.socfpga   |  3 ---
 drivers/mmc/Kconfig  | 28 
 drivers/mmc/Makefile | 10 +-
 include/configs/exynos-common.h  |  1 -
 include/configs/hikey.h  |  1 -
 include/configs/socfpga_common.h |  1 -
 7 files changed, 34 insertions(+), 11 deletions(-)

diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 4a9546a..539c7d3 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -11,5 +11,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_CACHE=y
 CONFIG_MMC_DW=y
+CONFIG_MMC_DW_K3=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/doc/README.socfpga b/doc/README.socfpga
index e61bfef..e717637 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -19,6 +19,3 @@ controller support within SOCFPGA
 
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256
 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
-
-#define CONFIG_SOCFPGA_DWMMC
--> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 32fd6c5..02205a4 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -75,6 +75,24 @@ config MMC_DW
  block, this provides host support for SD and MMC interfaces, in both
  PIO, internal DMA mode and external DMA mode.
 
+config MMC_DW_EXYNOS
+   bool "Exynos specific extensions for Synopsys DW Memory Card Interface"
+   depends on ARCH_EXYNOS
+   depends on MMC_DW
+   default y
+   help
+ This selects support for Samsung Exynos SoC specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on Exynos4 and Exynos5 SoC's.
+
+config MMC_DW_K3
+   bool "K3 specific extensions for Synopsys DW Memory Card Interface"
+   depends on MMC_DW
+   help
+ This selects support for Hisilicon K3 SoC specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on Hisilicon K3 SoC's.
+
 config MMC_DW_ROCKCHIP
bool "Rockchip SD/MMC controller support"
depends on DM_MMC && OF_CONTROL
@@ -85,6 +103,16 @@ config MMC_DW_ROCKCHIP
  SD 3.0, SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well
  as removeable SD and micro-SD cards.
 
+config MMC_DW_SOCFPGA
+   bool "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
+   depends on ARCH_SOCFPGA
+   depends on MMC_DW
+   default y
+   help
+ This selects support for Altera SOCFPGA specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on Altera SOCFPGA.
+
 config SH_SDHI
bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
depends on RMOBILE
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 74a8881..439afbe 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -17,9 +17,11 @@ obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
 obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
 obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
-obj-$(CONFIG_MMC_DW) += dw_mmc.o
-obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
-obj-$(CONFIG_HIKEY_DWMMC) += hi6220_dw_mmc.o
+obj-$(CONFIG_MMC_DW)   += dw_mmc.o
+obj-$(CONFIG_MMC_DW_EXYNOS)+= exynos_dw_mmc.o
+obj-$(CONFIG_MMC_DW_K3)+= hi6220_dw_mmc.o
+obj-$(CONFIG_MMC_DW_ROCKCHIP)  += rockchip_dw_mmc.o
+obj-$(CONFIG_MMC_DW_SOCFPGA)   += socfpga_dw_mmc.o
 obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
 obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
@@ -36,7 +38,6 @@ 

Re: [U-Boot] U-Boot merge window is open

[york sun]

Sorry for spamming the list. I meant to sent to our internal teams. My 
apologies.

On 01/09/2017 08:02 PM, york sun wrote:
> Guys,
>
> U-Boot 2017.01 has been released. The merge window is open. If you need
> to update your patches, please do so ASAP. I will start to test and
> merge existing patches soon.
>
> York
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>

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[U-Boot] U-Boot merge window is open

[york sun]

Guys,

U-Boot 2017.01 has been released. The merge window is open. If you need 
to update your patches, please do so ASAP. I will start to test and 
merge existing patches soon.

York
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Re: [U-Boot] [v4 18/29] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

[Chee, Tien Fong]

On Isn, 2017-01-09 at 08:47 -0600, Dinh Nguyen wrote:
> 
> On 01/09/2017 05:31 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Add base address header file for Stratix10 SoC
> > 
> > Signed-off-by: Chin Liang See 
> > Signed-off-by: Tien Fong Chee 
> > Cc: Marek Vasut 
> > Cc: Dinh Nguyen 
> > Cc: Ley Foon Tan 
> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   48
> > 
> >  1 files changed, 48 insertions(+), 0 deletions(-)
> >  create mode 100755 arch/arm/mach-
> > socfpga/include/mach/base_addr_s10.h
> While this is really nice to see, but can you separate this patch out
> from the Arria10 series. It's already confusing enough.
> 
> Dinh
Ahhthis was rebased from 01-arria10. Okay, i will remove this
patch.
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Re: [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee, Tien Fong]

On Isn, 2017-01-09 at 13:43 +0100, Marek Vasut wrote:
> On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Add remaining 3 I2C base addresses for the Arria10.
> > 
> > Signed-off-by: Dinh Nguyen 
> > Signed-off-by: Tien Fong Chee 
> > Reviewed-by: Stefan Roese 
> > Cc: Marek Vasut 
> > Cc: Dinh Nguyen 
> > Cc: Chin Liang See 
> > Cc: Tien Fong 
> Please, just use git send-email to send the whole series. Don't drop
> the
> PATCH from the subject or anything. I am ignoring this series until
> it's
> sent properly.
> 
Ahhi catched what you means. I was used --subject-prefix when -v
was not working. Well, i would try again.
> > 
> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |3 +++
> >  1 files changed, 3 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > index a7056d4..902c321 100644
> > --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > @@ -29,6 +29,9 @@
> >  #define SOCFPGA_MPUL2_ADDRESS  0xf000
> >  #define SOCFPGA_I2C0_ADDRESS   0xffc02200
> >  #define SOCFPGA_I2C1_ADDRESS   0xffc02300
> > +#define SOCFPGA_I2C2_ADDRESS   0xffc02400
> > +#define SOCFPGA_I2C3_ADDRESS   0xffc02500
> > +#define SOCFPGA_I2C4_ADDRESS   0xffc02600
> >  
> >  #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
> >  #define SOCFPGA_UART0_ADDRESS  0xffc02000
> > 
> 
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Re: [U-Boot] [PATCH v1 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D3

[Wenyou.Yang]

Hi Andreas,

There are several patches I sent two months ago using the your older mail 
address,
I am not sure if you received them successfully. If not, I will resent them.

Sorry for the inconvenience caused.


Best Regards,
Wenyou Yang

> -Original Message-
> From: Wenyou Yang [mailto:wenyou.y...@atmel.com]
> Sent: 2016年10月28日 15:01
> To: U-Boot Mailing List 
> Cc: andreas.de...@googlemail.com; Albert Aribaud ;
> Wenyou Yang - A41535 ; Simon Glass
> ; Stephen Warren ; Heiko Schocher
> ; Wenyou Yang - A41535 
> Subject: [PATCH v1 0/2] ARM: dts: at91: add dts files for the boards of 
> SAMA5D3
> 
> The purpose of the patchset is add the dts files for boards,
> sama5d3 Xplained board and sama5d3xek board.
> 
> 
> Wenyou Yang (2):
>   ARM: at91: dt: add dts files for sama5d3ek board
>   ARM: at91: dt: add dts file for sama5d3 Xplained
> 
>  arch/arm/dts/Makefile  |7 +
>  arch/arm/dts/at91-sama5d3_xplained.dts |  341 
>  arch/arm/dts/sama5d3.dtsi  | 1505
> 
>  arch/arm/dts/sama5d31.dtsi |   16 +
>  arch/arm/dts/sama5d31ek.dts|   52 ++
>  arch/arm/dts/sama5d33.dtsi |   14 +
>  arch/arm/dts/sama5d33ek.dts|   45 +
>  arch/arm/dts/sama5d34.dtsi |   16 +
>  arch/arm/dts/sama5d34ek.dts|   62 ++
>  arch/arm/dts/sama5d35.dtsi |   18 +
>  arch/arm/dts/sama5d35ek.dts|   55 ++
>  arch/arm/dts/sama5d36.dtsi |   20 +
>  arch/arm/dts/sama5d36ek.dts|   57 ++
>  arch/arm/dts/sama5d36ek_cmp.dts|   55 ++
>  arch/arm/dts/sama5d3_can.dtsi  |   74 ++
>  arch/arm/dts/sama5d3_emac.dtsi |   55 ++
>  arch/arm/dts/sama5d3_gmac.dtsi |   88 ++
>  arch/arm/dts/sama5d3_lcd.dtsi  |  215 +
>  arch/arm/dts/sama5d3_mci2.dtsi |   59 ++
>  arch/arm/dts/sama5d3_tcb1.dtsi |   39 +
>  arch/arm/dts/sama5d3_uart.dtsi |   79 ++
>  arch/arm/dts/sama5d3xcm.dtsi   |  123 +++
>  arch/arm/dts/sama5d3xcm_cmp.dtsi   |  166 
>  arch/arm/dts/sama5d3xdm.dtsi   |   41 +
>  arch/arm/dts/sama5d3xmb.dtsi   |  221 +
>  arch/arm/dts/sama5d3xmb_cmp.dtsi   |  230 +
>  26 files changed, 3653 insertions(+)
>  create mode 100644 arch/arm/dts/at91-sama5d3_xplained.dts
>  create mode 100644 arch/arm/dts/sama5d3.dtsi  create mode 100644
> arch/arm/dts/sama5d31.dtsi  create mode 100644 arch/arm/dts/sama5d31ek.dts
> create mode 100644 arch/arm/dts/sama5d33.dtsi  create mode 100644
> arch/arm/dts/sama5d33ek.dts  create mode 100644 arch/arm/dts/sama5d34.dtsi
> create mode 100644 arch/arm/dts/sama5d34ek.dts  create mode 100644
> arch/arm/dts/sama5d35.dtsi  create mode 100644 arch/arm/dts/sama5d35ek.dts
> create mode 100644 arch/arm/dts/sama5d36.dtsi  create mode 100644
> arch/arm/dts/sama5d36ek.dts  create mode 100644
> arch/arm/dts/sama5d36ek_cmp.dts  create mode 100644
> arch/arm/dts/sama5d3_can.dtsi  create mode 100644
> arch/arm/dts/sama5d3_emac.dtsi  create mode 100644
> arch/arm/dts/sama5d3_gmac.dtsi  create mode 100644
> arch/arm/dts/sama5d3_lcd.dtsi  create mode 100644
> arch/arm/dts/sama5d3_mci2.dtsi  create mode 100644
> arch/arm/dts/sama5d3_tcb1.dtsi  create mode 100644
> arch/arm/dts/sama5d3_uart.dtsi  create mode 100644
> arch/arm/dts/sama5d3xcm.dtsi  create mode 100644
> arch/arm/dts/sama5d3xcm_cmp.dtsi  create mode 100644
> arch/arm/dts/sama5d3xdm.dtsi  create mode 100644
> arch/arm/dts/sama5d3xmb.dtsi  create mode 100644
> arch/arm/dts/sama5d3xmb_cmp.dtsi
> 
> --
> 2.7.4

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Re: [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee, Tien Fong]

On Isn, 2017-01-09 at 10:54 -0600, Dinh Nguyen wrote:
> On Mon, Jan 9, 2017 at 6:43 AM, Marek Vasut  wrote:
> > 
> > On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> > > 
> > > From: Tien Fong Chee 
> > > 
> > > Add remaining 3 I2C base addresses for the Arria10.
> > > 
> > > Signed-off-by: Dinh Nguyen 
> > > Signed-off-by: Tien Fong Chee 
> > > Reviewed-by: Stefan Roese 
> > > Cc: Marek Vasut 
> > > Cc: Dinh Nguyen 
> > > Cc: Chin Liang See 
> > > Cc: Tien Fong 
> > Please, just use git send-email to send the whole series. Don't
> > drop the
> > PATCH from the subject or anything. I am ignoring this series until
> > it's
> > sent properly.
> > 
Hi, i dind't drop any patch, this is rev4 with changes suggested from
Dinh which is merging the patch21 into patch7.

> Also, can I ask why the revision bump to v4? Please give reviewers
> time to
> review such a big change set before bumping the rev when most of the
> patches haven't been reviewed yet.
> 
> Dinh
Ohhwe thought that if reviewer has comment on any patch, some
reviewers might waiting next revision then only review.
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Re: [U-Boot] [PATCH] rpi: Fix device tree path on ARM64

[Stephen Warren]

On 01/09/2017 06:34 AM, Tuomas Tynkkynen wrote:

On Thu, 5 Jan 2017 16:44:43 -0700
Stephen Warren  wrote:


On 01/03/2017 03:39 AM, Tuomas Tynkkynen wrote:

The directory structure of device tree files produced by the kernel's
'make dtbs_install' is different on ARM64, the RPi3 device tree file is
in a 'broadcom' subdirectory there. Make the set_fdtfile function account
for this so that the distro boot scripts can locate the DTB file.


I'm not 100% sure there's an expectation/guarantee that "make
dtbs_install" will be used to create the DTB layout that the bootloader
uses, although I suppose this is a reasonable thing to do.



It certainly would be nice from the distro's point of view to have the same
scripts work on both ARM and ARM64.


diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c



 static void set_fdtfile(void)



-   fdtfile = model->fdtfile;
+   if (IS_ENABLED(CONFIG_ARM64))
+   strcat(fdtfile, "broadcom/");
+   strcat(fdtfile, model->fdtfile);


Instead of writing code for this, and in particular code that doesn't
check for buffer size/overflow/..., wouldn't it be better to simply edit
the RPi 3 entry in rpi_models_new_scheme[] to contain "broadcom/" in the
DTB filename string?



I did it this way to keep the 32-bit builds looking in the old location,
as that's where it was planned to be added for 32-bit ARM:

https://patchwork.kernel.org/patch/9148261/

I did consider some preprocessor magic and compile-time string concatenation
but this seemed a cleaner way.


I'm not convinced it's cleaner. It feels best to represent data as data, 
rather than writing code to calculate it at run-time, especially once 
all the complexity of error-checking is added in. I'd suggest:


Adding the following before the models table:

#ifdef CONFIG_ARM64
#define DTB_DIR "broadcom/"
#else
#define DTB_DIR ""
#endif

Then changing the table entries from:

[0x8] = {
"3 Model B",
"bcm2837-rpi-3-b.dtb",

... to:

[0x8] = {
"3 Model B",
DTB_DIR "bcm2837-rpi-3-b.dtb",

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[U-Boot] [PATCH v2 1/4] aspeed: Add drivers common to all Aspeed SoCs

[Maxim Sloyko]

Add support for Watchdog Timer, which is compatible with AST2400 and
AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver
does not follow the driver model. It also uses fixed clock, so no clock
driver is needed.

Add support for timer for Aspeed ast2400/ast2500 devices.
The driver actually controls several devices, but because all devices
share the same Control Register, it is somewhat difficult to completely
decouple them. Since only one timer is needed at the moment, this should
be OK. The timer uses fixed clock, so does not rely on a clock driver.

Add sysreset driver, which uses watchdog timer to do resets and particular
watchdog device to use is hardcoded (0)

---

Changes in v2:
- Moved number of WDTs to a Kconfig option

Changes in v1:
- Merged together the patches related to aspeed common drivers and
  configuration
- Fixed timer driver name (was sandbox_timer)
- Removed yet nonexistent files from mach-aspeed/Makefile


Signed-off-by: Maxim Sloyko 
---
 arch/arm/Kconfig |  7 +++
 arch/arm/Makefile|  1 +
 arch/arm/include/asm/arch-aspeed/timer.h | 54 ++
 arch/arm/include/asm/arch-aspeed/wdt.h   | 89 +
 arch/arm/mach-aspeed/Kconfig | 22 
 arch/arm/mach-aspeed/Makefile|  7 +++
 arch/arm/mach-aspeed/ast_wdt.c   | 37 
 drivers/sysreset/Makefile|  1 +
 drivers/sysreset/sysreset_ast.c  | 55 ++
 drivers/timer/Kconfig|  7 +++
 drivers/timer/Makefile   |  1 +
 drivers/timer/ast_timer.c| 96 
 12 files changed, 377 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-aspeed/timer.h
 create mode 100644 arch/arm/include/asm/arch-aspeed/wdt.h
 create mode 100644 arch/arm/mach-aspeed/Kconfig
 create mode 100644 arch/arm/mach-aspeed/Makefile
 create mode 100644 arch/arm/mach-aspeed/ast_wdt.c
 create mode 100644 drivers/sysreset/sysreset_ast.c
 create mode 100644 drivers/timer/ast_timer.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 714dd8b514..135c544335 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -882,8 +882,15 @@ config TARGET_THUNDERX_88XX
select OF_CONTROL
select SYS_CACHE_SHIFT_7
 
+config ARCH_ASPEED
+   bool "Support Aspeed SoCs"
+   select OF_CONTROL
+   select DM
+
 endchoice
 
+source "arch/arm/mach-aspeed/Kconfig"
+
 source "arch/arm/mach-at91/Kconfig"
 
 source "arch/arm/mach-bcm283x/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 236debb452..cc73e1038e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -50,6 +50,7 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_ASPEED)  += aspeed
 machine-$(CONFIG_ARCH_AT91)+= at91
 machine-$(CONFIG_ARCH_BCM283X) += bcm283x
 machine-$(CONFIG_ARCH_DAVINCI) += davinci
diff --git a/arch/arm/include/asm/arch-aspeed/timer.h 
b/arch/arm/include/asm/arch-aspeed/timer.h
new file mode 100644
index 00..87c5b354ec
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/timer.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef _ASM_ARCH_TIMER_H
+#define _ASM_ARCH_TIMER_H
+
+/* Each timer has 4 control bits in ctrl1 register.
+ * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
+ * such that timer X uses bits (4 * X - 4):(4 * X - 1)
+ * If the timer does not support PWM, bit 4 is reserved.
+ */
+#define AST_TMC_EN (1 << 0)
+#define AST_TMC_1MHZ   (1 << 1)
+#define AST_TMC_OVFINTR(1 << 2)
+#define AST_TMC_PWM(1 << 3)
+
+/* Timers are counted from 1 in the datasheet. */
+#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
+
+#define AST_TMC_RATE  (1000*1000)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * All timers share control registers, which makes it harder to make them
+ * separate devices. Since only one timer is needed at the moment, making
+ * it this just one device.
+ */
+
+struct ast_timer_counter {
+   u32 status;
+   u32 reload_val;
+   u32 match1;
+   u32 match2;
+};
+
+struct ast_timer {
+   struct ast_timer_counter timers1[3];
+   u32 ctrl1;
+   u32 ctrl2;
+#ifdef CONFIG_ASPEED_AST2500
+   u32 ctrl3;
+   u32 ctrl1_clr;
+#else
+   u32 reserved[2];
+#endif
+   struct ast_timer_counter timers2[5];
+};
+
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _ASM_ARCH_TIMER_H */
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h 
b/arch/arm/include/asm/arch-aspeed/wdt.h
new file mode 100644
index 00..32774b1a70
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: 

[U-Boot] [PATCH v2 3/4] aspeed: Board init functions and common configs for ast2500 based boards

[Maxim Sloyko]

---

Changes in v2: None
Changes in v1:
- Merge together all patches related to ast2500 boards common
  functions/configs
- Add copyright statement to ast2500-board.c

Signed-off-by: Maxim Sloyko 
---
 arch/arm/mach-aspeed/Makefile|  2 +-
 arch/arm/mach-aspeed/ast2500-board.c | 78 +
 include/configs/aspeed-common.h  | 84 
 3 files changed, 163 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-aspeed/ast2500-board.c
 create mode 100644 include/configs/aspeed-common.h

diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile
index 1f7af71b03..9d29ff7f6f 100644
--- a/arch/arm/mach-aspeed/Makefile
+++ b/arch/arm/mach-aspeed/Makefile
@@ -5,4 +5,4 @@
 #
 
 obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o
-obj-$(CONFIG_ASPEED_AST2500) += ast2500/
+obj-$(CONFIG_ASPEED_AST2500) += ast2500/ ast2500-board.o
diff --git a/arch/arm/mach-aspeed/ast2500-board.c 
b/arch/arm/mach-aspeed/ast2500-board.c
new file mode 100644
index 00..6ff74f0a1f
--- /dev/null
+++ b/arch/arm/mach-aspeed/ast2500-board.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Second Watchdog Timer by default is configured
+ * to trigger secondary boot source.
+ */
+#define AST_2ND_BOOT_WDT   (1)
+
+/* Third Watchdog Timer by default is configured
+ * to toggle Flash address mode switch before reset.
+ */
+#define AST_FLASH_ADDR_DETECT_WDT  (2)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void lowlevel_init(void)
+{
+   /*
+* These two watchdogs need to be stopped as soon as possible,
+* otherwise the board might hang. By default they are set to
+* a very short timeout and even simple debug write to serial
+* console early in the init process might cause them to fire.
+*/
+   struct ast_wdt *flash_addr_wdt =
+   (struct ast_wdt *)(WDT_BASE +
+  sizeof(struct ast_wdt) *
+  AST_FLASH_ADDR_DETECT_WDT);
+
+   clrbits_le32(_addr_wdt->ctrl, WDT_CTRL_EN);
+
+#ifndef CONFIG_FIRMWARE_2ND_BOOT
+   struct ast_wdt *sec_boot_wdt =
+   (struct ast_wdt *)(WDT_BASE +
+  sizeof(struct ast_wdt) *
+  AST_2ND_BOOT_WDT);
+
+   clrbits_le32(_boot_wdt->ctrl, WDT_CTRL_EN);
+#endif
+}
+
+int board_init(void)
+{
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+   return 0;
+}
+
+int dram_init(void)
+{
+   struct udevice *dev;
+   int ret = uclass_get_device(UCLASS_RAM, 0, );
+   if (ret) {
+   debug("DRAM FAIL1\r\n");
+   return ret;
+   }
+
+   struct ram_info ram;
+   ret = ram_get_info(dev, );
+   if (ret) {
+   debug("DRAM FAIL2\r\n");
+   return ret;
+   }
+
+
+   gd->ram_size = ram.size;
+   return 0;
+}
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
new file mode 100644
index 00..c125e39e3f
--- /dev/null
+++ b/include/configs/aspeed-common.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2012-2020  ASPEED Technology Inc.
+ * Ryan Chen 
+ *
+ * Copyright 2016 IBM Corporation
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AST_COMMON_CONFIG_H
+#define __AST_COMMON_CONFIG_H
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/* Enable cache controller */
+#define CONFIG_SYS_DCACHE_OFF  1
+
+#ifdef CONFIG_PRE_CON_BUF_SZ
+#define PRE_CON_RAM_SZ CONFIG_PRE_CON_BUF_SZ
+#else
+#define PRE_CON_RAM_SZ 0
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE  0x8000
+#define CONFIG_SYS_INIT_RAM_ADDR   (0x1e72 + PRE_CON_RAM_SZ)
+#define CONFIG_SYS_INIT_RAM_SIZE   (36*1024 - PRE_CON_RAM_SZ)
+#define SYS_INIT_RAM_END   (CONFIG_SYS_INIT_RAM_ADDR \
++ CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR(SYS_INIT_RAM_END \
+- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_NR_DRAM_BANKS   1
+
+#define CONFIG_SYS_TEXT_BASE   0x
+
+#define CONFIG_SYS_MALLOC_LEN  (32 << 20)
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_BAUDRATE115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Miscellaneous configurable options
+ */

Re: [U-Boot] [PATCH 7/7] sunxi: remove bare default for CONFIG_MMC

[Jaehoon Chung]

Hi Masahiro,

On 01/10/2017 10:32 AM, Masahiro Yamada wrote:
> Hi Jaehoon,
> 
> 
> 2017-01-10 9:55 GMT+09:00 Jaehoon Chung :
>> Hi Jagan,
>>
>> On 01/01/2017 09:11 PM, Masahiro Yamada wrote:
>>> The bare default entry is wrong.  Just remove it since the (real)
>>> entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX".
>>
>> Do you have any opinion about this patch?
>> I want to know your ack or review.
>> If there is no objection, i will pick this patch on my repository.
>>
>> Best Regards,
>> Jaehoon Chung
> 
> If you are going to pick up this series,
> please be careful with invisible conflicts.
> Applying the series as-is will cause misconversion
> because it is already outdated.
> 
> You can re-generate the series with commands in each commit-log,
> or I can re-send the series based on the v2017.01 tag if requested.

Yes, i'm running buildman with these patches on v2017.01 tag.
If you can resend the patches, it's more helpful to me with Marek's 
reviewed-tag.
To prevent the conflict, i think it's good to apply ASAP.

Best Regards,
Jaehoon Chung

> 
> 
> 

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Re: [U-Boot] [PATCH 7/7] sunxi: remove bare default for CONFIG_MMC

[Masahiro Yamada]

Hi Jaehoon,


2017-01-10 9:55 GMT+09:00 Jaehoon Chung :
> Hi Jagan,
>
> On 01/01/2017 09:11 PM, Masahiro Yamada wrote:
>> The bare default entry is wrong.  Just remove it since the (real)
>> entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX".
>
> Do you have any opinion about this patch?
> I want to know your ack or review.
> If there is no objection, i will pick this patch on my repository.
>
> Best Regards,
> Jaehoon Chung

If you are going to pick up this series,
please be careful with invisible conflicts.
Applying the series as-is will cause misconversion
because it is already outdated.

You can re-generate the series with commands in each commit-log,
or I can re-send the series based on the v2017.01 tag if requested.



-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH] build-whitelist.sh: Ignore mach-types.h

[Tom Rini]

On Mon, Jan 09, 2017 at 07:59:29PM -0500, Tom Rini wrote:
> On Tue, Jan 10, 2017 at 09:50:42AM +0900, Masahiro Yamada wrote:
> > Hi Tom,
> > 
> > 
> > 2017-01-10 9:46 GMT+09:00 Tom Rini :
> > > The file arch/arm/include/asm/mach-types.h comes from the Linux kernel
> > > and contains a number of CONFIG_ symbols that we have no control over
> > > nor do we wish to do anything with.  Ignore that file and re-generate
> > > the whitelist.
> > >
> > > Cc: Masahiro Yamada 
> > > Signed-off-by: Tom Rini 
> > 
> > I had also noticed that
> > more than 1000 CONFIG symbols come from this header.
> > 
> > How many boards actually need mach-types.h?
> > Can we remove the header entirely?
> 
> At issue is that CONFIG_MACH_TYPE (which will require a little thinking
> about how to migrate) is not something that can be up and removed.  We
> support booting old Linux and we support booting non-Linux OSes that
> also make use of the old bd struct.
> 
> Something I had done half an experiment on at some point, and forgotten
> about, was syncing only the MACH_TYPE_xxx values as the entire rest of
> the header contains logic we don't need.  I'll give that a whirl and
> report back.

So, the build is still in progress but I'm seeing a handful of errors
related to MACH_TYPE_xxx values that are not present in v4.9.  In fact
(at first glance) appear to have been removed in various re-syncs with
the official source of the list.  I'm probably going to re-work this as
a series to remove the CONFIG_MACH_TYPE usage from a number of platforms
and then re-sync.

-- 
Tom


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Re: [U-Boot] [PATCH] build-whitelist.sh: Ignore mach-types.h

[Tom Rini]

On Tue, Jan 10, 2017 at 09:50:42AM +0900, Masahiro Yamada wrote:
> Hi Tom,
> 
> 
> 2017-01-10 9:46 GMT+09:00 Tom Rini :
> > The file arch/arm/include/asm/mach-types.h comes from the Linux kernel
> > and contains a number of CONFIG_ symbols that we have no control over
> > nor do we wish to do anything with.  Ignore that file and re-generate
> > the whitelist.
> >
> > Cc: Masahiro Yamada 
> > Signed-off-by: Tom Rini 
> 
> I had also noticed that
> more than 1000 CONFIG symbols come from this header.
> 
> How many boards actually need mach-types.h?
> Can we remove the header entirely?

At issue is that CONFIG_MACH_TYPE (which will require a little thinking
about how to migrate) is not something that can be up and removed.  We
support booting old Linux and we support booting non-Linux OSes that
also make use of the old bd struct.

Something I had done half an experiment on at some point, and forgotten
about, was syncing only the MACH_TYPE_xxx values as the entire rest of
the header contains logic we don't need.  I'll give that a whirl and
report back.

-- 
Tom


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Re: [U-Boot] [PATCH 7/7] sunxi: remove bare default for CONFIG_MMC

[Jaehoon Chung]

Hi Jagan,

On 01/01/2017 09:11 PM, Masahiro Yamada wrote:
> The bare default entry is wrong.  Just remove it since the (real)
> entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX".

Do you have any opinion about this patch?
I want to know your ack or review. 
If there is no objection, i will pick this patch on my repository.

Best Regards,
Jaehoon Chung

> 
> Signed-off-by: Masahiro Yamada 
> ---
> 
>  board/sunxi/Kconfig | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
> index e1d4ab1..11eb82a 100644
> --- a/board/sunxi/Kconfig
> +++ b/board/sunxi/Kconfig
> @@ -291,10 +291,6 @@ config OLD_SUNXI_KERNEL_COMPAT
>   Set this to enable various workarounds for old kernels, this results in
>   sub-optimal settings for newer kernels, only enable if needed.
>  
> -config MMC
> - depends on !UART0_PORT_F
> - default y if ARCH_SUNXI
> -
>  config MMC0_CD_PIN
>   string "Card detect pin for mmc0"
>   default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
> 

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Re: [U-Boot] [PATCH] build-whitelist.sh: Ignore mach-types.h

[Masahiro Yamada]

Hi Tom,


2017-01-10 9:46 GMT+09:00 Tom Rini :
> The file arch/arm/include/asm/mach-types.h comes from the Linux kernel
> and contains a number of CONFIG_ symbols that we have no control over
> nor do we wish to do anything with.  Ignore that file and re-generate
> the whitelist.
>
> Cc: Masahiro Yamada 
> Signed-off-by: Tom Rini 

I had also noticed that
more than 1000 CONFIG symbols come from this header.

How many boards actually need mach-types.h?
Can we remove the header entirely?




-- 
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH] build-whitelist.sh: Ignore mach-types.h

[Tom Rini]

The file arch/arm/include/asm/mach-types.h comes from the Linux kernel
and contains a number of CONFIG_ symbols that we have no control over
nor do we wish to do anything with.  Ignore that file and re-generate
the whitelist.

Cc: Masahiro Yamada 
Signed-off-by: Tom Rini 
---
 scripts/build-whitelist.sh   |2 +-
 scripts/config_whitelist.txt | 1078 --
 2 files changed, 1 insertion(+), 1079 deletions(-)

diff --git a/scripts/build-whitelist.sh b/scripts/build-whitelist.sh
index f169eaa3b23e..1a07ec12538b 100755
--- a/scripts/build-whitelist.sh
+++ b/scripts/build-whitelist.sh
@@ -30,7 +30,7 @@ git grep CONFIG_SYS_EXTRA_OPTIONS |sed -n \
| sed 's/ *\([A-Za-z0-9_]*\).*/CONFIG_\1/'
 
 git grep CONFIG_ | \
-   egrep -vi "(Kconfig:|defconfig:|README|\.py|\.pl:)" \
+   egrep -vi "(Kconfig:|defconfig:|README|\.py|\.pl:|mach-types.h:)" \
| tr ' \t' '\n\n' \
| sed -n 's/^\(CONFIG_[A-Za-z0-9_]*\).*/\1/p'
 ) \
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 00ee3f10cdae..7b608b4915f0 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -106,66 +106,26 @@ CONFIG_APER_SIZE
 CONFIG_API
 CONFIG_APUS_FAST_EXCEPT
 CONFIG_AP_SH4A_4A
-CONFIG_ARCH_AAED2000
-CONFIG_ARCH_ADI_COYOTE
-CONFIG_ARCH_ADPAG101P
-CONFIG_ARCH_AT91RM9200DK
-CONFIG_ARCH_AUTCPU12
-CONFIG_ARCH_BAST
-CONFIG_ARCH_CATS
-CONFIG_ARCH_CDB89712
-CONFIG_ARCH_CEIVA
-CONFIG_ARCH_CLEP7212
 CONFIG_ARCH_CPU_INIT
 CONFIG_ARCH_CSB226
 CONFIG_ARCH_DMA_PIO_WORDS
 CONFIG_ARCH_EARLY_INIT_R
-CONFIG_ARCH_EBSA110
-CONFIG_ARCH_EBSA285
-CONFIG_ARCH_EDB7211
-CONFIG_ARCH_ENP2611
-CONFIG_ARCH_FORTUNET
-CONFIG_ARCH_GUMSTIX
-CONFIG_ARCH_H1940
-CONFIG_ARCH_H5400
-CONFIG_ARCH_H7201
-CONFIG_ARCH_H7202
 CONFIG_ARCH_HAS_ILOG2_U32
 CONFIG_ARCH_HAS_ILOG2_U64
 CONFIG_ARCH_INNOKOM
-CONFIG_ARCH_IQ31244
-CONFIG_ARCH_IQ80321
-CONFIG_ARCH_IQ80331
-CONFIG_ARCH_IXCDP1100
-CONFIG_ARCH_IXDP2400
-CONFIG_ARCH_IXDP2401
-CONFIG_ARCH_IXDP2800
-CONFIG_ARCH_IXDP2801
-CONFIG_ARCH_IXDP425
 CONFIG_ARCH_KIRKWOOD
-CONFIG_ARCH_KS8695
-CONFIG_ARCH_L7200
 CONFIG_ARCH_LUBBOCK
 CONFIG_ARCH_MAP_SYSMEM
 CONFIG_ARCH_MISC_INIT
-CONFIG_ARCH_MX1ADS
-CONFIG_ARCH_NETWINDER
 CONFIG_ARCH_OMAP4
 CONFIG_ARCH_ORION5X
-CONFIG_ARCH_P720T
-CONFIG_ARCH_PERSONAL_SERVER
 CONFIG_ARCH_PLEB
 CONFIG_ARCH_PXA_CERF
 CONFIG_ARCH_PXA_IDP
 CONFIG_ARCH_RMOBILE_BOARD_STRING
 CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
-CONFIG_ARCH_RPC
-CONFIG_ARCH_S3C2440
-CONFIG_ARCH_SHARK
 CONFIG_ARCH_TEGRA
 CONFIG_ARCH_USE_BUILTIN_BSWAP
-CONFIG_ARCH_VERSATILE_PB
-CONFIG_ARCH_VIPER
 CONFIG_ARC_MMU_VER
 CONFIG_ARC_SERIAL
 CONFIG_ARC_UART_BASE
@@ -1931,1037 +1891,21 @@ CONFIG_MACB1_PHY
 CONFIG_MACB2_PHY
 CONFIG_MACB3_PHY
 CONFIG_MACB_SEARCH_PHY
-CONFIG_MACH_A0
-CONFIG_MACH_A2F
-CONFIG_MACH_ABACUS
-CONFIG_MACH_ABB_GMA_1_1
-CONFIG_MACH_ABILENE
-CONFIG_MACH_ABLE
-CONFIG_MACH_ACER_A5
-CONFIG_MACH_ACER_A8
-CONFIG_MACH_ACER_GAUGUIN
-CONFIG_MACH_ACER_MAYA
-CONFIG_MACH_ACMENETUSFOXG20
-CONFIG_MACH_ACMEROVER1
-CONFIG_MACH_ACRO37XBRD
-CONFIG_MACH_ACS5K
-CONFIG_MACH_ACSX106
-CONFIG_MACH_ADSSPHERE
-CONFIG_MACH_AEBL
-CONFIG_MACH_AF4000
-CONFIG_MACH_AFEB9260
-CONFIG_MACH_AG11005
-CONFIG_MACH_AG5EVM
-CONFIG_MACH_AKITA
-CONFIG_MACH_AMK_A4
-CONFIG_MACH_AML_M5900
-CONFIG_MACH_AMS_DELTA
-CONFIG_MACH_ANCHOVY
-CONFIG_MACH_ANTARES
-CONFIG_MACH_ANTERO
-CONFIG_MACH_ANUBIS
-CONFIG_MACH_ANW6410
-CONFIG_MACH_AP4EVB
-CONFIG_MACH_APALIS_T30
-CONFIG_MACH_APP3K_ROBIN
-CONFIG_MACH_AQUARIUS
-CONFIG_MACH_AQUILA
-CONFIG_MACH_ARCOM_VULCAN
-CONFIG_MACH_ARCOM_ZEUS
-CONFIG_MACH_ARK9431
-CONFIG_MACH_ARMADA_XP_DB
-CONFIG_MACH_ARMADILLO460
-CONFIG_MACH_ARMADILLO5X0
-CONFIG_MACH_ARMADILLO800EVA
-CONFIG_MACH_ARMCORE
-CONFIG_MACH_ARMLEX4210
-CONFIG_MACH_ARMLGUEST
-CONFIG_MACH_AROWANA
-CONFIG_MACH_ARTHUR
-CONFIG_MACH_ARUBA
-CONFIG_MACH_AS1167
-CONFIG_MACH_ASL_PHOENIX
-CONFIG_MACH_ASPEN
 CONFIG_MACH_ASPENITE
-CONFIG_MACH_AST2200
-CONFIG_MACH_AT2440EVB
-CONFIG_MACH_AT572D940HFEB
-CONFIG_MACH_AT91CAP7STK
-CONFIG_MACH_AT91CAP7XDK
-CONFIG_MACH_AT91CAP9ADK
-CONFIG_MACH_AT91EB01
-CONFIG_MACH_AT91RM9200EK
-CONFIG_MACH_AT91SAM9260EK
-CONFIG_MACH_AT91SAM9261EK
-CONFIG_MACH_AT91SAM9263DESK16L
-CONFIG_MACH_AT91SAM9263EK
-CONFIG_MACH_AT91SAM9263OTLITE
-CONFIG_MACH_AT91SAM9G10EK
-CONFIG_MACH_AT91SAM9G20EK
-CONFIG_MACH_AT91SAM9G20EK_2MMC
-CONFIG_MACH_AT91SAM9G45EKES
-CONFIG_MACH_AT91SAM9M10G45EK
-CONFIG_MACH_AT91SAM9RLEK
-CONFIG_MACH_AT91SAM9X5EK
-CONFIG_MACH_ATDGP318
-CONFIG_MACH_ATEB9200
-CONFIG_MACH_ATHENE
-CONFIG_MACH_ATLAS5_C1
-CONFIG_MACH_AUTOBOT
-CONFIG_MACH_AVENGERS_LITE
-CONFIG_MACH_AVILA
-CONFIG_MACH_AWM2
-CONFIG_MACH_AX502
-CONFIG_MACH_AX8008
-CONFIG_MACH_B5500
-CONFIG_MACH_BASI
-CONFIG_MACH_BCM2708
-CONFIG_MACH_BCM589X
-CONFIG_MACH_BCMHANA_SV
-CONFIG_MACH_BCMHANA_TABLET
-CONFIG_MACH_BCMRING
-CONFIG_MACH_BEECT
-CONFIG_MACH_BIGDISK
-CONFIG_MACH_BIO3K
-CONFIG_MACH_BIPNET
-CONFIG_MACH_BLISS
-CONFIG_MACH_BLISSC
-CONFIG_MACH_BLUECHEESE

Re: [U-Boot] travis-ci: Trigger build with multiple commits in one push

[Tom Rini]

On Tue, Jan 10, 2017 at 12:34:47AM +0100, Jagan Teki wrote:

> Hi Tom or Any,
> 
> Any idea how to trigger travis-ci with multiple commit (build all of
> them) at same push, say for example when I push 10 commits in one push
> and if the middle commit is an error commit but travis-ci doesn't show
> the build issue. Do I need to do any specific setting on travis-ci
> linked repo for this, or any - any help?

So you want travis-ci to take a range of 10 commits and build the tree
for each of them, yes?  The way I would do this is:
$ for REV in `git rev-list origin/master..`;do \
git push github $REV:WIP-$REV;done

And this will make a branch for each commit and travis-ci will (in due
time) build each and every one of them.  It will also however take a
long time.

-- 
Tom


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[U-Boot] travis-ci: Trigger build with multiple commits in one push

[Jagan Teki]

Hi Tom or Any,

Any idea how to trigger travis-ci with multiple commit (build all of
them) at same push, say for example when I push 10 commits in one push
and if the middle commit is an error commit but travis-ci doesn't show
the build issue. Do I need to do any specific setting on travis-ci
linked repo for this, or any - any help?

Jagan.
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Re: [U-Boot] [PATCH v3 09/10] am335x_evm: enable usb ether gadget as it supports DM_ETH

[Tom Rini]

On Mon, Jan 09, 2017 at 09:58:03PM +0100, Marek Vasut wrote:
> On 01/09/2017 09:45 PM, Simon Glass wrote:
> > On 17 November 2016 at 02:08, Mugunthan V N  wrote:
> >> Since usb ether gadget have support for driver model, so enable
> >> usb ether gadget.
> >>
> >> Signed-off-by: Mugunthan V N 
> >> Reviewed-by: Tom Rini 
> >> ---
> >>  include/configs/am335x_evm.h | 3 ---
> >>  1 file changed, 3 deletions(-)
> > 
> > Applied to u-boot-dm, thanks!
> 
> Shouldn't this go through u-boot-ti ?

No, I reviewed it so it can just go via the other tree.  I am not a fan
of breaking up a series into N maintainers, so long as the maintainers
have acked/reviewed/etc the series.

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Re: [U-Boot] [PATCH v3 09/10] am335x_evm: enable usb ether gadget as it supports DM_ETH

[Marek Vasut]

On 01/09/2017 09:45 PM, Simon Glass wrote:
> On 17 November 2016 at 02:08, Mugunthan V N  wrote:
>> Since usb ether gadget have support for driver model, so enable
>> usb ether gadget.
>>
>> Signed-off-by: Mugunthan V N 
>> Reviewed-by: Tom Rini 
>> ---
>>  include/configs/am335x_evm.h | 3 ---
>>  1 file changed, 3 deletions(-)
> 
> Applied to u-boot-dm, thanks!
> 
Shouldn't this go through u-boot-ti ?

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[U-Boot] Please pull u-boot-dm

[Simon Glass]

Hi Tom,

The following changes since commit a705ebc81b7f91bbd0ef7c634284208342901149:

  Prepare v2017.01 (2017-01-09 11:57:05 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-dm.git

for you to fetch changes up to f8f41ae668040d58271e03bc85b58e13becb14af:

  scsi: dm: Unbind all scsi based block devices before new scan
(2017-01-09 11:25:20 -0700)


Michal Simek (1):
  scsi: dm: Unbind all scsi based block devices before new scan

Mugunthan V N (4):
  drivers: usb: gadget: ether/rndis: convert driver to adopt
device driver model
  am33xx: board: init usb ether gadget for rndis support
  am335x_evm: enable usb ether gadget as it supports DM_ETH
  defconfig: am335x_evm: enable usb driver model

 arch/arm/mach-omap2/am33xx/board.c |   8 +
 common/scsi.c  |   2 ++
 configs/am335x_evm_defconfig   |   3 ++
 drivers/usb/gadget/Kconfig |   4 +++
 drivers/usb/gadget/ether.c | 153
--
 drivers/usb/gadget/rndis.c |  13 ++--
 drivers/usb/gadget/rndis.h |  19 +---
 include/configs/am335x_evm.h   |   3 --
 include/net.h  |   7 +
 9 files changed, 194 insertions(+), 18 deletions(-)

Regards,
Simon
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Re: [U-Boot] [PATCH] scsi: dm: Unbind all scsi based block devices before new scan

[Simon Glass]

On 9 January 2017 at 11:13, Simon Glass  wrote:
> On 2 January 2017 at 01:40, Michal Simek  wrote:
>>
>> New scan should unbind all block devices not to be listed again.
>> Without this patch if scsi reset or scan is called new block devices are
>> created which point to the same id and lun.
>>
>> For example:
>> ZynqMP> scsi scan
>> scsi_scan: if_type=2, devnum=0: sd...@ff17.blk, 6, 0
>> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 0
>> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 1
>> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 2
>> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 3
>> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 4
>> scanning bus for devices...
>>   Device 0: (1:0) Vendor: ATA Prod.: KINGSTON SVP200S Rev: 501A
>> Type: Hard Disk
>> Capacity: 57241.8 MB = 55.9 GB (117231408 x 512)
>>
>> Reported-by: Ken Ma 
>> Signed-off-by: Michal Simek 
>> ---
>>
>>  common/scsi.c | 2 ++
>>  1 file changed, 2 insertions(+)
>
> Acked-by: Simon Glass 

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v3 10/10] defconfig: am335x_evm: enable usb driver model

[Simon Glass]

On 21 November 2016 at 07:06, Tom Rini  wrote:
> On Thu, Nov 17, 2016 at 02:38:15PM +0530, Mugunthan V N wrote:
>
>> enable usb driver model for am335x bbb as musb supports
>> driver model
>>
>> Signed-off-by: Mugunthan V N 
>
> Reviewed-by: Tom Rini 

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v3 08/10] am33xx: board: init usb ether gadget for rndis support

[Simon Glass]

On 17 November 2016 at 02:08, Mugunthan V N  wrote:
> Add usb ether gadget device with usb_ether_init() when
> CONFIG_DM_ETH and CONFIG_USB_ETHER are defined.
>
> Signed-off-by: Mugunthan V N 
> Reviewed-by: Tom Rini 
> ---
>  arch/arm/cpu/armv7/am33xx/board.c | 8 
>  1 file changed, 8 insertions(+)

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v3 09/10] am335x_evm: enable usb ether gadget as it supports DM_ETH

[Simon Glass]

On 17 November 2016 at 02:08, Mugunthan V N  wrote:
> Since usb ether gadget have support for driver model, so enable
> usb ether gadget.
>
> Signed-off-by: Mugunthan V N 
> Reviewed-by: Tom Rini 
> ---
>  include/configs/am335x_evm.h | 3 ---
>  1 file changed, 3 deletions(-)

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH] mx6sx: Add initial support for UDOO Neo Board

[Andreas Färber]

Hi,

Am 25.11.2016 um 19:56 schrieb Breno Lima:
> diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
> new file mode 100644
> index 000..81e0481
> --- /dev/null
> +++ b/include/configs/udoo_neo.h
[...]
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "console=ttymxc0,115200\0" \
> + "fdt_high=0x\0" \
> + "initrd_high=0x\0" \
> + "fdt_file=undefined\0" \
> + "fdt_addr=0x8300\0" \

This needs to be fdt_addr_r.

=> boot
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
load - load binary file from a filesystem

Usage:
load  [ [ [ [bytes [pos]
- Load binary file 'filename' from partition 'part' on device
   type 'interface' instance 'dev' to address 'addr' in memory.
  'bytes' gives the size to load in bytes.
  If 'bytes' is 0 or omitted, the file is read until the end.
  'pos' gives the file byte position to start reading from.
  If 'pos' is 0 or omitted, the file is read from the start.
BOOTP broadcast 1
...

> + "ip_dyn=yes\0" \
> + "mmcdev=0\0" \
> + "mmcrootfstype=ext4\0" \
> + "mmcautodetect=no\0" \
> + "findfdt="\
> + "if test $board_name = BASIC; then " \
> + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \
> + "if test $board_name = BASICKS; then " \
> + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \
> + "if test $board_name = FULL; then " \
> + "setenv fdt_file imx6sx-udoo-neo-full.dtb; fi; " \
> + "if test $board_name = EXTENDED; then " \
> + "setenv fdt_file imx6sx-udoo-neo-extended.dtb; fi; " \
> + "if test $fdt_file = UNDEFINED; then " \
> + "echo WARNING: Could not determine dtb to use; fi; \0" \

Nit: Trailing semicolon and space could be dropped.

> + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
> + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
> + "ramdisk_addr_r=0x8300\0" \
> + "ramdiskaddr=0x8300\0" \

Why have a duplicate $ramdiskaddr for a new board?

Regards,
Andreas

> + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
> + BOOTENV
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 0)
> +
> +#define CONFIG_BOOTCOMMAND \
> + "run findfdt; " \
> + "run distro_bootcmd"
> +
> +#include 
[...]

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[U-Boot] [PATCH] rtc: pcf2127: Update Kconfig and code style

[Simon Glass]

From: Meng Yi 

Unfortunately version 2 of this patch was applied which was missing some
changes. Fix this.

Signed-off-by: Meng Yi 
Acked-by: Simon Glass 
Signed-off-by: Simon Glass 
---

 drivers/rtc/Kconfig   |  6 +-
 drivers/rtc/pcf2127.c | 42 ++
 2 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 57af1b56cbf..cb79a016316 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -17,6 +17,10 @@ config RTC_PCF2127
bool "Enable PCF2127 driver"
depends on DM_RTC
help
- Enable pcf2127 driver which provides rtc get and set function
+ The PCF2127 is a CMOS Real Time Clock (RTC) and calendar with an 
integrated
+ Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 
kHz quartz
+ crystal optimized for very high accuracy and very low power 
consumption. The PCF2127
+ has a selectable I2C-bus or SPI-bus, a backup battery switch-over 
circuit, a
+ programmable watchdog function, a timestamp function, and many other 
features.
 
 endmenu
diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c
index bc59c6cda35..dcf0340b4dc 100644
--- a/drivers/rtc/pcf2127.c
+++ b/drivers/rtc/pcf2127.c
@@ -11,21 +11,21 @@
 #include 
 #include 
 
-#define PCF2127_REG_CTRL1  (0x00)
-#define PCF2127_REG_CTRL2  (0x01)
-#define PCF2127_REG_CTRL3  (0x02)
-#define PCF2127_REG_SC (0x03)  /* datetime */
-#define PCF2127_REG_MN (0x04)
-#define PCF2127_REG_HR (0x05)
-#define PCF2127_REG_DM (0x06)
-#define PCF2127_REG_DW (0x07)
-#define PCF2127_REG_MO (0x08)
-#define PCF2127_REG_YR (0x09)
+#define PCF2127_REG_CTRL1  0x00
+#define PCF2127_REG_CTRL2  0x01
+#define PCF2127_REG_CTRL3  0x02
+#define PCF2127_REG_SC 0x03
+#define PCF2127_REG_MN 0x04
+#define PCF2127_REG_HR 0x05
+#define PCF2127_REG_DM 0x06
+#define PCF2127_REG_DW 0x07
+#define PCF2127_REG_MO 0x08
+#define PCF2127_REG_YR 0x09
 
 static int pcf2127_rtc_set(struct udevice *dev, const struct rtc_time *tm)
 {
uchar buf[8];
-   int i = 0;
+   int i = 0, ret;
 
/* start register address */
buf[i++] = PCF2127_REG_SC;
@@ -44,21 +44,22 @@ static int pcf2127_rtc_set(struct udevice *dev, const 
struct rtc_time *tm)
buf[i++] = bin2bcd(tm->tm_year % 100);
 
/* write register's data */
-   if (dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)) < 0)
-   return -1;
+   ret = dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
 
-   return 0;
+   return ret;
 }
 
 static int pcf2127_rtc_get(struct udevice *dev, struct rtc_time *tm)
 {
-   int rel = 0;
+   int ret = 0;
uchar buf[10] = { PCF2127_REG_CTRL1 };
 
-   if (dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, 1) < 0)
-   return -1;
-   if (dm_i2c_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)) < 0)
-   return -1;
+   ret = dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, 1);
+   if (ret < 0)
+   return ret;
+   ret = dm_i2c_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
+   if (ret < 0)
+   return ret;
 
if (buf[PCF2127_REG_CTRL3] & 0x04)
puts("### Warning: RTC Low Voltage - date/time not reliable\n");
@@ -79,12 +80,13 @@ static int pcf2127_rtc_get(struct udevice *dev, struct 
rtc_time *tm)
  tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  tm->tm_hour, tm->tm_min, tm->tm_sec);
 
-   return rel;
+   return ret;
 }
 
 static int pcf2127_rtc_reset(struct udevice *dev)
 {
/*Doing nothing here*/
+
return 0;
 }
 
-- 
2.11.0.390.gc69c2f50cf-goog

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Re: [U-Boot] [PATCH] scsi: dm: Unbind all scsi based block devices before new scan

[Simon Glass]

On 2 January 2017 at 01:40, Michal Simek  wrote:
>
> New scan should unbind all block devices not to be listed again.
> Without this patch if scsi reset or scan is called new block devices are
> created which point to the same id and lun.
>
> For example:
> ZynqMP> scsi scan
> scsi_scan: if_type=2, devnum=0: sd...@ff17.blk, 6, 0
> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 0
> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 1
> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 2
> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 3
> scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 4
> scanning bus for devices...
>   Device 0: (1:0) Vendor: ATA Prod.: KINGSTON SVP200S Rev: 501A
> Type: Hard Disk
> Capacity: 57241.8 MB = 55.9 GB (117231408 x 512)
>
> Reported-by: Ken Ma 
> Signed-off-by: Michal Simek 
> ---
>
>  common/scsi.c | 2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Simon Glass 
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[U-Boot] [RFC Patch] drivers: mmc: omap_hsmmc: Fix IO Buffer on OMAP36XX

[aford173]

From: Adam Ford 

On the OMAP36xx (and 37xx) the CONTROL_WKUP_CTRL register has
a field (bit 6) named GPIO_IO_PWRDNZ.  If 0, the IO buffers which
are related to the MMC are disabled. After the PBIAS is configured,
this bit should be set high to enable the MMC port.

Signed-off-by: Adam Ford 

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 0a1ee40..069fd5a 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -38,6 +38,7 @@
 #include 
 #endif
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -115,6 +116,11 @@ static unsigned char mmc_board_init(struct mmc *mmc)
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
_base->pbias_lite);
 
+   if (get_cpu_family() == CPU_OMAP36XX)
+   writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
+   OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
+   OMAP34XX_CTRL_WKUP_CTRL);
+
writel(readl(_base->devconf0) | MMCSDIO1ADPCLKISEL,
_base->devconf0);
 
-- 
2.7.4

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[U-Boot] [ANN] U-Boot v2017.01 is released

[Tom Rini]

Hey all,

I've released v2017.01 and it's now live on git and FTP and ACD (along
with PGP sig file).

This release I think is a good way to start out a new year.  There's the
usual level of forward progress on the things that've been in progress
for a while.

I'll leave pointing out big changes to the custodians and instead I want
to talk about what I see as the priorities for 2017.  In 2016 we fully
moved away from MAKEALL and to using buildman.  In 2017 I want to see us
finish the move to Kconfig.  In September we added logic to break builds
that introduce new symbols and since then we've been making progress on
removing CONFIG symbols.  I'm confident that this year we can finish the
transition.

Thanks again everyone!

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Re: [U-Boot] [PATCH] lib: gitignore *.elf and *.so generated by efi_loader

[Tom Rini]

On Mon, Jan 09, 2017 at 11:33:28AM +0100, Ladislav Michl wrote:

> Signed-off-by: Ladislav Michl 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Dinh Nguyen]

On Mon, Jan 9, 2017 at 6:43 AM, Marek Vasut  wrote:
> On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
>> From: Tien Fong Chee 
>>
>> Add remaining 3 I2C base addresses for the Arria10.
>>
>> Signed-off-by: Dinh Nguyen 
>> Signed-off-by: Tien Fong Chee 
>> Reviewed-by: Stefan Roese 
>> Cc: Marek Vasut 
>> Cc: Dinh Nguyen 
>> Cc: Chin Liang See 
>> Cc: Tien Fong 
>
> Please, just use git send-email to send the whole series. Don't drop the
> PATCH from the subject or anything. I am ignoring this series until it's
> sent properly.
>

Also, can I ask why the revision bump to v4? Please give reviewers time to
review such a big change set before bumping the rev when most of the
patches haven't been reviewed yet.

Dinh
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[U-Boot] [PATCH v2] cmd/fdt: Make fdt get value endian-safe for single-cell properties

[Andreas Färber]

On a Raspberry Pi 2 disagreements on cell endianness can be observed:

  U-Boot> fdt print /soc/gpio@7e20 phandle
  phandle = <0x000d>
  U-Boot> fdt get value myvar /soc/gpio@7e20 phandle; printenv myvar
  myvar=0x0D00

Fix this by always treating the pointer as BE and converting it in
fdt_value_setenv(), like its counterpart fdt_parse_prop() already does.

Consistently use fdt32_t, fdt32_to_cpu() and cpu_to_fdt32().

Fixes: bc80295 ("fdt: Add get commands to fdt")
Cc: Joe Hershberger 
Cc: Gerald Van Baren 
Signed-off-by: Andreas Färber 
---
 cmd/fdt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cmd/fdt.c b/cmd/fdt.c
index 8bd345a..42397d1 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -58,7 +58,7 @@ static int fdt_value_setenv(const void *nodep, int len, const 
char *var)
else if (len == 4) {
char buf[11];
 
-   sprintf(buf, "0x%08X", *(uint32_t *)nodep);
+   sprintf(buf, "0x%08X", fdt32_to_cpu(*(fdt32_t *)nodep));
setenv(var, buf);
} else if (len%4 == 0 && len <= 20) {
/* Needed to print things like sha1 hashes. */
@@ -764,7 +764,7 @@ static int fdt_parse_prop(char * const *newval, int count, 
char *data, int *len)
 
cp = newp;
tmp = simple_strtoul(cp, , 0);
-   *(__be32 *)data = __cpu_to_be32(tmp);
+   *(fdt32_t *)data = cpu_to_fdt32(tmp);
data  += 4;
*len += 4;
 
-- 
2.10.2

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Re: [U-Boot] [v4 18/29] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

[Dinh Nguyen]

On 01/09/2017 05:31 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> Add base address header file for Stratix10 SoC
> 
> Signed-off-by: Chin Liang See 
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   48 
> 
>  1 files changed, 48 insertions(+), 0 deletions(-)
>  create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

While this is really nice to see, but can you separate this patch out
from the Arria10 series. It's already confusing enough.

Dinh
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Re: [U-Boot] [PATCH v1 1/1] x86: Synchronize list of x86 subarchitectures (update bootparam.h)

[Stefan Roese]

(adding Simon and Bin to cc)

On 08.01.2017 21:51, Andy Shevchenko wrote:

Basically rename X86_SUBARCH_MRST to X86_SUBARCH_INTEL_MID to be more specific.

Signed-off-by: Andy Shevchenko 
---
 arch/x86/include/asm/bootparam.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index a373a79886..48b138c6b0 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -117,7 +117,8 @@ enum {
X86_SUBARCH_PC = 0,
X86_SUBARCH_LGUEST,
X86_SUBARCH_XEN,
-   X86_SUBARCH_MRST,
+   X86_SUBARCH_INTEL_MID,
+   X86_SUBARCH_CE4100,
X86_NR_SUBARCHS,
 };
 #endif /* _ASM_X86_BOOTPARAM_H */



Reviewed-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH] rpi: Fix device tree path on ARM64

[Tuomas Tynkkynen]

On Thu, 5 Jan 2017 16:44:43 -0700
Stephen Warren  wrote:

> On 01/03/2017 03:39 AM, Tuomas Tynkkynen wrote:
> > The directory structure of device tree files produced by the kernel's
> > 'make dtbs_install' is different on ARM64, the RPi3 device tree file is
> > in a 'broadcom' subdirectory there. Make the set_fdtfile function account
> > for this so that the distro boot scripts can locate the DTB file.
> 
> I'm not 100% sure there's an expectation/guarantee that "make 
> dtbs_install" will be used to create the DTB layout that the bootloader 
> uses, although I suppose this is a reasonable thing to do.
> 

It certainly would be nice from the distro's point of view to have the same
scripts work on both ARM and ARM64.

> > diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
> 
> >  static void set_fdtfile(void)
> 
> > -   fdtfile = model->fdtfile;
> > +   if (IS_ENABLED(CONFIG_ARM64))
> > +   strcat(fdtfile, "broadcom/");
> > +   strcat(fdtfile, model->fdtfile);
> 
> Instead of writing code for this, and in particular code that doesn't 
> check for buffer size/overflow/..., wouldn't it be better to simply edit 
> the RPi 3 entry in rpi_models_new_scheme[] to contain "broadcom/" in the 
> DTB filename string?
> 

I did it this way to keep the 32-bit builds looking in the old location,
as that's where it was planned to be added for 32-bit ARM:

https://patchwork.kernel.org/patch/9148261/

I did consider some preprocessor magic and compile-time string concatenation
but this seemed a cleaner way.
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Re: [U-Boot] [PATCH 1/1] arm: mach-omap2: Fix secure file generation

[Tom Rini]

On Fri, Jan 06, 2017 at 04:20:02PM -0600, Andrew F. Davis wrote:

> When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was
> not generated but generate an unsigned one anyway, first fix this
> warning to say that it was generated but not secured.
> 
> When the user then exports TI_SECURE_DEV_PKG after getting this warning,
> and tries to re-build, 'make' will detect the build artifacts as
> unchanged and so assume they do not need to be re-generated. This causes
> it to fail to sign the files and it will pack unsigned files into the
> final image, even though TI_SECURE_DEV_PKG is now correctly defined and
> working.
> 
> Fix this by using FORCE on the targets causes them to be re-run even if
> the dependent files have not changed.
> 
> This then causes another issue. We currently rename the signed dtb files
> to overwrite the non-signed ones. We do this so the 'mkimage' tool gives
> the packaged dtb sections the correct name. If we do not rename the files
> then SPL will not find them during boot.
> 
> Fix this by renaming the dtb files by appending _HS to the end of the
> filename, after the ".dtb", this causes them to still be named correctly
> in the FIT blob.
> 
> Signed-off-by: Andrew F. Davis 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] mx6ullevk: Add missing MAINTAINERS for mx6ull_14x14_evk_plugin_defconfig

[Tom Rini]

On Thu, Jan 05, 2017 at 03:32:50PM +0100, Jagan Teki wrote:

> Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig
> which is missing in below commit
> "imx: mx6ull_14x14_evk: add plugin defconfig"
> (sha1: b90ebf49bb8f74afe68f696f59a0e24cc79f2031)
> 
> Cc: Stefano Babic 
> Reviewed-by: Peng Fan 
> Signed-off-by: Jagan Teki 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] am335x: configs: Use ISW_ENTRY_ADDR to set SPL_TEXT_BASE

[Tom Rini]

On Fri, Jan 06, 2017 at 04:32:12PM -0600, Andrew F. Davis wrote:

> The SPL load address changes based on boot type in HS devices,
> ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs
> for similar reasons. Add this same logic for AM33xx devices.
> 
> Also make the default value for ISW_ENTRY_ADDR correct for GP
> devices based on SoC, HS devices already pick the correct
> value in their defconfig.
> 
> Signed-off-by: Andrew F. Davis 

Applied to u-boot/master, thanks!

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Re: [U-Boot] rockchip: rk3288: Possible regression in sdram setup

[Romain Perier]

Hi,


Le 09/01/2017 à 08:20, Kever Yang a écrit :


On 01/06/2017 06:52 PM, Romain Perier wrote:

Add Rockchip Engineers to Cc:


Le 06/01/2017 à 11:28, Romain Perier a écrit :

Hello,

I have a strange behaviour with the SPL on rk3288.

When I build u-boot-rockchip master for the rock2 (rock2_defconfig), 
I can easily start u-boot SPL and u-boot from an sdcard (the emmc 
boot partition is erased so my board starts in maskrom mode by 
default) without any issues.



Now, I load uboot SPL and uboot over usb:

- I power up the board

- I generate an image for the bootrom:

# tools/mkimage -n rk3288 -T rkimage -d spl/u-boot-spl-dtb.bin out

- I uploaded this image via usb to the board

# cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | 
../tools/rkflashtool/rkflashtool l


I get no output from the SPL. I have investigated and found that it 
is caused by sdram_rk3288.c: sdram_init(). More especially by the 
function phy_pctrl_reset(). I enabled EARLY_UART and added 2 
printascii() in this function. This functions hangs in the second 
for loop. I hacked this function locally, I reduce the number of 
iterations from 4 to 3 then I added 2 uart outputs to this function 
and "OH!":   it works, I get the following output:


pctrl_reset:for
pctrl_reset:end for
pctrl_reset:for
pctrl_reset:end for

U-Boot SPL 2016.11-08675-ga4ae4ddda3-dirty (Jan 06 2017 - 10:35:41)



Now, if I remove my printascii() functions completly, it's no longer 
working. Which suggests that it might have something to do with busy 
wait delays... (I could be wrong)


From the sdram setup point of view, I don't see a real difference 
between an SPL loaded from sdcard and an SPL loaded via usb.


Rockchip guys: Would you have an idea about the problem ?



SPL load from sdcard/emmc and loaded via usb, one difference may be 
cpu frequency.


I agree that the udelay() may not correct, could you help to do:
- delay 1 S or more with udelay(), then we can see if it's correct, I 
don't know how the udelay is implement on rk3288,

if it's using ARM generic timer, then it's related to cpu frequency;
- using rockchip_udelay() instead of udelay(), this interface is using 
rktimer, it should be correct.


I have just tried both solutions, unfortunately, it did not help (same 
issues)


Thanks,
Romain

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[U-Boot] [PATCH v1 1/1] x86: Synchronize list of x86 subarchitectures (update bootparam.h)

[Andy Shevchenko]

Basically rename X86_SUBARCH_MRST to X86_SUBARCH_INTEL_MID to be more specific.

Signed-off-by: Andy Shevchenko 
---
 arch/x86/include/asm/bootparam.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index a373a79886..48b138c6b0 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -117,7 +117,8 @@ enum {
X86_SUBARCH_PC = 0,
X86_SUBARCH_LGUEST,
X86_SUBARCH_XEN,
-   X86_SUBARCH_MRST,
+   X86_SUBARCH_INTEL_MID,
+   X86_SUBARCH_CE4100,
X86_NR_SUBARCHS,
 };
 #endif /* _ASM_X86_BOOTPARAM_H */
-- 
2.11.0

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[U-Boot] [PATCH] sunxi: Add defconfig for the Sinovoip BPI-M2+ board

[Mark Kettenis]

The Sinovoip BPI-M2+ is a SBC board based on the H3 SoC.  It has 1G of RAM,
8G eMMC, a microSD slot, USB, gigabit Ethernet, AP6212 WiFi, HDMI, etc.
---
 configs/Sinovoip_BPI_M2_plus_defconfig | 18 ++
 1 file changed, 18 insertions(+)
 create mode 100644 configs/Sinovoip_BPI_M2_plus_defconfig

diff --git a/configs/Sinovoip_BPI_M2_plus_defconfig 
b/configs/Sinovoip_BPI_M2_plus_defconfig
new file mode 100644
index 00..4733151db4
--- /dev/null
+++ b/configs/Sinovoip_BPI_M2_plus_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="MACPWR=SUNXI_GPD(6)"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
-- 
2.11.0

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[U-Boot] [PATCH] Avoid non-portable sed construct

[Mark Kettenis]

Using \n in a substitution is a GNU extension.  Use the 'G" command instead
to insert the desired line.

Signed-off-by: Mark Kettenis 
---
 scripts/Makefile.lib | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 13c975b8a4..4413e9f98b 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -311,7 +311,7 @@ quiet_cmd_dtc = DTC $@
 # Bring in any U-Boot-specific include after the '/dts-v1/;' header
 cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
cat $< $(if $(u_boot_dtsi),\
-   | sed 's%^/ {$$%\#include \"$(u_boot_dtsi)\"\n&%')  | \
+   | sed '/^\/ {$$/{x;s%$$%\#include \"$(u_boot_dtsi)\"%;G;}') | \
$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; 
\
$(DTC) -O dtb -o $@ -b 0 \
-i $(dir $<) $(DTC_FLAGS) \
-- 
2.11.0

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[U-Boot] [PATCH v1 1/1] gitignore: Append *.so and *.efi

[Andy Shevchenko]

EFI loader generates two types of binaries that usually are not a part of
source tree. Ignore them globally based on extension.

Signed-off-by: Andy Shevchenko 
---
 .gitignore | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.gitignore b/.gitignore
index 7fac5b3c74..b9fa0354dd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,7 @@
 #
 .*
 *.o
+*.so
 *.o.*
 *.a
 *.s
@@ -15,6 +16,7 @@
 *.i
 *.lst
 *.order
+*.efi
 *.elf
 *.swp
 *.bin
-- 
2.11.0

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Re: [U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers

[Icenowy Zheng]

2017年1月9日 下午7:06于 Maxime Ripard 写道：
>
> On Fri, Jan 06, 2017 at 07:13:17AM +0800, Icenowy Zheng wrote: 
> > 
> > 
> > 06.01.2017, 06:16, "Maxime Ripard" : 
> > > On Thu, Dec 29, 2016 at 02:50:48AM +0800, Icenowy Zheng wrote: 
> > >>  Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like 
> > >>  DesignWare DRAM controller, which do not have official free DRAM 
> > >>  initialization code, but can use modified dram_sun8i_h3.c. 
> > >> 
> > >>  Add a invisible option for easier DRAM initialization code reuse. 
> > > 
> > > Since it's used on all the newer SoCs, do we need to keep the H3 name 
> > > in the config option name? 
> > 
> > Good question... 
> > 
> > Name it "SUNXI_DW_DRAM"? 
>
> Looks good. 
>
> > (Although I think at least A33 uses the same series of DRAM controller) 
>
> Does it? Why do we need a separate DRAM init code then? 

I think it does. See dram_sun8i_a33.c .

We used to use per-device dram code, but failed after allwinner uses libdram, 
then we worked on modifying H3 code.

I think it's also possible to make H3 code 
capable of A33, but since our A33 code works well, should we do it?

>
> Thanks, 
> Maxime 
>
> -- 
> Maxime Ripard, Free Electrons 
> Embedded Linux and Kernel engineering 
> http://free-electrons.com 
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Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 1/4] sunxi: add DDR2 support to H3-like DRAM controller

[Icenowy Zheng]

2017年1月9日 下午6:30于 Andre Przywara 写道：
>
> Hi, 
>
> On 05/01/17 22:55, Icenowy Zheng wrote: 
> > 
> > 2017年1月6日 06:37于 Maxime Ripard 写道： 
> >> 
> >> On Thu, Dec 29, 2016 at 03:00:58AM +0800, Icenowy Zheng wrote: 
> >>> H3-like DRAM controller needs some special code to operate a DDR2 DRAM 
> >>> chip. Add the logic to probe such a chip. 
>
> Out of curiosity, how did you came up with those values? 
> It would be good if this was mentioned in the commit log. 
>
> >>> As there's no commercial boards available now with H3 and DDR2 DRAM, the 
> >>> patch is developed and tested on a V3s chip, which has in-package DDR2 
> >>> DRAM. 
> >>> 
> >>> Signed-off-by: Icenowy Zheng  
> >> 
> >> It would have been great if your previous patch renaming the H3 symbol 
> >> was part of that serie. 
> >> 
> >>> --- 
> >>>   arch/arm/mach-sunxi/dram_sun8i_h3.c | 114 
> >>>++-- 
> >>>   board/sunxi/Kconfig |  11  
> >>>   2 files changed, 120 insertions(+), 5 deletions(-) 
> >>> 
> >>> diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
> >>> b/arch/arm/mach-sunxi/dram_sun8i_h3.c 
> >>> index 8e2527dee1..a48320e01c 100644 
> >>> --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
> >>> +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c 
> >>> @@ -22,6 +22,9 @@ struct dram_para { 
> >>>   u8 bus_width; 
> >>>   u8 dual_rank; 
> >>>   u8 row_bits; 
> >>> +#ifdef CONFIG_SUNXI_H3_DRAM_DDR2 
> >>> + u8 bank_bits; 
> >>> +#endif 
> >>>   }; 
> >>>   
> >>>   static inline int ns_to_t(int nanoseconds) 
> >>> @@ -136,36 +139,77 @@ static void mctl_set_timing_params(struct dram_para 
> >>> *para) 
> >>>   struct sunxi_mctl_ctl_reg * const mctl_ctl = 
> >>>   (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 
> >>>   
> >>> +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 
> >>>   u8 tccd = 2; 
> >>> +#else 
> >>> + u8 tccd = 1; 
> >>> +#endif 
> >>>   u8 tfaw = ns_to_t(50); 
> >>> +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 
> >>>   u8 trrd = max(ns_to_t(10), 4); 
> >>>   u8 trcd = ns_to_t(15); 
> >>>   u8 trc = ns_to_t(53); 
> >>>   u8 txp = max(ns_to_t(8), 3); 
> >>>   u8 twtr = max(ns_to_t(8), 4); 
> >>>   u8 trtp = max(ns_to_t(8), 4); 
> >>> +#else 
> >>> + u8 trrd = max(ns_to_t(10), 2); 
> >>> + u8 trcd = ns_to_t(20); 
> >>> + u8 trc = ns_to_t(65); 
> >>> + u8 txp = 2; 
> >>> + u8 twtr = max(ns_to_t(8), 2); 
> >>> + u8 trtp = max(ns_to_t(8), 2); 
> >>> +#endif 
> >>>   u8 twr = max(ns_to_t(15), 3); 
> >>>   u8 trp = ns_to_t(15); 
> >>> +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 
> >>>   u8 tras = ns_to_t(38); 
> >>> +#else 
> >>> + u8 tras = ns_to_t(45); 
> >>> +#endif 
> >>>   u16 trefi = ns_to_t(7800) / 32; 
> >>> +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 
> >>>   u16 trfc = ns_to_t(350); 
> >>> +#else 
> >>> + u16 trfc = ns_to_t(328); 
> >>> +#endif 
> >>>   
> >>>   u8 tmrw = 0; 
> >>> +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 
> >>>   u8 tmrd = 4; 
> >>> +#else 
> >>> + u8 tmrd = 2; 
> >>> +#endif 
> >>>   u8 tmod = 12; 
> >>>   u8 tcke = 3; 
> >>>   u8 tcksrx = 5; 
> >>>   u8 tcksre = 5; 
> >>>   u8 tckesr = 4; 
> >>> +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 
> >>>   u8 trasmax = 24; 
> >>> +#else 
> >>> + u8 trasmax = 27; 
> >>> +#endif 
> >> 
> >> Can't that be moved into a structure that would have different 
> >> declaration, this is barely readable. 
>
> I agree to that. If I got this correctly, the existing parameters here 
> are actually DRAM chip specific. It just happens that we use DDR3-1333 
> parameters for all boards so far. Most A64 boards for instance sport 
> DDR3-1600 capable chips, also we will need adjustments for the LPDDR3 
> chips used on the SoPine and Pinebook. So it would be good to address 
> this properly. 
>
> Philipp has a quite elaborate rework to fix this and ease the way to 
> allow board specific tunings of those parameters: 
>
> https://github.com/ptomsich/u-boot/commit/4ae474c756c3208a3bfaf36ed6f1850d46b07429
>  
>
> as part of that branch: 
> https://github.com/ptomsich/u-boot/commits/a64uQ7-spl-wip 

I now think it worth to do a gaint rework for H3 DRAM code...

This patch may need to be splited, and supports of A64, H5, R40 are also 
worthful to be part of the refactor.

>
> At some point in the future I wanted to clean this up and upstream it, I 
> am wondering if you can take a look at this now? 
>
> Cheers, 
> Andre. 
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[U-Boot] spl export fdt crashes

[matti kaasinen]

Hi!
I tried to useing falcom mode from nand flash:
ti-u-boot,
am335x based board using modified am335x_evm.
include/configs/am335x_evm.h falcon mode variables untouched.

I ran manually commands presented in:
https://git.ti.com/ti-u-boot/ti-u-boot/blobs/ti-u-boot-2016.05/board/ti/am335x/README
with the exception that I took dtb spl-os partition, so nand read instead
of load nand, usin nand read. I get following printout from falcon mode
preparation:
=> run nandargs
=> nand read ${loadaddr} NAND.kernel

NAND read: device 0 offset 0x20, size 0x80
 8388608 bytes read: OK
=> nand read ${fdtaddr} NAND.u-boot-spl-os

NAND read: device 0 offset 0x8, size 0x4
 262144 bytes read: OK
=> run nandargs
=> spl export fdt ${loadaddr} - ${fdtaddr}
data abort
pc : [<8ff611b2>]  lr : [<8ff66325>]
reloc pc : [<8080e1b2>]lr : [<80813325>]
sp : 8ef28bd0  ip : 8ff971c7 fp : 8ffb30a0
r10: 8ffb30a0  r9 : 8ef32ed8 r8 : 8ef28c6c
r7 : 0003  r6 : 0007 r5 : 8ffb30a0  r4 : 8200
r3 :   r2 : 8208 r1 : 8200  r0 : 8ffa1711
Flags: Nzcv  IRQs off  FIQs on  Mode SVC_32
Resetting CPU ...

resetting ...

What might go wrong?
Thanks,
Matti
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Re: [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Marek Vasut]

On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> Add remaining 3 I2C base addresses for the Arria10.
> 
> Signed-off-by: Dinh Nguyen 
> Signed-off-by: Tien Fong Chee 
> Reviewed-by: Stefan Roese 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 

Please, just use git send-email to send the whole series. Don't drop the
PATCH from the subject or anything. I am ignoring this series until it's
sent properly.

> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
> b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> index a7056d4..902c321 100644
> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> @@ -29,6 +29,9 @@
>  #define SOCFPGA_MPUL2_ADDRESS0xf000
>  #define SOCFPGA_I2C0_ADDRESS 0xffc02200
>  #define SOCFPGA_I2C1_ADDRESS 0xffc02300
> +#define SOCFPGA_I2C2_ADDRESS 0xffc02400
> +#define SOCFPGA_I2C3_ADDRESS 0xffc02500
> +#define SOCFPGA_I2C4_ADDRESS 0xffc02600
>  
>  #define SOCFPGA_ECC_OCRAM_ADDRESS0xff8c3000
>  #define SOCFPGA_UART0_ADDRESS0xffc02000
> 


-- 
Best regards,
Marek Vasut
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[U-Boot] [v4 29/29] arm: socfpga: arria10: Enable fpga driver build for SPL.

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/Makefile |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa14..c15796b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)PINCTRL)+= pinctrl/
 obj-$(CONFIG_$(SPL_)RAM)   += ram/
 
 ifdef CONFIG_SPL_BUILD
-
+obj-$(CONFIG_FPGA) += fpga/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-- 
1.7.7.4

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[U-Boot] [v4 28/29] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

[Chee Tien Fong]

From: Tien Fong Chee 

This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/spl.c |   79 +--
 1 files changed, 76 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..d381904 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -19,37 +19,58 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define BOOTINFO_BSEL_SHIFT0
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define BOOTINFO_BSEL_SHIFT12
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(_regs->bootinfo);
 
-   switch (bsel & 0x7) {
+   switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
case 0x2:   /* NAND Flash (1.8V) */
case 0x3:   /* NAND Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
return BOOT_DEVICE_NAND;
case 0x4:   /* SD/MMC External Transceiver (1.8V) */
case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+#endif
return BOOT_DEVICE_MMC1;
case 0x6:   /* QSPI Flash (1.8V) */
case 0x7:   /* QSPI Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+#endif
return BOOT_DEVICE_SPI;
default:
printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -68,6 +89,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, _regs->lwhps2fpgaregs);
@@ -182,3 +204,54 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+   memset(__bss_start, 0, __bss_end - __bss_start);
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+   /* We need to access to FDT as this stage */
+   /* FDT is at end of image */
+   gd->fdt_blob = (void *)(__bss_end);
+   /* Check whether we have a valid FDT or not. */
+   if (fdtdec_prepare_fdt()) {
+   panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+   "doc/README.fdt-control");
+   }
+#endif /* CONFIG_OF_CONTROL */
+
+   /* Initialize the timer */
+   timer_init();
+
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   reset_deassert_uart();
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+#endif
-- 
1.7.7.4

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[U-Boot] [v4 27/29] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/pinmux.h |   17 +
 arch/arm/mach-socfpga/pinmux.c  |  104 +++
 2 files changed, 121 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux.c

diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..ff54caa
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_PINMUX_H_
+#define_PINMUX_H_
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c
new file mode 100644
index 000..d45722f
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux.c
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+static int __do_pinctr_pins(const void *blob, int child, const char 
*node_name);
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name);
+
+static int __do_pinctr_pins(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", );
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins",
+   );
+   if (cell != NULL) {
+   debug("%p %d\n", cell, len);
+   for (;len > 0; len -= (2*sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   }
+   return 1;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return 2;
+
+   node_name = fdt_get_name(blob, child, );
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name)) {
+   __do_pinctr_pins(blob, child, node_name);
+   return(0);
+   }
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, );
+   }
+
+   return 1;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return 2;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return 3;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return 2;
+
+   return 0;
+}
-- 
1.7.7.4

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[U-Boot] [v4 26/29] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/clock_manager.c  |  752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  |  954 
 .../{clock_manager.c => clock_manager_gen5.c}  |  240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * 

[U-Boot] [v4 25/29] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile|6 +-
 arch/arm/mach-socfpga/include/mach/misc.h |   32 ++
 arch/arm/mach-socfpga/misc.c  |  427 +
 arch/arm/mach-socfpga/misc_arria10.c  |  255 +++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c} |  232 ++
 5 files changed, 337 insertions(+), 615 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (66%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b8fcf6e..1ab68be 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,9 +9,11 @@
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o 
\
+   clock_manager_arria10.o pinmux.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
-   reset_manager_gen5.o
+   reset_manager_gen5.o misc_gen5.o \
+   clock_manager_gen5.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..045268d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define_MISC_H_
+
+extern void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode);
+
+struct bsel{
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+extern void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 510aa1d..7fd5c0e 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,45 +7,33 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#include 
-#else
-#include 
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#else
-static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
-   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
-static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
-   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
-#endif
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bselbsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -84,219 +72,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id,
-const u32 phymode)
-{
-   

[U-Boot] [v4 24/29] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee Tien Fong]

From: Tien Fong Chee 

Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile |   16 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  155 ++--
 arch/arm/mach-socfpga/reset_manager.c  |  112 +--
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  407 
 .../{reset_manager.c => reset_manager_gen5.c}  |   94 ++---
 5 files changed, 570 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b8fcf6e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,21 +2,27 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2016 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+   reset_manager_gen5.o
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
+   wrap_pinmux_config.o wrap_sdram_config.o
+endif
 
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6225118..13f9731 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,15 +7,27 @@
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_
 
+/* Common function prototypes */
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
 void socfpga_bridges_reset(int enable);
-
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+void reset_deassert_peripherals_handoff(void);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+void reset_assert_uart(void);
+void reset_deassert_uart(void);
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -29,40 +41,40 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
-   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
-   u32 brg_mod_reset;
-   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
-   u32 coldmodrst;
-   u32 nrstmodrst;
-   u32 dbgmodrst;
-   u32 mpuwarmmask;
-   u32 per0warmmask;
-   u32 per1warmmask;
-   u32 brgwarmmask;
-   u32 syswarmmask;
-   u32 nrstwarmmask;
-   u32 l3warmmask;
-   u32 tststa;
-   u32 tstscratch;
-   u32 hdsktimeout;
-   u32 hmcintr;
-   u32 

[U-Boot] [v4 23/29] arm: socfpga: arria10: Added support for Arria 10 socdk

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/system_manager.c  |4 ++-
 drivers/fpga/socfpga.c  |7 +++-
 include/configs/socfpga_arria10_socdk.h |   56 +++
 include/configs/socfpga_common.h|   33 --
 4 files changed, 71 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 9e1c3fd..e1f0082 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -11,8 +11,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index bfefafd..7fd922e 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
}
 
/* Prior programming the FPGA, all bridges need to be shut off */
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Disable all signals from hps peripheral controller to fpga */
writel(0, _regs->fpgaintfgrp_module);
+#endif
 
/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
index 577f60f..105c4c0 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2015 Altera Corporation 
+ *  Copyright (C) 2015-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0
  */
@@ -8,31 +8,20 @@
 #define __CONFIG_SOCFGPA_ARRIA10_H__
 
 #include 
+
 /* U-Boot Commands */
-#define CONFIG_SYS_NO_FLASH
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
 
-/*
- * Memory configurations
- */
-#define PHYS_SDRAM_1_SIZE  0x200
-
 /* Booting Linux */
-#define CONFIG_BOOTDELAY   3
 #define CONFIG_BOOTFILE"zImage"
 #define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
@@ -40,24 +29,30 @@
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /*
- * Display CPU and Board Info
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
+/*
+ * U-Boot console configurations
  */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DOS_PARTITION
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x8000
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9031
-
 #endif
 
+/*
+ * U-Boot environment configurations
+ */
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
-#define CONFIG_ENV_OFFSET  512/* just after the MBR */
 
 /*
  * arguments passed to the bootz command. The value of
@@ -89,6 +84,23 @@
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
"bootm ${loadaddr} - ${fdt_addr}\0"
 
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/*
+ 

[U-Boot] [v4 22/29] arm: socfpga: arria10: Added some hardware base address for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 902c321..2d66580 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -36,10 +36,13 @@
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
-- 
1.7.7.4

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