[U-Boot] imx6 u-boot update nand ecc issues.

[Andy Ng]

Hi

I did an update from 2013-10 imx6 u-boot to 2016-03, and when I
updated the u-boot, u-boot can't read the old environment regions.

NAND read from offest 11 failed -74

I have checked the code for 2016-03 and there are a lot of ecc changes
in mxs_nand.c

Was an ecc bug in 2013-10?

Updating the u-boot to 2016-03 and use it to write a ubi  filesystem
in NAND, a 3.0.35 kernel can't read those images. It returns

UBI: error: ubi_io_read: error -74 (ECC error) while reading 64 bytes
from PEB 0:0, read 64 bytes..
...
...
UBI: error: ubi_io_read: error -74 (ECC error) while reading 64 bytes
from PEB n:0, read 64 bytes..

So that means that a u-boot update to 2016-03, would need a new kernel too?

Any ideas? It seems strange that old ecc calculations failed.

Andy
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[U-Boot] [PATCH v3] arm64: booti: allow to place kernel image anywhere in physical memory

[Masahiro Yamada]

At first, the ARM64 Linux booting requirement recommended that the
kernel image be placed text_offset bytes from 2MB aligned base near
the start of usable system RAM because memory below that base address
was unusable at that time.

This requirement was relaxed by Linux commit a7f8de168ace ("arm64:
allow kernel Image to be loaded anywhere in physical memory").
Since then, the bit 3 of the flags field indicates the tolerance
of the kernel physical placement.  If this bit is set, the 2MB
aligned base may be anywhere in physical memory.  For details, see
Documentation/arm64/booting.txt of Linux.

The booti command should be also relaxed.  If the bit 3 is set,
images->ep is respected, and the image is placed at the nearest
bootable location.  Otherwise, it is relocated to the start of the
system RAM to keep the original behavior.

Another wrinkle we need to take care of is the unknown endianness of
text_offset for a kernel older than commit a2c1d73b94ed (i.e. v3.16).
We can detect this based on the image_size field.  If the field is
zero, just use a fixed offset 0x8.

Signed-off-by: Masahiro Yamada 
---

Changes in v3:
  - Use a fixed offset 0x8 for old kernel

Changes in v2:
  - Use le64_to_cpu() for correct endian-ness
  - Check the bit 3

 cmd/booti.c | 28 ++--
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/cmd/booti.c b/cmd/booti.c
index bff87a8..da6fb01 100644
--- a/cmd/booti.c
+++ b/cmd/booti.c
@@ -11,6 +11,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -20,7 +22,7 @@ struct Image_header {
uint32_tcode1;  /* Executable code */
uint64_ttext_offset;/* Image load offset, LE */
uint64_timage_size; /* Effective Image size, LE */
-   uint64_tres1;   /* reserved */
+   uint64_tflags;  /* Kernel flags, LE */
uint64_tres2;   /* reserved */
uint64_tres3;   /* reserved */
uint64_tres4;   /* reserved */
@@ -34,7 +36,7 @@ static int booti_setup(bootm_headers_t *images)
 {
struct Image_header *ih;
uint64_t dst;
-   uint64_t image_size;
+   uint64_t image_size, text_offset;
 
ih = (struct Image_header *)map_sysmem(images->ep, 0);
 
@@ -42,19 +44,33 @@ static int booti_setup(bootm_headers_t *images)
puts("Bad Linux ARM64 Image magic!\n");
return 1;
}
-   
+
+   /*
+* Prior to Linux commit a2c1d73b94ed, the text_offset field
+* is of unknown endianness.  In these cases, the image_size
+* field is zero, and we can assume a fixed value of 0x8.
+*/
if (ih->image_size == 0) {
puts("Image lacks image_size field, assuming 16MiB\n");
image_size = 16 << 20;
+   text_offset = 0x8;
} else {
image_size = le64_to_cpu(ih->image_size);
+   text_offset = le64_to_cpu(ih->text_offset);
}
 
/*
-* If we are not at the correct run-time location, set the new
-* correct location and then move the image there.
+* If bit 3 of the flags field is set, the 2MB aligned base of the
+* kernel image can be anywhere in physical memory, so respect
+* images->ep.  Otherwise, relocate the image to the base of RAM
+* since memory below it is not accessible via the linear mapping.
 */
-   dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset);
+   if (le64_to_cpu(ih->flags) & BIT(3))
+   dst = images->ep - text_offset;
+   else
+   dst = gd->bd->bi_dram[0].start;
+
+   dst = ALIGN(dst, SZ_2M) + text_offset;
 
unmap_sysmem(ih);
 
-- 
2.7.4

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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Trevor Woerner]

On Wed 2017-03-08 @ 06:17:13 PM, Tom Rini wrote:
> On Wed, Mar 08, 2017 at 05:32:45PM -0500, Trevor Woerner wrote:
> > On Wed 2017-03-08 @ 04:33:21 PM, Tom Rini wrote:
> > > Now, you've boot tested this, right? :)
> > 
> > Yes.
> > 
> > > Also, what board(s) show this problem exactly?
> > 
> > I'm working with the firefly-rk3288 board.
> 
> OK.  Can you please turn off CONFIG_ROCKCHIP_SPL_BACK_TO_BROM and see if
> we can link again without -N?  No, this won't boot, but that's not what
> I'm after just yet, thanks!

Building with binutils-2.28 and CONFIG_ROCKCHIP_SPL_BACK_TO_BROM disabled
succeeds.

In case this is where you were heading... ;-)

Building twice (once with binutils-2.27 and once with binutils-2.28) both
times without the -N and both times with CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
disabled produces a diff in the map files of:

--- 2.27-without-N-without-SPL/u-boot.map   2017-03-08 
23:27:38.555324770 -0500
+++ 2.28-without-N-without-SPL/u-boot.map   2017-03-08 
23:24:59.383082189 -0500
@@ -7080,6 +7080,7 @@
 
 .data   0x00143688 0x2970
  *(.data*)
+ .data.rel.ro   0x001436880x0 
arch/arm/cpu/armv7/start.o
  .data.rk3288_otg_data
 0x00143688   0x2c 
arch/arm/mach-rockchip/built-in.o
  .data.rk3288_dmc_ops
@@ -7944,6 +7945,9 @@
  *(.rel*)
  .rel.got   0x00147cd00x0 
arch/arm/cpu/armv7/start.o
  .rel.plt   0x00147cd00x0 
arch/arm/cpu/armv7/start.o
+ .rel.bss   0x00147cd00x0 
arch/arm/cpu/armv7/start.o
+ .rel.data.rel.ro
+0x00147cd00x0 
arch/arm/cpu/armv7/start.o
  .rel.iplt  0x00147cd00x0 
arch/arm/cpu/armv7/start.o
  .rel.text  0x00147cd0   0x20 
arch/arm/cpu/armv7/start.o
  .rel.vectors   0x00147cf0   0x38 
arch/arm/cpu/armv7/start.o
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[U-Boot] [GIT PULL] Please pull u-boot-mmc pmic

[Jaehoon Chung]

Dear Tom,

Could you pull this patch on your master branch?

The following changes since commit 0574f786d3c85ab1a9fe9ee8ade65e3ae83e18a4:

  Merge branch 'master' of git://git.denx.de/u-boot-video (2017-03-08 07:14:21 
-0500)

are available in the git repository at:

  git://git.denx.de/u-boot-mmc.git pmic

for you to fetch changes up to 3cc293e26fa87f54d4a4c70448ff99b817c76913:

  sunxi: power: axp809.c: Fix aldo1-2 being disabled for mvolt != 0 (2017-03-09 
11:26:02 +0900)


Rask Ingemann Lambertsen (1):
  sunxi: power: axp809.c: Fix aldo1-2 being disabled for mvolt != 0

 drivers/power/axp809.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Best Regards,
Jaehoon Chung
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Re: [U-Boot] [PATCH][RFT] sunxi: power: axp809.c: Fix aldo1-2 being disabled for mvolt != 0

[Jaehoon Chung]

On 01/19/2017 05:53 AM, Rask Ingemann Lambertsen wrote:
> The execution flow is currently like this for aldo_num == 1 or 2:
> 
> int axp_set_aldo(int aldo_num, unsigned int mvolt)
> {
> ...
>   if (mvolt == 0)
>   return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
>   AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
> ...
>   return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
>   AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
>  }
> 
> I.e. aldo1 and aldo2 will always be disabled. This patch fixes it by
> setting (rather than clearing) the enable bit when mvolt != 0.
> 
> Signed-off-by: Rask Ingemann Lambertsen 
> Fixes: 795857df413a ("sunxi: power: add AXP809 support")

Applied on u-boot-mmc(pmic branch). Thanks!

Best Regards,
Jaehoon Chung

> ---
> 
> This patch needs someone to test it. I can't do so myself because I don't
> have any hardware with an AXP809 PMIC. I just happened to spot the bug
> when looking at the code.
> 
>  drivers/power/axp809.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c
> index c5b608d..5b5cb36 100644
> --- a/drivers/power/axp809.c
> +++ b/drivers/power/axp809.c
> @@ -143,7 +143,7 @@ int axp_set_aldo(int aldo_num, unsigned int mvolt)
>   if (aldo_num == 3)
>   return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
>   AXP809_OUTPUT_CTRL2_ALDO3_EN);
> - return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
> + return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
>   AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
>  }
>  
> 

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Re: [U-Boot] [PATCH v2] arm64: booti: allow to place kernel image anywhere in physical memory

[Masahiro Yamada]

Hi Mark,


2017-03-09 1:05 GMT+09:00 Mark Rutland :
>>
>>   /*
>> -  * If we are not at the correct run-time location, set the new
>> -  * correct location and then move the image there.
>> +  * If bit 3 of the flags field is set, the 2MB aligned base of the
>> +  * kernel image can be anywhere in physical memory, so respect
>> +  * images->ep.  Otherwise, relocate the image to the base of RAM
>> +  * since memory below it is not accessible via the linear mapping.
>>*/
>> - dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset);
>> + if (le64_to_cpu(ih->flags) & BIT(3))
>> + dst = images->ep - le64_to_cpu(ih->text_offset);
>
> I take it this is a pre-correction for the ALIGN() below?

Without this, the image would be always relocated
even if images->ep is already bootable location.

Unnecessary relocation should be avoided.





> There's one last wrinkle to take care of here, if we want to boot a
> kernel older than commit a2c1d73b94ed49f5 (i.e. v3.16). Until then, the
> text_offset was of unknown endianness.
>
> As mentiond in the Linux documentation, you can detect this based on the
> image_size field, e.g.
>
> uint64_t text_offset;
>
> /*
>  * Prior to Linux commit a2c1d73b94ed49f5, the text_offset field
>  * is of unknown endianness. In these cases, the image_size
>  * field is zero, and we can assume a fixed value of 0x8.
>  */
> if (le64_to_cpu(ih->image_size) == 0)
> text_offset = 0x8;
> else
> text_offset = (le64_to_cpu(ih->text_offset));
>
> ... then you can reuse that text_offset value for both cases above.
>

Thanks.  I will fix this too.



-- 
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH v2 16/20] drivers: fpga: Add compile switch for Gen5 only registers

[Ley Foon Tan]

These registers only available for Gen5 device, excludes them
if for Arria 10 build.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 drivers/fpga/socfpga.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..3751574 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -268,8 +270,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
 
/* Prior programming the FPGA, all bridges need to be shut off */
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Disable all signals from hps peripheral controller to fpga */
writel(0, _regs->fpgaintfgrp_module);
+#endif
 
/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080
@@ -278,8 +282,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset(1);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Unmap the bridges from NIC-301 */
writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
 
/* Initialize the FPGA Manager */
status = fpgamgr_program_init();
-- 
1.8.2.3

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[U-Boot] [PATCH v2 20/20] arm: socfpga: Enable build for Arria 10

[Ley Foon Tan]

Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Kconfig  | 10 +
 arch/arm/mach-socfpga/Makefile | 46 ++
 2 files changed, 43 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index e56b3db..ee98a44 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -37,6 +37,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+   bool
+
 config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -48,6 +51,10 @@ choice
prompt "Altera SOCFPGA board select"
optional
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
@@ -93,6 +100,7 @@ endchoice
 
 config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -105,6 +113,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -118,6 +127,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 68d55e4..41b779c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,28 +2,48 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2017 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
-  fpga_manager.o board.o
+obj-y  += board.o
+obj-y  += clock_manager.o
+obj-y  += fpga_manager.o
+obj-y  += misc.o
+obj-y  += reset_manager.o
+obj-y  += timer.o
 
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
-   misc_arria10.o  \
-   pinmux_arria10.o\
-   reset_manager_arria10.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += clock_manager_gen5.o
+obj-y  += misc_gen5.o
+obj-y  += reset_manager_gen5.o
+obj-y  += scan_manager.o
+obj-y  += system_manager_gen5.o
+obj-y  += wrap_pll_config.o
+endif
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y  += clock_manager_arria10.o
+obj-y  += misc_arria10.o
+obj-y  += pinmux_arria10.o
+obj-y  += reset_manager_arria10.o
+endif
 
+ifdef CONFIG_SPL_BUILD
+obj-y  += spl.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += freeze_controller.o
+obj-y  += wrap_iocsr_config.o
+obj-y  += wrap_pinmux_config.o
+obj-y  += wrap_sdram_config.o
+endif
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  clock_manager_gen5.o 
reset_manager_gen5.o \
-  misc_gen5.o system_manager_gen5.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
-- 
1.8.2.3

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[U-Boot] [PATCH v2 18/20] arm: socfpga: Add config and defconfig for Arria 10

[Ley Foon Tan]

Add config and defconfig for the Arria10 and update socfpga_common.h.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 configs/socfpga_arria10_defconfig   | 30 +++
 include/configs/socfpga_arria10_socdk.h | 67 +
 include/configs/socfpga_common.h| 28 --
 3 files changed, 121 insertions(+), 4 deletions(-)
 create mode 100644 configs/socfpga_arria10_defconfig
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
new file mode 100644
index 000..9e6bc1e0
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_SPL=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_DOS_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 000..5b7d572
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,67 @@
+/*
+ *  Copyright (C) 2015-2017 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include 
+/* U-Boot Commands */
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+
+/* Booting Linux */
+#define CONFIG_LOADADDR0x0100
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+
+/*
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x8000
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#endif
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_IS_IN_MMC
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/* The rest of the configuration is shared */
+#include 
+
+#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index bc92a2c..a228ea5 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -34,9 +34,13 @@
 #define CONFIG_SYS_MALLOC_LEN  (64 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START   PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_INIT_RAM_ADDR   0x
 #define CONFIG_SYS_INIT_RAM_SIZE   0x1
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_INIT_RAM_ADDR   0xFFE0
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4 /* 256KB */
+#endif
 #define CONFIG_SYS_INIT_SP_OFFSET  \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR\
@@ -67,8 +71,10 @@
 #define CONFIG_SYS_HOSTNAMECONFIG_SYS_BOARD
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_CMD_PXE
 #define CONFIG_MENU
+#endif
 
 /*
  * Cache
@@ -103,13 +109,14 @@
 /*
  * FPGA Driver
  */
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
 #define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT  1
 #endif
-
+#endif
 /*
  * L4 OSC1 Timer 0
  */
@@ -209,11 +216,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE-4
-#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART0_ADDRESS
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_NS16550_CLK 100
-#else
+#elif 

[U-Boot] [PATCH v2 17/20] arm: socfpga: Convert Altera ddr driver to use Kconfig

[Ley Foon Tan]

Convert Altera ddr driver to use Kconfig method. Enable ALTERA_SDRAM
by default if it is on Gen5 target. Arria 10 will have different driver.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 drivers/Kconfig  | 2 ++
 drivers/ddr/Kconfig  | 1 +
 drivers/ddr/altera/Kconfig   | 6 ++
 include/configs/socfpga_common.h | 5 -
 4 files changed, 9 insertions(+), 5 deletions(-)
 create mode 100644 drivers/ddr/Kconfig
 create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 0e5d97d..3e6bbac 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/ddr/fsl/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 000..b764add
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 000..9554da7
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,6 @@
+config ALTERA_SDRAM
+   bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
+   default y if TARGET_SOCFPGA_GEN5
+   help
+ This is for building the SDRAM controller for the Arria5/Cyclone5
+ devices.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 55e0bf9..bc92a2c 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -77,11 +77,6 @@
 #define CONFIG_SYS_PL310_BASE  SOCFPGA_MPUL2_ADDRESS
 
 /*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
  * EPCS/EPCQx1 Serial Flash Controller
  */
 #ifdef CONFIG_ALTERA_SPI
-- 
1.8.2.3

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[U-Boot] [PATCH v2 15/20] arm: socfpga: Add SPL support for Arria 10

[Ley Foon Tan]

Add SPL support for Arria 10 and add reset_uart() to use in SPL.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 .../include/mach/reset_manager_arria10.h   |  1 +
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 18 +++
 arch/arm/mach-socfpga/spl.c| 55 +-
 3 files changed, 72 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index e3171d1..d0711cf 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -14,6 +14,7 @@ void emac_manage_reset(ulong emacbase, uint state);
 int reset_deassert_bridges_handoff(void);
 void reset_assert_fpga_connected_peripherals(void);
 void reset_deassert_osc1wd0(void);
+void reset_uart(int assert);
 
 struct socfpga_reset_manager {
u32 stat;
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c 
b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 547a8bb..bbf54f0 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -28,6 +28,24 @@ static const struct socfpga_system_manager *sysmgr_regs =
ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
 
+void reset_uart(int assert)
+{
+   u32 mask = 0;
+   unsigned int com_port;
+
+   com_port = uart_com_port(gd->fdt_blob);
+
+   if (com_port == SOCFPGA_UART1_ADDRESS)
+   mask |= ALT_RSTMGR_PER1MODRST_UART1_SET_MSK;
+   else if (com_port == SOCFPGA_UART0_ADDRESS)
+   mask |= ALT_RSTMGR_PER1MODRST_UART0_SET_MSK;
+
+   if (assert)
+   setbits_le32(_manager_base->per1modrst, mask);
+   else
+   clrbits_le32(_manager_base->per1modrst, mask);
+}
+
 static const u32 per0fpgamasks[] = {
ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..5c0cc98 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -19,23 +19,32 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(_regs->bootinfo);
 
-   switch (bsel & 0x7) {
+   switch ((bsel >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
case 0x2:   /* NAND Flash (1.8V) */
@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, _regs->lwhps2fpgaregs);
@@ -182,3 +192,44 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   reset_uart(0);
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+}
+#endif
-- 
1.8.2.3

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[U-Boot] [PATCH v2 13/20] fdt: Add compatible strings for Arria 10

[Ley Foon Tan]

Add compatible strings for Intel Arria 10 SoCFPGA device.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 include/fdtdec.h | 8 
 lib/fdtdec.c | 8 
 2 files changed, 16 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..2134701 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,14 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_SUNXI_NAND,  /* SUNXI NAND controller */
+   COMPAT_ALTERA_SOCFPGA_CLK,  /* SoCFPGA Clock initialization */
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,   /* SoCFPGA pinctrl-single */
+   COMPAT_ALTERA_SOCFPGA_H2F_BRG,  /* SoCFPGA hps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* SoCFPGA lwhps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_F2H_BRG,  /* SoCFPGA fpga2hps bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR0,   /* SoCFPGA fpga2SDRAM0 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR1,   /* SoCFPGA fpga2SDRAM1 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR2,   /* SoCFPGA fpga2SDRAM2 bridge */
 
COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 81f47ef..ebe4a9a 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+   COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+   COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+   COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
1.8.2.3

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[U-Boot] [PATCH v2 19/20] arm: socfpga: Add board files for the Arria10

[Ley Foon Tan]

Add support for the Arria10 SoCDK.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 board/altera/arria10-socdk/Kconfig   | 18 ++
 board/altera/arria10-socdk/Makefile  |  7 +++
 board/altera/arria10-socdk/socfpga.c |  7 +++
 3 files changed, 32 insertions(+)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig 
b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+   default "armv7"
+
+config SYS_BOARD
+   default "socfpga_arria10"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile 
b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000..8516633
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
-- 
1.8.2.3

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[U-Boot] [PATCH v2 14/20] arm: dts: Add dts and dtsi for Arria 10

[Ley Foon Tan]

Device tree files for Arria 10

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/socfpga_arria10.dtsi  | 859 +
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 479 
 4 files changed, 1369 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eb68c20..25e08eb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -139,6 +139,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb 
\
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
+   socfpga_arria10_socdk_sdmmc.dtb \
socfpga_arria5_socdk.dtb\
socfpga_cyclone5_is1.dtb\
socfpga_cyclone5_mcvevk.dtb \
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
new file mode 100644
index 000..52ab7fe
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -0,0 +1,859 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0X11
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   ethernet2 = 
+   serial0 = 
+   serial1 = 
+   timer0 = 
+   timer1 = 
+   timer2 = 
+   timer3 = 
+   spi0 = 
+   spi1 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: intc@d000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <>;
+   ranges;
+
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   pdma: pdma@ffda1000 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda1000 0x1000>;
+   interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+<0 84 IRQ_TYPE_LEVEL_HIGH>,
+<0 85 IRQ_TYPE_LEVEL_HIGH>,
+<0 86 IRQ_TYPE_LEVEL_HIGH>,
+<0 87 IRQ_TYPE_LEVEL_HIGH>,
+<0 88 IRQ_TYPE_LEVEL_HIGH>,
+<0 89 IRQ_TYPE_LEVEL_HIGH>,
+<0 90 IRQ_TYPE_LEVEL_HIGH>,
+<0 91 IRQ_TYPE_LEVEL_HIGH>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clocks = <_main_clk>;
+   clock-names = "apb_pclk";
+   };
+   };
+
+   clkmgr@ffd04000 {
+   compatible = "altr,clk-mgr";
+   reg = <0xffd04000 0x1000>;
+   reg-names = "soc_clock_manager_OCP_SLV";
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
+   #clock-cells = <0>;
+

[U-Boot] [PATCH v2 12/20] arm: socfpga: Add pinmux for Arria 10

[Ley Foon Tan]

Add pinmux support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile  |  1 +
 arch/arm/mach-socfpga/include/mach/pinmux.h | 15 +
 arch/arm/mach-socfpga/pinmux_arria10.c  | 96 +
 3 files changed, 112 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 9c4617f..68d55e4 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -12,6 +12,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \
 
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
misc_arria10.o  \
+   pinmux_arria10.o\
reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..c5d5dd6
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_PINMUX_H_
+#define_PINMUX_H_
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c 
b/arch/arm/mach-socfpga/pinmux_arria10.c
new file mode 100644
index 000..47339ea
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux_arria10.c
@@ -0,0 +1,96 @@
+/*
+ *  Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int do_pinctr_pin(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", );
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins",
+   );
+   if (cell != NULL && len > 0) {
+   debug("%p %d\n", cell, len);
+   for (; len > 0; len -= (2 * sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   }
+   return -EFAULT;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return -EINVAL;
+
+   node_name = fdt_get_name(blob, child, );
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name))
+   return do_pinctr_pin(blob, child, node_name);
+
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, );
+   }
+
+   return -EFAULT;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+   if (node < 0)
+   return -EINVAL;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return -EFAULT;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return -EFAULT;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+   if (node < 0)
+   return -EINVAL;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return -EFAULT;
+
+   return 0;
+}
-- 
1.8.2.3

___
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[U-Boot] [PATCH v2 11/20] arm: socfpga: Add misc support for Arria 10

[Ley Foon Tan]

Add misc support for Arria 10 and minor fix on misc Gen5.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile|   1 +
 arch/arm/mach-socfpga/include/mach/misc.h |   6 +
 arch/arm/mach-socfpga/misc_arria10.c  | 254 ++
 arch/arm/mach-socfpga/misc_gen5.c |   3 +-
 4 files changed, 263 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c494930..9c4617f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -11,6 +11,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
+   misc_arria10.o  \
reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
index 64f9b86..446ee0f 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -23,4 +23,10 @@ void socfpga_fpga_add(void);
 inline void socfpga_fpga_add(void) {}
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
 #endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
new file mode 100644
index 000..d2bad13
--- /dev/null
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3  0x08
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3  0x68
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7  0x18
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7  0x78
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3  0x98
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pl310_regs *const pl310 =
+   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static struct socfpga_system_manager *sysmgr_regs =
+   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE
+void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode)
+{
+   u32 reset;
+
+   if (of_reset_id == EMAC0_RESET) {
+   reset = SOCFPGA_RESET(EMAC0);
+   } else if (of_reset_id == EMAC1_RESET) {
+   reset = SOCFPGA_RESET(EMAC1);
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+   } else {
+   printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
+   return;
+   }
+
+   clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+
+   /* Release the EMAC controller from reset */
+   socfpga_per_reset(reset, 0);
+}
+#endif
+
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+   /* Put OCRAM in non-secure */
+   writel(0x003f, _fw_ocram_base->region0);
+   writel(0x1, _fw_ocram_base->enable);
+
+   /* Put DDR in non-secure */
+   writel(0x, _fw_ddr_l3_base->hpsregion0addr);
+   writel(0x1, _fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+   initialize_security_policies();
+
+   /* Configure the L2 controller to make SDRAM start at 0 */
+   writel(0x1, >pl310_addr_filter_start);
+
+   /* assert reset to all except L4WD0 and L4TIMER0 */
+   socfpga_per_reset_all();
+
+   /* configuring the clock based on handoff */
+   /* TODO: Add call to cm_basic_init() */
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
+   return 0;
+}
+
+/*
+ * This function looking the 1st encounter UART peripheral,
+ * and then return its offset of the dedicated/shared IO pin
+ * mux. offset value (zero and above).
+ */
+static int 

[U-Boot] [PATCH v2 10/20] arm: socfpga: Add sdram header file for Arria 10

[Ley Foon Tan]

Add sdram header file for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 380 +
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_arria10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
new file mode 100644
index 000..1d7b7c1
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_SDRAM_ARRIA10_H_
+#define _SOCFPGA_SDRAM_ARRIA10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 caltiming4;
+   u32 caltiming5;
+   u32 caltiming6;
+   u32 caltiming7;
+   u32 caltiming8;
+   u32 caltiming9;
+   u32 caltiming10;
+   u32 dramaddrw;
+   u32 sideband0;
+   u32 sideband1;
+   

[U-Boot] [PATCH v2 08/20] arm: socfpga: Add clock driver for Arria 10

[Ley Foon Tan]

Add clock driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |3 +-
 arch/arm/mach-socfpga/clock_manager.c  |   18 +-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 1104 
 arch/arm/mach-socfpga/include/mach/clock_manager.h |6 +
 .../include/mach/clock_manager_arria10.h   |  222 
 5 files changed, 1350 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index d81f003..c494930 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,7 +10,8 @@
 obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
+   reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index c2af6f3..ad602c8 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -5,6 +5,8 @@
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 
@@ -18,7 +20,12 @@ void cm_wait_for_lock(u32 mask)
u32 inter_val;
u32 retry = 0;
do {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
inter_val = readl(_manager_base->inter) & mask;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   inter_val = readl(_manager_base->stat) & mask;
+#endif
+   /* Wait for stable lock */
if (inter_val == mask)
retry++;
else
@@ -31,8 +38,10 @@ void cm_wait_for_lock(u32 mask)
 /* function to poll in the fsm busy bit */
 void cm_wait_for_fsm(void)
 {
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
+   wait_for_bit(__func__, (const u32 *)_manager_base->stat,
+CLKMGR_CLKMGR_STAT_BUSY_SET_MSK,
+false, 2, false);
+
 }
 
 int set_cpu_clk_info(void)
@@ -43,7 +52,12 @@ int set_cpu_clk_info(void)
 
gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
gd->bd->bi_dsp_freq = 0;
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
return 0;
 }
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
new file mode 100644
index 000..67b3e58
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -0,0 +1,1104 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 eosc1_hz;
+static u32 cb_intosc_hz;
+static u32 f2s_free_hz;
+static u32 cm_l4_main_clk_hz;
+static u32 cm_l4_sp_clk_hz;
+static u32 cm_l4_mp_clk_hz;
+static u32 cm_l4_sys_free_clk_hz;
+
+struct mainpll_cfg {
+   u32 vco0_psrc;
+   u32 vco1_denom;
+   u32 vco1_numer;
+   u32 mpuclk;
+   u32 mpuclk_cnt;
+   u32 mpuclk_src;
+   u32 nocclk;
+   u32 nocclk_cnt;
+   u32 nocclk_src;
+   u32 cntr2clk_cnt;
+   u32 cntr3clk_cnt;
+   u32 cntr4clk_cnt;
+   u32 cntr5clk_cnt;
+   u32 cntr6clk_cnt;
+   u32 cntr7clk_cnt;
+   u32 cntr7clk_src;
+   u32 cntr8clk_cnt;
+   u32 cntr9clk_cnt;
+   u32 cntr9clk_src;
+   u32 cntr15clk_cnt;
+   u32 nocdiv_l4mainclk;
+   u32 nocdiv_l4mpclk;
+   u32 nocdiv_l4spclk;
+   u32 nocdiv_csatclk;
+   u32 nocdiv_cstraceclk;
+   u32 nocdiv_cspdbclk;
+};
+
+struct perpll_cfg {
+   u32 vco0_psrc;
+   u32 vco1_denom;
+   u32 vco1_numer;
+   u32 cntr2clk_cnt;
+   u32 cntr2clk_src;
+   u32 cntr3clk_cnt;
+   u32 cntr3clk_src;
+   u32 cntr4clk_cnt;
+   u32 cntr4clk_src;
+   u32 cntr5clk_cnt;
+   u32 cntr5clk_src;
+   u32 cntr6clk_cnt;
+   u32 cntr6clk_src;
+   u32 cntr7clk_cnt;
+   u32 cntr8clk_cnt;
+   u32 cntr8clk_src;
+   u32 cntr9clk_cnt;
+   u32 emacctl_emac0sel;
+   u32 emacctl_emac1sel;
+   u32 emacctl_emac2sel;
+   u32 gpiodiv_gpiodbclk;
+};
+
+struct alteragrp_cfg {
+   u32 nocclk;
+   u32 mpuclk;
+};
+
+static const struct socfpga_clock_manager *clock_manager_base =
+   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg)
+{
+   if (fdtdec_get_int_array(blob, node, "altr,of_reg_value",
+   

[U-Boot] [PATCH v2 09/20] arm: socfpga: Add system manager for Arria 10

[Ley Foon Tan]

Add system manager register struct and defines for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 .../arm/mach-socfpga/include/mach/system_manager.h | 52 ++
 .../include/mach/system_manager_arria10.h  | 81 ++
 .../include/mach/system_manager_gen5.h |  1 +
 3 files changed, 134 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 53ced81..54078ce 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -31,8 +31,60 @@
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V   0x1
+#define VOLTAGE_SEL_2P5V   0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE  0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V   2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE  0
+#define WK_PU_ENABLE   1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT  PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT  PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT0x10
+#define PD_DRV_STRG_DEFAULT0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB0
+#define PD_SLW_RT_LSB  5
+#define PU_DRV_STRG_LSB8
+#define PU_SLW_RT_LSB  13
+#define WK_PU_LSB  16
+#define INPUT_BUF_LSB  17
+#define BIAS_TRIM_LSB  19
+#define VOLTAGE_SEL_LSB0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK   0x0010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK  0x0001
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK  0x0010
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK  0x0100
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK  0x0001
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK  0x0002
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK  0x0002
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
new file mode 100644
index 000..f235aba
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SYSTEM_MANAGER_ARRIA10_H_
+#define _SYSTEM_MANAGER_ARRIA10_H_
+
+struct socfpga_system_manager {
+   u32  siliconid1;
+   u32  siliconid2;
+   u32  wddbg;
+   u32  bootinfo;
+   u32  mpu_ctrl_l2_ecc;
+   u32  _pad_0x14_0x1f[3];
+   u32  dma;
+   u32  dma_periph;
+   u32  sdmmcgrp_ctrl;
+   u32  sdmmc_l3master;
+   u32  nand_bootstrap;
+   u32  nand_l3master;
+   u32  usb0_l3master;
+   u32  usb1_l3master;
+   u32  emac_global;
+   u32  emac[3];
+   u32  _pad_0x50_0x5f[4];
+   u32  fpgaintf_en_global;
+   u32  fpgaintf_en_0;
+   u32  fpgaintf_en_1;
+   u32  fpgaintf_en_2;
+   u32  fpgaintf_en_3;
+   u32  _pad_0x74_0x7f[3];
+   u32  noc_addr_remap_value;
+   u32  noc_addr_remap_set;
+   u32  noc_addr_remap_clear;
+   u32  _pad_0x8c_0x8f;
+   u32  ecc_intmask_value;
+   u32  ecc_intmask_set;
+   u32  ecc_intmask_clr;
+   u32  ecc_intstatus_serr;
+   u32  ecc_intstatus_derr;
+   u32  mpu_status_l2_ecc;
+   u32  mpu_clear_l2_ecc;
+   u32  mpu_status_l1_parity;
+   u32  mpu_clear_l1_parity;
+   u32  mpu_set_l1_parity;
+   u32  _pad_0xb8_0xbf[2];
+   u32  noc_timeout;
+   u32  noc_idlereq_set;
+   u32  noc_idlereq_clr;
+   u32  noc_idlereq_value;
+   u32  noc_idleack;
+   u32  noc_idlestatus;
+   u32  fpga2soc_ctrl;
+   u32  _pad_0xdc_0xff[9];
+   u32  tsmc_tsel_0;
+   u32  tsmc_tsel_1;
+   u32  tsmc_tsel_2;
+   u32  tsmc_tsel_3;
+   u32  _pad_0x110_0x200[60];
+   u32  romhw_ctrl;
+   u32  romcode_ctrl;
+   u32  romcode_cpu1startaddr;
+   u32  romcode_initswstate;
+   u32  romcode_initswlastld;
+   u32  _pad_0x214_0x217;
+   u32  warmram_enable;
+   u32  warmram_datastart;
+   u32  warmram_length;
+   u32  warmram_execution;
+   u32  

[U-Boot] [PATCH v2 07/20] arm: socfpga: Add reset driver support for Arria 10

[Ley Foon Tan]

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   2 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../include/mach/reset_manager_arria10.h   | 143 
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 362 +
 include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 ++
 5 files changed, 612 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e83da2e..d81f003 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,6 +10,8 @@
 obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 9e253bf..57dc034 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
new file mode 100644
index 000..e3171d1
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _RESET_MANAGER_ARRIA10_H_
+#define _RESET_MANAGER_ARRIA10_H_
+
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpumodrst;
+   u32 per0modrst;
+   u32 per1modrst;
+   u32 brgmodrst;
+   u32 sysmodrst;
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_NANDRSTMGR_DEFINE(1, 5)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSKBIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSKBIT(0)
+#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSKBIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSKBIT(2)
+#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
+#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
+#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
+#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
+#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSKBIT(7)
+#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
+#define 

[U-Boot] [PATCH v2 05/20] arm: socfpga: Restructure system manager

[Ley Foon Tan]

Restructure system manager in the preparation to support A10.
No functional change.

Change uint32_t to u32.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   4 +-
 .../arm/mach-socfpga/include/mach/system_manager.h | 125 ++---
 .../include/mach/system_manager_gen5.h | 121 
 arch/arm/mach-socfpga/system_manager.c |  85 --
 arch/arm/mach-socfpga/system_manager_gen5.c|  85 ++
 5 files changed, 215 insertions(+), 205 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
 delete mode 100644 arch/arm/mach-socfpga/system_manager.c
 create mode 100644 arch/arm/mach-socfpga/system_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5b09ea9..e83da2e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -7,7 +7,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
@@ -15,7 +15,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
   clock_manager_gen5.o 
reset_manager_gen5.o \
-  misc_gen5.o
+  misc_gen5.o system_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..53ced81 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -1,120 +1,11 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef_SYSTEM_MANAGER_H_
-#define_SYSTEM_MANAGER_H_
-
-#ifndef __ASSEMBLY__
-
-void sysmgr_pinmux_init(void);
-void sysmgr_config_warmrstcfgio(int enable);
-
-void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
-#endif
-
-struct socfpga_system_manager {
-   /* System Manager Module */
-   u32 siliconid1; /* 0x00 */
-   u32 siliconid2;
-   u32 _pad_0x8_0xf[2];
-   u32 wddbg;  /* 0x10 */
-   u32 bootinfo;
-   u32 hpsinfo;
-   u32 parityinj;
-   /* FPGA Interface Group */
-   u32 fpgaintfgrp_gbl;/* 0x20 */
-   u32 fpgaintfgrp_indiv;
-   u32 fpgaintfgrp_module;
-   u32 _pad_0x2c_0x2f;
-   /* Scan Manager Group */
-   u32 scanmgrgrp_ctrl;/* 0x30 */
-   u32 _pad_0x34_0x3f[3];
-   /* Freeze Control Group */
-   u32 frzctrl_vioctrl;/* 0x40 */
-   u32 _pad_0x44_0x4f[3];
-   u32 frzctrl_hioctrl;/* 0x50 */
-   u32 frzctrl_src;
-   u32 frzctrl_hwctrl;
-   u32 _pad_0x5c_0x5f;
-   /* EMAC Group */
-   u32 emacgrp_ctrl;   /* 0x60 */
-   u32 emacgrp_l3master;
-   u32 _pad_0x68_0x6f[2];
-   /* DMA Controller Group */
-   u32 dmagrp_ctrl;/* 0x70 */
-   u32 dmagrp_persecurity;
-   u32 _pad_0x78_0x7f[2];
-   /* Preloader (initial software) Group */
-   u32 iswgrp_handoff[8];  /* 0x80 */
-   u32 _pad_0xa0_0xbf[8];  /* 0xa0 */
-   /* Boot ROM Code Register Group */
-   u32 romcodegrp_ctrl;/* 0xc0 */
-   u32 romcodegrp_cpu1startaddr;
-   u32 romcodegrp_initswstate;
-   u32 romcodegrp_initswlastld;
-   u32 romcodegrp_bootromswstate;  /* 0xd0 */
-   u32 __pad_0xd4_0xdf[3];
-   /* Warm Boot from On-Chip RAM Group */
-   u32 romcodegrp_warmramgrp_enable;   /* 0xe0 */
-   u32 romcodegrp_warmramgrp_datastart;
-   u32 romcodegrp_warmramgrp_length;
-   u32 romcodegrp_warmramgrp_execution;
-   u32 romcodegrp_warmramgrp_crc;  /* 0xf0 */
-   u32 __pad_0xf4_0xff[3];
-   /* Boot ROM Hardware Register Group */
-   u32 romhwgrp_ctrl;  /* 0x100 */
-   u32 _pad_0x104_0x107;
-   /* SDMMC Controller Group */
-   u32 sdmmcgrp_ctrl;
-   u32 sdmmcgrp_l3master;
-   /* NAND Flash Controller Register Group */
-   u32 nandgrp_bootstrap;  /* 0x110 */
-   u32 

[U-Boot] [PATCH v2 06/20] arm: socfpga: Add A10 defines

[Ley Foon Tan]

Add i2c, timer and other A10 defines.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..448fbdc 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -29,14 +29,20 @@
 #define SOCFPGA_MPUL2_ADDRESS  0xf000
 #define SOCFPGA_I2C0_ADDRESS   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
-- 
1.8.2.3

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[U-Boot] [PATCH v2 04/20] arm: socfpga: Restructure misc driver

[Ley Foon Tan]

Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 file. No functional change.

Change all uint32_t_to u32.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile|   3 +-
 arch/arm/mach-socfpga/include/mach/misc.h |  26 +++
 arch/arm/mach-socfpga/misc.c  | 361 ++
 arch/arm/mach-socfpga/misc_gen5.c | 355 +
 4 files changed, 398 insertions(+), 347 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/misc_gen5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 97819ac..5b09ea9 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -14,7 +14,8 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  clock_manager_gen5.o 
reset_manager_gen5.o
+  clock_manager_gen5.o 
reset_manager_gen5.o \
+  misc_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..64f9b86
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define _MISC_H_
+
+void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode);
+
+struct bsel {
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..cd250af 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -24,16 +25,19 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bsel bsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -72,207 +76,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id,
-const u32 phymode)
-{
-   u32 physhift, reset;
-
-   if (of_reset_id == EMAC0_RESET) {
-   physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
-   reset = SOCFPGA_RESET(EMAC0);
-   } else if (of_reset_id == EMAC1_RESET) {
-   physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
-   reset = SOCFPGA_RESET(EMAC1);
-   } else {
-   printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
-   return;
-   }
-
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
-   /* configure to PHY interface select choosed */
-   setbits_le32(_regs->emacgrp_ctrl,
-phymode << physhift);
-
-   /* Release the EMAC controller from reset */
-   socfpga_per_reset(reset, 0);
-}
-
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
-   if (!phymode)
-   return -EINVAL;
-
-   if (!strcmp(phymode, "mii") || !strcmp(phymode, 

[U-Boot] [PATCH v2 03/20] arm: socfpga: Restructure reset manager driver

[Ley Foon Tan]

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files. Minor update in socfpga_per_reset().
No functional change.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   2 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  42 +---
 .../mach-socfpga/include/mach/reset_manager_gen5.h |  47 +
 arch/arm/mach-socfpga/reset_manager.c  |  93 +
 arch/arm/mach-socfpga/reset_manager_gen5.c | 113 +
 5 files changed, 168 insertions(+), 129 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b76de4c..97819ac 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  clock_manager_gen5.o
+  clock_manager_gen5.o 
reset_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..9e253bf 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -8,27 +8,12 @@
 #define_RESET_MANAGER_H_
 
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
 
 void socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
-struct socfpga_reset_manager {
-   u32 status;
-   u32 ctrl;
-   u32 counts;
-   u32 padding1;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;
-   u32 per2_mod_reset;
-   u32 brg_mod_reset;
-   u32 misc_mod_reset;
-   u32 padding2[12];
-   u32 tstscratch;
-};
-
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
 #else
@@ -55,28 +40,11 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
-/*
- * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
- * 0 ... mpumodrst
- * 1 ... permodrst
- * 2 ... per2modrst
- * 3 ... brgmodrst
- * 4 ... miscmodrst
- */
-#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
-#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
-#define RSTMGR_NANDRSTMGR_DEFINE(1, 4)
-#define RSTMGR_QSPIRSTMGR_DEFINE(1, 5)
-#define RSTMGR_L4WD0   RSTMGR_DEFINE(1, 6)
-#define RSTMGR_OSC1TIMER0  RSTMGR_DEFINE(1, 8)
-#define RSTMGR_UART0   RSTMGR_DEFINE(1, 16)
-#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 18)
-#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 19)
-#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
-#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
-#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
-
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include 
+#endif
+
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
new file mode 100644
index 000..028974a
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -0,0 +1,47 @@
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef_RESET_MANAGER_GEN5_H_
+#define_RESET_MANAGER_GEN5_H_
+
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+   u32 status;
+   u32 ctrl;
+   u32 counts;
+   u32 padding1;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;
+   u32 per2_mod_reset;
+   u32 brg_mod_reset;
+   u32 misc_mod_reset;
+   u32 padding2[12];
+   u32 tstscratch;
+};
+
+/*
+ * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... permodrst
+ * 2 ... per2modrst
+ * 3 ... brgmodrst
+ * 4 ... miscmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NANDRSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI  

[U-Boot] [PATCH v2 02/20] arm: socfpga: Update clock for Gen5

[Ley Foon Tan]

Rename some of variables and fixes on clock calculation.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/clock_manager_gen5.c | 126 +
 1 file changed, 76 insertions(+), 50 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c 
b/arch/arm/mach-socfpga/clock_manager_gen5.c
index bca27df..bef0adb 100644
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013-2017 Altera Corporation 
+ * Copyright (C) 2013-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -66,7 +66,6 @@ static void cm_write_with_phase(u32 value,
  * set source main and peripheral clocks
  * Ungate clocks
  */
-
 void cm_basic_init(const struct cm_config * const cfg)
 {
unsigned long end;
@@ -307,56 +306,73 @@ void cm_basic_init(const struct cm_config * const cfg)
 
 static unsigned int cm_get_main_vco_clk_hz(void)
 {
-   u32 reg, clock;
+   u32 src_hz, numer, denom, vco;
 
/* get the main VCO clock */
-   reg = readl(_manager_base->main_pll.vco);
-   clock = cm_get_osc_clk_hz(1);
-   clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
- CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
-   clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
- CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
+   vco = readl(_manager_base->main_pll.vco);
 
-   return clock;
+   numer = ((vco & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
+   CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET);
+   denom = ((vco & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
+CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET);
+
+   src_hz = cm_get_osc_clk_hz(1);
+
+   vco = src_hz;
+   vco /= (1 + denom);
+   vco *= (1 + numer);
+
+   return vco;
 }
 
 static unsigned int cm_get_per_vco_clk_hz(void)
 {
-   u32 reg, clock = 0;
+   u32 src_hz = 0;
+   u32 clk_src = 0;
+   u32 numer = 0;
+   u32 denom = 0;
+   u32 vco = 0;
 
/* identify PER PLL clock source */
-   reg = readl(_manager_base->per_pll.vco);
-   reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
+   clk_src = readl(_manager_base->per_pll.vco);
+   clk_src = (clk_src & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
  CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
-   if (reg == CLKMGR_VCO_SSRC_EOSC1)
-   clock = cm_get_osc_clk_hz(1);
-   else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-   clock = cm_get_osc_clk_hz(2);
-   else if (reg == CLKMGR_VCO_SSRC_F2S)
-   clock = cm_get_f2s_per_ref_clk_hz();
+   if (clk_src == CLKMGR_VCO_SSRC_EOSC1)
+   src_hz = cm_get_osc_clk_hz(1);
+   else if (clk_src == CLKMGR_VCO_SSRC_EOSC2)
+   src_hz = cm_get_osc_clk_hz(2);
+   else if (clk_src == CLKMGR_VCO_SSRC_F2S)
+   src_hz = cm_get_f2s_per_ref_clk_hz();
 
/* get the PER VCO clock */
-   reg = readl(_manager_base->per_pll.vco);
-   clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
- CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
-   clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
- CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
+   vco = readl(_manager_base->per_pll.vco);
 
-   return clock;
+   numer = (vco & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
+   CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET;
+
+   denom = (vco & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
+   CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET;
+
+   vco = src_hz;
+   vco /= (1 + denom);
+   vco *= (1 + numer);
+
+   return vco;
 }
 
 unsigned long cm_get_mpu_clk_hz(void)
 {
-   u32 reg, clock;
+   u32 reg, clk_hz;
 
-   clock = cm_get_main_vco_clk_hz();
+   clk_hz = cm_get_main_vco_clk_hz();
 
/* get the MPU clock */
reg = readl(_manager_base->altera.mpuclk);
-   clock /= (reg + 1);
+   clk_hz /= (reg + 1);
reg = readl(_manager_base->main_pll.mpuclk);
-   clock /= (reg + 1);
-   return clock;
+   clk_hz /= (reg + 1);
+
+   return clk_hz;
 }
 
 unsigned long cm_get_sdram_clk_hz(void)
@@ -392,7 +408,8 @@ unsigned long cm_get_sdram_clk_hz(void)
 
 unsigned int cm_get_l4_sp_clk_hz(void)
 {
-   u32 reg, clock = 0;
+   u32 clock = 0;
+   u32 reg;
 
/* identify the source of L4 SP clock */
reg = readl(_manager_base->main_pll.l4src);
@@ -426,37 +443,45 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 
 unsigned int cm_get_mmc_controller_clk_hz(void)
 {
-   u32 reg, clock = 0;
+   u32 clk_hz = 0;
+   u32 clk_input = 0;
 
-   /* identify the source of MMC clock */
-   reg = readl(_manager_base->per_pll.src);
-   reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
+   clk_input = readl(_manager_base->per_pll.src);
+   clk_input = (clk_input & 

[U-Boot] [PATCH v2 01/20] arm: socfpga: Restructure clock manager driver

[Ley Foon Tan]

Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files. No functional change.

Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   3 +-
 arch/arm/mach-socfpga/clock_manager.c  | 510 +
 arch/arm/mach-socfpga/clock_manager_gen5.c | 510 +
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 312 +
 .../mach-socfpga/include/mach/clock_manager_gen5.h | 322 +
 5 files changed, 846 insertions(+), 811 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_gen5.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b76de4c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -13,7 +13,8 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o 
clock_manager.o \
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
+  clock_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index 29e18f8..c2af6f3 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -13,10 +13,10 @@ DECLARE_GLOBAL_DATA_PTR;
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+void cm_wait_for_lock(u32 mask)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
+   u32 inter_val;
+   u32 retry = 0;
do {
inter_val = readl(_manager_base->inter) & mask;
if (inter_val == mask)
@@ -29,512 +29,12 @@ static void cm_wait_for_lock(uint32_t mask)
 }
 
 /* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
+void cm_wait_for_fsm(void)
 {
while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
;
 }
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
-
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
-}
-
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
-{
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
-
-   writel(value, reg_address);
-
-   while (readl(reg_address) & mask)
-   ;
-}
-
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * Assert/deassert outreset all.
- * Take all pll's out of bypass
- * Clear safe mode
- * set source main and peripheral clocks
- * Ungate clocks
- */
-
-void cm_basic_init(const struct cm_config * const cfg)
-{
-   unsigned long end;
-
-   /* Start by being paranoid and gate all sw managed clocks */
-
-   /*
-* We need to disable nandclk
-* and then do another apb access before disabling
-* gatting off the rest of the periperal clocks.
-*/
-   writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
-   readl(_manager_base->per_pll.en),
-   _manager_base->per_pll.en);
-
-   /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
-   writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
-   CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
-   CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
-   CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |

[U-Boot] [PATCH v2 00/20] Add Intel Arria 10 SoC support

[Ley Foon Tan]

This is the 2nd version of patchset to adds support for Intel Arria 10 SoC.
This version mainly resolved comments from Marek in [v1].

This is initial patchset enables the basic support for Arria 10 and other
features will come after this.

This series is working on top of “arm: socfpga: Move to using distro boot”
series [1] from Dalon Westergreen.

[1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg239560.html

v1 -> v2 changes:
-
- Changed to use wait_for_bit() for status polling
- Sorted #ifdef in GEN5 then ARRIA10 order.
- Removed the keyword "register" and "volatile"
- Changed to use errno.h error code
- Dropped "drivers: Makefile: include fpga build in SPL" patch
- A10 reset driver
- Combined reset_assert_uart() & reset_deassert_uart()
- Moved reset_uart to later patch
- A10 clock driver
- Moved clock driver GEN5 update to new patch
- Changed global clock variables to static
- Moved cm_print_clock_quick_summary() to Gen5 and Arria 10
- Resolved warnings and errors from checkpatch.pl.

Patchset history

[v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg240052.html

Ley Foon Tan (20):
  arm: socfpga: Restructure clock manager driver
  arm: socfpga: Update clock for Gen5
  arm: socfpga: Restructure reset manager driver
  arm: socfpga: Restructure misc driver
  arm: socfpga: Restructure system manager
  arm: socfpga: Add A10 defines
  arm: socfpga: Add reset driver support for Arria 10
  arm: socfpga: Add clock driver for Arria 10
  arm: socfpga: Add system manager for Arria 10
  arm: socfpga: Add sdram header file for Arria 10
  arm: socfpga: Add misc support for Arria 10
  arm: socfpga: Add pinmux for Arria 10
  fdt: Add compatible strings for Arria 10
  arm: dts: Add dts and dtsi for Arria 10
  arm: socfpga: Add SPL support for Arria 10
  drivers: fpga: Add compile switch for Gen5 only registers
  arm: socfpga: Convert Altera ddr driver to use Kconfig
  arm: socfpga: Add config and defconfig for Arria 10
  arm: socfpga: Add board files for the Arria10
  arm: socfpga: Enable build for Arria 10

 arch/arm/dts/Makefile  |1 +
 arch/arm/dts/socfpga_arria10.dtsi  |  859 +++
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |   30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   |  479 +
 arch/arm/mach-socfpga/Kconfig  |   10 +
 arch/arm/mach-socfpga/Makefile |   41 +-
 arch/arm/mach-socfpga/clock_manager.c  |  526 +-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 1104 
 arch/arm/mach-socfpga/clock_manager_gen5.c |  536 ++
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |8 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  314 +-
 .../include/mach/clock_manager_arria10.h   |  222 
 .../mach-socfpga/include/mach/clock_manager_gen5.h |  322 ++
 arch/arm/mach-socfpga/include/mach/misc.h  |   32 +
 arch/arm/mach-socfpga/include/mach/pinmux.h|   15 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   44 +-
 .../include/mach/reset_manager_arria10.h   |  144 +++
 .../mach-socfpga/include/mach/reset_manager_gen5.h |   47 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |  380 +++
 .../arm/mach-socfpga/include/mach/system_manager.h |  177 ++--
 .../include/mach/system_manager_arria10.h  |   81 ++
 .../include/mach/system_manager_gen5.h |  122 +++
 arch/arm/mach-socfpga/misc.c   |  361 +--
 arch/arm/mach-socfpga/misc_arria10.c   |  254 +
 arch/arm/mach-socfpga/misc_gen5.c  |  356 +++
 arch/arm/mach-socfpga/pinmux_arria10.c |   96 ++
 arch/arm/mach-socfpga/reset_manager.c  |   93 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  380 +++
 arch/arm/mach-socfpga/reset_manager_gen5.c |  113 ++
 arch/arm/mach-socfpga/spl.c|   55 +-
 arch/arm/mach-socfpga/system_manager.c |   85 --
 arch/arm/mach-socfpga/system_manager_gen5.c|   85 ++
 board/altera/arria10-socdk/Kconfig |   18 +
 board/altera/arria10-socdk/Makefile|7 +
 board/altera/arria10-socdk/socfpga.c   |7 +
 configs/socfpga_arria10_defconfig  |   30 +
 drivers/Kconfig|2 +
 drivers/ddr/Kconfig|1 +
 drivers/ddr/altera/Kconfig |6 +
 drivers/fpga/socfpga.c |6 +
 include/configs/socfpga_arria10_socdk.h|   67 ++
 include/configs/socfpga_common.h   |   33 +-
 include/dt-bindings/reset/altr,rst-mgr-a10.h   |  103 ++
 include/fdtdec.h   |8 +
 lib/fdtdec.c   |8 +
 45 files 

[U-Boot] [PATCH 6/8] sunxi: video: Add A64/H3/H5 HDMI driver

[Jernej Skrabec]

This commit adds support for HDMI output.

Signed-off-by: Jernej Skrabec 
---

 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |   8 +
 arch/arm/include/asm/arch-sunxi/display2.h  | 124 +
 board/sunxi/Kconfig |  10 +
 drivers/video/sunxi/Makefile|   1 +
 drivers/video/sunxi/sunxi_de2.c | 258 ++
 drivers/video/sunxi/sunxi_dw_hdmi.c | 389 
 include/configs/sunxi-common.h  |   5 +
 7 files changed, 795 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/display2.h
 create mode 100644 drivers/video/sunxi/sunxi_de2.c
 create mode 100644 drivers/video/sunxi/sunxi_dw_hdmi.c

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index ea672fe844..3ce46d024e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -18,6 +18,8 @@
 #define SUNXI_SRAM_D_BASE  0x0001  /* 4 kiB */
 #define SUNXI_SRAM_B_BASE  0x0002  /* 64 kiB (secure) */
 
+#define SUNXI_DE2_BASE 0x0100
+
 #ifdef CONFIG_MACH_SUN8I_A83T
 #define SUNXI_CPUCFG_BASE  0x0170
 #endif
@@ -46,7 +48,9 @@
 #define SUNXI_USB1_BASE0x01c14000
 #endif
 #define SUNXI_SS_BASE  0x01c15000
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
 #define SUNXI_HDMI_BASE0x01c16000
+#endif
 #define SUNXI_SPI2_BASE0x01c17000
 #define SUNXI_SATA_BASE0x01c18000
 #ifdef CONFIG_SUNXI_GEN_SUN4I
@@ -164,6 +168,10 @@ defined(CONFIG_MACH_SUN50I)
 #define SUNXI_MP_BASE  0x01e8
 #define SUNXI_AVG_BASE 0x01ea
 
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#define SUNXI_HDMI_BASE0x01ee
+#endif
+
 #define SUNXI_RTC_BASE 0x01f0
 #define SUNXI_PRCM_BASE0x01f01400
 
diff --git a/arch/arm/include/asm/arch-sunxi/display2.h 
b/arch/arm/include/asm/arch-sunxi/display2.h
new file mode 100644
index 00..b5875f9605
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/display2.h
@@ -0,0 +1,124 @@
+/*
+ * Sunxi platform display controller register and constant defines
+ *
+ * (C) Copyright 2017 Jernej Skrabec 
+ *
+ * Based on out of tree Linux DRM driver defines:
+ * Copyright (C) 2016 Jean-Francois Moine 
+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
+*
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_DISPLAY2_H
+#define _SUNXI_DISPLAY2_H
+
+/* internal clock settings */
+struct de_clk {
+   u32 gate_cfg;
+   u32 bus_cfg;
+   u32 rst_cfg;
+   u32 div_cfg;
+   u32 sel_cfg;
+};
+
+/* global control */
+struct de_glb {
+   u32 ctl;
+   u32 status;
+   u32 dbuff;
+   u32 size;
+};
+
+/* alpha blending */
+struct de_bld {
+   u32 fcolor_ctl;
+   struct {
+   u32 fcolor;
+   u32 insize;
+   u32 offset;
+   u32 dum;
+   } attr[4];
+   u32 dum0[15];
+   u32 route;
+   u32 premultiply;
+   u32 bkcolor;
+   u32 output_size;
+   u32 bld_mode[4];
+   u32 dum1[4];
+   u32 ck_ctl;
+   u32 ck_cfg;
+   u32 dum2[2];
+   u32 ck_max[4];
+   u32 dum3[4];
+   u32 ck_min[4];
+   u32 dum4[3];
+   u32 out_ctl;
+};
+
+/* VI channel */
+struct de_vi {
+   struct {
+   u32 attr;
+   u32 size;
+   u32 coord;
+   u32 pitch[3];
+   u32 top_laddr[3];
+   u32 bot_laddr[3];
+   } cfg[4];
+   u32 fcolor[4];
+   u32 top_haddr[3];
+   u32 bot_haddr[3];
+   u32 ovl_size[2];
+   u32 hori[2];
+   u32 vert[2];
+};
+
+struct de_ui {
+   struct {
+   u32 attr;
+   u32 size;
+   u32 coord;
+   u32 pitch;
+   u32 top_laddr;
+   u32 bot_laddr;
+   u32 fcolor;
+   u32 dum;
+   } cfg[4];
+   u32 top_haddr;
+   u32 bot_haddr;
+   u32 ovl_size;
+};
+
+/*
+ * DE register constants.
+ */
+#define SUNXI_DE2_MUX0_BASE(SUNXI_DE2_BASE + 0x10)
+#define SUNXI_DE2_MUX1_BASE(SUNXI_DE2_BASE + 0x20)
+
+#define SUNXI_DE2_MUX_GLB_REGS 0x0
+#define SUNXI_DE2_MUX_BLD_REGS 0x01000
+#define SUNXI_DE2_MUX_CHAN_REGS0x02000
+#define SUNXI_DE2_MUX_CHAN_SZ  0x1000
+#define SUNXI_DE2_MUX_VSU_REGS 0x2
+#define SUNXI_DE2_MUX_GSU1_REGS0x3
+#define SUNXI_DE2_MUX_GSU2_REGS0x4
+#define SUNXI_DE2_MUX_GSU3_REGS0x5
+#define 

[U-Boot] [PATCH 1/8] rockchip: video: Fix HDMI audio clocks

[Jernej Skrabec]

Function hdmi_lookup_n_cts() is feed with clock in Hz, which gets
compared with clocks in kHz. Fix that by converting all clocks to Hz.

Signed-off-by: Jernej Skrabec 
---

 drivers/video/rockchip/rk_hdmi.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 7b0c43b858..274d108851 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -32,37 +32,37 @@ struct rk_hdmi_priv {
 
 static const struct tmds_n_cts n_cts_table[] = {
{
-   .tmds = 25175, .n = 6144, .cts = 25175,
+   .tmds = 25175000, .n = 6144, .cts = 25175,
}, {
-   .tmds = 25200, .n = 6144, .cts = 25200,
+   .tmds = 2520, .n = 6144, .cts = 25200,
}, {
-   .tmds = 27000, .n = 6144, .cts = 27000,
+   .tmds = 2700, .n = 6144, .cts = 27000,
}, {
-   .tmds = 27027, .n = 6144, .cts = 27027,
+   .tmds = 27027000, .n = 6144, .cts = 27027,
}, {
-   .tmds = 4, .n = 6144, .cts = 4,
+   .tmds = 4000, .n = 6144, .cts = 4,
}, {
-   .tmds = 54000, .n = 6144, .cts = 54000,
+   .tmds = 5400, .n = 6144, .cts = 54000,
}, {
-   .tmds = 54054, .n = 6144, .cts = 54054,
+   .tmds = 54054000, .n = 6144, .cts = 54054,
}, {
-   .tmds = 65000, .n = 6144, .cts = 65000,
+   .tmds = 6500, .n = 6144, .cts = 65000,
}, {
-   .tmds = 74176, .n = 11648, .cts = 140625,
+   .tmds = 74176000, .n = 11648, .cts = 140625,
}, {
-   .tmds = 74250, .n = 6144, .cts = 74250,
+   .tmds = 7425, .n = 6144, .cts = 74250,
}, {
-   .tmds = 83500, .n = 6144, .cts = 83500,
+   .tmds = 8350, .n = 6144, .cts = 83500,
}, {
-   .tmds = 106500, .n = 6144, .cts = 106500,
+   .tmds = 10650, .n = 6144, .cts = 106500,
}, {
-   .tmds = 108000, .n = 6144, .cts = 108000,
+   .tmds = 10800, .n = 6144, .cts = 108000,
}, {
-   .tmds = 148352, .n = 5824, .cts = 140625,
+   .tmds = 148352000, .n = 5824, .cts = 140625,
}, {
-   .tmds = 148500, .n = 6144, .cts = 148500,
+   .tmds = 14850, .n = 6144, .cts = 148500,
}, {
-   .tmds = 297000, .n = 5120, .cts = 247500,
+   .tmds = 29700, .n = 5120, .cts = 247500,
}
 };
 
-- 
2.12.0

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[U-Boot] [PATCH 7/8] sunxi: Enable A64/H3/H5 video driver in defconfigs

[Jernej Skrabec]

Signed-off-by: Jernej Skrabec 
---

 configs/orangepi_2_defconfig   | 1 +
 configs/orangepi_lite_defconfig| 1 +
 configs/orangepi_one_defconfig | 1 +
 configs/orangepi_pc2_defconfig | 1 +
 configs/orangepi_pc_defconfig  | 1 +
 configs/orangepi_pc_plus_defconfig | 1 +
 configs/orangepi_plus2e_defconfig  | 1 +
 configs/orangepi_plus_defconfig| 1 +
 configs/pine64_plus_defconfig  | 1 +
 9 files changed, 9 insertions(+)

diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 74712c6d6e..6af44691ad 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -19,3 +19,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
index 38f4583fd0..79b6b335a1 100644
--- a/configs/orangepi_lite_defconfig
+++ b/configs/orangepi_lite_defconfig
@@ -15,3 +15,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 56c9a871b1..17b287c925 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -16,3 +16,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 19a5c2b882..7cd8c5c23b 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -17,3 +17,4 @@ CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SPL_SPI_SUNXI=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 8d331bdf91..1df0721493 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -18,3 +18,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_pc_plus_defconfig 
b/configs/orangepi_pc_plus_defconfig
index 636599c361..116f532157 100644
--- a/configs/orangepi_pc_plus_defconfig
+++ b/configs/orangepi_pc_plus_defconfig
@@ -19,3 +19,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_plus2e_defconfig 
b/configs/orangepi_plus2e_defconfig
index 60f4eaa655..ff88613b7d 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -20,3 +20,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 78be69eec5..d889adb63c 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -21,3 +21,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 7c7d86ff80..ade7a64ab8 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -14,3 +14,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
-- 
2.12.0

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Re: [U-Boot] [linux-sunxi] [PATCH 8/8] [DO NOT MERGE] sunxi: power: add AXP803 support

[Icenowy Zheng]

2017年3月9日 07:34于 Jernej Skrabec 写道：
>
> From: Icenowy Zheng  

I'm making newer version of this patch.

>
> The A64 uses the AXP803 as its PMIC. 
>
> Signed-off-by: Icenowy Zheng  
>
> Signed-off-by: Jernej Skrabec  
> --- 
>
> arch/arm/mach-sunxi/Makefile   |   3 + 
> arch/arm/mach-sunxi/pmic_bus.c |   6 +- 
> arch/arm/mach-sunxi/rsb.c  |   2 +- 
> board/sunxi/board.c    |  31 ++--- 
> drivers/power/Kconfig  |  87 -- 
> drivers/power/Makefile |   1 + 
> drivers/power/axp803.c | 256 
> + 
> drivers/power/axp818.c |   2 +- 
> include/axp803.h   |  73  
> include/axp_pmic.h |   3 + 
> 10 files changed, 414 insertions(+), 50 deletions(-) 
> create mode 100644 drivers/power/axp803.c 
> create mode 100644 include/axp803.h 
>
> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile 
> index efab4811ee..861a52c6d0 100644 
> --- a/arch/arm/mach-sunxi/Makefile 
> +++ b/arch/arm/mach-sunxi/Makefile 
> @@ -19,9 +19,11 @@ endif 
> obj-$(CONFIG_MACH_SUN6I) += prcm.o 
> obj-$(CONFIG_MACH_SUN8I) += prcm.o 
> obj-$(CONFIG_MACH_SUN9I) += prcm.o 
> +obj-$(CONFIG_MACH_SUN50I) += prcm.o 
> obj-$(CONFIG_MACH_SUN6I) += p2wi.o 
> obj-$(CONFIG_MACH_SUN8I) += rsb.o 
> obj-$(CONFIG_MACH_SUN9I) += rsb.o 
> +obj-$(CONFIG_MACH_SUN50I) += rsb.o 
> obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o 
> obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o 
> obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o 
> @@ -37,6 +39,7 @@ obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o 
> obj-$(CONFIG_AXP152_POWER) += pmic_bus.o 
> obj-$(CONFIG_AXP209_POWER) += pmic_bus.o 
> obj-$(CONFIG_AXP221_POWER) += pmic_bus.o 
> +obj-$(CONFIG_AXP803_POWER) += pmic_bus.o 
> obj-$(CONFIG_AXP809_POWER) += pmic_bus.o 
> obj-$(CONFIG_AXP818_POWER) += pmic_bus.o 
>
> diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c 
> index 7c57f02792..0ac64a97cf 100644 
> --- a/arch/arm/mach-sunxi/pmic_bus.c 
> +++ b/arch/arm/mach-sunxi/pmic_bus.c 
> @@ -36,7 +36,7 @@ int pmic_bus_init(void) 
> if (!needs_init) 
> return 0; 
>
> -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
> CONFIG_AXP818_POWER 
> +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined 
> CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 
> # ifdef CONFIG_MACH_SUN6I 
> p2wi_init(); 
> ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, 
> @@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data) 
> return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); 
> #elif defined CONFIG_AXP209_POWER 
> return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); 
> -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
> CONFIG_AXP818_POWER 
> +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined 
> CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 
> # ifdef CONFIG_MACH_SUN6I 
> return p2wi_read(reg, data); 
> # else 
> @@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data) 
> return i2c_write(AXP152_I2C_ADDR, reg, 1, , 1); 
> #elif defined CONFIG_AXP209_POWER 
> return i2c_write(AXP209_I2C_ADDR, reg, 1, , 1); 
> -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
> CONFIG_AXP818_POWER 
> +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined 
> CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 
> # ifdef CONFIG_MACH_SUN6I 
> return p2wi_write(reg, data); 
> # else 
> diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c 
> index 6fd11f1529..28d05e962a 100644 
> --- a/arch/arm/mach-sunxi/rsb.c 
> +++ b/arch/arm/mach-sunxi/rsb.c 
> @@ -20,7 +20,7 @@ static int rsb_set_device_mode(void); 
>
> static void rsb_cfg_io(void) 
> { 
> -#ifdef CONFIG_MACH_SUN8I 
> +#if defined CONFIG_MACH_SUN8I || defined CONFIG_MACH_SUN50I 
> sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); 
> sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); 
> sunxi_gpio_set_pull(SUNXI_GPL(0), 1); 
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c 
> index b9660128e5..75e53bebbd 100644 
> --- a/board/sunxi/board.c 
> +++ b/board/sunxi/board.c 
> @@ -487,26 +487,27 @@ void sunxi_board_init(void) 
> #endif 
>
> #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 
> - defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 
> - defined CONFIG_AXP818_POWER 
> + defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ 
> + defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 
> power_failed = axp_init(); 
>
> -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 
> - defined CONFIG_AXP818_POWER 
> +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ 
> + defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 
> power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 
> #endif 
> 

[U-Boot] [PATCH 8/8] [DO NOT MERGE] sunxi: power: add AXP803 support

[Jernej Skrabec]

From: Icenowy Zheng 

The A64 uses the AXP803 as its PMIC.

Signed-off-by: Icenowy Zheng 

Signed-off-by: Jernej Skrabec 
---

 arch/arm/mach-sunxi/Makefile   |   3 +
 arch/arm/mach-sunxi/pmic_bus.c |   6 +-
 arch/arm/mach-sunxi/rsb.c  |   2 +-
 board/sunxi/board.c|  31 ++---
 drivers/power/Kconfig  |  87 --
 drivers/power/Makefile |   1 +
 drivers/power/axp803.c | 256 +
 drivers/power/axp818.c |   2 +-
 include/axp803.h   |  73 
 include/axp_pmic.h |   3 +
 10 files changed, 414 insertions(+), 50 deletions(-)
 create mode 100644 drivers/power/axp803.c
 create mode 100644 include/axp803.h

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index efab4811ee..861a52c6d0 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -19,9 +19,11 @@ endif
 obj-$(CONFIG_MACH_SUN6I)   += prcm.o
 obj-$(CONFIG_MACH_SUN8I)   += prcm.o
 obj-$(CONFIG_MACH_SUN9I)   += prcm.o
+obj-$(CONFIG_MACH_SUN50I)  += prcm.o
 obj-$(CONFIG_MACH_SUN6I)   += p2wi.o
 obj-$(CONFIG_MACH_SUN8I)   += rsb.o
 obj-$(CONFIG_MACH_SUN9I)   += rsb.o
+obj-$(CONFIG_MACH_SUN50I)  += rsb.o
 obj-$(CONFIG_MACH_SUN4I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)   += clock_sun6i.o
@@ -37,6 +39,7 @@ obj-$(CONFIG_MACH_SUN9I)  += clock_sun9i.o gtbus_sun9i.o
 obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
+obj-$(CONFIG_AXP803_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP809_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
 
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 7c57f02792..0ac64a97cf 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -36,7 +36,7 @@ int pmic_bus_init(void)
if (!needs_init)
return 0;
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined 
CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
p2wi_init();
ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data)
return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
 #elif defined CONFIG_AXP209_POWER
return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined 
CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
return p2wi_read(reg, data);
 # else
@@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data)
return i2c_write(AXP152_I2C_ADDR, reg, 1, , 1);
 #elif defined CONFIG_AXP209_POWER
return i2c_write(AXP209_I2C_ADDR, reg, 1, , 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined 
CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
return p2wi_write(reg, data);
 # else
diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c
index 6fd11f1529..28d05e962a 100644
--- a/arch/arm/mach-sunxi/rsb.c
+++ b/arch/arm/mach-sunxi/rsb.c
@@ -20,7 +20,7 @@ static int rsb_set_device_mode(void);
 
 static void rsb_cfg_io(void)
 {
-#ifdef CONFIG_MACH_SUN8I
+#if defined CONFIG_MACH_SUN8I || defined CONFIG_MACH_SUN50I
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index b9660128e5..75e53bebbd 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -487,26 +487,27 @@ void sunxi_board_init(void)
 #endif
 
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
-   defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-   defined CONFIG_AXP818_POWER
+   defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+   defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
power_failed = axp_init();
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-   defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+   defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
 #endif
power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
-#if 

[U-Boot] [PATCH 5/8] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

[Jernej Skrabec]

This is needed for HDMI, which will be added later.

Signed-off-by: Jernej Skrabec 
---

 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 54 +++
 arch/arm/mach-sunxi/clock_sun6i.c | 40 +++-
 drivers/video/sunxi/lcdc.c|  4 ++
 include/configs/sun50i.h  |  2 +
 include/configs/sun8i.h   |  4 ++
 scripts/config_whitelist.txt  |  1 +
 6 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 1aefd5a64c..ebb642747b 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
u32 dram_pll_cfg;   /* 0xf8 PLL_DDR cfg register, A33 only */
u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
u32 dram_clk_gate;  /* 0x100 DRAM module gating */
+#ifdef CONFIG_SUNXI_DE2
+   u32 de_clk_cfg; /* 0x104 DE module clock */
+#else
u32 be0_clk_cfg;/* 0x104 BE0 module clock */
+#endif
u32 be1_clk_cfg;/* 0x108 BE1 module clock */
u32 fe0_clk_cfg;/* 0x10c FE0 module clock */
u32 fe1_clk_cfg;/* 0x110 FE1 module clock */
u32 mp_clk_cfg; /* 0x114 MP module clock */
+#ifdef CONFIG_SUNXI_DE2
+   u32 lcd0_clk_cfg;   /* 0x118 LCD0 module clock */
+   u32 lcd1_clk_cfg;   /* 0x11c LCD1 module clock */
+#else
u32 lcd0_ch0_clk_cfg;   /* 0x118 LCD0 CH0 module clock */
u32 lcd1_ch0_clk_cfg;   /* 0x11c LCD1 CH0 module clock */
+#endif
u32 reserved14[3];
u32 lcd0_ch1_clk_cfg;   /* 0x12c LCD0 CH1 module clock */
u32 lcd1_ch1_clk_cfg;   /* 0x130 LCD1 CH1 module clock */
@@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
u32 dmic_clk_cfg;   /* 0x148 Digital Mic module clock*/
u32 reserved15;
u32 hdmi_clk_cfg;   /* 0x150 HDMI module clock */
+#ifdef CONFIG_SUNXI_DE2
+   u32 hdmi_slow_clk_cfg;  /* 0x154 HDMI slow module clock */
+#else
u32 ps_clk_cfg; /* 0x154 PS module clock */
+#endif
u32 mtc_clk_cfg;/* 0x158 MTC module clock */
u32 mbus0_clk_cfg;  /* 0x15c MBUS0 module clock */
u32 mbus1_clk_cfg;  /* 0x160 MBUS1 module clock */
@@ -193,6 +206,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL3_CTRL_N_MASK   (0x7f << CCM_PLL3_CTRL_N_SHIFT)
 #define CCM_PLL3_CTRL_N(n) n) - 1) & 0x7f) << 8)
 #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
+#define CCM_PLL3_CTRL_LOCK (0x1 << 28)
 #define CCM_PLL3_CTRL_EN   (0x1 << 31)
 
 #define CCM_PLL5_CTRL_M(n) n) - 1) & 0x3) << 0)
@@ -222,6 +236,16 @@ struct sunxi_ccm_reg {
 #define CCM_MIPI_PLL_CTRL_LDO_EN   (0x3 << 22)
 #define CCM_MIPI_PLL_CTRL_EN   (0x1 << 31)
 
+#define CCM_PLL10_CTRL_M_SHIFT 0
+#define CCM_PLL10_CTRL_M_MASK  (0xf << CCM_PLL10_CTRL_M_SHIFT)
+#define CCM_PLL10_CTRL_M(n)n) - 1) & 0xf) << 0)
+#define CCM_PLL10_CTRL_N_SHIFT 8
+#define CCM_PLL10_CTRL_N_MASK  (0x7f << CCM_PLL10_CTRL_N_SHIFT)
+#define CCM_PLL10_CTRL_N(n)n) - 1) & 0x7f) << 8)
+#define CCM_PLL10_CTRL_INTEGER_MODE(0x1 << 24)
+#define CCM_PLL10_CTRL_LOCK(0x1 << 28)
+#define CCM_PLL10_CTRL_EN  (0x1 << 31)
+
 #define CCM_PLL11_CTRL_N(n)n) - 1) & 0x3f) << 8)
 #define CCM_PLL11_CTRL_SIGMA_DELTA_EN  (0x1 << 24)
 #define CCM_PLL11_CTRL_UPD (0x1 << 30)
@@ -273,9 +297,15 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_DRC0   25
 #define AHB_GATE_OFFSET_DE_FE0 14
 #define AHB_GATE_OFFSET_DE_BE0 12
+#define AHB_GATE_OFFSET_DE 12
 #define AHB_GATE_OFFSET_HDMI   11
+#ifndef CONFIG_SUNXI_DE2
 #define AHB_GATE_OFFSET_LCD1   5
 #define AHB_GATE_OFFSET_LCD0   4
+#else
+#define AHB_GATE_OFFSET_LCD1   4
+#define AHB_GATE_OFFSET_LCD0   3
+#endif
 
 #define CCM_MMC_CTRL_M(x)  ((x) - 1)
 #define CCM_MMC_CTRL_OCLK_DLY(x)   ((x) << 8)
@@ -357,6 +387,12 @@ struct sunxi_ccm_reg {
 #define CCM_LCD_CH1_CTRL_PLL7_2X   (3 << 24)
 #define CCM_LCD_CH1_CTRL_GATE  (0x1 << 31)
 
+#define CCM_LCD0_CTRL_GATE (0x1 << 31)
+#define CCM_LCD0_CTRL_M(n) n) - 1) & 0xf) << 0)
+
+#define CCM_LCD1_CTRL_GATE (0x1 << 31)
+#define CCM_LCD1_CTRL_M(n) n) - 1) & 0xf) << 0)
+
 #define CCM_HDMI_CTRL_M(n) n) - 1) & 0xf) << 0)
 #define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
 #define CCM_HDMI_CTRL_PLL3 (0 << 24)
@@ -366,6 +402,8 @@ struct sunxi_ccm_reg {
 #define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
 #define CCM_HDMI_CTRL_GATE (0x1 << 31)
 
+#define CCM_HDMI_SLOW_CTRL_DDC_GATE

[U-Boot] [PATCH 3/8] rockchip: video: Split out HDMI controller code

[Jernej Skrabec]

Designware HDMI controller and phy are used in other SoCs as well. Split
out platform independent code.

DW HDMI has 8 bit registers but they can be represented as 32 bit
registers as well. Add support to select access mode.

EDID reading code use reading by blocks which is not supported by other
SoCs in general. Make it more general using byte by byte approach, which
is also used in Linux driver.

Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
Support custom phys by making controller code independent from phy code.

Signed-off-by: Jernej Skrabec 
---

 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 --
 drivers/video/dw_hdmi.c  | 764 +++
 drivers/video/rockchip/Makefile  |   2 +-
 drivers/video/rockchip/rk_hdmi.c | 757 +-
 drivers/video/rockchip/rk_vop.c  |   1 -
 include/dw_hdmi.h| 486 ++
 6 files changed, 1275 insertions(+), 1191 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
 create mode 100644 drivers/video/dw_hdmi.c
 create mode 100644 include/dw_hdmi.h

diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
deleted file mode 100644
index 0b51d40882..00
--- a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Copyright 2014 Rockchip Inc.
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_HDMI_H
-#define _ASM_ARCH_HDMI_H
-
-
-#define HDMI_EDID_BLOCK_SIZE128
-
-struct rk3288_hdmi {
-   u32 reserved0[0x100];
-   u32 ih_fc_stat0;
-   u32 ih_fc_stat1;
-   u32 ih_fc_stat2;
-   u32 ih_as_stat0;
-   u32 ih_phy_stat0;
-   u32 ih_i2cm_stat0;
-   u32 ih_cec_stat0;
-   u32 ih_vp_stat0;
-   u32 ih_i2cmphy_stat0;
-   u32 ih_ahbdmaaud_stat0;
-   u32 reserved1[0x17f-0x109];
-   u32 ih_mute_fc_stat0;
-   u32 ih_mute_fc_stat1;
-   u32 ih_mute_fc_stat2;
-   u32 ih_mute_as_stat0;
-   u32 ih_mute_phy_stat0;
-   u32 ih_mute_i2cm_stat0;
-   u32 ih_mute_cec_stat0;
-   u32 ih_mute_vp_stat0;
-   u32 ih_mute_i2cmphy_stat0;
-   u32 ih_mute_ahbdmaaud_stat0;
-   u32 reserved2[0x1fe - 0x189];
-   u32 ih_mute;
-   u32 tx_invid0;
-   u32 tx_instuffing;
-   u32 tx_gydata0;
-   u32 tx_gydata1;
-   u32 tx_rcrdata0;
-   u32 tx_rcrdata1;
-   u32 tx_bcbdata0;
-   u32 tx_bcbdata1;
-   u32 reserved3[0x7ff-0x207];
-   u32 vp_status;
-   u32 vp_pr_cd;
-   u32 vp_stuff;
-   u32 vp_remap;
-   u32 vp_conf;
-   u32 vp_stat;
-   u32 vp_int;
-   u32 vp_mask;
-   u32 vp_pol;
-   u32 reserved4[0xfff-0x808];
-   u32 fc_invidconf;
-   u32 fc_inhactv0;
-   u32 fc_inhactv1;
-   u32 fc_inhblank0;
-   u32 fc_inhblank1;
-   u32 fc_invactv0;
-   u32 fc_invactv1;
-   u32 fc_invblank;
-   u32 fc_hsyncindelay0;
-   u32 fc_hsyncindelay1;
-   u32 fc_hsyncinwidth0;
-   u32 fc_hsyncinwidth1;
-   u32 fc_vsyncindelay;
-   u32 fc_vsyncinwidth;
-   u32 fc_infreq0;
-   u32 fc_infreq1;
-   u32 fc_infreq2;
-   u32 fc_ctrldur;
-   u32 fc_exctrldur;
-   u32 fc_exctrlspac;
-   u32 fc_ch0pream;
-   u32 fc_ch1pream;
-   u32 fc_ch2pream;
-   u32 fc_aviconf3;
-   u32 fc_gcp;
-   u32 fc_aviconf0;
-   u32 fc_aviconf1;
-   u32 fc_aviconf2;
-   u32 fc_avivid;
-   u32 fc_avietb0;
-   u32 fc_avietb1;
-   u32 fc_avisbb0;
-   u32 fc_avisbb1;
-   u32 fc_avielb0;
-   u32 fc_avielb1;
-   u32 fc_avisrb0;
-   u32 fc_avisrb1;
-   u32 fc_audiconf0;
-   u32 fc_audiconf1;
-   u32 fc_audiconf2;
-   u32 fc_audiconf3;
-   u32 fc_vsdieeeid0;
-   u32 fc_vsdsize;
-   u32 reserved7[0x2fff-0x102a];
-   u32 phy_conf0;
-   u32 phy_tst0;
-   u32 phy_tst1;
-   u32 phy_tst2;
-   u32 phy_stat0;
-   u32 phy_int0;
-   u32 phy_mask0;
-   u32 phy_pol0;
-   u32 reserved8[0x301f-0x3007];
-   u32 phy_i2cm_slave_addr;
-   u32 phy_i2cm_address_addr;
-   u32 phy_i2cm_datao_1_addr;
-   u32 phy_i2cm_datao_0_addr;
-   u32 phy_i2cm_datai_1_addr;
-   u32 phy_i2cm_datai_0_addr;
-   u32 phy_i2cm_operation_addr;
-   u32 phy_i2cm_int_addr;
-   u32 phy_i2cm_ctlint_addr;
-   u32 phy_i2cm_div_addr;
-   u32 phy_i2cm_softrstz_addr;
-   u32 phy_i2cm_ss_scl_hcnt_1_addr;
-   u32 phy_i2cm_ss_scl_hcnt_0_addr;
-   u32 phy_i2cm_ss_scl_lcnt_1_addr;
-   u32 phy_i2cm_ss_scl_lcnt_0_addr;
-   u32 phy_i2cm_fs_scl_hcnt_1_addr;
-   u32 phy_i2cm_fs_scl_hcnt_0_addr;
-   u32 phy_i2cm_fs_scl_lcnt_1_addr;
-   u32 

[U-Boot] [PATCH 4/8] sunxi: video: Split out TCON code

[Jernej Skrabec]

TCON unit has similar layout and functionality also on newer SoCs. This
commit splits out TCON code for easier reuse later.

Signed-off-by: Jernej Skrabec 
---

 arch/arm/include/asm/arch-sunxi/display.h | 103 --
 arch/arm/include/asm/arch-sunxi/lcdc.h| 128 +
 drivers/video/Makefile|   2 +-
 drivers/video/sunxi/Makefile  |   8 ++
 drivers/video/sunxi/lcdc.c| 205 +++
 drivers/video/{ => sunxi}/sunxi_display.c | 224 ++
 6 files changed, 387 insertions(+), 283 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/lcdc.h
 create mode 100644 drivers/video/sunxi/Makefile
 create mode 100644 drivers/video/sunxi/lcdc.c
 rename drivers/video/{ => sunxi}/sunxi_display.c (86%)

diff --git a/arch/arm/include/asm/arch-sunxi/display.h 
b/arch/arm/include/asm/arch-sunxi/display.h
index b64f310b8b..93803addfb 100644
--- a/arch/arm/include/asm/arch-sunxi/display.h
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -157,52 +157,6 @@ struct sunxi_de_be_reg {
u32 output_color_coef[12];  /* 0x9d0 */
 };
 
-struct sunxi_lcdc_reg {
-   u32 ctrl;   /* 0x00 */
-   u32 int0;   /* 0x04 */
-   u32 int1;   /* 0x08 */
-   u8 res0[0x04];  /* 0x0c */
-   u32 tcon0_frm_ctrl; /* 0x10 */
-   u32 tcon0_frm_seed[6];  /* 0x14 */
-   u32 tcon0_frm_table[4]; /* 0x2c */
-   u8 res1[4]; /* 0x3c */
-   u32 tcon0_ctrl; /* 0x40 */
-   u32 tcon0_dclk; /* 0x44 */
-   u32 tcon0_timing_active;/* 0x48 */
-   u32 tcon0_timing_h; /* 0x4c */
-   u32 tcon0_timing_v; /* 0x50 */
-   u32 tcon0_timing_sync;  /* 0x54 */
-   u32 tcon0_hv_intf;  /* 0x58 */
-   u8 res2[0x04];  /* 0x5c */
-   u32 tcon0_cpu_intf; /* 0x60 */
-   u32 tcon0_cpu_wr_dat;   /* 0x64 */
-   u32 tcon0_cpu_rd_dat0;  /* 0x68 */
-   u32 tcon0_cpu_rd_dat1;  /* 0x6c */
-   u32 tcon0_ttl_timing0;  /* 0x70 */
-   u32 tcon0_ttl_timing1;  /* 0x74 */
-   u32 tcon0_ttl_timing2;  /* 0x78 */
-   u32 tcon0_ttl_timing3;  /* 0x7c */
-   u32 tcon0_ttl_timing4;  /* 0x80 */
-   u32 tcon0_lvds_intf;/* 0x84 */
-   u32 tcon0_io_polarity;  /* 0x88 */
-   u32 tcon0_io_tristate;  /* 0x8c */
-   u32 tcon1_ctrl; /* 0x90 */
-   u32 tcon1_timing_source;/* 0x94 */
-   u32 tcon1_timing_scale; /* 0x98 */
-   u32 tcon1_timing_out;   /* 0x9c */
-   u32 tcon1_timing_h; /* 0xa0 */
-   u32 tcon1_timing_v; /* 0xa4 */
-   u32 tcon1_timing_sync;  /* 0xa8 */
-   u8 res3[0x44];  /* 0xac */
-   u32 tcon1_io_polarity;  /* 0xf0 */
-   u32 tcon1_io_tristate;  /* 0xf4 */
-   u8 res4[0x108]; /* 0xf8 */
-   u32 mux_ctrl;   /* 0x200 */
-   u8 res5[0x1c];  /* 0x204 */
-   u32 lvds_ana0;  /* 0x220 */
-   u32 lvds_ana1;  /* 0x224 */
-};
-
 struct sunxi_hdmi_reg {
u32 version_id; /* 0x000 */
u32 ctrl;   /* 0x004 */
@@ -347,63 +301,6 @@ struct sunxi_tve_reg {
 #define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE   1
 
 /*
- * LCDC register constants.
- */
-#define SUNXI_LCDC_X(x)(((x) - 1) << 16)
-#define SUNXI_LCDC_Y(y)(((y) - 1) << 0)
-#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
-#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
-#define SUNXI_LCDC_CTRL_IO_MAP_MASK(1 << 0)
-#define SUNXI_LCDC_CTRL_IO_MAP_TCON0   (0 << 0)
-#define SUNXI_LCDC_CTRL_IO_MAP_TCON1   (1 << 0)
-#define SUNXI_LCDC_CTRL_TCON_ENABLE(1 << 31)
-#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666   ((1 << 31) | (0 << 4))
-#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565   ((1 << 31) | (5 << 4))
-#define SUNXI_LCDC_TCON0_FRM_SEED  0x
-#define SUNXI_LCDC_TCON0_FRM_TAB0  0x0101
-#define SUNXI_LCDC_TCON0_FRM_TAB1  0x1515
-#define SUNXI_LCDC_TCON0_FRM_TAB2  0x5757
-#define SUNXI_LCDC_TCON0_FRM_TAB3  0x7f7f
-#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
-#define SUNXI_LCDC_TCON0_CTRL_ENABLE   (1 << 31)
-#define SUNXI_LCDC_TCON0_DCLK_DIV(n)   ((n) << 0)
-#define SUNXI_LCDC_TCON0_DCLK_ENABLE   (0xf << 28)
-#define SUNXI_LCDC_TCON0_TIMING_H_BP(n)(((n) - 1) << 0)
-#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
-#define 

[U-Boot] [PATCH 2/8] rockchip: video: Remove CSC initialization (HDMI)

[Jernej Skrabec]

Despite the comment in the code, CSC unit is never used. According to
the only public description of DW HDMI controller (i.MX6 manual), CSC
unit is bypassed in MC_FLOWCTRL register and then actually powered
down in MC_CLKDIS register.

Signed-off-by: Jernej Skrabec 
---

 drivers/video/rockchip/rk_hdmi.c | 39 ---
 1 file changed, 39 deletions(-)

diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 274d108851..c8608db23c 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -124,12 +124,6 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = 
{
}
 };
 
-static const u32 csc_coeff_default[3][4] = {
-   { 0x2000, 0x, 0x, 0x },
-   { 0x, 0x2000, 0x, 0x },
-   { 0x, 0x, 0x2000, 0x }
-};
-
 static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 
cts)
 {
uint cts3;
@@ -220,37 +214,6 @@ static void hdmi_video_sample(struct rk3288_hdmi *regs)
writel(0x0, >tx_bcbdata1);
 }
 
-static void hdmi_update_csc_coeffs(struct rk3288_hdmi *regs)
-{
-   u32 i, j;
-   u32 csc_scale = 1;
-
-   /* the csc registers are sequential, alternating msb then lsb */
-   for (i = 0; i < ARRAY_SIZE(csc_coeff_default); i++) {
-   for (j = 0; j < ARRAY_SIZE(csc_coeff_default[0]); j++) {
-   u32 coeff = csc_coeff_default[i][j];
-   writel(coeff >> 8, >csc_coef[i][j].msb);
-   writel(coeff && 0xff, >csc_coef[i][j].lsb);
-   }
-   }
-
-   clrsetbits_le32(>csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
-   csc_scale);
-}
-
-static void hdmi_video_csc(struct rk3288_hdmi *regs)
-{
-   u32 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
-   u32 interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
-
-   /* configure the csc registers */
-   writel(interpolation, >csc_cfg);
-   clrsetbits_le32(>csc_scale,
-   HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth);
-
-   hdmi_update_csc_coeffs(regs);
-}
-
 static void hdmi_video_packetize(struct rk3288_hdmi *regs)
 {
u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
@@ -467,7 +430,6 @@ static int hdmi_phy_init(struct rk3288_hdmi *regs, uint 
mpixelclock)
hdmi_phy_enable_tmds(regs, 0);
hdmi_phy_enable_power(regs, 0);
 
-   /* enable csc */
ret = hdmi_phy_configure(regs, mpixelclock);
if (ret) {
debug("hdmi phy config failure %d\n", ret);
@@ -837,7 +799,6 @@ static int rk_hdmi_enable(struct udevice *dev, int 
panel_bpp,
hdmi_audio_set_samplerate(regs, edid->pixelclock.typ);
 
hdmi_video_packetize(regs);
-   hdmi_video_csc(regs);
hdmi_video_sample(regs);
 
hdmi_clear_overflow(regs);
-- 
2.12.0

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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Tom Rini]

On Wed, Mar 08, 2017 at 05:32:45PM -0500, Trevor Woerner wrote:
> On Wed 2017-03-08 @ 04:33:21 PM, Tom Rini wrote:
> > Now, you've boot tested this, right? :)
> 
> Yes.
> 
> > Also, what board(s) show this problem exactly?
> 
> I'm working with the firefly-rk3288 board.

OK.  Can you please turn off CONFIG_ROCKCHIP_SPL_BACK_TO_BROM and see if
we can link again without -N?  No, this won't boot, but that's not what
I'm after just yet, thanks!

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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Trevor Woerner]

On Wed 2017-03-08 @ 05:32:45 PM, Trevor Woerner wrote:
> I have a patch for the meta-rockchip layer

https://lists.yoctoproject.org/pipermail/yocto/2017-March/034985.html
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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Trevor Woerner]

On Wed 2017-03-08 @ 04:33:21 PM, Tom Rini wrote:
> Now, you've boot tested this, right? :)

Yes.

> Also, what board(s) show this problem exactly?

I'm working with the firefly-rk3288 board.

If it would be preferable to you, I have a patch for the meta-rockchip layer
that solves the problem for me. If you're leery about adding this for
everyone, I could just carry this patch locally and not affect u-boot upstream
at all.

I'm unfamiliar with the u-boot sources, is there a way to add a build flag
only for a specific board?
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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Tom Rini]

On Wed, Mar 08, 2017 at 02:53:04PM -0500, Trevor Woerner wrote:
> On Wed 2017-03-08 @ 01:41:24 PM, Tom Rini wrote:
> > What does 2.27 without -N look like compared with
> > 2.28 with -N ?
> 
> I'm no expert in reading map files, but it looks like the size of .rodata is a
> little bit smaller with 2.28 which pulls everything after it up a little bit
> address-wise (?)

Yeah, that's what it looks like to me as well.  Now, you've boot tested
this, right? :)  Also, what board(s) show this problem exactly?

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Re: [U-Boot] [PATCH 02/31] spl: fit: Break out some functions into a common file

[Franklin S Cooper Jr]

+Andre

On 03/08/2017 03:01 PM, Simon Glass wrote:
> Hi Franklin,
> 
> On 2 March 2017 at 12:04, Franklin S Cooper Jr  wrote:
>> Some of the functions within spl_fit will be used for non spl purposes.
>> Instead of duplicating functions simply break the functions to be reused
>> into its own file.
>>
>> Signed-off-by: Franklin S Cooper Jr 
>> Reviewed-by: Tom Rini 
>> ---
>>  common/Makefile  |  1 +
>>  common/common_fit.c  | 86 
>> 
>>  common/spl/spl_fit.c | 76 +-
>>  include/image.h  |  8 +
>>  4 files changed, 96 insertions(+), 75 deletions(-)
>>  create mode 100644 common/common_fit.c
> 
> This seems to conflict with Andre's series. What is the plan here?

I'll have to look at it closely again but from what I remember Andre's
series was adding additional functionality to functions within spl_fit
while I only care about making those same functions accessible beyond
SPL. So it depends on whose code is merged first but I don't think it is
a big problem to manage.

> 
> - Simon
> 
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Re: [U-Boot] Complete verified uboot example

[Simon Glass]

Hi Ron,

On 28 February 2017 at 17:06, Ron Brash  wrote:
> Hello,
>
> Here is a list of things I have tried:  The raw zImage (which is compressed
> with XZ), various addresses from indeed load address 0x2300, entry
> at 0x23008000
> (and the same), I've tried setting the FTD address since it sets itself
> neatly at 0x22f and change, which will probably get itself clobbered.
>
> I've tried playing with the "magic" variables of ftdaddr, loadaddr, and
> verify.  No luck other than a few loops, hangs and
> illegitimate instructions being executed.
>
> Something is missing from my system, documentation or more and it appears
> to be uboot and/or the fit format + FDT/DTBs.
>
> Is there a magic formula?  Before FIT I could just copy my kernel to
> 0x22... and my DTB to another address that wouldn't be clobbered, use bootm
> and everything would work given I set it to a uImage.
>
> Question, does the FDT need a load address specified as well?  Why does the
> documentation use all 0's?  Usually, all zeros is either an example, or
> will be inherit some address from a variable? (perhaps this is not
> obviously documented).

You should be able to set up load addresses for each image in the FIT,
and use the same addresses as you used to use before FIT. The FIT
itself can then be loaded to some other address. That's probably the
safest approach.

What board are you using? It's a shame to have to break new ground here.`

[...]

Regards,
Simon
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Re: [U-Boot] [RFC PATCH 1/3] dm: core: Add pre-OS remove flag to device_remove()

[Simon Glass]

Hi Stefan,

On 2 March 2017 at 23:24, Stefan Roese  wrote:
> Hi Simon,
>
> On 03.03.2017 05:53, Simon Glass wrote:
>> On 1 March 2017 at 03:23, Stefan Roese  wrote:
>>> This patch adds the pre_os_remove boolean flag to device_remove() and
>>> changes all calls to this function to provide the default value of
>>> "false". This is in preparation for the driver specific pre-OS remove
>>> support.
>>>
>>> Signed-off-by: Stefan Roese 
>>> Cc: Simon Glass 
>>> ---
>>>  arch/x86/cpu/queensbay/tnc.c   |  4 ++--
>>>  cmd/cros_ec.c  |  2 +-
>>>  cmd/sf.c   |  2 +-
>>>  drivers/block/blk-uclass.c |  2 +-
>>>  drivers/block/sandbox.c|  2 +-
>>>  drivers/core/device-remove.c   |  9 +
>>>  drivers/core/device.c  |  2 +-
>>>  drivers/core/root.c|  2 +-
>>>  drivers/core/uclass.c  |  2 +-
>>>  drivers/mmc/mmc-uclass.c   |  2 +-
>>>  drivers/mtd/spi/sandbox.c  |  2 +-
>>>  drivers/mtd/spi/sf-uclass.c|  2 +-
>>>  drivers/spi/spi-uclass.c   |  4 ++--
>>>  drivers/usb/emul/sandbox_hub.c |  2 +-
>>>  drivers/usb/host/usb-uclass.c  |  4 ++--
>>>  include/dm/device-internal.h   |  5 +++--
>>>  include/dm/device.h|  3 +++
>>>  test/dm/bus.c  |  8 
>>>  test/dm/core.c | 16 
>>>  test/dm/eth.c  |  2 +-
>>>  test/dm/spi.c  |  2 +-
>>>  21 files changed, 42 insertions(+), 37 deletions(-)
>>
>> I think adding a parameter to device_remove() makes sense, but how
>> about using flags instead? The true/false meaning is not clear here
>> and your comment in device.h doesn't really help.
>
> So you are suggesting something like this:
>
> int device_remove(struct udevice *dev, uin32_t remove_flags);

Yes, or really 'uint remove_flags'

>
> ?
>
>> Also I think it is better to name it after the required function
>> rather than state related to the caller. IOW instead of 'pre-os' use
>> something like 'active_dma_only' or as a flag ONLY_REMOVE_ACTIVE_DMA.
>>
>> Do you think the presence of DMA should be a device flag?
>
> The usage of flags instead of this pre-os parameter could make
> sense to me, as its much more flexible. But I'm not so sure about
> the flag (re-)naming to something specific like DMA. As there
> could be multiple reasons other than DMA related for this last-stage
> driver cleanup / configuration before the OS is started. E.g.
> if a driver needs to stop an internal timer before the OS is started,
> it would need to "abuse" this DMA flag to get called at the last
> pre-OS stage. Or is your thinking that in such cases (e.g. stopping
> of timer) a new flag should get introduced and added to this
> "remove_flags" parameter in bootm?

Yes, so that it is explicit. Another approach would be:

enum {
  DM_REMOVE_ACTIVE_ALL   = 1 << 0, /* Remove all devices */
  DM_REMOVE_ACTIVE_DMA  = 1 << 1, /* Remove only devices with active DMA */
  /* Add more use cases here */
};

Then, DM_REMOVE_ACTIVE_ALL means everything will be removed, and if
that flag is not set, the other flags can be used.

I am assuming that there actually will be other cases - your email
suggests that could be true.

Regards,
Simon
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Re: [U-Boot] [PATCH 17/17] sunxi: use SPL header DT name for FIT board matching

[Simon Glass]

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> Now that we can store a DT name in the SPL header, use this string (if
> available) when finding the right DT blob to load for U-Boot proper.
> This allows a generic U-Boot (proper) image to be combined with a bunch
> of supported DTs, with just the SPL (possibly only that string) to be
> different.
> Eventually this string can be written after the build process by some
> firmware update tool.

Or perhaps placed in the device tree attached to SPL, if there is one.

>
> Signed-off-by: Andre Przywara 
> ---
>  board/sunxi/board.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v1] gpt: Fix uuid string format

[Simon Glass]

Hi Andy,

On 3 March 2017 at 08:18, Andy Shevchenko  wrote:
> On Fri, Mar 3, 2017 at 6:52 AM, Simon Glass  wrote:
>> Hi Andy,
>>
>> On 27 February 2017 at 07:11, Andy Shevchenko
>>  wrote:
>>> From: Vincent Tinelli 
>>>
>>> Change GPT UUID string format from UUID to GUID per specification.
>>>
>>> Signed-off-by: Vincent Tinelli 
>>> ---
>>>  cmd/gpt.c   | 2 +-
>>>  disk/part_efi.c | 2 +-
>>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> Reviewed-by: Simon Glass 
>>
>> How about also a patch to add comments to that enum in uuid.h?
>
> I hope it's not a condition for your tag? Otherwise we might do this
> later at some point.

No, it's a suggestion. I normally use something 'but please ...' if I
think something needs to be done.

However it does seem confusing, as this bug suggests.

Regards,
Simon
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Re: [U-Boot] [PATCH 09/17] sunxi: A64: move SPL stack to end of SRAM A2

[Simon Glass]

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> The SPL stack is usually located at the end of SRAM A1, where it grows
> towards the end of the SPL.
> For the really big AArch64 binaries the stack overwrites code pretty
> soon, so move the SPL stack to the end of SRAM A2, which is unused at this
> time.
>
> Signed-off-by: Andre Przywara 
> ---
>  include/configs/sunxi-common.h | 5 +
>  1 file changed, 5 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] Complete verified uboot example

[Simon Glass]

Hi Ron,

On 21 February 2017 at 11:08, Ron Brash  wrote:
> Hello all,
>
> I am adding verified kernel support on a board we are using and I am
> struggling to fully understand all of the concepts and steps required to
> pull everything together (on ARM, using ZImages and booting with a working
> DTB on 4.4.3x).  I also looked at the test script inside of examples, but
> it left me with more questions than understanding.
>
> Please correct me where appropriate in my understanding, but if I am
> confused, likely others are too and I hope this helps everyone involved
> overall.

See also the beaglebone_vboot.txt file which has an end-to-end example
for that board. That is a much better example than the test.

>
> Steps:
> ---
>
> First, u-boot needs to have the appropriate features enabled and to be
> built using them.  At a minimum, I suspect:
>
> CONFIG_RSA=y
> CONFIG_FIT=y
> CONFIG_FIT_SIGNATURE=y
> CONFIG_OF_CONTROL=y

Yes.

>
> Next, we need to derive the appropriate cryptographic primitives/keys.
>
> #Generate a private signing key (RSA2048):
> openssl genrsa -F4 -out \
> "${key_dir}"/"${key_name}".key 2048
>
> # Generate a public key:
> openssl req -batch -new -x509 \
> -key "${key_dir}"/"${key_name}".key \
> -out "${key_dir}"/"${key_name}".crt
>
> Then we derive the ITS or image source file - a file that hints/describes
> the elements that will be verified and/or inside of the FIT image?  Lets
> call this $FIT_ITS
>
> / dts - v1 /;
> / {
> description = "Configuration to load a Xen Kernel";
> #address-cells = <1>;
> images {
> linux_kernel @ 1 {
> description = "Linux zImage";
> data = /incbin / ("pathToImage/zImage");
> type = "kernel";
> arch = "arm";
> os = "linux";
> compression = "none";
> load = <0xaf60 >;
> entry = <0xaf60 >;
> hash @ 1 {
> algo = "sha1";
> };
> };
> fdt @ 1 {
> description = "FDT blob";
> data = /incbin / ("PathToDTBUsedByBootingKernel/ex.dtb");
> type = "flat_dt";
> arch = "arm";
> compression = "none";
> load = <0xaec0 >;
> hash @ 1 {
> algo = "sha1";
> };
> };
> };
> configurations {
> default = "config@1";
> config @ 1 {
> description = "Plain Linux";
> kernel = "linux_kernel@1";
> fdt = "fdt@1";
> loadables = "linux_kernel@1";

You need a signature@1 node in here, otherwise mkimage will not sign anything.

> };
> };
> };
>
> Question: Does a signature section go into this as well? underneath the
> hash node for each value?
>
> signature@1 {
>  algo = "sha1,rsa2048";
>  value = <...kernel signature 1...>
>  };

That goes in the config@1 node, as above. See sign-configs.txt for an example.

>
> Then using the device-tree-compiler (dtc), I create a DTB for u-boot.  This
> is the control FDT and this defines what keys are used etc..
>
> #Assemble control FDT for U-Boot with space for public key:
> $DTC -p 0x1000 u-boot.dts -O dtb -o u-boot.dtb

Well if you are using CONFIG_OF_CONTROL, U-Boot will create this file
automatically. Also mkimage will add space if needed automatically. So
I don't think you need this step.

>
> Question: What is required inside of the u-boot.dts for u-boot?  Is it
> simply the same .dts used by the booting kernel, but with a section
> proclaiming the keys?

You don't even need that. It will create it for you.

>
> Question:  Where will the compiled u-boot.dtb eventually go?  Is this put
> into a FIT image, or flashed onto the board alongside the u-boot bootloader
> itself?

It needs to be protected from being written. Normally it is added to
the end of U-Boot:

cat u-boot-nodtb.bin u-boot.dtb >u-boot.bin

>
> Next, given that the above steps are completed, I need to create a FIT
> image with space for the signature.
>
> # Generate fitImage with space for signature:
> $MKIMG -D "-I dts -O dtb -p 2000" \
> -f f$FIT_ITS $FIT_IMG

Again, mkimage will add space if needed.

>
> Question: Is the FIT_IMAGE the actual zimage or is it an output image that
> contains all of the values contained within the ITS?

The latter.

>
> Next this FIT_IMAGE (assuming that this is the final FIT image that
> contains the FDT and zImage) needs to be signed and the public key added to
> it; given that that the key information is in the uboot.
>
> # Sign fitImage and add public key into u-boot.dtb:
> $MKIMG -D "-I dts -O dtb -p 2000" -F \
> -k "${key dir}" -K u-boot.dtb -r $FIT_IMG

Yes.

>
> Then, we sign the subsequent fitImage again - correct?
>
> # Signing subsequent fitImage:
> $MKIMG -D "-I dts -O dtb -p 2000" \
> -k "${key dir}" -f $FIT_ITS -r $FIT_IMG

No, that step isn't needed.

>
> Now that all of the above is done - we need to:
> 1. Write our uboot to the flash
> 2. Write our FIT_IMAGE to flash
>
> Question: Do we write anything else to persistent storage? The ITS? etc..

No.

>
> Question: Do we just boot using anything else or just bootm
> 0xLocationOfTheFitImageInRAM

Just bootm.

>
> Greatly appreciate any assistance to all of these questions and I'm sure
> 

Re: [U-Boot] [PATCH 11/17] sunxi: SPL: add FIT config selector for Pine64 boards

[Simon Glass]

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> For a board or platform to support FIT loading in the SPL, it has to
> provide a board_fit_config_name_match() routine, which helps to select
> one of possibly multiple DTBs contained in a FIT image.
> Provide a simple function which chooses the DT name U-Boot was
> configured with.
> If the DT name is one of the two Pine64 versions, determine the exact
> model by checking the DRAM size.
>
> Signed-off-by: Andre Przywara 
> ---
>  board/sunxi/board.c | 23 +++
>  1 file changed, 23 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 13/17] sunxi: A64: Pine64: introduce FIT generator script

[Simon Glass]

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> Now that the Makefile can call a generator script to build a more
> advanced FIT image, let's use this feature to address the needs of
> Allwinner A64 boards.
> The (DTB stripped) U-Boot binary and the ATF are static, but we allow
> an arbitrary number of supported device trees to be passed.
> The script enters both a DT entry in the /images node and the respective
> subnode in /configurations to support all listed DTBs.
>
> This requires to copy the ARM Trusted Firmware build (bl31.bin) into
> the U-Boot source directory (or to create a symlink to it).
>
> Signed-off-by: Andre Przywara 
> ---
>  board/sunxi/mksunxi_fit_atf.sh | 73 
> ++
>  1 file changed, 73 insertions(+)
>  create mode 100755 board/sunxi/mksunxi_fit_atf.sh

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v3 7/7] rockchip: rk3288: add defconfig for evb-rk3328

[Simon Glass]

Hi Kever,

On 23 February 2017 at 17:46, Kever Yang  wrote:
> Hi Simon,
>
> There is a typo on the subject of this patch, it should be rk3328
> instead
> of rk3288 :(
> Sorry for that, are you able to fix it in your tree?

OK, done.

Regards,
Simon
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Re: [U-Boot] [PATCH 12/17] Makefile: add rules to generate SPL FIT images

[Simon Glass]

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> Some platforms require more complex U-Boot images than we can easily
> generate via the mkimage command line, for instance to load additional
> image files.
> Introduce a CONFIG_SPL_FIT_SOURCE and CONFIG_SPL_FIT_GENERATOR symbol,
> which can either hold an .its source file describing the image layout,
> or, in the second case, a generator tool (script) to create such
> a source file. This script gets passed the list of device tree files
> from the CONFIG_OF_LIST variable.
> A platform or board can define either of those in their defconfig file
> to allow an easy building of such an image.
>
> Signed-off-by: Andre Przywara 
> ---
>  Kconfig  | 17 +
>  Makefile | 20 
>  2 files changed, 37 insertions(+)

Reviewed-by: Simon Glass 

But please can you mention this in the documentation at doc/uImage.FIT?
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Re: [U-Boot] [PATCH 15/17] sunxi: OrangePi-PC2: defconfig: enable SPL FIT support

[Simon Glass]

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> Enable the SPL FIT support and the FIT generator script for the
> OrangePi PC2 board, as it also need to load an ATF binary.
>
> Signed-off-by: Andre Przywara 
> ---
>  configs/orangepi_pc2_defconfig | 6 ++
>  1 file changed, 6 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] Complete verified uboot example

[Simon Glass]

Hi Ron,

On 27 February 2017 at 14:49, Ron Brash  wrote:
> Looks like far more progress:
>
> #> setenv my_bootcount 0; bootm 0xD0084000
> Initial value for argc=3
> Final value for argc=3
> ## Current stack ends at 0x23f11db8 *  kernel: cmdline image address =
> 0xd0084000
>Reading image header from dataflash address d0084000 to RAM address
> 2200
>FIT/FDT format image found at 0x2200, size 0x0016c0b1
>Reading image remaining data from dataflash address d0084040 to RAM
> address 2240
> ## Loading kernel from FIT Image at 2200 ...
> No configuration specified, trying default...
> Found default configuration: 'config@1'
>Using 'config@1' configuration
>Trying 'linux_kernel@1' kernel subimage
>  Description:  Linux zImage
>  Type: Kernel Image
>  Compression:  uncompressed
>  Data Start:   0x22dc
>  Data Size:1465544 Bytes = 1.4 MiB
>  Architecture: ARM
>  OS:   Linux
>  Load Address: 0x2200
>  Entry Point:  0x22008000
>  Hash node:'hash@1'
>  Hash algo:sha256
>  Hash value:
> 5dcf9a4328bca6fe5c3405e03b9a58402dce36f3a4f0c757e52091b050d2bcb2
>  Hash len: 32
>Verifying Hash Integrity ... sha256+ OK
>kernel data at 0x22dc, len = 0x00165cc8 (1465544)
> *  ramdisk: using config 'config@1' from image at 0x2200
> *  ramdisk: no 'ramdisk' in config
> *  fdt: using config 'config@1' from image at 0x2200
> ## Checking for 'FDT'/'FDT Image' at 2200
> ## Loading fdt from FIT Image at 2200 ...
>Using 'config@1' configuration
>Trying 'fdt@1' fdt subimage
>  Description:  FDT blob
>  Type: Flat Device Tree
>  Compression:  uncompressed
>  Data Start:   0x22165ea4
>  Data Size:21681 Bytes = 21.2 KiB
>  Architecture: ARM
>  Hash node:'hash@1'
>  Hash algo:sha256
>  Hash value:
> c7f32d039871d858dda8d397c3b6a685bc914c78cf70f03d1860f61ecfe9c689
>  Hash len: 32
>Verifying Hash Integrity ... sha256+ OK
>Loading fdt from 0x22165ea4 to 0x2800
>Booting using the fdt blob at 0x2800
>of_flat_tree at 0x2800 size 0x54b1
> Initial value for argc=3
> Final value for argc=3
>Loading Kernel Image ... OK
> CACHE: Misaligned operation at range [2200, 22165cc8]
>kernel loaded at 0x2200, end = 0x22165cc8
> images.os.start = 0x2200, images.os.end = 0x2216c0f1
> images.os.load = 0x2200, load_end = 0x22165cc8
> ERROR: new format image overwritten - must RESET the board to recover
> resetting ...
>
> This appears to be an addressing issue.  Anyone care to comment?
>
> I'll put up how I got to this point after, but I am curious on how all of
> the addresses are leveraged, is there an order they follow and more?

At this point you are not dealing with a verified boot problem, IMO.
This is just about getting your board to load things at the right
address.

BTW you appear to be using image verification - I think you should
consider using configuration verification as it is more secure.

[...]

Regards,
Simon
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Re: [U-Boot] [PATCH 02/31] spl: fit: Break out some functions into a common file

[Simon Glass]

Hi Franklin,

On 2 March 2017 at 12:04, Franklin S Cooper Jr  wrote:
> Some of the functions within spl_fit will be used for non spl purposes.
> Instead of duplicating functions simply break the functions to be reused
> into its own file.
>
> Signed-off-by: Franklin S Cooper Jr 
> Reviewed-by: Tom Rini 
> ---
>  common/Makefile  |  1 +
>  common/common_fit.c  | 86 
> 
>  common/spl/spl_fit.c | 76 +-
>  include/image.h  |  8 +
>  4 files changed, 96 insertions(+), 75 deletions(-)
>  create mode 100644 common/common_fit.c

This seems to conflict with Andre's series. What is the plan here?

- Simon
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Re: [U-Boot] [PATCH 02/17] SPL: FIT: refactor FDT loading

[Simon Glass]

Hi Andre,

On 3 March 2017 at 04:09, Andre Przywara  wrote:
> Hi Simon,
>
> On 03/03/17 04:53, Simon Glass wrote:
>> Hi Andre,
>>
>> On 28 February 2017 at 19:25, Andre Przywara  wrote:
>>> Currently the SPL FIT loader uses the spl_fit_select_fdt() function to
>>> find the offset to the right DTB within the FIT image.
>>> For this it iterates over all subnodes of the /configuration node in
>>> the FIT tree and compares all "description" strings therein using a
>>> board specific matching function.
>>> If that finds a match, it uses the string in the "fdt" property of that
>>> subnode to locate the matching subnode in the /images node, which points
>>> to the DTB data.
>>> Now this works very well, but is quite specific to cover this particular
>>> use case. To open up the door for a more generic usage, let's split this
>>> function into:
>>> 1) a function that just returns the node offset for the matching
>>>configuration node (spl_fit_find_config_node())
>>> 2) a function that returns the image data any given property in a given
>>>configuration node points to, additionally using a given index into
>>>a possbile list of strings (spl_fit_select_index())
>>> This allows us to replace the specific function above by asking for the
>>> image the _first string of the "fdt" property_ in the matching
>>> configuration subnode points to.
>>>
>>> This patch introduces no functional changes, it just refactors the code
>>> to allow reusing it later.
>>>
>>> (diff is overly clever here and produces a hard-to-read patch, so I
>>> recommend to throw a look at the result instead).
>>
>> First I want to commend you on your excellent commit messages. For
>> example this one explains the current situation, the change your
>> commit performs and the motivation for that change. With these more
>> complicated / core pieces, it is very valuable and you are an example
>> to us all :-)
>
> Thank you very much, you made my day. That is a welcome departure from
> the usual Linux ML communication style ;-)
>
> And yes, will fix those things you mentioned below, though have to wrap
> my mind about pytest first.
>
>
> Now back into the rough waters of the Linux mailing lists ...

Godspeed - perhaps keep a beer by the computer to use in emergencies :-)

Regards,
Simon
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Re: [U-Boot] [PATCH 16/17] sunxi: Store the device tree name in the SPL header

[Simon Glass]

Hi Andre,

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> From: Siarhei Siamashka 
>
> This patch updates the mksunxiboot tool to optionally add
> the default device tree name string to the SPL header. This
> information can be used by the firmware upgrade tools to
> protect users from harming themselves by trying to upgrade
> to an incompatible bootloader.
>
> The primary use case here is a non-removable bootable media
> (such as NAND, eMMC or SPI flash), which already may have
> a properly working, but a little bit outdated bootloader
> installed. For example, the user may download or build a
> new U-Boot image for "Cubieboard", and then attemept to
> install it on a "Cubieboard2" hardware by mistake as a
> replacement for the already existing bootloader. If this
> happens, the flash programming tool can identify this
> problem and warn the user.
>
> The size of the SPL header is also increased from 64 bytes
> to 96 bytes to provide enough space for the device tree name
> string.
> [Andre: split patch to remove OF_LIST hash feature]
>
> Signed-off-by: Siarhei Siamashka 
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/include/asm/arch-sunxi/spl.h | 19 +++---
>  include/configs/sunxi-common.h|  8 +++---
>  scripts/Makefile.spl  |  3 ++-
>  tools/mksunxiboot.c   | 49 
> ---
>  4 files changed, 67 insertions(+), 12 deletions(-)

Can this code move into mkimage as a new image type? This is what
rockchip does. It feels like this tool should be subsumed. If that
doesn't work, perhaps binman?

- Simon
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Re: [U-Boot] [RFC PATCH 3/3] arm: bootm: Add dm_pre_os_remove() call to announce_and_cleanup()

[Simon Glass]

Hi Stefan,

On 2 March 2017 at 23:35, Stefan Roese  wrote:
> Hi Simon,
>
>
> On 03.03.2017 05:53, Simon Glass wrote:
>>
>> On 1 March 2017 at 03:23, Stefan Roese  wrote:
>>>
>>> This patch adds a call to dm_pre_os_remove() to announce_and_cleanup()
>>> so that drivers that have the flag DM_FLAG_PRE_OS_REMOVE set may do
>>> some last-stage cleanup before the OS is started.
>>>
>>> Signed-off-by: Stefan Roese 
>>> Cc: Simon Glass 
>>> ---
>>>  arch/arm/lib/bootm.c | 8 
>>>  1 file changed, 8 insertions(+)
>>>
>>> diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
>>> index 8125cf023f..84f3415c1e 100644
>>> --- a/arch/arm/lib/bootm.c
>>> +++ b/arch/arm/lib/bootm.c
>>> @@ -91,6 +91,14 @@ static void announce_and_cleanup(int fake)
>>>
>>> board_quiesce_devices();
>>>
>>> +   /*
>>> +* Call remove function of all devices with the pre-OS remove
>>> flag
>>> +* set (DM_FLAG_PRE_OS_REMOVE). This may be useful for last-stage
>>> +* operations, like cancelling of DMA operation or releasing
>>> device
>>> +* internal buffers.
>>> +*/
>>> +   dm_pre_os_remove();
>>
>>
>> In a full DM world we could perhaps have devices which use the DMA
>> uclass, so we can tell which ones need to be removed.
>>
>> How about dm_remove_dma_devices()?
>
>
> I'm not so sure. As we would perhaps need to add other calls for
> further pre-OS removal reasons (e.g. the stop timer example). How
> about calling a function with the removal flags as parameter:
>
> dm_remove_devices_conditional(ONLY_REMOVE_ACTIVE_DMA | ...);
>
> or
>
> dm_remove_devices_flags(ONLY_REMOVE_ACTIVE_DMA | ...);
>
> What do you think?

Seems reasonable - see my previous email for a flag naming idea (i.e.
having an explicit ALL flag to avoid all the flags having to use
negative logic).

>
>>> +
>>> cleanup_before_linux();
>>>  }
>>>
>>> --
>>> 2.12.0
>>>
>>
>> Also (once we have things figured out) this needs some sort of test in
>> test/.
>
>
> I already feared that. ;)
>
> Sure, I'll try to add some test, once the path is clear.
>
> Thanks,
> Stefan

Regards,
Simon
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Re: [U-Boot] [PATCH 10/17] sunxi: SPL: store RAM size in gd

[Simon Glass]

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> The sunxi SPL was holding the detected RAM size in some local variable
> only, so it wasn't accessible for other functions.
> Store the value in gd->ram_size instead, so it can be used later on.
>
> Signed-off-by: Andre Przywara 
> ---
>  board/sunxi/board.c | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 06/17] tools: mksunxiboot: allow larger SPL binaries

[Simon Glass]

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> mksunxiboot limits the size of the resulting SPL binaries to pretty
> conservative values to cover all SoCs and all boot media (NAND).
> It turns out that we have limit checks in place in the build process,
> so mksunxiboot can be relaxed and allow packaging binaries up to the
> actual 32KB the mask boot ROM actually imposes.
> This allows to have a bigger SPL, which is crucial for AArch64 builds.
>
> Signed-off-by: Andre Przywara 
> ---
>  tools/mksunxiboot.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 08/17] armv8: fsl: move ccn504 code into FSL Makefile

[Simon Glass]

Hi Andre,

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> The generic ARMv8 assembly code contains routines for setting up
> a CCN interconnect, though the Freescale SoCs are the only user.
> Link this code only for Freescale targets, this saves some precious
> bytes in the chronically tight SPL.
>
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
>  arch/arm/lib/Makefile  | 1 -
>  2 files changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index c9ab93e..ca09973 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -7,6 +7,7 @@
>  obj-y += cpu.o
>  obj-y += lowlevel.o
>  obj-y += soc.o
> +obj-y += ccn504.o

Don't you need to move the file into the same directory?

>  obj-$(CONFIG_MP) += mp.o
>  obj-$(CONFIG_OF_LIBFDT) += fdt.o
>  obj-$(CONFIG_SPL) += spl.o
> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
> index 71de1ca..60ffb4a 100644
> --- a/arch/arm/lib/Makefile
> +++ b/arch/arm/lib/Makefile
> @@ -43,7 +43,6 @@ obj-y += stack.o
>  ifdef CONFIG_CPU_V7M
>  obj-y  += interrupts_m.o
>  else ifdef CONFIG_ARM64
> -obj-y  += ccn504.o
>  ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
>  obj-y  += gic_64.o
>  endif
> --
> 2.8.2
>

Regards,
Simon
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Re: [U-Boot] [PATCH 07/17] armv8: SPL: only compile GIC code if needed

[Simon Glass]

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> Not every SoC needs to set up the GIC interrupt controller, so link
> think code only when the respective config option is set.
> This shaves off some bytes from the SPL code size.
>
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/lib/Makefile | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 05/17] SPL: FIT: allow loading multiple images

[Simon Glass]

Hi Andre,

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> So far we were not using the FIT image format to its full potential:
> The SPL FIT loader was just loading the first image from the /images
> node plus one of the listed DTBs.
> Now with the refactored loader code it's easy to load an arbitrary
> number of images in addition to the two mentioned above.
> As described in the FIT image source file format description, iterate
> over all images listed at the "loadables" property in the configuration
> node and load every image at its desired location.
> This allows to load any kind of images:
> - firmware images to execute before U-Boot proper (for instance
>   ARM Trusted Firmware (ATF))
> - firmware images for management processors (SCP, arisc, ...)
> - firmware images for devices like WiFi controllers
> - bit files for FPGAs
> - additional configuration data
> - kernels and/or ramdisks
> The actual usage of this feature would be platform and/or board specific.
>
> Signed-off-by: Andre Przywara 
> ---
>  common/spl/spl_fit.c | 32 
>  1 file changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index ad5ba15..5583e09 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -178,10 +178,7 @@ static int spl_load_fit_image(struct spl_load_info 
> *info, ulong sector,
> if (image_info) {
> image_info->load_addr = load_addr;
> image_info->size = length;
> -   if (entry == -1UL)
> -   image_info->entry_point = load_addr;
> -   else
> -   image_info->entry_point = entry;
> +   image_info->entry_point = entry;

Need to update function comment to indicate that it can put -1 in here.

> }
>
> return 0;
> @@ -196,6 +193,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
> struct spl_image_info image_info;
> int node, images;
> int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
> +   int index = 0;
>
> /*
>  * Figure out where the external images start. This is the base for 
> the
> @@ -240,6 +238,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
> if (node < 0) {
> debug("could not find firmware image, trying loadables...\n");
> node = spl_fit_get_image_node(fit, images, "loadables", 0);
> +   /*
> +* If we pick the U-Boot image from "loadables", start at
> +* the second image when later loading additional images.
> +*/
> +   index = 1;
> }
> if (node < 0) {
> debug("%s: Cannot find u-boot image node: %d\n",
> @@ -265,5 +268,26 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
> image_info.load_addr = spl_image->load_addr + spl_image->size;
> spl_load_fit_image(info, sector, fit, base_offset, node, _info);
>
> +   /* Now check if there are more images for us to load */
> +   for (; ; index++) {
> +   node = spl_fit_get_image_node(fit, images, "loadables", 
> index);
> +   if (node < 0)
> +   break;
> +
> +   spl_load_fit_image(info, sector, fit, base_offset, node,
> +  _info);

Error check?

> +
> +   /*
> +* If the "firmware" image did not provide an entry point,
> +* use the first valid entry point from the loadables.
> +*/
> +   if (spl_image->entry_point == -1UL &&
> +   image_info.entry_point != -1UL)
> +   spl_image->entry_point = image_info.entry_point;
> +   }
> +
> +   if (spl_image->entry_point == -1UL || spl_image->entry_point == 0)

Why does 0 mean there is no entry point? I suppose that is safe, but
would anyone use this?

> +   spl_image->entry_point = spl_image->load_addr;
> +
> return 0;
>  }
> --
> 2.8.2
>

Regards,
Simon
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Re: [U-Boot] [PATCH 04/17] SPL: FIT: factor out spl_load_fit_image()

[Simon Glass]

Hi Andre,

On 28 February 2017 at 19:25, Andre Przywara  wrote:
> At the moment we load two images from a FIT image: the actual U-Boot
> image and the DTB. Both times we have very similar code to deal with
> alignment requirement the media we load from imposes upon us.
> Factor out this code into a new function, which we just call twice.
>
> Signed-off-by: Andre Przywara 
> ---
>  common/spl/spl_fit.c | 129 
> +++
>  1 file changed, 57 insertions(+), 72 deletions(-)
>
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index 572a5db..ad5ba15 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -18,7 +18,7 @@ static ulong fdt_getprop_u32(const void *fdt, int node, 
> const char *prop)
>
> cell = fdt_getprop(fdt, node, prop, );
> if (len != sizeof(*cell))
> -   return -1U;
> +   return -1UL;

Looks like an unrelated change but I see you need it below, so OK.

> return fdt32_to_cpu(*cell);
>  }
>
> @@ -139,19 +139,63 @@ static int get_aligned_image_size(struct spl_load_info 
> *info, int data_size,
> return (data_size + info->bl_len - 1) / info->bl_len;
>  }
>
> +static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
> + void *fit, ulong base_offset, int node,
> + struct spl_image_info *image_info)

Please add a full comment to this one.

> +{
> +   ulong offset;
> +   size_t length;
> +   ulong load_addr, load_ptr, entry;
> +   void *src;
> +   ulong overhead;
> +   int nr_sectors;
> +   int align_len = ARCH_DMA_MINALIGN - 1;
> +
> +   offset = fdt_getprop_u32(fit, node, "data-offset") + base_offset;

I think you need to check that offset is not -1 first.

> +   length = fdt_getprop_u32(fit, node, "data-size");
> +   load_addr = fdt_getprop_u32(fit, node, "load");
> +   if (load_addr == -1UL && image_info)
> +   load_addr = image_info->load_addr;
> +   load_ptr = (load_addr + align_len) & ~align_len;
> +   entry = fdt_getprop_u32(fit, node, "entry");
> +
> +   overhead = get_aligned_image_overhead(info, offset);
> +   nr_sectors = get_aligned_image_size(info, length, offset);
> +
> +   if (info->read(info, sector + get_aligned_image_offset(info, offset),
> +  nr_sectors, (void*)load_ptr) != nr_sectors)
> +   return -EIO;
> +   debug("image: dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset,
> + (unsigned long)length);
> +
> +   src = (void *)load_ptr + overhead;
> +#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
> +   board_fit_image_post_process(, );
> +#endif
> +
> +   memcpy((void*)load_addr, src, length);
> +
> +   if (image_info) {
> +   image_info->load_addr = load_addr;
> +   image_info->size = length;
> +   if (entry == -1UL)
> +   image_info->entry_point = load_addr;
> +   else
> +   image_info->entry_point = entry;
> +   }
> +
> +   return 0;
> +}
> +
>  int spl_load_simple_fit(struct spl_image_info *spl_image,
> struct spl_load_info *info, ulong sector, void *fit)
>  {
> int sectors;
> -   ulong size, load;
> +   ulong size;
> unsigned long count;
> +   struct spl_image_info image_info;
> int node, images;
> -   void *load_ptr;
> -   int fdt_offset, fdt_len;
> -   int data_offset, data_size;
> int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
> -   int src_sector;
> -   void *dst, *src;
>
> /*
>  * Figure out where the external images start. This is the base for 
> the
> @@ -203,82 +247,23 @@ int spl_load_simple_fit(struct spl_image_info 
> *spl_image,
> return -1;
> }
>
> -   /* Get its information and set up the spl_image structure */
> -   data_offset = fdt_getprop_u32(fit, node, "data-offset");
> -   data_size = fdt_getprop_u32(fit, node, "data-size");
> -   load = fdt_getprop_u32(fit, node, "load");
> -   debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
> -   spl_image->load_addr = load;
> -   spl_image->entry_point = load;
> +   /* Load the image and set up the spl_image structure */
> +   spl_load_fit_image(info, sector, fit, base_offset, node, spl_image);

Check error return?

> spl_image->os = IH_OS_U_BOOT;
>
> -   /*
> -* Work out where to place the image. We read it so that the first
> -* byte will be at 'load'. This may mean we need to load it starting
> -* before then, since we can only read whole blocks.
> -*/
> -   data_offset += base_offset;
> -   sectors = get_aligned_image_size(info, data_size, data_offset);
> -   load_ptr = (void *)load;
> -   debug("U-Boot size %x, 

Re: [U-Boot] [PATCH v5 01/11] armv8: Add global variable resv_ram

[Simon Glass]

On 6 March 2017 at 10:02, York Sun  wrote:
> Use gd->arch.resv_ram to track reserved memory allocation.
>
> Signed-off-by: York Sun 
>
> ---
>
> Changes in v5:
>   Rename RESV_RAM_TOP to RESV_RAM in Kconfig
>   Revise "help" message and add comment to explain how RESV_RAM is used.
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 ++
>  arch/arm/include/asm/global_data.h|  7 +++
>  cmd/bdinfo.c  |  4 
>  3 files changed, 21 insertions(+)

Reviewed-by: Simon Glass 
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[U-Boot] [PATCH] mmc: sdhci: only flush cache for data command

[Kevin Liu]

No need to flush cache for command without data.

Signed-off-by: Kevin Liu 
---
 drivers/mmc/sdhci.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 93cefd8..c94d58d 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -242,8 +242,10 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
 
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 #ifdef CONFIG_MMC_SDHCI_SDMA
-   trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
-   flush_cache(start_addr, trans_bytes);
+   if (data != 0) {
+   trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
+   flush_cache(start_addr, trans_bytes);
+   }
 #endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
start = get_timer(0);
-- 
1.9.1


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[U-Boot] Initramfs ignored by kernel

[Koeller, Thomas]

Hi,

I am using u-boot 2016.09.01 to load a linux kernel on an embedded ARM (Zynq) 
board.

First, I built my kernel with the initramfs linked to it, setting 
CONFIG_INITRAMFS_SOURCE to my source files. The resulting kernel is then 
packaged as a legacy u-boot image (make uImage). This image can be booted using 
the 'bootm' command, passing only an FDT blob (no intramfs). Everything is fine 
so far.

Next, I modified my kernel configuration to use an initramfs built separately 
(CONFIG_BLK_DEV_INITRD=y, CONFIG_INITRAMFS_SOURCE=""). The initramfs is the 
same as above. I then used the mkimage program to create a FIT image containing 
the kernel (zImage format), initramfs (cpio.gz created using 'gen_init_cpio' 
from the kernel), and an FDT binary blob created by dtc. This is what the 
result looks like:

FIT description: Production Test Kernel/Initramfs/FDT
Created: Wed Mar  8 09:39:47 2017
 Image 0 (kernel@1)
  Description:  ProductionTest Kernel
  Created:  Wed Mar  8 09:39:47 2017
  Type: Kernel Image
  Compression:  uncompressed
  Data Size:1203704 Bytes = 1175.49 kB = 1.15 MB
  Architecture: ARM
  OS:   Linux
  Load Address: 0x8000
  Entry Point:  0x8000
  Hash algo:crc32
  Hash value:   c45cf4b5
 Image 1 (ramdisk@1)
  Description:  ramdisk
  Created:  Wed Mar  8 09:39:47 2017
  Type: RAMDisk Image
  Compression:  uncompressed
  Data Size:2835138 Bytes = 2768.69 kB = 2.70 MB
  Architecture: ARM
  OS:   Linux
  Load Address: 0x
  Entry Point:  0x002b42c2
  Hash algo:crc32
  Hash value:   bf16e40b
 Image 2 (fdt@1)
  Description:  Flattened Device Tree blob
  Created:  Wed Mar  8 09:39:47 2017
  Type: Flat Device Tree
  Compression:  uncompressed
  Data Size:15526 Bytes = 15.16 kB = 0.01 MB
  Architecture: ARM
  Hash algo:crc32
  Hash value:   6122026f
 Default Configuration: 'conf@1'
 Configuration 0 (conf@1)
  Description:  Production Test
  Kernel:   kernel@1
  Init Ramdisk: ramdisk@1
  FDT:  fdt@1

Booting this image via the 'bootm' command seems to work at first:

Devkit> bootm  ${kernel_addr}
## Loading kernel from FIT Image at 0300 ...
   Using 'conf@1' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel@1' kernel subimage
 Description:  ProductionTest Kernel
 Type: Kernel Image
 Compression:  uncompressed
 Data Start:   0x03e0
 Data Size:1203704 Bytes = 1.1 MiB
 Architecture: ARM
 OS:   Linux
 Load Address: 0x8000
 Entry Point:  0x8000
 Hash algo:crc32
 Hash value:   f057a702
   Verifying Hash Integrity ... crc32+ OK
## Loading ramdisk from FIT Image at 0300 ...
   Using 'conf@1' configuration
   Trying 'ramdisk@1' ramdisk subimage
 Description:  ramdisk
 Type: RAMDisk Image
 Compression:  uncompressed
 Data Start:   0x03125fac
 Data Size:2835161 Bytes = 2.7 MiB
 Architecture: ARM
 OS:   Linux
 Load Address: 0x
 Entry Point:  unavailable
 Hash algo:crc32
 Hash value:   2e7965c4
   Verifying Hash Integrity ... crc32+ OK
## Loading fdt from FIT Image at 0300 ...
   Using 'conf@1' configuration
   Trying 'fdt@1' fdt subimage
 Description:  Flattened Device Tree blob
 Type: Flat Device Tree
 Compression:  uncompressed
 Data Start:   0x033da35c
 Data Size:15526 Bytes = 15.2 KiB
 Architecture: ARM
 Hash algo:crc32
 Hash value:   6122026f
   Verifying Hash Integrity ... crc32+ OK
   Booting using the fdt blob at 0x33da35c
   Loading Kernel Image ... OK
   Loading Ramdisk to 1fd4b000, end 12d9 ... OK
   Loading Device Tree to 1fd44000, end 1fd4aca5 ... OK

Starting kernel ...

However, the kernel apparently fails to access the initramfs image:

Failed to execute /init (error -2)
Kernel panic - not syncing: No working init found.  Try passing init= option to 
kernel. See Linux Documentation/init.txt for guidance.

I verified that /init is actually present in the initramfs image and has 
permission 755. Can anybody help with this problem?

Thomas



Thomas Koeller
Senior Software Developer



Basler AG
An der Strusbek 60-62
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Germany

Tel. +49 4102 463 390
Fax +49 4102 463 46 390

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www.baslerweb.com



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[U-Boot] [PATCH] arm: omap-common: Fix typo in CONFIG_OMAP54XX guard

[Matthijs van Duin]

Some initialization was unintentionally being skipped on omap5.

Fixes: f5af0827f276 ("arm: omap-common: Guard some parts of the code with 
CONFIG_OMAP44XX/OMAP54XX")
Signed-off-by: Matthijs van Duin 
---
 arch/arm/mach-omap2/emif-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/emif-common.c 
b/arch/arm/mach-omap2/emif-common.c
index b26984e26c5e..def7fe0f0a85 100644
--- a/arch/arm/mach-omap2/emif-common.c
+++ b/arch/arm/mach-omap2/emif-common.c
@@ -1195,7 +1195,7 @@ static void do_sdram_init(u32 base)
ddr3_init(base, regs);
 #endif
}
-#ifdef CONFIG_OMAP54X
+#ifdef CONFIG_OMAP54XX
if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
set_lpmode_selfrefresh(base);
-- 
2.11.0

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[U-Boot] Errors on NAND chip

[chris warth]

I am running into errors after creating a UBI filesystems on our NAND
device.  Can anyone suggest where I might look for the error?

A summary is included below and complete debug logs can be seen at
https://gist.github.com/263e422eefa1401db68565fa3e4149bd

After reset, the low-level `nand` commands work well.  However if I
format the partition for UBI with `ubi part`, the low-level `nand`
calls start to fail.  Calling `ubi part` again results in tons of ECC
errors.  I've confirmed that this
sequence of commands works without error on a similar board with a
different nand chip.

The Cypress S34MS04G2 nand chip and is identified as a
"AMD/Spansion S34MS04G2" under Linux.  The SOC is an LS1046A which has
an embedded freescale flash controller.

Thank you in advance for any advice.

=> na nd erase.part nand_uboot
Erasing at 0xfe -- 100% complete.
OK

=> nand read 8200 nand_uboot 4
 262144 bytes read: OK

=> ubi part nand_uboot
ubi0: attached mtd1 (name "mtd=0", size 16 MiB)
ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
ubi0: good PEBs: 128, bad PEBs: 0, corrupted PEBs: 0
ubi0: user volume: 0, internal volumes: 1, max. volumes count: 128
ubi0: max/mean erase counter: 1/0, WL threshold: 4096, image sequence number: 0
ubi0: available PEBs: 44, total reserved PEBs: 84, PEBs reserved for
bad PEB handling: 80

=> nand read 8200 nand_uboot 4
NAND read from offset 0 failed -74
 0 bytes read: ERROR
Command failed, result=1

=> ubi part nand_uboot
[...]
ubi0 warning: ubi_io_read: error -74 (ECC error) while reading 2048
bytes from PEB 0:2048, read only 2048 bytes, retry
ubi0 warning: ubi_io_read: error -74 (ECC error) while reading 2048
bytes from PEB 0:2048, read only 2048 bytes, retry
ubi0 warning: ubi_io_read: error -74 (ECC error) while reading 2048
bytes from PEB 0:2048, read only 2048 bytes, retry
ubi0 error: ubi_io_read: error -74 (ECC error) while reading 2048
bytes from PEB 0:2048, read 2048 bytes
[...]
ubi0 error: ubi_read_volume_table: the layout volume was not found
ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22
UBI error: cannot attach mtd1UBI error: cannot initialize UBI, error
-22UBI init error 22
Command failed, result=22
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[U-Boot] Apparent conflict between CONFIG_BLK and CONFIG_API

[fuz]

Good evening,

I am trying to port FreeBSD to the ASUS Tinker Board, a computer based
on the Rockchip 3288 SoC. FreeBSD's boot loader (named loader(8)) needs
CONFIG_API to be enabled, but trying to build an U-Boot from trunk with
both CONFIG_API and CONFIG_BLK (as required for Rockchip SoC's?) leads
to the following build failure:

$ CROSS_COMPILE=arm-none-eabi- gmake tinker-rk3288_defconfig all
...
  CC  api/api_storage.o
api/api_storage.c: In function 'dev_read_stor':
api/api_storage.c:334:9: error: 'struct blk_desc' has no member named 
'block_read'
  if ((dd->block_read) == NULL) {
 ^~
api/api_storage.c:339:11: error: 'struct blk_desc' has no member named 
'block_read'
  return dd->block_read(dd, start, len, buf);
   ^~
api/api_storage.c:340:1: warning: control reaches end of non-void function 
[-Wreturn-type]
 }
 ^
gmake[2]: *** [scripts/Makefile.build:281: api/api_storage.o] Fehler 1
gmake[1]: *** [Makefile:1229: api] Fehler 2
gmake: *** [Makefile:460: __build_one_by_one] Error 2

I applied the following fix, but the product doesn't boot. Perhaps
that's not a property of the fix though:

diff --git a/api/api_storage.c b/api/api_storage.c
index e80818df1c..815ed1128d 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -331,10 +331,14 @@ lbasize_t dev_read_stor(void *cookie, void *buf, 
lbasize_t len, lbastart_t start
if (!dev_stor_is_valid(type, dd))
return 0;
 
+#ifdef CONFIG_BLK
+   return blk_dread(dd, start, len, buf);
+#else
if ((dd->block_read) == NULL) {
debugf("no block_read() for device 0x%08x\n", cookie);
return 0;
}
 
return dd->block_read(dd, start, len, buf);
+#endif /* defined(CONFIG_BLK) */
 }

Yours,
Robert Clausecker

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[U-Boot] [PATCH v5 00/11] Rewrite ARMv8 layerscape MMU

[York Sun]

A recent debug revealed MMU for DDR shouldn't be enabled before
DDR is initialized. Otherwise, a "normal memory" mapping may cause
speculative access which may hang the system if accessing to DDR
is not allowed at time.  For Layerscape platforms, we have early
MMU setup to speed up execution on emulators. The solution is to
update MMU after DDR is ready. The same idea goes to final MMU as
well. Actual DDR size is used to create the mappings. Non-exist
address should be marked as "fault", i.e. invalid to avoid unwanted
speculative access. Break-before-make process is followed when
change is made for MMU.

Aside from the DDR size, reserved memory used for secure RAM and
Management Complex (MC) makes things more complicated. To simplify
it, a new global is added to track the reserved RAM. Secure RAM
is excluded from U-Boot MMU. The reserved RAM is still mapped
under U-Boot since we will need to copy data into it. Reserved
RAM is excluded when device tree is fixed up so OS won't see it.
An SoC level efi_add_known_memory() is implemented to add valid
memory banks. DP-DDR is not added as memory.

Some MC configurations are moved to Kconfig.

Verified on LS2080ARDB with regular Linux boot and distro boot from USB.

Changes in v5:
  Rename RESV_RAM_TOP to RESV_RAM in Kconfig
  Revise "help" message and add comment to explain how RESV_RAM is used.

Changes in v4:
  Revert the change of C bit in v3 patch.

Changes in v3:
  Instead of flushing d-cache, following the break-before-make process
  to change MMU table.
  Add a patch to drop early MMU setup for LS2080A SPL build.

Changes in v2:
  Add change to efi mapping
  Implement SoC level efi_add_known_memory(). DP-DDR is skipped so no
  need to add it as reserved memory later.

York Sun (11):
  armv8: Add global variable resv_ram
  armv8: ls2080a: Move CONFIG_FSL_MC_ENET to Kconfig
  armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to Kconfig
  efi: Add a hook to allow adding memory mapping
  armv8: layerscape: Rewrite memory reservation
  driver: net: fsl-mc: Update calculation of MC RAM
  armv8: layerscape: Update MMU mapping with actual DDR size
  armv8: layerscape: Fix the sequence of changing MMU table
  armv8: ls2080a: Drop early MMU for SPL build
  armv8: mmu: Add a function to change mapping attributes
  armv8: layerscape: Update early MMU for DDR after initialization

 arch/arm/cpu/armv8/cache_v8.c |  72 -
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  26 ++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   | 331 --
 arch/arm/cpu/armv8/fsl-layerscape/spl.c   |   3 -
 arch/arm/include/asm/arch-fsl-layerscape/config.h |   4 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h|  12 +-
 arch/arm/include/asm/arch-fsl-layerscape/mmu.h|   2 +-
 arch/arm/include/asm/armv8/mmu.h  |   5 +
 arch/arm/include/asm/global_data.h|   7 +
 arch/arm/include/asm/system.h |   1 +
 board/freescale/ls1012afrdm/ls1012afrdm.c |  34 +--
 board/freescale/ls1012aqds/ls1012aqds.c   |  34 +--
 board/freescale/ls1012ardb/ls1012ardb.c   |  34 +--
 board/freescale/ls1043aqds/ddr.c  |  29 --
 board/freescale/ls1043aqds/ls1043aqds.c   |   5 +
 board/freescale/ls1043ardb/ddr.c  |  29 --
 board/freescale/ls1043ardb/ls1043ardb.c   |   7 -
 board/freescale/ls1046aqds/ddr.c  |  29 --
 board/freescale/ls1046aqds/ls1046aqds.c   |   5 +
 board/freescale/ls1046ardb/ddr.c  |  29 --
 board/freescale/ls1046ardb/ls1046ardb.c   |   7 -
 board/freescale/ls2080a/ddr.c |  55 
 board/freescale/ls2080a/ls2080a.c |  17 +-
 board/freescale/ls2080aqds/ddr.c  |  55 
 board/freescale/ls2080aqds/ls2080aqds.c   |  17 +-
 board/freescale/ls2080ardb/ddr.c  |  55 
 board/freescale/ls2080ardb/ls2080ardb.c   |  26 +-
 cmd/bdinfo.c  |   4 +
 common/board_f.c  |  32 +--
 drivers/net/fsl-mc/mc.c   |  75 +
 include/configs/ls2080a_common.h  |   2 -
 lib/efi_loader/efi_memory.c   |  14 +-
 scripts/config_whitelist.txt  |   2 -
 33 files changed, 519 insertions(+), 540 deletions(-)

-- 
2.7.4

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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Tom Rini]

On Wed, Mar 08, 2017 at 01:19:12PM -0500, Trevor Woerner wrote:
> On Wed 2017-03-08 @ 12:20:47 PM, Tom Rini wrote:
> > On Wed, Mar 08, 2017 at 11:57:58AM -0500, Trevor Woerner wrote:
> > > On Wed 2017-03-08 @ 10:35:19 AM, Tom Rini wrote:
> > > > perhaps we can do -N --no-omgic (which negates most of what -N does
> > > 
> > > Unfortunately "-N --no-omagic" doesn't succeed either (same problem):
> > > 
> > >   arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
> > > headers, try linking with -N
> > 
> > OK.  Lets dig a little harder.  Do you have an older binutils around as
> > well?  It would be good to compare the objdump between the older version
> > and newer version with -N passed in as well.  Thanks!
> 
> No problem, OpenEmbedded FTW!! ;-)
> (it's quite easy to switch between them and build, using OE)
> 
> Would comparing the map files suffice? If I build u-boot twice (once with
> binutils-2.27 and once with binutils-2.28) and add the "-N" flag to the
> linking for both builds, comparing the map files I get:
> 
>   $ diff -u 2.27-with-N/u-boot.map 2.28-with-N/u-boot.map 
>   --- 2.27-with-N/u-boot.map  2017-03-08 13:05:32.380107036 -0500
>   +++ 2.28-with-N/u-boot.map  2017-03-08 13:07:50.240330617 -0500
>   @@ -7084,6 +7084,7 @@
>
>.data   0x00043678 0x296c
> *(.data*)
>   + .data.rel.ro   0x000436780x0 
> arch/arm/cpu/armv7/start.o
> .data.rk3288_otg_data
>0x00043678   0x2c 
> arch/arm/mach-rockchip/built-in.o
> .data.rk3288_dmc_ops
>   @@ -7946,6 +7947,9 @@
> *(.rel*)
> .rel.got   0x00047cc00x0 
> arch/arm/cpu/armv7/start.o
> .rel.plt   0x00047cc00x0 
> arch/arm/cpu/armv7/start.o
>   + .rel.bss   0x00047cc00x0 
> arch/arm/cpu/armv7/start.o
>   + .rel.data.rel.ro
>   +0x00047cc00x0 
> arch/arm/cpu/armv7/start.o
> .rel.iplt  0x00047cc00x0 
> arch/arm/cpu/armv7/start.o
> .rel.text  0x00047cc0   0x20 
> arch/arm/cpu/armv7/start.o
> .rel.vectors   0x00047ce0   0x38 
> arch/arm/cpu/armv7/start.o
> 
> 
> 
> If this isn't what you're looking for, please suggest what you'd like and I'll
> give it a try.

That's very close :)  What does 2.27 without -N look like compared with
2.28 with -N ?

-- 
Tom


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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Trevor Woerner]

On Wed 2017-03-08 @ 12:20:47 PM, Tom Rini wrote:
> On Wed, Mar 08, 2017 at 11:57:58AM -0500, Trevor Woerner wrote:
> > On Wed 2017-03-08 @ 10:35:19 AM, Tom Rini wrote:
> > > perhaps we can do -N --no-omgic (which negates most of what -N does
> > 
> > Unfortunately "-N --no-omagic" doesn't succeed either (same problem):
> > 
> > arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
> > headers, try linking with -N
> 
> OK.  Lets dig a little harder.  Do you have an older binutils around as
> well?  It would be good to compare the objdump between the older version
> and newer version with -N passed in as well.  Thanks!

No problem, OpenEmbedded FTW!! ;-)
(it's quite easy to switch between them and build, using OE)

Would comparing the map files suffice? If I build u-boot twice (once with
binutils-2.27 and once with binutils-2.28) and add the "-N" flag to the
linking for both builds, comparing the map files I get:

$ diff -u 2.27-with-N/u-boot.map 2.28-with-N/u-boot.map 
--- 2.27-with-N/u-boot.map  2017-03-08 13:05:32.380107036 -0500
+++ 2.28-with-N/u-boot.map  2017-03-08 13:07:50.240330617 -0500
@@ -7084,6 +7084,7 @@
 
 .data   0x00043678 0x296c
  *(.data*)
+ .data.rel.ro   0x000436780x0 
arch/arm/cpu/armv7/start.o
  .data.rk3288_otg_data
 0x00043678   0x2c 
arch/arm/mach-rockchip/built-in.o
  .data.rk3288_dmc_ops
@@ -7946,6 +7947,9 @@
  *(.rel*)
  .rel.got   0x00047cc00x0 
arch/arm/cpu/armv7/start.o
  .rel.plt   0x00047cc00x0 
arch/arm/cpu/armv7/start.o
+ .rel.bss   0x00047cc00x0 
arch/arm/cpu/armv7/start.o
+ .rel.data.rel.ro
+0x00047cc00x0 
arch/arm/cpu/armv7/start.o
  .rel.iplt  0x00047cc00x0 
arch/arm/cpu/armv7/start.o
  .rel.text  0x00047cc0   0x20 
arch/arm/cpu/armv7/start.o
  .rel.vectors   0x00047ce0   0x38 
arch/arm/cpu/armv7/start.o



If this isn't what you're looking for, please suggest what you'd like and I'll
give it a try.

Best regards,
Trevor
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Re: [U-Boot] Pull request: u-boot-net.git master

[Tom Rini]

On Tue, Mar 07, 2017 at 02:01:49PM -0600, Joe Hershberger wrote:

> Hi Tom,
> 
> The following changes since commit 3fd2b3aa19b9479b5e785087e4951d3a7bbb87be:
> 
>   net: macb: Fix ETH not found when clock not support (2017-03-01 21:28:39 
> -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-net.git master
> 
> for you to fetch changes up to 2c2ab8d65ff6c95a8af0fdb90cb34a777c28e3a1:
> 
>   net: zynq_gem: Fix masking of supported phydev features (2017-03-07 
> 11:27:33 -0600)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Tom Rini]

On Wed, Mar 08, 2017 at 11:57:58AM -0500, Trevor Woerner wrote:
> On Wed 2017-03-08 @ 10:35:19 AM, Tom Rini wrote:
> > perhaps we can do -N --no-omgic (which negates most of what -N does
> 
> Unfortunately "-N --no-omagic" doesn't succeed either (same problem):
> 
>   arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
> headers, try linking with -N

OK.  Lets dig a little harder.  Do you have an older binutils around as
well?  It would be good to compare the objdump between the older version
and newer version with -N passed in as well.  Thanks!

-- 
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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Trevor Woerner]

On Wed 2017-03-08 @ 10:35:19 AM, Tom Rini wrote:
> perhaps we can do -N --no-omgic (which negates most of what -N does

Unfortunately "-N --no-omagic" doesn't succeed either (same problem):

arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
headers, try linking with -N
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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Peter Robinson]

On Wed, Mar 8, 2017 at 4:43 PM, Trevor Woerner  wrote:
> On Wed 2017-03-08 @ 08:43:33 AM, Peter Robinson wrote:
>> On Wed, Mar 8, 2017 at 8:22 AM, Trevor Woerner  wrote:
>> > On Wed 2017-03-08 @ 02:39:00 AM, Trevor Woerner wrote:
>> >> It appears as though linking u-boot with binutils-2.28 fails:
>> >>
>> >>   arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
>> >> headers, try linking with -N
>> >
>> > ...and as it turns out linking with -N succeeds! Who knew? The help message
>> > was actually helpful! :-D
>>
>> I'm glad this wasn't just me seeing this. I have seen breakage with
>> this too but hadn't had time to investigate this further than just
>> realising it was the new binutils.
>
> Out of curiosity, which arch are you seeing this on? I'm seeing it when
> building for arm so am "fixing" it by poking at arch/arm/config.mk.
>
> I'm guessing you're not also coincidently building u-boot from rockchip's
> repository?

Yes, rockchip devices on ARMv7.
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[U-Boot] [PATCH v2] board: ns2: Add support for Broadcom Northstar 2

[Jon Mason]

Add support for the Broadcom Northstar2 SoC and SVK (bcm958712k).  The
BCM5871X is a series of quad-core 64-bit 2GHz ARMv8 Cortex-A57
processors targeting a broad range of networking applications.

Signed-off-by: Jon Mason 
---
 arch/arm/Kconfig  |  9 ++
 board/broadcom/bcm958712k/MAINTAINERS |  6 
 board/broadcom/bcmns2/Kconfig | 15 +
 board/broadcom/bcmns2/Makefile|  7 +
 board/broadcom/bcmns2/northstar2.c| 58 +++
 configs/bcm958712k_defconfig  | 10 ++
 include/configs/bcm_northstar2.h  | 55 +
 7 files changed, 160 insertions(+)
 create mode 100644 board/broadcom/bcm958712k/MAINTAINERS
 create mode 100644 board/broadcom/bcmns2/Kconfig
 create mode 100644 board/broadcom/bcmns2/Makefile
 create mode 100644 board/broadcom/bcmns2/northstar2.c
 create mode 100644 configs/bcm958712k_defconfig
 create mode 100644 include/configs/bcm_northstar2.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e84b74e..db6aa88 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -471,6 +471,14 @@ config TARGET_BCMNSP
bool "Support bcmnsp"
select CPU_V7
 
+config TARGET_BCMNS2
+   bool "Support Broadcom Northstar2"
+   select ARM64
+   help
+ Support for Broadcom Northstar 2 SoCs.  NS2 is a quad-core 64-bit
+ ARMv8 Cortex-A57 processors targeting a broad range of networking
+ applications
+
 config ARCH_EXYNOS
bool "Samsung EXYNOS"
select DM
@@ -1091,6 +1099,7 @@ source "board/broadcom/bcm23550_w1d/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
 source "board/broadcom/bcmnsp/Kconfig"
+source "board/broadcom/bcmns2/Kconfig"
 source "board/cavium/thunderx/Kconfig"
 source "board/cirrus/edb93xx/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
diff --git a/board/broadcom/bcm958712k/MAINTAINERS 
b/board/broadcom/bcm958712k/MAINTAINERS
new file mode 100644
index 000..024fb14
--- /dev/null
+++ b/board/broadcom/bcm958712k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958712K BOARD
+M: Jon Mason 
+S: Maintained
+F: board/broadcom/bcmns2/
+F: include/configs/bcm_northstar2.h
+F: configs/bcm958712k_defconfig
diff --git a/board/broadcom/bcmns2/Kconfig b/board/broadcom/bcmns2/Kconfig
new file mode 100644
index 000..3ac6724
--- /dev/null
+++ b/board/broadcom/bcmns2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCMNS2
+
+config SYS_BOARD
+   default "bcmns2"
+
+config SYS_VENDOR
+   default "broadcom"
+
+config SYS_SOC
+   default "ns2"
+
+config SYS_CONFIG_NAME
+   default "bcm_northstar2"
+
+endif
diff --git a/board/broadcom/bcmns2/Makefile b/board/broadcom/bcmns2/Makefile
new file mode 100644
index 000..f6ddd80
--- /dev/null
+++ b/board/broadcom/bcmns2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Broadcom Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := northstar2.o
diff --git a/board/broadcom/bcmns2/northstar2.c 
b/board/broadcom/bcmns2/northstar2.c
new file mode 100644
index 000..b226c3c
--- /dev/null
+++ b/board/broadcom/bcmns2/northstar2.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2016 Broadcom Ltd.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+
+static struct mm_region ns2_mem_map[] = {
+   {
+   .virt = 0x0UL,
+   .phys = 0x0UL,
+   .size = 0x8000UL,
+   .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+   }, {
+   .virt = 0x8000UL,
+   .phys = 0x8000UL,
+   .size = 0xff8000UL,
+   .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+   }, {
+   /* List terminator */
+   0,
+   }
+};
+
+struct mm_region *mem_map = ns2_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+   return 0;
+}
+
+int dram_init(void)
+{
+   gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
+   PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
+   return 0;
+}
+
+void dram_init_banksize(void)
+{
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+   gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
+   gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+void reset_cpu(ulong addr)
+{
+   psci_system_reset();
+}
diff --git a/configs/bcm958712k_defconfig b/configs/bcm958712k_defconfig
new file mode 100644
index 000..96e4bce
--- /dev/null
+++ b/configs/bcm958712k_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BCMNS2=y
+CONFIG_IDENT_STRING=" Broadcom Northstar 2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_CPUINFO is not set

Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Trevor Woerner]

On Wed 2017-03-08 @ 08:43:33 AM, Peter Robinson wrote:
> On Wed, Mar 8, 2017 at 8:22 AM, Trevor Woerner  wrote:
> > On Wed 2017-03-08 @ 02:39:00 AM, Trevor Woerner wrote:
> >> It appears as though linking u-boot with binutils-2.28 fails:
> >>
> >>   arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
> >> headers, try linking with -N
> >
> > ...and as it turns out linking with -N succeeds! Who knew? The help message
> > was actually helpful! :-D
> 
> I'm glad this wasn't just me seeing this. I have seen breakage with
> this too but hadn't had time to investigate this further than just
> realising it was the new binutils.

Out of curiosity, which arch are you seeing this on? I'm seeing it when
building for arm so am "fixing" it by poking at arch/arm/config.mk.

I'm guessing you're not also coincidently building u-boot from rockchip's
repository?
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Re: [U-Boot] [PATCH v2] arm64: booti: allow to place kernel image anywhere in physical memory

[Mark Rutland]

On Wed, Mar 08, 2017 at 11:35:12AM +0900, Masahiro Yamada wrote:
> At first, the ARM64 Linux booting requirement recommended that the
> kernel image be placed text_offset bytes from 2MB aligned base near
> the start of usable system RAM because memory below that base address
> was unusable at that time.
> 
> This requirement was relaxed by Linux commit a7f8de168ace ("arm64:
> allow kernel Image to be loaded anywhere in physical memory").
> Since then, the bit 3 of the flags field indicates the tolerance
> of the kernel physical placement.  If this bit is set, the 2MB
> aligned base may be anywhere in physical memory.  For details, see
> Documentation/arm64/booting.txt of Linux.
> 
> The booti command should be also relaxed.  If the bit 3 is set,
> images->ep is respected, and the image is placed at the nearest
> bootable location.  Otherwise, it is relocated to the start of the
> system RAM to keep the original behavior.
> 
> Signed-off-by: Masahiro Yamada 
> ---
> 
> Changes in v2:
>   - Use le64_to_cpu() for correct endian-ness
>   - Check the bit 3
> 
>  cmd/booti.c | 18 ++
>  1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/cmd/booti.c b/cmd/booti.c
> index bff87a8..8f3507d 100644
> --- a/cmd/booti.c
> +++ b/cmd/booti.c
> @@ -11,6 +11,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -20,7 +22,7 @@ struct Image_header {
>   uint32_tcode1;  /* Executable code */
>   uint64_ttext_offset;/* Image load offset, LE */
>   uint64_timage_size; /* Effective Image size, LE */
> - uint64_tres1;   /* reserved */
> + uint64_tflags;  /* Kernel flags, LE */
>   uint64_tres2;   /* reserved */
>   uint64_tres3;   /* reserved */
>   uint64_tres4;   /* reserved */
> @@ -51,10 +53,18 @@ static int booti_setup(bootm_headers_t *images)
>   }
>  
>   /*
> -  * If we are not at the correct run-time location, set the new
> -  * correct location and then move the image there.
> +  * If bit 3 of the flags field is set, the 2MB aligned base of the
> +  * kernel image can be anywhere in physical memory, so respect
> +  * images->ep.  Otherwise, relocate the image to the base of RAM
> +  * since memory below it is not accessible via the linear mapping.
>*/
> - dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset);
> + if (le64_to_cpu(ih->flags) & BIT(3))
> + dst = images->ep - le64_to_cpu(ih->text_offset);

I take it this is a pre-correction for the ALIGN() below?

> + else
> + dst = gd->bd->bi_dram[0].start;
> +
> + dst = ALIGN(dst, SZ_2M);
> + dst += le64_to_cpu(ih->text_offset);

There's one last wrinkle to take care of here, if we want to boot a
kernel older than commit a2c1d73b94ed49f5 (i.e. v3.16). Until then, the
text_offset was of unknown endianness.

As mentiond in the Linux documentation, you can detect this based on the
image_size field, e.g.

uint64_t text_offset;

/*
 * Prior to Linux commit a2c1d73b94ed49f5, the text_offset field
 * is of unknown endianness. In these cases, the image_size
 * field is zero, and we can assume a fixed value of 0x8.
 */
if (le64_to_cpu(ih->image_size) == 0)
text_offset = 0x8;
else
text_offset = (le64_to_cpu(ih->text_offset));

... then you can reuse that text_offset value for both cases above.

Otherwise, this looks fine to me.

Thanks,
Mark.
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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Tom Rini]

On Wed, Mar 08, 2017 at 08:18:16AM -0700, Simon Glass wrote:
> +Tom
> 
> Hi Peter,
> 
> On 8 March 2017 at 01:43, Peter Robinson  wrote:
> >
> > On Wed, Mar 8, 2017 at 8:22 AM, Trevor Woerner  wrote:
> > > On Wed 2017-03-08 @ 02:39:00 AM, Trevor Woerner wrote:
> > >> It appears as though linking u-boot with binutils-2.28 fails:
> > >>
> > >>   arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
> > >> headers, try linking with -N
> > >
> > > ...and as it turns out linking with -N succeeds! Who knew? The help 
> > > message
> > > was actually helpful! :-D
> >
> > I'm glad this wasn't just me seeing this. I have seen breakage with
> > this too but hadn't had time to investigate this further than just
> > realising it was the new binutils.
> >
> > Simon is adding -N the proper fix? Might be useful to get a fix into
> > 2017.03 GA as I'm sure in the coming weeks the new binutils will start
> > to land more widely in various distros.
> 
> Well we only have a few more days so if you want that please send a
> patch and we'll see what Tom says. What does the -N flag do?

Looking at the manpage for v2.26.1:
   -N
   --omagic
   Set the text and data sections to be readable and writable.  Also,
   do not page-align the data segment, and disable linking against
   shared libraries.  If the output format supports Unix style magic
   numbers, mark the output as "OMAGIC". Note: Although a writable
   text section is allowed for PE-COFF targets, it does not conform to
   the format specification published by Microsoft.

So, today we don't try and use a writable text section anywhere, perhaps
we can do -N --no-omgic (which negates most of what -N does, but since
we use a custom linker script I think at least the alignment part above
isn't true anyhow) ?

-- 
Tom


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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Simon Glass]

+Tom

Hi Peter,

On 8 March 2017 at 01:43, Peter Robinson  wrote:
>
> On Wed, Mar 8, 2017 at 8:22 AM, Trevor Woerner  wrote:
> > On Wed 2017-03-08 @ 02:39:00 AM, Trevor Woerner wrote:
> >> It appears as though linking u-boot with binutils-2.28 fails:
> >>
> >>   arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
> >> headers, try linking with -N
> >
> > ...and as it turns out linking with -N succeeds! Who knew? The help message
> > was actually helpful! :-D
>
> I'm glad this wasn't just me seeing this. I have seen breakage with
> this too but hadn't had time to investigate this further than just
> realising it was the new binutils.
>
> Simon is adding -N the proper fix? Might be useful to get a fix into
> 2017.03 GA as I'm sure in the coming weeks the new binutils will start
> to land more widely in various distros.

Well we only have a few more days so if you want that please send a
patch and we'll see what Tom says. What does the -N flag do?

Regards,
Simon
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Re: [U-Boot] [PATCH] ARM: keystone: Pass SPI MTD partition table via kernel command line

[Tom Rini]

On Mon, Mar 06, 2017 at 03:16:57PM +0530, Vignesh R wrote:
> Hi,
> 
> On Saturday 04 March 2017 10:39 PM, Tom Rini wrote:
> > On Sat, Mar 04, 2017 at 06:17:30PM +0530, Vignesh R wrote:
> > 
> >> SPI U-Boot image for K2 boards have now exceeded 512K partition
> >> allocated to it and no longer fit the partitions defined in kernel DTS
> >> file. Therefore, pass an updated MTD partition table from U-Boot as
> >> kernel command line arguments to avoid kernel from accidentally
> >> modifying boot loader image that has overflowed to next user partition.
> > 
> > So pretty much everyone is now hitting the problem of "U-Boot" gets huge
> > because we're including N DTB files in the binary in order to pick the
> > correct one.  We really need to start figuring out a real solution here
> > that perhaps involves saying where a copy of the tree lives on hardware,
> > and if not found falling back to a generic functional-enough tree.
> 
> Hmm.. The DTBs need to be stored on boot media(spi flash here) anyways
> and that will lead to altering SPI paritions

Yes.  This, FWIW, is exactly the use case at least some people describe
as the point where the hardware is capable of shipping the device tree.

> >> To do is, introduce a common environment file for declaring SPI
> >> partition so that each individual boards need not repeat the same.
> >> Choose appropriate SPI bus from board config file and pass it as command
> >> line argument to kernel.
> >>
> >> Signed-off-by: Vignesh R 
> > 
> > So, we want the mtdparts to be passed in via the device tree, not the
> > command line directly.  

To be clear, I was saying that fdt_fixup_mtdparts() should be used
(which sadly isn't a common hook today, but that also gets to the next
big problem below) to pass in whatever the partition layout is.  I'm not
a huge fan of dumping tons of data into the cmdline, but that's because
I swear I've seen cases where that ends up being truncated.

> Passing mtdparts via DT creates DT backward compatibility issues and
> does not scale well if partitions size/layout needs to altered in future
> like this case. OTOH, cmdline args provide flexibility of not being
> static and is mostly transparent (as partitions appear in cmdline). Few
> recent discussions on lkml also point to use of non static way of
> passing mtd partition table with cmdline as one of the options:
> https://patchwork.kernel.org/patch/9499119/
> https://patchwork.kernel.org/patch/9515551/

Adding in Tony since it seems like there's some confusion here perhaps.
If you change the partition table of flash on a given device, you've
changed the partition table on a given device, and users that had been
using that previous table are SOL.  Given that we (generally) do not
have an MBR or GPT or anything on the front of flash, it doesn't matter
if we have a "flag day" type change at the device tree file itself or
now the environment has changed and we're passing in a different set of
arguments somewhere.  So if we're changing the partitioning of flash
frequently, it doesn't matter where we're putting the definition of it,
the problem is that we're doing it as it means we haven't put enough
thought into the design to start with.  Thanks!

[snipped out the rest as yes, OK, thanks]

-- 
Tom


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Re: [U-Boot] [PATCH] rockchip: set scan_dev_for_boot_part env for rockchip SoC

[Eddie Cai]

2017-03-08 17:29 GMT+08:00 Sjoerd Simons :

> On Wed, 2017-03-08 at 09:30 +0800, Eddie Cai wrote:
> > Hi Simon
> >
> > 2017-03-06 14:46 GMT+08:00 Eddie Cai :
> >
> > > Hi Simon
> > >
> > > 2017-02-23 11:33 GMT+08:00 Simon Glass :
> > >
> > > > Hi Eddie,
> > > >
> > > > On 22 February 2017 at 07:12, Eddie Cai  > > > m>
> > > > wrote:
> > > > > Hi Simon
> > > > >
>
> > Look like Tom don't like put this changes to default environment. See
> > [0].
> > I think I would have to limit this change on Rockchip SoC because i
> > can
> > only guarantee GPT table exist on Rockchip SoC. What do you think?
> > [0]: https://patchwork.ozlabs.org/patch/735557/
>
> How can you guarantee that it exists on all rockchip deployments? This
> very much depends on the software stack/image people use on rockchip
> boards.
>
We define PARTS_DEFAULT in rockchip-common.h. All rockchip SoC based board
include this file.
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \
"name=reserved1,size=64K,uuid=${uuid_gpt_reserved1};" \
"name=reserved2,size=4M,uuid=${uuid_gpt_reserved2};" \
"name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \
"name=atf,size=4M,uuid=${uuid_gpt_atf};" \
"name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \
"name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \

>
> One of the nice things about the distro bootcmds is that it's a
> flexible generic setup which should just work regardless of how systems
> are installed (as long as some basic conventions are followed). There
> isn't really a requirement for people to use GPT on those system.
>
That is correct. Also that is why i want to limit the change on Rockchip
SoC based board.

>
> Also from a quick look, this seems to want to automatically write GPT
> tables on whatever boot device is scanned, not just the internal media.
> So you're adding a big potential for destroying peoples SD cards here
> :)
>
Yes, I should limit it on the first boot device.

>
> Fwiw I'm also not sure what actual value of writing a GPT table is?
> It's extremely unlikely that this would then allow you to successfully
> boot from the device afterwards.
>
It is PARTS_DEFAULT. For Rockchip SoC, It defined in rockchip-common.h

>
> --
> Sjoerd Simons
> Collabora Ltd.
>
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Re: [U-Boot] [PATCH 2/2] arm: omap3: Bring back ARM errata workaround 725233

[Tom Rini]

On Mon, Mar 06, 2017 at 03:16:53AM +0200, Siarhei Siamashka wrote:

> The workaround for ARM errata 725233 had been lost since
> commit 45bf05854bc94e (armv7: adapt omap3 to the new cache
> maintenance framework). Bring it back in order to avoid
> very difficult to reproduce, but actually encountered in
> the wild CPU deadlocks when running software rendered
> X11 desktop on OMAP3530 hardware.
> 
> This patch adds the new errata define to the whitelist instead
> of introducing a new Kconfig option. It's probably best to
> convert all ARM errata to Kconfig in one go via a separate
> patch.
> 
> Signed-off-by: Siarhei Siamashka 

In concept:
Reviewed-by: Tom Rini 

Do you want to v2 on top of my patch that migrates the current ARM
errata or would you rather I v2 it and apply?  Thanks again!

-- 
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Re: [U-Boot] Simple Malloc Breaks omap3_logic

[Tom Rini]

On Wed, Mar 08, 2017 at 07:11:51AM -0500, Tom Rini wrote:
> On Tue, Mar 07, 2017 at 09:31:02PM -0600, Adam Ford wrote:
> > On Tue, Mar 7, 2017 at 7:04 PM, Tom Rini  wrote:
> > > On Tue, Mar 07, 2017 at 04:23:08PM -0600, Adam Ford wrote:
> > >> On Tue, Mar 7, 2017 at 4:05 PM, Tom Rini  wrote:
> > >> > On Tue, Mar 07, 2017 at 04:02:22PM -0600, Adam Ford wrote:
> > >> >> On Wed, Feb 15, 2017 at 7:23 AM, Adam Ford  wrote:
> > >> >> > On Tue, Feb 14, 2017 at 4:07 PM, Tom Rini  
> > >> >> > wrote:
> > >> >> >> On Tue, Feb 14, 2017 at 03:56:43PM -0600, Adam Ford wrote:
> > >> >> >>> On Feb 14, 2017 3:10 PM, "Tom Rini"  wrote:
> > >> >> >>>
> > >> >> >>> On Tue, Feb 14, 2017 at 03:03:44PM -0600, Adam Ford wrote:
> > >> >> >>>
> > >> >> >>> > Tom,
> > >> >> >>> >
> > >> >> >>> > I noticed there was an update to the omap3_logic_defconfig to 
> > >> >> >>> > use Simple
> > >> >> >>> Malloc
> > >> >> >>> >
> > >> >> >>> > http://git.denx.de/?p=u-boot.git;a=commit;h=0959649dc6d9e6a371617abd3b0363
> > >> >> >>> 0c5d4d5a72
> > >> >> >>> >
> > >> >> >>> >
> > >> >> >>> > I didn't see anything in my inbox indicating the patch, I only 
> > >> >> >>> > noticed
> > >> >> >>> > it because I pulled the latest from the trunk.  Unfortunately, 
> > >> >> >>> > this
> > >> >> >>> > patch breaks the board.
> > >> >> >>> >
> > >> >> >>> > (ie. MLO doesn't load U-Boot)
> > >> >> >>> >
> > >> >> >>> > See Log:
> > >> >> >>> >
> > >> >> >>> > U-Boot SPL 2017.03-rc2-8-g2ebb842-dirty (Feb 14 2017 - 
> > >> >> >>> > 14:54:59)
> > >> >> >>> > Trying to boot from MMC1
> > >> >> >>> > reading args
> > >> >> >>> > spl_load_image_fat_os: error reading image args, err - -1
> > >> >> >>> > reading u-boot.img
> > >> >> >>> > reading u-boot.img
> > >> >> >>> >
> > >> >> >>> > (then it just hangs)
> > >> >> >>> >
> > >> >> >>> > Removing this line from the defconfig returns the board to a 
> > >> >> >>> > functional
> > >> >> >>> state.
> > >> >> >>> >
> > >> >> >>> > Is there an alternative that we can explore to give you what 
> > >> >> >>> > you need?
> > >> >> >>> >
> > >> >> >>> > I am able to build with gcc version 5.4.0 , but I can help you 
> > >> >> >>> > do some
> > >> >> >>> > testing if you need.
> > >> >> >>>
> > >> >> >>> Oh, sorry, I thought I had made sure to copy all of the required 
> > >> >> >>> logic
> > >> >> >>> to have simple malloc work.  I think it's highly likely I forgot 
> > >> >> >>> to make
> > >> >> >>> sure that CONFIG_SYS_MALLOC_F_LEN is also set and that's why it 
> > >> >> >>> all went
> > >> >> >>> south.  Sorry again!
> > >> >> >>>
> > >> >> >>>
> > >> >> >>> That's OK, I just hope I can be included in changes so I can test 
> > >> >> >>> them. I
> > >> >> >>> do appreciate the help in making the code and user experience 
> > >> >> >>> better.
> > >> >> >>>
> > >> >> >>> Can you send me an updated patch so I can test your change?
> > >> >> >>
> > >> >> >> Try this please:
> > >> >> >> diff --git a/configs/omap3_logic_defconfig 
> > >> >> >> b/configs/omap3_logic_defconfig
> > >> >> >> index fe762c0a6b04..9d1304f08e49 100644
> > >> >> >> --- a/configs/omap3_logic_defconfig
> > >> >> >> +++ b/configs/omap3_logic_defconfig
> > >> >> >> @@ -1,5 +1,6 @@
> > >> >> >>  CONFIG_ARM=y
> > >> >> >>  CONFIG_OMAP34XX=y
> > >> >> >> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > >> >> >>  CONFIG_TARGET_OMAP3_LOGIC=y
> > >> >> >>  CONFIG_SYS_EXTRA_OPTIONS="NAND"
> > >> >> >>  CONFIG_SYS_CONSOLE_INFO_QUIET=y
> > >> >> >>
> > >> >> >
> > >> >>
> > >> >> Tom,
> > >> >>
> > >> >> I am not sure what you're trying to fix here, but I looked at other
> > >> >> OMAP3 and AM3X boards, but they don't have either the config options
> > >> >> you are proposing.  Even with both sets of config options, the board
> > >> >> fails to boot.
> > >> >>
> > >> >> I did look at the some of the other TI boards, and they have some SPL
> > >> >> related memory allocation settings.
> > >> >>
> > >> >> If I perform the following, I can get my board to boot, but since I am
> > >> >> not sure what you're trying to fix, I am not sure if it helps your
> > >> >> issue.
> > >> >>
> > >> >>
> > >> >> --- a/configs/omap3_logic_defconfig
> > >> >> +++ b/configs/omap3_logic_defconfig
> > >> >> @@ -5,9 +5,10 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND"
> > >> >>  CONFIG_SYS_CONSOLE_INFO_QUIET=y
> > >> >>  CONFIG_VERSION_VARIABLE=y
> > >> >>  CONFIG_SPL=y
> > >> >> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > >> >>  CONFIG_SPL_MTD_SUPPORT=y
> > >> >>  CONFIG_SPL_OS_BOOT=y
> > >> >> +CONFIG_SPL_STACK_R_ADDR=0x8200
> > >> >> +CONFIG_SPL_STACK_R=y
> > >> >>  CONFIG_HUSH_PARSER=y
> > >> >>  CONFIG_SYS_PROMPT="OMAP Logic # "
> > >> >>  CONFIG_CMD_BOOTZ=y
> > >> >>
> > >> >> Do those options make any sense?  I'd like to get this resolved before
> > >> >> the 2017.03 release comes as of right now, the stuff in the trunk does
> > >> >> not boot my board.
> > >> >
> > >> > Please submit this as a 

Re: [U-Boot] Simple Malloc Breaks omap3_logic

[Tom Rini]

On Tue, Mar 07, 2017 at 09:31:02PM -0600, Adam Ford wrote:
> On Tue, Mar 7, 2017 at 7:04 PM, Tom Rini  wrote:
> > On Tue, Mar 07, 2017 at 04:23:08PM -0600, Adam Ford wrote:
> >> On Tue, Mar 7, 2017 at 4:05 PM, Tom Rini  wrote:
> >> > On Tue, Mar 07, 2017 at 04:02:22PM -0600, Adam Ford wrote:
> >> >> On Wed, Feb 15, 2017 at 7:23 AM, Adam Ford  wrote:
> >> >> > On Tue, Feb 14, 2017 at 4:07 PM, Tom Rini  wrote:
> >> >> >> On Tue, Feb 14, 2017 at 03:56:43PM -0600, Adam Ford wrote:
> >> >> >>> On Feb 14, 2017 3:10 PM, "Tom Rini"  wrote:
> >> >> >>>
> >> >> >>> On Tue, Feb 14, 2017 at 03:03:44PM -0600, Adam Ford wrote:
> >> >> >>>
> >> >> >>> > Tom,
> >> >> >>> >
> >> >> >>> > I noticed there was an update to the omap3_logic_defconfig to use 
> >> >> >>> > Simple
> >> >> >>> Malloc
> >> >> >>> >
> >> >> >>> > http://git.denx.de/?p=u-boot.git;a=commit;h=0959649dc6d9e6a371617abd3b0363
> >> >> >>> 0c5d4d5a72
> >> >> >>> >
> >> >> >>> >
> >> >> >>> > I didn't see anything in my inbox indicating the patch, I only 
> >> >> >>> > noticed
> >> >> >>> > it because I pulled the latest from the trunk.  Unfortunately, 
> >> >> >>> > this
> >> >> >>> > patch breaks the board.
> >> >> >>> >
> >> >> >>> > (ie. MLO doesn't load U-Boot)
> >> >> >>> >
> >> >> >>> > See Log:
> >> >> >>> >
> >> >> >>> > U-Boot SPL 2017.03-rc2-8-g2ebb842-dirty (Feb 14 2017 - 
> >> >> >>> > 14:54:59)
> >> >> >>> > Trying to boot from MMC1
> >> >> >>> > reading args
> >> >> >>> > spl_load_image_fat_os: error reading image args, err - -1
> >> >> >>> > reading u-boot.img
> >> >> >>> > reading u-boot.img
> >> >> >>> >
> >> >> >>> > (then it just hangs)
> >> >> >>> >
> >> >> >>> > Removing this line from the defconfig returns the board to a 
> >> >> >>> > functional
> >> >> >>> state.
> >> >> >>> >
> >> >> >>> > Is there an alternative that we can explore to give you what you 
> >> >> >>> > need?
> >> >> >>> >
> >> >> >>> > I am able to build with gcc version 5.4.0 , but I can help you do 
> >> >> >>> > some
> >> >> >>> > testing if you need.
> >> >> >>>
> >> >> >>> Oh, sorry, I thought I had made sure to copy all of the required 
> >> >> >>> logic
> >> >> >>> to have simple malloc work.  I think it's highly likely I forgot to 
> >> >> >>> make
> >> >> >>> sure that CONFIG_SYS_MALLOC_F_LEN is also set and that's why it all 
> >> >> >>> went
> >> >> >>> south.  Sorry again!
> >> >> >>>
> >> >> >>>
> >> >> >>> That's OK, I just hope I can be included in changes so I can test 
> >> >> >>> them. I
> >> >> >>> do appreciate the help in making the code and user experience 
> >> >> >>> better.
> >> >> >>>
> >> >> >>> Can you send me an updated patch so I can test your change?
> >> >> >>
> >> >> >> Try this please:
> >> >> >> diff --git a/configs/omap3_logic_defconfig 
> >> >> >> b/configs/omap3_logic_defconfig
> >> >> >> index fe762c0a6b04..9d1304f08e49 100644
> >> >> >> --- a/configs/omap3_logic_defconfig
> >> >> >> +++ b/configs/omap3_logic_defconfig
> >> >> >> @@ -1,5 +1,6 @@
> >> >> >>  CONFIG_ARM=y
> >> >> >>  CONFIG_OMAP34XX=y
> >> >> >> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> >> >> >>  CONFIG_TARGET_OMAP3_LOGIC=y
> >> >> >>  CONFIG_SYS_EXTRA_OPTIONS="NAND"
> >> >> >>  CONFIG_SYS_CONSOLE_INFO_QUIET=y
> >> >> >>
> >> >> >
> >> >>
> >> >> Tom,
> >> >>
> >> >> I am not sure what you're trying to fix here, but I looked at other
> >> >> OMAP3 and AM3X boards, but they don't have either the config options
> >> >> you are proposing.  Even with both sets of config options, the board
> >> >> fails to boot.
> >> >>
> >> >> I did look at the some of the other TI boards, and they have some SPL
> >> >> related memory allocation settings.
> >> >>
> >> >> If I perform the following, I can get my board to boot, but since I am
> >> >> not sure what you're trying to fix, I am not sure if it helps your
> >> >> issue.
> >> >>
> >> >>
> >> >> --- a/configs/omap3_logic_defconfig
> >> >> +++ b/configs/omap3_logic_defconfig
> >> >> @@ -5,9 +5,10 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND"
> >> >>  CONFIG_SYS_CONSOLE_INFO_QUIET=y
> >> >>  CONFIG_VERSION_VARIABLE=y
> >> >>  CONFIG_SPL=y
> >> >> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> >> >>  CONFIG_SPL_MTD_SUPPORT=y
> >> >>  CONFIG_SPL_OS_BOOT=y
> >> >> +CONFIG_SPL_STACK_R_ADDR=0x8200
> >> >> +CONFIG_SPL_STACK_R=y
> >> >>  CONFIG_HUSH_PARSER=y
> >> >>  CONFIG_SYS_PROMPT="OMAP Logic # "
> >> >>  CONFIG_CMD_BOOTZ=y
> >> >>
> >> >> Do those options make any sense?  I'd like to get this resolved before
> >> >> the 2017.03 release comes as of right now, the stuff in the trunk does
> >> >> not boot my board.
> >> >
> >> > Please submit this as a proper patch and I'll make sure it still fits in
> >> > size wise everywhere, thanks!
> >> >
> >>
> >> No problem - done.  :-)
> >>
> >> Can you tell me what you're seeing so I can try to replicate it on my
> >> end?  I assume you're seeing stuff overflow memory with a certain
> >> compiler and/or library 

Re: [U-Boot] [PATCHv2 3/5] fsl PPA: add support PPA image loading from NAND and SD

[Jaehoon Chung]

Hi,

On 03/08/2017 03:24 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang 
> 
> Signed-off-by: Hou Zhiqiang 
> ---
> V2:
>  - added flush cache operation after nand read
> 
>  arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 122 
> +++-
>  1 file changed, 121 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> index b68e87d..4df70aa 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> @@ -4,6 +4,7 @@
>   * SPDX-License-Identifier:  GPL-2.0+
>   */
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -21,9 +22,17 @@
>  #include 
>  #endif
>  
> +#ifdef CONFIG_SYS_LS_PPA_FW_IN_NAND
> +#include 
> +#elif defined(CONFIG_SYS_LS_PPA_FW_IN_MMC)
> +#include 
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  int ppa_init(void)
>  {
> - const void *ppa_fit_addr;
> + void *ppa_fit_addr;
>   u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
>   int ret;
>  
> @@ -34,10 +43,116 @@ int ppa_init(void)
>  
>  #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
>   ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
> + debug("%s: PPA image load from XIP\n", __func__);
> +#else /* !CONFIG_SYS_LS_PPA_FW_IN_XIP */
> + size_t fw_length, fdt_header_len = sizeof(struct fdt_header);
> +
> + /* Copy PPA image from MMC/SD/NAND to allocated memory */
> +#ifdef CONFIG_SYS_LS_PPA_FW_IN_MMC
> + struct mmc *mmc;
> + int dev = CONFIG_SYS_MMC_ENV_DEV;
> + struct fdt_header *fitp;
> + u32 cnt;
> + u32 blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
> +
> + debug("%s: PPA image load from eMMC/SD\n", __func__);
> +
> + mmc_initialize(gd->bd);

It should be failed. need to check the return value.

> + mmc = find_mmc_device(dev);
> + if (!mmc) {
> + printf("PPA: MMC cannot find device for PPA firmware\n");
> + return -ENODEV;
> + }
> +
> + mmc_init(mmc);

ditto.

> +
> + fitp = malloc(roundup(fdt_header_len, 512));
> + if (!fitp) {
> + printf("PPA: malloc failed for FIT header(size 0x%zx)\n",
> +roundup(fdt_header_len, 512));
> + return -ENOMEM;
> + }
> +
> + cnt = DIV_ROUND_UP(fdt_header_len, 512);
> + debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
> +   __func__, dev, blk, cnt);
> + ret = mmc->block_dev.block_read(>block_dev, blk, cnt, fitp);
> + if (ret != cnt) {
> + free(fitp);
> + printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
> +CONFIG_SYS_LS_PPA_FW_ADDR);
> + return -EIO;
> + }
> +
> + /* flush cache after read */
> + flush_cache((ulong)fitp, cnt * 512);
> +
> + fw_length = fdt_totalsize(fitp);
> + free(fitp);
> +
> + fw_length = roundup(fw_length, 512);
> + ppa_fit_addr = malloc(fw_length);
> + if (!ppa_fit_addr) {
> + printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
> +fw_length);
> + return -ENOMEM;
> + }
> +
> + cnt = DIV_ROUND_UP(fw_length, 512);
> + debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
> +   __func__, dev, blk, cnt);
> + ret = mmc->block_dev.block_read(>block_dev,
> + blk, cnt, ppa_fit_addr);
> + if (ret != cnt) {
> + free(ppa_fit_addr);
> + printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
> +CONFIG_SYS_LS_PPA_FW_ADDR);
> + return -EIO;
> + }
> +
> + /* flush cache after read */
> + flush_cache((ulong)ppa_fit_addr, cnt * 512);
> +
> +#elif defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
> + struct fdt_header fit;
> +
> + debug("%s: PPA image load from NAND\n", __func__);
> +
> + nand_init();
> + ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
> +_header_len, (u_char *));
> + if (ret == -EUCLEAN) {
> + printf("NAND read of PPA FIT header at offset 0x%x failed\n",
> +CONFIG_SYS_LS_PPA_FW_ADDR);
> + return -EIO;
> + }
> +
> + fw_length = fdt_totalsize();
> +
> + ppa_fit_addr = malloc(fw_length);
> + if (!ppa_fit_addr) {
> + printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
> +fw_length);
> + return -ENOMEM;
> + }
> +
> + ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
> +_length, (u_char *)ppa_fit_addr);
> + if (ret == -EUCLEAN) {
> + free(ppa_fit_addr);
> + printf("NAND read of PPA firmware at offset 0x%x failed\n",
> +CONFIG_SYS_LS_PPA_FW_ADDR);
> + return -EIO;
> + }
> +
> + /* flush cache after read */
> + flush_cache((ulong)ppa_fit_addr, fw_length);
>  #else

Re: [U-Boot] [PATCH] rockchip: set scan_dev_for_boot_part env for rockchip SoC

[Sjoerd Simons]

On Wed, 2017-03-08 at 09:30 +0800, Eddie Cai wrote:
> Hi Simon
> 
> 2017-03-06 14:46 GMT+08:00 Eddie Cai :
> 
> > Hi Simon
> > 
> > 2017-02-23 11:33 GMT+08:00 Simon Glass :
> > 
> > > Hi Eddie,
> > > 
> > > On 22 February 2017 at 07:12, Eddie Cai  > > m>
> > > wrote:
> > > > Hi Simon
> > > > 

> Look like Tom don't like put this changes to default environment. See
> [0].
> I think I would have to limit this change on Rockchip SoC because i
> can
> only guarantee GPT table exist on Rockchip SoC. What do you think?
> [0]: https://patchwork.ozlabs.org/patch/735557/

How can you guarantee that it exists on all rockchip deployments? This
very much depends on the software stack/image people use on rockchip
boards.

One of the nice things about the distro bootcmds is that it's a
flexible generic setup which should just work regardless of how systems
are installed (as long as some basic conventions are followed). There
isn't really a requirement for people to use GPT on those system.

Also from a quick look, this seems to want to automatically write GPT
tables on whatever boot device is scanned, not just the internal media.
So you're adding a big potential for destroying peoples SD cards here
:)

Fwiw I'm also not sure what actual value of writing a GPT table is?
It's extremely unlikely that this would then allow you to successfully
boot from the device afterwards.

-- 
Sjoerd Simons
Collabora Ltd.
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Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Peter Robinson]

On Wed, Mar 8, 2017 at 8:22 AM, Trevor Woerner  wrote:
> On Wed 2017-03-08 @ 02:39:00 AM, Trevor Woerner wrote:
>> It appears as though linking u-boot with binutils-2.28 fails:
>>
>>   arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
>> headers, try linking with -N
>
> ...and as it turns out linking with -N succeeds! Who knew? The help message
> was actually helpful! :-D

I'm glad this wasn't just me seeing this. I have seen breakage with
this too but hadn't had time to investigate this further than just
realising it was the new binutils.

Simon is adding -N the proper fix? Might be useful to get a fix into
2017.03 GA as I'm sure in the coming weeks the new binutils will start
to land more widely in various distros.

Peter
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[U-Boot] [PATCH v2] ARM: keystone: Pass SPI MTD partition table via kernel command line

[Vignesh R]

SPI U-Boot image for K2 boards have now exceeded 512K partition
allocated to it and no longer fit the partitions defined in kernel DTS
file. Therefore, pass an updated MTD partition table from U-Boot as
kernel command line arguments to avoid kernel from accidentally
modifying boot loader image that has overflowed to next user partition.

To do is, introduce a common environment file for declaring SPI
partition so that each individual boards need not repeat the same.
Choose appropriate SPI bus from board config file and pass it as command
line argument to kernel.

Signed-off-by: Vignesh R 
---

v2: prefix KEYSTONE for definitions in include/environment/ti/spi.h

 include/configs/k2e_evm.h|  5 +
 include/configs/k2g_evm.h|  3 +++
 include/configs/k2hk_evm.h   |  4 
 include/configs/k2l_evm.h|  4 
 include/configs/ti_armv7_keystone2.h |  7 ++-
 include/environment/ti/spi.h | 15 +++
 6 files changed, 37 insertions(+), 1 deletion(-)
 create mode 100644 include/environment/ti/spi.h

diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 777f22540afb..3a7993e8290c 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_K2E_EVM_H
 #define __CONFIG_K2E_EVM_H
 
+#include 
+
 /* Platform type */
 #define CONFIG_SOC_K2E
 
@@ -30,6 +32,9 @@
 /* SPL SPI Loader Configuration */
 #define CONFIG_SPL_TEXT_BASE   0x0c10
 
+
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
 /* NAND Configuration */
 #define CONFIG_SYS_NAND_PAGE_2K
 
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index bd252312a20b..9e5949e3706b 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_K2G_EVM_H
 #define __CONFIG_K2G_EVM_H
 
+#include 
+
 /* Platform type */
 #define CONFIG_SOC_K2G
 
@@ -76,4 +78,5 @@
 #define CONFIG_BOUNCE_BUFFER
 #endif
 
+#define SPI_MTD_PARTS  KEYSTONE_SPI1_MTD_PARTS
 #endif /* __CONFIG_K2G_EVM_H */
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 4adb119b3066..202167bdef79 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_K2HK_EVM_H
 #define __CONFIG_K2HK_EVM_H
 
+#include 
+
 /* Platform type */
 #define CONFIG_SOC_K2HK
 
@@ -30,6 +32,8 @@
 /* SPL SPI Loader Configuration */
 #define CONFIG_SPL_TEXT_BASE   0x0c20
 
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
 /* NAND Configuration */
 #define CONFIG_SYS_NAND_PAGE_2K
 
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 9bdd56570be7..a7ccdd117cd2 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_K2L_EVM_H
 #define __CONFIG_K2L_EVM_H
 
+#include 
+
 /* Platform type */
 #define CONFIG_SOC_K2L
 
@@ -30,6 +32,8 @@
 /* SPL SPI Loader Configuration */
 #define CONFIG_SPL_TEXT_BASE   0x0c10
 
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
 /* NAND Configuration */
 #define CONFIG_SYS_NAND_PAGE_4K
 
diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index 5d4ef58e5f1a..c48d7ba17a2d 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -213,6 +213,10 @@
 /* EDMA3 */
 #define CONFIG_TI_EDMA3
 
+#define KERNEL_MTD_PARTS   \
+   "mtdparts=" \
+   SPI_MTD_PARTS
+
 #define DEFAULT_FW_INITRAMFS_BOOT_ENV  \
"name_fw_rd=k2-fw-initrd.cpio.gz\0" \
"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0"\
@@ -269,7 +273,8 @@
"sf write ${loadaddr} 0 ${filesize}\0"  \
"burn_uboot_nand=nand erase 0 0x10; "   \
"nand write ${loadaddr} 0 ${filesize}\0"\
-   "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0"  \
+   "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 "   \
+   KERNEL_MTD_PARTS\
"args_net=setenv bootargs ${bootargs} rootfstype=nfs "  \
"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
"${nfs_options} ip=dhcp\0"  \
diff --git a/include/environment/ti/spi.h b/include/environment/ti/spi.h
new file mode 100644
index ..18c857c47dc9
--- /dev/null
+++ b/include/environment/ti/spi.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for SPI on TI boards.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __TI_SPI_H
+#define __TI_SPI_H
+
+#define KEYSTONE_SPI0_MTD_PARTS "spi0.0:1m(u-boot-spl)ro,-(misc);\0"
+#define KEYSTONE_SPI1_MTD_PARTS 

Re: [U-Boot] linking rockchip-linux/u-boot.git with binutils-2.28

[Trevor Woerner]

On Wed 2017-03-08 @ 02:39:00 AM, Trevor Woerner wrote:
> It appears as though linking u-boot with binutils-2.28 fails:
> 
>   arm-oe-linux-gnueabi-ld.bfd: u-boot: Not enough room for program 
> headers, try linking with -N

...and as it turns out linking with -N succeeds! Who knew? The help message
was actually helpful! :-D
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