Re: [U-Boot] DDR training code for Armada 38x

[Stefan Roese]

Hi Chris,

On 19.09.2017 20:58, Chris Packham wrote:

When you did the port from Marvell's source did you script any of the
tidy-up that you did along the way?


Not really. At least not in a reproducible way. I spent long
hours running Lindent, recursive-replace tools and especially
manual code inspection and re-formatting on this huge code.
Still the outcome is far from perfect, but hopefully better
that the original version.


I'm running up a new board and with the upstream u-boot DDR training
occasionally fails. But with the Marvell bootloader it doesn't fail.
The initial port was done from TIP-1.29 but Marvell are now up to
TIP-1.55 so there is probably some difference that results in my board
working.

One difference I've spotted so far is that Marvell enable 2T timing
mode for all Armada 38x boards (the comment says "resolve low freq
instability"). But doing that doesn't magically make my board work.


Did you compare all DDR register values (the "good" ones and the "bad"
ones) and only the the 2T timing is different?


I'm thinking I need to compare TIP-1.29 with TIP-1.55 to look for
other differences but obviously that's going to be hard given the
style changes.


Has the style changed in between the Marvell versions as well? I
have not looked into this code for quite some time.


If you have any scripts (or even just a record of the
regexes) that you used would you be able to share them?


Please find some scripts attached, I've located that I have used while
doing this porting.

Thanks,
Stefan


replace-recursive.sh
Description: Bourne shell script


replace-common-marvell-stuff.sh
Description: Bourne shell script
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Re: [U-Boot] [PATCH v2 5/6] ARM: Add a new arch + board for QEMU's 'virt' machine

[Bin Meng]

Hi Tuomas,

On Wed, Sep 20, 2017 at 4:18 AM, Tuomas Tynkkynen
 wrote:
> This board builds an U-Boot binary that is bootable with QEMU's 'virt'
> machine on ARM. The minimal QEMU command line is:
>
> qemu-system-arm -machine virt,highmem=off -bios u-boot.bin
>
> (Note that the 'highmem=off' parameter to the 'virt' machine is required for
> PCI to work in U-Boot.) This command line enables the following:
> - u-boot.bin loaded and executing in the emulated flash at address 0x0
> - A generated device tree blob placed at the start of RAM
> - A freely configurable amount of RAM, described by the DTB
> - A PL011 serial port, discoverable via the DTB
> - An ARMv7 architected timer
> - PSCI for rebooting the system
> - A generic ECAM-based PCI host controller, discoverable via the DTB
>
> Additionally, QEMU allows plugging a bunch of useful peripherals to the PCI 
> bus.
> The following ones are supported by both U-Boot and Linux:
>
> - To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.:
> -drive if=none,file=disk.img,id=mydisk -device ich9-ahci,id=ahci -device 
> ide-drive,drive=mydisk,bus=ahci.0
> - To add an Intel E1000 network adapter, pass e.g.:
> -net nic,model=e1000 -net user

With this parameter I got:

Warning: requested NIC (anonymous, model e1000) was not created (not
supported by this machine?)

I am using QEMU v2.5.0. It's better to mention the minimum required
QEMU version in the commit message as well.

> - To add an EHCI-compliant USB host controller, pass e.g.:
> -device usb-ehci,id=ehci
> - To add a NVMe disk, pass e.g.:
> -drive if=none,file=disk.img,id=mydisk -device 
> nvme,drive=mydisk,serial=foo
>
> Signed-off-by: Tuomas Tynkkynen 
> ---
> v2:
> - enable CONFIG_NVME
> - alphasort correctly
> - remove unnecessary gd declaration
> - move board under board/emulation
> - add MAINTAINERS
> ---
>  arch/arm/Kconfig | 10 +++
>  arch/arm/mach-qemu/Kconfig   | 12 
>  board/emulation/qemu-arm/MAINTAINERS |  6 
>  board/emulation/qemu-arm/Makefile|  5 
>  board/emulation/qemu-arm/qemu-arm.c  | 33 
>  configs/qemu_arm_defconfig   | 28 +
>  include/configs/qemu-arm.h   | 58 
> 
>  7 files changed, 152 insertions(+)
>  create mode 100644 arch/arm/mach-qemu/Kconfig
>  create mode 100644 board/emulation/qemu-arm/MAINTAINERS
>  create mode 100644 board/emulation/qemu-arm/Makefile
>  create mode 100644 board/emulation/qemu-arm/qemu-arm.c
>  create mode 100644 configs/qemu_arm_defconfig
>  create mode 100644 include/configs/qemu-arm.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 53eae8953e..1de5be7a72 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -630,6 +630,14 @@ config ARCH_MX5
> select CPU_V7
> select BOARD_EARLY_INIT_F
>
> +config ARCH_QEMU
> +   bool "QEMU Virtual Platform"
> +   select CPU_V7
> +   select ARCH_SUPPORT_PSCI
> +   select DM
> +   select DM_SERIAL
> +   select OF_CONTROL
> +
>  config ARCH_RMOBILE
> bool "Renesas ARM SoCs"
> select DM
> @@ -1142,6 +1150,8 @@ source "arch/arm/mach-rmobile/Kconfig"
>
>  source "arch/arm/mach-meson/Kconfig"
>
> +source "arch/arm/mach-qemu/Kconfig"
> +
>  source "arch/arm/mach-rockchip/Kconfig"
>
>  source "arch/arm/mach-s5pc1xx/Kconfig"
> diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig
> new file mode 100644
> index 00..3500b56cb0
> --- /dev/null
> +++ b/arch/arm/mach-qemu/Kconfig
> @@ -0,0 +1,12 @@
> +if ARCH_QEMU
> +
> +config SYS_VENDOR
> +   default "emulation"
> +
> +config SYS_BOARD
> +   default "qemu-arm"
> +
> +config SYS_CONFIG_NAME
> +   default "qemu-arm"
> +
> +endif
> diff --git a/board/emulation/qemu-arm/MAINTAINERS 
> b/board/emulation/qemu-arm/MAINTAINERS
> new file mode 100644
> index 00..a803061ff4
> --- /dev/null
> +++ b/board/emulation/qemu-arm/MAINTAINERS
> @@ -0,0 +1,6 @@
> +QEMU ARM 'VIRT' BOARD
> +M: Tuomas Tynkkynen 
> +S: Maintained
> +F: board/emulation/qemu-arm/
> +F: include/configs/qemu-arm.h
> +F: configs/qemu_arm_defconfig
> diff --git a/board/emulation/qemu-arm/Makefile 
> b/board/emulation/qemu-arm/Makefile
> new file mode 100644
> index 00..716a6e9c28
> --- /dev/null
> +++ b/board/emulation/qemu-arm/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y  += qemu-arm.o
> diff --git a/board/emulation/qemu-arm/qemu-arm.c 
> b/board/emulation/qemu-arm/qemu-arm.c
> new file mode 100644
> index 00..e29ba4630f
> --- /dev/null
> +++ b/board/emulation/qemu-arm/qemu-arm.c
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (c) 2017 Tuomas Tynkkynen
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +#include 
> +#include 
> +
> +int board_init(void)
> +{
> 

Re: [U-Boot] [PATCH v2 6/6] travis.yml: Add job for running test.py in qemu_arm

[Bin Meng]

Hi Tuomas,

On Wed, Sep 20, 2017 at 4:18 AM, Tuomas Tynkkynen
 wrote:
> Note that this commit requires
> https://github.com/swarren/uboot-test-hooks/pull/14 to go in first.
>

I believe the above should not be put into the commit message, instead
we can put it below ---

> Signed-off-by: Tuomas Tynkkynen 
> ---
>  .travis.yml | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/.travis.yml b/.travis.yml
> index 1d29eb35c1..b8f69f0a0c 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -289,6 +289,11 @@ matrix:
>QEMU_TARGET="arm-softmmu"
>BUILDMAN="^integratorcp_cm926ejs$"
>  - env:
> +- TEST_PY_BD="qemu_arm"
> +  TEST_PY_TEST_SPEC="not sleep"
> +  QEMU_TARGET="arm-softmmu"
> +  BUILDMAN="^qemu_arm$"
> +- env:
>  - TEST_PY_BD="qemu_mips"
>TEST_PY_TEST_SPEC="not sleep"
>QEMU_TARGET="mips-softmmu"
> --

Regards,
Bin
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Re: [U-Boot] [PATCH v2 4/6] PCI: Add driver for a 'pci-host-ecam-generic' host controller

[Bin Meng]

Hi Tuomas,

On Wed, Sep 20, 2017 at 4:18 AM, Tuomas Tynkkynen
 wrote:
> QEMU emulates such a device with '-machine virt,highmem=off' on ARM.
> The 'highmem=off' part is required for things to work as the PCI code
> in U-Boot doesn't seem to support 64-bit BARs.
>
> Signed-off-by: Tuomas Tynkkynen 
> ---
> v2:
>  - no 'default n'
>  - remove unnecessary non-DM struct field (inherited from the Xilinx driver)
>  - fix doc comment problems (inherited from the Xilinx driver)
>  - use the new generic memory mapped config space helpers
> ---
>  drivers/pci/Kconfig |   8 +++
>  drivers/pci/Makefile|   1 +
>  drivers/pci/pcie_ecam_generic.c | 143 
> 
>  3 files changed, 152 insertions(+)
>  create mode 100644 drivers/pci/pcie_ecam_generic.c
>
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index e2a1c0a409..648dff7543 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -33,6 +33,14 @@ config PCI_PNP
> help
>   Enable PCI memory and I/O space resource allocation and assignment.
>
> +config PCIE_ECAM_GENERIC
> +   bool "Generic ECAM-based PCI host controller support"
> +   default n

Still 'default n' here?

> +   depends on DM_PCI
> +   help
> + Say Y here if you want to enable support for generic ECAM-based
> + PCIe host controllers, such as the one emulated by QEMU.
> +
>  config PCIE_DW_MVEBU
> bool "Enable Armada-8K PCIe driver (DesignWare core)"
> default n
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index ad44e83996..5eb12efbf5 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
>  endif
>  obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
>
> +obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
>  obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
>  obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
>  obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
> diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c
> new file mode 100644
> index 00..2758f90de1
> --- /dev/null
> +++ b/drivers/pci/pcie_ecam_generic.c
> @@ -0,0 +1,143 @@
> +/*
> + * Generic PCIE host provided by e.g. QEMU
> + *
> + * Heavily based on drivers/pci/pcie_xilinx.c
> + *
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +/**
> + * struct generic_ecam_pcie - generic_ecam PCIe controller state
> + * @cfg_base: The base address of memory mapped configuration space
> + */
> +struct generic_ecam_pcie {
> +   void *cfg_base;
> +};
> +
> +/**
> + * pci_generic_ecam_conf_address() - Calculate the address of a config access

nits: please add one blank line here

> + * @bus: Pointer to the PCI bus
> + * @bdf: Identifies the PCIe device to access
> + * @offset: The offset into the device's configuration space
> + * @paddress: Pointer to the pointer to write the calculates address to
> + *
> + * Calculates the address that should be accessed to perform a PCIe
> + * configuration space access for a given device identified by the PCIe
> + * controller device @pcie and the bus, device & function numbers in @bdf. If
> + * access to the device is not valid then the function will return an error
> + * code. Otherwise the address to access will be written to the pointer 
> pointed
> + * to by @paddress.
> + */
> +static int pci_generic_ecam_conf_address(struct udevice *bus, pci_dev_t bdf,
> +   uint offset, void **paddress)
> +{
> +   struct generic_ecam_pcie *pcie = dev_get_priv(bus);
> +   void *addr;
> +
> +   addr = pcie->cfg_base;
> +   addr += PCI_BUS(bdf) << 20;
> +   addr += PCI_DEV(bdf) << 15;
> +   addr += PCI_FUNC(bdf) << 12;
> +   addr += offset;
> +   *paddress = addr;
> +
> +   return 0;
> +}
> +
> +/**
> + * pci_generic_ecam_read_config() - Read from configuration space

nits: please add one blank line here

> + * @bus: Pointer to the PCI bus
> + * @bdf: Identifies the PCIe device to access
> + * @offset: The offset into the device's configuration space
> + * @valuep: A pointer at which to store the read value
> + * @size: Indicates the size of access to perform
> + *
> + * Read a value of size @size from offset @offset within the configuration
> + * space of the device identified by the bus, device & function numbers in 
> @bdf
> + * on the PCI bus @bus.
> + */
> +static int pci_generic_ecam_read_config(struct udevice *bus, pci_dev_t bdf,
> +  uint offset, ulong *valuep,
> +  enum pci_size_t size)
> +{
> +   return pci_generic_mmap_read_config(bus, 
> pci_generic_ecam_conf_address,
> +   bdf, offset, valuep, size);
> +}
> +

Re: [U-Boot] [PATCH v2 1/6] pci: Add helper for implementing memory-mapped config space accesses

[Bin Meng]

Hi Tuomas,

On Wed, Sep 20, 2017 at 4:18 AM, Tuomas Tynkkynen
 wrote:
> This sort of pattern for implementing memory-mapped PCI config space
> accesses appears in U-Boot twice already, and a third user is coming up.
> So add helper functions to avoid code duplication, similar to how Linux
> has pci_generic_config_write and pci_generic_config_read.
>
> Signed-off-by: Tuomas Tynkkynen 
> ---
>  drivers/pci/pci-uclass.c | 58 
> 
>  include/pci.h| 51 ++
>  2 files changed, 109 insertions(+)
>
> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
> index 86df141d60..5a24eb6428 100644
> --- a/drivers/pci/pci-uclass.c
> +++ b/drivers/pci/pci-uclass.c
> @@ -518,6 +518,64 @@ int pci_auto_config_devices(struct udevice *bus)
> return sub_bus;
>  }
>
> +int pci_generic_mmap_write_config(
> +   struct udevice *bus,
> +   int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void 
> **addrp),
> +   pci_dev_t bdf,
> +   uint offset,
> +   ulong value,
> +   enum pci_size_t size)
> +{
> +   void *address;
> +
> +   if (addr_f(bus, bdf, offset, ) < 0)
> +   return 0;
> +
> +   switch (size) {
> +   case PCI_SIZE_8:
> +   writeb(value, address);
> +   return 0;
> +   case PCI_SIZE_16:
> +   writew(value, address);
> +   return 0;
> +   case PCI_SIZE_32:
> +   writel(value, address);
> +   return 0;
> +   default:
> +   return -EINVAL;
> +   }
> +}
> +
> +int pci_generic_mmap_read_config(
> +   struct udevice *bus,
> +   int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void 
> **addrp),
> +   pci_dev_t bdf,
> +   uint offset,
> +   ulong *valuep,
> +   enum pci_size_t size)
> +{
> +   void *address;
> +
> +   if (addr_f(bus, bdf, offset, ) < 0) {
> +   *valuep = pci_get_ff(size);
> +   return 0;
> +   }
> +
> +   switch (size) {
> +   case PCI_SIZE_8:
> +   *valuep = readb(address);
> +   return 0;
> +   case PCI_SIZE_16:
> +   *valuep = readw(address);
> +   return 0;
> +   case PCI_SIZE_32:
> +   *valuep = readl(address);
> +   return 0;
> +   default:
> +   return -EINVAL;
> +   }
> +}
> +
>  int dm_pci_hose_probe_bus(struct udevice *bus)
>  {
> int sub_bus;
> diff --git a/include/pci.h b/include/pci.h
> index c8ef997d0d..7adc04301c 100644
> --- a/include/pci.h
> +++ b/include/pci.h
> @@ -1086,6 +1086,57 @@ int pci_read_config32(pci_dev_t pcidev, int offset, 
> u32 *valuep);
>  int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
>  int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
>
> +/**
> + * pci_generic_mmap_write_config() - Generic helper for writing to
> + * memory-mapped PCI configuration space.

nits: suggest adding one blank line here.

> + * @bus: Pointer to the PCI bus
> + * @addr_f: Callback for calculating the config space address
> + * @bdf: Identifies the PCI device to access
> + * @offset: The offset into the device's configuration space
> + * @value: The value to write
> + * @size: Indicates the size of access to perform
> + *
> + * Write the value @value of size @size from offset @offset within the
> + * configuration space of the device identified by the bus, device & function
> + * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
> + * responsible for calculating the CPU address of the respective 
> configuration
> + * space offset.
> + *
> + * Return: 0 on success, else -EINVAL
> + */
> +int pci_generic_mmap_write_config(
> +   struct udevice *bus,
> +   int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void 
> **addrp),
> +   pci_dev_t bdf,
> +   uint offset,
> +   ulong value,
> +   enum pci_size_t size);
> +
> +/**
> + * pci_generic_mmap_read_config() - Generic helper for reading from
> + * memory-mapped PCI configuration space.

nits: suggest adding one blank line here.

> + * @bus: Pointer to the PCI bus
> + * @addr_f: Callback for calculating the config space address
> + * @bdf: Identifies the PCI device to access
> + * @offset: The offset into the device's configuration space
> + * @valuep: A pointer at which to store the read value
> + * @size: Indicates the size of access to perform
> + *
> + * Read a value of size @size from offset @offset within the configuration
> + * space of the device identified by the bus, device & function numbers in 
> @bdf
> + * on the PCI bus @bus. The callback function @addr_f is responsible for
> + * calculating the CPU address of the respective configuration space offset.
> + *
> + * Return: 0 on success, else -EINVAL
> + */
> +int pci_generic_mmap_read_config(
> + 

Re: [U-Boot] [PATCH v2 2/6] pci: xilinx: Use pci_generic_mmap_{read, write}_config()

[Bin Meng]

On Wed, Sep 20, 2017 at 4:18 AM, Tuomas Tynkkynen
 wrote:
> Use the new helper function to avoid boilerplate in the driver.
>
> Note that this changes __raw_writel et al. to writel. AFAICT this is
> no problem because:
>
> - The Linux driver for the same hardware uses the non-__raw variants as
>   well (via pci_generic_config_write()).
> - This driver seems to be used only on MIPS so far, where the __raw and
>   non-__raw accessors are the same.
>
> Signed-off-by: Tuomas Tynkkynen 
> ---
>  drivers/pci/pcie_xilinx.c | 53 
> +++
>  1 file changed, 7 insertions(+), 46 deletions(-)
>

Reviewed-by: Bin Meng 
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[U-Boot] Sandbox 'usb start' causes segment fault

[Bin Meng]

Hi,

Not sure if I am running sandbox correctly with USB support, but here
is the log:

$ ./u-boot -D


U-Boot 2017.09-00191-gc145392-dirty (Sep 17 2017 - 21:33:01 +0800)

Model: sandbox
DRAM:  128 MiB
MMC:
Using default environment

In:cros-ec-keyb
Out:   vidconsole
Err:   vidconsole
Model: sandbox
SCSI:  Net:   eth0: eth@10002000, eth1: eth@8000, eth5: eth@9000
IDE:   Bus 0: not available
=> usb start
starting USB...
USB0:   scanning bus 0 for devices... Segmentation fault (core dumped)

Regards,
Bin
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Re: [U-Boot] [PATCH v3] cmd: usb: add blk devices to ignore list in tree graph

[Bin Meng]

Hi Suneel,

On Wed, Sep 20, 2017 at 2:31 AM, Suneel Garapati  wrote:
> Hi Bin,
>
> On Tue, Sep 19, 2017 at 12:32 AM, Bin Meng  wrote:
>> Hi Suneel,
>>
>> On Tue, Sep 19, 2017 at 1:55 PM, Suneel Garapati  
>> wrote:
>>> add blk child devices to ignore list while displaying
>>> usb tree graph, otherwise usb tree and info commands
>>> may cause crash treating blk as usb device.
>>>
>>> Signed-off-by: Suneel Garapati 
>>> ---
>>>
>>> Changes v3:
>>>  - remove 'check on parent uclass' in description
>>
>> thanks for making the changes.
>>
>>> Changes v2:
>>>  - remove check on parent uclass
>>> Changes v1:
>>>  - add separate check on blk uclass
>>>  - modify description
>>>  - add separate check on parent uclass as usb
>>>
>>>  cmd/usb.c | 11 ---
>>>  1 file changed, 8 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/cmd/usb.c b/cmd/usb.c
>>> index d95bcf5..3889994 100644
>>> --- a/cmd/usb.c
>>> +++ b/cmd/usb.c
>>> @@ -414,8 +414,12 @@ static void usb_show_tree_graph(struct usb_device 
>>> *dev, char *pre)
>>>
>>> udev = dev_get_parent_priv(child);
>>>
>>> -   /* Ignore emulators, we only want real devices */
>>> -   if (device_get_uclass_id(child) != UCLASS_USB_EMUL) {
>>> +   /*
>>> +* Ignore emulators and block child devices, we only want
>>> +* real devices
>>> +*/
>>> +   if ((device_get_uclass_id(child) != UCLASS_USB_EMUL) &&
>>> +   (device_get_uclass_id(child) != UCLASS_BLK)) {
>>> usb_show_tree_graph(udev, pre);
>>> pre[index] = 0;
>>> }
>>> @@ -605,7 +609,8 @@ static void usb_show_info(struct usb_device *udev)
>>> for (device_find_first_child(udev->dev, );
>>>  child;
>>>  device_find_next_child()) {
>>> -   if (device_active(child)) {
>>> +   if (device_active(child) &&
>>> +   (device_get_uclass_id(child) != UCLASS_BLK)) {
>>> udev = dev_get_parent_priv(child);
>>> usb_show_info(udev);
>>> }
>>> --
>>
>> My testing of 'usb info' looks OK, however 'usb tree' still has some
>> issues below:
>>
>> => usb tree
>> USB device tree:
>>   1  Hub (5 Gb/s, 0mA)
>>   |  U-Boot XHCI Host Controller
>>   |
>>   +-2  Hub (5 Gb/s, 0mA)
>>   | |  GenesysLogic USB3.0 Hub
>>   | |
>>   | +-5  Vendor specific (5 Gb/s, 36mA)
>>   |  Realtek USB 10/100/1000 LAN 00E04C680977
>>   |
> Leaving block devices, why the extra print here for lan port?

There is nothing wrong here. Every device has a separation line.

>
>>   +-3  Hub (480 Mb/s, 100mA)
>>   | |  GenesysLogic USB2.0 Hub
>>   | |
> And here?
>

Again, nothing wrong here.

>>   | +-6  Mass Storage (480 Mb/s, 98mA)
>>   | | |  USBest Technology USB Mass Storage Device 10c452b7c0
>>   | | |
>>
>> As you see, we just don't print out the BLK device, but we still print
>> out the | here.
> I believe if the extra print for other devices is correct, then this
> tree is fine.

It's not correct. The tree graphic does not look correct now.

> Also, I believe this is not related to the fix this patch aims at.
> Let me know if otherwise.

No, you should not fix one thing but introduce another thing.

>
> Regards,
> Suneel
>>
>>   | +-7  Human Interface (1.5 Mb/s, 70mA)
>>   |  Dell Dell USB Keyboard
>>   |
>>   +-4  Mass Storage (480 Mb/s, 300mA)
>> |  JetFlash Mass Storage Device 16Q6ZPH20GF3E8UQ
>> |
>>
>> And here.

Regards,
Bin
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Re: [U-Boot] [PATCH] imx6: disable clock command and print_cpuinfo code in SPL

[Fabio Estevam]

Hi Stefano,

On Tue, Sep 19, 2017 at 4:54 AM, Stefano Babic  wrote:

> Reason is clear: boards have in SPL a setup_display() that calls
> enable_ipu_clock. But it makes no sense to have IPU support in SPL.

Good catch, thanks!

Anatolij,

Do you plan to remove IPU code from SPL?

Thanks!
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Re: [U-Boot] [PATCH 13/13] log: Add documentation

[Masahiro Yamada]

Hi Simon


2017-09-17 6:23 GMT+09:00 Simon Glass :

> +
> +
> +To Do
> +-
> +
> +There are lots of useful additions that could be made. None of the below is
> +implemented! If you do one, please add a test in test/py/tests/test_log.py
> +
> +Convenience functions to support setting the category:
> +
> +   log_arch(level, format_string, ...) - category LOGC_ARCH
> +   log_board(level, format_string, ...) - category LOGC_BOARD
> +   log_core(level, format_string, ...) - category LOGC_CORE
> +   log_dt(level, format_string, ...) - category LOGC_DT


I do not want to see any more proliferation of log functions...



> +Convenience functions to support a category defined for a single file, for
> +example:
> +
> +   #define LOG_CATEGORY   UCLASS_USB
> +
> +all of these can use LOG_CATEGORY as the category, and a log level
> +corresponding to the function name:
> +
> +   logc(level, format_string, ...)
> +   pr_panic(format_string, ...)
> +   pr_crit(format_string, ...)
> +   pr_err(format_string, ...)
> +   pr_warn(format_string, ...)
> +   pr_note(format_string, ...)
> +   pr_info(format_string, ...)
> +   pr_detail(format_string, ...)
> +   pr_debug(format_string, ...)
>


Linux uses:

pr_emerg(fmt, ...)
pr_alert(fmt, ...)
pr_crit(fmt, ...)
pr_err(fmt, ...)
pr_warn(fmt, ...)
pr_notice(fmt, ...)
pr_info(fmt, ...)
pr_debug(fmt, ...)


Please do not invent similar, but different APIs.



-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH 06/13] log: Add an implemention of logging

[Masahiro Yamada]

Hi Simon,


2017-09-17 6:23 GMT+09:00 Simon Glass :

>
> +menu "Logging"
> +
> +config LOG
> +   bool "Enable logging support"
> +   help
> + This enables support for logging of status and debug messages. These
> + can be displayed on the console, recorded in a memory buffer, or
> + discarded if not needed. Logging supports various categories and
> + levels of severity.
> +
> +config SPL_LOG
> +   bool "Enable logging support in SPL"
> +   help
> + This enables support for logging of status and debug messages. These
> + can be displayed on the console, recorded in a memory buffer, or
> + discarded if not needed. Logging supports various categories and
> + levels of severity.


Please note CONFIG_IS_ENABLED(LOG) is never enabled for TPL_BUILD.

Since commit f1c6e1922eb57f4a212c09709801a1cc7920ffa9,
CONFIG_IS_ENABLED(LOG) is expanded to CONFIG_TPL_LOG
when building for TPL.

Since that commit, if you add SPL_ prefixed option,
you need to add a TPL_ one as well.

I cannot believe why such a commit was accepted.




> +config LOG_MAX_LEVEL
> +   int "Maximum log level to record"
> +   depends on LOG
> +   default 5
> +   help
> + This selects the maximum log level that will be recorded. Any value
> + higher than this will be ignored. If possible log statements below
> + this level will be discarded at build time. Levels:
> +
> +   0 - panic
> +   1 - critical
> +   2 - error
> +   3 - warning
> +   4 - note
> +   5 - info
> +   6 - detail
> +   7 - debug


Please do not invent our own for U-Boot.
Just use Linux log level.

0 (KERN_EMERG)  system is unusable
1 (KERN_ALERT)  action must be taken immediately
2 (KERN_CRIT)   critical conditions
3 (KERN_ERR)error conditions
4 (KERN_WARNING)warning conditions
5 (KERN_NOTICE) normal but significant condition
6 (KERN_INFO)   informational
7 (KERN_DEBUG)  debug-level messages




> +config LOG_SPL_MAX_LEVEL
> +   int "Maximum log level to record in SPL"
> +   depends on SPL_LOG
> +   default 3
> +   help
> + This selects the maximum log level that will be recorded. Any value
> + higher than this will be ignored. If possible log statements below
> + this level will be discarded at build time. Levels:
> +
> +   0 - panic
> +   1 - critical
> +   2 - error
> +   3 - warning
> +   4 - note
> +   5 - info
> +   6 - detail
> +   7 - debug
>


If you want to use CONFIG_VAL(LOG_MAX_LEVEL),
this must be SPL_LOG_MAX_LEVEL.
(this coding mistake is now hidden by another mistake)

Again, you will probably end up with TPL_LOG_MAX_LEVEL.




> +
> +/**
> + * log_dispatch() - Send a log record to all log devices for processing
> + *
> + * The log record is sent to each log device in turn, skipping those which 
> have
> + * filters which block the record
> + *
> + * @rec: Log record to dispatch
> + * @return 0 (meaning success)
> + */
> +static int log_dispatch(struct log_rec *rec)
> +{
> +   struct log_device *ldev;
> +
> +   list_for_each_entry(ldev, >log_head, sibling_node) {
> +   if (log_passes_filters(ldev, rec))
> +   ldev->drv->emit(ldev, rec);
> +   }
> +
> +   return 0;
> +}
> +
> +int _log(enum log_category_t cat, enum log_level_t level, const char *file,
> +int line, const char *func, const char *fmt, ...)
> +{
> +   char buf[CONFIG_SYS_CBSIZE];
> +   struct log_rec rec;
> +   va_list args;
> +
> +   rec.cat = cat;
> +   rec.level = level;
> +   rec.file = file;
> +   rec.line = line;
> +   rec.func = func;
> +   va_start(args, fmt);
> +   vsnprintf(buf, sizeof(buf), fmt, args);
> +   va_end(args);
> +   rec.msg = buf;
> +   if (!gd || !(gd->flags & GD_FLG_LOG_READY)) {
> +   if (gd)
> +   gd->log_drop_count++;
> +   return -ENOSYS;
> +   }
> +   log_dispatch();
> +
> +   return 0;
> +}
> +
> +int log_add_filter(const char *drv_name, enum log_category_t cat_list[],
> +  enum log_level_t max_level, const char *file_list)
> +{
> +   struct log_filter *filt;
> +   struct log_device *ldev;
> +   int i;
> +
> +   ldev = log_device_find_by_name(drv_name);
> +   if (!ldev)
> +   return -ENOENT;
> +   filt = (struct log_filter *)calloc(1, sizeof(*filt));
> +   if (!filt)
> +   return -ENOMEM;
> +
> +   if (cat_list) {
> +   filt->flags |= LOGFF_HAS_CAT;
> +   for (i = 

Re: [U-Boot] [PATCH 00/13] log: Add a new logging feature

[Masahiro Yamada]

Hi Simon,


2017-09-17 6:23 GMT+09:00 Simon Glass :
> U-Boot currently has fairly rudimentary logging features. A basic printf()
> provides console output and debug() provides debug output which is
> activated if DEBUG is defined in the file containing the debug()
> statements.
>
> It would be useful to have a few more features:
>
> - control of debug output at runtime, so  problems can potentially be
> debugged without recompiling U-Boot
> - control of which subsystems output debug information, so that (for
> example) it is possible to enable debugging for MMC or SATA at runtime
> - indication of severity with each message, so that the user can control
> whether just errors are displayed, warnings, or all debug messages
> - sending logging information to different destinations, such as console,
> memory, linux, etc,
>
> At present U-Boot has a logbuffer feature which records output in a memory
> buffer for later display or storage. This is useful but is not at present
> enabled for any board.
>
> This series introduced a new logging system which supports:
> - various log levels from panic to debug
> - log categories including all uclasses and a few others
> - log drivers to which all log records can be sent
> - log filters which control which log records make it to which drivers
>
> Enabling logging with the default options does not add much to code size.
> By default the maximum recorded log level is LOGL_INFO, meaning that debug
> messages (and above) are discarded a build-time. Increasing this level
> provides more run-time flexibility to enable/disable logging at the cost
> of increased code size.
>
> This feature is by no means finished. The README provides a long list of
> features and clean-ups that could be done. But hopefully this is a
> starting point for improving this important area in U-Boot.
>
> The series is available at u-boot-dm/log-working



As you notice, this series has lots of conflicts with my clean-up works.

The lesson we leaned is we should prepare Linux-compatible APIs where possible,
instead of inventing similar ones for our own.
Otherwise, people would start to sprinkle compat macros/headers everywhere.

In this sense, this series introduce similar, but different
interfaces.

If you want the log interface, could you implement it
as a back-end of printk() (after my clean-ups) ?
Users can use printk(), or more preferably pr_()
to call the log API.


If CONFIG_LOG is disabled, printk() falls back to printf(),
i.e. the log is immediately printed to the console.

If CONFIG_LOG is enabled, printk() sends the log message
to the log facility you are implementing.


I am not sure how much demand exists for category/file filters.
Having both of them (or even one of them) might be over-implementation.

I do not like the category filter because I do not want to see
   log(LOGC_BOARD, ...)




-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for stm32h7 SoCs

[Vikas Manocha]

Hi Patrice,

On 09/13/2017 09:00 AM, patrice.chot...@st.com wrote:
> From: Patrice Chotard 
> 
> This driver implements basic clock setup, only clock gating
> is implemented.
> 
> This driver doesn't implement .of_match as it's binded
> by MFD RCC driver.
> 
> Files include/dt-bindings/clock/stm32h7-clks.h and
> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
> will be available soon in a kernel tag, as all the
> bindings have been acked by Rob Herring [1].
> 
> [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
> 
> Signed-off-by: Patrice Chotard 
> ---
>  doc/device-tree-bindings/clock/st,stm32h7-rcc.txt | 152 
>  drivers/clk/Makefile  |   1 +
>  drivers/clk/clk_stm32h7.c | 802 
> ++
>  include/dt-bindings/clock/stm32h7-clks.h  | 167 +
>  4 files changed, 1122 insertions(+)
>  create mode 100644 doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
>  create mode 100644 drivers/clk/clk_stm32h7.c
>  create mode 100644 include/dt-bindings/clock/stm32h7-clks.h
> 
> diff --git a/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt 
> b/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
> new file mode 100644
> index 000..9d4b587
> --- /dev/null
> +++ b/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
> @@ -0,0 +1,152 @@
> +STMicroelectronics STM32H7 Reset and Clock Controller
> +=
> +
> +The RCC IP is both a reset and a clock controller.
> +
> +Please refer to clock-bindings.txt for common clock controller binding usage.
> +Please also refer to reset.txt for common reset controller binding usage.
> +
> +Required properties:
> +- compatible: Should be:
> +  "st,stm32h743-rcc"
> +
> +- reg: should be register base and length as documented in the
> +  datasheet
> +
> +- #reset-cells: 1, see below
> +
> +- #clock-cells : from common clock binding; shall be set to 1
> +
> +- clocks: External oscillator clock phandle
> +  - high speed external clock signal (HSE)
> +  - low speed external clock signal (LSE)
> +  - external I2S clock (I2S_CKIN)
> +
> +- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
> +  write protection (RTC clock).

st,syscfg is confusing if we are using it for PWR or SYSCFG peripheral of the 
device.
Also why company name to reference the phandle, it can just be syscfg or better 
something like pwr_xxx as we it pointing to pwrcfg phandle.

> +
> +- pll x node: Allow to register a pll with specific parameters.
> +  Please see PLL section below.
> +
> +Example:
> +
> + rcc: rcc@58024400 {
> + #reset-cells = <1>;
> + #clock-cells = <2>
> + compatible = "st,stm32h743-rcc", "st,stm32-rcc";
> + reg = <0x58024400 0x400>;
> + clocks = <_hse>, <_lse>, <_i2s_ckin>;
> +
> + st,syscfg = <>;

see above.

> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vco1@58024430 {
> + #clock-cells = <0>;
> + compatible = "stm32,pll";
> + reg = <0>;
> + };
> +
> + vco2@58024438 {
> + #clock-cells = <0>;
> + compatible = "stm32,pll";
> + reg = <1>;
> + st,clock-div = <2>;
> + st,clock-mult = <40>;
> + st,frac-status = <0>;
> + st,frac = <0>;
> + st,vcosel = <1>;
> + st,pllrge = <2>;
> + };
> + };
> +
> +
> +STM32H7 PLL
> +---
> +
> +The VCO of STM32 PLL could be reprensented like this:
> +
> +  Vref-   
> +>| / DIVM  |>| x DIVN | --> VCO
> +  -   
> +  ^
> +  |
> +   ---
> +  | FRACN |
> +   ---
> +
> +When the PLL is configured in integer mode:
> +- VCO = ( Vref / DIVM ) * DIVN
> +
> +When the PLL is configured in fractional mode:
> +- VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13)
> +
> +
> +Required properties for pll node:
> +- compatible: Should be:
> +  "stm32,pll"
> +
> +- #clock-cells: from common clock binding; shall be set to 0
> +- reg: Should be the pll number.
> +
> +Optional properties:
> +- st,clock-div:  DIVM division factor   : <1..63>
> +- st,clock-mult: DIVN multiplication factor : <4..512>
> +
> +- st,frac-status:
> +   - 0 Pll is configured in integer mode
> +   - 1 Pll is configure in fractional mode
> +
> +- st,frac: Fractional part of the multiplication factor : <0..8191>
> +
> +- st,vcosel: VCO selection
> +  - 0: Wide VCO range:192 to 836 MHz
> +  - 1: Medium VCO range:150 to 420 MHz
> +
> +- st,pllrge: PLL input frequency range
> +  - 0: The PLL input (Vref / DIVM) clock range frequency 

Re: [U-Boot] [PATCH v2 0/5] rockchip: back-to-bootrom: replace assembly-implementation with C-code

[Andy Yan]

Hi Philipp:


On 2017年09月19日 20:45, Dr. Philipp Tomsich wrote:

Andy,

On 19 Sep 2017, at 11:10, Dr. Philipp Tomsich 
> wrote:


Andy,

On 19 Sep 2017, at 09:19, Andy Yan > wrote:


Hi Philipp:


On 2017年09月19日 10:06, Andy Yan wrote:

Hi Philipp:


On 2017年09月19日 02:18, Philipp Tomsich wrote:

Recent discussions confirmed (what the code always assumed): the
Rockchip BROM always enters U-Boot with the stack-pointer valid
(i.e. the U-Boot startup code is running off the BROM stack).

We can thus replace the back-to-bootrom code (i.e. both the
save_boot_params and back_to_bootrom implementations) using C-code
based on setjmp/longjmp.  The new implementation is already structured
to allow an easy drop-in of Andy's changes to enter download-mode when
returning to the BROM.

This entails one minor tweak to asm/system.h, which only exported
the save_boot_params_ret prototype for ARMv7, but not for AArch64.

For v2, we force bootrom.o to alway be emitted as A32 (not T32), so we
can safely call save_boot_params_ret().


  This still have a problem, because the setjmp  implementation for 
ARM32 platform  has humb code when CONFIG_SYS_THUMB_BUILD is

enabled, this is a default setting for most ARMv7 boards.
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
".align 2\n"
"adr r0, jmp_target\n"
"add r0, r0, $1\n"  // r0 stored the jump target address and with 
bit[0] = 1, this will trigger a thumb switch in longjmp with code 
"bx r0"

#endif

When I force the setjmp code go arm code path, I can back to 
bootrom successfully, But I got a data abort exception in later. it 
seems it happens when bootrom finished the uboot code

copy, when jump to sdram, I need a further debug.


I found that r9 also need to be preserved, it seems that it hold the 
sdram base.


Thanks for testing and debugging: this is invaluable support, as I 
only have AArch64 boards to test.


The r9 issue will be easy enough to resolve.
However, it looks like I will need more work on setjmp/longjmp to 
make this safe both for T32 and A32.
Plus: I need to figure out why this didn’t show in my disassembly (I 
don’t remember whether it was a rk3188 or rk3288 board I looked at).


I had a quick look and things may be quicker to resolve than I thought.
Before I create a new version, I was wondering what the requirements 
on the BROM end are:
Without changes to setjmp/longjmp, I can currently preserve "r4-r11, 
lr, sp” (i.e "r1-r3, ip" will be clobbered).
If the BROM need any of these additional registers preserved (i.e. 
r1,r2,r3,ip): let me know and I will change setjmp/longjmp to be more 
conservative.




 The BROM code that call TPL/SPL also write in C like bellow:
 fp = (pFunc)(ptr + 4);
 ret = (*fp)(); // fp point to TPL/SPL first address
 if (ret)
 return;
 ptr = (uint8*)SDRAM_ADDR;

So the code doesn't touch the register directly, It's the compile stored 
SDRAM_ADDR in r9(I saw it on rk3036 platform).

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[U-Boot] [PATCH 1/2] arm: dts: am3517_evm: Sync DTS files with Linux 4.13-RC5

[Adam Ford]

To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.

There are some spacing issues in the patch, but they appear to be
present in the Linux source files.  I'll try to get to fixing them there,
and do a future re-sync at a later date.

Signed-off-by: Adam Ford 
---
 arch/arm/dts/am3517-evm-u-boot.dtsi |  12 
 arch/arm/dts/am3517-evm.dts |  61 +
 arch/arm/dts/am3517-u-boot.dtsi |  10 +++
 arch/arm/dts/am3517.dtsi| 107 ++
 arch/arm/dts/am35xx-clocks.dtsi | 128 
 5 files changed, 318 insertions(+)

diff --git a/arch/arm/dts/am3517-evm-u-boot.dtsi 
b/arch/arm/dts/am3517-evm-u-boot.dtsi
new file mode 100644
index 000..24a67db
--- /dev/null
+++ b/arch/arm/dts/am3517-evm-u-boot.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2017
+ * Logic PD - http://www.logicpd.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts
new file mode 100644
index 000..0e4a125
--- /dev/null
+++ b/arch/arm/dts/am3517-evm.dts
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am3517.dtsi"
+
+/ {
+   model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)";
+   compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3";
+
+   memory@8000 {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256 MB */
+   };
+
+vmmc_fixed: vmmc {
+compatible = "regulator-fixed";
+regulator-name = "vmmc_fixed";
+regulator-min-microvolt = <330>;
+regulator-max-microvolt = <330>;
+};
+};
+
+_emac {
+status = "okay";
+};
+
+_mdio {
+status = "okay";
+};
+
+ {
+   clock-frequency = <40>;
+};
+
+ {
+   clock-frequency = <40>;
+};
+
+ {
+   clock-frequency = <40>;
+};
+
+ {
+   vmmc-supply = <_fixed>;
+   bus-width = <4>;
+};
+
+ {
+  status = "disabled";
+};
+
+ {
+  status = "disabled";
+};
+
diff --git a/arch/arm/dts/am3517-u-boot.dtsi b/arch/arm/dts/am3517-u-boot.dtsi
new file mode 100644
index 000..2190052
--- /dev/null
+++ b/arch/arm/dts/am3517-u-boot.dtsi
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2017
+ * Logic PD - http://www.logicpd.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+ {
+   reg-shift = <2>;
+};
diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi
new file mode 100644
index 000..00da3f2
--- /dev/null
+++ b/arch/arm/dts/am3517.dtsi
@@ -0,0 +1,107 @@
+/*
+ * Device Tree Source for am3517 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "omap3.dtsi"
+
+/ {
+   aliases {
+   serial3 = 
+   can = 
+   };
+
+   ocp@6800 {
+   am35x_otg_hs: am35x_otg_hs@5c04 {
+   compatible = "ti,omap3-musb";
+   ti,hwmods = "am35x_otg_hs";
+   status = "disabled";
+   reg = <0x5c04 0x1000>;
+   interrupts = <71>;
+   interrupt-names = "mc";
+   };
+
+   davinci_emac: ethernet@0x5c00 {
+   compatible = "ti,am3517-emac";
+   ti,hwmods = "davinci_emac";
+   status = "disabled";
+   reg = <0x5c00 0x3>;
+   interrupts = <67 68 69 70>;
+   syscon = <_conf>;
+   ti,davinci-ctrl-reg-offset = <0x1>;
+   ti,davinci-ctrl-mod-reg-offset = <0>;
+   ti,davinci-ctrl-ram-offset = <0x2>;
+   ti,davinci-ctrl-ram-size = <0x2000>;
+   ti,davinci-rmii-en = /bits/ 8 <1>;
+   local-mac-address = [ 00 00 00 00 00 00 ];
+   };
+
+   davinci_mdio: ethernet@0x5c03 {
+   compatible = "ti,davinci_mdio";
+   ti,hwmods = "davinci_mdio";
+   status = "disabled";
+   reg = <0x5c03 0x1000>;
+   bus_freq = <100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   uart4: serial@4809e000 {
+ 

[U-Boot] [PATCH 2/2] ARM: omap3: am3517-evm: Add device tree and DM support

[Adam Ford]

With the device tree ported from Linux 4.13, this enables
Driver Model and Device Tree support for the am3517-evm

Signed-off-by: Adam Ford 
---
 arch/arm/mach-omap2/omap3/Kconfig   |  5 +++
 board/logicpd/am3517evm/am3517evm.c | 71 -
 configs/am3517_evm_defconfig|  6 ++--
 include/configs/am3517_evm.h| 14 +---
 4 files changed, 57 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-omap2/omap3/Kconfig 
b/arch/arm/mach-omap2/omap3/Kconfig
index 11f5f05..4dbf9a2 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -22,6 +22,11 @@ choice
 
 config TARGET_AM3517_EVM
bool "AM3517 EVM"
+   select DM
+   select DM_SERIAL
+   select DM_GPIO
+   select DM_I2C
+   select DM_MMC
 
 config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
diff --git a/board/logicpd/am3517evm/am3517evm.c 
b/board/logicpd/am3517evm/am3517evm.c
index c18a5a3..29f136a 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -12,6 +12,8 @@
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -34,6 +36,22 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define AM3517_IP_SW_RESET 0x48002598
 #define CPGMACSS_SW_RST(1 << 1)
+#define PHY_GPIO   30
+
+/* This is only needed until SPL gets OF support */
+#ifdef CONFIG_SPL_BUILD
+static const struct ns16550_platdata am3517_serial = {
+   .base = OMAP34XX_UART3,
+   .reg_shift = 2,
+   .clock = V_NS16550_CLK,
+   .fcr = UART_FCR_DEFVAL,
+};
+
+U_BOOT_DEVICE(am3517_uart) = {
+   "ns16550_serial",
+   _serial
+};
+#endif
 
 /*
  * Routine: board_init
@@ -113,30 +131,35 @@ int misc_init_r(void)
 
am3517_evm_musb_init();
 
-   /* activate PHY reset */
-   gpio_direction_output(30, 0);
-   gpio_set_value(30, 0);
-
-   ctr  = 0;
-   do {
-   udelay(1000);
-   ctr++;
-   } while (ctr < 300);
-
-   /* deactivate PHY reset */
-   gpio_set_value(30, 1);
-
-   /* allow the PHY to stabilize and settle down */
-   ctr = 0;
-   do {
-   udelay(1000);
-   ctr++;
-   } while (ctr < 300);
-
-   /* ensure that the module is out of reset */
-   reset = readl(AM3517_IP_SW_RESET);
-   reset &= (~CPGMACSS_SW_RST);
-   writel(reset,AM3517_IP_SW_RESET);
+   if (gpio_request(PHY_GPIO, "gpio_30") == 0) {
+   /* activate PHY reset */
+   gpio_direction_output(PHY_GPIO, 0);
+   gpio_set_value(PHY_GPIO, 0);
+
+   ctr  = 0;
+   do {
+   udelay(1000);
+   ctr++;
+   } while (ctr < 300);
+
+   /* deactivate PHY reset */
+   gpio_set_value(PHY_GPIO, 1);
+
+   /* allow the PHY to stabilize and settle down */
+   ctr = 0;
+   do {
+   udelay(1000);
+   ctr++;
+   } while (ctr < 300);
+
+   /* ensure that the module is out of reset */
+   reset = readl(AM3517_IP_SW_RESET);
+   reset &= (~CPGMACSS_SW_RST);
+   writel(reset, AM3517_IP_SW_RESET);
+
+   /* Free requested GPIO */
+   gpio_free(PHY_GPIO);
+   }
 
return 0;
 }
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 920c61c..8ab0186 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -4,11 +4,14 @@ CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x8010
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 # CONFIG_SPL_GPIO_SUPPORT is not set
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_AM3517_EVM=y
 CONFIG_EMIF4=y
+CONFIG_DEFAULT_DEVICE_TREE="am3517-evm"
 CONFIG_BOOTDELAY=10
 CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_EXT_SUPPORT is not set
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_HUSH_PARSER=y
@@ -27,13 +30,12 @@ CONFIG_CMD_CACHE=y
 # CONFIG_CMD_TIME is not set
 CONFIG_CMD_UBI=y
 CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_STORAGE=y
 # CONFIG_FAT_WRITE is not set
 CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 708a98f..adb33a9 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -21,6 +21,7 @@
  * header. That is 0x800FFFC0--0x8010 should not be used for any
  * other needs.
  */
+
 #define CONFIG_SYS_TEXT_BASE   0x8010
 #define CONFIG_SYS_SPL_MALLOC_START0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
@@ -33,16 +34,6 @@
 
 /* Hardware drivers */
 
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE(-4)
-
-/* select serial 

Re: [U-Boot] Kconfiglib update and tools/moveconfig.py

[Simon Glass]

+ML

On 19 September 2017 at 16:38, Ulf Magnusson  wrote:
> Hello,
>
> Just as an FYI, I had to change tools/moveconfig.py to keep it working
> the same as before after the Kconfiglib update - see the commit
> message and changes in
> https://lists.denx.de/pipermail/u-boot/2017-September/306735.html.
>
> I guess tools/moveconfig.py could be updated in a separate commit if
> there's something more reasonable to do now that there's 'imply'
> support. I just blindly modified it to make sure the Kconfiglib update
> was a no-op.
>
> Cheers,
> Ulf
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Re: [U-Boot] [RESEND PATCH 5/5] sunxi: video: add LCD support to DE2 driver

[Icenowy Zheng]

于 2017年9月20日 GMT+08:00 上午3:00:30, Vasily Khoruzhick  写到:
>On Tue, Sep 19, 2017 at 1:33 AM, Maxime Ripard
> wrote:
>> On Mon, Sep 18, 2017 at 10:04:21PM -0700, Vasily Khoruzhick wrote:
>>> Extend DE2 driver with LCD support
>>
>> (All) your commit messages could use a bit more details.
>
>OK, will add in v2.
>
>> Here, for example, explaining the following things would help:
>>   - Why are you creating yet another file
>
>Are you talking about any specific file? I guess adding another driver
>justifies creation of another file.
>
>>   - What is the situation with old Allwinner SoCs that should share
>> the same code
>
>As far as I can tell, DE2 is present in H3, V3s, A64 and newer. LCD is
>supported in A64 only. I.e. hardware is not present
>in H3 or V3s

The only display output of V3s is LCD.

>
>>   - What are the expected users
>
>Pinebook
>
>>   - Which SoC / board have you tested it on
>
>A64 / Pinebook
>
>>
>> etc...
>>
>>> Signed-off-by: Vasily Khoruzhick 
>>> ---
>>>  arch/arm/mach-sunxi/Kconfig |   2 +-
>>>  drivers/video/sunxi/Makefile|   2 +-
>>>  drivers/video/sunxi/sunxi_de2.c |  17 +
>>>  drivers/video/sunxi/sunxi_lcd.c | 142
>
>>>  4 files changed, 161 insertions(+), 2 deletions(-)
>>>  create mode 100644 drivers/video/sunxi/sunxi_lcd.c
>>>
>>> diff --git a/arch/arm/mach-sunxi/Kconfig
>b/arch/arm/mach-sunxi/Kconfig
>>> index 2309f5..06d697e3a7 100644
>>> --- a/arch/arm/mach-sunxi/Kconfig
>>> +++ b/arch/arm/mach-sunxi/Kconfig
>>> @@ -680,7 +680,7 @@ config VIDEO_LCD_MODE
>>>
>>>  config VIDEO_LCD_DCLK_PHASE
>>>   int "LCD panel display clock phase"
>>> - depends on VIDEO
>>> + depends on VIDEO || DM_VIDEO
>>>   default 1
>>>   ---help---
>>>   Select LCD panel display clock phase shift, range 0-3.
>>> diff --git a/drivers/video/sunxi/Makefile
>b/drivers/video/sunxi/Makefile
>>> index 0d64c2021f..8c91766c24 100644
>>> --- a/drivers/video/sunxi/Makefile
>>> +++ b/drivers/video/sunxi/Makefile
>>> @@ -6,4 +6,4 @@
>>>  #
>>>
>>>  obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o
>../videomodes.o
>>> -obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o
>../dw_hdmi.o
>>> +obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o
>../dw_hdmi.o sunxi_lcd.o
>>> diff --git a/drivers/video/sunxi/sunxi_de2.c
>b/drivers/video/sunxi/sunxi_de2.c
>>> index ee67764ac5..a838bbacd1 100644
>>> --- a/drivers/video/sunxi/sunxi_de2.c
>>> +++ b/drivers/video/sunxi/sunxi_de2.c
>>> @@ -232,6 +232,23 @@ static int sunxi_de2_probe(struct udevice *dev)
>>>   if (!(gd->flags & GD_FLG_RELOC))
>>>   return 0;
>>>
>>> + ret = uclass_find_device_by_name(UCLASS_DISPLAY,
>>> +  "sunxi_lcd", );
>>> + if (!ret) {
>>> + int mux;
>>> +
>>> + mux = 0;
>>> +
>>> + ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32,
>disp, mux,
>>> +  false);
>>> + if (!ret) {
>>> + video_set_flush_dcache(dev, 1);
>>
>> Why do you need to flush the dcache here?
>
>Copied from HDMI driver init. If it's not necessary why it's here for
>HDMI?
>
>>
>>> + return 0;
>>> + }
>>> + }
>>> +
>>> + debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
>>> +
>>>   ret = uclass_find_device_by_name(UCLASS_DISPLAY,
>>>"sunxi_dw_hdmi", );
>>>   if (!ret) {
>>> diff --git a/drivers/video/sunxi/sunxi_lcd.c
>b/drivers/video/sunxi/sunxi_lcd.c
>>> new file mode 100644
>>> index 00..154eb5835e
>>> --- /dev/null
>>> +++ b/drivers/video/sunxi/sunxi_lcd.c
>>> @@ -0,0 +1,142 @@
>>> +/*
>>> + * Allwinner LCD driver
>>> + *
>>> + * (C) Copyright 2017 Vasily Khoruzhick 
>>> + *
>>> + * SPDX-License-Identifier:  GPL-2.0+
>>> + */
>>> +
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +
>>> +struct sunxi_lcd_priv {
>>> + struct display_timing timing;
>>> + int panel_bpp;
>>> +};
>>> +
>>> +static void sunxi_lcdc_config_pinmux(void)
>>> +{
>>> + int pin;
>>> + for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
>>> + sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
>>> + sunxi_gpio_set_drv(pin, 3);
>>> + }
>>> +}
>>> +
>>> +static int sunxi_lcd_enable(struct udevice *dev, int bpp,
>>> +   const struct display_timing *edid)
>>> +{
>>> + struct sunxi_ccm_reg * const ccm =
>>> +(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>> + struct sunxi_lcdc_reg * const lcdc =
>>> +(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
>>> + struct sunxi_lcd_priv *priv = dev_get_priv(dev);
>>> + struct udevice *backlight;
>>> + 

[U-Boot] [PATCH v2 6/6] travis.yml: Add job for running test.py in qemu_arm

[Tuomas Tynkkynen]

Note that this commit requires
https://github.com/swarren/uboot-test-hooks/pull/14 to go in first.

Signed-off-by: Tuomas Tynkkynen 
---
 .travis.yml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/.travis.yml b/.travis.yml
index 1d29eb35c1..b8f69f0a0c 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -289,6 +289,11 @@ matrix:
   QEMU_TARGET="arm-softmmu"
   BUILDMAN="^integratorcp_cm926ejs$"
 - env:
+- TEST_PY_BD="qemu_arm"
+  TEST_PY_TEST_SPEC="not sleep"
+  QEMU_TARGET="arm-softmmu"
+  BUILDMAN="^qemu_arm$"
+- env:
 - TEST_PY_BD="qemu_mips"
   TEST_PY_TEST_SPEC="not sleep"
   QEMU_TARGET="mips-softmmu"
-- 
2.13.0

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[U-Boot] [PATCH v2 5/6] ARM: Add a new arch + board for QEMU's 'virt' machine

[Tuomas Tynkkynen]

This board builds an U-Boot binary that is bootable with QEMU's 'virt'
machine on ARM. The minimal QEMU command line is:

qemu-system-arm -machine virt,highmem=off -bios u-boot.bin

(Note that the 'highmem=off' parameter to the 'virt' machine is required for
PCI to work in U-Boot.) This command line enables the following:
- u-boot.bin loaded and executing in the emulated flash at address 0x0
- A generated device tree blob placed at the start of RAM
- A freely configurable amount of RAM, described by the DTB
- A PL011 serial port, discoverable via the DTB
- An ARMv7 architected timer
- PSCI for rebooting the system
- A generic ECAM-based PCI host controller, discoverable via the DTB

Additionally, QEMU allows plugging a bunch of useful peripherals to the PCI bus.
The following ones are supported by both U-Boot and Linux:

- To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.:
-drive if=none,file=disk.img,id=mydisk -device ich9-ahci,id=ahci -device 
ide-drive,drive=mydisk,bus=ahci.0
- To add an Intel E1000 network adapter, pass e.g.:
-net nic,model=e1000 -net user
- To add an EHCI-compliant USB host controller, pass e.g.:
-device usb-ehci,id=ehci
- To add a NVMe disk, pass e.g.:
-drive if=none,file=disk.img,id=mydisk -device nvme,drive=mydisk,serial=foo

Signed-off-by: Tuomas Tynkkynen 
---
v2:
- enable CONFIG_NVME
- alphasort correctly
- remove unnecessary gd declaration
- move board under board/emulation
- add MAINTAINERS
---
 arch/arm/Kconfig | 10 +++
 arch/arm/mach-qemu/Kconfig   | 12 
 board/emulation/qemu-arm/MAINTAINERS |  6 
 board/emulation/qemu-arm/Makefile|  5 
 board/emulation/qemu-arm/qemu-arm.c  | 33 
 configs/qemu_arm_defconfig   | 28 +
 include/configs/qemu-arm.h   | 58 
 7 files changed, 152 insertions(+)
 create mode 100644 arch/arm/mach-qemu/Kconfig
 create mode 100644 board/emulation/qemu-arm/MAINTAINERS
 create mode 100644 board/emulation/qemu-arm/Makefile
 create mode 100644 board/emulation/qemu-arm/qemu-arm.c
 create mode 100644 configs/qemu_arm_defconfig
 create mode 100644 include/configs/qemu-arm.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 53eae8953e..1de5be7a72 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -630,6 +630,14 @@ config ARCH_MX5
select CPU_V7
select BOARD_EARLY_INIT_F
 
+config ARCH_QEMU
+   bool "QEMU Virtual Platform"
+   select CPU_V7
+   select ARCH_SUPPORT_PSCI
+   select DM
+   select DM_SERIAL
+   select OF_CONTROL
+
 config ARCH_RMOBILE
bool "Renesas ARM SoCs"
select DM
@@ -1142,6 +1150,8 @@ source "arch/arm/mach-rmobile/Kconfig"
 
 source "arch/arm/mach-meson/Kconfig"
 
+source "arch/arm/mach-qemu/Kconfig"
+
 source "arch/arm/mach-rockchip/Kconfig"
 
 source "arch/arm/mach-s5pc1xx/Kconfig"
diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig
new file mode 100644
index 00..3500b56cb0
--- /dev/null
+++ b/arch/arm/mach-qemu/Kconfig
@@ -0,0 +1,12 @@
+if ARCH_QEMU
+
+config SYS_VENDOR
+   default "emulation"
+
+config SYS_BOARD
+   default "qemu-arm"
+
+config SYS_CONFIG_NAME
+   default "qemu-arm"
+
+endif
diff --git a/board/emulation/qemu-arm/MAINTAINERS 
b/board/emulation/qemu-arm/MAINTAINERS
new file mode 100644
index 00..a803061ff4
--- /dev/null
+++ b/board/emulation/qemu-arm/MAINTAINERS
@@ -0,0 +1,6 @@
+QEMU ARM 'VIRT' BOARD
+M: Tuomas Tynkkynen 
+S: Maintained
+F: board/emulation/qemu-arm/
+F: include/configs/qemu-arm.h
+F: configs/qemu_arm_defconfig
diff --git a/board/emulation/qemu-arm/Makefile 
b/board/emulation/qemu-arm/Makefile
new file mode 100644
index 00..716a6e9c28
--- /dev/null
+++ b/board/emulation/qemu-arm/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += qemu-arm.o
diff --git a/board/emulation/qemu-arm/qemu-arm.c 
b/board/emulation/qemu-arm/qemu-arm.c
new file mode 100644
index 00..e29ba4630f
--- /dev/null
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2017 Tuomas Tynkkynen
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+
+int board_init(void)
+{
+   return 0;
+}
+
+int dram_init(void)
+{
+   if (fdtdec_setup_memory_size() != 0)
+   return -EINVAL;
+
+   return 0;
+}
+
+int dram_init_banksize(void)
+{
+   fdtdec_setup_memory_banksize();
+
+   return 0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+   /* QEMU loads a generated DTB for us at the start of RAM. */
+   return (void *)CONFIG_SYS_SDRAM_BASE;
+}
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
new file mode 100644
index 00..2a8594d472
--- /dev/null
+++ b/configs/qemu_arm_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y

[U-Boot] [PATCH v2 4/6] PCI: Add driver for a 'pci-host-ecam-generic' host controller

[Tuomas Tynkkynen]

QEMU emulates such a device with '-machine virt,highmem=off' on ARM.
The 'highmem=off' part is required for things to work as the PCI code
in U-Boot doesn't seem to support 64-bit BARs.

Signed-off-by: Tuomas Tynkkynen 
---
v2:
 - no 'default n'
 - remove unnecessary non-DM struct field (inherited from the Xilinx driver)
 - fix doc comment problems (inherited from the Xilinx driver)
 - use the new generic memory mapped config space helpers
---
 drivers/pci/Kconfig |   8 +++
 drivers/pci/Makefile|   1 +
 drivers/pci/pcie_ecam_generic.c | 143 
 3 files changed, 152 insertions(+)
 create mode 100644 drivers/pci/pcie_ecam_generic.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index e2a1c0a409..648dff7543 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -33,6 +33,14 @@ config PCI_PNP
help
  Enable PCI memory and I/O space resource allocation and assignment.
 
+config PCIE_ECAM_GENERIC
+   bool "Generic ECAM-based PCI host controller support"
+   default n
+   depends on DM_PCI
+   help
+ Say Y here if you want to enable support for generic ECAM-based
+ PCIe host controllers, such as the one emulated by QEMU.
+
 config PCIE_DW_MVEBU
bool "Enable Armada-8K PCIe driver (DesignWare core)"
default n
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index ad44e83996..5eb12efbf5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
 endif
 obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
 
+obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
 obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
 obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
 obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c
new file mode 100644
index 00..2758f90de1
--- /dev/null
+++ b/drivers/pci/pcie_ecam_generic.c
@@ -0,0 +1,143 @@
+/*
+ * Generic PCIE host provided by e.g. QEMU
+ *
+ * Heavily based on drivers/pci/pcie_xilinx.c
+ *
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+/**
+ * struct generic_ecam_pcie - generic_ecam PCIe controller state
+ * @cfg_base: The base address of memory mapped configuration space
+ */
+struct generic_ecam_pcie {
+   void *cfg_base;
+};
+
+/**
+ * pci_generic_ecam_conf_address() - Calculate the address of a config access
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @paddress: Pointer to the pointer to write the calculates address to
+ *
+ * Calculates the address that should be accessed to perform a PCIe
+ * configuration space access for a given device identified by the PCIe
+ * controller device @pcie and the bus, device & function numbers in @bdf. If
+ * access to the device is not valid then the function will return an error
+ * code. Otherwise the address to access will be written to the pointer pointed
+ * to by @paddress.
+ */
+static int pci_generic_ecam_conf_address(struct udevice *bus, pci_dev_t bdf,
+   uint offset, void **paddress)
+{
+   struct generic_ecam_pcie *pcie = dev_get_priv(bus);
+   void *addr;
+
+   addr = pcie->cfg_base;
+   addr += PCI_BUS(bdf) << 20;
+   addr += PCI_DEV(bdf) << 15;
+   addr += PCI_FUNC(bdf) << 12;
+   addr += offset;
+   *paddress = addr;
+
+   return 0;
+}
+
+/**
+ * pci_generic_ecam_read_config() - Read from configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ */
+static int pci_generic_ecam_read_config(struct udevice *bus, pci_dev_t bdf,
+  uint offset, ulong *valuep,
+  enum pci_size_t size)
+{
+   return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
+   bdf, offset, valuep, size);
+}
+
+/**
+ * pci_generic_ecam_write_config() - Write to configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers 

[U-Boot] [PATCH v2 3/6] pci: layerscape: Use pci_generic_mmap_{read, write}_config

[Tuomas Tynkkynen]

Use the new helpers to avoid boilerplate in the driver.

Signed-off-by: Tuomas Tynkkynen 
---
 drivers/pci/pcie_layerscape.c | 68 +++
 1 file changed, 17 insertions(+), 51 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 610f85c4e8..0cb7f6d564 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -241,14 +241,19 @@ static int ls_pcie_addr_valid(struct ls_pcie *pcie, 
pci_dev_t bdf)
return 0;
 }
 
-void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf,
-  int offset)
+int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf,
+uint offset, void **paddress)
 {
-   struct udevice *bus = pcie->bus;
+   struct ls_pcie *pcie = dev_get_priv(bus);
u32 busdev;
 
-   if (PCI_BUS(bdf) == bus->seq)
-   return pcie->dbi + offset;
+   if (ls_pcie_addr_valid(pcie, bdf))
+   return -EINVAL;
+
+   if (PCI_BUS(bdf) == bus->seq) {
+   *paddress = pcie->dbi + offset;
+   return 0;
+   }
 
busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) |
 PCIE_ATU_DEV(PCI_DEV(bdf)) |
@@ -256,67 +261,28 @@ void *ls_pcie_conf_address(struct ls_pcie *pcie, 
pci_dev_t bdf,
 
if (PCI_BUS(bdf) == bus->seq + 1) {
ls_pcie_cfg0_set_busdev(pcie, busdev);
-   return pcie->cfg0 + offset;
+   *paddress = pcie->cfg0 + offset;
} else {
ls_pcie_cfg1_set_busdev(pcie, busdev);
-   return pcie->cfg1 + offset;
+   *paddress = pcie->cfg1 + offset;
}
+   return 0;
 }
 
 static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
   uint offset, ulong *valuep,
   enum pci_size_t size)
 {
-   struct ls_pcie *pcie = dev_get_priv(bus);
-   void *address;
-
-   if (ls_pcie_addr_valid(pcie, bdf)) {
-   *valuep = pci_get_ff(size);
-   return 0;
-   }
-
-   address = ls_pcie_conf_address(pcie, bdf, offset);
-
-   switch (size) {
-   case PCI_SIZE_8:
-   *valuep = readb(address);
-   return 0;
-   case PCI_SIZE_16:
-   *valuep = readw(address);
-   return 0;
-   case PCI_SIZE_32:
-   *valuep = readl(address);
-   return 0;
-   default:
-   return -EINVAL;
-   }
+   return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
+   bdf, offset, valuep, size);
 }
 
 static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,
enum pci_size_t size)
 {
-   struct ls_pcie *pcie = dev_get_priv(bus);
-   void *address;
-
-   if (ls_pcie_addr_valid(pcie, bdf))
-   return 0;
-
-   address = ls_pcie_conf_address(pcie, bdf, offset);
-
-   switch (size) {
-   case PCI_SIZE_8:
-   writeb(value, address);
-   return 0;
-   case PCI_SIZE_16:
-   writew(value, address);
-   return 0;
-   case PCI_SIZE_32:
-   writel(value, address);
-   return 0;
-   default:
-   return -EINVAL;
-   }
+   return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
+bdf, offset, value, size);
 }
 
 /* Clear multi-function bit */
-- 
2.13.0

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[U-Boot] [PATCH v2 1/6] pci: Add helper for implementing memory-mapped config space accesses

[Tuomas Tynkkynen]

This sort of pattern for implementing memory-mapped PCI config space
accesses appears in U-Boot twice already, and a third user is coming up.
So add helper functions to avoid code duplication, similar to how Linux
has pci_generic_config_write and pci_generic_config_read.

Signed-off-by: Tuomas Tynkkynen 
---
 drivers/pci/pci-uclass.c | 58 
 include/pci.h| 51 ++
 2 files changed, 109 insertions(+)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 86df141d60..5a24eb6428 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -518,6 +518,64 @@ int pci_auto_config_devices(struct udevice *bus)
return sub_bus;
 }
 
+int pci_generic_mmap_write_config(
+   struct udevice *bus,
+   int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void 
**addrp),
+   pci_dev_t bdf,
+   uint offset,
+   ulong value,
+   enum pci_size_t size)
+{
+   void *address;
+
+   if (addr_f(bus, bdf, offset, ) < 0)
+   return 0;
+
+   switch (size) {
+   case PCI_SIZE_8:
+   writeb(value, address);
+   return 0;
+   case PCI_SIZE_16:
+   writew(value, address);
+   return 0;
+   case PCI_SIZE_32:
+   writel(value, address);
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
+int pci_generic_mmap_read_config(
+   struct udevice *bus,
+   int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void 
**addrp),
+   pci_dev_t bdf,
+   uint offset,
+   ulong *valuep,
+   enum pci_size_t size)
+{
+   void *address;
+
+   if (addr_f(bus, bdf, offset, ) < 0) {
+   *valuep = pci_get_ff(size);
+   return 0;
+   }
+
+   switch (size) {
+   case PCI_SIZE_8:
+   *valuep = readb(address);
+   return 0;
+   case PCI_SIZE_16:
+   *valuep = readw(address);
+   return 0;
+   case PCI_SIZE_32:
+   *valuep = readl(address);
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
 int dm_pci_hose_probe_bus(struct udevice *bus)
 {
int sub_bus;
diff --git a/include/pci.h b/include/pci.h
index c8ef997d0d..7adc04301c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1086,6 +1086,57 @@ int pci_read_config32(pci_dev_t pcidev, int offset, u32 
*valuep);
 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
 
+/**
+ * pci_generic_mmap_write_config() - Generic helper for writing to
+ * memory-mapped PCI configuration space.
+ * @bus: Pointer to the PCI bus
+ * @addr_f: Callback for calculating the config space address
+ * @bdf: Identifies the PCI device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
+ * responsible for calculating the CPU address of the respective configuration
+ * space offset.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+int pci_generic_mmap_write_config(
+   struct udevice *bus,
+   int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void 
**addrp),
+   pci_dev_t bdf,
+   uint offset,
+   ulong value,
+   enum pci_size_t size);
+
+/**
+ * pci_generic_mmap_read_config() - Generic helper for reading from
+ * memory-mapped PCI configuration space.
+ * @bus: Pointer to the PCI bus
+ * @addr_f: Callback for calculating the config space address
+ * @bdf: Identifies the PCI device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus. The callback function @addr_f is responsible for
+ * calculating the CPU address of the respective configuration space offset.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+int pci_generic_mmap_read_config(
+   struct udevice *bus,
+   int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void 
**addrp),
+   pci_dev_t bdf,
+   uint offset,
+   ulong *valuep,
+   enum pci_size_t size);
+
 #ifdef CONFIG_DM_PCI_COMPAT
 /* Compatibility with old naming */
 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
-- 
2.13.0

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[U-Boot] [PATCH v2 2/6] pci: xilinx: Use pci_generic_mmap_{read, write}_config()

[Tuomas Tynkkynen]

Use the new helper function to avoid boilerplate in the driver.

Note that this changes __raw_writel et al. to writel. AFAICT this is
no problem because:

- The Linux driver for the same hardware uses the non-__raw variants as
  well (via pci_generic_config_write()).
- This driver seems to be used only on MIPS so far, where the __raw and
  non-__raw accessors are the same.

Signed-off-by: Tuomas Tynkkynen 
---
 drivers/pci/pcie_xilinx.c | 53 +++
 1 file changed, 7 insertions(+), 46 deletions(-)

diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
index 08e2e93445..d788552fed 100644
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -43,7 +43,7 @@ static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
 
 /**
  * pcie_xilinx_config_address() - Calculate the address of a config access
- * @pcie: Pointer to the PCI controller state
+ * @udev: Pointer to the PCI bus
  * @bdf: Identifies the PCIe device to access
  * @offset: The offset into the device's configuration space
  * @paddress: Pointer to the pointer to write the calculates address to
@@ -57,9 +57,10 @@ static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
  *
  * Return: 0 on success, else -ENODEV
  */
-static int pcie_xilinx_config_address(struct xilinx_pcie *pcie, pci_dev_t bdf,
+static int pcie_xilinx_config_address(struct udevice *udev, pci_dev_t bdf,
  uint offset, void **paddress)
 {
+   struct xilinx_pcie *pcie = dev_get_priv(udev);
unsigned int bus = PCI_BUS(bdf);
unsigned int dev = PCI_DEV(bdf);
unsigned int func = PCI_FUNC(bdf);
@@ -103,29 +104,8 @@ static int pcie_xilinx_read_config(struct udevice *bus, 
pci_dev_t bdf,
   uint offset, ulong *valuep,
   enum pci_size_t size)
 {
-   struct xilinx_pcie *pcie = dev_get_priv(bus);
-   void *address;
-   int err;
-
-   err = pcie_xilinx_config_address(pcie, bdf, offset, );
-   if (err < 0) {
-   *valuep = pci_get_ff(size);
-   return 0;
-   }
-
-   switch (size) {
-   case PCI_SIZE_8:
-   *valuep = __raw_readb(address);
-   return 0;
-   case PCI_SIZE_16:
-   *valuep = __raw_readw(address);
-   return 0;
-   case PCI_SIZE_32:
-   *valuep = __raw_readl(address);
-   return 0;
-   default:
-   return -EINVAL;
-   }
+   return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address,
+   bdf, offset, valuep, size);
 }
 
 /**
@@ -146,27 +126,8 @@ static int pcie_xilinx_write_config(struct udevice *bus, 
pci_dev_t bdf,
uint offset, ulong value,
enum pci_size_t size)
 {
-   struct xilinx_pcie *pcie = dev_get_priv(bus);
-   void *address;
-   int err;
-
-   err = pcie_xilinx_config_address(pcie, bdf, offset, );
-   if (err < 0)
-   return 0;
-
-   switch (size) {
-   case PCI_SIZE_8:
-   __raw_writeb(value, address);
-   return 0;
-   case PCI_SIZE_16:
-   __raw_writew(value, address);
-   return 0;
-   case PCI_SIZE_32:
-   __raw_writel(value, address);
-   return 0;
-   default:
-   return -EINVAL;
-   }
+   return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,
+bdf, offset, value, size);
 }
 
 /**
-- 
2.13.0

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[U-Boot] [PATCH v2 0/6] Board for QEMU's '-machine virt' on ARM

[Tuomas Tynkkynen]

These patches add a board for running U-Boot under QEMU's '-machine virt'
emulation, thus making it possible to boot Linux distros that use the
extlinux.conf booting method under '-machine virt'.

To some extent, this is currently possible by emulating and running
U-Boot on some of the Versatile boards, but (IIRC) they have some
limitations like limiting to 1GB of RAM or lacking support for PCI.

Changes in v2:
 - Introduce helper functions for implementing memory-mapped PCI config
   space accesses + refactor two existing drivers to use them.
 - Addresses Bin Meng's review comments (in patches 4 & 5)
 - Hook up test.py to run on Travis CI (patch 6). This requires
   https://github.com/swarren/uboot-test-hooks/pull/14 to go in first.

Travis run with the uboot-test-hooks hacked to point to my local
repository: https://travis-ci.org/dezgeg/u-boot/builds/276392558

Tuomas Tynkkynen (6):
  pci: Add helper for implementing memory-mapped config space accesses
  pci: xilinx: Use pci_generic_mmap_{read,write}_config()
  pci: layerscape: Use pci_generic_mmap_{read,write}_config
  PCI: Add driver for a 'pci-host-ecam-generic' host controller
  ARM: Add a new arch + board for QEMU's 'virt' machine
  travis.yml: Add job for running test.py in qemu_arm

 .travis.yml  |   5 ++
 arch/arm/Kconfig |  10 +++
 arch/arm/mach-qemu/Kconfig   |  12 +++
 board/emulation/qemu-arm/MAINTAINERS |   6 ++
 board/emulation/qemu-arm/Makefile|   5 ++
 board/emulation/qemu-arm/qemu-arm.c  |  33 
 configs/qemu_arm_defconfig   |  28 +++
 drivers/pci/Kconfig  |   8 ++
 drivers/pci/Makefile |   1 +
 drivers/pci/pci-uclass.c |  58 ++
 drivers/pci/pcie_ecam_generic.c  | 143 +++
 drivers/pci/pcie_layerscape.c|  68 +
 drivers/pci/pcie_xilinx.c|  53 ++---
 include/configs/qemu-arm.h   |  58 ++
 include/pci.h|  51 +
 15 files changed, 442 insertions(+), 97 deletions(-)
 create mode 100644 arch/arm/mach-qemu/Kconfig
 create mode 100644 board/emulation/qemu-arm/MAINTAINERS
 create mode 100644 board/emulation/qemu-arm/Makefile
 create mode 100644 board/emulation/qemu-arm/qemu-arm.c
 create mode 100644 configs/qemu_arm_defconfig
 create mode 100644 drivers/pci/pcie_ecam_generic.c
 create mode 100644 include/configs/qemu-arm.h

-- 
2.13.0

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Re: [U-Boot] [PATCH 1/1] test/py: provide example scripts for integrating qemu

[Heinrich Schuchardt]

On 09/18/2017 11:28 PM, Stephen Warren wrote:
> On 09/18/2017 01:55 PM, Heinrich Schuchardt wrote:
>> On 09/18/2017 08:27 PM, Stephen Warren wrote:
>>> On 09/17/2017 01:32 PM, Heinrich Schuchardt wrote:
 The necessary parameters for running Python tests on qemu are
 tediouus to find.
>>>
>>> Nit: tedious
>>>
>>> Let's wrap the commit description to 72-74 characters; it's rather
>>> narrow right now.
>>>

 The patch adds examples for u-boot-test-console and
 u-boot-test-reset.
>>>
 diff --git a/test/py/README.md b/test/py/README.md
 index 829c7efbb2..f3ad10df5a 100644
 --- a/test/py/README.md
 +++ b/test/py/README.md
 @@ -197,6 +197,23 @@ simulator includes a virtual reset button! If
 not, you can launch the
    simulator from `u-boot-test-reset` instead, while arranging for
 this console
    process to always communicate with the current simulator instance.
> 
 +    #!/bin/sh
 +    touch /tmp/u-boot-monitor-socket
 +    qemu-system-x86_64 -bios build-qemu-x86/u-boot.rom -nographic
 -netdev \
 +
 user,id=eth0,tftp=../tftp,net=192.168.76.0/24,dhcpstart=192.168.76.9 \
> 
>>> I think this (and the other) script should "exec" the commands to avoid
>>> leaving the shell instance around.
>>
>> Is this really needed? It just adds complexity.
>> You cannot execute anything in the lines after exec,
>> e.g. deleting the socket file.
> 
> Not using exec won't break functionality. However, there's no point
> leaving the shell process hanging about, and since you're editing the
> change anyway it's trivial to fix this up. At present, there's no need
> to run anything after qemu. If we ever have need to, we can remove the
> exec at that time.
> 
>>> This example seems to enable networking support in qemu, and a TFTP
>>> server. I believe you'll need to provide an example Python board
>>> configuration so that test/py knows to enable the network tests.
>>
>> tftp is used for testing bootefi hello
>>
>> Empty file
>> __init__.py
> 
> __init__.py isn't the correct filename. You would need to implement
> u_boot_boardenv_sandbox_na.py I believe. Also, the file can't be empty;
> it needs specific content to enable the TFTP test. See the comments in
> e.g. test/py/tests/test_net.py or test/py/tests/test_efi_loader.py. If
> you don't want to complicate the simple example with this, then I'd
> suggest simplifying the qemu command-line to remove all the
> network/TFTP-related options.
> 
>> u_boot_boardenv_qemu_x86.py
>> env__net_dhcp_server = True
>> env__efi_loader_helloworld_file = {
>>  "fn": "helloworld.efi",
>>  "size": 4298,
>>  "crc32": "55d96ef8",
>> }
>>
>> This is another file needed:
>>
>> u-boot-test-quit
>> #!/bin/sh
>> echo quit | socat - UNIX-CONNECT:/tmp/u-boot-monitor-socket
> 
> The test/py framework doesn't execute "u-boot-test-quit. Adding such a
> file won't affect anything.
> 
>> The following script comes in handy to create the .py file:
>>
>> #!/bin/bash
>> echo env__efi_loader_$(basename $1 | sed 's/\./_/g') = \{
>> echo '    "fn":' $(basename $1)
>> echo '    "len":' $(stat --printf="%s" $1)
>> echo '    "crc32":' $(crc32 $1)
>> echo \}
> 
> Let's just specify the content of the Python file (which the user can
> simply cut/past) rather than making life complicated by writing a shell
> script to create the Python file.
> 
 +    -device e1000,netdev=eth0 -machine pc-i440fx-2.8 \
 +    -monitor unix:/tmp/u-boot-monitor-socket,server,nowait
 +
 +In `u-boot-test-reset` call the socat command to send a system reset:
 +
 +    #!/bin/sh
 +    echo system_reset | socat -
 UNIX-CONNECT:/tmp/u-boot-monitor-socket
 +    sleep 1
 +    true
>>>
>>> Why is the sleep needed?
>>
>> This avoids race conditions.
>> Qemu will need some milliseconds to actually shut down qemu.
>> I want to be sure that Python does not execute any command before this
>> is completed.
> 
> I don't believe there's any issue here. test/py will wait for qemu to
> boot U-Boot before attempting to send any commands after the reset
> occurs, and that wait operation can start as soon as the reset trigger
> is sent. Did you observe any issue in practice?
> 
>>> The true command shouldn't have any effect
>>> given set -e isn't in use.
>>
>> man dash:
>> The shell will return the exit status of the last command executed.
>>
>> If the last command is false running the test suite fails.
> 
> OK. Why would either the echo or sleep fail? If they do, then that
> failure should be passed back to test/py so that it can record the
> problem. Errors shouldn't just be ignored.
> 

true is really needed here. The return code of the script otherwise is
always false even though the system reset succeeds.

If you really want to analyze if qemu successfully executes the control
commands you have to use qmp.

But I wanted to create a trivial example and not start parsing JSON.

Just for reference, this is how you would do a 

Re: [U-Boot] [RESEND PATCH 5/5] sunxi: video: add LCD support to DE2 driver

[Jernej Škrabec]

Hi,

Dne torek, 19. september 2017 ob 21:00:30 CEST je Vasily Khoruzhick 
napisal(a):
> On Tue, Sep 19, 2017 at 1:33 AM, Maxime Ripard
> 
>  wrote:
> > On Mon, Sep 18, 2017 at 10:04:21PM -0700, Vasily Khoruzhick wrote:
> >> Extend DE2 driver with LCD support
> > 
> > (All) your commit messages could use a bit more details.
> 
> OK, will add in v2.
> 
> > Here, for example, explaining the following things would help:
> >   - Why are you creating yet another file
> 
> Are you talking about any specific file? I guess adding another driver
> justifies creation of another file.
> 
> >   - What is the situation with old Allwinner SoCs that should share
> >   
> > the same code
> 
> As far as I can tell, DE2 is present in H3, V3s, A64 and newer. LCD is
> supported in A64 only. I.e. hardware is not present
> in H3 or V3s
> 
> >   - What are the expected users
> 
> Pinebook
> 
> >   - Which SoC / board have you tested it on
> 
> A64 / Pinebook
> 
> > etc...
> > 
> >> Signed-off-by: Vasily Khoruzhick 
> >> ---
> >> 
> >>  arch/arm/mach-sunxi/Kconfig |   2 +-
> >>  drivers/video/sunxi/Makefile|   2 +-
> >>  drivers/video/sunxi/sunxi_de2.c |  17 +
> >>  drivers/video/sunxi/sunxi_lcd.c | 142
> >>   4 files changed, 161
> >>  insertions(+), 2 deletions(-)
> >>  create mode 100644 drivers/video/sunxi/sunxi_lcd.c
> >> 
> >> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> >> index 2309f5..06d697e3a7 100644
> >> --- a/arch/arm/mach-sunxi/Kconfig
> >> +++ b/arch/arm/mach-sunxi/Kconfig
> >> @@ -680,7 +680,7 @@ config VIDEO_LCD_MODE
> >> 
> >>  config VIDEO_LCD_DCLK_PHASE
> >>  
> >>   int "LCD panel display clock phase"
> >> 
> >> - depends on VIDEO
> >> + depends on VIDEO || DM_VIDEO
> >> 
> >>   default 1
> >>   ---help---
> >>   Select LCD panel display clock phase shift, range 0-3.
> >> 
> >> diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile
> >> index 0d64c2021f..8c91766c24 100644
> >> --- a/drivers/video/sunxi/Makefile
> >> +++ b/drivers/video/sunxi/Makefile
> >> @@ -6,4 +6,4 @@
> >> 
> >>  #
> >>  
> >>  obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o
> >>  ../videomodes.o>> 
> >> -obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o
> >> ../dw_hdmi.o
> >> +obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o
> >> ../dw_hdmi.o sunxi_lcd.o diff --git a/drivers/video/sunxi/sunxi_de2.c
> >> b/drivers/video/sunxi/sunxi_de2.c index ee67764ac5..a838bbacd1 100644
> >> --- a/drivers/video/sunxi/sunxi_de2.c
> >> +++ b/drivers/video/sunxi/sunxi_de2.c
> >> @@ -232,6 +232,23 @@ static int sunxi_de2_probe(struct udevice *dev)
> >> 
> >>   if (!(gd->flags & GD_FLG_RELOC))
> >>   
> >>   return 0;
> >> 
> >> + ret = uclass_find_device_by_name(UCLASS_DISPLAY,
> >> +  "sunxi_lcd", );
> >> + if (!ret) {
> >> + int mux;
> >> +
> >> + mux = 0;
> >> +
> >> + ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp,
> >> mux,
> >> +  false);
> >> + if (!ret) {
> >> + video_set_flush_dcache(dev, 1);
> > 
> > Why do you need to flush the dcache here?
> 
> Copied from HDMI driver init. If it's not necessary why it's here for HDMI?
> 

When I was developing HDMI driver, it proved necessary, since screen was not 
rendered correctly otherwise. I guess simple test without this line would show 
if it is really necessary or not.

> >> + return 0;
> >> + }
> >> + }
> >> +
> >> + debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
> >> +
> >> 
> >>   ret = uclass_find_device_by_name(UCLASS_DISPLAY,
> >>   
> >>"sunxi_dw_hdmi", );
> >>   
> >>   if (!ret) {
> >> 
> >> diff --git a/drivers/video/sunxi/sunxi_lcd.c
> >> b/drivers/video/sunxi/sunxi_lcd.c new file mode 100644
> >> index 00..154eb5835e
> >> --- /dev/null
> >> +++ b/drivers/video/sunxi/sunxi_lcd.c
> >> @@ -0,0 +1,142 @@
> >> +/*
> >> + * Allwinner LCD driver
> >> + *
> >> + * (C) Copyright 2017 Vasily Khoruzhick 
> >> + *
> >> + * SPDX-License-Identifier:  GPL-2.0+
> >> + */
> >> +
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +
> >> +struct sunxi_lcd_priv {
> >> + struct display_timing timing;
> >> + int panel_bpp;
> >> +};
> >> +
> >> +static void sunxi_lcdc_config_pinmux(void)
> >> +{
> >> + int pin;
> >> + for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
> >> + sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
> >> + sunxi_gpio_set_drv(pin, 3);
> >> + }
> >> +}
> >> +
> >> +static int 

[U-Boot] [PATCH v3 1/1] test/py: provide example scripts for integrating qemu

[Heinrich Schuchardt]

The necessary parameters for running Python tests on qemu are
tedious to find.

The patch adds a complete example for running the Python tests for
qemu-x86_defconfig on an X86 system.

Cc: Stephen Warren 
Signed-off-by: Heinrich Schuchardt 
---
v3
Move the example into the correct section.
Consider comments by Stephen.
v2
Include all necessary information to run tests for qemu-x86_defconfig
in a separate chapter.
---
 test/py/README.md | 81 +++
 1 file changed, 81 insertions(+)

diff --git a/test/py/README.md b/test/py/README.md
index 829c7efbb2..80e26a3460 100644
--- a/test/py/README.md
+++ b/test/py/README.md
@@ -330,6 +330,87 @@ CROSS_COMPILE=arm-none-eabi- \
 ./test/py/test.py --bd seaboard --build
 ```
 
+ Running tests for qemu-x86\_defconfig on an x86 system
+
+We build u-boot.rom with
+
+export BUILD_ROM=y
+make mrproper
+make qemu-x86_defconfig
+make
+
+We create directories `$HOME/ubtest/bin` and `$HOME/ubtest/py` for the script
+files below and `../tftp` for the tftp server.
+
+We copy helloworld.efi to the tftp directory.
+
+cp lib/efi_loader/helloworld.efi ../tftp/
+
+This file is used by the test\_efi\_loader.py test case.
+
+In the `$HOME/ubtest/bin` directory we create:
+
+File `u-boot-test-console` chmod 755
+
+#!/bin/sh
+touch /tmp/u-boot-monitor-socket
+exec qemu-system-x86_64 -bios u-boot.rom -nographic -netdev \
+  user,id=eth0,tftp=../tftp,net=192.168.76.0/24,dhcpstart=192.168.76.9 \
+  -device e1000,netdev=eth0 -machine pc-i440fx-2.8 \
+  -monitor unix:/tmp/u-boot-monitor-socket,server,nowait
+
+This script is executed when the tests commence. It starts qemu with a network
+and a tftp server enabled. The control console is directed to the Unix socket
+`/tmp/u-boot-monitor-socket`.
+
+File `u-boot-test-flash` chmod 755
+
+#!/bin/sh
+echo ... u-boot-test-flash ...
+
+This script serves to initialize the board. Nothing needs to be done here as we
+pass u-boot.rom as a parameter in `u-boot-test-console`.
+
+File `u-boot-test-quit` chmod 755
+
+#!/bin/sh
+echo quit | socat - UNIX-CONNECT:/tmp/u-boot-monitor-socket
+
+This script is called when all tests are completed. The `quit` command is
+passed to the qemu control console to terminate the qemu session.
+
+File `u-boot-test-reset` chmod 755
+
+#!/bin/sh
+echo system_reset | socat - UNIX-CONNECT:/tmp/u-boot-monitor-socket
+true
+
+This script is called when a board reset is needed. The `system_reset` command
+is passed to the qemu control console to reboot the qemu instance. The script
+has to return true or the tests will fail.
+
+In the `$HOME/ubtest/py` directory we create file `u_boot_boardenv_qemu_x86.py`
+
+env__net_dhcp_server = True
+env__efi_loader_helloworld_file = {
+  "fn": "helloworld.efi",
+  "size": 4298,
+  "crc32": "55d96ef8",
+}
+
+The parameter `env__net_dhcp_server` enables the network tests. The parameter
+`env__efi_loader_helloworld_file` is needed to make the file `helloworld.efi`
+available which is loaded from the tftp server in `test_efi_loader.py`.
+
+The fields size and crc32 have to be updated to match the actual values. The
+`crc32` command can be used to determine the latter.
+
+We now can run the Python tests with
+
+export PATH=$HOME/ubtest/bin:/usr/bin:/bin
+export PYTHONPATH=$HOME/ubtest/py
+./test/py/test.py --bd=qemu-x86 --build-dir=.
+
 ## Writing tests
 
 Please refer to the pytest documentation for details of writing pytest tests.
-- 
2.11.0

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Re: [U-Boot] [PATCH V3 1/5] mmc: uniphier-sd: Factor out register IO

[Marek Vasut]

On 09/12/2017 07:04 PM, Marek Vasut wrote:
> On 08/20/2017 05:11 PM, Marek Vasut wrote:
>> This patch prepares the driver to support controller(s) with registers
>> at locations shifted by constant. Pull out the readl()/writel() from
>> the driver into separate functions, where the adjustment of the register
>> offset can be easily contained.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Masahiro Yamada 
>> Cc: Jaehoon Chung 
> 
> Hello Jaehoon,
> 
> just a reminder that this missed previous MW, so it would be nice if it
> made it into this one.

Another week has passed and no response. It has been a month since these
patches were posted and ACKed, but they are still not in the tree, what
is going on ?!

> Thanks
> 
>> ---
>> V2: Use unsigned int for the reg argument
>> V3: Remove const ...
> [...]
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [RESEND PATCH 5/5] sunxi: video: add LCD support to DE2 driver

[Vasily Khoruzhick]

On Tue, Sep 19, 2017 at 1:33 AM, Maxime Ripard
 wrote:
> On Mon, Sep 18, 2017 at 10:04:21PM -0700, Vasily Khoruzhick wrote:
>> Extend DE2 driver with LCD support
>
> (All) your commit messages could use a bit more details.

OK, will add in v2.

> Here, for example, explaining the following things would help:
>   - Why are you creating yet another file

Are you talking about any specific file? I guess adding another driver
justifies creation of another file.

>   - What is the situation with old Allwinner SoCs that should share
> the same code

As far as I can tell, DE2 is present in H3, V3s, A64 and newer. LCD is
supported in A64 only. I.e. hardware is not present
in H3 or V3s

>   - What are the expected users

Pinebook

>   - Which SoC / board have you tested it on

A64 / Pinebook

>
> etc...
>
>> Signed-off-by: Vasily Khoruzhick 
>> ---
>>  arch/arm/mach-sunxi/Kconfig |   2 +-
>>  drivers/video/sunxi/Makefile|   2 +-
>>  drivers/video/sunxi/sunxi_de2.c |  17 +
>>  drivers/video/sunxi/sunxi_lcd.c | 142 
>> 
>>  4 files changed, 161 insertions(+), 2 deletions(-)
>>  create mode 100644 drivers/video/sunxi/sunxi_lcd.c
>>
>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
>> index 2309f5..06d697e3a7 100644
>> --- a/arch/arm/mach-sunxi/Kconfig
>> +++ b/arch/arm/mach-sunxi/Kconfig
>> @@ -680,7 +680,7 @@ config VIDEO_LCD_MODE
>>
>>  config VIDEO_LCD_DCLK_PHASE
>>   int "LCD panel display clock phase"
>> - depends on VIDEO
>> + depends on VIDEO || DM_VIDEO
>>   default 1
>>   ---help---
>>   Select LCD panel display clock phase shift, range 0-3.
>> diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile
>> index 0d64c2021f..8c91766c24 100644
>> --- a/drivers/video/sunxi/Makefile
>> +++ b/drivers/video/sunxi/Makefile
>> @@ -6,4 +6,4 @@
>>  #
>>
>>  obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o 
>> ../videomodes.o
>> -obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
>> +obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o 
>> sunxi_lcd.o
>> diff --git a/drivers/video/sunxi/sunxi_de2.c 
>> b/drivers/video/sunxi/sunxi_de2.c
>> index ee67764ac5..a838bbacd1 100644
>> --- a/drivers/video/sunxi/sunxi_de2.c
>> +++ b/drivers/video/sunxi/sunxi_de2.c
>> @@ -232,6 +232,23 @@ static int sunxi_de2_probe(struct udevice *dev)
>>   if (!(gd->flags & GD_FLG_RELOC))
>>   return 0;
>>
>> + ret = uclass_find_device_by_name(UCLASS_DISPLAY,
>> +  "sunxi_lcd", );
>> + if (!ret) {
>> + int mux;
>> +
>> + mux = 0;
>> +
>> + ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
>> +  false);
>> + if (!ret) {
>> + video_set_flush_dcache(dev, 1);
>
> Why do you need to flush the dcache here?

Copied from HDMI driver init. If it's not necessary why it's here for HDMI?

>
>> + return 0;
>> + }
>> + }
>> +
>> + debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
>> +
>>   ret = uclass_find_device_by_name(UCLASS_DISPLAY,
>>"sunxi_dw_hdmi", );
>>   if (!ret) {
>> diff --git a/drivers/video/sunxi/sunxi_lcd.c 
>> b/drivers/video/sunxi/sunxi_lcd.c
>> new file mode 100644
>> index 00..154eb5835e
>> --- /dev/null
>> +++ b/drivers/video/sunxi/sunxi_lcd.c
>> @@ -0,0 +1,142 @@
>> +/*
>> + * Allwinner LCD driver
>> + *
>> + * (C) Copyright 2017 Vasily Khoruzhick 
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +struct sunxi_lcd_priv {
>> + struct display_timing timing;
>> + int panel_bpp;
>> +};
>> +
>> +static void sunxi_lcdc_config_pinmux(void)
>> +{
>> + int pin;
>> + for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
>> + sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
>> + sunxi_gpio_set_drv(pin, 3);
>> + }
>> +}
>> +
>> +static int sunxi_lcd_enable(struct udevice *dev, int bpp,
>> +   const struct display_timing *edid)
>> +{
>> + struct sunxi_ccm_reg * const ccm =
>> +(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>> + struct sunxi_lcdc_reg * const lcdc =
>> +(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
>> + struct sunxi_lcd_priv *priv = dev_get_priv(dev);
>> + struct udevice *backlight;
>> + int clk_div, clk_double, ret;
>> +
>> + /* Reset off */
>> + setbits_le32(>ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
>> +
>> + /* Clock on */
>> + setbits_le32(>ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
>
> This has nothing to do with using a 

[U-Boot] DDR training code for Armada 38x

[Chris Packham]

Hi Stefan,

When you did the port from Marvell's source did you script any of the
tidy-up that you did along the way?

I'm running up a new board and with the upstream u-boot DDR training
occasionally fails. But with the Marvell bootloader it doesn't fail.
The initial port was done from TIP-1.29 but Marvell are now up to
TIP-1.55 so there is probably some difference that results in my board
working.

One difference I've spotted so far is that Marvell enable 2T timing
mode for all Armada 38x boards (the comment says "resolve low freq
instability"). But doing that doesn't magically make my board work.
I'm thinking I need to compare TIP-1.29 with TIP-1.55 to look for
other differences but obviously that's going to be hard given the
style changes. If you have any scripts (or even just a record of the
regexes) that you used would you be able to share them?

Thanks,
Chris
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[U-Boot] [PATCH 6/6] i.MX6Q: icore: Add imx6q board for icore/icore_rqs

[Jagan Teki]

From: Jagan Teki 

icore and icore_rqs boards are i.MX6QDL SOC type, so
create them as imx6q board and place the code as optimum
as possible.

Signed-off-by: Jagan Teki 
---
 arch/arm/mach-imx/mx6/Kconfig  | 24 +--
 board/engicam/icorem6_rqs/Kconfig  | 12 --
 board/engicam/icorem6_rqs/MAINTAINERS  |  9 
 board/engicam/icorem6_rqs/Makefile |  6 ---
 board/engicam/icorem6_rqs/README   | 30 -
 board/engicam/icorem6_rqs/icorem6_rqs.c| 49 --
 board/engicam/{icorem6 => imx6q}/Kconfig   |  2 +-
 board/engicam/{icorem6 => imx6q}/MAINTAINERS   |  8 +++-
 board/engicam/{icorem6 => imx6q}/Makefile  |  2 +-
 board/engicam/{icorem6 => imx6q}/README|  9 ++--
 board/engicam/{icorem6/icorem6.c => imx6q/imx6q.c} | 41 +-
 configs/imx6qdl_icore_rqs_defconfig|  2 +-
 12 files changed, 56 insertions(+), 138 deletions(-)
 delete mode 100644 board/engicam/icorem6_rqs/Kconfig
 delete mode 100644 board/engicam/icorem6_rqs/MAINTAINERS
 delete mode 100644 board/engicam/icorem6_rqs/Makefile
 delete mode 100644 board/engicam/icorem6_rqs/README
 delete mode 100644 board/engicam/icorem6_rqs/icorem6_rqs.c
 rename board/engicam/{icorem6 => imx6q}/Kconfig (87%)
 rename board/engicam/{icorem6 => imx6q}/MAINTAINERS (58%)
 rename board/engicam/{icorem6 => imx6q}/Makefile (80%)
 rename board/engicam/{icorem6 => imx6q}/README (71%)
 rename board/engicam/{icorem6/icorem6.c => imx6q/imx6q.c} (88%)

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 9f2b30c..412bac7 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -185,26 +185,7 @@ config TARGET_MX6QARM2
bool "mx6qarm2"
 
 config TARGET_MX6Q_ICORE
-   bool "Support Engicam i.Core"
-   select BOARD_LATE_INIT
-   select MX6QDL
-   select OF_CONTROL
-   select SPL_OF_LIBFDT
-   select DM
-   select DM_ETH
-   select DM_GPIO
-   select DM_I2C
-   select DM_MMC
-   select DM_THERMAL
-   select SUPPORT_SPL
-   select SPL_LOAD_FIT
-   select SPL_DM if SPL
-   select SPL_OF_CONTROL if SPL
-   select SPL_SEPARATE_BSS if SPL
-   select SPL_PINCTRL if SPL
-
-config TARGET_MX6Q_ICORE_RQS
-   bool "Support Engicam i.Core RQS"
+   bool "Support Engicam i.Core(RQS)"
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
@@ -439,8 +420,7 @@ source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/engicam/geam6ul/Kconfig"
-source "board/engicam/icorem6/Kconfig"
-source "board/engicam/icorem6_rqs/Kconfig"
+source "board/engicam/imx6q/Kconfig"
 source "board/engicam/isiotmx6ul/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6sabreauto/Kconfig"
diff --git a/board/engicam/icorem6_rqs/Kconfig 
b/board/engicam/icorem6_rqs/Kconfig
deleted file mode 100644
index 6dc3a07..000
--- a/board/engicam/icorem6_rqs/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MX6Q_ICORE_RQS
-
-config SYS_BOARD
-   default "icorem6_rqs"
-
-config SYS_VENDOR
-   default "engicam"
-
-config SYS_CONFIG_NAME
-   default "imx6-engicam"
-
-endif
diff --git a/board/engicam/icorem6_rqs/MAINTAINERS 
b/board/engicam/icorem6_rqs/MAINTAINERS
deleted file mode 100644
index 9a74265..000
--- a/board/engicam/icorem6_rqs/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-ICOREM6QDL_RQS BOARD
-M: Jagan Teki 
-S: Maintained
-F: board/engicam/icorem6_rqs
-F: include/configs/imx6-engicam.h
-F: configs/imx6qdl_icore_rqs_defconfig
-F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
-F: arch/arm/dts/imx6q-icore-rqs.dts
-F: arch/arm/dts/imx6dl-icore-rqs.dts
diff --git a/board/engicam/icorem6_rqs/Makefile 
b/board/engicam/icorem6_rqs/Makefile
deleted file mode 100644
index 2e3933c..000
--- a/board/engicam/icorem6_rqs/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright (C) 2016 Amarula Solutions B.V.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y  := icorem6_rqs.o
diff --git a/board/engicam/icorem6_rqs/README b/board/engicam/icorem6_rqs/README
deleted file mode 100644
index 97e978c..000
--- a/board/engicam/icorem6_rqs/README
+++ /dev/null
@@ -1,30 +0,0 @@
-How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter 
Kit:
---
-
-$ make mrproper
-
-- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual/Solo/DualLite:
-$ make imx6qdl_icore_rqs_defconfig
-
-- Build U-Boot
-$ make
-
-This will generate the SPL image called SPL and the u-boot-dtb.img.
-
-- Flash the SPL image into the micro SD card:
-
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
-
-- Flash the 

[U-Boot] [PATCH 2/6] imx6ul: geam6ul/isiot: Fix to MMC devices

[Jagan Teki]

From: Jagan Teki 

U-Boot proper is using DM_MMC so, enable CONFIG_BLK otherwise
find_mmc_device failed to detect MMC device.

Signed-off-by: Jagan Teki 
---
 configs/imx6ul_geam_mmc_defconfig   | 1 -
 configs/imx6ul_isiot_emmc_defconfig | 1 -
 configs/imx6ul_isiot_mmc_defconfig  | 1 -
 3 files changed, 3 deletions(-)

diff --git a/configs/imx6ul_geam_mmc_defconfig 
b/configs/imx6ul_geam_mmc_defconfig
index d329127..f663190 100644
--- a/configs/imx6ul_geam_mmc_defconfig
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -33,7 +33,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-# CONFIG_BLK is not set
 CONFIG_SYS_I2C_MXC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
diff --git a/configs/imx6ul_isiot_emmc_defconfig 
b/configs/imx6ul_isiot_emmc_defconfig
index be1f23d..7de9662 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -32,7 +32,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-# CONFIG_BLK is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
 CONFIG_FEC_MXC=y
diff --git a/configs/imx6ul_isiot_mmc_defconfig 
b/configs/imx6ul_isiot_mmc_defconfig
index 760bb2e..7e48f6a 100644
--- a/configs/imx6ul_isiot_mmc_defconfig
+++ b/configs/imx6ul_isiot_mmc_defconfig
@@ -33,7 +33,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-# CONFIG_BLK is not set
 CONFIG_SYS_I2C_MXC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
-- 
2.7.4

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[U-Boot] [PATCH 5/6] i.MX6Q: icore: Add SPL_OF_CONTROL support

[Jagan Teki]

From: Jagan Teki 

Add OF_CONTROL support for SPL code.

Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6qdl-icore-rqs.dtsi |   2 +
 arch/arm/dts/imx6qdl-icore.dtsi |   2 +
 arch/arm/dts/imx6qdl.dtsi   |   5 ++
 arch/arm/mach-imx/mx6/Kconfig   |   8 +++
 board/engicam/icorem6/icorem6.c |  75 ---
 board/engicam/icorem6_rqs/icorem6_rqs.c | 102 
 configs/imx6qdl_icore_mmc_defconfig |   1 +
 configs/imx6qdl_icore_rqs_defconfig |   1 +
 include/configs/imx6-engicam.h  |  22 +++
 9 files changed, 31 insertions(+), 187 deletions(-)

diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi 
b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
index 8b9d5b4..65cbf5a 100644
--- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
@@ -100,6 +100,7 @@
 };
 
  {
+   u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <_usdhc3>;
cd-gpios = < 1 GPIO_ACTIVE_LOW>;
@@ -165,6 +166,7 @@
};
 
pinctrl_usdhc3: usdhc3grp {
+   u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD0x17070
MX6QDL_PAD_SD3_CLK__SD3_CLK0x10070
diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
index a485c3e..06d9bc3 100644
--- a/arch/arm/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -118,6 +118,7 @@
 };
 
  {
+   u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <_usdhc1>;
cd-gpios = < 1 GPIO_ACTIVE_LOW>;
@@ -208,6 +209,7 @@
};
 
pinctrl_usdhc1: usdhc1grp {
+   u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD0x17070
MX6QDL_PAD_SD1_CLK__SD1_CLK0x10070
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index b13b0b2..e04b570 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -77,6 +77,7 @@
compatible = "simple-bus";
interrupt-parent = <>;
ranges;
+   u-boot,dm-spl;
 
dma_apbh: dma-apbh@0011 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@@ -225,6 +226,7 @@
#size-cells = <1>;
reg = <0x0200 0x10>;
ranges;
+   u-boot,dm-spl;
 
spba-bus@0200 {
compatible = "fsl,spba-bus", "simple-bus";
@@ -516,6 +518,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+   u-boot,dm-spl;
};
 
gpio2: gpio@020a {
@@ -805,6 +808,7 @@
iomuxc: iomuxc@020e {
compatible = "fsl,imx6dl-iomuxc", 
"fsl,imx6q-iomuxc";
reg = <0x020e 0x4000>;
+   u-boot,dm-spl;
};
 
ldb: ldb@020e0008 {
@@ -889,6 +893,7 @@
#size-cells = <1>;
reg = <0x0210 0x10>;
ranges;
+   u-boot,dm-spl;
 
crypto: caam@210 {
compatible = "fsl,sec-v4.0";
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 540f2b2..9f2b30c 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -198,6 +198,10 @@ config TARGET_MX6Q_ICORE
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
+   select SPL_DM if SPL
+   select SPL_OF_CONTROL if SPL
+   select SPL_SEPARATE_BSS if SPL
+   select SPL_PINCTRL if SPL
 
 config TARGET_MX6Q_ICORE_RQS
bool "Support Engicam i.Core RQS"
@@ -213,6 +217,10 @@ config TARGET_MX6Q_ICORE_RQS
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
+   select SPL_DM if SPL
+   select SPL_OF_CONTROL if SPL
+   select SPL_SEPARATE_BSS if SPL
+   select SPL_PINCTRL if SPL
 
 config TARGET_MX6SABREAUTO
bool "mx6sabreauto"
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index e173124..a967ccd 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -7,7 +7,6 @@
  */
 
 #include 
-#include 
 
 #include 
 #include 
@@ -191,77 +190,3 @@ void setup_display(void)
writel(reg, >gpr[3]);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
-
-#ifdef CONFIG_SPL_BUILD
-/* MMC board initialization is needed till adding DM support in SPL */
-#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
-#include 
-#include 

[U-Boot] [PATCH 4/6] i.MX6Q: icorem6: Move spl load fit to common/spl

[Jagan Teki]

From: Jagan Teki 

Move spl load fit code into common/spl

Signed-off-by: Jagan Teki 
---
 board/engicam/common/spl.c  | 16 
 board/engicam/icorem6/icorem6.c | 12 
 board/engicam/icorem6_rqs/icorem6_rqs.c | 12 
 3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c
index 6964c13..0a79ffd 100644
--- a/board/engicam/common/spl.c
+++ b/board/engicam/common/spl.c
@@ -39,6 +39,22 @@ static iomux_v3_cfg_t const uart_pads[] = {
 #endif
 };
 
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
+return 0;
+else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
+return 0;
+else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
+return 0;
+else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, 
"imx6dl-icore-rqs"))
+return 0;
+else
+return -1;
+}
+#endif
+
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index 59c085b..e173124 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -264,16 +264,4 @@ int board_mmc_init(bd_t *bis)
return 0;
 }
 #endif
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-   if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
-   return 0;
-   else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
-   return 0;
-   else
-   return -1;
-}
-#endif
 #endif /* CONFIG_SPL_BUILD */
diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c 
b/board/engicam/icorem6_rqs/icorem6_rqs.c
index edf9d086..599cea3 100644
--- a/board/engicam/icorem6_rqs/icorem6_rqs.c
+++ b/board/engicam/icorem6_rqs/icorem6_rqs.c
@@ -148,16 +148,4 @@ void board_boot_order(u32 *spl_boot_list)
 }
 #endif
 #endif
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-   if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
-   return 0;
-   else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, 
"imx6dl-icore-rqs"))
-   return 0;
-   else
-   return -1;
-}
-#endif
 #endif /* CONFIG_SPL_BUILD */
-- 
2.7.4

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[U-Boot] [PATCH 3/6] i.MX6: engicam: Move set_fdt_file to common

[Jagan Teki]

From: Jagan Teki 

setenv_fdt_file to common code and set dtb based on
CONFIG_DEFAULT_DEVICE_TREE and cpu_type.

Signed-off-by: Jagan Teki 
---
 board/engicam/common/board.c| 24 
 board/engicam/common/board.h|  1 -
 board/engicam/geam6ul/geam6ul.c |  6 --
 board/engicam/icorem6/icorem6.c |  8 
 board/engicam/icorem6_rqs/icorem6_rqs.c |  8 
 board/engicam/isiotmx6ul/isiotmx6ul.c   | 11 ---
 6 files changed, 24 insertions(+), 34 deletions(-)

diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c
index c7ec55f..f86fb2b 100644
--- a/board/engicam/common/board.c
+++ b/board/engicam/common/board.c
@@ -32,6 +32,30 @@ static void mmc_late_init(void)
 }
 #endif
 
+static void setenv_fdt_file(void)
+{
+   const char *cmp_dtb = CONFIG_DEFAULT_DEVICE_TREE;
+
+   if (!strcmp(cmp_dtb, "imx6q-icore")) {
+   if (is_mx6dq())
+   env_set("fdt_file", "imx6q-icore.dtb");
+   else if(is_mx6dl() || is_mx6solo())
+   env_set("fdt_file", "imx6dl-icore.dtb");
+   } else if (!strcmp(cmp_dtb, "imx6q-icore-rqs")) {
+   if (is_mx6dq())
+   env_set("fdt_file", "imx6q-icore-rqs.dtb");
+   else if(is_mx6dl() || is_mx6solo())
+   env_set("fdt_file", "imx6dl-icore-rqs.dtb");
+   } else if (!strcmp(cmp_dtb, "imx6ul-geam-kit"))
+   env_set("fdt_file", "imx6ul-geam-kit.dtb");
+   else if (!strcmp(cmp_dtb, "imx6ul-isiot-mmc"))
+   env_set("fdt_file", "imx6ul-isiot-mmc.dtb");
+   else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc"))
+   env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
+   else if (!strcmp(cmp_dtb, "imx6ul-isiot-nand"))
+   env_set("fdt_file", "imx6ul-isiot-nand.dtb");
+}
+
 int board_late_init(void)
 {
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
diff --git a/board/engicam/common/board.h b/board/engicam/common/board.h
index f364a23..c720b0b 100644
--- a/board/engicam/common/board.h
+++ b/board/engicam/common/board.h
@@ -6,7 +6,6 @@
 
 #ifndef _BOARD_H_
 #define _BOARD_H_
-void setenv_fdt_file(void);
 void setup_gpmi_nand(void);
 void setup_display(void);
 #endif /* _BOARD_H_ */
diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c
index ffd383a..15bd8b2 100644
--- a/board/engicam/geam6ul/geam6ul.c
+++ b/board/engicam/geam6ul/geam6ul.c
@@ -90,12 +90,6 @@ void setup_gpmi_nand(void)
 }
 #endif /* CONFIG_NAND_MXS */
 
-void setenv_fdt_file(void)
-{
-   if (is_mx6ul())
-   env_set("fdt_file", "imx6ul-geam-kit.dtb");
-}
-
 #ifdef CONFIG_SPL_BUILD
 /* MMC board initialization is needed till adding DM support in SPL */
 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index 3d4f713..59c085b 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -192,14 +192,6 @@ void setup_display(void)
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
-void setenv_fdt_file(void)
-{
-   if (is_mx6dq())
-   env_set("fdt_file", "imx6q-icore.dtb");
-   else if(is_mx6dl() || is_mx6solo())
-   env_set("fdt_file", "imx6dl-icore.dtb");
-}
-
 #ifdef CONFIG_SPL_BUILD
 /* MMC board initialization is needed till adding DM support in SPL */
 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c 
b/board/engicam/icorem6_rqs/icorem6_rqs.c
index 2a321dc..edf9d086 100644
--- a/board/engicam/icorem6_rqs/icorem6_rqs.c
+++ b/board/engicam/icorem6_rqs/icorem6_rqs.c
@@ -32,14 +32,6 @@ int board_mmc_get_env_dev(int devno)
 }
 #endif
 
-void setenv_fdt_file(void)
-{
-   if (is_mx6dq())
-   env_set("fdt_file", "imx6q-icore-rqs.dtb");
-   else if(is_mx6dl() || is_mx6solo())
-   env_set("fdt_file", "imx6dl-icore-rqs.dtb");
-}
-
 #ifdef CONFIG_SPL_BUILD
 #include 
 
diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c 
b/board/engicam/isiotmx6ul/isiotmx6ul.c
index fbf1724..9afa8e4 100644
--- a/board/engicam/isiotmx6ul/isiotmx6ul.c
+++ b/board/engicam/isiotmx6ul/isiotmx6ul.c
@@ -98,17 +98,6 @@ int board_mmc_get_env_dev(int devno)
 }
 #endif
 
-void setenv_fdt_file(void)
-{
-   if (is_mx6ul()) {
-#ifdef CONFIG_ENV_IS_IN_MMC
-   env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
-#else
-   env_set("fdt_file", "imx6ul-isiot-nand.dtb");
-#endif
-   }
-}
-
 #ifdef CONFIG_SPL_BUILD
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH 1/6] i.MX6: engicam: Fix MAINTAINERS/README

[Jagan Teki]

From: Jagan Teki 

- Update newly added include/configs file in MAINTAINERS
- Update newly added defconfig file in README

Signed-off-by: Jagan Teki 
---
 board/engicam/geam6ul/MAINTAINERS | 2 +-
 board/engicam/icorem6/MAINTAINERS | 2 +-
 board/engicam/icorem6/README  | 7 ++-
 board/engicam/icorem6_rqs/MAINTAINERS | 2 +-
 board/engicam/icorem6_rqs/README  | 7 ++-
 board/engicam/isiotmx6ul/MAINTAINERS  | 2 +-
 6 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/board/engicam/geam6ul/MAINTAINERS 
b/board/engicam/geam6ul/MAINTAINERS
index 1c31375..2b882d2 100644
--- a/board/engicam/geam6ul/MAINTAINERS
+++ b/board/engicam/geam6ul/MAINTAINERS
@@ -2,7 +2,7 @@ GEAM6UL BOARD
 M: Jagan Teki 
 S: Maintained
 F: board/engicam/geam6ul
-F: include/configs/imx6ul_geam.h
+F: include/configs/imx6-engicam.h
 F: configs/imx6ul_geam_mmc_defconfig
 F: configs/imx6ul_geam_nand_defconfig
 F: arch/arm/dts/imx6ul-geam-kit.dts
diff --git a/board/engicam/icorem6/MAINTAINERS 
b/board/engicam/icorem6/MAINTAINERS
index 26b4b56..a348bdd 100644
--- a/board/engicam/icorem6/MAINTAINERS
+++ b/board/engicam/icorem6/MAINTAINERS
@@ -2,7 +2,7 @@ ICOREM6QDL BOARD
 M: Jagan Teki 
 S: Maintained
 F: board/engicam/icorem6
-F: include/configs/imx6qdl_icore.h
+F: include/configs/imx6-engicam.h
 F: configs/imx6qdl_icore_mmc_defconfig
 F: configs/imx6qdl_icore_nand_defconfig
 F: arch/arm/dts/imx6qdl-icore.dtsi
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
index 6461c0a..3779e96 100644
--- a/board/engicam/icorem6/README
+++ b/board/engicam/icorem6/README
@@ -3,11 +3,8 @@ How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and 
Quad/Dual Starter Kit:
 
 $ make mrproper
 
-- Configure U-Boot for Engicam i.CoreM6 Quad/Dual:
-$ make imx6q_icore_mmc_defconfig
-
-- Configure U-Boot for Engicam i.CoreM6 Solo/DualLite:
-$ make imx6dl_icore_mmc_defconfig
+- Configure U-Boot for Engicam i.CoreM6 Quad/Dual/Solo/DualLite:
+$ make imx6qdl_icore_mmc_defconfig
 
 - Build U-Boot
 $ make
diff --git a/board/engicam/icorem6_rqs/MAINTAINERS 
b/board/engicam/icorem6_rqs/MAINTAINERS
index 6205acb..9a74265 100644
--- a/board/engicam/icorem6_rqs/MAINTAINERS
+++ b/board/engicam/icorem6_rqs/MAINTAINERS
@@ -2,7 +2,7 @@ ICOREM6QDL_RQS BOARD
 M: Jagan Teki 
 S: Maintained
 F: board/engicam/icorem6_rqs
-F: include/configs/imx6qdl_icore_rqs.h
+F: include/configs/imx6-engicam.h
 F: configs/imx6qdl_icore_rqs_defconfig
 F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
 F: arch/arm/dts/imx6q-icore-rqs.dts
diff --git a/board/engicam/icorem6_rqs/README b/board/engicam/icorem6_rqs/README
index ccce622..97e978c 100644
--- a/board/engicam/icorem6_rqs/README
+++ b/board/engicam/icorem6_rqs/README
@@ -3,11 +3,8 @@ How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and 
Quad/Dual Starter Ki
 
 $ make mrproper
 
-- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual:
-$ make imx6q_icore_rqs_mmc_defconfig
-
-- Configure U-Boot for Engicam i.CoreM6 RQS Solo/DualLite:
-$ make imx6dl_icore_rqs_mmc_defconfig
+- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual/Solo/DualLite:
+$ make imx6qdl_icore_rqs_defconfig
 
 - Build U-Boot
 $ make
diff --git a/board/engicam/isiotmx6ul/MAINTAINERS 
b/board/engicam/isiotmx6ul/MAINTAINERS
index c30cfe7..9b66c8d 100644
--- a/board/engicam/isiotmx6ul/MAINTAINERS
+++ b/board/engicam/isiotmx6ul/MAINTAINERS
@@ -2,7 +2,7 @@ ISIOTMX6UL BOARD
 M: Jagan Teki 
 S: Maintained
 F: board/engicam/isiotmx6ul
-F: include/configs/imx6ul_isiot.h
+F: include/configs/imx6-engicam.h
 F: configs/imx6ul_isiot_mmc_defconfig
 F: configs/imx6ul_isiot_emmc_defconfig
 F: configs/imx6ul_isiot_nand_defconfig
-- 
2.7.4

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[U-Boot] [PATCH 0/6] i.MX6Q: Add SPL_OF_CONTROL support

[Jagan Teki]

From: Jagan Teki 

This series add OF_CONTROL support for SPL on Engicam i.MX6QDL
boards, along with proper code optimzation changes.


Jagan Teki (6):
  i.MX6: engicam: Fix MAINTAINERS/README
  imx6ul: geam6ul/isiot: Fix to MMC devices
  i.MX6: engicam: Move set_fdt_file to common
  i.MX6Q: icorem6: Move spl load fit to common/spl
  i.MX6Q: icore: Add SPL_OF_CONTROL support
  i.MX6Q: icore: Add imx6q board for icore/icore_rqs

 arch/arm/dts/imx6qdl-icore-rqs.dtsi|   2 +
 arch/arm/dts/imx6qdl-icore.dtsi|   2 +
 arch/arm/dts/imx6qdl.dtsi  |   5 +
 arch/arm/mach-imx/mx6/Kconfig  |  24 +--
 board/engicam/common/board.c   |  24 +++
 board/engicam/common/board.h   |   1 -
 board/engicam/common/spl.c |  16 ++
 board/engicam/geam6ul/MAINTAINERS  |   2 +-
 board/engicam/geam6ul/geam6ul.c|   6 -
 board/engicam/icorem6/README   |  33 
 board/engicam/icorem6_rqs/Kconfig  |  12 --
 board/engicam/icorem6_rqs/MAINTAINERS  |   9 --
 board/engicam/icorem6_rqs/Makefile |   6 -
 board/engicam/icorem6_rqs/icorem6_rqs.c| 171 -
 board/engicam/{icorem6 => imx6q}/Kconfig   |   2 +-
 board/engicam/{icorem6 => imx6q}/MAINTAINERS   |  10 +-
 board/engicam/{icorem6 => imx6q}/Makefile  |   2 +-
 board/engicam/{icorem6_rqs => imx6q}/README|  12 +-
 board/engicam/{icorem6/icorem6.c => imx6q/imx6q.c} | 108 +++--
 board/engicam/isiotmx6ul/MAINTAINERS   |   2 +-
 board/engicam/isiotmx6ul/isiotmx6ul.c  |  11 --
 configs/imx6qdl_icore_mmc_defconfig|   1 +
 configs/imx6qdl_icore_rqs_defconfig|   3 +-
 configs/imx6ul_geam_mmc_defconfig  |   1 -
 configs/imx6ul_isiot_emmc_defconfig|   1 -
 configs/imx6ul_isiot_mmc_defconfig |   1 -
 include/configs/imx6-engicam.h |  22 +--
 27 files changed, 112 insertions(+), 377 deletions(-)
 delete mode 100644 board/engicam/icorem6/README
 delete mode 100644 board/engicam/icorem6_rqs/Kconfig
 delete mode 100644 board/engicam/icorem6_rqs/MAINTAINERS
 delete mode 100644 board/engicam/icorem6_rqs/Makefile
 delete mode 100644 board/engicam/icorem6_rqs/icorem6_rqs.c
 rename board/engicam/{icorem6 => imx6q}/Kconfig (87%)
 rename board/engicam/{icorem6 => imx6q}/MAINTAINERS (51%)
 rename board/engicam/{icorem6 => imx6q}/Makefile (80%)
 rename board/engicam/{icorem6_rqs => imx6q}/README (68%)
 rename board/engicam/{icorem6/icorem6.c => imx6q/imx6q.c} (73%)

-- 
2.7.4

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Re: [U-Boot] [PATCH v3] cmd: usb: add blk devices to ignore list in tree graph

[Suneel Garapati]

Hi Bin,

On Tue, Sep 19, 2017 at 12:32 AM, Bin Meng  wrote:
> Hi Suneel,
>
> On Tue, Sep 19, 2017 at 1:55 PM, Suneel Garapati  
> wrote:
>> add blk child devices to ignore list while displaying
>> usb tree graph, otherwise usb tree and info commands
>> may cause crash treating blk as usb device.
>>
>> Signed-off-by: Suneel Garapati 
>> ---
>>
>> Changes v3:
>>  - remove 'check on parent uclass' in description
>
> thanks for making the changes.
>
>> Changes v2:
>>  - remove check on parent uclass
>> Changes v1:
>>  - add separate check on blk uclass
>>  - modify description
>>  - add separate check on parent uclass as usb
>>
>>  cmd/usb.c | 11 ---
>>  1 file changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/cmd/usb.c b/cmd/usb.c
>> index d95bcf5..3889994 100644
>> --- a/cmd/usb.c
>> +++ b/cmd/usb.c
>> @@ -414,8 +414,12 @@ static void usb_show_tree_graph(struct usb_device *dev, 
>> char *pre)
>>
>> udev = dev_get_parent_priv(child);
>>
>> -   /* Ignore emulators, we only want real devices */
>> -   if (device_get_uclass_id(child) != UCLASS_USB_EMUL) {
>> +   /*
>> +* Ignore emulators and block child devices, we only want
>> +* real devices
>> +*/
>> +   if ((device_get_uclass_id(child) != UCLASS_USB_EMUL) &&
>> +   (device_get_uclass_id(child) != UCLASS_BLK)) {
>> usb_show_tree_graph(udev, pre);
>> pre[index] = 0;
>> }
>> @@ -605,7 +609,8 @@ static void usb_show_info(struct usb_device *udev)
>> for (device_find_first_child(udev->dev, );
>>  child;
>>  device_find_next_child()) {
>> -   if (device_active(child)) {
>> +   if (device_active(child) &&
>> +   (device_get_uclass_id(child) != UCLASS_BLK)) {
>> udev = dev_get_parent_priv(child);
>> usb_show_info(udev);
>> }
>> --
>
> My testing of 'usb info' looks OK, however 'usb tree' still has some
> issues below:
>
> => usb tree
> USB device tree:
>   1  Hub (5 Gb/s, 0mA)
>   |  U-Boot XHCI Host Controller
>   |
>   +-2  Hub (5 Gb/s, 0mA)
>   | |  GenesysLogic USB3.0 Hub
>   | |
>   | +-5  Vendor specific (5 Gb/s, 36mA)
>   |  Realtek USB 10/100/1000 LAN 00E04C680977
>   |
Leaving block devices, why the extra print here for lan port?

>   +-3  Hub (480 Mb/s, 100mA)
>   | |  GenesysLogic USB2.0 Hub
>   | |
And here?

>   | +-6  Mass Storage (480 Mb/s, 98mA)
>   | | |  USBest Technology USB Mass Storage Device 10c452b7c0
>   | | |
>
> As you see, we just don't print out the BLK device, but we still print
> out the | here.
I believe if the extra print for other devices is correct, then this
tree is fine.
Also, I believe this is not related to the fix this patch aims at.
Let me know if otherwise.

Regards,
Suneel
>
>   | +-7  Human Interface (1.5 Mb/s, 70mA)
>   |  Dell Dell USB Keyboard
>   |
>   +-4  Mass Storage (480 Mb/s, 300mA)
> |  JetFlash Mass Storage Device 16Q6ZPH20GF3E8UQ
> |
>
> And here.
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 1/1] scripts/checkpatch: add missing spelling.txt

[Dan Murphy]

On 09/19/2017 12:28 PM, Heinrich Schuchardt wrote:
> Checkpatch can use two dictionaries for finding typos:
> * scripts/spelling.txt
> * /usr/share/codespell/dictionary.txt
>   which comes with package codespell and is selected by parameter
>   --codespell
> 
> If the file scripts/spelling.txt is missing, a warning is shown.
> 
> Add the spelling.txt file from the Linux kernel 4.13 source.
> 
> We can later add our own typo corrections.
> 
> Signed-off-by: Heinrich Schuchardt 

Acked-by: Dan Murphy 

> ---
>  scripts/spelling.txt | 1217 
> ++
>  1 file changed, 1217 insertions(+)
>  create mode 100644 scripts/spelling.txt
> 
> diff --git a/scripts/spelling.txt b/scripts/spelling.txt
> new file mode 100644
> index 00..400ef35169
> --- /dev/null
> +++ b/scripts/spelling.txt
> @@ -0,0 +1,1217 @@
> +# Originally from Debian's Lintian tool. Various false positives have been
> +# removed, and various additions have been made as they've been discovered
> +# in the kernel source.
> +#
> +# License: GPLv2
> +#
> +# The format of each line is:
> +# mistake||correction
> +#
> +abandonning||abandoning
> +abigious||ambiguous
> +abitrate||arbitrate
> +abov||above
> +abreviated||abbreviated
> +absense||absence
> +absolut||absolute
> +absoulte||absolute
> +acccess||access
> +acceess||access
> +acceleratoin||acceleration
> +accelleration||acceleration
> +accesing||accessing
> +accesnt||accent
> +accessable||accessible
> +accesss||access
> +accidentaly||accidentally
> +accidentually||accidentally
> +accoding||according
> +accomodate||accommodate
> +accomodates||accommodates
> +accordign||according
> +accoring||according
> +accout||account
> +accquire||acquire
> +accquired||acquired
> +accross||across
> +acessable||accessible
> +acess||access
> +achitecture||architecture
> +acient||ancient
> +acitions||actions
> +acitve||active
> +acknowldegement||acknowledgment
> +acknowledgement||acknowledgment
> +ackowledge||acknowledge
> +ackowledged||acknowledged
> +acording||according
> +activete||activate
> +actived||activated
> +actualy||actually
> +acumulating||accumulating
> +acumulator||accumulator
> +adapater||adapter
> +addional||additional
> +additionaly||additionally
> +addres||address
> +adddress||address
> +addreses||addresses
> +addresss||address
> +aditional||additional
> +aditionally||additionally
> +aditionaly||additionally
> +adminstrative||administrative
> +adress||address
> +adresses||addresses
> +adviced||advised
> +afecting||affecting
> +againt||against
> +agaist||against
> +albumns||albums
> +alegorical||allegorical
> +algined||aligned
> +algorith||algorithm
> +algorithmical||algorithmically
> +algoritm||algorithm
> +algoritms||algorithms
> +algorrithm||algorithm
> +algorritm||algorithm
> +aligment||alignment
> +alignement||alignment
> +allign||align
> +alligned||aligned
> +allocatote||allocate
> +allocatrd||allocated
> +allocte||allocate
> +allpication||application
> +alocate||allocate
> +alogirhtms||algorithms
> +alogrithm||algorithm
> +alot||a lot
> +alow||allow
> +alows||allows
> +altough||although
> +alue||value
> +ambigious||ambiguous
> +amoung||among
> +amout||amount
> +an union||a union
> +an user||a user
> +an userspace||a userspace
> +an one||a one
> +analysator||analyzer
> +ang||and
> +anniversery||anniversary
> +annoucement||announcement
> +anomolies||anomalies
> +anomoly||anomaly
> +anway||anyway
> +aplication||application
> +appearence||appearance
> +applicaion||application
> +appliction||application
> +applictions||applications
> +applys||applies
> +appplications||applications
> +appropiate||appropriate
> +appropriatly||appropriately
> +approriate||appropriate
> +approriately||appropriately
> +apropriate||appropriate
> +aquainted||acquainted
> +aquired||acquired
> +aquisition||acquisition
> +arbitary||arbitrary
> +architechture||architecture
> +arguement||argument
> +arguements||arguments
> +aritmetic||arithmetic
> +arne't||aren't
> +arraival||arrival
> +artifical||artificial
> +artillary||artillery
> +asign||assign
> +asser||assert
> +assertation||assertion
> +assiged||assigned
> +assigment||assignment
> +assigments||assignments
> +assistent||assistant
> +assocation||association
> +associcated||associated
> +assotiated||associated
> +assum||assume
> +assumtpion||assumption
> +asuming||assuming
> +asycronous||asynchronous
> +asynchnous||asynchronous
> +atomatically||automatically
> +atomicly||atomically
> +atempt||attempt
> +attachement||attachment
> +attched||attached
> +attemps||attempts
> +attemping||attempting
> +attruibutes||attributes
> +authentification||authentication
> +automaticaly||automatically
> +automaticly||automatically
> +automatize||automate
> +automatized||automated
> +automatizes||automates
> +autonymous||autonomous
> +auxillary||auxiliary
> +auxilliary||auxiliary
> +avaiable||available
> +avaible||available
> +availabe||available
> +availabled||available
> +availablity||availability
> 

[U-Boot] [PATCH] mx53loco: Let CONFIG_DISPLAY_CPUINFO be selected

[Fabio Estevam]

With CONFIG_DISPLAY_CPUINFO=y we get a "Reset cause" line, which
brings important information of the reboot cause.

Signed-off-by: Fabio Estevam 
---
 configs/mx53loco_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index b431c89..c89274d 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -8,7 +8,6 @@ CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
-- 
2.7.4

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[U-Boot] [PATCH v2 1/1] x86: provide CONFIG_BUILD_ROM

[Heinrich Schuchardt]

Up to now we depended on an exported variable to build u-boot.rom.
What we build should be specified by the configuration file.

With this patch the export variable is deprecated and replaced by the
Kconfig option CONFIG_BUILD_ROM. To make the change as smooth as
possible 'export BUILD_ROM' is still usable but removed from the
documentation.

This option depends on CONFIG_X86 and is selected in
qemu-x86_defconfig and qemu-x86_64_defconfig.

Cc: Bin Meng 
Signed-off-by: Heinrich Schuchardt 
---
v2
Enable CONFIG_BUILD_ROM for qemu-x86_64_defconfig
as suggested by Bin.
Fix typos.
Remove 'default n'
---
 Kconfig   | 10 ++
 Makefile  |  2 +-
 configs/qemu-x86_64_defconfig |  1 +
 configs/qemu-x86_defconfig|  1 +
 doc/README.x86|  2 +-
 5 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/Kconfig b/Kconfig
index 238fa3e1ed..989d81c04c 100644
--- a/Kconfig
+++ b/Kconfig
@@ -158,6 +158,15 @@ config PHYS_64BIT
  This can be used not only for 64bit SoCs, but also for
  large physical address extention on 32bit SoCs.
 
+config BUILD_ROM
+   bool "Build U-Boot as BIOS replacement"
+   depends on X86
+   help
+ This option allows to build a ROM version of U-Boot.
+ The build process generally requires several binary blobs
+ which are not shipped in the U-Boot source tree.
+ Please, see doc/README.x86 for details.
+
 endmenu# General setup
 
 menu "Boot images"
diff --git a/Makefile b/Makefile
index 8250b3409a..50fe0003f5 100644
--- a/Makefile
+++ b/Makefile
@@ -796,7 +796,7 @@ ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
 ALL-$(CONFIG_EFI_APP) += u-boot-app.efi
 ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
 
-ifneq ($(BUILD_ROM),)
+ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
 ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
 endif
 
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 67e9a45fbc..a6a14a8de9 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -1,4 +1,5 @@
 CONFIG_X86=y
+CONFIG_BUILD_ROM=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x1000
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 7ce97ff091..346abf621d 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -1,4 +1,5 @@
 CONFIG_X86=y
+CONFIG_BUILD_ROM=y
 CONFIG_MAX_CPUS=2
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
 CONFIG_SMP=y
diff --git a/doc/README.x86 b/doc/README.x86
index c96a22cb08..226c9af281 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -82,7 +82,7 @@ shipped in the U-Boot source tree. Due to this reason, the 
u-boot.rom build is
 not turned on by default in the U-Boot source tree. Firstly, you need turn it
 on by enabling the ROM build:
 
-$ export BUILD_ROM=y
+CONFIG_BUILD_ROM=y
 
 This tells the Makefile to build u-boot.rom as a target.
 
-- 
2.11.0

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[U-Boot] [PATCH 1/1] scripts/checkpatch: add missing spelling.txt

[Heinrich Schuchardt]

Checkpatch can use two dictionaries for finding typos:
* scripts/spelling.txt
* /usr/share/codespell/dictionary.txt
  which comes with package codespell and is selected by parameter
  --codespell

If the file scripts/spelling.txt is missing, a warning is shown.

Add the spelling.txt file from the Linux kernel 4.13 source.

We can later add our own typo corrections.

Signed-off-by: Heinrich Schuchardt 
---
 scripts/spelling.txt | 1217 ++
 1 file changed, 1217 insertions(+)
 create mode 100644 scripts/spelling.txt

diff --git a/scripts/spelling.txt b/scripts/spelling.txt
new file mode 100644
index 00..400ef35169
--- /dev/null
+++ b/scripts/spelling.txt
@@ -0,0 +1,1217 @@
+# Originally from Debian's Lintian tool. Various false positives have been
+# removed, and various additions have been made as they've been discovered
+# in the kernel source.
+#
+# License: GPLv2
+#
+# The format of each line is:
+# mistake||correction
+#
+abandonning||abandoning
+abigious||ambiguous
+abitrate||arbitrate
+abov||above
+abreviated||abbreviated
+absense||absence
+absolut||absolute
+absoulte||absolute
+acccess||access
+acceess||access
+acceleratoin||acceleration
+accelleration||acceleration
+accesing||accessing
+accesnt||accent
+accessable||accessible
+accesss||access
+accidentaly||accidentally
+accidentually||accidentally
+accoding||according
+accomodate||accommodate
+accomodates||accommodates
+accordign||according
+accoring||according
+accout||account
+accquire||acquire
+accquired||acquired
+accross||across
+acessable||accessible
+acess||access
+achitecture||architecture
+acient||ancient
+acitions||actions
+acitve||active
+acknowldegement||acknowledgment
+acknowledgement||acknowledgment
+ackowledge||acknowledge
+ackowledged||acknowledged
+acording||according
+activete||activate
+actived||activated
+actualy||actually
+acumulating||accumulating
+acumulator||accumulator
+adapater||adapter
+addional||additional
+additionaly||additionally
+addres||address
+adddress||address
+addreses||addresses
+addresss||address
+aditional||additional
+aditionally||additionally
+aditionaly||additionally
+adminstrative||administrative
+adress||address
+adresses||addresses
+adviced||advised
+afecting||affecting
+againt||against
+agaist||against
+albumns||albums
+alegorical||allegorical
+algined||aligned
+algorith||algorithm
+algorithmical||algorithmically
+algoritm||algorithm
+algoritms||algorithms
+algorrithm||algorithm
+algorritm||algorithm
+aligment||alignment
+alignement||alignment
+allign||align
+alligned||aligned
+allocatote||allocate
+allocatrd||allocated
+allocte||allocate
+allpication||application
+alocate||allocate
+alogirhtms||algorithms
+alogrithm||algorithm
+alot||a lot
+alow||allow
+alows||allows
+altough||although
+alue||value
+ambigious||ambiguous
+amoung||among
+amout||amount
+an union||a union
+an user||a user
+an userspace||a userspace
+an one||a one
+analysator||analyzer
+ang||and
+anniversery||anniversary
+annoucement||announcement
+anomolies||anomalies
+anomoly||anomaly
+anway||anyway
+aplication||application
+appearence||appearance
+applicaion||application
+appliction||application
+applictions||applications
+applys||applies
+appplications||applications
+appropiate||appropriate
+appropriatly||appropriately
+approriate||appropriate
+approriately||appropriately
+apropriate||appropriate
+aquainted||acquainted
+aquired||acquired
+aquisition||acquisition
+arbitary||arbitrary
+architechture||architecture
+arguement||argument
+arguements||arguments
+aritmetic||arithmetic
+arne't||aren't
+arraival||arrival
+artifical||artificial
+artillary||artillery
+asign||assign
+asser||assert
+assertation||assertion
+assiged||assigned
+assigment||assignment
+assigments||assignments
+assistent||assistant
+assocation||association
+associcated||associated
+assotiated||associated
+assum||assume
+assumtpion||assumption
+asuming||assuming
+asycronous||asynchronous
+asynchnous||asynchronous
+atomatically||automatically
+atomicly||atomically
+atempt||attempt
+attachement||attachment
+attched||attached
+attemps||attempts
+attemping||attempting
+attruibutes||attributes
+authentification||authentication
+automaticaly||automatically
+automaticly||automatically
+automatize||automate
+automatized||automated
+automatizes||automates
+autonymous||autonomous
+auxillary||auxiliary
+auxilliary||auxiliary
+avaiable||available
+avaible||available
+availabe||available
+availabled||available
+availablity||availability
+availale||available
+availavility||availability
+availble||available
+availiable||available
+avalable||available
+avaliable||available
+aysnc||async
+backgroud||background
+backword||backward
+backwords||backwards
+bahavior||behavior
+bakup||backup
+baloon||balloon
+baloons||balloons
+bandwith||bandwidth
+banlance||balance
+batery||battery
+beacuse||because
+becasue||because
+becomming||becoming
+becuase||because
+beeing||being
+befor||before
+begining||beginning
+beter||better

Re: [U-Boot] [PATCH] net: ravb: Add PHY reset GPIO support

[Joe Hershberger]

On Fri, Sep 15, 2017 at 2:11 PM, Marek Vasut  wrote:
> Add support for obtaining PHY reset GPIO from DT and toggling it
> before configuring the PHY to put the PHY into defined state.
>
> Signed-off-by: Marek Vasut 
> Cc: Nobuhiro Iwamatsu 
> Cc: Joe Hershberger 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 1/1] test/py: provide example scripts for integrating qemu

[Stephen Warren]

On 09/18/2017 03:37 PM, Heinrich Schuchardt wrote:

On 09/18/2017 11:28 PM, Stephen Warren wrote:

On 09/18/2017 01:55 PM, Heinrich Schuchardt wrote:

On 09/18/2017 08:27 PM, Stephen Warren wrote:

On 09/17/2017 01:32 PM, Heinrich Schuchardt wrote:

The necessary parameters for running Python tests on qemu are
tediouus to find.



Empty file
__init__.py


__init__.py isn't the correct filename.


We need 2 *.py files.

__init__.py to make the directory a package directory and the board
file. My example is not for the sandbox but for qemu-x86_defconfig.


You don't need __init__.py. The directory doesn't need to be a Python 
package. You just need u_boot_boardenv_xxx.py in a directory, and to add 
that directory into $PYTHONPATH.

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[U-Boot] [PATCH] rockchip: pinctrl: rk3368: add pinctrl for SDMMC0

[Philipp Tomsich]

Apparently, our earlier assumption that the BROM will always set up
the iomux for SDcard communication does not always hold true: when
booting U-Boot from the on-module (on the RK3368-uQ7) eMMC, the SDcard
pins are not set up and need to be configured by the pinctrl driver to
allow SD card access.

This change implements support for setting up the SDMMC pins in
pinctrl for the RK3368.

Reported-by: Klaus Goger 
Signed-off-by: Philipp Tomsich 
---

 drivers/pinctrl/rockchip/pinctrl_rk3368.c | 39 +++
 1 file changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index b1f5704..25249e3 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -208,6 +208,29 @@ enum {
GPIO2A0_FLASH_CSN0  = (1 << GPIO2A0_SHIFT),
 };
 
+/*GRF_GPIO2B_IOMUX*/
+enum {
+   GPIO2B3_SHIFT   = 6,
+   GPIO2B3_MASK= GENMASK(GPIO2B3_SHIFT + 1, GPIO2B3_SHIFT),
+   GPIO2B3_GPIO= 0,
+   GPIO2B3_SDMMC0_DTECTN   = (1 << GPIO2B3_SHIFT),
+
+   GPIO2B2_SHIFT   = 4,
+   GPIO2B2_MASK= GENMASK(GPIO2B2_SHIFT + 1, GPIO2B2_SHIFT),
+   GPIO2B2_GPIO= 0,
+   GPIO2B2_SDMMC0_CMD  = (1 << GPIO2B2_SHIFT),
+
+   GPIO2B1_SHIFT   = 2,
+   GPIO2B1_MASK= GENMASK(GPIO2B1_SHIFT + 1, GPIO2B1_SHIFT),
+   GPIO2B1_GPIO= 0,
+   GPIO2B1_SDMMC0_CLKOUT   = (1 << GPIO2B1_SHIFT),
+
+   GPIO2B0_SHIFT   = 0,
+   GPIO2B0_MASK= GENMASK(GPIO2B0_SHIFT + 1, GPIO2B0_SHIFT),
+   GPIO2B0_GPIO= 0,
+   GPIO2B0_SDMMC0_D3   = (1 << GPIO2B0_SHIFT),
+};
+
 /*GRF_GPIO2D_IOMUX*/
 enum {
GPIO2D7_SHIFT   = 14,
@@ -580,11 +603,17 @@ static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf 
*grf, int mmc_id)
 GPIO2A4_EMMC_CLKOUT);
break;
case PERIPH_ID_SDCARD:
-   /*
-* We assume that the BROM has already set this up
-* correctly for us and that there's nothing to do
-* here.
-*/
+   debug("mmc id = %d setting registers!\n", mmc_id);
+   rk_clrsetreg(>gpio2a_iomux,
+GPIO2A5_MASK | GPIO2A7_MASK |
+GPIO2A7_MASK,
+GPIO2A5_SDMMC0_D0 | GPIO2A6_SDMMC0_D1 |
+GPIO2A7_SDMMC0_D2);
+   rk_clrsetreg(>gpio2b_iomux,
+GPIO2B0_MASK | GPIO2B1_MASK |
+GPIO2B2_MASK | GPIO2B3_MASK,
+GPIO2B0_SDMMC0_D3 | GPIO2B1_SDMMC0_CLKOUT |
+GPIO2B2_SDMMC0_CMD | GPIO2B3_SDMMC0_DTECTN);
break;
default:
debug("mmc id = %d iomux error!\n", mmc_id);
-- 
2.1.4

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Re: [U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[See, Chin Liang]

On Tue, 2017-09-19 at 11:51 +0200, Marek Vasut wrote:
> On 09/19/2017 11:22 AM, chin.liang@intel.com wrote:
> > 
> > From: Chin Liang See 
> > 
> > Add the base address map for Statix10 SoC
> > 
> > Signed-off-by: Chin Liang See 
> Add only the stuff which is not obtainable from DT please.
> 

Sure, let me remove the SDMMC, EMAC and QSPI since they are extracted
from DT today

Thanks
Chin Liang

> > 
> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58
> > ++
> >  1 file changed, 58 insertions(+)
> >  create mode 100644 arch/arm/mach-
> > socfpga/include/mach/base_addr_s10.h
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > new file mode 100644
> > index 000..feb1881
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > @@ -0,0 +1,58 @@
> > +/*
> > + * Copyright (C) 2016-2017 Intel Corporation 
> > + *
> > + * SPDX-License-Identifier:GPL-2.0
> > + */
> > +
> > +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> > +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> > +
> > +#define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xf8000400
> > +#define SOCFPGA_HMC_MMR_IO48_ADDRESS   0xf801
> > +#define SOCFPGA_SDR_ADDRESS0xf8011000
> > +#define SOCFPGA_SMMU_ADDRESS   0xfa00
> > +#define SOCFPGA_EMAC0_ADDRESS  0xff80
> > +#define SOCFPGA_EMAC1_ADDRESS  0xff802000
> > +#define SOCFPGA_EMAC2_ADDRESS  0xff804000
> > +#define SOCFPGA_SDMMC_ADDRESS  0xff808000
> > +#define SOCFPGA_QSPIREGS_ADDRESS   0xff8d2000
> > +#define SOCFPGA_QSPIDATA_ADDRESS   0xff90
> > +#define SOCFPGA_MAILBOX_ADDRESS0xffA3
> > +#define SOCFPGA_USB0_ADDRESS   0xffb0
> > +#define SOCFPGA_USB1_ADDRESS   0xffb4
> > +#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
> > +#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
> > +#define SOCFPGA_UART0_ADDRESS  0xffc02000
> > +#define SOCFPGA_UART1_ADDRESS  0xffc02100
> > +#define SOCFPGA_I2C0_ADDRESS   0xffc02800
> > +#define SOCFPGA_I2C1_ADDRESS   0xffc02900
> > +#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
> > +#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
> > +#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
> > +#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
> > +#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
> > +#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
> > +#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
> > +#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
> > +#define SOCFPGA_SYSTIMER1_ADDRESS  0xffd00100
> > +#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
> > +#define SOCFPGA_L4WD1_ADDRESS  0xffd00300
> > +#define SOCFPGA_L4WD2_ADDRESS  0xffd00400
> > +#define SOCFPGA_L4WD3_ADDRESS  0xffd00500
> > +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
> > +#define SOCFPGA_GTIMER_NSEC_ADDRESS0xffd02000
> > +#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
> > +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
> > +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
> > +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
> > +#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
> > +#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
> > +#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
> > +#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
> > +#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
> > +#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
> > +#define SOCFPGA_OCRAM_ADDRESS  0xffe0
> > +#define GICD_BASE  0xfffc1000
> > +#define GICC_BASE  0xfffc2000
> > +
> > +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
> > 
> 
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Re: [U-Boot] [PATCH v2 0/5] rockchip: back-to-bootrom: replace assembly-implementation with C-code

[Dr. Philipp Tomsich]

Andy,

> On 19 Sep 2017, at 11:10, Dr. Philipp Tomsich 
>  wrote:
> 
> Andy,
> 
>> On 19 Sep 2017, at 09:19, Andy Yan  wrote:
>> 
>> Hi Philipp:
>> 
>> 
>> On 2017年09月19日 10:06, Andy Yan wrote:
>>> Hi Philipp:
>>> 
>>> 
>>> On 2017年09月19日 02:18, Philipp Tomsich wrote:
 Recent discussions confirmed (what the code always assumed): the
 Rockchip BROM always enters U-Boot with the stack-pointer valid
 (i.e. the U-Boot startup code is running off the BROM stack).
 
 We can thus replace the back-to-bootrom code (i.e. both the
 save_boot_params and back_to_bootrom implementations) using C-code
 based on setjmp/longjmp.  The new implementation is already structured
 to allow an easy drop-in of Andy's changes to enter download-mode when
 returning to the BROM.
 
 This entails one minor tweak to asm/system.h, which only exported
 the save_boot_params_ret prototype for ARMv7, but not for AArch64.
 
 For v2, we force bootrom.o to alway be emitted as A32 (not T32), so we
 can safely call save_boot_params_ret().
>>> 
>>>   This still have a problem, because the setjmp  implementation for ARM32 
>>> platform  has humb code when CONFIG_SYS_THUMB_BUILD is
>>> enabled, this is a default setting for most ARMv7 boards.
>>> #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
>>> ".align 2\n"
>>> "adr r0, jmp_target\n"
>>> "add r0, r0, $1\n"  // r0 stored the jump target address and with bit[0] = 
>>> 1, this will trigger a thumb switch in longjmp with code "bx r0"
>>> #endif
>>> 
>>> When I force the setjmp code go arm code path, I can back to bootrom 
>>> successfully, But I got a data abort exception in later. it seems it 
>>> happens when bootrom finished the uboot code
>>> copy, when jump to sdram, I need a further debug.
>> 
>> I found that r9 also need to be preserved, it seems that it hold the sdram 
>> base.
> 
> Thanks for testing and debugging: this is invaluable support, as I only have 
> AArch64 boards to test.
> 
> The r9 issue will be easy enough to resolve.
> However, it looks like I will need more work on setjmp/longjmp to make this 
> safe both for T32 and A32.
> Plus: I need to figure out why this didn’t show in my disassembly (I don’t 
> remember whether it was a rk3188 or rk3288 board I looked at).

I had a quick look and things may be quicker to resolve than I thought.
Before I create a new version, I was wondering what the requirements on the 
BROM end are:
Without changes to setjmp/longjmp, I can currently preserve "r4-r11, lr, sp” 
(i.e "r1-r3, ip" will be clobbered).
If the BROM need any of these additional registers preserved (i.e. 
r1,r2,r3,ip): let me know and I will change setjmp/longjmp to be more 
conservative.

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Re: [U-Boot] [PATCH] dm: core: Round up size when allocating so that it is cache line aligned

[Faiz Abbas]

Hi Bin,

On Tuesday 19 September 2017 05:42 PM, Bin Meng wrote:
> Hi Faiz,
> 
> On Tue, Sep 19, 2017 at 7:23 PM, Faiz Abbas  wrote:
>> The size variable may not be always be a mulitple of
>> ARCH_DMA_MINALIGN and using it to flush cache leads to cache
>> misaligned warnings.
>>
>> Therefore, round up the size to a multiple of ARCH_DMA_MINLAIGN
>> when allocating private data.
>>
>> Signed-off-by: Faiz Abbas 
>> ---
>>  drivers/core/device.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
> 
> Isn't DM_FLAG_ALLOC_PRIV_DMA sufficient?

The check_cache_range function checks both the beginning and the
end of the range given to it for cache alignment.
DM_FLAG_ALLOC_PRIV_DMA aligns only the base address but the end
address decided by size need not be at a multiple of ARCH_DMA_MINALIGN.

Thanks,
Faiz

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Re: [U-Boot] [PATCH] imx6: disable clock command and print_cpuinfo code in SPL

[Anatolij Gustschin]

Hi Stefano,

On Tue, 19 Sep 2017 09:54:30 +0200
Stefano Babic sba...@denx.de wrote:
...
> This patch has some side-effects and breaks some boards. Even if the
> changes are correct, some boards (wandboard, icore are examples) don't
> disable IPU support in SPL. Even if this is useless and generates only a
> bigger footprint.
> 
> In fact, I get :
> 
>arm:  +   wandboard
> +board/wandboard/built-in.o: In function `setup_display':
> +board/wandboard/wandboard.c:355: undefined reference to `enable_ipu_clock'
> +make[2]: *** [spl/u-boot-spl] Error 1
> +make[1]: *** [spl/u-boot-spl] Error 2
> +make: *** [sub-make] Error 2
> 
> 
> Reason is clear: boards have in SPL a setup_display() that calls
> enable_ipu_clock. But it makes no sense to have IPU support in SPL.
> 
> We can fix with a follow-up patch, but this is bad for bisecting. The
> other option is to fix here and disable IPU in spl for the affected
> boards. What you think ?

Sorry for the build breakage, I didn't test with a full imx6 build.
Yes, we shouldn't break bisection. I'll fix and resubmit. Thanks!

--
Anatolij
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Re: [U-Boot] [PATCH] dm: core: Round up size when allocating so that it is cache line aligned

[Bin Meng]

Hi Faiz,

On Tue, Sep 19, 2017 at 7:23 PM, Faiz Abbas  wrote:
> The size variable may not be always be a mulitple of
> ARCH_DMA_MINALIGN and using it to flush cache leads to cache
> misaligned warnings.
>
> Therefore, round up the size to a multiple of ARCH_DMA_MINLAIGN
> when allocating private data.
>
> Signed-off-by: Faiz Abbas 
> ---
>  drivers/core/device.c | 1 +
>  1 file changed, 1 insertion(+)
>

Isn't DM_FLAG_ALLOC_PRIV_DMA sufficient?

Regards,
Bin
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Re: [U-Boot] [U-Boot,v2,00/14] Add rockchip SARADC support

[Dr. Philipp Tomsich]

David,

> On 19 Sep 2017, at 12:53, David Wu  wrote:
> 
> The SARADC is used for adc keys and charging detect at uboot
> loader. Except for the rk3036 and rk3228 Socs, the others
> support the SARADC IP.

I am hoping to apply this series later this week (and include in a PR for
on next Monday), but some of these patches still have an empty commit
message.

Could you fix the empty commit messages and send a v3?
Also: it would be very helpful, if you sent these out using patman and
used the ‘Series-changes’ tag, so I know what changed in each version.

See tools/patman/README for info...

Thanks,
Philipp.

> David Wu (14):
>  adc: Add driver for Rockchip SARADC
>  configs: rockchip: Enable the ROCKCHIP_SARADC config
>  clk: rockchip: Add rv1108 SARADC clock support
>  clk: rockchip: Add SARADC clock support for rk3288
>  clk: rockchip: Add rk3328 SARADC clock support
>  clk: rockchip: Add rk3368 SARADC clock support
>  clk: rockchip: Add rk3399 SARADC clock support
>  arm: dts: rv1108: Add Saradc node at dtsi level
>  arm: dts: Enable SARADC for rv1108-evb
>  arm: dts: Enable SARADC for rk3288-popmetal
>  arm: dts: Enable SARADC for rk3328-evb
>  arm: dts: Enable SARADC for rk3368-px5-evb
>  arm: dts: Enable SARADC for rk3368-sheep
>  arm: dts: Enable SARADC for rk3399-evb
> 
> arch/arm/dts/rk3288-popmetal.dtsi   |   4 +
> arch/arm/dts/rk3328-evb.dts |   4 +
> arch/arm/dts/rk3368-px5-evb.dts |   4 +
> arch/arm/dts/rk3368-sheep.dts   |   4 +
> arch/arm/dts/rk3399-evb.dts |   4 +
> arch/arm/dts/rv1108-evb.dts |   4 +
> arch/arm/dts/rv1108.dtsi|  11 ++
> arch/arm/include/asm/arch-rockchip/cru_rk3368.h |   5 +
> arch/arm/include/asm/arch-rockchip/cru_rv1108.h |   5 +
> configs/chromebit_mickey_defconfig  |   2 +
> configs/chromebook_jerry_defconfig  |   2 +
> configs/chromebook_minnie_defconfig |   2 +
> configs/evb-px5_defconfig   |   2 +
> configs/evb-rk3288_defconfig|   2 +
> configs/evb-rk3328_defconfig|   2 +
> configs/evb-rk3399_defconfig|   2 +
> configs/evb-rv1108_defconfig|   2 +
> configs/fennec-rk3288_defconfig |   2 +
> configs/firefly-rk3288_defconfig|   2 +
> configs/firefly-rk3399_defconfig|   2 +
> configs/geekbox_defconfig   |   2 +
> configs/lion-rk3368_defconfig   |   2 +
> configs/miqi-rk3288_defconfig   |   2 +
> configs/phycore-rk3288_defconfig|   2 +
> configs/popmetal-rk3288_defconfig   |   2 +
> configs/puma-rk3399_defconfig   |   2 +
> configs/rock2_defconfig |   2 +
> configs/rock_defconfig  |   2 +
> configs/sheep-rk3368_defconfig  |   2 +
> configs/tinker-rk3288_defconfig |   2 +
> drivers/adc/Kconfig |   9 ++
> drivers/adc/Makefile|   1 +
> drivers/adc/rockchip-saradc.c   | 183 
> drivers/clk/rockchip/clk_rk3288.c   |  41 ++
> drivers/clk/rockchip/clk_rk3328.c   |  35 -
> drivers/clk/rockchip/clk_rk3368.c   |  32 +
> drivers/clk/rockchip/clk_rk3399.c   |  36 -
> drivers/clk/rockchip/clk_rv1108.c   |  33 -
> include/dt-bindings/clock/rv1108-cru.h  |   2 +
> 39 files changed, 456 insertions(+), 3 deletions(-)
> create mode 100644 drivers/adc/rockchip-saradc.c
> 
> -- 
> 2.7.4
> 
> 

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[U-Boot] [PATCH] dm: core: Round up size when allocating so that it is cache line aligned

[Faiz Abbas]

The size variable may not be always be a mulitple of
ARCH_DMA_MINALIGN and using it to flush cache leads to cache
misaligned warnings.

Therefore, round up the size to a multiple of ARCH_DMA_MINLAIGN
when allocating private data.

Signed-off-by: Faiz Abbas 
---
 drivers/core/device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 5463d1f..96dfb21 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -254,6 +254,7 @@ static void *alloc_priv(int size, uint flags)
void *priv;
 
if (flags & DM_FLAG_ALLOC_PRIV_DMA) {
+   size = ROUND(size, ARCH_DMA_MINALIGN);
priv = memalign(ARCH_DMA_MINALIGN, size);
if (priv) {
memset(priv, '\0', size);
-- 
2.7.4

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[U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

[Faiz Abbas]

A flush of the cache is required before any DMA access can take place.
The minimum size that can be flushed from the cache is one cache line
size. Therefore, any buffer allocated for DMA should be in multiples
of cache line size.

Thus, allocate memory for ep0_trb in multiples of cache line size.

Also, when local variable trb is assigned to dwc->ep0_trb[1] and used
to flush cache, it leads to cache misaligned messages as only the base
address dwc->ep0_trb is cache aligned.

Therefore, flush cache using ep0_trb_addr which is always cache aligned.

Signed-off-by: Faiz Abbas 
---
 drivers/usb/dwc3/ep0.c| 7 ---
 drivers/usb/dwc3/gadget.c | 3 ++-
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index e61d980..f3a17a1 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -82,7 +82,7 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, 
dma_addr_t buf_dma,
| DWC3_TRB_CTRL_LST);
 
dwc3_flush_cache((uintptr_t)buf_dma, len);
-   dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+   dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr, sizeof(*trb) * 2);
 
if (chain)
return 0;
@@ -790,7 +790,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
if (!r)
return;
 
-   dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+   dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr, sizeof(*trb) * 2);
 
status = DWC3_TRB_SIZE_TRBSTS(trb->size);
if (status == DWC3_TRBSTS_SETUP_PENDING) {
@@ -821,7 +821,8 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
ur->actual += transferred;
 
trb++;
-   dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+   dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr,
+sizeof(*trb) * 2);
length = trb->size & DWC3_TRB_SIZE_MASK;
 
ep0->free_slot = 0;
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index e065c5a..895a5bc 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2567,7 +2567,8 @@ int dwc3_gadget_init(struct dwc3 *dwc)
goto err0;
}
 
-   dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
+   dwc->ep0_trb = dma_alloc_coherent(ROUND(sizeof(*dwc->ep0_trb) * 2,
+   CACHELINE_SIZE),
  (unsigned long *)>ep0_trb_addr);
if (!dwc->ep0_trb) {
dev_err(dwc->dev, "failed to allocate ep0 trb\n");
-- 
2.7.4

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[U-Boot] [U-Boot,v2,11/14] arm: dts: Enable SARADC for rk3328-evb

[David Wu]

Signed-off-by: David Wu 
---
 arch/arm/dts/rk3328-evb.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 8a14c65..df44ccb 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -42,6 +42,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
2.7.4


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[U-Boot] [U-Boot, v2, 12/14] arm: dts: Enable SARADC for rk3368-px5-evb

[David Wu]

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@@CONTACT_ADDRESS@@ for details.

Content preview:  Signed-off-by: David Wu  --- 
arch/arm/dts/rk3368-px5-evb.dts
   | 4  1 file changed, 4 insertions(+) diff --git 
a/arch/arm/dts/rk3368-px5-evb.dts
   b/arch/arm/dts/rk3368-px5-evb.dts index c7478f7..e9c5eba 100644 --- 
a/arch/arm/dts/rk3368-px5-evb.dts
   +++ b/arch/arm/dts/rk3368-px5-evb.dts @@ -296,6 +296,10 @@ }; }; [...] 

Content analysis details:   (6.9 points, 5.0 required)

 pts rule name  description
 -- --
 0.6 RCVD_IN_SORBS_WEB  RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
 1.2 RCVD_IN_BL_SPAMCOP_NET RBL: Received via a relay in bl.spamcop.net
 [Blocked - see ]
 2.7 RCVD_IN_PSBL   RBL: Received via a relay in PSBL
[211.157.147.135 listed in psbl.surriel.com]
 2.4 RCVD_IN_MSPIKE_L5  RBL: Very bad reputation (-5)
[211.157.147.135 listed in bl.mailspike.net]
 0.0 RCVD_IN_MSPIKE_BL  Mailspike blacklisted


--- Begin Message ---
Signed-off-by: David Wu 
---
 arch/arm/dts/rk3368-px5-evb.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/rk3368-px5-evb.dts b/arch/arm/dts/rk3368-px5-evb.dts
index c7478f7..e9c5eba 100644
--- a/arch/arm/dts/rk3368-px5-evb.dts
+++ b/arch/arm/dts/rk3368-px5-evb.dts
@@ -296,6 +296,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
rockchip,hw-tshut-mode = <0>; /* CRU */
-- 
2.7.4


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[U-Boot] [U-Boot, v2, 10/14] arm: dts: Enable SARADC for rk3288-popmetal

[David Wu]

Signed-off-by: David Wu 
---
 arch/arm/dts/rk3288-popmetal.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/rk3288-popmetal.dtsi 
b/arch/arm/dts/rk3288-popmetal.dtsi
index dd6ce8b..63785eb 100644
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -491,6 +491,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
-- 
2.7.4


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[U-Boot] [U-Boot,v2,09/14] arm: dts: Enable SARADC for rv1108-evb

[David Wu]

Signed-off-by: David Wu 
---
 arch/arm/dts/rv1108-evb.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts
index 0128dd8..e21b57f 100644
--- a/arch/arm/dts/rv1108-evb.dts
+++ b/arch/arm/dts/rv1108-evb.dts
@@ -30,6 +30,10 @@
snps,reset-gpio = < RK_PC1 GPIO_ACTIVE_LOW>;
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
flash@0 {
-- 
2.7.4


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[U-Boot] [U-Boot, v2, 08/14] arm: dts: rv1108: Add SARADC node at dtsi level

[David Wu]

Signed-off-by: David Wu 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---
 arch/arm/dts/rv1108.dtsi | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
index 77ca24e..d6927ee 100644
--- a/arch/arm/dts/rv1108.dtsi
+++ b/arch/arm/dts/rv1108.dtsi
@@ -126,6 +126,17 @@
reg = <0x1030 0x1000>;
};
 
+   saradc: saradc@1038c000 {
+   compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+   reg = <0x1038c000 0x100>;
+   interrupts = ;
+   #io-channel-cells = <1>;
+   clock-frequency = <100>;
+   clocks = < SCLK_SARADC>, < PCLK_SARADC>;
+   clock-names = "saradc", "apb_pclk";
+   status = "disabled";
+   };
+
pmugrf: syscon@2006 {
compatible = "rockchip,rv1108-pmugrf", "syscon";
reg = <0x2006 0x1000>;
-- 
2.7.4


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[U-Boot] [U-Boot, v2, 07/14] clk: rockchip: Add rk3399 SARADC clock support

[David Wu]

Spam detection software, running on the system "lists.denx.de",
has identified this incoming email as possible spam.  The original
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Content preview:  The clk_saradc is dividing from the 24M, 
clk_saradc=24MHz/(saradc_div_con+1).
   SARADC integer divider control register is 8-bits width. Signed-off-by: David
   Wu  Acked-by: Philipp Tomsich 

   Reviewed-by: Philipp Tomsich  ---
  [...] 

Content analysis details:   (6.9 points, 5.0 required)

 pts rule name  description
 -- --
 0.6 RCVD_IN_SORBS_WEB  RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
 1.2 RCVD_IN_BL_SPAMCOP_NET RBL: Received via a relay in bl.spamcop.net
 [Blocked - see ]
 2.7 RCVD_IN_PSBL   RBL: Received via a relay in PSBL
[211.157.147.135 listed in psbl.surriel.com]
 2.4 RCVD_IN_MSPIKE_L5  RBL: Very bad reputation (-5)
[211.157.147.135 listed in bl.mailspike.net]
 0.0 RCVD_IN_MSPIKE_BL  Mailspike blacklisted


--- Begin Message ---
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---

Change in v2:
 - Use GENMASK.

 drivers/clk/rockchip/clk_rk3399.c | 36 +++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 3edafea..105c499 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -181,7 +182,8 @@ enum {
 
/* CLKSEL_CON26 */
CLK_SARADC_DIV_CON_SHIFT= 8,
-   CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT,
+   CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
+   CLK_SARADC_DIV_CON_WIDTH= 8,
 
/* CLKSEL_CON27 */
CLK_TSADC_SEL_X24M  = 0x0,
@@ -860,6 +862,32 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 
return set_rate;
 }
+
+static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
+{
+   u32 div, val;
+
+   val = readl(>clksel_con[26]);
+   div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+  CLK_SARADC_DIV_CON_WIDTH);
+
+   return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
+{
+   int src_clk_div;
+
+   src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+   assert(src_clk_div < 128);
+
+   rk_clrsetreg(>clksel_con[26],
+CLK_SARADC_DIV_CON_MASK,
+src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+   return rk3399_saradc_get_clk(cru);
+}
+
 static ulong rk3399_clk_get_rate(struct clk *clk)
 {
struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
@@ -895,6 +923,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
break;
case PCLK_EFUSE1024NS:
break;
+   case SCLK_SARADC:
+   rate = rk3399_saradc_get_clk(priv->cru);
+   break;
default:
return -ENOENT;
}
@@ -943,6 +974,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong 
rate)
break;
case PCLK_EFUSE1024NS:
break;
+   case SCLK_SARADC:
+   ret = rk3399_saradc_set_clk(priv->cru, rate);
+   break;
default:
return -ENOENT;
}
-- 
2.7.4


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[U-Boot] [U-Boot, v2, 05/14] clk: rockchip: Add rk3328 SARADC clock support

[David Wu]

Spam detection software, running on the system "lists.denx.de",
has identified this incoming email as possible spam.  The original
message has been attached to this so you can view it or label
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@@CONTACT_ADDRESS@@ for details.

Content preview:  The clk_saradc is dividing from the 24M, 
clk_saradc=24MHz/(saradc_div_con+1).
   SARADC integer divider control register is 10-bits width. Signed-off-by:
  David Wu  Acked-by: Philipp Tomsich 

   Reviewed-by: Philipp Tomsich  ---
  [...] 

Content analysis details:   (6.9 points, 5.0 required)

 pts rule name  description
 -- --
 0.6 RCVD_IN_SORBS_WEB  RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
 1.2 RCVD_IN_BL_SPAMCOP_NET RBL: Received via a relay in bl.spamcop.net
 [Blocked - see ]
 2.7 RCVD_IN_PSBL   RBL: Received via a relay in PSBL
[211.157.147.135 listed in psbl.surriel.com]
 2.4 RCVD_IN_MSPIKE_L5  RBL: Very bad reputation (-5)
[211.157.147.135 listed in bl.mailspike.net]
 0.0 RCVD_IN_MSPIKE_BL  Mailspike blacklisted


--- Begin Message ---
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---

Change in v2:
 - Use extract_bits.

 drivers/clk/rockchip/clk_rk3328.c | 35 ++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3328.c 
b/drivers/clk/rockchip/clk_rk3328.c
index c3a6650..540d910 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -114,7 +115,8 @@ enum {
 
/* CLKSEL_CON23 */
CLK_SARADC_DIV_CON_SHIFT= 0,
-   CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT,
+   CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
+   CLK_SARADC_DIV_CON_WIDTH= 10,
 
/* CLKSEL_CON24 */
CLK_PWM_PLL_SEL_CPLL= 0,
@@ -478,6 +480,31 @@ static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, 
uint hz)
return DIV_TO_RATE(GPLL_HZ, div);
 }
 
+static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
+{
+   u32 div, val;
+
+   val = readl(>clksel_con[23]);
+   div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+  CLK_SARADC_DIV_CON_WIDTH);
+
+   return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
+{
+   int src_clk_div;
+
+   src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+   assert(src_clk_div < 128);
+
+   rk_clrsetreg(>clksel_con[23],
+CLK_SARADC_DIV_CON_MASK,
+src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+   return rk3328_saradc_get_clk(cru);
+}
+
 static ulong rk3328_clk_get_rate(struct clk *clk)
 {
struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
@@ -501,6 +528,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
case SCLK_PWM:
rate = rk3328_pwm_get_clk(priv->cru);
break;
+   case SCLK_SARADC:
+   rate = rk3328_saradc_get_clk(priv->cru);
+   break;
default:
return -ENOENT;
}
@@ -531,6 +561,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong 
rate)
case SCLK_PWM:
ret = rk3328_pwm_set_clk(priv->cru, rate);
break;
+   case SCLK_SARADC:
+   ret = rk3328_saradc_set_clk(priv->cru, rate);
+   break;
default:
return -ENOENT;
}
-- 
2.7.4


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[U-Boot] [U-Boot, v2, 06/14] clk: rockchip: Add rk3368 SARADC clock support

[David Wu]

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---

Change in v2:
 - Use GENMASK.

 arch/arm/include/asm/arch-rockchip/cru_rk3368.h |  5 
 drivers/clk/rockchip/clk_rk3368.c   | 32 +
 2 files changed, 37 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 2b1197f..5f6a5fb 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -89,6 +89,11 @@ enum {
MCU_CLK_DIV_SHIFT   = 0,
MCU_CLK_DIV_MASK= GENMASK(4, 0),
 
+   /* CLKSEL_CON25 */
+   CLK_SARADC_DIV_CON_SHIFT= 8,
+   CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
+   CLK_SARADC_DIV_CON_WIDTH= 8,
+
/* CLKSEL43_CON */
GMAC_MUX_SEL_EXTCLK = BIT(8),
 
diff --git a/drivers/clk/rockchip/clk_rk3368.c 
b/drivers/clk/rockchip/clk_rk3368.c
index 2be1f57..2eedf77 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -397,6 +398,31 @@ static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, 
ulong clk_id, uint hz)
return rk3368_spi_get_clk(cru, clk_id);
 }
 
+static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)
+{
+   u32 div, val;
+
+   val = readl(>clksel_con[25]);
+   div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+  CLK_SARADC_DIV_CON_WIDTH);
+
+   return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
+{
+   int src_clk_div;
+
+   src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+   assert(src_clk_div < 128);
+
+   rk_clrsetreg(>clksel_con[25],
+CLK_SARADC_DIV_CON_MASK,
+src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+   return rk3368_saradc_get_clk(cru);
+}
+
 static ulong rk3368_clk_get_rate(struct clk *clk)
 {
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -419,6 +445,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
rate = rk3368_mmc_get_clk(priv->cru, clk->id);
break;
 #endif
+   case SCLK_SARADC:
+   rate = rk3368_saradc_get_clk(priv->cru);
+   break;
default:
return -ENOENT;
}
@@ -453,6 +482,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong 
rate)
ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);
break;
 #endif
+   case SCLK_SARADC:
+   ret =  rk3368_saradc_set_clk(priv->cru, rate);
+   break;
default:
return -ENOENT;
}
-- 
2.7.4


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[U-Boot] [U-Boot, v2, 03/14] clk: rockchip: Add rv1108 SARADC clock support

[David Wu]

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---

Change in v2:
 - Use extract_bits.

 arch/arm/include/asm/arch-rockchip/cru_rv1108.h |  5 
 drivers/clk/rockchip/clk_rv1108.c   | 33 -
 include/dt-bindings/clock/rv1108-cru.h  |  2 ++
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h 
b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
index 2a1ae69..ad2dc96 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
@@ -90,6 +90,11 @@ enum {
CORE_CLK_DIV_SHIFT  = 0,
CORE_CLK_DIV_MASK   = 0x1f << CORE_CLK_DIV_SHIFT,
 
+   /* CLKSEL_CON22 */
+   CLK_SARADC_DIV_CON_SHIFT= 0,
+   CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
+   CLK_SARADC_DIV_CON_WIDTH= 10,
+
/* CLKSEL24_CON */
MAC_PLL_SEL_SHIFT   = 12,
MAC_PLL_SEL_MASK= 1 << MAC_PLL_SEL_SHIFT,
diff --git a/drivers/clk/rockchip/clk_rv1108.c 
b/drivers/clk/rockchip/clk_rv1108.c
index cf966bb..86e73e4 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -36,7 +37,7 @@ enum {
 #hz "Hz cannot be hit with PLL "\
 "divisors on line " __stringify(__LINE__));
 
-/* use interge mode*/
+/* use integer mode */
 static inline int rv1108_pll_id(enum rk_clk_id clk_id)
 {
int id = 0;
@@ -130,6 +131,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint 
rate)
return DIV_TO_RATE(pll_rate, div);
 }
 
+static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
+{
+   u32 div, val;
+
+   val = readl(>clksel_con[22]);
+   div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+  CLK_SARADC_DIV_CON_WIDTH);
+
+   return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
+{
+   int src_clk_div;
+
+   src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+   assert(src_clk_div < 128);
+
+   rk_clrsetreg(>clksel_con[22],
+CLK_SARADC_DIV_CON_MASK,
+src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+   return rv1108_saradc_get_clk(cru);
+}
+
 static ulong rv1108_clk_get_rate(struct clk *clk)
 {
struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
@@ -137,6 +163,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk)
switch (clk->id) {
case 0 ... 63:
return rkclk_pll_get_rate(priv->cru, clk->id);
+   case SCLK_SARADC:
+   return rv1108_saradc_get_clk(priv->cru);
default:
return -ENOENT;
}
@@ -154,6 +182,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong 
rate)
case SCLK_SFC:
new_rate = rv1108_sfc_set_clk(priv->cru, rate);
break;
+   case SCLK_SARADC:
+   new_rate = rv1108_saradc_set_clk(priv->cru, rate);
+   break;
default:
return -ENOENT;
}
diff --git a/include/dt-bindings/clock/rv1108-cru.h 
b/include/dt-bindings/clock/rv1108-cru.h
index d2ad3bb..7defc6b 100644
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -39,6 +39,7 @@
 #define SCLK_MAC_TX88
 #define SCLK_MACREF89
 #define SCLK_MACREF_OUT90
+#define SCLK_SARADC91
 
 
 /* aclk gates */
@@ -67,6 +68,7 @@
 #define PCLK_TIMER 270
 #define PCLK_PERI  271
 #define PCLK_GMAC  272
+#define PCLK_SARADC273
 
 /* hclk gates */
 #define HCLK_I2S0_8CH  320
-- 
2.7.4


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[U-Boot] [U-Boot,v2,01/14] adc: Add driver for Rockchip SARADC

[David Wu]

The ADC can support some channels signal-ended some bits Successive 
Approximation
Register (SAR) A/D Converter, like 6-channel and 10-bit. It converts the analog
input signal into some bits binary digital codes.

Signed-off-by: David Wu 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---

Changes in v2:
 - Order the the include file.
 - Use structures for I/O access.
 - Use dev_read_add.

 drivers/adc/Kconfig   |   9 +++
 drivers/adc/Makefile  |   1 +
 drivers/adc/rockchip-saradc.c | 183 ++
 3 files changed, 193 insertions(+)
 create mode 100644 drivers/adc/rockchip-saradc.c

diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index e5335f7..8094420 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -28,3 +28,12 @@ config ADC_SANDBOX
  - 4 analog input channels
  - 16-bit resolution
  - single and multi-channel conversion mode
+
+config SARADC_ROCKCHIP
+   bool "Enable Rockchip SARADC driver"
+   help
+ This enables driver for Rockchip SARADC.
+ It provides:
+ - 2~6 analog input channels
+ - 1O or 12 bits resolution
+ - Up to 1MSPS of sample rate
diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile
index cebf26d..4b5aa69 100644
--- a/drivers/adc/Makefile
+++ b/drivers/adc/Makefile
@@ -8,3 +8,4 @@
 obj-$(CONFIG_ADC) += adc-uclass.o
 obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o
 obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
+obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o
diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
new file mode 100644
index 000..0e6271d
--- /dev/null
+++ b/drivers/adc/rockchip-saradc.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2017, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Rockchip SARADC driver for U-Boot
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SARADC_CTRL_CHN_MASK   GENMASK(2, 0)
+#define SARADC_CTRL_POWER_CTRL BIT(3)
+#define SARADC_CTRL_IRQ_ENABLE BIT(5)
+#define SARADC_CTRL_IRQ_STATUS BIT(6)
+
+#define SARADC_TIMEOUT (100 * 1000)
+
+struct rockchip_saradc_regs {
+   unsigned int data;
+   unsigned int stas;
+   unsigned int ctrl;
+   unsigned int dly_pu_soc;
+};
+
+struct rockchip_saradc_data {
+   int num_bits;
+   int num_channels;
+   unsigned long   clk_rate;
+};
+
+struct rockchip_saradc_priv {
+   struct rockchip_saradc_regs *regs;
+   int active_channel;
+   const struct rockchip_saradc_data   *data;
+};
+
+int rockchip_saradc_channel_data(struct udevice *dev, int channel,
+unsigned int *data)
+{
+   struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+   struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+
+   if (channel != priv->active_channel) {
+   error("Requested channel is not active!");
+   return -EINVAL;
+   }
+
+   if ((readl(>regs->ctrl) & SARADC_CTRL_IRQ_STATUS) !=
+   SARADC_CTRL_IRQ_STATUS)
+   return -EBUSY;
+
+   /* Read value */
+   *data = readl(>regs->data);
+   *data &= uc_pdata->data_mask;
+
+   /* Power down adc */
+   writel(0, >regs->ctrl);
+
+   return 0;
+}
+
+int rockchip_saradc_start_channel(struct udevice *dev, int channel)
+{
+   struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+
+   if (channel < 0 || channel >= priv->data->num_channels) {
+   error("Requested channel is invalid!");
+   return -EINVAL;
+   }
+
+   /* 8 clock periods as delay between power up and start cmd */
+   writel(8, >regs->dly_pu_soc);
+
+   /* Select the channel to be used and trigger conversion */
+   writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) |
+  SARADC_CTRL_IRQ_ENABLE, >regs->ctrl);
+
+   priv->active_channel = channel;
+
+   return 0;
+}
+
+int rockchip_saradc_stop(struct udevice *dev)
+{
+   struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+
+   /* Power down adc */
+   writel(0, >regs->ctrl);
+
+   priv->active_channel = -1;
+
+   return 0;
+}
+
+int rockchip_saradc_probe(struct udevice *dev)
+{
+   struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+   struct clk clk;
+   int ret;
+
+   ret = clk_get_by_index(dev, 0, );
+   if (ret)
+   return ret;
+
+   ret = clk_set_rate(, priv->data->clk_rate);
+   if (IS_ERR_VALUE(ret))
+   return ret;
+
+   priv->active_channel = -1;
+
+   return 0;
+}
+
+int rockchip_saradc_ofdata_to_platdata(struct udevice *dev)
+{
+ 

[U-Boot] [U-Boot, v2, 02/14] configs: rockchip: Enable the ROCKCHIP_SARADC config

[David Wu]

Except for 3036 and 3228 Socs, which don't support SARADC,
enable the ROCKCHIP_SARADC config at the other Socs' defconfig.

Signed-off-by: David Wu 
---

Change in v2:
 - Enable the ROCKCHIP_SARADC at other configs

 configs/chromebit_mickey_defconfig  | 2 ++
 configs/chromebook_jerry_defconfig  | 2 ++
 configs/chromebook_minnie_defconfig | 2 ++
 configs/evb-px5_defconfig   | 2 ++
 configs/evb-rk3288_defconfig| 2 ++
 configs/evb-rk3328_defconfig| 2 ++
 configs/evb-rk3399_defconfig| 2 ++
 configs/evb-rv1108_defconfig| 2 ++
 configs/fennec-rk3288_defconfig | 2 ++
 configs/firefly-rk3288_defconfig| 2 ++
 configs/firefly-rk3399_defconfig| 2 ++
 configs/geekbox_defconfig   | 2 ++
 configs/lion-rk3368_defconfig   | 2 ++
 configs/miqi-rk3288_defconfig   | 2 ++
 configs/phycore-rk3288_defconfig| 2 ++
 configs/popmetal-rk3288_defconfig   | 2 ++
 configs/puma-rk3399_defconfig   | 2 ++
 configs/rock2_defconfig | 2 ++
 configs/rock_defconfig  | 2 ++
 configs/sheep-rk3368_defconfig  | 2 ++
 configs/tinker-rk3288_defconfig | 2 ++
 21 files changed, 42 insertions(+)

diff --git a/configs/chromebit_mickey_defconfig 
b/configs/chromebit_mickey_defconfig
index f40c0b9..e84706d 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -40,6 +40,8 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index cdeabaa..f612d31 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -42,6 +42,8 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/chromebook_minnie_defconfig 
b/configs/chromebook_minnie_defconfig
index c1e36fa..38a4b42 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -41,6 +41,8 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index 4323b77..cbf467f 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -13,6 +13,8 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_CACHE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 5294ba9..f09b769 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -37,6 +37,8 @@ CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 7bec001..b44b029 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -20,6 +20,8 @@ CONFIG_CMD_TIME=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_MMC_DW=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 7a0bd4a..6d0d1a0 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -30,6 +30,8 @@ CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig
index ab4276a..3278104 100644
--- a/configs/evb-rv1108_defconfig
+++ b/configs/evb-rv1108_defconfig
@@ -13,6 +13,8 @@ CONFIG_CMD_TIME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index 96a07de..913849e 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -40,6 +40,8 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 82da601..75f8cdb 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -40,6 +40,8 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_ADC=y
+CONFIG_SARADC_ROCKCHIP=y
 CONFIG_CLK=y
 

[U-Boot] [U-Boot,v2,00/14] Add rockchip SARADC support

[David Wu]

The SARADC is used for adc keys and charging detect at uboot
loader. Except for the rk3036 and rk3228 Socs, the others
support the SARADC IP.

David Wu (14):
  adc: Add driver for Rockchip SARADC
  configs: rockchip: Enable the ROCKCHIP_SARADC config
  clk: rockchip: Add rv1108 SARADC clock support
  clk: rockchip: Add SARADC clock support for rk3288
  clk: rockchip: Add rk3328 SARADC clock support
  clk: rockchip: Add rk3368 SARADC clock support
  clk: rockchip: Add rk3399 SARADC clock support
  arm: dts: rv1108: Add Saradc node at dtsi level
  arm: dts: Enable SARADC for rv1108-evb
  arm: dts: Enable SARADC for rk3288-popmetal
  arm: dts: Enable SARADC for rk3328-evb
  arm: dts: Enable SARADC for rk3368-px5-evb
  arm: dts: Enable SARADC for rk3368-sheep
  arm: dts: Enable SARADC for rk3399-evb

 arch/arm/dts/rk3288-popmetal.dtsi   |   4 +
 arch/arm/dts/rk3328-evb.dts |   4 +
 arch/arm/dts/rk3368-px5-evb.dts |   4 +
 arch/arm/dts/rk3368-sheep.dts   |   4 +
 arch/arm/dts/rk3399-evb.dts |   4 +
 arch/arm/dts/rv1108-evb.dts |   4 +
 arch/arm/dts/rv1108.dtsi|  11 ++
 arch/arm/include/asm/arch-rockchip/cru_rk3368.h |   5 +
 arch/arm/include/asm/arch-rockchip/cru_rv1108.h |   5 +
 configs/chromebit_mickey_defconfig  |   2 +
 configs/chromebook_jerry_defconfig  |   2 +
 configs/chromebook_minnie_defconfig |   2 +
 configs/evb-px5_defconfig   |   2 +
 configs/evb-rk3288_defconfig|   2 +
 configs/evb-rk3328_defconfig|   2 +
 configs/evb-rk3399_defconfig|   2 +
 configs/evb-rv1108_defconfig|   2 +
 configs/fennec-rk3288_defconfig |   2 +
 configs/firefly-rk3288_defconfig|   2 +
 configs/firefly-rk3399_defconfig|   2 +
 configs/geekbox_defconfig   |   2 +
 configs/lion-rk3368_defconfig   |   2 +
 configs/miqi-rk3288_defconfig   |   2 +
 configs/phycore-rk3288_defconfig|   2 +
 configs/popmetal-rk3288_defconfig   |   2 +
 configs/puma-rk3399_defconfig   |   2 +
 configs/rock2_defconfig |   2 +
 configs/rock_defconfig  |   2 +
 configs/sheep-rk3368_defconfig  |   2 +
 configs/tinker-rk3288_defconfig |   2 +
 drivers/adc/Kconfig |   9 ++
 drivers/adc/Makefile|   1 +
 drivers/adc/rockchip-saradc.c   | 183 
 drivers/clk/rockchip/clk_rk3288.c   |  41 ++
 drivers/clk/rockchip/clk_rk3328.c   |  35 -
 drivers/clk/rockchip/clk_rk3368.c   |  32 +
 drivers/clk/rockchip/clk_rk3399.c   |  36 -
 drivers/clk/rockchip/clk_rv1108.c   |  33 -
 include/dt-bindings/clock/rv1108-cru.h  |   2 +
 39 files changed, 456 insertions(+), 3 deletions(-)
 create mode 100644 drivers/adc/rockchip-saradc.c

-- 
2.7.4


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[U-Boot] [PATCH v2 1/1] kconfiglib: update with 'imply' support

[Ulf Magnusson]

Corresponds to 375506d (File writing nit) from upstream
(https://github.com/ulfalizer/Kconfiglib).

Adds proper 'imply' support and fixes a few minor issues, one of which
previously triggered the following weird warning:

  configs/taurus_defconfig: /tmp/tmpisI45S:6: warning: assignment to 
SPL_LDSCRIPT changes mode of containing choice from 
"arch/$(ARCH)/cpu/u-boot-spl.lds" to "y"

The change in 8639f69 (genconfig.py: Print defconfig next to warnings)
was reapplied.

tools/moveconfig.py previously depended on a hack that merged 'select's
with 'imply's. It was modified to look at the union of
Symbol.get_selected_symbols() and Symbol.get_implied_symbols(), which
should give the same behavior.

tools/genboardscfg.py was verified to produce identical board.cfg's
before and after the change.

Signed-off-by: Ulf Magnusson 
---
 tools/buildman/kconfiglib.py | 333 +--
 tools/moveconfig.py  |   2 +-
 2 files changed, 194 insertions(+), 141 deletions(-)

diff --git a/tools/buildman/kconfiglib.py b/tools/buildman/kconfiglib.py
index 352ad43..68b470a 100644
--- a/tools/buildman/kconfiglib.py
+++ b/tools/buildman/kconfiglib.py
@@ -73,6 +73,7 @@ email service. Don't wrestle with internal APIs. Tell me what 
you need and I
 might add it in a safe way as a client API instead."""
 
 import os
+import platform
 import re
 import sys
 
@@ -137,10 +138,8 @@ class Config(object):
 # The set of all symbols, indexed by name (a string)
 self.syms = {}
 # Python 2/3 compatibility hack. This is the only one needed.
-if sys.version_info[0] >= 3:
-self.syms_iter = self.syms.values
-else:
-self.syms_iter = self.syms.itervalues
+self.syms_iter = self.syms.values if sys.version_info[0] >= 3 else \
+ self.syms.itervalues
 
 # The set of all defined symbols in the configuration in the order they
 # appear in the Kconfig files. This excludes the special symbols n, m,
@@ -173,7 +172,7 @@ class Config(object):
 self.m = register_special_symbol(TRISTATE, "m", "m")
 self.y = register_special_symbol(TRISTATE, "y", "y")
 # DEFCONFIG_LIST uses this
-register_special_symbol(STRING, "UNAME_RELEASE", os.uname()[2])
+register_special_symbol(STRING, "UNAME_RELEASE", platform.uname()[2])
 
 # The symbol with "option defconfig_list" set, containing a list of
 # default .config files
@@ -183,16 +182,20 @@ class Config(object):
 self.arch = os.environ.get("ARCH")
 self.srcarch = os.environ.get("SRCARCH")
 
+# If you set CONFIG_ in the environment, Kconfig will prefix all 
symbols
+# with its value when saving the configuration, instead of using the 
default, "CONFIG_".
+self.config_prefix = os.environ.get("CONFIG_")
+if self.config_prefix is None:
+self.config_prefix = "CONFIG_"
+
 # See Config.__init__(). We need this for get_defconfig_filename().
 self.srctree = os.environ.get("srctree")
 if self.srctree is None:
 self.srctree = "."
 
 self.filename = filename
-if base_dir is None:
-self.base_dir = self.srctree
-else:
-self.base_dir = os.path.expandvars(base_dir)
+self.base_dir = self.srctree if base_dir is None else \
+os.path.expandvars(base_dir)
 
 # The 'mainmenu' text
 self.mainmenu_text = None
@@ -222,7 +225,8 @@ class Config(object):
 self._transform_m = None
 
 # Parse the Kconfig files
-self.top_block = self._parse_file(filename, None, None, None)
+self.top_block = []
+self._parse_file(filename, None, None, None, self.top_block)
 
 # Build Symbol.dep for all symbols
 self._build_dep()
@@ -405,6 +409,10 @@ class Config(object):
 """
 
 self._warnings = []
+# Regular expressions for parsing .config files
+_set_re_match = 
re.compile(r"{}(\w+)=(.*)".format(self.config_prefix)).match
+_unset_re_match = re.compile(r"# {}(\w+) is not 
set".format(self.config_prefix)).match
+
 # Put this first so that a missing file doesn't screw up our state
 filename = os.path.expandvars(filename)
 line_feeder = _FileFeed(filename)
@@ -524,14 +532,12 @@ class Config(object):
 with open(filename, "w") as f:
 # Write header
 if header is not None:
-f.write(_comment(header))
-f.write("\n")
+f.write(_comment(header) + "\n")
 
 # Build and write configuration
 conf_strings = []
 _make_block_conf(self.top_block, conf_strings.append)
-f.write("\n".join(conf_strings))
-f.write("\n")
+f.write("\n".join(conf_strings) + "\n")
 
 def eval(self, s):
 """Returns the value of 

[U-Boot] [PATCH v2 0/1] Update Kconfiglib with 'imply' support

[Ulf Magnusson]

Changes for v2:
tools/moveconfig.py previously depended on a hack that merged 'select's with
'imply's. Update it to look at both so that it will work the same way with the
new kconfiglib version.

Ulf Magnusson (1):
  kconfiglib: update with 'imply' support

 tools/buildman/kconfiglib.py | 333 +--
 tools/moveconfig.py  |   2 +-
 2 files changed, 194 insertions(+), 141 deletions(-)

-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 1/1] kconfiglib: update with 'imply' support

[Ulf Magnusson]

Corresponds to 375506d (File writing nit) from upstream
(https://github.com/ulfalizer/Kconfiglib).

Adds proper 'imply' support and fixes a few minor issues, one of which
previously triggered the following weird warning:

  configs/taurus_defconfig: /tmp/tmpisI45S:6: warning: assignment to 
SPL_LDSCRIPT changes mode of containing choice from 
"arch/$(ARCH)/cpu/u-boot-spl.lds" to "y"

The change in 8639f69 (genconfig.py: Print defconfig next to warnings)
has been reapplied.

tools/genboardscfg.py was verified to produce identical board.cfg's
before and after the change.

Signed-off-by: Ulf Magnusson 
---
 tools/buildman/kconfiglib.py | 333 +--
 1 file changed, 193 insertions(+), 140 deletions(-)

diff --git a/tools/buildman/kconfiglib.py b/tools/buildman/kconfiglib.py
index 352ad43..68b470a 100644
--- a/tools/buildman/kconfiglib.py
+++ b/tools/buildman/kconfiglib.py
@@ -73,6 +73,7 @@ email service. Don't wrestle with internal APIs. Tell me what 
you need and I
 might add it in a safe way as a client API instead."""
 
 import os
+import platform
 import re
 import sys
 
@@ -137,10 +138,8 @@ class Config(object):
 # The set of all symbols, indexed by name (a string)
 self.syms = {}
 # Python 2/3 compatibility hack. This is the only one needed.
-if sys.version_info[0] >= 3:
-self.syms_iter = self.syms.values
-else:
-self.syms_iter = self.syms.itervalues
+self.syms_iter = self.syms.values if sys.version_info[0] >= 3 else \
+ self.syms.itervalues
 
 # The set of all defined symbols in the configuration in the order they
 # appear in the Kconfig files. This excludes the special symbols n, m,
@@ -173,7 +172,7 @@ class Config(object):
 self.m = register_special_symbol(TRISTATE, "m", "m")
 self.y = register_special_symbol(TRISTATE, "y", "y")
 # DEFCONFIG_LIST uses this
-register_special_symbol(STRING, "UNAME_RELEASE", os.uname()[2])
+register_special_symbol(STRING, "UNAME_RELEASE", platform.uname()[2])
 
 # The symbol with "option defconfig_list" set, containing a list of
 # default .config files
@@ -183,16 +182,20 @@ class Config(object):
 self.arch = os.environ.get("ARCH")
 self.srcarch = os.environ.get("SRCARCH")
 
+# If you set CONFIG_ in the environment, Kconfig will prefix all 
symbols
+# with its value when saving the configuration, instead of using the 
default, "CONFIG_".
+self.config_prefix = os.environ.get("CONFIG_")
+if self.config_prefix is None:
+self.config_prefix = "CONFIG_"
+
 # See Config.__init__(). We need this for get_defconfig_filename().
 self.srctree = os.environ.get("srctree")
 if self.srctree is None:
 self.srctree = "."
 
 self.filename = filename
-if base_dir is None:
-self.base_dir = self.srctree
-else:
-self.base_dir = os.path.expandvars(base_dir)
+self.base_dir = self.srctree if base_dir is None else \
+os.path.expandvars(base_dir)
 
 # The 'mainmenu' text
 self.mainmenu_text = None
@@ -222,7 +225,8 @@ class Config(object):
 self._transform_m = None
 
 # Parse the Kconfig files
-self.top_block = self._parse_file(filename, None, None, None)
+self.top_block = []
+self._parse_file(filename, None, None, None, self.top_block)
 
 # Build Symbol.dep for all symbols
 self._build_dep()
@@ -405,6 +409,10 @@ class Config(object):
 """
 
 self._warnings = []
+# Regular expressions for parsing .config files
+_set_re_match = 
re.compile(r"{}(\w+)=(.*)".format(self.config_prefix)).match
+_unset_re_match = re.compile(r"# {}(\w+) is not 
set".format(self.config_prefix)).match
+
 # Put this first so that a missing file doesn't screw up our state
 filename = os.path.expandvars(filename)
 line_feeder = _FileFeed(filename)
@@ -524,14 +532,12 @@ class Config(object):
 with open(filename, "w") as f:
 # Write header
 if header is not None:
-f.write(_comment(header))
-f.write("\n")
+f.write(_comment(header) + "\n")
 
 # Build and write configuration
 conf_strings = []
 _make_block_conf(self.top_block, conf_strings.append)
-f.write("\n".join(conf_strings))
-f.write("\n")
+f.write("\n".join(conf_strings) + "\n")
 
 def eval(self, s):
 """Returns the value of the expression 's' -- where 's' is represented
@@ -609,16 +615,18 @@ class Config(object):
 # Kconfig parsing
 #
 
-def _parse_file(self, filename, parent, deps, visible_if_deps, res=None):
-"""Parses the Kconfig file 'filename'. Returns a list 

Re: [U-Boot] [PATCH v2 0/5] rockchip: back-to-bootrom: replace assembly-implementation with C-code

[Dr. Philipp Tomsich]

> On 19 Sep 2017, at 11:12, Heiko Stübner  wrote:
> 
> Am Dienstag, 19. September 2017, 11:10:29 CEST schrieb Dr. Philipp Tomsich:
>> Andy,
>> 
>>> On 19 Sep 2017, at 09:19, Andy Yan  wrote:
>>> 
>>> Hi Philipp:
>>> 
>>> On 2017年09月19日 10:06, Andy Yan wrote:
 Hi Philipp:
 
 On 2017年09月19日 02:18, Philipp Tomsich wrote:
> Recent discussions confirmed (what the code always assumed): the
> Rockchip BROM always enters U-Boot with the stack-pointer valid
> (i.e. the U-Boot startup code is running off the BROM stack).
> 
> We can thus replace the back-to-bootrom code (i.e. both the
> save_boot_params and back_to_bootrom implementations) using C-code
> based on setjmp/longjmp.  The new implementation is already structured
> to allow an easy drop-in of Andy's changes to enter download-mode when
> returning to the BROM.
> 
> This entails one minor tweak to asm/system.h, which only exported
> the save_boot_params_ret prototype for ARMv7, but not for AArch64.
> 
> For v2, we force bootrom.o to alway be emitted as A32 (not T32), so we
> can safely call save_boot_params_ret().
> 
   This still have a problem, because the setjmp  implementation for
   ARM32 platform  has humb code when CONFIG_SYS_THUMB_BUILD is>> 
 enabled, this is a default setting for most ARMv7 boards.
 #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
 ".align 2\n"
 "adr r0, jmp_target\n"
 "add r0, r0, $1\n"  // r0 stored the jump target address and with bit[0]
 = 1, this will trigger a thumb switch in longjmp with code "bx r0"
 #endif
 
 When I force the setjmp code go arm code path, I can back to bootrom
 successfully, But I got a data abort exception in later. it seems it
 happens when bootrom finished the uboot code copy, when jump to sdram, I
 need a further debug.
>>> 
>>> I found that r9 also need to be preserved, it seems that it hold the sdram
>>> base.
>> Thanks for testing and debugging: this is invaluable support, as I only have
>> AArch64 boards to test.
>> 
>> The r9 issue will be easy enough to resolve.
>> However, it looks like I will need more work on setjmp/longjmp to make this
>> safe both for T32 and A32. Plus: I need to figure out why this didn’t show
>> in my disassembly (I don’t remember whether it was a rk3188 or rk3288 board
>> I looked at).
>> 
>> Might be tomorrow or Thursday until I can provide an new version.
> 
> From this conversation, it looks to me that I should wait for that new
> version for testing on rk3188, as it will likely show the same issues, right?

Yes.
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Re: [U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[Marek Vasut]

On 09/19/2017 11:22 AM, chin.liang@intel.com wrote:
> From: Chin Liang See 
> 
> Add the base address map for Statix10 SoC
> 
> Signed-off-by: Chin Liang See 

Add only the stuff which is not obtainable from DT please.

> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58 
> ++
>  1 file changed, 58 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
> b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> new file mode 100644
> index 000..feb1881
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> @@ -0,0 +1,58 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0
> + */
> +
> +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> +
> +#define SOCFPGA_SDR_SCHEDULER_ADDRESS0xf8000400
> +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801
> +#define SOCFPGA_SDR_ADDRESS  0xf8011000
> +#define SOCFPGA_SMMU_ADDRESS 0xfa00
> +#define SOCFPGA_EMAC0_ADDRESS0xff80
> +#define SOCFPGA_EMAC1_ADDRESS0xff802000
> +#define SOCFPGA_EMAC2_ADDRESS0xff804000
> +#define SOCFPGA_SDMMC_ADDRESS0xff808000
> +#define SOCFPGA_QSPIREGS_ADDRESS 0xff8d2000
> +#define SOCFPGA_QSPIDATA_ADDRESS 0xff90
> +#define SOCFPGA_MAILBOX_ADDRESS  0xffA3
> +#define SOCFPGA_USB0_ADDRESS 0xffb0
> +#define SOCFPGA_USB1_ADDRESS 0xffb4
> +#define SOCFPGA_NANDREGS_ADDRESS 0xffb8
> +#define SOCFPGA_NANDDATA_ADDRESS 0xffb9
> +#define SOCFPGA_UART0_ADDRESS0xffc02000
> +#define SOCFPGA_UART1_ADDRESS0xffc02100
> +#define SOCFPGA_I2C0_ADDRESS 0xffc02800
> +#define SOCFPGA_I2C1_ADDRESS 0xffc02900
> +#define SOCFPGA_I2C2_ADDRESS 0xffc02a00
> +#define SOCFPGA_I2C3_ADDRESS 0xffc02b00
> +#define SOCFPGA_I2C4_ADDRESS 0xffc02c00
> +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
> +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
> +#define SOCFPGA_GPIO0_ADDRESS0xffc03200
> +#define SOCFPGA_GPIO1_ADDRESS0xffc03300
> +#define SOCFPGA_SYSTIMER0_ADDRESS0xffd0
> +#define SOCFPGA_SYSTIMER1_ADDRESS0xffd00100
> +#define SOCFPGA_L4WD0_ADDRESS0xffd00200
> +#define SOCFPGA_L4WD1_ADDRESS0xffd00300
> +#define SOCFPGA_L4WD2_ADDRESS0xffd00400
> +#define SOCFPGA_L4WD3_ADDRESS0xffd00500
> +#define SOCFPGA_GTIMER_SEC_ADDRESS   0xffd01000
> +#define SOCFPGA_GTIMER_NSEC_ADDRESS  0xffd02000
> +#define SOCFPGA_CLKMGR_ADDRESS   0xffd1
> +#define SOCFPGA_RSTMGR_ADDRESS   0xffd11000
> +#define SOCFPGA_SYSMGR_ADDRESS   0xffd12000
> +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS  0xffd13000
> +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda
> +#define SOCFPGA_DMASECURE_ADDRESS0xffda1000
> +#define SOCFPGA_SPIS0_ADDRESS0xffda2000
> +#define SOCFPGA_SPIS1_ADDRESS0xffda3000
> +#define SOCFPGA_SPIM0_ADDRESS0xffda4000
> +#define SOCFPGA_SPIM1_ADDRESS0xffda5000
> +#define SOCFPGA_OCRAM_ADDRESS0xffe0
> +#define GICD_BASE0xfffc1000
> +#define GICC_BASE0xfffc2000
> +
> +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [RESEND PATCH 1/3] pwm: sunxi: add support for PWM found on Allwinner A64 and H3

[Andre Przywara]

Hi,

On 19/09/17 09:53, Icenowy Zheng wrote:
> 
> 
> 于 2017年9月19日 GMT+08:00 下午4:51:32, Andre Przywara  写到:
>> Hi,
>>
>> On 19/09/17 06:06, Vasily Khoruzhick wrote:
>>> This commit adds basic support for PWM found on Allwinner A64 and H3
>>
>> Mmh, can you explain (for instance in a 0/3 email) what this is used
>> for? My understanding is that PWM0 (which is what you hard code here)
>> is
>> only exposed on PD22, which is also used for the MDC line to the
>> Ethernet PHY. All boards I heard of have Ethernet, so PWM0 is not
>> usable
>> there.
>> So is this for a special board?
> 
> Backlight for Pinebook.

Ah, right, forgot about that missing Ethernet there ...
Thanks for the heads up.

Cheers,
Andre.

>>>
>>> Signed-off-by: Vasily Khoruzhick 
>>> ---
>>>  arch/arm/include/asm/arch-sunxi/gpio.h |   1 +
>>>  arch/arm/include/asm/arch-sunxi/pwm.h  |  12 +++
>>>  arch/arm/mach-sunxi/board.c|  11 +++
>>>  drivers/pwm/Kconfig|   7 ++
>>>  drivers/pwm/Makefile   |   1 +
>>>  drivers/pwm/sunxi_pwm.c| 174
>> +
>>>  6 files changed, 206 insertions(+)
>>>  create mode 100644 drivers/pwm/sunxi_pwm.c
>>>
>>> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
>> b/arch/arm/include/asm/arch-sunxi/gpio.h
>>> index 24f85206c8..7265d18099 100644
>>> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
>>> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
>>> @@ -173,6 +173,7 @@ enum sunxi_gpio_number {
>>>  #define SUN8I_GPD_SDC1 3
>>>  #define SUNXI_GPD_LCD0 2
>>>  #define SUNXI_GPD_LVDS03
>>> +#define SUNXI_GPD_PWM  2
>>>  
>>>  #define SUN5I_GPE_SDC2 3
>>>  #define SUN8I_GPE_TWI2 3
>>> diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h
>> b/arch/arm/include/asm/arch-sunxi/pwm.h
>>> index 5884b5dbe7..673e0eb7b5 100644
>>> --- a/arch/arm/include/asm/arch-sunxi/pwm.h
>>> +++ b/arch/arm/include/asm/arch-sunxi/pwm.h
>>> @@ -11,8 +11,15 @@
>>>  #define SUNXI_PWM_CH0_PERIOD   (SUNXI_PWM_BASE + 4)
>>>  
>>>  #define SUNXI_PWM_CTRL_PRESCALE0(x)((x) & 0xf)
>>> +#define SUNXI_PWM_CTRL_PRESCALE0_MASK  (0xf)
>>>  #define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4)
>>>  #define SUNXI_PWM_CTRL_POLARITY0(x)((x) << 5)
>>> +#define SUNXI_PWM_CTRL_POLARITY0_MASK  (1 << 5)
>>> +#define SUNXI_PWM_CTRL_CLK_GATE(1 << 6)
>>> +
>>> +#define SUNXI_PWM_CH0_PERIOD_MAX   (0x)
>>> +#define SUNXI_PWM_CH0_PERIOD_PRD(x)((x & 0x) << 16)
>>> +#define SUNXI_PWM_CH0_PERIOD_DUTY(x)   ((x) & 0x)
>>>  
>>>  #define SUNXI_PWM_PERIOD_80PCT 0x04af03c0
>>>  
>>> @@ -31,4 +38,9 @@
>>>  #define SUNXI_PWM_MUX  SUN8I_GPH_PWM
>>>  #endif
>>>  
>>> +struct sunxi_pwm {
>>> +   u32 ctrl;
>>> +   u32 ch0_period;
>>> +};
>>> +
>>>  #endif
>>> diff --git a/arch/arm/mach-sunxi/board.c
>> b/arch/arm/mach-sunxi/board.c
>>> index 65b1ebd837..a85f973a46 100644
>>> --- a/arch/arm/mach-sunxi/board.c
>>> +++ b/arch/arm/mach-sunxi/board.c
>>> @@ -141,6 +141,16 @@ static int gpio_init(void)
>>> return 0;
>>>  }
>>>  
>>> +static int pwm_init(void)
>>> +{
>>> +#ifdef CONFIG_PWM_SUNXI
>>> +#ifdef CONFIG_MACH_SUN50I
>>> +   sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
>>
>> So this would probably kill Ethernet.
>> At the very least this should be somehow protected against this clash.
>> And I wonder if this should move into the PWM driver, for instance into
>> the .enable function.
>>
>> Cheers,
>> Andre.
>>
>>> +#endif
>>> +#endif
>>> +   return 0;
>>> +}
>>> +
>>>  #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) &&
>> defined(CONFIG_SPL_BUILD)
>>>  static int spl_board_load_image(struct spl_image_info *spl_image,
>>> struct spl_boot_device *bootdev)
>>> @@ -204,6 +214,7 @@ void s_init(void)
>>> clock_init();
>>> timer_init();
>>> gpio_init();
>>> +   pwm_init();
>>>  #ifndef CONFIG_DM_I2C
>>> i2c_init_board();
>>>  #endif
>>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>>> index e827558052..67e3f355e7 100644
>>> --- a/drivers/pwm/Kconfig
>>> +++ b/drivers/pwm/Kconfig
>>> @@ -43,3 +43,10 @@ config PWM_TEGRA
>>>   four channels with a programmable period and duty cycle. Only a
>>>   32KHz clock is supported by the driver but the duty cycle is
>>>   configurable.
>>> +
>>> +config PWM_SUNXI
>>> +   bool "Enable support for the Allwinner Sunxi PWM"
>>> +   depends on DM_PWM
>>> +   help
>>> + This PWM is found on A64 and other Allwinner SoCs. It supports a
>>> + programmable period and duty cycle. A 32-bit counter is used.
>>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>>> index 29d59916cb..1a8f8a58bc 100644
>>> --- a/drivers/pwm/Makefile
>>> +++ b/drivers/pwm/Makefile
>>> @@ -17,3 +17,4 @@ obj-$(CONFIG_PWM_IMX) += pwm-imx.o 
>>> pwm-imx-util.o
>>>  obj-$(CONFIG_PWM_ROCKCHIP) += 

[U-Boot] [PATCH 11/14] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add timer support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/timer.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index 253cde3..23450b0 100644
--- a/arch/arm/mach-socfpga/timer.c
+++ b/arch/arm/mach-socfpga/timer.c
@@ -1,5 +1,6 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2016-2017 Intel Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -10,15 +11,29 @@
 
 #define TIMER_LOAD_VAL 0x
 
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+#endif
 
 /*
  * Timer initialization
  */
 int timer_init(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+   int enable = 0x3;   /* timer enable + output signal masked */
+   int loadval = ~0;
+
+   /* enable system counter */
+   writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
+   /* enable processor pysical counter */
+   asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
+   asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
+
+#else
writel(TIMER_LOAD_VAL, _base->load_val);
writel(TIMER_LOAD_VAL, _base->curr_val);
writel(readl(_base->ctrl) | 0x3, _base->ctrl);
+#endif
return 0;
 }
-- 
2.2.2

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[U-Boot] [PATCH 07/14] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add mailbox support for Stratix SoC

Signed-off-by: Ley Foon Tan 
Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/Makefile   |   1 +
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 108 ++
 arch/arm/mach-socfpga/mailbox_s10.c  | 239 +++
 3 files changed, 348 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b253914..43e18d2 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += mailbox_s10.o
 obj-y  += misc_s10.o
 obj-y  += reset_manager_s10.o
 obj-y  += system_manager_s10.o
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h 
b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
new file mode 100644
index 000..b9bddf6
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+#ifndef _MAILBOX_S10_H_
+#define _MAILBOX_S10_H_
+
+/* user define Uboot ID */
+#define MBOX_CLIENT_ID_UBOOT   0xB
+#define MBOX_ID_UBOOT  0x1
+
+#define MBOX_MAX_CMD_INDEX 2047
+#define MBOX_CMD_BUFFER_SIZE   32
+#define MBOX_RESP_BUFFER_SIZE  16
+
+#define MBOX_HDR_CMD_LSB   0
+#define MBOX_HDR_CMD_MSK   (BIT(11) - 1)
+#define MBOX_HDR_I_LSB 11
+#define MBOX_HDR_I_MSK BIT(11)
+#define MBOX_HDR_LEN_LSB   12
+#define MBOX_HDR_LEN_MSK   0x007FF000
+#define MBOX_HDR_ID_LSB24
+#define MBOX_HDR_ID_MSK0x0F00
+#define MBOX_HDR_CLIENT_LSB28
+#define MBOX_HDR_CLIENT_MSK0xF000
+
+/* Interrupt flags */
+#define MBOX_FLAGS_INT_COE BIT(0)  /* COUT update interrupt enable */
+#define MBOX_FLAGS_INT_RIE BIT(1)  /* RIN update interrupt enable */
+#define MBOX_FLAGS_INT_UAE BIT(8)  /* Urgent ACK interrupt enable */
+#define MBOX_ALL_INTRS (MBOX_FLAGS_INT_COE | \
+MBOX_FLAGS_INT_RIE | \
+MBOX_FLAGS_INT_UAE)
+
+/* Status */
+#define MBOX_STATUS_UA_MSK BIT(8)
+
+#define MBOX_CMD_HEADER(client, id, len, cmd) \
+   (((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
+   (((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
+   (((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)| \
+   (((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)
+
+#define MBOX_RESP_ERR_GET(resp)\
+   (((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
+#define MBOX_RESP_LEN_GET(resp)\
+   (((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
+#define MBOX_RESP_ID_GET(resp) \
+   (((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
+#define MBOX_RESP_CLIENT_GET(resp) \
+   (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
+
+/* Response error list */
+typedef enum {
+   /* CMD completed succesfully, but check resp ARGS for any errors */
+   MBOX_RESP_STATOK = 0,
+   /* CMD is incorrectly formatted in some way */
+   MBOX_RESP_INVALID_COMMAND = 1,
+   /* BootROM Command code not undesrtood */
+   MBOX_RESP_UNKNOWN_BR = 2,
+   /* CMD code not recognized by firmware */
+   MBOX_RESP_UNKNOWN = 3,
+   /* Indicates that the device is not configured */
+   MBOX_RESP_NOT_CONFIGURED = 256,
+   /* Indicates that the device is busy */
+   MBOX_RESP_DEVICE_BUSY = 0x1FF,
+   /* Indicates that there is no valid response available */
+   MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
+   /* General Error */
+   MBOX_RESP_ERROR = 0x3FF,
+} ALT_SDM_MBOX_RESP_CODE;
+
+/* Mailbox command list */
+#define MBOX_RESTART   2
+#define MBOX_QSPI_OPEN 50
+#define MBOX_QSPI_CLOSE51
+#define MBOX_QSPI_DIRECT   59
+
+struct socfpga_mailbox {
+   u32 cin;/* command valid offset */
+   u32 rout;   /* response output offset */
+   u32 urg;/* urgent command */
+   u32 flags;  /* interrupt enables */
+   u32 pad_0x10_0x1f[4];   /* 0x10 - 0x1F reserved */
+   u32 cout;   /* command free offset */
+   u32 rin;/* respond valid offset */
+   u32 pad_0x28;   /* 0x28 reserved */
+   u32 status; /* mailbox status */
+   u32 pad_0x30_0x3f[4];   /* 0x30 - 0x3F reserved */
+   u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];  /* 0x40 - 0xBC circular command
+  buffer to SDM */
+   u32 resp_buf[MBOX_RESP_BUFFER_SIZE];/* 0xC0 

[U-Boot] [PATCH 12/14] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add DDR support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 +
 drivers/ddr/altera/Makefile|   1 +
 drivers/ddr/altera/sdram_s10.c | 382 +
 3 files changed, 716 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 drivers/ddr/altera/sdram_s10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
new file mode 100644
index 000..d0fd958
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -0,0 +1,333 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SDRAM_S10_H_
+#define_SDRAM_S10_H_
+
+unsigned long sdram_calculate_size(void);
+int sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+#define DDR_TWR15
+#define DDR_READ_LATENCY_DELAY 40
+#define DDR_ACTIVATE_FAWBANK   0x1
+
+
+struct socfpga_ecc_hmc {
+   uint32_t ip_rev_id;
+   uint32_t _pad_0x4_0x7;
+   uint32_t ddrioctrl;
+   uint32_t ddrcalstat;
+   uint32_t mpr_0beat1;
+   uint32_t mpr_1beat1;
+   uint32_t mpr_2beat1;
+   uint32_t mpr_3beat1;
+   uint32_t mpr_4beat1;
+   uint32_t mpr_5beat1;
+   uint32_t mpr_6beat1;
+   uint32_t mpr_7beat1;
+   uint32_t mpr_8beat1;
+   uint32_t mpr_0beat2;
+   uint32_t mpr_1beat2;
+   uint32_t mpr_2beat2;
+   uint32_t mpr_3beat2;
+   uint32_t mpr_4beat2;
+   uint32_t mpr_5beat2;
+   uint32_t mpr_6beat2;
+   uint32_t mpr_7beat2;
+   uint32_t mpr_8beat2;
+   uint32_t _pad_0x58_0x5f[2];
+   uint32_t auto_precharge;
+   uint32_t _pad_0x64_0xdf[31];
+   uint32_t dramaddrwidth;
+   uint32_t _pad_0xe4_0xff[7];
+   uint32_t eccctrl;
+   uint32_t eccctrl2;
+   uint32_t _pad_0x108_0x10f[2];
+   uint32_t errinten;
+   uint32_t errintens;
+   uint32_t errintenr;
+   uint32_t intmode;
+   uint32_t intstat;
+   uint32_t diaginttest;
+   uint32_t modstat;
+   uint32_t derraddra;
+   uint32_t serraddra;
+   uint32_t _pad_0x134_0x137;
+   uint32_t autowb_corraddr;
+   uint32_t serrcntreg;
+   uint32_t autowb_drop_cntreg;
+   uint32_t ecc_reg2wreccdatabus;
+   uint32_t ecc_rdeccdata2regbus;
+   uint32_t ecc_reg2rdeccdatabus;
+   uint32_t ecc_diagon;
+   uint32_t ecc_decstat;
+   uint32_t _pad_0x158_0x15f[2];
+   uint32_t ecc_errgenaddr_0;
+   uint32_t ecc_errgenaddr_1;
+   uint32_t ecc_errgenaddr_2;
+   uint32_t ecc_errgenaddr_3;
+   uint32_t ecc_ref2rddatabus_beat0;
+   uint32_t ecc_ref2rddatabus_beat1;
+   uint32_t ecc_ref2rddatabus_beat2;
+   uint32_t ecc_ref2rddatabus_beat3;
+   uint32_t ecc_errgenhaddr_0;
+   uint32_t ecc_errgenhaddr_1;
+   uint32_t ecc_errgenhaddr_2;
+   uint32_t ecc_errgenhaddr_3;
+   uint32_t ecc_rdeccdata2regbus_beat0;
+   uint32_t ecc_rdeccdata2regbus_beat1;
+   uint32_t ecc_rdeccdata2regbus_beat2;
+   uint32_t ecc_rdeccdata2regbus_beat3;
+   uint32_t _pad_0x1a0_0x1af[4];
+   uint32_t derrhaddr;
+   uint32_t serrhaddr;
+   uint32_t _pad_0x1b8_0x1bb;
+   uint32_t autowb_corrhaddr;
+   uint32_t _pad_0x1c0_0x20f[20];
+   uint32_t hpsintfcsel;
+   uint32_t rsthandshakectrl;
+   uint32_t rsthandshakestat;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   uint32_t main_scheduler_id_coreid;
+   uint32_t main_scheduler_id_revisionid;
+   uint32_t main_scheduler_ddrconf;
+   uint32_t main_scheduler_ddrtiming;
+   uint32_t main_scheduler_ddrmode;
+   uint32_t main_scheduler_readlatency;
+   uint32_t _pad_0x18_0x37[8];
+   uint32_t main_scheduler_activate;
+   uint32_t main_scheduler_devtodev;
+   uint32_t main_scheduler_ddr4timing;
+};
+
+struct socfpga_io48_mmr {
+   uint32_t dbgcfg0;
+   uint32_t dbgcfg1;
+   uint32_t dbgcfg2;
+   uint32_t dbgcfg3;
+   uint32_t dbgcfg4;
+   uint32_t dbgcfg5;
+   uint32_t dbgcfg6;
+   uint32_t reserve0;
+   uint32_t reserve1;
+   uint32_t reserve2;
+   uint32_t ctrlcfg0;
+   uint32_t ctrlcfg1;
+   uint32_t ctrlcfg2;
+   uint32_t ctrlcfg3;
+   uint32_t ctrlcfg4;
+   uint32_t ctrlcfg5;
+   uint32_t ctrlcfg6;
+   uint32_t ctrlcfg7;
+   uint32_t ctrlcfg8;
+   uint32_t ctrlcfg9;
+   uint32_t dramtiming0;
+   uint32_t dramodt0;
+   uint32_t dramodt1;
+   uint32_t sbcfg0;
+   uint32_t sbcfg1;
+   uint32_t sbcfg2;
+   uint32_t sbcfg3;
+   uint32_t sbcfg4;
+   uint32_t sbcfg5;
+   uint32_t sbcfg6;
+   uint32_t sbcfg7;
+   uint32_t caltiming0;
+  

[U-Boot] [PATCH 09/14] arm: socfpga: Restructure the SPL file

[chin . liang . see]

From: Chin Liang See 

Restructure the SPL so each devices such as CV, A10 and S10
will have their own dedicated SPL file. SPL file determine
the HW initialization flow which is device specific

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/Makefile  |   5 +-
 arch/arm/mach-socfpga/spl_a10.c | 105 
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c} |  46 
 3 files changed, 109 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/spl_a10.c
 rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (83%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 098e5e9..b669d43 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -41,13 +41,16 @@ obj-y   += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
-obj-y  += spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += spl_gen5.o
 obj-y  += freeze_controller.o
 obj-y  += wrap_iocsr_config.o
 obj-y  += wrap_pinmux_config.o
 obj-y  += wrap_sdram_config.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y  += spl_a10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
new file mode 100644
index 000..e6fc766
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -0,0 +1,105 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_system_manager *sysmgr_regs =
+   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+u32 spl_boot_device(void)
+{
+   const u32 bsel = readl(_regs->bootinfo);
+
+   switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+   case 0x1:   /* FPGA (HPS2FPGA Bridge) */
+   return BOOT_DEVICE_RAM;
+   case 0x2:   /* NAND Flash (1.8V) */
+   case 0x3:   /* NAND Flash (3.0V) */
+   socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+   return BOOT_DEVICE_NAND;
+   case 0x4:   /* SD/MMC External Transceiver (1.8V) */
+   case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+   socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+   socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+   return BOOT_DEVICE_MMC1;
+   case 0x6:   /* QSPI Flash (1.8V) */
+   case 0x7:   /* QSPI Flash (3.0V) */
+   socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+   return BOOT_DEVICE_SPI;
+   default:
+   printf("Invalid boot device (bsel=%08x)!\n", bsel);
+   hang();
+   }
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+   return MMCSD_MODE_FS;
+#else
+   return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void spl_board_init(void)
+{
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   socfpga_reset_uart(0);
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   socfpga_watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   socfpga_reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+}
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl_gen5.c
similarity index 83%
rename from arch/arm/mach-socfpga/spl.c
rename to arch/arm/mach-socfpga/spl_gen5.c
index 71bae82..9864082 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -22,21 +22,15 @@
 #include 
 #include 
 #include 
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#include 
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#endif
-
 static const struct socfpga_system_manager *sysmgr_regs =
(struct 

[U-Boot] [PATCH 05/14] arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add pinmux driver support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/Makefile |   2 +
 .../arm/mach-socfpga/include/mach/system_manager.h |   5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h | 169 +
 arch/arm/mach-socfpga/system_manager_s10.c |  91 +++
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c |  55 +++
 5 files changed, 321 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index f10b05c..910eb6f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -33,6 +33,8 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
 obj-y  += reset_manager_s10.o
+obj-y  += system_manager_s10.o
+obj-y  += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e6d4280..80c7d0b 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -7,6 +7,9 @@
 #ifndef _SYSTEM_MANAGER_H_
 #define _SYSTEM_MANAGER_H_
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include 
+#else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIOBIT(1)
 #define SYSMGR_ECC_OCRAM_ENBIT(0)
@@ -89,5 +92,5 @@
 
 #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
-
+#endif
 #endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
new file mode 100644
index 000..d992072
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SYSTEM_MANAGER_S10_
+#define_SYSTEM_MANAGER_S10_
+
+void sysmgr_pinmux_init(void);
+void populate_sysmgr_fpgaintf_module(void);
+void populate_sysmgr_pinmux(void);
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
+
+struct socfpga_system_manager {
+   /* System Manager Module */
+   u32 siliconid1; /* 0x00 */
+   u32 siliconid2;
+   u32 wddbg;
+   u32 _pad_0xc;
+   u32 mpu_status; /* 0x10 */
+   u32 mpu_ace;
+   u32 _pad_0x18_0x1c[2];
+   u32 dma;/* 0x20 */
+   u32 dma_periph;
+   /* SDMMC Controller Group */
+   u32 sdmmcgrp_ctrl;
+   u32 sdmmcgrp_l3master;
+   /* NAND Flash Controller Register Group */
+   u32 nandgrp_bootstrap;  /* 0x30 */
+   u32 nandgrp_l3master;
+   /* USB Controller Group */
+   u32 usb0_l3master;
+   u32 usb1_l3master;
+   /* EMAC Group */
+   u32 emac_gbl;   /* 0x40 */
+   u32 emac0;
+   u32 emac1;
+   u32 emac2;
+   u32 emac0_ace;  /* 0x50 */
+   u32 emac1_ace;
+   u32 emac2_ace;
+   u32 nand_axuser;
+   u32 _pad_0x60_0x64[2];  /* 0x60 */
+   /* FPGA interface Group */
+   u32 fpgaintf_en_1;
+   u32 fpgaintf_en_2;
+   u32 fpgaintf_en_3;  /* 0x70 */
+   u32 dma_l3master;
+   u32 etr_l3master;
+   u32 _pad_0x7c;
+   u32 sec_ctrl_slt;   /* 0x80 */
+   u32 osc_trim;
+   u32 _pad_0x88_0x8c[2];
+   /* ECC Group */
+   u32 ecc_intmask_value;  /* 0x90 */
+   u32 ecc_intmask_set;
+   u32 ecc_intmask_clr;
+   u32 ecc_intstatus_serr;
+   u32 ecc_intstatus_derr; /* 0xa0 */
+   u32 _pad_0xa4_0xac[3];
+   u32 noc_addr_remap; /* 0xb0 */
+   u32 hmc_clk;
+   u32 io_pa_ctrl;
+   u32 _pad_0xbc;
+   /* NOC Group */
+   u32 noc_timeout;/* 0xc0 */
+   u32 noc_idlereq_set;
+   u32 noc_idlereq_clr;
+   u32 noc_idlereq_value;
+   u32 noc_idleack;/* 0xd0 */
+   u32 noc_idlestatus;
+   u32 fpga2soc_ctrl;
+   u32 

[U-Boot] [PATCH 08/14] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add MMU support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/Makefile|  1 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++
 2 files changed, 72 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 43e18d2..098e5e9 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
 obj-y  += mailbox_s10.o
 obj-y  += misc_s10.o
+obj-y  += mmu-arm64_s10.o
 obj-y  += reset_manager_s10.o
 obj-y  += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c 
b/arch/arm/mach-socfpga/mmu-arm64_s10.c
new file mode 100644
index 000..91c7f2e
--- /dev/null
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+   {
+   /* MEM 2GB*/
+   .virt   = 0x0UL,
+   .phys   = 0x0UL,
+   .size   = 0x8000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* FPGA 1.5GB */
+   .virt   = 0x8000UL,
+   .phys   = 0x8000UL,
+   .size   = 0x6000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* DEVICE 142MB */
+   .virt   = 0xF700UL,
+   .phys   = 0xF700UL,
+   .size   = 0x08E0UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* OCRAM 1MB but available 256KB */
+   .virt   = 0xFFE0UL,
+   .phys   = 0xFFE0UL,
+   .size   = 0x0010UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* DEVICE 32KB */
+   .virt   = 0xFFFCUL,
+   .phys   = 0xFFFCUL,
+   .size   = 0x8000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* MEM 124GB */
+   .virt   = 0x01UL,
+   .phys   = 0x01UL,
+   .size   = 0x1FUL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* DEVICE 4GB */
+   .virt   = 0x20UL,
+   .phys   = 0x20UL,
+   .size   = 0x01UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* List terminator */
+   },
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;
-- 
2.2.2

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[U-Boot] [PATCH 13/14] board: altera: stratix10: Add socdk board support for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add socdk board support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 board/altera/stratix10-socdk/MAINTAINERS | 7 +++
 board/altera/stratix10-socdk/Makefile| 7 +++
 board/altera/stratix10-socdk/socfpga.c   | 7 +++
 3 files changed, 21 insertions(+)
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c

diff --git a/board/altera/stratix10-socdk/MAINTAINERS 
b/board/altera/stratix10-socdk/MAINTAINERS
new file mode 100644
index 000..6192bc9
--- /dev/null
+++ b/board/altera/stratix10-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chin-Liang See 
+M: Dinh Nguyen 
+S: Maintained
+F: board/altera/stratix10-socdk/
+F: include/configs/socfpga_stratix10_socdk.h
+F: configs/socfpga_stratix10_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile 
b/board/altera/stratix10-socdk/Makefile
new file mode 100644
index 000..02a9cad
--- /dev/null
+++ b/board/altera/stratix10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016-2017 Intel Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c 
b/board/altera/stratix10-socdk/socfpga.c
new file mode 100644
index 000..3deb989
--- /dev/null
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
-- 
2.2.2

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[U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add Clock Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/Makefile |   4 +
 arch/arm/mach-socfpga/clock_manager.c  |   4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c  | 359 +
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  | 202 
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c|  46 +++
 7 files changed, 644 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..e5f9dd7 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -30,6 +30,10 @@ obj-y+= pinmux_arria10.o
 obj-y  += reset_manager_arria10.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += clock_manager_s10.o
+obj-y  += wrap_pll_config_s10.o
+endif
 ifdef CONFIG_SPL_BUILD
 obj-y  += spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index cb6ae03..f9450a4 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)
do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
inter_val = readl(_manager_base->inter) & mask;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
inter_val = readl(_manager_base->stat) & mask;
 #endif
/* Wait for stable lock */
@@ -52,7 +52,7 @@ int set_cpu_clk_info(void)
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
gd->bd->bi_ddr_freq = 0;
 #endif
 
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c 
b/arch/arm/mach-socfpga/clock_manager_s10.c
new file mode 100644
index 000..a9f9b07
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -0,0 +1,359 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_clock_manager *clock_manager_base =
+   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void cm_write_bypass_mainpll(uint32_t val)
+{
+   writel(val, _manager_base->main_pll.bypass);
+   cm_wait_for_fsm();
+}
+static void cm_write_bypass_perpll(uint32_t val)
+{
+   writel(val, _manager_base->per_pll.bypass);
+   cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void cm_write_ctrl(uint32_t val)
+{
+   writel(val, _manager_base->ctrl);
+   cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ */
+void cm_basic_init(const struct cm_config * const cfg)
+{
+   uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;
+
+   if (cfg == 0)
+   return;
+
+   /* Put all plls in bypass */
+   cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
+   cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
+
+   /* setup main PLL dividers */
+   /* calculate the vcocalib value */
+   mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+   CLKMGR_FDBCK_MDIV_MASK;
+   refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+   mscnt = 200 / (6 + mdiv) / refclkdiv;
+   hscnt = (mdiv + 6) * mscnt / refclkdiv - 9;
+   vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+  CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+   writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+   ~CLKMGR_PLLGLOB_RST_MASK),
+   _manager_base->main_pll.pllglob);
+   writel(cfg->main_pll_fdbck, _manager_base->main_pll.fdbck);
+   writel(vcocalib, _manager_base->main_pll.vcocalib);
+   writel(cfg->main_pll_pllc0, _manager_base->main_pll.pllc0);
+   writel(cfg->main_pll_pllc1, _manager_base->main_pll.pllc1);
+   writel(cfg->main_pll_nocdiv, _manager_base->main_pll.nocdiv);
+
+   /* setup peripheral PLL dividers */
+   /* calculate the vcocalib value */
+   mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+   CLKMGR_FDBCK_MDIV_MASK;
+   

[U-Boot] [PATCH 10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add SPL driver support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/Makefile |   4 +
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   4 +
 arch/arm/mach-socfpga/include/mach/firewall_s10.h  |  84 +
 arch/arm/mach-socfpga/spl_s10.c| 138 +
 4 files changed, 230 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b669d43..35b124a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -40,6 +40,7 @@ obj-y += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y  += spl_gen5.o
@@ -51,6 +52,9 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y  += spl_a10.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += spl_s10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
index feb1881..d79b9cd 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -45,6 +45,10 @@
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA  0xffd21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA0xffd21300
 #define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
 #define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
 #define SOCFPGA_SPIS0_ADDRESS  0xffda2000
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h 
b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
new file mode 100644
index 000..6894bb9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_FIREWALL_S10_
+#define_FIREWALL_S10_
+
+struct socfpga_firwall_l4_per {
+   u32 nand;   /* 0x00 */
+   u32 nand_data;
+   u32 _pad_0x8;
+   u32 usb0;
+   u32 usb1;   /* 0x10 */
+   u32 _pad_0x14;
+   u32 _pad_0x18;
+   u32 spim0;
+   u32 spim1;  /* 0x20 */
+   u32 spis0;
+   u32 spis1;
+   u32 emac0;
+   u32 emac1;  /* 0x30 */
+   u32 emac2;
+   u32 _pad_0x38;
+   u32 _pad_0x3c;
+   u32 sdmmc;  /* 0x40 */
+   u32 gpio0;
+   u32 gpio1;
+   u32 _pad_0x4c;
+   u32 i2c0;   /* 0x50 */
+   u32 i2c1;
+   u32 i2c2;
+   u32 i2c3;
+   u32 i2c4;   /* 0x60 */
+   u32 timer0;
+   u32 timer1;
+   u32 uart0;
+   u32 uart1;  /* 0x70 */
+};
+
+struct socfpga_firwall_l4_sys {
+   u32 _pad_0x00;  /* 0x00 */
+   u32 _pad_0x04;
+   u32 dma_ecc;
+   u32 emac0rx_ecc;
+   u32 emac0tx_ecc;/* 0x10 */
+   u32 emac1rx_ecc;
+   u32 emac1tx_ecc;
+   u32 emac2rx_ecc;
+   u32 emac2tx_ecc;/* 0x20 */
+   u32 _pad_0x24;
+   u32 _pad_0x28;
+   u32 nand_ecc;
+   u32 nand_read_ecc;  /* 0x30 */
+   u32 nand_write_ecc;
+   u32 ocram_ecc;
+   u32 _pad_0x3c;
+   u32 sdmmc_ecc;  /* 0x40 */
+   u32 usb0_ecc;
+   u32 usb1_ecc;
+   u32 clock_manager;
+   u32 _pad_0x50;  /* 0x50 */
+   u32 io_manager;
+   u32 reset_manager;
+   u32 system_manager;
+   u32 osc0_timer; /* 0x60 */
+   u32 osc1_timer;
+   u32 watchdog0;
+   u32 watchdog1;
+   u32 watchdog2;  /* 0x70 */
+   u32 watchdog3;
+};
+
+#define FIREWALL_L4_DISABLE_ALL(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_BRIDGE_DISABLE_ALL(~0)
+
+#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR 0xf7004688
+#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR  0xf7018628
+
+#define CCU_ADMASK_P_MASK  (BIT(0))
+#define CCU_ADMASK_NS_MASK (BIT(1))
+
+#endif /* _FIREWALL_S10_ */
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
new file mode 100644
index 000..12cafe6
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -0,0 +1,138 @@

[U-Boot] [PATCH 14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build

[chin . liang . see]

From: Chin Liang See 

Add build support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/Kconfig  |   8 +-
 arch/arm/mach-socfpga/Kconfig |  13 ++
 configs/socfpga_stratix10_defconfig   |  39 ++
 include/configs/socfpga_stratix10_socdk.h | 216 ++
 4 files changed, 273 insertions(+), 3 deletions(-)
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bb64b9c..13dd144 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -655,21 +655,23 @@ config ARCH_SNAPDRAGON
 
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
-   select CPU_V7
+   select CPU_V7 if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+   select ARM64 if TARGET_SOCFPGA_STRATIX10
select SUPPORT_SPL
select OF_CONTROL
select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
-   select ENABLE_ARM_SOC_BOOT0_HOOK
+   select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || 
TARGET_SOCFPGA_ARRIA10
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
-   select SYS_THUMB_BUILD
+   select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
imply CMD_MTDPARTS
imply CRC32_VERIFY
imply FAT_WRITE
+   select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
 
 config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 45e5379..03ab956 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -49,6 +49,12 @@ config TARGET_SOCFPGA_GEN5
bool
select ALTERA_SDRAM
 
+config TARGET_SOCFPGA_STRATIX10
+   bool
+   select ARMV8_MULTIENTRY
+   select ARMV8_SPIN_TABLE
+   select ARMV8_SET_SMPEN
+
 choice
prompt "Altera SOCFPGA board select"
optional
@@ -86,6 +92,10 @@ config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+   bool "Intel SOCFPGA SoCDK (Stratix 10)"
+   select TARGET_SOCFPGA_STRATIX10
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -116,12 +126,14 @@ config SYS_BOARD
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
+   default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+   default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
@@ -145,6 +157,7 @@ config SYS_CONFIG_NAME
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+   default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif
diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
new file mode 100644
index 000..e5a7a69
--- /dev/null
+++ b/configs/socfpga_stratix10_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_stratix10"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_MMC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DFU_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_CADENCE_QSPI=y
+CONFIG_DM_ETH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
new file mode 100644
index 000..0d955f8
--- /dev/null
+++ 

[U-Boot] [PATCH 06/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add misc support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/Makefile   |   1 +
 arch/arm/mach-socfpga/misc.c |   4 +
 arch/arm/mach-socfpga/misc_s10.c | 165 +++
 3 files changed, 170 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 910eb6f..b253914 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += misc_s10.o
 obj-y  += reset_manager_s10.o
 obj-y  += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 00eff90..2ea94bc 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -23,8 +23,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#endif
 
 struct bsel bsel_str[] = {
{ "rsvd", "Reserved", },
@@ -53,6 +55,7 @@ void enable_caches(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
/* Disable the L2 cache */
@@ -73,6 +76,7 @@ void v7_outer_cache_disable(void)
/* Disable the L2 cache */
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
+#endif
 
 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
new file mode 100644
index 000..b84f055
--- /dev/null
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE
+void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode)
+{
+   /* Put the emac we're using into reset.
+* This is required before configuring the PHY interface
+*/
+   socfpga_emac_manage_reset(of_reset_id, 1);
+
+   clrsetbits_le32(_regs->emac0 + (of_reset_id - EMAC0_RESET),
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+
+   socfpga_emac_manage_reset(of_reset_id, 0);
+}
+
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+   if (!phymode)
+   return -EINVAL;
+
+   if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+   return 0;
+   }
+
+   if (!strcmp(phymode, "rgmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+   return 0;
+   }
+
+   if (!strcmp(phymode, "rmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+   return 0;
+   }
+
+   return -EINVAL;
+}
+
+static int socfpga_eth_reset(void)
+{
+   const void *fdt = gd->fdt_blob;
+   struct fdtdec_phandle_args args;
+   const char *phy_mode;
+   u32 phy_modereg;
+   int nodes[2];   /* Max. 3 GMACs */
+   int ret, count;
+   int i, node;
+
+   count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+  COMPAT_ALTERA_SOCFPGA_DWMAC,
+  nodes, ARRAY_SIZE(nodes));
+   for (i = 0; i < count; i++) {
+   node = nodes[i];
+   if (node <= 0)
+   continue;
+
+   ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+"#reset-cells", 1, 0,
+);
+   if (ret || (args.args_count != 1)) {
+   debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+   continue;
+   }
+
+   phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+   ret = dwmac_phymode_to_modereg(phy_mode, _modereg);
+   if (ret) {
+   debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+   continue;
+   }
+
+   dwmac_deassert_reset(args.args[0], phy_modereg);
+   }
+
+   return 0;
+}
+#else
+static int socfpga_eth_reset(void)
+{
+   return 0;
+};
+#endif
+
+/*
+ * Print CPU information
+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+   

[U-Boot] [PATCH 04/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/Makefile |   1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 +
 arch/arm/mach-socfpga/reset_manager.c  |   5 +
 arch/arm/mach-socfpga/reset_manager_s10.c  | 140 +
 include/dt-bindings/reset/altr,rst-mgr-s10.h   |  97 ++
 6 files changed, 361 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e5f9dd7..f10b05c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += reset_manager_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6591745..577fcce 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include 
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
new file mode 100644
index 000..07ada59
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_RESET_MANAGER_S10_
+#define_RESET_MANAGER_S10_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+   u32 status;
+   u32 mpu_rst_stat;
+   u32 misc_stat;
+   u32 padding1;
+   u32 hdsk_en;
+   u32 hdsk_req;
+   u32 hdsk_ack;
+   u32 hdsk_stall;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in S10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
+   u32 brg_mod_reset;
+   u32 padding2;
+   u32 cold_mod_reset;
+   u32 padding3;
+   u32 dbg_mod_reset;
+   u32 tap_mod_reset;
+   u32 padding4;
+   u32 padding5;
+   u32 brg_warm_mask;
+   u32 padding6[3];
+   u32 tst_stat;
+   u32 padding7;
+   u32 hdsk_timeout;
+   u32 mpul2flushtimeout;
+   u32 dbghdsktimeout;
+};
+
+#define RSTMGR_MPUMODRST_CORE0 0
+#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK   0X0040
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET 8
+#define RSTMGR_BANK_MASK   0x7
+#define RSTMGR_RESET_OFFSET0
+#define RSTMGR_RESET_MASK  0x1f
+#define RSTMGR_DEFINE(_bank, _offset)  \
+   ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset)   \
+   (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset)\
+   (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_USB0RSTMGR_DEFINE(1, 3)
+#define RSTMGR_USB1RSTMGR_DEFINE(1, 4)
+#define RSTMGR_NANDRSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_EMAC0_OCP   RSTMGR_DEFINE(1, 8)
+#define RSTMGR_EMAC1_OCP   RSTMGR_DEFINE(1, 9)
+#define RSTMGR_EMAC2_OCP   RSTMGR_DEFINE(1, 10)
+#define RSTMGR_USB0_OCPRSTMGR_DEFINE(1, 11)
+#define RSTMGR_USB1_OCPRSTMGR_DEFINE(1, 12)
+#define RSTMGR_NAND_OCPRSTMGR_DEFINE(1, 13)
+#define RSTMGR_SDMMC_OCP   

[U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Device tree for Stratix10 SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/dts/Makefile|   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts | 141 +++
 2 files changed, 143 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fee4680..4cf5fd0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts 
b/arch/arm/dts/socfpga_stratix10_socdk.dts
new file mode 100644
index 000..484c630
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
+   compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   aliases {
+   ethernet0 = 
+   spi0 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x8000>; /* 2GB */
+   };
+
+   regulator_3_3v: 3-3-v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   ranges;
+   u-boot,dm-pre-reloc;
+
+   rst: rstmgr@ffd11000 {
+   #reset-cells = <1>;
+   compatible = "altr,rst-mgr";
+   reg = <0xffd11000 0x100>;
+   altr,modrst-offset = <0x20>;
+   };
+
+   gmac0: ethernet@ff80 {
+   compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", 
"snps,dwmac";
+   reg = <0xff80 0x2000>;
+   interrupts = <0 90 4>;
+   interrupt-names = "macirq";
+   mac-address = [00 00 00 00 00 00];
+   resets = < EMAC0_RESET>;
+   reset-names = "stmmaceth";
+   phy-mode = "rgmii";
+   phy-addr = <0x>; /* probe for phy addr */
+   max-speed = <1000>;
+   txd0-skew-ps = <0>; /* -420ps */
+   txd1-skew-ps = <0>; /* -420ps */
+   txd2-skew-ps = <0>; /* -420ps */
+   txd3-skew-ps = <0>; /* -420ps */
+   rxd0-skew-ps = <420>; /* 0ps */
+   rxd1-skew-ps = <420>; /* 0ps */
+   rxd2-skew-ps = <420>; /* 0ps */
+   rxd3-skew-ps = <420>; /* 0ps */
+   txen-skew-ps = <0>; /* -420ps */
+   txc-skew-ps = <1860>; /* 960ps */
+   rxdv-skew-ps = <420>; /* 0ps */
+   rxc-skew-ps = <1680>; /* 780ps */
+   status = "okay";
+   };
+
+   mmc0: dwmmc0@0xff808000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "altr,socfpga-dw-mshc";
+   reg = <0xff808000 0x1000>;
+   interrupts = <0 96 4>;
+   num-slots = <1>;
+   broken-cd;
+   bus-width = <4>;
+   fifo-depth = <0x400>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   drvsel = <3>;
+   smplsel = <0>;
+   status = "okay";
+   u-boot,dm-pre-reloc;
+   vmmc-supply = <_3_3v>;
+   vqmmc-supply = <_3_3v>;
+   };
+
+   uart0: serial0@ffc02000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0xffc02000 0x1000>;
+  

[U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add the base address map for Statix10 SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58 ++
 1 file changed, 58 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100644
index 000..feb1881
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS   0xf801
+#define SOCFPGA_SDR_ADDRESS0xf8011000
+#define SOCFPGA_SMMU_ADDRESS   0xfa00
+#define SOCFPGA_EMAC0_ADDRESS  0xff80
+#define SOCFPGA_EMAC1_ADDRESS  0xff802000
+#define SOCFPGA_EMAC2_ADDRESS  0xff804000
+#define SOCFPGA_SDMMC_ADDRESS  0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS   0xff8d2000
+#define SOCFPGA_QSPIDATA_ADDRESS   0xff90
+#define SOCFPGA_MAILBOX_ADDRESS0xffA3
+#define SOCFPGA_USB0_ADDRESS   0xffb0
+#define SOCFPGA_USB1_ADDRESS   0xffb4
+#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
+#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
+#define SOCFPGA_UART0_ADDRESS  0xffc02000
+#define SOCFPGA_UART1_ADDRESS  0xffc02100
+#define SOCFPGA_I2C0_ADDRESS   0xffc02800
+#define SOCFPGA_I2C1_ADDRESS   0xffc02900
+#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
+#define SOCFPGA_SYSTIMER1_ADDRESS  0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS  0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS  0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS  0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
+#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS  0xffe0
+#define GICD_BASE  0xfffc1000
+#define GICC_BASE  0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
2.2.2

___
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[U-Boot] [PATCH 00/14] Enable Stratix10 SoC support

[chin . liang . see]

From: Chin Liang See 

This patch series are enabling support for Stratix 10 SoC

Chin Liang See (14):
  arm: socfpga: stratix10: Add base address map for Statix10 SoC
  arm: dts: Add dts for Stratix10 SoC
  arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC
  arm: socfpga: stratix10: Add misc support for Stratix10 SoC
  arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC
  arm: socfpga: stratix10: Add MMU support for Stratix10 SoC
  arm: socfpga: Restructure the SPL file
  arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC
  arm: socfpga: stratix10: Add timer support for Stratix10 SoC
  ddr: altera: stratix10: Add DDR support for Stratix10 SoC
  board: altera: stratix10: Add socdk board support for Stratix10 SoC
  arm: socfpga: stratix10: Enable Stratix10 SoC build

 arch/arm/Kconfig   |   8 +-
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts   | 141 
 arch/arm/mach-socfpga/Kconfig  |  13 +
 arch/arm/mach-socfpga/Makefile |  19 +-
 arch/arm/mach-socfpga/clock_manager.c  |   4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c  | 359 +++
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |  62 
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  | 202 +++
 arch/arm/mach-socfpga/include/mach/firewall_s10.h  |  84 +
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h   | 108 ++
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 +++
 arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 ++
 .../arm/mach-socfpga/include/mach/system_manager.h |   5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h | 169 +
 arch/arm/mach-socfpga/mailbox_s10.c| 239 +
 arch/arm/mach-socfpga/misc.c   |   4 +
 arch/arm/mach-socfpga/misc_s10.c   | 165 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c  |  71 
 arch/arm/mach-socfpga/reset_manager.c  |   5 +
 arch/arm/mach-socfpga/reset_manager_s10.c  | 140 
 arch/arm/mach-socfpga/spl_a10.c| 105 ++
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c}|  46 ---
 arch/arm/mach-socfpga/spl_s10.c| 138 
 arch/arm/mach-socfpga/system_manager_s10.c |  91 +
 arch/arm/mach-socfpga/timer.c  |  17 +-
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c |  55 +++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c|  46 +++
 board/altera/stratix10-socdk/MAINTAINERS   |   7 +
 board/altera/stratix10-socdk/Makefile  |   7 +
 board/altera/stratix10-socdk/socfpga.c |   7 +
 configs/socfpga_stratix10_defconfig|  39 +++
 drivers/ddr/altera/Makefile|   1 +
 drivers/ddr/altera/sdram_s10.c | 382 +
 include/configs/socfpga_stratix10_socdk.h  | 216 
 include/dt-bindings/reset/altr,rst-mgr-s10.h   |  97 ++
 39 files changed, 3482 insertions(+), 55 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/spl_a10.c
 rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (83%)
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c
 create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 

Re: [U-Boot] [PATCH v2 0/5] rockchip: back-to-bootrom: replace assembly-implementation with C-code

[Heiko Stübner]

Am Dienstag, 19. September 2017, 11:10:29 CEST schrieb Dr. Philipp Tomsich:
> Andy,
> 
> > On 19 Sep 2017, at 09:19, Andy Yan  wrote:
> > 
> > Hi Philipp:
> > 
> > On 2017年09月19日 10:06, Andy Yan wrote:
> >> Hi Philipp:
> >> 
> >> On 2017年09月19日 02:18, Philipp Tomsich wrote:
> >>> Recent discussions confirmed (what the code always assumed): the
> >>> Rockchip BROM always enters U-Boot with the stack-pointer valid
> >>> (i.e. the U-Boot startup code is running off the BROM stack).
> >>> 
> >>> We can thus replace the back-to-bootrom code (i.e. both the
> >>> save_boot_params and back_to_bootrom implementations) using C-code
> >>> based on setjmp/longjmp.  The new implementation is already structured
> >>> to allow an easy drop-in of Andy's changes to enter download-mode when
> >>> returning to the BROM.
> >>> 
> >>> This entails one minor tweak to asm/system.h, which only exported
> >>> the save_boot_params_ret prototype for ARMv7, but not for AArch64.
> >>> 
> >>> For v2, we force bootrom.o to alway be emitted as A32 (not T32), so we
> >>> can safely call save_boot_params_ret().
> >>> 
> >>This still have a problem, because the setjmp  implementation for
> >>ARM32 platform  has humb code when CONFIG_SYS_THUMB_BUILD is>> 
> >> enabled, this is a default setting for most ARMv7 boards.
> >> #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
> >> ".align 2\n"
> >> "adr r0, jmp_target\n"
> >> "add r0, r0, $1\n"  // r0 stored the jump target address and with bit[0]
> >> = 1, this will trigger a thumb switch in longjmp with code "bx r0"
> >> #endif
> >> 
> >> When I force the setjmp code go arm code path, I can back to bootrom
> >> successfully, But I got a data abort exception in later. it seems it
> >> happens when bootrom finished the uboot code copy, when jump to sdram, I
> >> need a further debug.
> > 
> > I found that r9 also need to be preserved, it seems that it hold the sdram
> > base.
> Thanks for testing and debugging: this is invaluable support, as I only have
> AArch64 boards to test.
> 
> The r9 issue will be easy enough to resolve.
> However, it looks like I will need more work on setjmp/longjmp to make this
> safe both for T32 and A32. Plus: I need to figure out why this didn’t show
> in my disassembly (I don’t remember whether it was a rk3188 or rk3288 board
> I looked at).
> 
> Might be tomorrow or Thursday until I can provide an new version.

From this conversation, it looks to me that I should wait for that new
version for testing on rk3188, as it will likely show the same issues, right?


Heiko
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Re: [U-Boot] [PATCH v2 0/5] rockchip: back-to-bootrom: replace assembly-implementation with C-code

[Dr. Philipp Tomsich]

Andy,

> On 19 Sep 2017, at 09:19, Andy Yan  wrote:
> 
> Hi Philipp:
> 
> 
> On 2017年09月19日 10:06, Andy Yan wrote:
>> Hi Philipp:
>> 
>> 
>> On 2017年09月19日 02:18, Philipp Tomsich wrote:
>>> Recent discussions confirmed (what the code always assumed): the
>>> Rockchip BROM always enters U-Boot with the stack-pointer valid
>>> (i.e. the U-Boot startup code is running off the BROM stack).
>>> 
>>> We can thus replace the back-to-bootrom code (i.e. both the
>>> save_boot_params and back_to_bootrom implementations) using C-code
>>> based on setjmp/longjmp.  The new implementation is already structured
>>> to allow an easy drop-in of Andy's changes to enter download-mode when
>>> returning to the BROM.
>>> 
>>> This entails one minor tweak to asm/system.h, which only exported
>>> the save_boot_params_ret prototype for ARMv7, but not for AArch64.
>>> 
>>> For v2, we force bootrom.o to alway be emitted as A32 (not T32), so we
>>> can safely call save_boot_params_ret().
>> 
>>This still have a problem, because the setjmp  implementation for ARM32 
>> platform  has humb code when CONFIG_SYS_THUMB_BUILD is
>> enabled, this is a default setting for most ARMv7 boards.
>> #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
>> ".align 2\n"
>> "adr r0, jmp_target\n"
>> "add r0, r0, $1\n"  // r0 stored the jump target address and with bit[0] = 
>> 1, this will trigger a thumb switch in longjmp with code "bx r0"
>> #endif
>> 
>> When I force the setjmp code go arm code path, I can back to bootrom 
>> successfully, But I got a data abort exception in later. it seems it happens 
>> when bootrom finished the uboot code
>> copy, when jump to sdram, I need a further debug.
> 
> I found that r9 also need to be preserved, it seems that it hold the sdram 
> base.

Thanks for testing and debugging: this is invaluable support, as I only have 
AArch64 boards to test.

The r9 issue will be easy enough to resolve.
However, it looks like I will need more work on setjmp/longjmp to make this 
safe both for T32 and A32.
Plus: I need to figure out why this didn’t show in my disassembly (I don’t 
remember whether it was a rk3188 or rk3288 board I looked at).

Might be tomorrow or Thursday until I can provide an new version.

Regards,
Philipp.

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Re: [U-Boot] [RESEND PATCH 3/3] dts: sunxi: add PWM node for sun50i

[Andre Przywara]

Hi,

On 19/09/17 06:06, Vasily Khoruzhick wrote:
> Signed-off-by: Vasily Khoruzhick 
> ---
>  arch/arm/dts/sun50i-a64.dtsi | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
> index 65a344d9ce..14e94bf00e 100644
> --- a/arch/arm/dts/sun50i-a64.dtsi
> +++ b/arch/arm/dts/sun50i-a64.dtsi
> @@ -319,6 +319,14 @@
>   };
>   };
>  
> + pwm: pwm@01c21400 {
> + compatible = "allwinner,sun50i-a64-pwm";

So the A64 PWM seems to be fully compatible with the H3 one, which has a
documented binding (also used in the Linux driver).
So can you please make this:
compatible = "allwinner,sun50i-a64-pwm",
 "allwinner,sun8i-h3-pwm";

and then drop the sun50i-a64-pwm string in the driver?

And I wonder if we should have the pinctrl already in here, since there
is only one choice for PWM0? At least that would document the clash.

> + reg = <0x01c21400 0x8>;
> + clocks = <>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
>   uart0: serial@1c28000 {
>   compatible = "snps,dw-apb-uart";
>   reg = <0x01c28000 0x400>;
> 
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Re: [U-Boot] [RESEND PATCH 1/3] pwm: sunxi: add support for PWM found on Allwinner A64 and H3

[Andre Przywara]

Hi,

On 19/09/17 06:06, Vasily Khoruzhick wrote:
> This commit adds basic support for PWM found on Allwinner A64 and H3

Mmh, can you explain (for instance in a 0/3 email) what this is used
for? My understanding is that PWM0 (which is what you hard code here) is
only exposed on PD22, which is also used for the MDC line to the
Ethernet PHY. All boards I heard of have Ethernet, so PWM0 is not usable
there.
So is this for a special board?

> 
> Signed-off-by: Vasily Khoruzhick 
> ---
>  arch/arm/include/asm/arch-sunxi/gpio.h |   1 +
>  arch/arm/include/asm/arch-sunxi/pwm.h  |  12 +++
>  arch/arm/mach-sunxi/board.c|  11 +++
>  drivers/pwm/Kconfig|   7 ++
>  drivers/pwm/Makefile   |   1 +
>  drivers/pwm/sunxi_pwm.c| 174 
> +
>  6 files changed, 206 insertions(+)
>  create mode 100644 drivers/pwm/sunxi_pwm.c
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
> b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 24f85206c8..7265d18099 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -173,6 +173,7 @@ enum sunxi_gpio_number {
>  #define SUN8I_GPD_SDC1   3
>  #define SUNXI_GPD_LCD0   2
>  #define SUNXI_GPD_LVDS0  3
> +#define SUNXI_GPD_PWM2
>  
>  #define SUN5I_GPE_SDC2   3
>  #define SUN8I_GPE_TWI2   3
> diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h 
> b/arch/arm/include/asm/arch-sunxi/pwm.h
> index 5884b5dbe7..673e0eb7b5 100644
> --- a/arch/arm/include/asm/arch-sunxi/pwm.h
> +++ b/arch/arm/include/asm/arch-sunxi/pwm.h
> @@ -11,8 +11,15 @@
>  #define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4)
>  
>  #define SUNXI_PWM_CTRL_PRESCALE0(x)  ((x) & 0xf)
> +#define SUNXI_PWM_CTRL_PRESCALE0_MASK(0xf)
>  #define SUNXI_PWM_CTRL_ENABLE0   (0x5 << 4)
>  #define SUNXI_PWM_CTRL_POLARITY0(x)  ((x) << 5)
> +#define SUNXI_PWM_CTRL_POLARITY0_MASK(1 << 5)
> +#define SUNXI_PWM_CTRL_CLK_GATE  (1 << 6)
> +
> +#define SUNXI_PWM_CH0_PERIOD_MAX (0x)
> +#define SUNXI_PWM_CH0_PERIOD_PRD(x)  ((x & 0x) << 16)
> +#define SUNXI_PWM_CH0_PERIOD_DUTY(x) ((x) & 0x)
>  
>  #define SUNXI_PWM_PERIOD_80PCT   0x04af03c0
>  
> @@ -31,4 +38,9 @@
>  #define SUNXI_PWM_MUXSUN8I_GPH_PWM
>  #endif
>  
> +struct sunxi_pwm {
> + u32 ctrl;
> + u32 ch0_period;
> +};
> +
>  #endif
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index 65b1ebd837..a85f973a46 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -141,6 +141,16 @@ static int gpio_init(void)
>   return 0;
>  }
>  
> +static int pwm_init(void)
> +{
> +#ifdef CONFIG_PWM_SUNXI
> +#ifdef CONFIG_MACH_SUN50I
> + sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);

So this would probably kill Ethernet.
At the very least this should be somehow protected against this clash.
And I wonder if this should move into the PWM driver, for instance into
the .enable function.

Cheers,
Andre.

> +#endif
> +#endif
> + return 0;
> +}
> +
>  #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
>  static int spl_board_load_image(struct spl_image_info *spl_image,
>   struct spl_boot_device *bootdev)
> @@ -204,6 +214,7 @@ void s_init(void)
>   clock_init();
>   timer_init();
>   gpio_init();
> + pwm_init();
>  #ifndef CONFIG_DM_I2C
>   i2c_init_board();
>  #endif
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index e827558052..67e3f355e7 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -43,3 +43,10 @@ config PWM_TEGRA
> four channels with a programmable period and duty cycle. Only a
> 32KHz clock is supported by the driver but the duty cycle is
> configurable.
> +
> +config PWM_SUNXI
> + bool "Enable support for the Allwinner Sunxi PWM"
> + depends on DM_PWM
> + help
> +   This PWM is found on A64 and other Allwinner SoCs. It supports a
> +   programmable period and duty cycle. A 32-bit counter is used.
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index 29d59916cb..1a8f8a58bc 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -17,3 +17,4 @@ obj-$(CONFIG_PWM_IMX)   += pwm-imx.o 
> pwm-imx-util.o
>  obj-$(CONFIG_PWM_ROCKCHIP)   += rk_pwm.o
>  obj-$(CONFIG_PWM_SANDBOX)+= sandbox_pwm.o
>  obj-$(CONFIG_PWM_TEGRA)  += tegra_pwm.o
> +obj-$(CONFIG_PWM_SUNXI)  += sunxi_pwm.o
> diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c
> new file mode 100644
> index 00..3e6d69fa1c
> --- /dev/null
> +++ b/drivers/pwm/sunxi_pwm.c
> @@ -0,0 +1,174 @@
> +/*
> + * Copyright (c) 2017 Vasily Khoruzhick 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> 

Re: [U-Boot] [RESEND PATCH 3/3] dts: sunxi: add PWM node for sun50i

[Maxime Ripard]

On Mon, Sep 18, 2017 at 10:06:41PM -0700, Vasily Khoruzhick wrote:
> Signed-off-by: Vasily Khoruzhick 

Commit log please. At least mention the fact that this binding has not
been accepted in Linux yet.

Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [U-Boot] [RESEND PATCH 5/5] sunxi: video: add LCD support to DE2 driver

[Maxime Ripard]

On Mon, Sep 18, 2017 at 10:04:21PM -0700, Vasily Khoruzhick wrote:
> Extend DE2 driver with LCD support

(All) your commit messages could use a bit more details.

Here, for example, explaining the following things would help:
  - Why are you creating yet another file
  - What is the situation with old Allwinner SoCs that should share
the same code
  - What are the expected users
  - Which SoC / board have you tested it on

etc...

> Signed-off-by: Vasily Khoruzhick 
> ---
>  arch/arm/mach-sunxi/Kconfig |   2 +-
>  drivers/video/sunxi/Makefile|   2 +-
>  drivers/video/sunxi/sunxi_de2.c |  17 +
>  drivers/video/sunxi/sunxi_lcd.c | 142 
> 
>  4 files changed, 161 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/video/sunxi/sunxi_lcd.c
> 
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 2309f5..06d697e3a7 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -680,7 +680,7 @@ config VIDEO_LCD_MODE
>  
>  config VIDEO_LCD_DCLK_PHASE
>   int "LCD panel display clock phase"
> - depends on VIDEO
> + depends on VIDEO || DM_VIDEO
>   default 1
>   ---help---
>   Select LCD panel display clock phase shift, range 0-3.
> diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile
> index 0d64c2021f..8c91766c24 100644
> --- a/drivers/video/sunxi/Makefile
> +++ b/drivers/video/sunxi/Makefile
> @@ -6,4 +6,4 @@
>  #
>  
>  obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o 
> ../videomodes.o
> -obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
> +obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o 
> sunxi_lcd.o
> diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c
> index ee67764ac5..a838bbacd1 100644
> --- a/drivers/video/sunxi/sunxi_de2.c
> +++ b/drivers/video/sunxi/sunxi_de2.c
> @@ -232,6 +232,23 @@ static int sunxi_de2_probe(struct udevice *dev)
>   if (!(gd->flags & GD_FLG_RELOC))
>   return 0;
>  
> + ret = uclass_find_device_by_name(UCLASS_DISPLAY,
> +  "sunxi_lcd", );
> + if (!ret) {
> + int mux;
> +
> + mux = 0;
> +
> + ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
> +  false);
> + if (!ret) {
> + video_set_flush_dcache(dev, 1);

Why do you need to flush the dcache here?

> + return 0;
> + }
> + }
> +
> + debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
> +
>   ret = uclass_find_device_by_name(UCLASS_DISPLAY,
>"sunxi_dw_hdmi", );
>   if (!ret) {
> diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c
> new file mode 100644
> index 00..154eb5835e
> --- /dev/null
> +++ b/drivers/video/sunxi/sunxi_lcd.c
> @@ -0,0 +1,142 @@
> +/*
> + * Allwinner LCD driver
> + *
> + * (C) Copyright 2017 Vasily Khoruzhick 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +struct sunxi_lcd_priv {
> + struct display_timing timing;
> + int panel_bpp;
> +};
> +
> +static void sunxi_lcdc_config_pinmux(void)
> +{
> + int pin;
> + for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
> + sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
> + sunxi_gpio_set_drv(pin, 3);
> + }
> +}
> +
> +static int sunxi_lcd_enable(struct udevice *dev, int bpp,
> +   const struct display_timing *edid)
> +{
> + struct sunxi_ccm_reg * const ccm =
> +(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> + struct sunxi_lcdc_reg * const lcdc =
> +(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
> + struct sunxi_lcd_priv *priv = dev_get_priv(dev);
> + struct udevice *backlight;
> + int clk_div, clk_double, ret;
> +
> + /* Reset off */
> + setbits_le32(>ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
> +
> + /* Clock on */
> + setbits_le32(>ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);

This has nothing to do with using a panel or not, it should be in
lcdc_init().

> + lcdc_init(lcdc);
> + sunxi_lcdc_config_pinmux();

This is already handled in sunxi_lcdc_tcon0_mode_set, why duplicate
it?

> + lcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000,
> +  _div, _double);
> + lcdc_tcon0_mode_set(lcdc, edid, clk_div, false,
> + priv->panel_bpp, CONFIG_VIDEO_LCD_DCLK_PHASE);
> + lcdc_enable(lcdc, priv->panel_bpp);
> +
> + ret = uclass_get_device(UCLASS_PANEL_BACKLIGHT, 0, );
> + if (!ret)
> + backlight_enable(backlight);
> +
> + return 0;
> +}
> +
> 

Re: [U-Boot] [OE-core] [PATCH] u-boot: Upgrade to 2017.09

[Marek Vasut]

On 09/18/2017 06:06 PM, Tom Rini wrote:
> On Mon, Sep 18, 2017 at 04:51:31PM +0100, Burton, Ross wrote:
>> On 18 September 2017 at 16:46, Otavio Salvador <
>> otavio.salva...@ossystems.com.br> wrote:
>>
>>> What is the policy on doing u-boot version upgrades this late in the
>>>
>>> release cycle? SHouldn't this wait until after the release?
>>>
>>>
>>> Why?
>>>
>>> It is just another recipe and we are upgrading to the final release.
>>>
>>> As Martin said, it was already broken.
>>>
>>> I'll take the responsibility to fix it. But as other packages, upgrades
>>> has risk and we have more than enough time to proper fix it.
>>>
>>
>> Why?  Because it was merged to master after the freeze.
>>
>> Personally I'm of the opinion that u-boot is one of those special recipes
>> that if an upgrade appears just after freeze, we consider it.  If we don't
>> keep it up to date BSPs won't use the recipe, and we'll be back to every
>> BSP layer containing its own special copy of the u-boot recipe.
> 
> Also please note that U-Boot has a rather regular and public release
> schedule: http://www.denx.de/wiki/U-Boot/ReleaseCycle so you can have a
> good idea beforehand if you want to grab something for a release or not.
> 
> Personally, I would like to see this in.  But the security issue that's
> been disclosed now is "resolved" just by not enabling functionality that
> no one was enabling in mainline, and will be removed in the next
> release, so don't feel you need to pull it in on those grounds.

I agree that the 2017.09 upgrade is a good idea.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] imx6: disable clock command and print_cpuinfo code in SPL

[Stefano Babic]

Hi Anatolji,

On 28/08/2017 21:46, Anatolij Gustschin wrote:
> We do not use print_cpuinfo and clock command code in SPL,
> disable it when building SPL image.
> 
> Signed-off-by: Anatolij Gustschin 
> ---
>  arch/arm/mach-imx/cpu.c   |  4 ++--
>  arch/arm/mach-imx/mx6/clock.c | 30 --
>  2 files changed, 18 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
> index 1017eb8..18205dc 100644
> --- a/arch/arm/mach-imx/cpu.c
> +++ b/arch/arm/mach-imx/cpu.c
> @@ -25,7 +25,7 @@
>  #include 
>  #endif
>  
> -#if defined(CONFIG_DISPLAY_CPUINFO)
> +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
>  static u32 reset_cause = -1;
>  
>  static char *get_reset_cause(void)
> @@ -132,7 +132,7 @@ unsigned imx_ddr_size(void)
>  }
>  #endif
>  
> -#if defined(CONFIG_DISPLAY_CPUINFO)
> +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
>  
>  const char *get_imx_type(u32 imxtype)
>  {
> diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
> index 0e019c4..71a9e6b 100644
> --- a/arch/arm/mach-imx/mx6/clock.c
> +++ b/arch/arm/mach-imx/mx6/clock.c
> @@ -1220,6 +1220,20 @@ void enable_thermal_clk(void)
>   enable_pll3();
>  }
>  
> +#ifdef CONFIG_MTD_NOR_FLASH
> +void enable_eim_clk(unsigned char enable)
> +{
> + u32 reg;
> +
> + reg = __raw_readl(_ccm->CCGR6);
> + if (enable)
> + reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
> + else
> + reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
> + __raw_writel(reg, _ccm->CCGR6);
> +}
> +#endif
> +
>  unsigned int mxc_get_clock(enum mxc_clock clk)
>  {
>   switch (clk) {
> @@ -1262,6 +1276,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
>   return 0;
>  }
>  
> +#ifndef CONFIG_SPL_BUILD
>  /*
>   * Dump some core clockes.
>   */
> @@ -1463,20 +1478,6 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
>  }
>  #endif
>  
> -#ifdef CONFIG_MTD_NOR_FLASH
> -void enable_eim_clk(unsigned char enable)
> -{
> - u32 reg;
> -
> - reg = __raw_readl(_ccm->CCGR6);
> - if (enable)
> - reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
> - else
> - reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
> - __raw_writel(reg, _ccm->CCGR6);
> -}
> -#endif
> -
>  /***/
>  
>  U_BOOT_CMD(
> @@ -1484,3 +1485,4 @@ U_BOOT_CMD(
>   "display clocks",
>   ""
>  );
> +#endif
> 

This patch has some side-effects and breaks some boards. Even if the
changes are correct, some boards (wandboard, icore are examples) don't
disable IPU support in SPL. Even if this is useless and generates only a
bigger footprint.

In fact, I get :

   arm:  +   wandboard
+board/wandboard/built-in.o: In function `setup_display':
+board/wandboard/wandboard.c:355: undefined reference to `enable_ipu_clock'
+make[2]: *** [spl/u-boot-spl] Error 1
+make[1]: *** [spl/u-boot-spl] Error 2
+make: *** [sub-make] Error 2


Reason is clear: boards have in SPL a setup_display() that calls
enable_ipu_clock. But it makes no sense to have IPU support in SPL.

We can fix with a follow-up patch, but this is bad for bisecting. The
other option is to fix here and disable IPU in spl for the affected
boards. What you think ?

Best regards,
Stefano

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Re: [U-Boot] [PATCH v3] cmd: usb: add blk devices to ignore list in tree graph

[Bin Meng]

Hi Suneel,

On Tue, Sep 19, 2017 at 1:55 PM, Suneel Garapati  wrote:
> add blk child devices to ignore list while displaying
> usb tree graph, otherwise usb tree and info commands
> may cause crash treating blk as usb device.
>
> Signed-off-by: Suneel Garapati 
> ---
>
> Changes v3:
>  - remove 'check on parent uclass' in description

thanks for making the changes.

> Changes v2:
>  - remove check on parent uclass
> Changes v1:
>  - add separate check on blk uclass
>  - modify description
>  - add separate check on parent uclass as usb
>
>  cmd/usb.c | 11 ---
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/cmd/usb.c b/cmd/usb.c
> index d95bcf5..3889994 100644
> --- a/cmd/usb.c
> +++ b/cmd/usb.c
> @@ -414,8 +414,12 @@ static void usb_show_tree_graph(struct usb_device *dev, 
> char *pre)
>
> udev = dev_get_parent_priv(child);
>
> -   /* Ignore emulators, we only want real devices */
> -   if (device_get_uclass_id(child) != UCLASS_USB_EMUL) {
> +   /*
> +* Ignore emulators and block child devices, we only want
> +* real devices
> +*/
> +   if ((device_get_uclass_id(child) != UCLASS_USB_EMUL) &&
> +   (device_get_uclass_id(child) != UCLASS_BLK)) {
> usb_show_tree_graph(udev, pre);
> pre[index] = 0;
> }
> @@ -605,7 +609,8 @@ static void usb_show_info(struct usb_device *udev)
> for (device_find_first_child(udev->dev, );
>  child;
>  device_find_next_child()) {
> -   if (device_active(child)) {
> +   if (device_active(child) &&
> +   (device_get_uclass_id(child) != UCLASS_BLK)) {
> udev = dev_get_parent_priv(child);
> usb_show_info(udev);
> }
> --

My testing of 'usb info' looks OK, however 'usb tree' still has some
issues below:

=> usb tree
USB device tree:
  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller
  |
  +-2  Hub (5 Gb/s, 0mA)
  | |  GenesysLogic USB3.0 Hub
  | |
  | +-5  Vendor specific (5 Gb/s, 36mA)
  |  Realtek USB 10/100/1000 LAN 00E04C680977
  |
  +-3  Hub (480 Mb/s, 100mA)
  | |  GenesysLogic USB2.0 Hub
  | |
  | +-6  Mass Storage (480 Mb/s, 98mA)
  | | |  USBest Technology USB Mass Storage Device 10c452b7c0
  | | |

As you see, we just don't print out the BLK device, but we still print
out the | here.

  | +-7  Human Interface (1.5 Mb/s, 70mA)
  |  Dell Dell USB Keyboard
  |
  +-4  Mass Storage (480 Mb/s, 300mA)
|  JetFlash Mass Storage Device 16Q6ZPH20GF3E8UQ
|

And here.

Regards,
Bin
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Re: [U-Boot] [PATCH 1/1] x86: provide CONFIG_BUILD_ROM

[Bin Meng]

Hi Heinrich,

On Tue, Sep 19, 2017 at 2:15 PM, Heinrich Schuchardt  wrote:
> On 09/19/2017 07:54 AM, Bin Meng wrote:
>> Hi Heinrich,
>>
>> On Sun, Sep 17, 2017 at 7:57 PM, Heinrich Schuchardt  
>> wrote:
>>> Up to now we depended on an exported variable to build u-boot.rom.
>>> What we build should be specified by the configuration file.
>>>
>>> With this patch the export variable is deprecated and replaced by the
>>> Kconfig option CONFIG_BUILD_ROM.
>>>
>>> This option depends on CONFIG_X86 and is selected in qemu-x86_defconfig.
>>>
>>> Signed-off-by: Heinrich Schuchardt 
>>> ---
>>>  Kconfig| 10 ++
>>>  Makefile   |  2 +-
>>>  configs/qemu-x86_defconfig |  1 +
>>>  doc/README.x86 |  2 +-
>>>  4 files changed, 13 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Kconfig b/Kconfig
>>> index 238fa3e1ed..7b782298bf 100644
>>> --- a/Kconfig
>>> +++ b/Kconfig
>>> @@ -158,6 +158,16 @@ config PHYS_64BIT
>>>   This can be used not only for 64bit SoCs, but also for
>>>   large physical address extention on 32bit SoCs.
>>>
>>> +config BUILD_ROM
>>> +   bool "Build U-BOOT as BIOS replacement"
>>
>> nits: U-Boot
>>
>>> +   depends on X86
>>> +   default n
>>
>> nits: this is not needed as 'n' is the default one.
>>
>>> +   help
>>> + This option allows to BUILD a ROM version of U-BOOT.
>>
>> nits: U-Boot
>>
>>> + The build process generally requires several binary blobs
>>> + which are not shipped in the U-Boot source tree.
>>> + Please, see doc/README.x86 for detials.
>>> +
>>>  endmenu# General setup
>>>
>>>  menu "Boot images"
>>> diff --git a/Makefile b/Makefile
>>> index 8250b3409a..50fe0003f5 100644
>>> --- a/Makefile
>>> +++ b/Makefile
>>> @@ -796,7 +796,7 @@ ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
>>>  ALL-$(CONFIG_EFI_APP) += u-boot-app.efi
>>>  ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
>>>
>>> -ifneq ($(BUILD_ROM),)
>>> +ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
>>>  ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
>>>  endif
>>>
>>> diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
>>> index d84e1d7dc9..60c2e3c404 100644
>>> --- a/configs/qemu-x86_defconfig
>>> +++ b/configs/qemu-x86_defconfig
>>
>> We should also enable this on qemu-x86_64_defconfig.
>>
>>> @@ -1,4 +1,5 @@
>>>  CONFIG_X86=y
>>> +CONFIG_BUILD_ROM=y
>>>  CONFIG_MAX_CPUS=2
>>>  CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
>>>  CONFIG_SMP=y
>>> diff --git a/doc/README.x86 b/doc/README.x86
>>> index c542a6965c..4971f4b95e 100644
>>> --- a/doc/README.x86
>>> +++ b/doc/README.x86
>>> @@ -81,7 +81,7 @@ shipped in the U-Boot source tree. Due to this reason, 
>>> the u-boot.rom build is
>>>  not turned on by default in the U-Boot source tree. Firstly, you need turn 
>>> it
>>>  on by enabling the ROM build:
>>>
>>> -$ export BUILD_ROM=y
>>> +CONFIG_BUILD_ROM=y
>>>
>>>  This tells the Makefile to build u-boot.rom as a target.
>>>
>>> --
>>
>> For non-QEMU targets, this requires an additional step after we do
>> 'make xxx_defconfig', I am not sure if that's convenient.
>
> You still can export BUILD_ROM.
>

OK.

> Would you prefer to make CONFIG_BUILD_ROM 'default y'?
> Probably you always want to build u-boot.rom for an X86 system.
>

No. That will break buildman testing as the required binary blobs are
not in the U-Boot tree.

>> Simon, what do you think about this patch?

Regards,
Bin
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Re: [U-Boot] [PATCH v2 0/5] rockchip: back-to-bootrom: replace assembly-implementation with C-code

[Andy Yan]

Hi Philipp:


On 2017年09月19日 10:06, Andy Yan wrote:

Hi Philipp:


On 2017年09月19日 02:18, Philipp Tomsich wrote:

Recent discussions confirmed (what the code always assumed): the
Rockchip BROM always enters U-Boot with the stack-pointer valid
(i.e. the U-Boot startup code is running off the BROM stack).

We can thus replace the back-to-bootrom code (i.e. both the
save_boot_params and back_to_bootrom implementations) using C-code
based on setjmp/longjmp.  The new implementation is already structured
to allow an easy drop-in of Andy's changes to enter download-mode when
returning to the BROM.

This entails one minor tweak to asm/system.h, which only exported
the save_boot_params_ret prototype for ARMv7, but not for AArch64.

For v2, we force bootrom.o to alway be emitted as A32 (not T32), so we
can safely call save_boot_params_ret().


This still have a problem, because the setjmp  implementation for 
ARM32 platform  has humb code when CONFIG_SYS_THUMB_BUILD is

enabled, this is a default setting for most ARMv7 boards.
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
 ".align 2\n"
 "adr r0, jmp_target\n"
 "add r0, r0, $1\n"  // r0 stored the jump target address and with 
bit[0] = 1, this will trigger a thumb switch in longjmp with code "bx r0"

#endif

When I force the setjmp code go arm code path, I can back to bootrom 
successfully, But I got a data abort exception in later. it seems it 
happens when bootrom finished the uboot code

copy, when jump to sdram, I need a further debug.


I found that r9 also need to be preserved, it seems that it hold the 
sdram base.


It also turned out that I had not caught the RK3188 in my earlier
series... and my luck being what it is, the RK3188 needed some extra
handholding to adapt to the new regime: instead of passing the context
address (for returning to the BROM) from the TPL to the SPL, the SPL
now returns to the TPL and the TPL then returns to the BROM.

Changes in v2:
- [added in v2] chain back_to_bootrom calls for SPL, first returning
   to the TPL (using the same mechanism) and further calling through
   to the BROM from the TPL by invoking back_to_bootrom again
- adapt the RK3188 spl support file (that I had originally missed)

Philipp Tomsich (5):
   arm: make save_boot_params_ret prototype visible for AArch64
   rockchip: back-to-bootrom: replace assembly-implementation with 
C-code

   rockchip: back-to-bootrom: rk3188: chain from SPL via TPL to the BROM
   rockchip: back-to-bootrom: allow passing a cmd to the bootrom
   rockchip: back-to-bootrom: do not compile bootrom.o in thumb mode

  arch/arm/include/asm/arch-rockchip/bootrom.h | 30 +---
  arch/arm/include/asm/system.h| 62 
-

  arch/arm/mach-rockchip/Makefile  | 10 +++-
  arch/arm/mach-rockchip/bootrom.c | 54 
+-

  arch/arm/mach-rockchip/rk3036-board-spl.c|  2 +-
  arch/arm/mach-rockchip/rk3188-board-spl.c| 14 +-
  arch/arm/mach-rockchip/rk3188-board-tpl.c| 19 
  arch/arm/mach-rockchip/rk322x-board-spl.c|  2 +-
  arch/arm/mach-rockchip/rk3288-board-spl.c|  4 +-
  arch/arm/mach-rockchip/rk3368-board-tpl.c|  2 +-
  arch/arm/mach-rockchip/rk3399-board-spl.c|  2 +-
  arch/arm/mach-rockchip/save_boot_param.S | 69 


  12 files changed, 133 insertions(+), 137 deletions(-)
  delete mode 100644 arch/arm/mach-rockchip/save_boot_param.S






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Re: [U-Boot] [PATCH 1/1] x86: provide CONFIG_BUILD_ROM

[Heinrich Schuchardt]

On 09/19/2017 07:54 AM, Bin Meng wrote:
> Hi Heinrich,
> 
> On Sun, Sep 17, 2017 at 7:57 PM, Heinrich Schuchardt  
> wrote:
>> Up to now we depended on an exported variable to build u-boot.rom.
>> What we build should be specified by the configuration file.
>>
>> With this patch the export variable is deprecated and replaced by the
>> Kconfig option CONFIG_BUILD_ROM.
>>
>> This option depends on CONFIG_X86 and is selected in qemu-x86_defconfig.
>>
>> Signed-off-by: Heinrich Schuchardt 
>> ---
>>  Kconfig| 10 ++
>>  Makefile   |  2 +-
>>  configs/qemu-x86_defconfig |  1 +
>>  doc/README.x86 |  2 +-
>>  4 files changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/Kconfig b/Kconfig
>> index 238fa3e1ed..7b782298bf 100644
>> --- a/Kconfig
>> +++ b/Kconfig
>> @@ -158,6 +158,16 @@ config PHYS_64BIT
>>   This can be used not only for 64bit SoCs, but also for
>>   large physical address extention on 32bit SoCs.
>>
>> +config BUILD_ROM
>> +   bool "Build U-BOOT as BIOS replacement"
> 
> nits: U-Boot
> 
>> +   depends on X86
>> +   default n
> 
> nits: this is not needed as 'n' is the default one.
> 
>> +   help
>> + This option allows to BUILD a ROM version of U-BOOT.
> 
> nits: U-Boot
> 
>> + The build process generally requires several binary blobs
>> + which are not shipped in the U-Boot source tree.
>> + Please, see doc/README.x86 for detials.
>> +
>>  endmenu# General setup
>>
>>  menu "Boot images"
>> diff --git a/Makefile b/Makefile
>> index 8250b3409a..50fe0003f5 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -796,7 +796,7 @@ ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
>>  ALL-$(CONFIG_EFI_APP) += u-boot-app.efi
>>  ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
>>
>> -ifneq ($(BUILD_ROM),)
>> +ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
>>  ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
>>  endif
>>
>> diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
>> index d84e1d7dc9..60c2e3c404 100644
>> --- a/configs/qemu-x86_defconfig
>> +++ b/configs/qemu-x86_defconfig
> 
> We should also enable this on qemu-x86_64_defconfig.
> 
>> @@ -1,4 +1,5 @@
>>  CONFIG_X86=y
>> +CONFIG_BUILD_ROM=y
>>  CONFIG_MAX_CPUS=2
>>  CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
>>  CONFIG_SMP=y
>> diff --git a/doc/README.x86 b/doc/README.x86
>> index c542a6965c..4971f4b95e 100644
>> --- a/doc/README.x86
>> +++ b/doc/README.x86
>> @@ -81,7 +81,7 @@ shipped in the U-Boot source tree. Due to this reason, the 
>> u-boot.rom build is
>>  not turned on by default in the U-Boot source tree. Firstly, you need turn 
>> it
>>  on by enabling the ROM build:
>>
>> -$ export BUILD_ROM=y
>> +CONFIG_BUILD_ROM=y
>>
>>  This tells the Makefile to build u-boot.rom as a target.
>>
>> --
> 
> For non-QEMU targets, this requires an additional step after we do
> 'make xxx_defconfig', I am not sure if that's convenient.

You still can export BUILD_ROM.

Would you prefer to make CONFIG_BUILD_ROM 'default y'?
Probably you always want to build u-boot.rom for an X86 system.

Best regards

Heinrich

> 
> Simon, what do you think about this patch?
> 
> Regards,
> Bin
> 

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