[U-Boot] Uboot send pull request

[uboot]

 Hi Tom,

 Please pull the following patch from u-boot-nds32 into your tree.
 Thanks!

The following changes since commit 6e9b109aa9bcdd094e77da9fb03de8b44da8eb9d:

  Merge git://git.denx.de/u-boot-usb (2017-09-27 09:39:48 -0400)

are available in the git repository at:


  git://git.denx.de/u-boot-nds32.git master

for you to fetch changes up to 9c7ffc94dce3d7438a19576a833d96956ca7f3eb:

  nds32: Fix io.h warning message about readb (2017-09-28 13:16:54 +0800)


rick (1):
  nds32: Fix io.h warning message about readb

 arch/nds32/include/asm/io.h |   12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)
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Re: [U-Boot] [PATCH V4 11/12] imx: mx6sabresd: enable dm drivers

[Peng Fan]

Hi Stefano,

> -Original Message-
> From: Peng Fan
> Sent: Tuesday, September 26, 2017 10:04 AM
> To: 'Stefano Babic' 
> Cc: van.free...@gmail.com; u-boot@lists.denx.de; Fabio Estevam
> 
> Subject: RE: [PATCH V4 11/12] imx: mx6sabresd: enable dm drivers
> 
> Hi Stefano,
> 
> 
> > -Original Message-
> > From: Stefano Babic [mailto:sba...@denx.de]
> > Sent: Monday, September 25, 2017 10:12 PM
> > To: Peng Fan ; sba...@denx.de
> > Cc: van.free...@gmail.com; u-boot@lists.denx.de; Fabio Estevam
> > 
> > Subject: Re: [PATCH V4 11/12] imx: mx6sabresd: enable dm drivers
> >
> > Hi Peng,
> >
> > On 30/08/2017 08:14, Peng Fan wrote:
> > > Enable DM MMC/I2C/PMIC/GPIO/REGULATOR.
> > >
> > > Signed-off-by: Peng Fan 
> > > Cc: Fabio Estevam 
> > > Cc: Stefano Babic 
> > > ---
> > >
> > > V2->V4: none
> > >
> [..]
> 
> > >
> >
> > Enabling DM drivers seems to break sabresd:
> >
> >   arm:  +   mx6sabresd
> > +common/usb_storage.c: In function 'usb_stor_probe_device':
> > +common/usb_storage.c:218:30: error: 'struct usb_device' has no member
> > named 'dev'
> > +  data = dev_get_platdata(udev->dev);
> > +  ^
> > +common/usb_storage.c:228:32: error: 'struct usb_device' has no member
> > named 'dev'
> > +   ret = blk_create_devicef(udev->dev, "usb_storage_blk", str,
> > +^
> >
> >
> > Can you take a look ?
> 
> I build mx6sabresd_defconfig, I met the following warning based on imx
> master branch, but did not met the build error.
>   CC  spl/common/spl/spl_fit.o
> common/spl/spl_fit.c: In function 'spl_load_fit_image':
> common/spl/spl_fit.c:201:7: warning: passing argument 4 of 'gunzip' from
> incompatible pointer type [enabled by default]
>src, )) {
>^
> In file included from common/spl/spl_fit.c:8:0:
> include/common.h:627:5: note: expected 'long unsigned int *' but argument is
> of type 'size_t *'
>  int gunzip(void *, int, unsigned char *, unsigned long *);

Missed to say that this is not introduced by my patch. 
Did not meet that error when build mx6sabresd_defconfig? I did not meet that 
error based on
master or imx master branch.

Thanks,
Peng.

>  ^
> 
> Thanks,
> Peng.
> >
> > Best regards,
> > Stefano
> >
> >
> > --
> >
> 
> > =
> > DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
> >
> 
> > =
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[U-Boot] [PATCH] usb: storage: Fix overwritten in usb_stor_set_max_xfer_blk()

[Bin Meng]

The stored 'blk' value is overwritten to 'size / 512' before it can
be used in usb_stor_set_max_xfer_blk(). This is not what we want.
In fact, when 'size' exceeds the upper limit (USHRT_MAX * 512), we
should simply assign 'size' to the upper limit.

Reported-by: Coverity (CID: 167250)
Signed-off-by: Bin Meng 
---

 common/usb_storage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/usb_storage.c b/common/usb_storage.c
index a57570b..a91b1c0 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -964,7 +964,7 @@ static void usb_stor_set_max_xfer_blk(struct usb_device 
*udev,
blk = 20;
} else {
if (size > USHRT_MAX * 512)
-   blk = USHRT_MAX;
+   size = USHRT_MAX * 512;
blk = size / 512;
}
 #endif
-- 
2.7.4

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Re: [U-Boot] u-boot-usb/master sandbox unit test failure

[Bin Meng]

Hi,

On Tue, Sep 26, 2017 at 11:27 PM, Bin Meng  wrote:
> +Simon,
>
> On Tue, Sep 26, 2017 at 10:14 PM, Bin Meng  wrote:
>> On Tue, Sep 26, 2017 at 5:32 PM, Bin Meng  wrote:
>>> Hi Stephen,
>>>
>>> On Tue, Sep 26, 2017 at 1:11 AM, Stephen Warren  
>>> wrote:
 On 09/25/2017 10:40 AM, Marek Vasut wrote:
>
> On 09/25/2017 06:13 PM, Stephen Warren wrote:
>>
>> Marek,
>
>
> +CC Bin
>
> I will drop the xhci patchset and hope to get a fixed one from him.


 The latest branch content (0184c6fb34b4 "usb: dwc2: Align size of
 invalidating dcache before starting DMA") passes the tests.

>>>
>>> My tests shows that 'ut dm usb_flash' fails, and should have failed
>>> for quite a long time.
>>>
>>> $ ./u-boot -d arch/sandbox/dts/test.dtb
>>>
>>>
>>> U-Boot 2017.09-00337-g0184c6f (Sep 26 2017 - 17:29:31 +0800)
>>>
>>> Model: sandbox
>>> DRAM:  128 MiB
>>> MMC:   ** First descriptor is NOT a primary desc on 0:1 **
>>> ** First descriptor is NOT a primary desc on 1:1 **
>>> ** First descriptor is NOT a primary desc on 2:1 **
>>> mmc2: 2 (SD), mmc1: 1 (SD), mmc0: 0 (SD)
>>> Using default environment
>>>
>>> In:serial
>>> Out:   vidconsole
>>> Err:   vidconsole
>>> Model: sandbox
>>> SCSI:  Net:   eth0: eth@10002000, eth5: eth@10003000, eth3: sbe5,
>>> eth1: eth@10004000
>>> IDE:   Bus 0: not available
>>> => ut dm usb_flash
>>> Test: dm_test_usb_flash: usb.c
>>> test/dm/usb.c:53, dm_test_usb_flash(): 2 == blk_dread(dev_desc, 0, 2,
>>> cmp): Expected 2, got 0
>>> Test: dm_test_usb_flash: usb.c (flat tree)
>>> test/dm/usb.c:48, dm_test_usb_flash(): 0 ==
>>> blk_get_device_by_str("usb", "0", _desc): Expected 0, got -2
>>> Failures: 2
>>>

>> The latest u-boot-usb master branch breaks the following unit tests for
>> the sandbox target (as run by test/py):
>>
>> 8 failed
>> ... test_ut[ut_dm_blk_usb]
>> ... test_ut[ut_dm_usb_flash]
>> ... test_ut[ut_dm_usb_keyb]
>> ... test_ut[ut_dm_usb_multi]
>> ... test_ut[ut_dm_usb_remove]
>> ... test_ut[ut_dm_usb_tree]
>> ... test_ut[ut_dm_usb_tree_remove]
>> ... test_ut[ut_dm_usb_tree_reorder]
>>>
>>> I've fixed all test failures except 'ut dm usb_flash'.
>>>
>>
>> Looks I was jumping to conclusions. Previously I was just marking
>> sandbox as an exception in the 'usb_stop', and all tests were passed.
>> But I feel that's inconsistent. Now with a proper fix for sandbox, the
>> 'usb remove' test no longer passed because I was trying to delete the
>> "/usb@1/hub/hub-emul/flash-stick@1" node from device tree but a
>> follow-up 'usb_init()' will fail. I am new to the sandbox emulator and
>> still investigating this. Any hints?
>>
>
> Please check my WIP patch @
> http://git.denx.de/?p=u-boot/u-boot-x86.git;a=commitdiff;h=e8481c91c295027f7ae2f4c59853c1c36f2e64f4
> for fixing sandbox 'usb remove' issues.
>
> Below are my test logs on Sandbox:
>
> => usb start
> starting USB...
> USB0:   scanning bus 1 for devices... 5 USB Device(s) found
>scanning usb for storage devices... 3 Storage Device(s) found
> => usb stop
> stopping USB..
> => fdt addr -c
> The address of the fdt is 0x5986ba0
> => fdt addr 0x5986ba0
> => fdt rm "/usb@1/hub/hub-emul/flash-stick@1"
> => usb start
> starting USB...
> USB0:   scanning bus 1 for devices...
>   USB device not accepting new address (error=8000)
> failed, error -2
>scanning usb for storage devices... 0 Storage Device(s) found
>
> Any hints?

Any suggestions would be appreciated. I don't think I was the first
one who wanted to test deleting some nodes from the device tree, and
redo the fdt scan stuff.

Regards,
Bin
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[U-Boot] [PATCH 1/1] rockchip: provide installation instruction for Firefly-RK3399.

[Heinrich Schuchardt]

Unfortunately installing U-Boot on an SD card for the Firefly-RK3399
is not trivial.

I could not get U-Boot running with SPL.  So I ended up using the
Rockchip miniloader.

Adding a README hopefully will give other users an easier start.

Signed-off-by: Heinrich Schuchardt 
---
 board/rockchip/firefly_rk3399/README | 55 
 1 file changed, 55 insertions(+)
 create mode 100644 board/rockchip/firefly_rk3399/README

diff --git a/board/rockchip/firefly_rk3399/README 
b/board/rockchip/firefly_rk3399/README
new file mode 100644
index 00..e9fb41f02d
--- /dev/null
+++ b/board/rockchip/firefly_rk3399/README
@@ -0,0 +1,55 @@
+Installation of U-Boot on the Firefly-RK3399
+
+
+Here is a step-by-step instruction for installing U-Boot for the
+Firefly-RK3399 on an SD card using the precompiled miniloader provided
+by Rockchip. An alternative is to use the second stage loader SPL built by
+U-Boot.
+
+Get precompiled binaries
+
+
+git clone https://github.com/rockchip-linux/rkbin.git
+
+Flash precompiled binaries to the SD card
+=
+
+mkimage -n rk3399 -T rksd -d rkbin/rk33/rk3399_ddr_800MHz_v1.08.bin \
+  idbloader.img
+cat rkbin/rk33/rk3399_miniloader_v1.06.bin >> idbloader.img
+sudo dd if=idbloader.img of=/dev/sdX seek=64 conv=notrunc
+cat > trust.ini << EOF
+[VERSION]
+MAJOR=1
+MINOR=0
+[BL30_OPTION]
+SEC=0
+[BL31_OPTION]
+SEC=1
+PATH=rkbin/rk33/rk3399_bl31_v1.00.elf
+ADDR=0x1
+[BL32_OPTION]
+SEC=0
+[BL33_OPTION]
+SEC=0
+[OUTPUT]
+PATH=trust.img
+EOF
+rkbin/tools/trust_merger trust.ini
+sudo dd if=trust.img of=/dev/sdX seek=24576 conv=notrunc
+
+Running trust_merger requires an x86_64 system.
+
+Compile U-Boot
+==
+
+make mrproper
+make firefly-rk3399_defconfig
+make
+mkimage -n rk3399 -O u-boot -a 0x2 -T rkimage -d u-boot-dtb.bin \
+  uboot.img
+
+Flash U-Boot to the SD-card
+===
+
+sudo dd if=u-boot/uboot.img of=/dev/sdX seek=16384 conv=notrunc
-- 
2.14.1

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Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Chee, Tien Fong]

On Rab, 2017-09-27 at 10:32 +0200, Marek Vasut wrote:
> On 09/27/2017 07:43 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee 
> > > > > > 
> > > > > > Add support to memory allocation in SPL for preparation to
> > > > > > enable
> > > > > > FAT
> > > > > > in SPL. Memory allocation is needed by FAT to work
> > > > > > properly.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee 
> > > > > Gen 5 does have malloc support in SPL, so what's the deal
> > > > > here ?
> > > > > 
> > > > For FAT to work properly in Arria 10 SPL, SPL malloc need to be
> > > > enabled,
> > > It is already enabled on Gen 5
> > > 
> > I think i have confused you, this patch is for getting the malloc
> > area
> > mapping to Arria 10 SRAM memory correctly. I will improve the
> > commit
> > message.
> > > 
> > > > 
> > > > 
> > > > and the min of SPL malloc size is 0x2000.
> > > Where did you find about this minimum ? That can be configured
> > > ...
> > > 
> > I having issue to boot u-boot successful(Hung or reset), after
> > debuging
> > through debugger, just found that 0x2000 is min required.
> You can set the value much lower and depending on the requirements,
> it
> will work, so the problem must be elsewhere ...
> 
Okay, i will test it out.
> > 
> > > 
> > > > 
> > > > 
> > > > FAT needed in Arria
> > > > 10 SPL, because u-boot.img is stored in FAT partition.
> > > It can also be stored on ext partition (which is preferred,
> > > patent-
> > > wise)
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > ---
> > > > > >  include/configs/socfpga_common.h | 23
> > > > > > ++-
> > > > > >  1 file changed, 22 insertions(+), 1 deletion(-)
> > > > > > 
> > > > > > diff --git a/include/configs/socfpga_common.h
> > > > > > b/include/configs/socfpga_common.h
> > > > > > index 7549ee8..9b6719e 100644
> > > > > > --- a/include/configs/socfpga_common.h
> > > > > > +++ b/include/configs/socfpga_common.h
> > > > > > @@ -280,17 +280,34 @@ unsigned int
> > > > > > cm_get_qspi_controller_clk_hz(void);
> > > > > >  /*
> > > > > >   * SPL
> > > > > >   *
> > > > > > - * SRAM Memory layout:
> > > > > > + * SRAM Memory layout for gen 5:
> > > > > >   *
> > > > > >   * 0x_ .. Start of SRAM
> > > > > >   * 0x_ .. Top of stack (grows down)
> > > > > >   * 0x_ .. Malloc area
> > > > > >   * 0x_ .. Global Data
> > > > > >   * 0x_FF00 .. End of SRAM
> > > > > > + *
> > > > > > + * SRAM Memory layout for Arria 10:
> > > > > > + * 0xFFE0_ .. Start of SRAM (bottom)
> > > > > > + * 0xFFEx_ .. Top of stack (grows down to bottom)
> > > > > > + * 0xFFEy_ .. Malloc area (grows up to top)
> > > > > > + * 0xFFEz_ .. Global Data
> > > > > > + * 0xFFE3_ .. End of SRAM (top)
> > > > > >   */
> > > > > >  #define CONFIG_SPL_FRAMEWORK
> > > > > >  #define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INI
> > > > > > T_RA
> > > > > > M_AD
> > > > > > DR
> > > > > >  #define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT
> > > > > > _RAM
> > > > > > _SIZ
> > > > > > E
> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > > +/* SPL memory allocation configuration, it is required by
> > > > > > FAT
> > > > > > feature */
> > > > > > +#ifndef CONFIG_SYS_SPL_MALLOC_START
> > > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000
> > > > > > +#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_INI
> > > > > > T_RA
> > > > > > M_SI
> > > > > > ZE - \
> > > > > > +    GENERATED_GBL_DAT
> > > > > > A_SI
> > > > > > ZE -
> > > > > > \
> > > > > > +    CONFIG_SYS_SPL_MA
> > > > > > LLOC
> > > > > > _SIZ
> > > > > > E + \
> > > > > > +    CONFIG_SYS_INIT_R
> > > > > > AM_A
> > > > > > DDR)
> > > > > > +#endif
> > > > > > +#endif
> > > > > >  
> > > > > >  /* SPL SDMMC boot support */
> > > > > >  #ifdef CONFIG_SPL_MMC_SUPPORT
> > > > > > @@ -320,7 +337,11 @@ unsigned int
> > > > > > cm_get_qspi_controller_clk_hz(void);
> > > > > >  /*
> > > > > >   * Stack setup
> > > > > >   */
> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > >  #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP
> > > > > > _ADD
> > > > > > R
> > > > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > > +#define CONFIG_SPL_STACK   (CONFIG_SYS_SPL_MA
> > > > > > LLOC
> > > > > > _STA
> > > > > > RT - 1)
> > > > > > +#endif
> > > > > >  
> > > > > >  /* Extra Environment */
> > > > > >  #ifndef CONFIG_SPL_BUILD
> > > > > > 
> 

Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Chee, Tien Fong]

On Rab, 2017-09-27 at 10:29 +0200, Marek Vasut wrote:
> On 09/27/2017 05:12 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:30 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:39 AM, tien.fong.c...@intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee 
> > > > > > 
> > > > > > This patch adds description on properties about location of
> > > > > > FPGA
> > > > > > RBFs are
> > > > > > stored, type and functionality of RBF used to configure
> > > > > > FPGA.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee 
> > > > > Why does this patch have different tags than 1/19 ? Please
> > > > > keep
> > > > > things
> > > > > consistent ...
> > > > > 
> > > > Not get you. What's you means for tags?
> > > ARM: socfpga: , not the random doc: dtbinding: .
> > > Heck, the first and second patch change the same file, yet have
> > > different tags, why ?
> > > 
> > I ported patch 01 from Linux, so i keep everything intact. For
> > patch
> > 02, i put doc:dtbinding because i think that is more descriptive to
> > the
> > file i changed.
> > I can change to ARM:socfpga .
> The tags are standardized ... inventing new random ones only messes
> things up.
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > ---
> > > > > >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > > > mgr.txt
> > > > > > > 
> > > > > > > 11
> > > > > > +++
> > > > > >  1 file changed, 11 insertions(+)
> > > > > > 
> > > > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-
> > > > > > a10-
> > > > > > fpga-
> > > > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > fpga-
> > > > > > mgr.txt
> > > > > > index 2fd8e7a..7abb746 100644
> > > > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > fpga-
> > > > > > mgr.txt
> > > > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > fpga-
> > > > > > mgr.txt
> > > > > > @@ -7,6 +7,14 @@ Required properties:
> > > > > > - The second index is for writing FPGA
> > > > > > configuration data.
> > > > > >  - resets : Phandle and reset specifier for the
> > > > > > device's
> > > > > > reset.
> > > > > >  - clocks : Clocks used by the device.
> > > > > > +- bitstream_periph : FPGA peripheral raw binary file which
> > > > > > is
> > > > > > used
> > > > > > to
> > > > > > + initialize FPGA IOs, PLL, IO48 and
> > > > > > DDR.
> > > > > > +- bitstream_core : FPGA core raw binary file contains FPGA
> > > > > > design
> > > > > > which is used
> > > > > > +   to program FPGA CRAM and ERAM.
> > > > > > +- bitstream_devpart : Partition of flash device where
> > > > > > bitstream
> > > > > > files are
> > > > > > +      stored.
> > > > > > +   - dev is flash device
> > > > > > number,
> > > > > > part is flash
> > > > > > + device partition.
> > > > > >  
> > > > > >  Example:
> > > > > >  
> > > > > > @@ -16,4 +24,7 @@ Example:
> > > > > >        0xffcfe400 0x20>;
> > > > > >     clocks = <_mp_clk>;
> > > > > >     resets = < FPGAMGR_RESET>;
> > > > > > +   bitstream_periph =
> > > > > > "ghrd_10as066n2.periph.rbf.mkimage";
> > > > > > +   bitstream_core =
> > > > > > "ghrd_10as066n2.core.rbf.mkimage";
> > > > > > +   bitstream_devpart = "0:1";
> > > > > >     };
> > > > > > 
> 
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Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Chee, Tien Fong]

On Rab, 2017-09-27 at 10:30 +0200, Marek Vasut wrote:
> On 09/27/2017 08:05 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:32 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee 
> > > > > > 
> > > > > > These drivers handle FPGA program operation from flash
> > > > > > loading
> > > > > > RBF to memory and then to program FPGA.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee 
> > > > > Did you run checkpatch on this before submitting ? I presume
> > > > > no
> > > > > ...
> > > > > 
> > > > Yeah, i run checkpatch for all patches. What's the issue here?
> > > It should definitely indicate problem with ie. yoda-notation
> > > +if (0 == flashinfo->remaining) {
> > > and indent ...
> > > 
> > No complaint from checkpath. I know someone saying bad for
> > readbility,
> > but yoda-notation at this simple implementation doesn't impact the
> > readbility, and having benefit to leverage detection of compiler on
> > missing "=". Overall, this can help to improve coding quality. I
> > can
> > remove it if this doesn't favored in U-boot.
> It is not welcome and modern gcc warns you about such things .
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > ---
> > > > > >  .../include/mach/fpga_manager_arria10.h|  27
> > > > > > ++
> > > > > >  drivers/fpga/socfpga_arria10.c | 391
> > > > > > -
> > > > > >  include/altera.h   |   6 +
> > > > > >  include/configs/socfpga_common.h   |   4 +
> > > > > >  4 files changed, 425 insertions(+), 3 deletions(-)
> > > > > [...]
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > @@ -112,13 +122,14 @@ static int
> > > > > > wait_for_nconfig_pin_and_nstatus_pin(void)
> > > > > >     unsigned long mask =
> > > > > > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
> > > > > >     ALT_FPGAMGR_IMGCFG_STAT_F2
> > > > > > S_NS
> > > > > > TATU
> > > > > > S_PIN_SET_MSK;
> > > > > >  
> > > > > > -   /* Poll until f2s_nconfig_pin and f2s_nstatus_pin;
> > > > > > loop
> > > > > > until de-asserted,
> > > > > > -    * timeout at 1000ms
> > > > > > +   /*
> > > > > > +    * Poll until f2s_nconfig_pin and f2s_nstatus_pin;
> > > > > > loop
> > > > > > until
> > > > > > +    * de-asserted, timeout at 1000ms
> > > > > >      */
> > > > > >     return wait_for_bit(__func__,
> > > > > >     _manager_base-
> > > > > > >imgcfg_stat,
> > > > > >     mask,
> > > > > > -   false, FPGA_TIMEOUT_MSEC,
> > > > > > false);
> > > > > > +   true, FPGA_TIMEOUT_MSEC,
> > > > > > false);
> > > > > >  }
> > > > > Seems more like a fix, split this out.
> > > > > 
> > > > Okay.
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > >  static int wait_for_f2s_nstatus_pin(unsigned long value)
> > > > > > @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc,
> > > > > > const
> > > > > > void
> > > > > > *rbf_data, size_t rbf_size)
> > > > > >  
> > > > > >     /* Initialize the FPGA Manager */
> > > > > >     status = fpgamgr_program_init((u32 *)rbf_data,
> > > > > > rbf_size);
> > > > > > +
> > > > > >     if (status)
> > > > > >     return status;
> > > > > >  
> > > > > > @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc,
> > > > > > const
> > > > > > void *rbf_data, size_t rbf_size)
> > > > > >  
> > > > > >     return fpgamgr_program_finish();
> > > > > >  }
> > > > > > +
> > > > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > > > +const char *get_cff_filename(const void *fdt, int *len,
> > > > > > u32
> > > > > > core)
> > > > > > +{
> > > > > > +   const char *cff_filename = NULL;
> > > > > > +   const char *cell;
> > > > > > +   int nodeoffset;
> > > > > > +   nodeoffset = fdtdec_next_compatible(fdt, 0,
> > > > > > +    COMPAT_ALTERA_SOCFPGA_FPGA0);
> > > > > > +
> > > > > > +   if (nodeoffset >= 0) {
> > > > > > +   if (core)
> > > > > > +   cell = fdt_getprop(fdt,
> > > > > > +   nodeoffset,
> > > > > > +   "bitstream_core",
> > > > > > +   len);
> > > > > > +   else
> > > > > > +   cell = fdt_getprop(fdt,
> > > > > > nodeoffset,
> > > > > > "bitstream_periph",
> > > > > > +    len);
> > > > > > +
> > > > > > +   if (cell)
> > > > > > +   cff_filename = cell;
> > > > > > +   }
> > > > > > +
> > > > > > +   return cff_filename;
> > > > > > +}
> > > > > 

Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[Chee, Tien Fong]

On Rab, 2017-09-27 at 10:33 +0200, Marek Vasut wrote:
> On 09/27/2017 05:30 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee 
> > > > > > 
> > > > > > Enhance preloader header with both additional program
> > > > > > length
> > > > > > and
> > > > > > program
> > > > > > entry offset attributes, which offset is relative to the
> > > > > > start
> > > > > > of
> > > > > > program
> > > > > > header.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee 
> > > > > > ---
> > > > > >  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +-
> > > > > > -
> > > > > >  1 file changed, 9 insertions(+), 2 deletions(-)
> > > > > > 
> > > > > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > > index 22d9e7f..33c9368 100644
> > > > > > --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > > @@ -11,8 +11,15 @@
> > > > > >     .balignl 64,0xf33db33f;
> > > > > >  
> > > > > >     .word   0x1337c0d3; /* SoCFPGA
> > > > > > preloader
> > > > > > validation word */
> > > > > > -   .word   0xc01df00d; /* Version, flags,
> > > > > > length
> > > > > > */
> > > > > > -   .word   0xcafec0d3; /* Checksum, zero-
> > > > > > pad
> > > > > > */
> > > > > > +   .word   0xc01df00d; /* Header
> > > > > > length(2B),flags(1B),version(1B) */
> > > > > > +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
> > > > > > +   .word   0xfeedface; /* Program length(4B) */
> > > > > Keep this indent intact, then it won't generate these crappy
> > > > > -
> > > > > entries.
> > > > > 
> > > > Are you saying to keep the comment indent intact, and allign
> > > > with
> > > > 1st
> > > > comment  /* SoCFPGA preloader validation word */ ?
> > > Just look at the diff and make sure that it only changes the
> > > relevant
> > > parts, not extras due to indent changes.
> > > 
> > Not get you, which particular change is due to indent changes only?
> > Some changes are for re-writing more descriptive comment. And some
> > new
> > adding header attributes to support Arria 10.
> Aaargh, then don't do two things in one patch.
> 
I can split them.
> > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > +   .word   0xf00dcafe; /*
> > > > > > +    * Program entry
> > > > > > offset(4B),relative
> > > > > > to
> > > > > > +    * the start of program header
> > > > > > +    */
> > > > > > +#endif
> > > > > > +   .word   0xcafec0d3; /* Simple
> > > > > > checksum(2B),spare offset(2B) */
> > > > > >     nop;
> > > > > >  
> > > > > >     b reset;/* SoCFPGA jumps here */
> > > > > > 
> 
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Re: [U-Boot] [U-Boot, 5/5] dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled

[Tom Rini]

On Thu, Sep 28, 2017 at 03:55:24AM +0200, Marek Vasut wrote:
> On 09/28/2017 03:39 AM, Tom Rini wrote:
> > On Thu, Sep 28, 2017 at 09:34:23AM +0800, Bin Meng wrote:
> >> Hi Tom,
> >>
> >> On Thu, Sep 28, 2017 at 12:34 AM, Tom Rini  wrote:
> >>> On Thu, Sep 07, 2017 at 06:13:21AM -0700, Bin Meng wrote:
> >>>
>  When EHCD and xHCD are enabled at the same time, USB storage device
>  driver will fail to read/write from/to the storage device attached
>  to the xHCI interface, due to its transfer blocks exceeds the xHCD
>  driver limitation.
> 
>  With driver model, we have an API to get the controller's maximum
>  transfer size and we can use that to determine the storage driver's
>  capability of read/write.
> 
>  Note: the non-DM version driver is still broken with xHCD and the
>  intent here is not to fix the non-DM one, since the xHCD itself is
>  already broken in places like 3.0 hub support, etc.
> 
>  Signed-off-by: Bin Meng 
>  Tested-by: Stefan Roese 
> >>> [snip]
>  @@ -953,6 +957,17 @@ static void usb_stor_set_max_xfer_blk(struct 
>  us_data *us)
>   #else
>    blk = 20;
>   #endif
>  +#else
>  + ret = usb_get_max_xfer_size(udev, (size_t *));
>  + if (ret < 0) {
>  + /* unimplemented, let's use default 20 */
>  + blk = 20;
>  + } else {
>  + if (size > USHRT_MAX * 512)
>  + blk = USHRT_MAX;
>  + blk = size / 512;
>  + }
>  +#endif
> >>>
> >>> So, Coverity saw this and found an issue (CID 167250), and I was going
> >>> to just fix it, but I'm not sure.  The problem is that we check size >
> >>> (USHRT_MAX * 512), and then assign blk.  Then, we always assign blk, so
> >>> the test above isn't used.  But my background recollection is that
> >>> there's a real issue that's being addressed here.  Can we really just
> >>> always say blk = size / 512 in this case, or did we want to be shifting
> >>> size not blk under the if?  Thanks!
> >>
> >> Did this patch applied to anywhere? I see it is in the usb tree, but
> >> not in the u-boot/master.
> >>
> >> The fix should be:
> >>
> >>  if (size > USHRT_MAX * 512)
> >>  size = USHRT_MAX * 512;
> > 
> > It's in usb/master, and will be in master itself shortly.  Please submit
> > a patch that corrects this and has the Reported-by for Coverity.  Marek,
> > do you want to take it via your tree or should I just grab it?  Thanks!
> 
> A USB patch should always go through -usb , I believe that's an
> established practice .

Aside from when you tell me to just pick up a fix directly, for whatever
appropriate reason, yes.  Which is why I asked.

-- 
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Re: [U-Boot] [PULL] u-boot-usb/master

[Tom Rini]

On Wed, Sep 27, 2017 at 03:35:26PM +0200, Marek Vasut wrote:

> The following changes since commit 9241265f29f3670e380a9859a343ddc14873c46f:
> 
>   Merge git://www.denx.de/git/u-boot-cfi-flash (2017-09-26 19:38:04 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to a939af0c748e2ea1eeb8cf47fa9771a95786de70:
> 
>   usb: dwc2: Align size of invalidating dcache before starting DMA
> (2017-09-27 12:12:23 +0200)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 5/5] dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled

[Marek Vasut]

On 09/28/2017 03:39 AM, Tom Rini wrote:
> On Thu, Sep 28, 2017 at 09:34:23AM +0800, Bin Meng wrote:
>> Hi Tom,
>>
>> On Thu, Sep 28, 2017 at 12:34 AM, Tom Rini  wrote:
>>> On Thu, Sep 07, 2017 at 06:13:21AM -0700, Bin Meng wrote:
>>>
 When EHCD and xHCD are enabled at the same time, USB storage device
 driver will fail to read/write from/to the storage device attached
 to the xHCI interface, due to its transfer blocks exceeds the xHCD
 driver limitation.

 With driver model, we have an API to get the controller's maximum
 transfer size and we can use that to determine the storage driver's
 capability of read/write.

 Note: the non-DM version driver is still broken with xHCD and the
 intent here is not to fix the non-DM one, since the xHCD itself is
 already broken in places like 3.0 hub support, etc.

 Signed-off-by: Bin Meng 
 Tested-by: Stefan Roese 
>>> [snip]
 @@ -953,6 +957,17 @@ static void usb_stor_set_max_xfer_blk(struct us_data 
 *us)
  #else
   blk = 20;
  #endif
 +#else
 + ret = usb_get_max_xfer_size(udev, (size_t *));
 + if (ret < 0) {
 + /* unimplemented, let's use default 20 */
 + blk = 20;
 + } else {
 + if (size > USHRT_MAX * 512)
 + blk = USHRT_MAX;
 + blk = size / 512;
 + }
 +#endif
>>>
>>> So, Coverity saw this and found an issue (CID 167250), and I was going
>>> to just fix it, but I'm not sure.  The problem is that we check size >
>>> (USHRT_MAX * 512), and then assign blk.  Then, we always assign blk, so
>>> the test above isn't used.  But my background recollection is that
>>> there's a real issue that's being addressed here.  Can we really just
>>> always say blk = size / 512 in this case, or did we want to be shifting
>>> size not blk under the if?  Thanks!
>>
>> Did this patch applied to anywhere? I see it is in the usb tree, but
>> not in the u-boot/master.
>>
>> The fix should be:
>>
>>  if (size > USHRT_MAX * 512)
>>  size = USHRT_MAX * 512;
> 
> It's in usb/master, and will be in master itself shortly.  Please submit
> a patch that corrects this and has the Reported-by for Coverity.  Marek,
> do you want to take it via your tree or should I just grab it?  Thanks!

A USB patch should always go through -usb , I believe that's an
established practice .

-- 
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Marek Vasut
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Re: [U-Boot] [U-Boot, 5/5] dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled

[Tom Rini]

On Thu, Sep 28, 2017 at 09:34:23AM +0800, Bin Meng wrote:
> Hi Tom,
> 
> On Thu, Sep 28, 2017 at 12:34 AM, Tom Rini  wrote:
> > On Thu, Sep 07, 2017 at 06:13:21AM -0700, Bin Meng wrote:
> >
> >> When EHCD and xHCD are enabled at the same time, USB storage device
> >> driver will fail to read/write from/to the storage device attached
> >> to the xHCI interface, due to its transfer blocks exceeds the xHCD
> >> driver limitation.
> >>
> >> With driver model, we have an API to get the controller's maximum
> >> transfer size and we can use that to determine the storage driver's
> >> capability of read/write.
> >>
> >> Note: the non-DM version driver is still broken with xHCD and the
> >> intent here is not to fix the non-DM one, since the xHCD itself is
> >> already broken in places like 3.0 hub support, etc.
> >>
> >> Signed-off-by: Bin Meng 
> >> Tested-by: Stefan Roese 
> > [snip]
> >> @@ -953,6 +957,17 @@ static void usb_stor_set_max_xfer_blk(struct us_data 
> >> *us)
> >>  #else
> >>   blk = 20;
> >>  #endif
> >> +#else
> >> + ret = usb_get_max_xfer_size(udev, (size_t *));
> >> + if (ret < 0) {
> >> + /* unimplemented, let's use default 20 */
> >> + blk = 20;
> >> + } else {
> >> + if (size > USHRT_MAX * 512)
> >> + blk = USHRT_MAX;
> >> + blk = size / 512;
> >> + }
> >> +#endif
> >
> > So, Coverity saw this and found an issue (CID 167250), and I was going
> > to just fix it, but I'm not sure.  The problem is that we check size >
> > (USHRT_MAX * 512), and then assign blk.  Then, we always assign blk, so
> > the test above isn't used.  But my background recollection is that
> > there's a real issue that's being addressed here.  Can we really just
> > always say blk = size / 512 in this case, or did we want to be shifting
> > size not blk under the if?  Thanks!
> 
> Did this patch applied to anywhere? I see it is in the usb tree, but
> not in the u-boot/master.
> 
> The fix should be:
> 
>  if (size > USHRT_MAX * 512)
>  size = USHRT_MAX * 512;

It's in usb/master, and will be in master itself shortly.  Please submit
a patch that corrects this and has the Reported-by for Coverity.  Marek,
do you want to take it via your tree or should I just grab it?  Thanks!

-- 
Tom


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Re: [U-Boot] [U-Boot, 5/5] dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled

[Bin Meng]

Hi Tom,

On Thu, Sep 28, 2017 at 12:34 AM, Tom Rini  wrote:
> On Thu, Sep 07, 2017 at 06:13:21AM -0700, Bin Meng wrote:
>
>> When EHCD and xHCD are enabled at the same time, USB storage device
>> driver will fail to read/write from/to the storage device attached
>> to the xHCI interface, due to its transfer blocks exceeds the xHCD
>> driver limitation.
>>
>> With driver model, we have an API to get the controller's maximum
>> transfer size and we can use that to determine the storage driver's
>> capability of read/write.
>>
>> Note: the non-DM version driver is still broken with xHCD and the
>> intent here is not to fix the non-DM one, since the xHCD itself is
>> already broken in places like 3.0 hub support, etc.
>>
>> Signed-off-by: Bin Meng 
>> Tested-by: Stefan Roese 
> [snip]
>> @@ -953,6 +957,17 @@ static void usb_stor_set_max_xfer_blk(struct us_data 
>> *us)
>>  #else
>>   blk = 20;
>>  #endif
>> +#else
>> + ret = usb_get_max_xfer_size(udev, (size_t *));
>> + if (ret < 0) {
>> + /* unimplemented, let's use default 20 */
>> + blk = 20;
>> + } else {
>> + if (size > USHRT_MAX * 512)
>> + blk = USHRT_MAX;
>> + blk = size / 512;
>> + }
>> +#endif
>
> So, Coverity saw this and found an issue (CID 167250), and I was going
> to just fix it, but I'm not sure.  The problem is that we check size >
> (USHRT_MAX * 512), and then assign blk.  Then, we always assign blk, so
> the test above isn't used.  But my background recollection is that
> there's a real issue that's being addressed here.  Can we really just
> always say blk = size / 512 in this case, or did we want to be shifting
> size not blk under the if?  Thanks!

Did this patch applied to anywhere? I see it is in the usb tree, but
not in the u-boot/master.

The fix should be:

 if (size > USHRT_MAX * 512)
 size = USHRT_MAX * 512;

Regards,
Bin
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[U-Boot] [PATCH v2] ARM: zynq: Add support for SYZYGY Hub board

[Tom McLeod]

Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board
contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports
booting from SD.

Signed-off-by: Tom McLeod 
Cc: Michal Simek 
CC: Albert Aribaud 
---
Changes for v2:
  - Append syzygy-hub dtb to the end of the Zynq section in the dts Makefile
as this appears to be the convention, if desired I can change this
  - Add an opalkelly,syzygy-hub compatible line to the syzygy hub dts
  - Clean up the ps7_init_gpl sources, removing old/unnecessary/unused code
and eliminating all checkpatch warnings/errors

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/zynq-syzygy-hub.dts   |  72 
 board/opalkelly/zynq/MAINTAINERS   |   6 +
 board/opalkelly/zynq/Makefile  |   9 +
 board/opalkelly/zynq/board.c   |   1 +
 .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c  | 431 +
 .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h  |  82 
 configs/syzygy_hub_defconfig   |  57 +++
 include/configs/syzygy_hub.h   |  72 
 9 files changed, 732 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/zynq-syzygy-hub.dts
 create mode 100644 board/opalkelly/zynq/MAINTAINERS
 create mode 100644 board/opalkelly/zynq/Makefile
 create mode 100644 board/opalkelly/zynq/board.c
 create mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
 create mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
 create mode 100644 configs/syzygy_hub_defconfig
 create mode 100644 include/configs/syzygy_hub.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 762429c..1a6a8ff 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -135,7 +135,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
-   zynq-zc770-xm013.dtb
+   zynq-zc770-xm013.dtb \
+   zynq-syzygy-hub.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb\
zynqmp-zcu102-revA.dtb  \
diff --git a/arch/arm/dts/zynq-syzygy-hub.dts b/arch/arm/dts/zynq-syzygy-hub.dts
new file mode 100644
index 000..ebd08b4
--- /dev/null
+++ b/arch/arm/dts/zynq-syzygy-hub.dts
@@ -0,0 +1,72 @@
+/*
+ * SYZYGY Hub DTS
+ *
+ *  Copyright (C) 2011 - 2015 Xilinx
+ *  Copyright (C) 2017 Opal Kelly Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+   model = "SYZYGY Hub";
+   compatible = "opalkelly,syzygy-hub", "xlnx,zynq-7000";
+
+   aliases {
+   ethernet0 = 
+   serial0 = 
+   mmc0 = 
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x4000>;
+   };
+
+   chosen {
+   bootargs = "";
+   stdout-path = "serial0:115200n8";
+   };
+
+   usb_phy0: phy0 {
+   #phy-cells = <0>;
+   compatible = "usb-nop-xceiv";
+   reset-gpios = < 47 1>;
+   };
+};
+
+ {
+   ps-clk-frequency = <5000>;
+};
+
+ {
+   status = "okay";
+   phy-mode = "rgmii-id";
+   phy-handle = <_phy>;
+
+   ethernet_phy: ethernet-phy@0 {
+   reg = <0>;
+   device_type = "ethernet-phy";
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   dr_mode = "otg";
+   usb-phy = <_phy0>;
+};
diff --git a/board/opalkelly/zynq/MAINTAINERS b/board/opalkelly/zynq/MAINTAINERS
new file mode 100644
index 000..df4b9b6
--- /dev/null
+++ b/board/opalkelly/zynq/MAINTAINERS
@@ -0,0 +1,6 @@
+ZYNQ BOARD
+M: Tom McLeod 
+S: Maintained
+F: board/opalkelly/zynq/
+F: include/configs/syzygy_hub.h
+F: configs/syzygy_hub_defconfig
diff --git a/board/opalkelly/zynq/Makefile b/board/opalkelly/zynq/Makefile
new file mode 100644
index 000..09fc788
--- /dev/null
+++ b/board/opalkelly/zynq/Makefile
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := board.o
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
diff --git a/board/opalkelly/zynq/board.c b/board/opalkelly/zynq/board.c
new file mode 100644
index 000..a95c9d1
--- /dev/null
+++ b/board/opalkelly/zynq/board.c
@@ -0,0 +1 @@
+#include "../../xilinx/zynq/board.c"
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c 
b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
new file mode 100644
index 000..7ae0475
--- /dev/null
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -0,0 +1,431 @@

Re: [U-Boot] [PATCH] mx7ulp_evk: Move CONFIG_CMD_BOOTZ to Kconfig

[Peng Fan]

> -Original Message-
> From: Fabio Estevam [mailto:fabio.este...@nxp.com]
> Sent: Thursday, September 28, 2017 2:01 AM
> To: sba...@denx.de
> Cc: Peng Fan ; u-boot@lists.denx.de; Fabio Estevam
> 
> Subject: [PATCH] mx7ulp_evk: Move CONFIG_CMD_BOOTZ to Kconfig
> 
> CONFIG_CMD_BOOTZ symbol does not work in board config file anymore, so
> fix this by moving it to Kconfig.
> 
> Signed-off-by: Fabio Estevam 

Reviewed-by: Peng Fan 

> ---
>  configs/mx7ulp_evk_defconfig | 1 +
>  include/configs/mx7ulp_evk.h | 1 -
>  2 files changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
> index d630113..0470fbd 100644
> --- a/configs/mx7ulp_evk_defconfig
> +++ b/configs/mx7ulp_evk_defconfig
> @@ -4,6 +4,7 @@ CONFIG_TARGET_MX7ULP_EVK=y
> CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
> 
> CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/i
> mximage.cfg"
>  CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_BOOTZ=y
>  CONFIG_CMD_GPIO=y
>  CONFIG_CMD_I2C=y
>  CONFIG_CMD_MMC=y
> diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
> index a7992ea..56d74e9 100644
> --- a/include/configs/mx7ulp_evk.h
> +++ b/include/configs/mx7ulp_evk.h
> @@ -90,7 +90,6 @@
>  #define PHYS_SDRAM_SIZE  SZ_1G
>  #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
>  #define CONFIG_SYS_SDRAM_BASEPHYS_SDRAM
> -#define CONFIG_CMD_BOOTZ
> 
>  #define CONFIG_LOADADDR 0x6080
> 
> --
> 2.7.4

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[U-Boot] [PATCH 2/2] ARM: rmobile: Enable pinconf

[Marek Vasut]

Enable pinconf since it's now implemented and used in the DTs.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 configs/r8a7795_salvator-x_defconfig | 1 +
 configs/r8a7795_ulcb_defconfig   | 1 +
 configs/r8a7796_salvator-x_defconfig | 1 +
 configs/r8a7796_ulcb_defconfig   | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/r8a7795_salvator-x_defconfig 
b/configs/r8a7795_salvator-x_defconfig
index 7a60100455..8690902f4b 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -42,6 +42,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_PINCTRL_PFC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
index 1aa2e69ac6..58ba3fdf2a 100644
--- a/configs/r8a7795_ulcb_defconfig
+++ b/configs/r8a7795_ulcb_defconfig
@@ -35,6 +35,7 @@ CONFIG_MMC_UNIPHIER=y
 CONFIG_DM_ETH=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_PINCTRL_PFC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/r8a7796_salvator-x_defconfig 
b/configs/r8a7796_salvator-x_defconfig
index 083a832c56..e71b37fa97 100644
--- a/configs/r8a7796_salvator-x_defconfig
+++ b/configs/r8a7796_salvator-x_defconfig
@@ -43,6 +43,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_PINCTRL_PFC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
index cbeda77bfd..5ea832ff49 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/r8a7796_ulcb_defconfig
@@ -36,6 +36,7 @@ CONFIG_MMC_UNIPHIER=y
 CONFIG_DM_ETH=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_PINCTRL_PFC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
-- 
2.11.0

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[U-Boot] [PATCH V2 1/2] pinctrl: rmobile: Add pinconf to Renesas RCar pincontrol driver

[Marek Vasut]

Add pinconf support to the PFC driver, so that it can handle DT
props bias-disable, bias-pull-up, bias-pull-down, drive-strength
and power-source.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
V2: Unlock the pincontrol registers via PMMR when setting drive
strength and power source
---
 drivers/pinctrl/renesas/pfc.c | 187 ++
 1 file changed, 187 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 63e2eeb449..1675485d66 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -477,6 +477,188 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev, 
unsigned group_selector
 done:
return ret;
 }
+#if CONFIG_IS_ENABLED(PINCONF)
+static const struct pinconf_param sh_pfc_pinconf_params[] = {
+   { "bias-disable",   PIN_CONFIG_BIAS_DISABLE,0 },
+   { "bias-pull-up",   PIN_CONFIG_BIAS_PULL_UP,1 },
+   { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN,  1 },
+   { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH,  0 },
+   { "power-source",   PIN_CONFIG_POWER_SOURCE,3300 },
+};
+
+static void __iomem *
+sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
+  unsigned int *offset, unsigned int *size)
+{
+   const struct pinmux_drive_reg_field *field;
+   const struct pinmux_drive_reg *reg;
+   unsigned int i;
+
+   for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
+   for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
+   field = >fields[i];
+
+   if (field->size && field->pin == pin) {
+   *offset = field->offset;
+   *size = field->size;
+
+   return (void __iomem *)(uintptr_t)reg->reg;
+   }
+   }
+   }
+
+   return NULL;
+}
+
+static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
+unsigned int pin, u16 strength)
+{
+   unsigned int offset;
+   unsigned int size;
+   unsigned int step;
+   void __iomem *reg;
+   void __iomem *unlock_reg =
+   (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
+   u32 val;
+
+   reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, , );
+   if (!reg)
+   return -EINVAL;
+
+   step = size == 2 ? 6 : 3;
+
+   if (strength < step || strength > 24)
+   return -EINVAL;
+
+   /* Convert the value from mA based on a full drive strength value of
+* 24mA. We can make the full value configurable later if needed.
+*/
+   strength = strength / step - 1;
+
+   val = sh_pfc_read_raw_reg(reg, 32);
+   val &= ~GENMASK(offset + size - 1, offset);
+   val |= strength << offset;
+
+   if (unlock_reg)
+   sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
+
+   sh_pfc_write_raw_reg(reg, 32, val);
+
+   return 0;
+}
+
+/* Check whether the requested parameter is supported for a pin. */
+static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
+   unsigned int param)
+{
+   int idx = sh_pfc_get_pin_index(pfc, _pin);
+   const struct sh_pfc_pin *pin = >info->pins[idx];
+
+   switch (param) {
+   case PIN_CONFIG_BIAS_DISABLE:
+   return pin->configs &
+   (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
+
+   case PIN_CONFIG_BIAS_PULL_UP:
+   return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
+
+   case PIN_CONFIG_BIAS_PULL_DOWN:
+   return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
+
+   case PIN_CONFIG_DRIVE_STRENGTH:
+   return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
+
+   case PIN_CONFIG_POWER_SOURCE:
+   return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
+
+   default:
+   return false;
+   }
+}
+
+static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
+ unsigned int param, unsigned int arg)
+{
+   struct sh_pfc *pfc = pmx->pfc;
+   void __iomem *pocctrl;
+   void __iomem *unlock_reg =
+   (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
+   u32 addr, val;
+   int bit, ret;
+
+   if (!sh_pfc_pinconf_validate(pfc, _pin, param))
+   return -ENOTSUPP;
+
+   switch (param) {
+   case PIN_CONFIG_BIAS_PULL_UP:
+   case PIN_CONFIG_BIAS_PULL_DOWN:
+   case PIN_CONFIG_BIAS_DISABLE:
+   if (!pfc->info->ops || !pfc->info->ops->set_bias)
+   return -ENOTSUPP;
+
+   pfc->info->ops->set_bias(pfc, _pin, param);
+
+   break;
+
+   case PIN_CONFIG_DRIVE_STRENGTH:
+   ret = 

Re: [U-Boot] rockchip: rk3036: fix grf macro define

[Philipp Tomsich]

> Some of macros definition are not correct, fix them according to TRM.
> 
> Signed-off-by: Kever Yang 
> Reviewed-by: Philipp Tomsich 
> ---
> 
>  arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROM

[Philipp Tomsich]

> Instead of directly calling into the back-to-bootrom code, the RK3399
> common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a
> transfer back into the bootrom.
> 
> With this factored out, the spl_board_init function can not be
> customised for each RK3399 board.
> 
> Signed-off-by: Philipp Tomsich 
> Reviewed-by: Simon Glass 
> ---
> 
>  arch/arm/mach-rockchip/rk3399-board-spl.c | 18 +-
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] rockchip: clk: fix typo in rk322x clock driver

[Philipp Tomsich]

> Fix typo RK322X/RK3036 in rk322x clock driver.
> 
> Signed-off-by: Kever Yang 
> Reviewed-by: Philipp Tomsich 
> ---
> 
>  drivers/clk/rockchip/clk_rk322x.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] rockchip: mkimage: add support for rk3128 soc

[Philipp Tomsich]

> Add support for rk3128 package header in mkimage tool.
> 
> Signed-off-by: Kever Yang 
> Reviewed-by: Philipp Tomsich 
> ---
> 
>  tools/rkcommon.c | 1 +
>  1 file changed, 1 insertion(+)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] rockchip: mkimage: add support for rk3128 soc

[Philipp Tomsich]

> Add support for rk3128 package header in mkimage tool.
> 
> Signed-off-by: Kever Yang 
> ---
> 
>  tools/rkcommon.c | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] rockchip: clk: fix typo in rk322x clock driver

[Philipp Tomsich]

> Fix typo RK322X/RK3036 in rk322x clock driver.
> 
> Signed-off-by: Kever Yang 
> ---
> 
>  drivers/clk/rockchip/clk_rk322x.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] rockchip: mkimage: add support for rk3128 soc

[Philipp Tomsich]

> Add support for rk3128 package header in mkimage tool.
> 
> Signed-off-by: Kever Yang 
> ---
> 
>  tools/rkcommon.c | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] rockchip: rk3036: fix grf macro define

[Philipp Tomsich]

> Some of macros definition are not correct, fix them according to TRM.
> 
> Signed-off-by: Kever Yang 
> Reviewed-by: Philipp Tomsich 
> ---
> 
>  arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] rockchip: clk: fix typo in rk322x clock driver

[Philipp Tomsich]

> Fix typo RK322X/RK3036 in rk322x clock driver.
> 
> Signed-off-by: Kever Yang 
> ---
> 
>  drivers/clk/rockchip/clk_rk322x.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] rockchip: rk3036: fix grf macro define

[Philipp Tomsich]

> Some of macros definition are not correct, fix them according to TRM.
> 
> Signed-off-by: Kever Yang 
> ---
> 
>  arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [PATCH 1/2] pinctrl: rmobile: Add Renesas RCar pincontrol driver

[Marek Vasut]

On 09/25/2017 10:52 PM, Marek Vasut wrote:
> Add pinconf support to the PFC driver, so that it can handle DT
> props bias-disable, bias-pull-up, bias-pull-down, drive-strength
> and power-source.
> 
> Signed-off-by: Marek Vasut 
> Cc: Nobuhiro Iwamatsu 
Please ignore, V2 is coming.

> ---
>  drivers/pinctrl/renesas/pfc.c | 176 
> ++
>  1 file changed, 176 insertions(+)
> 
> diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
> index 63e2eeb449..53139d7a26 100644
> --- a/drivers/pinctrl/renesas/pfc.c
> +++ b/drivers/pinctrl/renesas/pfc.c
> @@ -477,6 +477,177 @@ static int sh_pfc_pinctrl_group_set(struct udevice 
> *dev, unsigned group_selector
>  done:
>   return ret;
>  }
> +#if CONFIG_IS_ENABLED(PINCONF)
> +static const struct pinconf_param sh_pfc_pinconf_params[] = {
> + { "bias-disable",   PIN_CONFIG_BIAS_DISABLE,0 },
> + { "bias-pull-up",   PIN_CONFIG_BIAS_PULL_UP,1 },
> + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN,  1 },
> + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH,  0 },
> + { "power-source",   PIN_CONFIG_POWER_SOURCE,3300 },
> +};
> +
> +static void __iomem *
> +sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
> +unsigned int *offset, unsigned int *size)
> +{
> + const struct pinmux_drive_reg_field *field;
> + const struct pinmux_drive_reg *reg;
> + unsigned int i;
> +
> + for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
> + for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
> + field = >fields[i];
> +
> + if (field->size && field->pin == pin) {
> + *offset = field->offset;
> + *size = field->size;
> +
> + return (void __iomem *)(uintptr_t)reg->reg;
> + }
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
> +  unsigned int pin, u16 strength)
> +{
> + unsigned int offset;
> + unsigned int size;
> + unsigned int step;
> + void __iomem *reg;
> + u32 val;
> +
> + reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, , );
> + if (!reg)
> + return -EINVAL;
> +
> + step = size == 2 ? 6 : 3;
> +
> + if (strength < step || strength > 24)
> + return -EINVAL;
> +
> + /* Convert the value from mA based on a full drive strength value of
> +  * 24mA. We can make the full value configurable later if needed.
> +  */
> + strength = strength / step - 1;
> +
> + val = sh_pfc_read_raw_reg(reg, 32);
> + val &= ~GENMASK(offset + size - 1, offset);
> + val |= strength << offset;
> +
> + sh_pfc_write_raw_reg(reg, 32, val);
> +
> + return 0;
> +}
> +
> +/* Check whether the requested parameter is supported for a pin. */
> +static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
> + unsigned int param)
> +{
> + int idx = sh_pfc_get_pin_index(pfc, _pin);
> + const struct sh_pfc_pin *pin = >info->pins[idx];
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + return pin->configs &
> + (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
> +
> + case PIN_CONFIG_BIAS_PULL_UP:
> + return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
> +
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
> +
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
> +
> + case PIN_CONFIG_POWER_SOURCE:
> + return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
> +
> + default:
> + return false;
> + }
> +}
> +
> +static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
> +   unsigned int param, unsigned int arg)
> +{
> + struct sh_pfc *pfc = pmx->pfc;
> + void __iomem *pocctrl;
> + u32 addr, val;
> + int bit, ret;
> +
> + if (!sh_pfc_pinconf_validate(pfc, _pin, param))
> + return -ENOTSUPP;
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_PULL_UP:
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + case PIN_CONFIG_BIAS_DISABLE:
> + if (!pfc->info->ops || !pfc->info->ops->set_bias)
> + return -ENOTSUPP;
> +
> + pfc->info->ops->set_bias(pfc, _pin, param);
> +
> + break;
> +
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
> + if (ret < 0)
> + return ret;
> +
> + break;
> +
> + case PIN_CONFIG_POWER_SOURCE:
> + 

Re: [U-Boot] [PATCH 1/1] rockchip: rk3399: spl: implicit declaration back_to_bootrom

[Dr. Philipp Tomsich]

On 27 Sep 2017, at 21:05, Heinrich Schuchardt  wrote:
> 
> Without #include asm/arch-rockchip/bootrom.h we get:
> 
> arch/arm/mach-rockchip/rk3399-board-spl.c:162:2:
> warning: implicit declaration of function ‘back_to_bootrom’
> [-Wimplicit-function-declaration]
> 
> for CONFIG_ROCKCHIP_BACK_TO_BROM=y

We already had the conversion of the rk3399 SPL support to use
BOOT_DEVICE_BOOTROM scheduled in
https://patchwork.ozlabs.org/patch/812308/

Looks like this got lost somewhere along the way together with
a few other changes from around that time.  I’ll need to look into
what happened there.

> Signed-off-by: Heinrich Schuchardt 
> ---
> v2:
>   rebase to rockchip/master HEAD
> ---
> arch/arm/mach-rockchip/rk3399-board-spl.c | 1 +
> 1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c 
> b/arch/arm/mach-rockchip/rk3399-board-spl.c
> index 3406156447..37c48bd1dd 100644
> --- a/arch/arm/mach-rockchip/rk3399-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
> @@ -9,6 +9,7 @@
> #include 
> #include 
> #include 
> +#include 
> #include 
> #include 
> #include 
> -- 
> 2.14.1
> 

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[U-Boot] Rainbow Screen of Death - Raspberry PI Current u-boot master

[Duncan Hare]

I pulled the latest master from git clone git://git.denx.de/u-boot.gitbuilt the 
raspberry pi imagemake r_3_32b_defconfigmakecopied the u-boot bin the a working 
sd cardand I get the rainbow screen of death from the pi.
When I use a u-boot.bin build from a git clone of u-boot in about Jan 2017, it 
works.
Just to reassure myself I was not doing something stupid, I did a second 
time.Deleted the u-boot directory and re-ran the git clone
Suggestions? If you need a pi for testing, I'll send one. with sd card, fedex.
ThanksDuncan Hare

714 931 7952
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Re: [U-Boot] [PATCH v2 5/6] ARM: Add a new arch + board for QEMU's 'virt' machine

[Peter Robinson]

>> Hi Tuomas,
>>
>> On Wed, Sep 20, 2017 at 4:18 AM, Tuomas Tynkkynen
>>  wrote:
>>>
>>> This board builds an U-Boot binary that is bootable with QEMU's 'virt'
>>> machine on ARM. The minimal QEMU command line is:
>>>
>>>  qemu-system-arm -machine virt,highmem=off -bios u-boot.bin
>>>
>>> (Note that the 'highmem=off' parameter to the 'virt' machine is required
>>> for
>>> PCI to work in U-Boot.) This command line enables the following:
>>>  - u-boot.bin loaded and executing in the emulated flash at address
>>> 0x0
>>>  - A generated device tree blob placed at the start of RAM
>>>  - A freely configurable amount of RAM, described by the DTB
>>>  - A PL011 serial port, discoverable via the DTB
>>>  - An ARMv7 architected timer
>>>  - PSCI for rebooting the system
>>>  - A generic ECAM-based PCI host controller, discoverable via the DTB
>>>
>>> Additionally, QEMU allows plugging a bunch of useful peripherals to the
>>> PCI bus.
>>> The following ones are supported by both U-Boot and Linux:
>>>
>>> - To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.:
>>>  -drive if=none,file=disk.img,id=mydisk -device ich9-ahci,id=ahci
>>> -device ide-drive,drive=mydisk,bus=ahci.0
>>> - To add an Intel E1000 network adapter, pass e.g.:
>>>  -net nic,model=e1000 -net user
>>
>>
>> With this parameter I got:
>>
>> Warning: requested NIC (anonymous, model e1000) was not created (not
>> supported by this machine?)
>>
>> I am using QEMU v2.5.0. It's better to mention the minimum required
>> QEMU version in the commit message as well.
>>
>
> I primarily tested with 2.9.0, but I found out that it will work in 2.5.0 as
> well by changing the syntax to
> -netdev user,id=net0 -device e1000,netdev=net0
> I will update the commit message accordingly.

I wonder how hard it would be to support virtio interfaces for
network/storage, that would provide a fast/standard interface.

Peter
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Re: [U-Boot] [PATCH] mmc: uniphier-sd: Add vqmmc regulator support

[Marek Vasut]

On 09/27/2017 06:13 PM, Masahiro Yamada wrote:
> 2017-09-28 0:50 GMT+09:00 Marek Vasut :
>> On 09/27/2017 05:19 PM, Masahiro Yamada wrote:
>>> 2017-09-26 16:41 GMT+09:00 Jaehoon Chung :
 Hi Marek,

 On 09/26/2017 01:47 AM, Marek Vasut wrote:
> On 09/15/2017 09:10 PM, Marek Vasut wrote:
>> Add initial support for setting the vqmmc regulator. Since we do not
>> support 1V8 modes, set the regulator to 3V3 and enable it.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Masahiro Yamada 
>> Cc: Jaehoon Chung 
>
> Anything ?! I don't see this in the PR ...

 Sorry...I missed this patch..First, i have checked on patchwork.
 Will pick this patch into u-boot-mmc.

 Best Regards,
 Jaehoon Chung

>>>
>>>
>>> UniPhier SoCs have different mechanism for 3.3/1.8 switching,
>>> but it is not a problem for me because I do not have a plan
>>> for enabling CONFIG_DM_REGULATOR.
>>>
>>> Acked-by: Masahiro Yamada 
>>
>> Cool, thanks!
>>
>> Is there a documentation for the uniphier mechanism somewhere ?
>>
> 
> No document available.

I hope that new 96borad will have documentation available, *ahem* :-)

> Only crappy private documents.
> 
> They say SoC spec books are CONFIDENTIAL!!
> Sigh.

OK, I'll keep in mind there's a uniphier-specific way to toggle the 1V8
when adding HS200 support, so you can fill that in when you have time.

Thanks!

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH 1/1] rockchip: rk3399: spl: implicit declaration back_to_bootrom

[Heinrich Schuchardt]

Without #include asm/arch-rockchip/bootrom.h we get:

arch/arm/mach-rockchip/rk3399-board-spl.c:162:2:
warning: implicit declaration of function ‘back_to_bootrom’
[-Wimplicit-function-declaration]

for CONFIG_ROCKCHIP_BACK_TO_BROM=y

Signed-off-by: Heinrich Schuchardt 
---
v2:
rebase to rockchip/master HEAD
---
 arch/arm/mach-rockchip/rk3399-board-spl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c 
b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 3406156447..37c48bd1dd 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-- 
2.14.1

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[U-Boot] [PATCH 1/1] rockchip: rk3399: spl: implicit declaration back_to_bootrom

[Heinrich Schuchardt]

Without #include asm/arch-rockchip/bootrom.h we get:

arch/arm/mach-rockchip/rk3399-board-spl.c:162:2:
warning: implicit declaration of function ‘back_to_bootrom’
[-Wimplicit-function-declaration]

for CONFIG_ROCKCHIP_BACK_TO_BROM=y

Signed-off-by: Heinrich Schuchardt 
---
 arch/arm/mach-rockchip/rk3399-board-spl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c 
b/arch/arm/mach-rockchip/rk3399-board-spl.c
index d6bf74f7ad..014b8afba0 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
-- 
2.14.1

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[U-Boot] [PATCH 1/1] evb-rk3399: avoid redefinition of CONFIG_ENV_OFFSET

[Heinrich Schuchardt]

CONFIG_ENV_OFFSET is already defined in
include/configs/rockchip-common.h

For CONFIG_ROCKCHIP_BACK_TO_BROM=y we redefine CONFIG_ENV_OFFSET
to an unsuitable value. We were lucky to get a compiler warning.

Remove the incorrect redefinition.

Signed-off-by: Heinrich Schuchardt 
---
 include/configs/evb_rk3399.h | 6 --
 1 file changed, 6 deletions(-)

diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
index 015f25a774..66ead6c117 100644
--- a/include/configs/evb_rk3399.h
+++ b/include/configs/evb_rk3399.h
@@ -10,12 +10,6 @@
 #include 
 
 #define CONFIG_SYS_MMC_ENV_DEV 1
-/*
- * SPL @ 32k for ~36k
- * ENV @ 96k
- * u-boot @ 128K
- */
-#define CONFIG_ENV_OFFSET (96 * 1024)
 
 #define SDRAM_BANK_SIZE(2UL << 30)
 
-- 
2.14.1

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[U-Boot] [PATCH] mx7ulp_evk: Move CONFIG_CMD_BOOTZ to Kconfig

[Fabio Estevam]

CONFIG_CMD_BOOTZ symbol does not work in board config file
anymore, so fix this by moving it to Kconfig.

Signed-off-by: Fabio Estevam 
---
 configs/mx7ulp_evk_defconfig | 1 +
 include/configs/mx7ulp_evk.h | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index d630113..0470fbd 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MX7ULP_EVK=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index a7992ea..56d74e9 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -90,7 +90,6 @@
 #define PHYS_SDRAM_SIZESZ_1G
 #define CONFIG_SYS_MEMTEST_START   PHYS_SDRAM
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM
-#define CONFIG_CMD_BOOTZ
 
 #define CONFIG_LOADADDR 0x6080
 
-- 
2.7.4

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[U-Boot] [PATCH v2 3/5] rk3288: vyasa: Add TPL support

[Chakra Divi]

From: Jagan Teki 

Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.

So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc

Signed-off-by: Jagan Teki 
Reviewed-by: Philipp Tomsich 
---
Changes for v2:
- Drop console output from commit message
- Updated licence note
- Moved read/write L2CTRL and configure_l2ctlr to common
- Moved debug header in include files list
- Moved preprocessor macro to top
Note:
Idea is not to build this in SPL when TPL enabled,
so CONFIG_SUPPORT_TPL work that case.

 arch/arm/mach-rockchip/Makefile   |  1 +
 arch/arm/mach-rockchip/rk3288-board-spl.c |  3 ++
 arch/arm/mach-rockchip/rk3288-board-tpl.c | 84 +++
 arch/arm/mach-rockchip/rk3288/Kconfig | 16 ++
 configs/vyasa-rk3288_defconfig|  3 ++
 doc/README.rockchip   | 18 +++
 include/configs/rk3288_common.h   |  6 ++-
 7 files changed, 130 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 79e9704..daafc8d 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -12,6 +12,7 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o 
save_boot_param.o
 obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
 
 obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
+obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
 obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
 
 obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 23af653..5239cbc 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -204,12 +204,15 @@ void board_init_f(ulong dummy)
}
 #endif
 
+#if !defined(CONFIG_SUPPORT_TPL)
debug("\nspl:init dram\n");
ret = uclass_get_device(UCLASS_RAM, 0, );
if (ret) {
debug("DRAM init failed: %d\n", ret);
return;
}
+#endif
+
 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
 #endif
diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c 
b/arch/arm/mach-rockchip/rk3288-board-tpl.c
new file mode 100644
index 000..3d08b5b
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288-board-tpl.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2017 Amarula Solutions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GRF_BASE   0xff77
+void board_init_f(ulong dummy)
+{
+   struct udevice *dev;
+   int ret;
+
+   /* Example code showing how to enable the debug UART on RK3288 */
+   /* Enable early UART on the RK3288 */
+   struct rk3288_grf * const grf = (void *)GRF_BASE;
+
+   rk_clrsetreg(>gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
+GPIO7C6_MASK << GPIO7C6_SHIFT,
+GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
+GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+   /*
+* Debug UART can be used from here if required:
+*
+* debug_uart_init();
+* printch('a');
+* printhex8(0x1234);
+* printascii("string");
+*/
+   debug_uart_init();
+
+   ret = spl_early_init();
+   if (ret) {
+   debug("spl_early_init() failed: %d\n", ret);
+   hang();
+   }
+
+   rockchip_timer_init();
+   configure_l2ctlr();
+
+   ret = rockchip_get_clk();
+   if (ret) {
+   debug("CLK init failed: %d\n", ret);
+   return;
+   }
+
+   ret = uclass_get_device(UCLASS_RAM, 0, );
+   if (ret) {
+   debug("DRAM init failed: %d\n", ret);
+   return;
+   }
+}
+
+void board_return_to_bootrom(void)
+{
+   back_to_bootrom();
+}
+
+u32 spl_boot_device(void)
+{
+   return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_board_init(void)
+{
+   puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
+   U_BOOT_TIME ")\n");
+}
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
b/arch/arm/mach-rockchip/rk3288/Kconfig
index 4ad2940..6beb26f 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -87,6 +87,22 @@ config TARGET_POPMETAL_RK3288
 config TARGET_VYASA_RK3288
bool "Vyasa-RK3288"
select BOARD_LATE_INIT
+   select TPL
+   select SUPPORT_TPL
+   select TPL_DM
+   select 

[U-Boot] [PATCH v2 4/5] rk3288: vyasa: Add falcon mode support

[Chakra Divi]

From: Jagan Teki 

Add Falcon mode support in vyasa rk3288 board.

Signed-off-by: Jagan Teki 
Reviewed-by: Philipp Tomsich 
Acked-by: Philipp Tomsich 
---
Changes for v2:
- none 

 board/amarula/vyasa-rk3288/vyasa-rk3288.c | 13 +
 include/configs/vyasa-rk3288.h| 17 +
 2 files changed, 30 insertions(+)

diff --git a/board/amarula/vyasa-rk3288/vyasa-rk3288.c 
b/board/amarula/vyasa-rk3288/vyasa-rk3288.c
index ceee42c..7985671 100644
--- a/board/amarula/vyasa-rk3288/vyasa-rk3288.c
+++ b/board/amarula/vyasa-rk3288/vyasa-rk3288.c
@@ -5,3 +5,16 @@
  */
 
 #include 
+
+#ifndef CONFIG_TPL_BUILD
+#include 
+
+int spl_start_uboot(void)
+{
+/* break into full u-boot on 'c' */
+if (serial_tstc() && serial_getc() == 'c')
+return 1;
+
+return 0;
+}
+#endif
diff --git a/include/configs/vyasa-rk3288.h b/include/configs/vyasa-rk3288.h
index 9d6c80f..8774e42 100644
--- a/include/configs/vyasa-rk3288.h
+++ b/include/configs/vyasa-rk3288.h
@@ -20,4 +20,21 @@
 #define CONFIG_SYS_MMC_ENV_DEV 1
 #undef CONFIG_CMD_USB_MASS_STORAGE
 
+#ifndef CONFIG_TPL_BUILD
+
+#define CONFIG_SPL_OS_BOOT
+
+/* Falcon Mode */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME   "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR   0x0ffe5000
+#define CONFIG_CMD_SPL_WRITE_SIZE  (128 * SZ_1K)
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 
512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR0x1000  /* 2MB */
+#endif
+
 #endif
-- 
2.7.4

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[U-Boot] [PATCH v2 5/5] rk3288: spl: Add dram_init_banksize

[Chakra Divi]

From: Jagan Teki 

Falcon mode, is updating DDR dt node configuration through
spl_fixup_fdt() so add appropriate DDR base and size through
dram_init_banksize.

Signed-off-by: Jagan Teki 
Reviewed-by: Philipp Tomsich 
Acked-by: Philipp Tomsich 
---
Changes for v2:
- none 

 arch/arm/mach-rockchip/rk3288-board-spl.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 5239cbc..7b7fd5a 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -19,7 +19,9 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -290,3 +292,18 @@ err:
/* No way to report error here */
hang();
 }
+
+#ifdef CONFIG_SPL_OS_BOOT
+
+#define PMU_BASE   0xff73
+int dram_init_banksize(void)
+{
+   struct rk3288_pmu *const pmu = (void *)PMU_BASE;
+   size_t size = rockchip_sdram_size((phys_addr_t)>sys_reg[2]);
+
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   gd->bd->bi_dram[0].size = size;
+
+   return 0;
+}
+#endif
-- 
2.7.4

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[U-Boot] [PATCH v2 1/5] armv7: Move L2CTLR read/write to common

[Chakra Divi]

From: Jagan Teki 

L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.

Cc: Tom Warren 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- New patch

 arch/arm/include/asm/armv7.h  | 21 +
 arch/arm/mach-rockchip/rk3288-board-spl.c | 22 +-
 arch/arm/mach-tegra/cache.c   |  5 +++--
 3 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index a20702e..efc515e 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -61,6 +61,27 @@
 #include 
 #include 
 
+/* read L2 control register (L2CTLR) */
+static inline uint32_t read_l2ctlr(void)
+{
+   uint32_t val = 0;
+
+   asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
+
+   return val;
+}
+
+/* write L2 control register (L2CTLR) */
+static inline void write_l2ctlr(uint32_t val)
+{
+   /*
+* Note: L2CTLR can only be written when the L2 memory system
+* is idle, ie before the MMU is enabled.
+*/
+   asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
+   isb();
+}
+
 /*
  * Workaround for ARM errata # 798870
  * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 6b7bf85..8a1066c 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -80,27 +81,6 @@ u32 spl_boot_mode(const u32 boot_device)
return MMCSD_MODE_RAW;
 }
 
-/* read L2 control register (L2CTLR) */
-static inline uint32_t read_l2ctlr(void)
-{
-   uint32_t val = 0;
-
-   asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
-
-   return val;
-}
-
-/* write L2 control register (L2CTLR) */
-static inline void write_l2ctlr(uint32_t val)
-{
-   /*
-* Note: L2CTLR can only be written when the L2 memory system
-* is idle, ie before the MMU is enabled.
-*/
-   asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
-   isb();
-}
-
 static void configure_l2ctlr(void)
 {
uint32_t l2ctlr;
diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c
index 6dad403..2f3f822 100644
--- a/arch/arm/mach-tegra/cache.c
+++ b/arch/arm/mach-tegra/cache.c
@@ -7,6 +7,7 @@
 /* Tegra cache routines */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,9 +31,9 @@ void config_cache(void)
 * Systems with an architectural L2 cache must not use the PL310.
 * Config L2CTLR here for a data RAM latency of 3 cycles.
 */
-   asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
+   reg = read_l2ctlr();
reg &= ~7;
reg |= 2;
-   asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
+   write_l2ctlr(reg);
 }
 #endif
-- 
2.7.4

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[U-Boot] [PATCH v2 2/5] armv7: rk3288: Move configure_l2ctlr to common

[Chakra Divi]

From: Jagan Teki 

configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h

Signed-off-by: Jagan Teki 
---
Changes for v2:
- New patch

 arch/arm/include/asm/arch-rockchip/sys_proto.h | 23 +++
 arch/arm/mach-rockchip/rk3288-board-spl.c  | 21 +
 2 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h 
b/arch/arm/include/asm/arch-rockchip/sys_proto.h
index 35423e1..e428d59 100644
--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -7,4 +7,27 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
+#ifdef CONFIG_ROCKCHIP_RK3288
+#include 
+
+static void configure_l2ctlr(void)
+{
+   uint32_t l2ctlr;
+
+   l2ctlr = read_l2ctlr();
+   l2ctlr &= 0xfffc; /* clear bit0~bit17 */
+
+   /*
+   * Data RAM write latency: 2 cycles
+   * Data RAM read latency: 2 cycles
+   * Data RAM setup latency: 1 cycle
+   * Tag RAM write latency: 1 cycle
+   * Tag RAM read latency: 1 cycle
+   * Tag RAM setup latency: 1 cycle
+   */
+   l2ctlr |= (1 << 3 | 1 << 0);
+   write_l2ctlr(l2ctlr);
+}
+#endif /* CONFIG_ROCKCHIP_RK3288 */
+
 #endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 8a1066c..23af653 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -13,7 +13,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -21,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -81,25 +81,6 @@ u32 spl_boot_mode(const u32 boot_device)
return MMCSD_MODE_RAW;
 }
 
-static void configure_l2ctlr(void)
-{
-   uint32_t l2ctlr;
-
-   l2ctlr = read_l2ctlr();
-   l2ctlr &= 0xfffc; /* clear bit0~bit17 */
-
-   /*
-   * Data RAM write latency: 2 cycles
-   * Data RAM read latency: 2 cycles
-   * Data RAM setup latency: 1 cycle
-   * Tag RAM write latency: 1 cycle
-   * Tag RAM read latency: 1 cycle
-   * Tag RAM setup latency: 1 cycle
-   */
-   l2ctlr |= (1 << 3 | 1 << 0);
-   write_l2ctlr(l2ctlr);
-}
-
 #ifdef CONFIG_SPL_MMC_SUPPORT
 static int configure_emmc(struct udevice *pinctrl)
 {
-- 
2.7.4

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[U-Boot] [PATCH v2 0/5] rk3288: Falcon mode support

[Chakra Divi]

From: Jagan Teki 

Updated with fixing previous version changes.

Hi Philipp,
TPL working fine but Falcon mode is not working in latest master
- hang at mmc read [1] with CMD 12, hoping that Debug uart not printing
  further on console.

Let me know if you find any, same patches work fine on previous version
with sha1 [2]

[1] https://paste.ubuntu.com/25625484/
[2] ef8452f871afd8cb116fa96c8db2fe6260538319

Jagan Teki (5):
  armv7: Move L2CTLR read/write to common
  armv7: rk3288: Move configure_l2ctlr to common
  rk3288: vyasa: Add TPL support
  rk3288: vyasa: Add falcon mode support
  rk3288: spl: Add dram_init_banksize

 arch/arm/include/asm/arch-rockchip/sys_proto.h | 23 +++
 arch/arm/include/asm/armv7.h   | 21 +++
 arch/arm/mach-rockchip/Makefile|  1 +
 arch/arm/mach-rockchip/rk3288-board-spl.c  | 61 +++
 arch/arm/mach-rockchip/rk3288-board-tpl.c  | 84 ++
 arch/arm/mach-rockchip/rk3288/Kconfig  | 16 +
 arch/arm/mach-tegra/cache.c|  5 +-
 board/amarula/vyasa-rk3288/vyasa-rk3288.c  | 13 
 configs/vyasa-rk3288_defconfig |  3 +
 doc/README.rockchip| 18 ++
 include/configs/rk3288_common.h|  6 +-
 include/configs/vyasa-rk3288.h | 17 ++
 12 files changed, 225 insertions(+), 43 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c

-- 
2.7.4

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[U-Boot] [PATCH v3 2/2] wandboard: Add support for the MX6QP variant

[Fabio Estevam]

Add support for the latest MX6QP wandboard variant.

Based on Richard Hu's work from Technexion's U-Boot tree.

Signed-off-by: Fabio Estevam 
---
Changes since v2:
- Also turn on ldb_di0 clock. Able to boot the kernel now.

 arch/arm/include/asm/arch-mx6/imx-regs.h |   3 +
 board/wandboard/spl.c| 135 ++-
 board/wandboard/wandboard.c  |   6 +-
 include/configs/wandboard.h  |   2 +
 4 files changed, 142 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 86e2670..624ccec 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -346,6 +346,9 @@
 #define IOMUXC_SNVS_BASE_ADDR   (AIPS3_ARB_BASE_ADDR + 0x9)
 #define SNVS_GPR_BASE_ADDR  (AIPS3_ARB_BASE_ADDR + 0x94000)
 #endif
+
+#define NOC_DDR_BASE_ADDR   (GPV0_BASE_ADDR + 0xB)
+
 /* Only for i.MX6SX */
 #define LCDIF2_BASE_ADDR(AIPS3_ARB_BASE_ADDR + 0x24000)
 #define MX6SX_LCDIF1_BASE_ADDR  (AIPS3_ARB_BASE_ADDR + 0x2)
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 00c75d0..2446699 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX6DQ_DRIVE_STRENGTH  0x30
 #define IMX6SDL_DRIVE_STRENGTH 0x28
+#define IMX6QP_DRIVE_STRENGTH  0x28
 
 /* configure MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
@@ -260,15 +261,145 @@ static void ccgr_init(void)
writel(0x00C03F3F, >CCGR0);
writel(0x0030FC03, >CCGR1);
writel(0x0FFFC000, >CCGR2);
-   writel(0x3FF0, >CCGR3);
+   writel(0x3FF03000, >CCGR3);
writel(0x00FFF300, >CCGR4);
writel(0x0FC3, >CCGR5);
writel(0x03FF, >CCGR6);
 }
 
+static void spl_dram_init_imx6qp_lpddr3(void)
+{
+   /* DDR IO TYPE */
+   writel(0x000C, IOMUXC_BASE_ADDR + 0x798);
+   writel(0x, IOMUXC_BASE_ADDR + 0x758);
+   /* Clock */
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x588);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x594);
+   /* Address */
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x56c);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x578);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x74c);
+   /* Control */
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x57c);
+   writel(0x, IOMUXC_BASE_ADDR + 0x58c);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x59c);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5a0);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x78c);
+   /* Data Strobe */
+   writel(0x0002, IOMUXC_BASE_ADDR + 0x750);
+
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5a8);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5b0);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x524);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x51c);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x518);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x50c);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5b8);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5c0);
+   /* Data */
+   writel(0x0002, IOMUXC_BASE_ADDR + 0x774);
+
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x784);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x788);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x794);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x79c);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x7a0);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x7a4);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x7a8);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x748);
+
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5ac);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5b4);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x528);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x520);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x514);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x510);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5bc);
+   writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5c4);
+
+   /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
+   writel(0x8000, MMDC_P0_BASE_ADDR + 0x01c);
+
+   /* Calibrations - ZQ */
+   writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
+   /* write leveling */
+   writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
+   writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
+   writel(0x0004, MMDC_P1_BASE_ADDR + 0x80c);
+   writel(0x, MMDC_P1_BASE_ADDR + 

Re: [U-Boot] imx6qp wandboard getting stuck in U-Boot

[Fabio Estevam]

On Wed, Sep 27, 2017 at 1:39 PM, Fabio Estevam  wrote:

> Then I am able to boot the kernel fine. Will try to find out what is
> the missing clock for the imx6qp case.

Ok, just sent a v3 that allows me to boot the kernel on a imx6qp wandboard.
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[U-Boot] [PATCH v3 1/2] wandboard: Add support for the latest revd1 revision

[Fabio Estevam]

Latest wandboard hardware revision is revd1, which brings the following
new features:

- PFUZE100 PMIC
- AR8035 Ethernet PHY
- Upgrade Wifi/BT chip to BCM4339/BCM43430.

The detection mechanism is to probe the PMIC and when it is
found, then the revision of the board is revd1.

As the detection is done via PMIC, we need to print the board version
at a later stage via CONFIG_DISPLAY_BOARDINFO_LATE and also need
to disable CONFIG_DISPLAY_BOARDINFO, which is done much earlier.

Make the necessary adjustments for the AR8035 PHY to work on revd1.

Based on Richard Hu's work from Technexion's U-Boot tree.

Signed-off-by: Fabio Estevam 
---
Changes since v2:
- Also turn on ldb_di0 clock. Able to boot the kernel now.

 board/wandboard/wandboard.c | 110 +---
 configs/wandboard_defconfig |   1 +
 include/configs/wandboard.h |  11 +
 3 files changed, 115 insertions(+), 7 deletions(-)

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index adfcf48..14dd378 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -30,6 +30,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,8 +53,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
 #define ETH_PHY_RESET  IMX_GPIO_NR(3, 29)
+#define ETH_PHY_AR8035_POWER   IMX_GPIO_NR(7, 13)
 #define REV_DETECTION  IMX_GPIO_NR(2, 28)
 
+static bool with_pmic;
+
 int dram_init(void)
 {
gd->ram_size = imx_ddr_size();
@@ -107,6 +112,11 @@ static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29| MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
+static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
+   /* AR8035 POWER */
+   IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const rev_detection_pad[] = {
IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
@@ -120,6 +130,14 @@ static void setup_iomux_enet(void)
 {
SETUP_IOMUX_PADS(enet_pads);
 
+   if (with_pmic) {
+   SETUP_IOMUX_PADS(enet_ar8035_power_pads);
+   /* enable AR8035 POWER */
+   gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
+   }
+   /* wait until 3.3V of PHY and clock become stable */
+   mdelay(10);
+
/* Reset AR8031 PHY */
gpio_direction_output(ETH_PHY_RESET, 0);
mdelay(10);
@@ -192,6 +210,7 @@ int board_mmc_init(bd_t *bis)
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
unsigned short val;
+   int mask;
 
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
@@ -199,7 +218,12 @@ static int ar8031_phy_fixup(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-   val &= 0xffe3;
+   if (with_pmic)
+   mask = 0xffe7;  /* AR8035 */
+   else
+   mask = 0xffe3;  /* AR8031 */
+
+   val &= mask;
val |= 0x18;
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 
@@ -257,6 +281,40 @@ struct i2c_pads_info mx6dl_i2c2_pad_info = {
}
 };
 
+struct i2c_pads_info mx6q_i2c3_pad_info = {
+   .scl = {
+   .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gp = IMX_GPIO_NR(1, 5)
+   },
+   .sda = {
+   .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gp = IMX_GPIO_NR(7, 11)
+   }
+};
+
+struct i2c_pads_info mx6dl_i2c3_pad_info = {
+   .scl = {
+   .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gp = IMX_GPIO_NR(1, 5)
+   },
+   .sda = {
+   .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gp = IMX_GPIO_NR(7, 11)
+   }
+};
+
 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
@@ -388,6 +446,31 @@ int board_early_init_f(void)
return 0;
 }
 
+#define PMIC_I2C_BUS   2
+
+int power_init_board(void)
+{
+   struct pmic *p;
+   u32 reg;
+
+   /* configure PFUZE100 PMIC */
+   

Re: [U-Boot] [PATCH 06/13] log: Add an implemention of logging

[Masahiro Yamada]

Hi Simon,


2017-09-27 4:10 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 20 September 2017 at 11:19, Masahiro Yamada
>  wrote:
>> Hi Simon,
>>
>>
>> 2017-09-20 22:49 GMT+09:00 Simon Glass :
>>> Hi Masahiro,
>>>
>>> On 19 September 2017 at 20:51, Masahiro Yamada
>>>  wrote:
 Hi Simon,


 2017-09-17 6:23 GMT+09:00 Simon Glass :

>
> +menu "Logging"
> +
> +config LOG
> +   bool "Enable logging support"
> +   help
> + This enables support for logging of status and debug messages. 
> These
> + can be displayed on the console, recorded in a memory buffer, or
> + discarded if not needed. Logging supports various categories and
> + levels of severity.
> +
> +config SPL_LOG
> +   bool "Enable logging support in SPL"
> +   help
> + This enables support for logging of status and debug messages. 
> These
> + can be displayed on the console, recorded in a memory buffer, or
> + discarded if not needed. Logging supports various categories and
> + levels of severity.


 Please note CONFIG_IS_ENABLED(LOG) is never enabled for TPL_BUILD.

 Since commit f1c6e1922eb57f4a212c09709801a1cc7920ffa9,
 CONFIG_IS_ENABLED(LOG) is expanded to CONFIG_TPL_LOG
 when building for TPL.

 Since that commit, if you add SPL_ prefixed option,
 you need to add a TPL_ one as well.

 I cannot believe why such a commit was accepted.
>>>
>>> Well either way is strange. it is strange that SPL is enabled for TPL
>>> when really they are separate.
>>>
>>> We could revert that commit. But how do you think all of this SPL/TPL
>>> control should actually work? What is intended?
>>>
>>> But I'm OK with not having logging in TPL until we need it.
>>
>> I will explain it in another mail.
>>
>>




> +config LOG_MAX_LEVEL
> +   int "Maximum log level to record"
> +   depends on LOG
> +   default 5
> +   help
> + This selects the maximum log level that will be recorded. Any 
> value
> + higher than this will be ignored. If possible log statements 
> below
> + this level will be discarded at build time. Levels:
> +
> +   0 - panic
> +   1 - critical
> +   2 - error
> +   3 - warning
> +   4 - note
> +   5 - info
> +   6 - detail
> +   7 - debug


 Please do not invent our own for U-Boot.
 Just use Linux log level.

 0 (KERN_EMERG)  system is unusable
 1 (KERN_ALERT)  action must be taken 
 immediately
 2 (KERN_CRIT)   critical conditions
 3 (KERN_ERR)error conditions
 4 (KERN_WARNING)warning conditions
 5 (KERN_NOTICE) normal but significant 
 condition
 6 (KERN_INFO)   informational
 7 (KERN_DEBUG)  debug-level messages
>>>
>>> Yes I looked hard at that. The first three seem hard to distinguish in
>>> U-Boot, but we can keep them I suppose. But most of my problem is with
>>> the last two. INFO is what I plan to use for normal printf() output.
>>> DEBUG is obviously for debugging and often involves vaste amounts of
>>> stuff (e.g. logging every access to an MMC peripheral). We need
>>> something in between. It could list the accesses to device at a high
>>> level (e.g API calls) but not every little register access.
>>>
>>> So I don't think the Linux levels are suitable at the high end. We
>>> could go up to 8 I suppose, instead of trying to save one at the
>>> bottom?
>>
>>
>> In fact, Linux has one more for debug.
>>  dev_vdbg() is widely used in Linux.
>>
>> If you like, we can add one more level:
>>
>>  8 (KERN_VDEBUG)   verbose debug messages
>>
>>
>> Perhaps, logging every access to an MMC peripheral
>> might belong to the vdbg level.
>
> I like the idea of having a log level for message contents (bytes) and
> another for I/O access. So I will add two more in v2.
>
>>
>>
>>
>> BTW, what do you mean "INFO is what I plan to use for normal printf() output"
>>
>> Is that mean printf() is equivalent to pr_info()?
>> If loglevel is 6 or smaller, will all print() be silent?
>> If so, probably we can not use command line interface.
>
> I mean that I want to (later) add a feature that logs normal printf()
> output. If the console is silent then it would still be logged. Maybe
> one day log functions will be used instead of printf(), but for now
> this provides a useful way to make 

Re: [U-Boot] imx6qp wandboard getting stuck in U-Boot

[Fabio Estevam]

On Wed, Sep 27, 2017 at 1:27 PM, Fabio Estevam  wrote:
> Hi,
>
> With the two attached U-Boot patches plus the dts one I get the
> following on imx6qp wandboard:
>
> U-Boot SPL 2017.09-37395-g28ca7c0-dirty (Sep 27 2017 - 11:04:41)
> Trying to boot from MMC1
>
>
> U-Boot 2017.09-37395-g28ca7c0-dirty (Sep 27 2017 - 11:04:41 -0300)
>
> CPU:   Freescale i.MX6QP rev1.0 at 792 MHz
> Reset cause: POR
> I2C:   ready
> DRAM:  2 GiB
> PMIC:  PFUZE100 ID=0x10
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
> No panel detected: default to HDMI
> Display: HDMI (1024x768)
> In:serial
> Out:   serial
> Err:   serial
> Board: Wandboard rev D1
> Net:   FEC [PRIME]
> Hit any key to stop autoboot:  0
> switch to partitions #0, OK
> mmc0 is current device
> Scanning mmc 0:1...
> Found U-Boot script /boot/boot.scr
> 336 bytes read in 69 ms (3.9 KiB/s)
> ## Executing script at 1200
> 38550 bytes read in 83 ms (453.1 KiB/s)
> 6378872 bytes read in 367 ms (16.6 MiB/s)
> ## Flattened Device Tree blob at 1800
>Booting using the fdt blob at 0x1800
>Using Device Tree in place at 1800, end 1800c695
> (Hangs here)

Looks like a clock issue. If I do this change:

--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -258,13 +258,13 @@ static void ccgr_init(void)
 {
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

-   writel(0x00C03F3F, >CCGR0);
-   writel(0x0030FC03, >CCGR1);
-   writel(0x0FFFC000, >CCGR2);
-   writel(0x3FF0, >CCGR3);
-   writel(0x00FFF300, >CCGR4);
-   writel(0x0FC3, >CCGR5);
-   writel(0x03FF, >CCGR6);
+   writel(0x, >CCGR0);
+   writel(0x, >CCGR1);
+   writel(0x, >CCGR2);
+   writel(0x, >CCGR3);
+   writel(0x, >CCGR4);
+   writel(0x, >CCGR5);
+   writel(0x, >CCGR6);
 }

Then I am able to boot the kernel fine. Will try to find out what is
the missing clock for the imx6qp case.
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Re: [U-Boot] [U-Boot, 5/5] dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled

[Tom Rini]

On Thu, Sep 07, 2017 at 06:13:21AM -0700, Bin Meng wrote:

> When EHCD and xHCD are enabled at the same time, USB storage device
> driver will fail to read/write from/to the storage device attached
> to the xHCI interface, due to its transfer blocks exceeds the xHCD
> driver limitation.
> 
> With driver model, we have an API to get the controller's maximum
> transfer size and we can use that to determine the storage driver's
> capability of read/write.
> 
> Note: the non-DM version driver is still broken with xHCD and the
> intent here is not to fix the non-DM one, since the xHCD itself is
> already broken in places like 3.0 hub support, etc.
> 
> Signed-off-by: Bin Meng 
> Tested-by: Stefan Roese 
[snip]
> @@ -953,6 +957,17 @@ static void usb_stor_set_max_xfer_blk(struct us_data *us)
>  #else
>   blk = 20;
>  #endif
> +#else
> + ret = usb_get_max_xfer_size(udev, (size_t *));
> + if (ret < 0) {
> + /* unimplemented, let's use default 20 */
> + blk = 20;
> + } else {
> + if (size > USHRT_MAX * 512)
> + blk = USHRT_MAX;
> + blk = size / 512;
> + }
> +#endif

So, Coverity saw this and found an issue (CID 167250), and I was going
to just fix it, but I'm not sure.  The problem is that we check size >
(USHRT_MAX * 512), and then assign blk.  Then, we always assign blk, so
the test above isn't used.  But my background recollection is that
there's a real issue that's being addressed here.  Can we really just
always say blk = size / 512 in this case, or did we want to be shifting
size not blk under the if?  Thanks!

-- 
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Re: [U-Boot] [PATCH] ARM: zynq: Add support for SYZYGY Hub board

[Tom McLeod]

Hi Michal,

Thanks for looking at the patch! I'll try to incorporate the changes and
get a new patch out soon.

As far as the device tree Makefile, do you want me to sort it any
particular way or should I just add our board to the end of it? I can see
now it appears as though it might be sorted in a release date order or
something to that effect. I had thought originally that the order wasn't
overly important.

-Tom
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[U-Boot] imx6qp wandboard getting stuck in U-Boot

[Fabio Estevam]

Hi,

With the two attached U-Boot patches plus the dts one I get the
following on imx6qp wandboard:

U-Boot SPL 2017.09-37395-g28ca7c0-dirty (Sep 27 2017 - 11:04:41)
Trying to boot from MMC1


U-Boot 2017.09-37395-g28ca7c0-dirty (Sep 27 2017 - 11:04:41 -0300)

CPU:   Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
No panel detected: default to HDMI
Display: HDMI (1024x768)
In:serial
Out:   serial
Err:   serial
Board: Wandboard rev D1
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot/boot.scr
336 bytes read in 69 ms (3.9 KiB/s)
## Executing script at 1200
38550 bytes read in 83 ms (453.1 KiB/s)
6378872 bytes read in 367 ms (16.6 MiB/s)
## Flattened Device Tree blob at 1800
   Booting using the fdt blob at 0x1800
   Using Device Tree in place at 1800, end 1800c695
(Hangs here)

A imx6q wandboard revd1 can boot well though.

Looks like an U-Boot issue. I have also tried booting a dtb + zImage
from the Technexion kernel with the same result.

I am using the very same DDR init from Technexion U-Boot, so not sure
why imx6qp wandboard is not lauching the kernel.

If you have any ideas, please met me know.

Thanks,

Fabio Estevam
From 07a03861d527fdff7adc38b6ab6612f7cc5ff828 Mon Sep 17 00:00:00 2001
From: Fabio Estevam 
Date: Wed, 20 Sep 2017 18:27:46 -0300
Subject: [PATCH v2 1/2] wandboard: Add support for the latest revd1 revision

Latest wandboard hardware revision is revd1, which brings the following
new features:

- PFUZE100 PMIC
- AR8035 Ethernet PHY
- Upgrade Wifi/BT chip to BCM4339/BCM43430.

The detection mechanism is to probe the PMIC and when it is
found, then the revision of the board is revd1.

As the detection is done via PMIC, we need to print the board version
at a later stage via CONFIG_DISPLAY_BOARDINFO_LATE and also need
to disable CONFIG_DISPLAY_BOARDINFO, which is done much earlier.

Make the necessary adjustments for the AR8035 PHY to work on revd1.

Based on Richard Hu's work from Technexion's U-Boot tree.

Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Fix typo in commit log (Wifi/BT)

 board/wandboard/wandboard.c | 110 +---
 configs/wandboard_defconfig |   1 +
 include/configs/wandboard.h |  11 +
 3 files changed, 115 insertions(+), 7 deletions(-)

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index adfcf48..14dd378 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -30,6 +30,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,8 +53,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)
 #define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)
 #define ETH_PHY_RESET		IMX_GPIO_NR(3, 29)
+#define ETH_PHY_AR8035_POWER	IMX_GPIO_NR(7, 13)
 #define REV_DETECTION		IMX_GPIO_NR(2, 28)
 
+static bool with_pmic;
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -107,6 +112,11 @@ static iomux_v3_cfg_t const enet_pads[] = {
 	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29| MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
+static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
+	/* AR8035 POWER */
+	IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const rev_detection_pad[] = {
 	IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
@@ -120,6 +130,14 @@ static void setup_iomux_enet(void)
 {
 	SETUP_IOMUX_PADS(enet_pads);
 
+	if (with_pmic) {
+		SETUP_IOMUX_PADS(enet_ar8035_power_pads);
+		/* enable AR8035 POWER */
+		gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
+	}
+	/* wait until 3.3V of PHY and clock become stable */
+	mdelay(10);
+
 	/* Reset AR8031 PHY */
 	gpio_direction_output(ETH_PHY_RESET, 0);
 	mdelay(10);
@@ -192,6 +210,7 @@ int board_mmc_init(bd_t *bis)
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
 	unsigned short val;
+	int mask;
 
 	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
@@ -199,7 +218,12 @@ static int ar8031_phy_fixup(struct phy_device *phydev)
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 
 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
+	if (with_pmic)
+		mask = 0xffe7;	/* AR8035 */
+	else
+		mask = 0xffe3;	/* AR8031 */
+
+	val &= mask;
 	val |= 0x18;
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 
@@ -257,6 +281,40 @@ struct i2c_pads_info mx6dl_i2c2_pad_info = {
 	}
 };
 
+struct i2c_pads_info mx6q_i2c3_pad_info = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = 

Re: [U-Boot] [PATCH 06/13] log: Add an implemention of logging

[Masahiro Yamada]

Hi Philipp,


2017-09-21 2:51 GMT+09:00 Dr. Philipp Tomsich
:
> Masahiro,
>
>> On 20 Sep 2017, at 19:34, Masahiro Yamada  
>> wrote:
>>
>> 2017-09-20 23:37 GMT+09:00 Dr. Philipp Tomsich
>> :
>>> Masahiro & Simon,
>>>
 On 20 Sep 2017, at 15:49, Simon Glass  wrote:

 Hi Masahiro,

 On 19 September 2017 at 20:51, Masahiro Yamada
  wrote:
> Hi Simon,
>
>
> 2017-09-17 6:23 GMT+09:00 Simon Glass :
>
>>
>> +menu "Logging"
>> +
>> +config LOG
>> +   bool "Enable logging support"
>> +   help
>> + This enables support for logging of status and debug messages. 
>> These
>> + can be displayed on the console, recorded in a memory buffer, 
>> or
>> + discarded if not needed. Logging supports various categories 
>> and
>> + levels of severity.
>> +
>> +config SPL_LOG
>> +   bool "Enable logging support in SPL"
>> +   help
>> + This enables support for logging of status and debug messages. 
>> These
>> + can be displayed on the console, recorded in a memory buffer, 
>> or
>> + discarded if not needed. Logging supports various categories 
>> and
>> + levels of severity.
>
>
> Please note CONFIG_IS_ENABLED(LOG) is never enabled for TPL_BUILD.
>
> Since commit f1c6e1922eb57f4a212c09709801a1cc7920ffa9,
> CONFIG_IS_ENABLED(LOG) is expanded to CONFIG_TPL_LOG
> when building for TPL.
>
> Since that commit, if you add SPL_ prefixed option,
> you need to add a TPL_ one as well.
>
> I cannot believe why such a commit was accepted.

 Well either way is strange. it is strange that SPL is enabled for TPL
 when really they are separate.

 We could revert that commit. But how do you think all of this SPL/TPL
 control should actually work? What is intended?

 But I'm OK with not having logging in TPL until we need it.
>>>
>>> If we don’t differentiate between TPL_ and SPL_, we’ll eventually run into
>>> size issues for TPL and the $(SPL_TPL_) mechanism will not match the
>>> CONFIG_IS_ENABLED() mechanism.
>>>
>>> I don’t think that anyone will miss this much in TPL and that this can be
>>> safely left off for TPL (if space was not at a premium in TPL, then why
>>> have a TPL at all…)
>>
>>
>> The motivation of TPL is
>> the image size is really limited
>> for the secondary boot loader in some cases.
>>
>>
>> Instead of:
>>  SPL -> TPL -> U-Boot full
>
> Note that this was retro-actively defined to be
> TPL -> SPL -> U-Boot full
> by Tom at some point and reiterated in
> https://lists.denx.de/pipermail/u-boot/2017-July/299266.html



Thanks.  I did not know that this flip had already happened.


In fact, I am probably the first man who suggested it.


Here is the history.


1. Scott Wood introduced TPL to support some freescale chip,
   which had only 4KB memory footprint for the second loader
   https://www.denx.de/wiki/pub/U-Boot/MiniSummitELCE2013/tpl-presentation.pdf

   At this point, the boot order was:  SPL -> TPL -> U-Boot
   And TPL means "Tertiary Program Loader".


2.  I imported Kbuild and Kconfig to U-Boot.


3.  During the migration of Kconfig, I noticed
switching the order of SPL / TPL has advantages.

The "Tiny Program Loader" was mentioned first in this mail:
https://lists.denx.de/pipermail/u-boot/2015-August/222900.html


4.  When Simon started to move CONFIG_TPL,
I suggested it once again
http://patchwork.ozlabs.org/patch/662396/



So, I'd like to make "TPL -> SPL" legitimate.


More ideally, I hope this is done outside of luxury frameworks.
No DM, no OF_CONTROL, then CONFIG_TPL_* are all gone.






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Masahiro Yamada
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Re: [U-Boot] [PATCH] mx6: toradex: Remove custom CONFIG_SPL_PAD_TO definition

[Stefan Agner]

On 25.09.2017 20:20, Fabio Estevam wrote:
> From: Fabio Estevam 
>
> CONFIG_SPL_PAD_TO is already defined inside "imx6_spl.h", so there
> is no need to redefine it in the board config files.

That looks good to me.
Reviewed-by: Stefan Agner 

--
Stefan

>
> Signed-off-by: Fabio Estevam 
> ---
>  include/configs/apalis_imx6.h  | 1 -
>  include/configs/colibri_imx6.h | 1 -
>  2 files changed, 2 deletions(-)
>
> diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
> index a15f19d..51bf61c 100644
> --- a/include/configs/apalis_imx6.h
> +++ b/include/configs/apalis_imx6.h
> @@ -23,7 +23,6 @@
>  
>  #ifdef CONFIG_SPL
>  #include "imx6_spl.h"
> -#define CONFIG_SPL_PAD_TO0x11000 /* 4k IVT/DCD, 64k SPL */
>  #endif
>  
>  #define CONFIG_CMDLINE_TAG
> diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
> index db71369..ac9a23d 100644
> --- a/include/configs/colibri_imx6.h
> +++ b/include/configs/colibri_imx6.h
> @@ -21,7 +21,6 @@
>  
>  #ifdef CONFIG_SPL
>  #include "imx6_spl.h"
> -#define CONFIG_SPL_PAD_TO0x11000 /* 4k IVT/DCD, 64k SPL */
>  #endif
>  
>  #define CONFIG_CMDLINE_TAG

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[U-Boot] [PATCH 3/4] usb: ehci-ci: Add a prototype for board_ehci_power()

[Diego Dorta]

When compiling with W=1 the following warning is observed:

board/freescale/mx6sabresd/mx6sabresd.c:601:5: warning: no previous prototype 
for ‘board_ehci_power’ [-Wmissing-prototypes] int board_ehci_power(int port, 
int on)

Remove this warning by adding the function prototype into usb/ehci-ci.h file.

Signed-off-by: Diego Dorta 
---
 include/usb/ehci-ci.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index cd3eb47..8c9f3cd 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -280,6 +280,7 @@ struct usb_ehci {
 int usb_phy_mode(int port);
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);
+int board_ehci_power(int port, int on);
 int board_usb_phy_mode(int port);
 
 #endif /* _EHCI_CI_H */
-- 
2.7.4

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Re: [U-Boot] [PATCH] mmc: uniphier-sd: Add vqmmc regulator support

[Masahiro Yamada]

2017-09-28 0:50 GMT+09:00 Marek Vasut :
> On 09/27/2017 05:19 PM, Masahiro Yamada wrote:
>> 2017-09-26 16:41 GMT+09:00 Jaehoon Chung :
>>> Hi Marek,
>>>
>>> On 09/26/2017 01:47 AM, Marek Vasut wrote:
 On 09/15/2017 09:10 PM, Marek Vasut wrote:
> Add initial support for setting the vqmmc regulator. Since we do not
> support 1V8 modes, set the regulator to 3V3 and enable it.
>
> Signed-off-by: Marek Vasut 
> Cc: Masahiro Yamada 
> Cc: Jaehoon Chung 

 Anything ?! I don't see this in the PR ...
>>>
>>> Sorry...I missed this patch..First, i have checked on patchwork.
>>> Will pick this patch into u-boot-mmc.
>>>
>>> Best Regards,
>>> Jaehoon Chung
>>>
>>
>>
>> UniPhier SoCs have different mechanism for 3.3/1.8 switching,
>> but it is not a problem for me because I do not have a plan
>> for enabling CONFIG_DM_REGULATOR.
>>
>> Acked-by: Masahiro Yamada 
>
> Cool, thanks!
>
> Is there a documentation for the uniphier mechanism somewhere ?
>

No document available.

Only crappy private documents.

They say SoC spec books are CONFIDENTIAL!!
Sigh.



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[U-Boot] [PATCH 2/4] mx6sabresd: Include header file

[Diego Dorta]

When compiling with W=1 the following warning is observed:

board/freescale/mx6sabresd/mx6sabresd.c:680:5: warning: no previous prototype 
for ‘board_spi_cs_gpio’ [-Wmissing-prototypes] int board_spi_cs_gpio(unsigned 
bus, unsigned cs)

Remove this warning by including .

Signed-off-by: Diego Dorta 
---
 board/freescale/mx6sabresd/mx6sabresd.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index 6c9524d..c494500 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-- 
2.7.4

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[U-Boot] [PATCH 4/4] mx6sabresd: Include header file

[Diego Dorta]

When compiling with W=1 the following warning is observed:

board/freescale/mx6sabresd/mx6sabresd.c:586:5: warning: no previous prototype 
for ‘board_ehci_hcd_init’ [-Wmissing-prototypes] int board_ehci_hcd_init(int 
port)

Remove this warning by including .

Signed-off-by: Diego Dorta 
---
 board/freescale/mx6sabresd/mx6sabresd.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index 0d31235..6c9524d 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -30,6 +30,7 @@
 #include 
 #include "../common/pfuze.h"
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-- 
2.7.4

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[U-Boot] [PATCH 1/4] mx6: soc: Include header file

[Diego Dorta]

When compiling with W=1 the following warning is observed:

arch/arm/mach-imx/mx6/soc.c:213:12: warning: no previous prototype for 
‘get_board_rev’ [-Wmissing-prototypes] u32 __weak get_board_rev(void)

Fix the build warning by including .

Signed-off-by: Diego Dorta 
---
 arch/arm/mach-imx/mx6/soc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index b724668..ad72c12 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-- 
2.7.4

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Re: [U-Boot] [GIT PULL] u-boot-sunxi/master

[Tom Rini]

On Wed, Sep 27, 2017 at 05:55:31PM +0200, Maxime Ripard wrote:
> Hi,
> 
> On Wed, Sep 27, 2017 at 03:45:20PM +, Tom Rini wrote:
> > On Wed, Sep 27, 2017 at 05:34:04PM +0200, Maxime Ripard wrote:
> > > On Wed, Sep 27, 2017 at 12:33:06PM +, Tom Rini wrote:
> > > > On Wed, Sep 27, 2017 at 12:31:16PM +0200, Maxime Ripard wrote:
> > > > > Hi Tom,
> > > > > 
> > > > > Here is a pull request for the sunxi related changes for the next
> > > > > U-Boot version.
> > > > > 
> > > > > The diffstat is a bit scary, but mostly because of the Kconfig
> > > > > migration of the USB ethernet related options, which were enabled by a
> > > > > big number of boards. The fastboot options simplification is also one
> > > > > of the offenders.
> > > > > 
> > > > > This is my first pull request ever, so I might have done something
> > > > > wrong, let me know if it's the case.
> > > > 
> > > > Sorry, this is pretty broken:
> > > > $ make O=/tmp/T sandbox_config
> > > > make[1]: Entering directory `/tmp/T'
> > > > GEN ./Makefile
> > > > drivers/usb/Kconfig:1:error: recursive dependency detected!
> > > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > > subsection "Kconfig recursive dependency limitations"
> > > > drivers/usb/Kconfig:1:  symbol USB is selected by ARCH_SUNXI
> > > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > > subsection "Kconfig recursive dependency limitations"
> > > > arch/arm/Kconfig:674:   symbol ARCH_SUNXI is part of choice 
> > > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > > subsection "Kconfig recursive dependency limitations"
> > > > arch/arm/Kconfig:291:   choice  contains symbol ARCH_SUNXI
> > > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > > subsection "Kconfig recursive dependency limitations"
> > > > arch/arm/Kconfig:674:   symbol ARCH_SUNXI depends on USB_MUSB_GADGET
> > > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > > subsection "Kconfig recursive dependency limitations"
> > > > drivers/usb/musb-new/Kconfig:11:symbol USB_MUSB_GADGET depends 
> > > > on USB
> > > 
> > > Gah. Sorry for that. So much for slipping in a fix without testing
> > > it...
> > > 
> > > I wonder why it's considered a recursive dependency though.
> > > 
> > > The situation seems to be:
> > > 
> > > selectsdepends
> > > ARCH_SUNXI > USB <- USB_MUSB_GADGET
> > > |
> > > +---> USB_ETHER
> > >  implies
> > > 
> > > USB_ETHER is implied only if USB_MUSB_GADGET is set, but that looks
> > > like a directed graph without any loop, right?
> > > 
> > > Or am I missing something?
> > 
> > implies is tricky, and I think it comes down to ARCH_SUNXI being under a
> > choice.  What I think we generally need to do here is use 'default y if
> > ...' under things like USB_MUSB_GADGET instead of imply X if Y, under
> > the ARCH_xxx choice and similar.
> 
> Yeah, I tested a similar option in parallel, and putting a default y
> if ARCH_SUNXI && USB_MUSB_GADGET under USB_ETHER work fine.
> 
> Would that work for you? I'll respin the pull request with this change
> if so.

That's fine, thanks!

> > An alternative that may, or may not, make sense would be mirroring
> > TI_COMMON_CMD_OPTIONS from board/ti/common/Kconfig, where the intent
> > there is that that TI-the-vendor wants a consistent experience on
> > their various EVMs so that gets set to enable X/Y/Z, but a custom
> > board based on a TI SoC might not want to enable all of that since
> > it's not an EVM that wants the kitchen sink, so to speak.
> 
> Yeah, we were also starting to think about it (mostly for tablets vs
> dev boards uses), but the discussion didn't really settle yet.

OK.

-- 
Tom


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Re: [U-Boot] [GIT PULL] u-boot-sunxi/master

[Maxime Ripard]

Hi,

On Wed, Sep 27, 2017 at 03:45:20PM +, Tom Rini wrote:
> On Wed, Sep 27, 2017 at 05:34:04PM +0200, Maxime Ripard wrote:
> > On Wed, Sep 27, 2017 at 12:33:06PM +, Tom Rini wrote:
> > > On Wed, Sep 27, 2017 at 12:31:16PM +0200, Maxime Ripard wrote:
> > > > Hi Tom,
> > > > 
> > > > Here is a pull request for the sunxi related changes for the next
> > > > U-Boot version.
> > > > 
> > > > The diffstat is a bit scary, but mostly because of the Kconfig
> > > > migration of the USB ethernet related options, which were enabled by a
> > > > big number of boards. The fastboot options simplification is also one
> > > > of the offenders.
> > > > 
> > > > This is my first pull request ever, so I might have done something
> > > > wrong, let me know if it's the case.
> > > 
> > > Sorry, this is pretty broken:
> > > $ make O=/tmp/T sandbox_config
> > > make[1]: Entering directory `/tmp/T'
> > > GEN ./Makefile
> > > drivers/usb/Kconfig:1:error: recursive dependency detected!
> > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > subsection "Kconfig recursive dependency limitations"
> > > drivers/usb/Kconfig:1:  symbol USB is selected by ARCH_SUNXI
> > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > subsection "Kconfig recursive dependency limitations"
> > > arch/arm/Kconfig:674:   symbol ARCH_SUNXI is part of choice 
> > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > subsection "Kconfig recursive dependency limitations"
> > > arch/arm/Kconfig:291:   choice  contains symbol ARCH_SUNXI
> > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > subsection "Kconfig recursive dependency limitations"
> > > arch/arm/Kconfig:674:   symbol ARCH_SUNXI depends on USB_MUSB_GADGET
> > > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > > subsection "Kconfig recursive dependency limitations"
> > > drivers/usb/musb-new/Kconfig:11:symbol USB_MUSB_GADGET depends on 
> > > USB
> > 
> > Gah. Sorry for that. So much for slipping in a fix without testing
> > it...
> > 
> > I wonder why it's considered a recursive dependency though.
> > 
> > The situation seems to be:
> > 
> > selectsdepends
> > ARCH_SUNXI > USB <- USB_MUSB_GADGET
> > |
> > +---> USB_ETHER
> >  implies
> > 
> > USB_ETHER is implied only if USB_MUSB_GADGET is set, but that looks
> > like a directed graph without any loop, right?
> > 
> > Or am I missing something?
> 
> implies is tricky, and I think it comes down to ARCH_SUNXI being under a
> choice.  What I think we generally need to do here is use 'default y if
> ...' under things like USB_MUSB_GADGET instead of imply X if Y, under
> the ARCH_xxx choice and similar.

Yeah, I tested a similar option in parallel, and putting a default y
if ARCH_SUNXI && USB_MUSB_GADGET under USB_ETHER work fine.

Would that work for you? I'll respin the pull request with this change
if so.

> An alternative that may, or may not, make sense would be mirroring
> TI_COMMON_CMD_OPTIONS from board/ti/common/Kconfig, where the intent
> there is that that TI-the-vendor wants a consistent experience on
> their various EVMs so that gets set to enable X/Y/Z, but a custom
> board based on a TI SoC might not want to enable all of that since
> it's not an EVM that wants the kitchen sink, so to speak.

Yeah, we were also starting to think about it (mostly for tablets vs
dev boards uses), but the discussion didn't really settle yet.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [U-Boot] [PATCH 6/9] net: sun8i_emac: Support RX/TX delay chains

[Joe Hershberger]

On Fri, Sep 22, 2017 at 2:26 AM, Chen-Yu Tsai  wrote:
> The EMAC syscon has configurable RX/TX delay chains for use with RGMII
> PHYs.
>
> This adds support for configuring them via device tree properties. The
> property names and format were defined in Linux's dwmac-sun8i binding
> that was merged at one point.
>
> Signed-off-by: Chen-Yu Tsai 
> ---
>  drivers/net/sun8i_emac.c | 25 +
>  1 file changed, 25 insertions(+)
>
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index 09bbb2cdb5ca..5fa1b4c170d7 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -56,6 +56,10 @@
>  #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
>
>  #define SC_RMII_EN BIT(13)
> +#define SC_TXDC_SHIFT  10
> +#define SC_TXDC_MASK   GENMASK(2, 0)
> +#define SC_RXDC_SHIFT  5
> +#define SC_RXDC_MASK   GENMASK(4, 0)
>  #define SC_EPITBIT(2) /* 1: RGMII, 0: MII */
>  #define SC_ETCS_MASK   GENMASK(1, 0)
>  #define SC_ETCS_EXT_GMII   0x1
> @@ -125,6 +129,8 @@ struct emac_eth_dev {
> u32 addr;
> u32 tx_slot;
> bool use_internal_phy;
> +   u32 tx_delay;
> +   u32 rx_delay;
>
> enum emac_variant variant;
> void *mac_reg;
> @@ -290,6 +296,12 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev 
> *priv)
> if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
> reg &= ~SC_RMII_EN;
>
> +   /* Configure RX/TX delay chains */
> +   reg &= ~(SC_RXDC_MASK << SC_RXDC_SHIFT);
> +   reg &= ~(SC_TXDC_MASK << SC_TXDC_SHIFT);
> +   reg |= (priv->rx_delay & SC_RXDC_MASK) << SC_RXDC_SHIFT;
> +   reg |= (priv->tx_delay & SC_TXDC_MASK) << SC_TXDC_SHIFT;

Why not use bitfield_replace_by_mask() from include/bitfield.h?

> +
> switch (priv->interface) {
> case PHY_INTERFACE_MODE_MII:
> /* default */
> @@ -836,6 +848,19 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct 
> udevice *dev)
> }
>  #endif
>
> +   /* Get RX/TX delays for RGMII */
> +   priv->rx_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
> +"allwinner,rx-delay-ps", 0);
> +   if (priv->rx_delay % 100 || priv->rx_delay > 3100)
> +   debug("%s: invalid rx delay value\n", __func__);
> +   priv->rx_delay /= 100;
> +
> +   priv->tx_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
> +"allwinner,tx-delay-ps", 0);
> +   if (priv->tx_delay % 100 || priv->tx_delay > 800)
> +   debug("%s: invalid tx delay value\n", __func__);
> +   priv->tx_delay /= 100;
> +
> return 0;
>  }
>
> --
> 2.14.1
>
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Re: [U-Boot] [PATCH 7/9] net: sun8i_emac: Fix build for non-H3/H5 SoCs

[Joe Hershberger]

On Fri, Sep 22, 2017 at 2:26 AM, Chen-Yu Tsai  wrote:
> Only the H3/H5 SoCs have an internal PHY and its related clock and
> reset controls.
>
> Use an #ifdef to guard the internal PHY control code block so it
> can be built for other SoCs, such as the A83T or A64.
>
> Signed-off-by: Chen-Yu Tsai 

Reviewed-by: Joe Hershberger 
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Re: [U-Boot] [GIT PULL] u-boot-sunxi/master

[Tom Rini]

On Wed, Sep 27, 2017 at 05:34:04PM +0200, Maxime Ripard wrote:
> On Wed, Sep 27, 2017 at 12:33:06PM +, Tom Rini wrote:
> > On Wed, Sep 27, 2017 at 12:31:16PM +0200, Maxime Ripard wrote:
> > > Hi Tom,
> > > 
> > > Here is a pull request for the sunxi related changes for the next
> > > U-Boot version.
> > > 
> > > The diffstat is a bit scary, but mostly because of the Kconfig
> > > migration of the USB ethernet related options, which were enabled by a
> > > big number of boards. The fastboot options simplification is also one
> > > of the offenders.
> > > 
> > > This is my first pull request ever, so I might have done something
> > > wrong, let me know if it's the case.
> > 
> > Sorry, this is pretty broken:
> > $ make O=/tmp/T sandbox_config
> > make[1]: Entering directory `/tmp/T'
> > GEN ./Makefile
> > drivers/usb/Kconfig:1:error: recursive dependency detected!
> > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > subsection "Kconfig recursive dependency limitations"
> > drivers/usb/Kconfig:1:  symbol USB is selected by ARCH_SUNXI
> > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > subsection "Kconfig recursive dependency limitations"
> > arch/arm/Kconfig:674:   symbol ARCH_SUNXI is part of choice 
> > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > subsection "Kconfig recursive dependency limitations"
> > arch/arm/Kconfig:291:   choice  contains symbol ARCH_SUNXI
> > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > subsection "Kconfig recursive dependency limitations"
> > arch/arm/Kconfig:674:   symbol ARCH_SUNXI depends on USB_MUSB_GADGET
> > For a resolution refer to Documentation/kbuild/kconfig-language.txt
> > subsection "Kconfig recursive dependency limitations"
> > drivers/usb/musb-new/Kconfig:11:symbol USB_MUSB_GADGET depends on 
> > USB
> 
> Gah. Sorry for that. So much for slipping in a fix without testing
> it...
> 
> I wonder why it's considered a recursive dependency though.
> 
> The situation seems to be:
> 
> selectsdepends
> ARCH_SUNXI > USB <- USB_MUSB_GADGET
> |
> +---> USB_ETHER
>  implies
> 
> USB_ETHER is implied only if USB_MUSB_GADGET is set, but that looks
> like a directed graph without any loop, right?
> 
> Or am I missing something?

implies is tricky, and I think it comes down to ARCH_SUNXI being under a
choice.  What I think we generally need to do here is use 'default y if
...' under things like USB_MUSB_GADGET instead of imply X if Y, under
the ARCH_xxx choice and similar.  An alternative that may, or may not,
make sense would be mirroring TI_COMMON_CMD_OPTIONS from
board/ti/common/Kconfig, where the intent there is that that
TI-the-vendor wants a consistent experience on their various EVMs so
that gets set to enable X/Y/Z, but a custom board based on a TI SoC
might not want to enable all of that since it's not an EVM that wants
the kitchen sink, so to speak.

-- 
Tom


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Re: [U-Boot] [PATCH 4/6] net: gmac_rockchip: Define the gmac grf register struct at gmac_rockchip.c

[Joe Hershberger]

On Thu, Sep 21, 2017 at 9:17 AM, David Wu  wrote:
> If we include both the rk3288_grf.h and rv1108_grf.h, there is a
> number of compiling error for redefinition. So we define the reg
> structs of mac_grf at gmac_rockchip.c. Remove the rk**_grf.h files,
> give them own grf offset for their use.
>
> Signed-off-by: David Wu 
> ---
>
>  drivers/net/gmac_rockchip.c | 144 
> +++-
>  1 file changed, 116 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
> index 586ccbf..5f8f0cd 100644
> --- a/drivers/net/gmac_rockchip.c
> +++ b/drivers/net/gmac_rockchip.c
> @@ -15,9 +15,6 @@
>  #include 
>  #include 
>  #include 
> -#include 
> -#include 
> -#include 

You should also delete these header files as part of the patch.

>  #include 
>  #include 
>  #include "designware.h"
> @@ -31,15 +28,37 @@ DECLARE_GLOBAL_DATA_PTR;
>   */
>  struct gmac_rockchip_platdata {
> struct dw_eth_pdata dw_eth_pdata;
> +   void *grf;
> int tx_delay;
> int rx_delay;
>  };
>
>  struct rk_gmac_ops {
> -   int (*fix_mac_speed)(struct dw_eth_dev *priv);
> +   int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata,
> +struct dw_eth_dev *priv);
> void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
>  };
>
> +struct gmac_rockchip_driver_data {
> +   const struct rk_gmac_ops *ops;
> +   unsigned int grf_offset;
> +};
> +
> +struct rk3288_mac_grf {
> +   u32 soc_con1;
> +   u32 reserved;
> +   u32 soc_con3;
> +};
> +
> +struct rk3368_mac_grf {
> +   u32 soc_con15;
> +   u32 soc_con16;
> +};
> +
> +struct rk3399_mac_grf {
> +   u32 soc_con5;
> +   u32 soc_con6;
> +};
>
>  static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
>  {
> @@ -58,10 +77,18 @@ static int gmac_rockchip_ofdata_to_platdata(struct 
> udevice *dev)
> return designware_eth_ofdata_to_platdata(dev);
>  }
>
> -static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
> +static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
> +struct dw_eth_dev *priv)
>  {
> -   struct rk3288_grf *grf;
> +   struct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;
> int clk;
> +   enum {
> +   RK3288_GMAC_CLK_SEL_SHIFT = 12,
> +   RK3288_GMAC_CLK_SEL_MASK  = GENMASK(13, 12),
> +   RK3288_GMAC_CLK_SEL_125M  = 0 << 12,
> +   RK3288_GMAC_CLK_SEL_25M   = 3 << 12,
> +   RK3288_GMAC_CLK_SEL_2_5M  = 2 << 12,
> +   };
>
> switch (priv->phydev->speed) {
> case 10:
> @@ -78,15 +105,15 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev 
> *priv)
> return -EINVAL;
> }
>
> -   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> rk_clrsetreg(>soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
>
> return 0;
>  }
>
> -static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
> +static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
> +struct dw_eth_dev *priv)
>  {
> -   struct rk3368_grf *grf;
> +   struct rk3368_mac_grf *grf = (struct rk3368_mac_grf *)pdata->grf;
> int clk;
> enum {
> RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
> @@ -110,16 +137,22 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev 
> *priv)
> return -EINVAL;
> }
>
> -   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> rk_clrsetreg(>soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
>
> return 0;
>  }
>
> -static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
> +static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
> +struct dw_eth_dev *priv)
>  {
> -   struct rk3399_grf_regs *grf;
> +   struct rk3399_mac_grf *grf = (struct rk3399_mac_grf *)pdata->grf;
> int clk;
> +   enum {
> +   RK3399_GMAC_CLK_SEL_MASK  = GENMASK(6, 4),
> +   RK3399_GMAC_CLK_SEL_125M  = 0 << 4,
> +   RK3399_GMAC_CLK_SEL_25M   = 3 << 4,
> +   RK3399_GMAC_CLK_SEL_2_5M  = 2 << 4,
> +   };
>
> switch (priv->phydev->speed) {
> case 10:
> @@ -136,7 +169,6 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev 
> *priv)
> return -EINVAL;
> }
>
> -   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> rk_clrsetreg(>soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
>
> return 0;
> @@ -144,9 +176,31 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev 
> *priv)
>
>  static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
>  {
> -   struct rk3288_grf *grf;
> +   struct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;
> +   enum {
> 

Re: [U-Boot] [PATCH] mmc: uniphier-sd: Add vqmmc regulator support

[Masahiro Yamada]

2017-09-26 16:41 GMT+09:00 Jaehoon Chung :
> Hi Marek,
>
> On 09/26/2017 01:47 AM, Marek Vasut wrote:
>> On 09/15/2017 09:10 PM, Marek Vasut wrote:
>>> Add initial support for setting the vqmmc regulator. Since we do not
>>> support 1V8 modes, set the regulator to 3V3 and enable it.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Masahiro Yamada 
>>> Cc: Jaehoon Chung 
>>
>> Anything ?! I don't see this in the PR ...
>
> Sorry...I missed this patch..First, i have checked on patchwork.
> Will pick this patch into u-boot-mmc.
>
> Best Regards,
> Jaehoon Chung
>


UniPhier SoCs have different mechanism for 3.3/1.8 switching,
but it is not a problem for me because I do not have a plan
for enabling CONFIG_DM_REGULATOR.

Acked-by: Masahiro Yamada 




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Masahiro Yamada
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Re: [U-Boot] [PATCH] mmc: uniphier-sd: Update the file to match V3 patchset

[Masahiro Yamada]

2017-09-27 3:05 GMT+09:00 Marek Vasut :
> Old version of the uniphier-sd 64bit IO support patchset V1 was
> applied by the maintainer, update the uniphier-sd.c with the
> changes from the V3 of the patchset.
>
> Signed-off-by: Marek Vasut 
> Cc: Masahiro Yamada 
> Cc: Jaehoon Chung 
> ---


Acked-by: Masahiro Yamada 



-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH 0/5] REVERT Follow the Linux Kernel in building dtc as needed

[Wolfgang Denk]

Dear Tom,

In message <20170927143112.GT3112@bill-the-cat> you wrote:
> 
> Well, NAK.  When you passed the "benevolent dictator" hat over, you
> passed it over.  I value your input, and I don't lightly over-rule
> feedback.  So, lets summarize things:

These are all technical arguments. You could have raised these in the
ongoing discussion.  If they are good, convincing arguments, you
should have no problems to have them accepted.

What I'm complainiung about is not WHAT was commited, but HOW it was
committed.

Marek wrote:

| I believe we have a well-established process of submitting patches,
| getting a review and then applying them. If the head maintainer doesn't
| follow the process, why should anyone else ?

You have a role model function. Please stick to the rules!


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
At the source of every error which is blamed on the computer you will
find at least two human errors, including the error of blaming it  on
the computer.
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[U-Boot] ClearFog base USB keyboard

[Влад Мао]

I have a ClearfogBase board with armada A388 processor (6828), and
trying to setup USB keyboard in U-boot.

SOM have 3 USB controllers, described in armada-38x.dtsi:
usb@58000 {
compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>;
interrupts = ;
clocks = < 18>;
status = "disabled";
};
usb3@f {
compatible = "marvell,armada-380-xhci";
reg = <0xf 0x4000>,<0xf4000 0x4000>;
interrupts = ;
clocks = < 9>;
status = "disabled";
};

usb3@f8000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
interrupts = ;
clocks = < 10>;
status = "disabled";
};

in armada-388-clearfog.dts:
usb@58000 {
status = "okay";
};
usb3@f {
status = "okay";
};
usb3@f8000 {
status = "okay";
};

In U-Boot menuconfig i enabled:

CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MARVELL=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y

When i load the U-boot, and type usb start, i see only USB Hub on
usb@58000, which have no connector on board.

I tried find out what's wrong and why my keyboard does not work, load
linux and find out - USB connector on board (U2) works with usb3@f8000
(i commented out status = "disabled" usb@58000 and usb3@f, and in
linux keyboard still works), dmesg from linux system:

[3.163750] usbcore: registered new interface driver asix
[3.169178] usbcore: registered new interface driver ax88179_178a
[3.175314] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[3.181871] ehci-pci: EHCI PCI platform driver
[3.186343] ehci-orion: EHCI orion driver
[3.190584] xhci-hcd f10f8000.usb3: xHCI Host Controller
[3.195924] xhci-hcd f10f8000.usb3: new USB bus registered,
assigned bus number 1
[3.203492] xhci-hcd f10f8000.usb3: hcc params 0x0a000990 hci
version 0x100 quirks 0x00010010
[3.212063] xhci-hcd f10f8000.usb3: irq 48, io mem 0xf10f8000
[3.218169] hub 1-0:1.0: USB hub found
[3.221991] hub 1-0:1.0: 1 port detected
[3.226072] xhci-hcd f10f8000.usb3: xHCI Host Controller
[3.231399] xhci-hcd f10f8000.usb3: new USB bus registered,
assigned bus number 2
[3.238978] usb usb2: We don't know the algorithms for LPM for this
host, disabling LPM.
[3.247420] hub 2-0:1.0: USB hub found
[3.251190] hub 2-0:1.0: 1 port detected
[3.255350] usbcore: registered new interface driver usb-storage

In linux with this settings keyboard work perfectry, but in U-boot i see:
=> usb start
starting USB...
scan end
No controllers found

How to fix it and get the keyboard working in U-boot?
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Re: [U-Boot] [PATCH 0/5] REVERT Follow the Linux Kernel in building dtc as needed

[Tom Rini]

On Wed, Sep 27, 2017 at 04:15:19PM +0200, Wolfgang Denk wrote:

> This patch series reverts some patches that should never have been
> merged into mainline at all:
> 
> - They were applied in violation of the well established rule that
>   ALL patches must be posted on the mailing list before, and given
>   enough time for review by the community.
> - Obviously, these patches have not been Acked-by: by anybody.
> - They implement a solution that probably does not represent the
>   majority of the developers who discussed this issue. They were
>   applied cutting short the ongoing discussion, without giving a
>   good, comprehensible reason.  Alternative solutions were
>   presented before, but this patch series ignores them.
> 
> U-Boot is a community project with an established and documented
> development process.  No single person, not even a custodian or
> maintainer, shall have the power to push through any changes without
> or against the consent of the community.  If we want to maintain
> these standards, we cannot accept this.  We therefore have only one
> choice: revert these patches now, and let them undergo the necessary
> review process on the mailing list, allowing for the usual grace
> period of two weeks.  Sorry.

Well, NAK.  When you passed the "benevolent dictator" hat over, you
passed it over.  I value your input, and I don't lightly over-rule
feedback.  So, lets summarize things:
- We need a modern device tree compiler.
- Everyone needs a modern device tree compiler, because everyone should
  be running 'make tests'.
- This is not the first, or second, or possibly even third time we've
  hit problems of people using different versions of dtc and seeing
  different results / problems.
- The Linux Kernel has avoided this problem for forever by just bundling
  the minimum required parts of dtc in order to build things.

So, I've imported the infrastructure to keep things in sync, and
imported upstream dtc.

Now, the best argument I've heard against this is "bundling is bad".  I
don't disagree, and the best way to fix this problem would be for
distributions to start shipping a new enough version here that the
kernel can drop it out, just like they did for linux-firmware recently.
A whole lot more people care about the kernel than they do about U-Boot,
and that's a more viable path forward.  It would even make some kernel
folks happy.

-- 
Tom


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[U-Boot] [PATCH 1/5] Revert "tools/mkimage: Make the path to the dtc binary that mkimage calls configurable"

[Wolfgang Denk]

This reverts commit 1f6049e2501b5c35c61435dbc05ba96743202674.

This patch is part of a series which has never been reviewed and
has not been generally accepted by the community.

Signed-off-by: Wolfgang Denk 

Cc: Albert Aribaud 
Cc: Alexander Graf 
Cc: Alexey Brodkin 
Cc: Anatolij Gustschin 
Cc: Andre Przywara ,
Cc: Andreas Bießmann 
Cc: Angelo Dureghello 
Cc: Bin Meng 
Cc: Daniel Hellstrom 
Cc: Daniel Schwierzeck 
Cc: Heiko Schocher 
Cc: Heinrich Schuchardt 
Cc: Huan Wang 
Cc: Jagan Teki 
Cc: Joe Hershberger 
Cc: Kim Phillips 
Cc: Kyungmin Park 
Cc: Lukasz Majewski 
Cc: Macpaul Lin 
Cc: Marek Vasut 
Cc: Marek Vasut 
Cc: Masahiro Yamada 
Cc: Michal Simek 
Cc: Minkyu Kang 
Cc: Nobuhiro Iwamatsu 
Cc: Pantelis Antoniou 
Cc: Prafulla Wadaskar 
Cc: Przemyslaw Marczak 
Cc: Robert Nelson 
Cc: Scott Wood  
Cc: Simon Glass 
Cc: Sonic Zhang 
Cc: Stanislav Galabov 
Cc: Stefan Roese 
Cc: Stefano Babic 
Cc: Stephen Warren 
Cc: Thomas Chou 
Cc: Tom Rini 
Cc: Tom Warren 
Cc: u-boot@lists.denx.de
Cc: Vagrant Cascadian 
Cc: Vipin Kumar 
Cc: York Sun 
---
 dts/Kconfig| 9 -
 tools/Makefile | 2 +-
 2 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/dts/Kconfig b/dts/Kconfig
index 4ee0510943..44fc9fe36d 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -170,12 +170,3 @@ config TPL_OF_PLATDATA
  information.
 
 endmenu
-
-config MKIMAGE_DTC_PATH
-   string "Path to dtc binary for use within mkimage"
-   default "dtc"
-   help
- The mkimage host tool will, in order to generate FIT images make
- calls to the dtc application in order to create the output.  In
- some cases the system dtc may not support all required features
- and the path to a different version should be given here.
diff --git a/tools/Makefile b/tools/Makefile
index c16477459d..a0db19d6b0 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -175,7 +175,7 @@ HOSTCFLAGS_rsa-sign.o += -Wno-deprecated-declarations
 endif
 endif
 
-HOSTCFLAGS_fit_image.o += -DMKIMAGE_DTC=\"$(CONFIG_MKIMAGE_DTC_PATH)\"
+HOSTCFLAGS_fit_image.o += -DMKIMAGE_DTC=\"$(DTC)\"
 
 HOSTLOADLIBES_dumpimage := $(HOSTLOADLIBES_mkimage)
 HOSTLOADLIBES_fit_info := $(HOSTLOADLIBES_mkimage)
-- 
2.13.3

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[U-Boot] [PATCH 3/5] Revert "scripts/dtc: Update to upstream version v1.4.4-50-gfe50bd1ecc1d"

[Wolfgang Denk]

This reverts commit 2d4c2259930b91fe5e7a2f92db32c03fe640ed60.

This patch is part of a series which has never been reviewed and
has not been generally accepted by the community.

Signed-off-by: Wolfgang Denk 

Cc: Albert Aribaud 
Cc: Alexander Graf 
Cc: Alexey Brodkin 
Cc: Anatolij Gustschin 
Cc: Andre Przywara ,
Cc: Andreas Bießmann 
Cc: Angelo Dureghello 
Cc: Bin Meng 
Cc: Daniel Hellstrom 
Cc: Daniel Schwierzeck 
Cc: Heiko Schocher 
Cc: Heinrich Schuchardt 
Cc: Huan Wang 
Cc: Jagan Teki 
Cc: Joe Hershberger 
Cc: Kim Phillips 
Cc: Kyungmin Park 
Cc: Lukasz Majewski 
Cc: Macpaul Lin 
Cc: Marek Vasut 
Cc: Marek Vasut 
Cc: Masahiro Yamada 
Cc: Michal Simek 
Cc: Minkyu Kang 
Cc: Nobuhiro Iwamatsu 
Cc: Pantelis Antoniou 
Cc: Prafulla Wadaskar 
Cc: Przemyslaw Marczak 
Cc: Robert Nelson 
Cc: Scott Wood  
Cc: Simon Glass 
Cc: Sonic Zhang 
Cc: Stanislav Galabov 
Cc: Stefan Roese 
Cc: Stefano Babic 
Cc: Stephen Warren 
Cc: Thomas Chou 
Cc: Tom Rini 
Cc: Tom Warren 
Cc: u-boot@lists.denx.de
Cc: Vagrant Cascadian 
Cc: Vipin Kumar 
Cc: York Sun 
---
 scripts/dtc/checks.c| 231 
 scripts/dtc/dtc.c   |   2 +-
 scripts/dtc/dtc.h   |   6 -
 scripts/dtc/libfdt/fdt_empty_tree.c |   1 +
 scripts/dtc/libfdt/fdt_ro.c |   4 +-
 scripts/dtc/libfdt/fdt_rw.c |  24 +---
 scripts/dtc/libfdt/fdt_sw.c |  16 +--
 scripts/dtc/libfdt/fdt_wip.c|   4 +-
 scripts/dtc/libfdt/libfdt.h |  68 +--
 scripts/dtc/livetree.c  |   3 +-
 scripts/dtc/version_gen.h   |   2 +-
 11 files changed, 16 insertions(+), 345 deletions(-)

diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c
index afabf64337..38f548e582 100644
--- a/scripts/dtc/checks.c
+++ b/scripts/dtc/checks.c
@@ -681,229 +681,6 @@ static void check_ranges_format(struct check *c, struct 
dt_info *dti,
 }
 WARNING(ranges_format, check_ranges_format, NULL, _size_cells);
 
-static const struct bus_type pci_bus = {
-   .name = "PCI",
-};
-
-static void check_pci_bridge(struct check *c, struct dt_info *dti, struct node 
*node)
-{
-   struct property *prop;
-   cell_t *cells;
-
-   prop = get_property(node, "device_type");
-   if (!prop || !streq(prop->val.val, "pci"))
-   return;
-
-   node->bus = _bus;
-
-   if (!strneq(node->name, "pci", node->basenamelen) &&
-   !strneq(node->name, "pcie", node->basenamelen))
-   FAIL(c, dti, "Node %s node name is not \"pci\" or \"pcie\"",
-node->fullpath);
-
-   prop = get_property(node, "ranges");
-   if (!prop)
-   FAIL(c, dti, "Node %s missing ranges for PCI bridge (or not a 
bridge)",
-node->fullpath);
-
-   if (node_addr_cells(node) != 3)
-   FAIL(c, dti, "Node %s incorrect #address-cells for PCI bridge",
-node->fullpath);
-   if (node_size_cells(node) != 2)
-   FAIL(c, dti, "Node %s incorrect #size-cells for PCI bridge",
-node->fullpath);
-
-   prop = get_property(node, "bus-range");
-   if (!prop) {
-   FAIL(c, dti, "Node %s missing bus-range for PCI bridge",
-node->fullpath);
-   return;
-   }
-   if (prop->val.len != (sizeof(cell_t) * 2)) {
-   FAIL(c, dti, "Node %s bus-range must be 2 cells",
-node->fullpath);
-   return;
-   }
-   cells = (cell_t *)prop->val.val;
-   if (fdt32_to_cpu(cells[0]) > fdt32_to_cpu(cells[1]))
-   FAIL(c, dti, "Node %s bus-range 1st cell must be less than or 
equal to 2nd cell",
-node->fullpath);
-   if (fdt32_to_cpu(cells[1]) > 0xff)
-   FAIL(c, dti, "Node %s bus-range maximum bus number must be less 
than 256",
-node->fullpath);
-}
-WARNING(pci_bridge, check_pci_bridge, NULL,
-   _type_is_string, _size_cells);
-

[U-Boot] [PATCH 0/5] REVERT Follow the Linux Kernel in building dtc as needed

[Wolfgang Denk]

This patch series reverts some patches that should never have been
merged into mainline at all:

- They were applied in violation of the well established rule that
  ALL patches must be posted on the mailing list before, and given
  enough time for review by the community.
- Obviously, these patches have not been Acked-by: by anybody.
- They implement a solution that probably does not represent the
  majority of the developers who discussed this issue. They were
  applied cutting short the ongoing discussion, without giving a
  good, comprehensible reason.  Alternative solutions were
  presented before, but this patch series ignores them.

U-Boot is a community project with an established and documented
development process.  No single person, not even a custodian or
maintainer, shall have the power to push through any changes without
or against the consent of the community.  If we want to maintain
these standards, we cannot accept this.  We therefore have only one
choice: revert these patches now, and let them undergo the necessary
review process on the mailing list, allowing for the usual grace
period of two weeks.  Sorry.

Signed-off-by: Wolfgang Denk 

Wolfgang Denk (5):
  Revert "tools/mkimage: Make the path to the dtc binary that mkimage
calls configurable"
  Revert "dtc: Switch to building and using our own dtc unless provided"
  Revert "scripts/dtc: Update to upstream version
v1.4.4-50-gfe50bd1ecc1d"
  Revert "scripts/dtc: Update to upstream version v1.4.4"
  Revert "scripts/dtc: Update to upstream version v1.4.3"

Cc: Albert Aribaud 
Cc: Alexander Graf 
Cc: Alexey Brodkin 
Cc: Anatolij Gustschin 
Cc: Andre Przywara ,
Cc: Andreas Bießmann 
Cc: Angelo Dureghello 
Cc: Bin Meng 
Cc: Daniel Hellstrom 
Cc: Daniel Schwierzeck 
Cc: Heiko Schocher 
Cc: Heinrich Schuchardt 
Cc: Huan Wang 
Cc: Jagan Teki 
Cc: Joe Hershberger 
Cc: Kim Phillips 
Cc: Kyungmin Park 
Cc: Lukasz Majewski 
Cc: Macpaul Lin 
Cc: Marek Vasut 
Cc: Marek Vasut 
Cc: Masahiro Yamada 
Cc: Michal Simek 
Cc: Minkyu Kang 
Cc: Nobuhiro Iwamatsu 
Cc: Pantelis Antoniou 
Cc: Prafulla Wadaskar 
Cc: Przemyslaw Marczak 
Cc: Robert Nelson 
Cc: Scott Wood  
Cc: Simon Glass 
Cc: Sonic Zhang 
Cc: Stanislav Galabov 
Cc: Stefan Roese 
Cc: Stefano Babic 
Cc: Stephen Warren 
Cc: Thomas Chou 
Cc: Tom Rini 
Cc: Tom Warren 
Cc: u-boot@lists.denx.de
Cc: Vagrant Cascadian 
Cc: Vipin Kumar 
Cc: York Sun 

 .travis.yml  |6 +-
 Makefile |   10 +-
 dts/Kconfig  |   13 -
 scripts/Kbuild.include   |5 +
 scripts/Makefile |1 -
 scripts/Makefile.extrawarn   |   16 +-
 scripts/dtc/Makefile |   31 -
 scripts/dtc/Makefile.dtc |   18 -
 scripts/dtc/checks.c | 1076 
 scripts/dtc/data.c   |  269 
 scripts/dtc/dtc-lexer.l  |  306 -
 scripts/dtc/dtc-lexer.lex.c_shipped  | 2255 -
 scripts/dtc/dtc-parser.tab.c_shipped | 2301 --
 scripts/dtc/dtc-parser.tab.h_shipped |  123 --
 scripts/dtc/dtc-parser.y |  519 
 scripts/dtc/dtc.c|  365 --
 scripts/dtc/dtc.h|  290 -
 scripts/dtc/flattree.c   |  940 --
 scripts/dtc/fstree.c |   90 --
 scripts/dtc/libfdt/Makefile.libfdt   |   11 -
 scripts/dtc/libfdt/fdt.c |  251 
 scripts/dtc/libfdt/fdt.h |  111 --
 scripts/dtc/libfdt/fdt_empty_tree.c  |   83 --
 scripts/dtc/libfdt/fdt_ro.c  |  703 ---
 scripts/dtc/libfdt/fdt_rw.c  |  505 
 scripts/dtc/libfdt/fdt_strerror.c|  102 --
 scripts/dtc/libfdt/fdt_sw.c  |  300 -
 scripts/dtc/libfdt/fdt_wip.c |  139 --
 scripts/dtc/libfdt/libfdt.h  | 1899 
 scripts/dtc/libfdt/libfdt_env.h  |  112 --
 scripts/dtc/libfdt/libfdt_internal.h |   95 --
 scripts/dtc/livetree.c   

[U-Boot] [PATCH 4/5] Revert "scripts/dtc: Update to upstream version v1.4.4"

[Wolfgang Denk]

This reverts commit d6fc90ced42e9fb77185cedfe45d0a2c7ac78508.

This patch is part of a series which has never been reviewed and
has not been generally accepted by the community.

Signed-off-by: Wolfgang Denk 

Cc: Albert Aribaud 
Cc: Alexander Graf 
Cc: Alexey Brodkin 
Cc: Anatolij Gustschin 
Cc: Andre Przywara ,
Cc: Andreas Bießmann 
Cc: Angelo Dureghello 
Cc: Bin Meng 
Cc: Daniel Hellstrom 
Cc: Daniel Schwierzeck 
Cc: Heiko Schocher 
Cc: Heinrich Schuchardt 
Cc: Huan Wang 
Cc: Jagan Teki 
Cc: Joe Hershberger 
Cc: Kim Phillips 
Cc: Kyungmin Park 
Cc: Lukasz Majewski 
Cc: Macpaul Lin 
Cc: Marek Vasut 
Cc: Marek Vasut 
Cc: Masahiro Yamada 
Cc: Michal Simek 
Cc: Minkyu Kang 
Cc: Nobuhiro Iwamatsu 
Cc: Pantelis Antoniou 
Cc: Prafulla Wadaskar 
Cc: Przemyslaw Marczak 
Cc: Robert Nelson 
Cc: Scott Wood  
Cc: Simon Glass 
Cc: Sonic Zhang 
Cc: Stanislav Galabov 
Cc: Stefan Roese 
Cc: Stefano Babic 
Cc: Stephen Warren 
Cc: Thomas Chou 
Cc: Tom Rini 
Cc: Tom Warren 
Cc: u-boot@lists.denx.de
Cc: Vagrant Cascadian 
Cc: Vipin Kumar 
Cc: York Sun 
---
 scripts/dtc/checks.c| 12 --
 scripts/dtc/data.c  | 16 
 scripts/dtc/dtc-lexer.l |  7 +++-
 scripts/dtc/dtc-lexer.lex.c_shipped | 81 -
 scripts/dtc/dtc.c   |  5 ++-
 scripts/dtc/dtc.h   |  5 ++-
 scripts/dtc/flattree.c  | 58 ++
 scripts/dtc/libfdt/libfdt_env.h | 26 ++--
 scripts/dtc/livetree.c  | 16 
 scripts/dtc/srcpos.h| 11 ++---
 scripts/dtc/treesource.c|  6 +--
 scripts/dtc/util.c  | 11 +++--
 scripts/dtc/util.h  | 30 +++---
 scripts/dtc/version_gen.h   |  2 +-
 14 files changed, 155 insertions(+), 131 deletions(-)

diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c
index 38f548e582..0e8b978c36 100644
--- a/scripts/dtc/checks.c
+++ b/scripts/dtc/checks.c
@@ -72,8 +72,12 @@ struct check {
 #define CHECK(_nm, _fn, _d, ...) \
CHECK_ENTRY(_nm, _fn, _d, false, false, __VA_ARGS__)
 
-static inline void  PRINTF(3, 4) check_msg(struct check *c, struct dt_info 
*dti,
-  const char *fmt, ...)
+#ifdef __GNUC__
+static inline void check_msg(struct check *c, struct dt_info *dti,
+const char *fmt, ...) __attribute__((format 
(printf, 3, 4)));
+#endif
+static inline void check_msg(struct check *c, struct dt_info *dti,
+const char *fmt, ...)
 {
va_list ap;
va_start(ap, fmt);
@@ -534,13 +538,13 @@ static void fixup_phandle_references(struct check *c, 
struct dt_info *dti,
FAIL(c, dti, "Reference to non-existent 
node or "
"label \"%s\"\n", 
m->ref);
else /* mark the entry as unresolved */
-   *((fdt32_t *)(prop->val.val + 
m->offset)) =
+   *((cell_t *)(prop->val.val + 
m->offset)) =
cpu_to_fdt32(0x);
continue;
}
 
phandle = get_node_phandle(dt, refnode);
-   *((fdt32_t *)(prop->val.val + m->offset)) = 
cpu_to_fdt32(phandle);
+   *((cell_t *)(prop->val.val + m->offset)) = 
cpu_to_fdt32(phandle);
}
}
 }
diff --git a/scripts/dtc/data.c b/scripts/dtc/data.c
index aa37a16c88..8cae237468 100644
--- a/scripts/dtc/data.c
+++ b/scripts/dtc/data.c
@@ -171,9 +171,9 @@ struct data data_merge(struct data d1, struct data d2)
 struct data data_append_integer(struct data d, uint64_t value, int bits)
 {
uint8_t value_8;
-   fdt16_t value_16;
-   fdt32_t value_32;
-   fdt64_t value_64;
+   uint16_t value_16;
+   uint32_t value_32;
+   uint64_t value_64;
 
switch 

[U-Boot] [PATCH 2/5] Revert "dtc: Switch to building and using our own dtc unless provided"

[Wolfgang Denk]

This reverts commit 36dd5f1b8abcd0aa5f8490b3ef1e4e7ecce2eb8c.

This patch is part of a series which has never been reviewed and
has not been generally accepted by the community.

Signed-off-by: Wolfgang Denk 

Cc: Albert Aribaud 
Cc: Alexander Graf 
Cc: Alexey Brodkin 
Cc: Anatolij Gustschin 
Cc: Andre Przywara ,
Cc: Andreas Bießmann 
Cc: Angelo Dureghello 
Cc: Bin Meng 
Cc: Daniel Hellstrom 
Cc: Daniel Schwierzeck 
Cc: Heiko Schocher 
Cc: Heinrich Schuchardt 
Cc: Huan Wang 
Cc: Jagan Teki 
Cc: Joe Hershberger 
Cc: Kim Phillips 
Cc: Kyungmin Park 
Cc: Lukasz Majewski 
Cc: Macpaul Lin 
Cc: Marek Vasut 
Cc: Marek Vasut 
Cc: Masahiro Yamada 
Cc: Michal Simek 
Cc: Minkyu Kang 
Cc: Nobuhiro Iwamatsu 
Cc: Pantelis Antoniou 
Cc: Prafulla Wadaskar 
Cc: Przemyslaw Marczak 
Cc: Robert Nelson 
Cc: Scott Wood  
Cc: Simon Glass 
Cc: Sonic Zhang 
Cc: Stanislav Galabov 
Cc: Stefan Roese 
Cc: Stefano Babic 
Cc: Stephen Warren 
Cc: Thomas Chou 
Cc: Tom Rini 
Cc: Tom Warren 
Cc: u-boot@lists.denx.de
Cc: Vagrant Cascadian 
Cc: Vipin Kumar 
Cc: York Sun 
---
 .travis.yml  |  6 --
 Makefile | 10 --
 dts/Kconfig  |  4 
 scripts/Makefile |  1 -
 4 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 00b2a73a5e..9dfd016da0 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -26,9 +26,11 @@ addons:
 - grub-efi-ia32-bin
 - rpm2cpio
 - wget
-- device-tree-compiler
 
 install:
+ # install latest device tree compiler
+ - git clone --depth=1 -b v1.4.3 
git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ - make -j4 -C /tmp/dtc
  # Clone uboot-test-hooks
  - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git 
/tmp/uboot-test-hooks
  - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
@@ -49,7 +51,7 @@ install:
 
 env:
   global:
-- PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin
+- 
PATH=/tmp/dtc:/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin
 - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
 - BUILD_DIR=build
 - HOSTCC="cc"
diff --git a/Makefile b/Makefile
index b7d5cbb3f9..e058e9854b 100644
--- a/Makefile
+++ b/Makefile
@@ -349,7 +349,7 @@ OBJDUMP = $(CROSS_COMPILE)objdump
 AWK= awk
 PERL   = perl
 PYTHON ?= python
-DTC?= $(objtree)/scripts/dtc/dtc
+DTC?= dtc
 CHECK  = sparse
 
 CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -872,7 +872,7 @@ endif
 PHONY += dtbs
 dtbs: dts/dt.dtb
@:
-dts/dt.dtb: u-boot
+dts/dt.dtb: checkdtc u-boot
$(Q)$(MAKE) $(build)=dts dtbs
 
 quiet_cmd_copy = COPY$@
@@ -1447,6 +1447,12 @@ SYSTEM_MAP = \
 System.map:u-boot
@$(call SYSTEM_MAP,$<) > $@
 
+checkdtc:
+   @if test $(call dtc-version) -lt 010403; then \
+   echo '*** Your dtc is too old, please upgrade to dtc 1.4.3 or 
newer'; \
+   false; \
+   fi
+
 #
 
 # ARM relocations should all be R_ARM_RELATIVE (32-bit) or
diff --git a/dts/Kconfig b/dts/Kconfig
index 44fc9fe36d..b4b7ddc144 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -5,15 +5,11 @@
 config SUPPORT_OF_CONTROL
bool
 
-config DTC
-   bool
-
 menu "Device Tree Control"
depends on SUPPORT_OF_CONTROL
 
 config OF_CONTROL
bool "Run-time configuration via Device Tree"
-   select DTC
help
  This feature provides for run-time configuration of U-Boot
  via a flattened device tree.
diff --git a/scripts/Makefile b/scripts/Makefile
index 9d55241463..3e10c16d59 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -21,4 +21,3 @@ build_docproc: $(obj)/docproc
 
 # Let clean descend into subdirs
 subdir-+= basic kconfig
-subdir-$(CONFIG_DTC)   += dtc
-- 
2.13.3

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[U-Boot] [PATCH 1/1] sunxi: Fix A20-OLinuXino-MICRO dts for LAN8710

[Stefan Mavrodiev]

From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
index 7e3006f..0bc5ea9 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
@@ -95,7 +95,7 @@
 
  {
pinctrl-names = "default";
-   pinctrl-0 = <_pins_mii_a>;
+   pinctrl-0 = <_pins_mii_a>,<_txerr>;
phy = <>;
phy-mode = "mii";
status = "okay";
@@ -226,6 +226,13 @@
 };
 
  {
+   gmac_txerr: gmac_txerr@0 {
+   allwinner,pins = "PA17";
+   allwinner,function = "gpio_out";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
allwinner,pins = "PH11";
allwinner,function = "gpio_in";
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/1] sunxi: Fix A20-OLinuXino-MICRO dts for LAN8710

[Stefan Mavrodiev]

On 09/27/2017 04:19 PM, Maxime Ripard wrote:

Hi Stefan,

You should also put Jagan Teki as recipients.

On Wed, Sep 27, 2017 at 07:19:10AM +, Stefan Mavrodiev wrote:

 From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.

Signed-off-by: Stefan Mavrodiev 
---
  arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 9 -
  1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
index 7e3006f..0bc5ea9 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
@@ -95,7 +95,7 @@
  
   {

pinctrl-names = "default";
-   pinctrl-0 = <_pins_mii_a>;
+   pinctrl-0 = <_pins_mii_a>,<_txerr>;
phy = <>;
phy-mode = "mii";
status = "okay";
@@ -226,6 +226,13 @@
  };
  
   {

+   gmac_txerr: gmac_txerr@0 {
+   allwinner,pins = "PA17";
+   allwinner,function = "gpio_out";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+

There's two issues with that patch:
   - In general we try to sync the DT with Linux when we can, and the
 patch that ended up in Linux wasn't this one.

I'm little confused. If I sync the DT with the one from mainline linux,
doesn't this counts as dangerous? I mean it will be the only one that is 
synced.

This could corrupt building if sun7i-a20.dtsi is not synced for example.

   - And we don't have any pinctrl support in U-Boot, that patch will
 basically do nothing

The code that changes the muxing is here:
http://git.denx.de/?p=u-boot.git;a=blob;f=board/sunxi/gmac.c#l34

Again, since this is common for all boards, doesn't it counts as dangerous?
This is feature only on our board.


Maxime



Best regards,
Stefan Mavrodiev



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[U-Boot] BUG: Environment is in SPI flash does not even compile (at least for Orange PI PC2

[kope]

Hi,

I'm trying to compile u-boot with Environment in SPI flash  
(CONFIG_ENV_IS_IN_SPI_FLASH?) for Orange PI PC2.


Compilation ends with an error:
  CC  env/sf.o
env/sf.c: In function ‘env_sf_save’:
env/sf.c:266:6: error: ‘CONFIG_ENV_SECT_SIZE’ undeclared (first use in  
this function); did you mean ‘CONFIG_ENV_SIZE’?



After defining CONFIG_ENV_SECT_SIZE in include/configs/sunxi-common.h  
linking fails with error:

  LD  u-boot
env/built-in.o: In function `setup_flash_device':
/root/uboot/u-boot/env/sf.c:71: undefined reference to `spi_flash_probe'
env/built-in.o: In function `env_sf_load':
/root/uboot/u-boot/env/sf.c:342: undefined reference to `spi_flash_free'

Is there a way to have the environment in the SPI?

Thanks. Regards,

Peter Kosa

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[U-Boot] [PATCH v1 2/6] serial: stm32x7: remove stm32f7-usart and stm32h7-usart compatible

[patrice.chotard]

From: Patrice Chotard 

This patch remove the extra compatibility string "st,stm32h7-usart"
and "st,stm32f7-usart" to avoid confusion, save some time & space.

Signed-off-by: Patrice Chotard 
Reviewed-by: Vikas Manocha 
---
 arch/arm/dts/stm32h743.dtsi | 4 ++--
 drivers/serial/serial_stm32x7.c | 2 --
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index 16e9308..a413866 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -76,7 +76,7 @@
};
 
usart1: serial@40011000 {
-   compatible = "st,stm32h7-usart", "st,stm32h7-uart";
+   compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
@@ -84,7 +84,7 @@
};
 
usart2: serial@40004400 {
-   compatible = "st,stm32h7-usart", "st,stm32h7-uart";
+   compatible = "st,stm32h7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
status = "disabled";
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 2f4eafa..bafcc36 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -110,9 +110,7 @@ static int stm32_serial_probe(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id stm32_serial_id[] = {
-   {.compatible = "st,stm32f7-usart"},
{.compatible = "st,stm32f7-uart"},
-   {.compatible = "st,stm32h7-usart"},
{.compatible = "st,stm32h7-uart"},
{}
 };
-- 
1.9.1

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[U-Boot] [PATCH v1 0/6] Update stm32x7 serial driver

[patrice.chotard]

From: Patrice Chotard 

This series update the serial_stm32x7 driver used by both STM32F7 and STM32H7 
SoCs :
_ clean the code by using BIT and GENMASK macro
_ remove useless CLK and OF_CONTROL flags
_ add fifo support for H7
_ introduce STM32F4 support

Currently, STM32F4 uses a dedicated serial driver drivers/serial/serial_stm32.c.
whereas STM32F7 and STM32H7 uses drivers/serial/serial/serial_stm32x7.c .
There is no reason to have 2 separate serial driver for STM32 SoCs family.

It's the first step to prepare STM32F4 conversion to driver model and 
device tree support. Hence this conversion will be done, serial_stm32x7.c 
driver will support alls SoCs (ie F4/F7 and H7) it will be then renamed with 
the generic name serial_stm32.c

Patrice Chotard (6):
  serial: stm32x7: cleanup code
  serial: stm32x7: remove stm32f7-usart and stm32h7-usart compatible
  serial: stm32x7: prepare the ground to STM32F4 support
  serial: stm32x7: add fifo support for STM32H7
  serial: stm32x7: add STM32F4 support
  serial: stm32x7: remove useless CONFIG_CLK and OF_CONTROL flag

 arch/arm/dts/stm32h743.dtsi |  4 +-
 drivers/serial/Kconfig  |  4 +-
 drivers/serial/serial_stm32x7.c | 84 ++---
 drivers/serial/serial_stm32x7.h | 71 +++---
 4 files changed, 99 insertions(+), 64 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH v1 5/6] serial: stm32x7: add STM32F4 support

[patrice.chotard]

From: Patrice Chotard 

stm32f4 doesn't support FIFO and OVERRUN feature.
The enable bit is not at the same location in CR1
register than for STM32F7 and STM32H7.

Signed-off-by: Patrice Chotard 
---
 drivers/serial/Kconfig  | 4 ++--
 drivers/serial/serial_stm32x7.c | 1 +
 drivers/serial/serial_stm32x7.h | 7 +++
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 9bf2e26..7c54a49 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -531,9 +531,9 @@ config STI_ASC_SERIAL
 
 config STM32X7_SERIAL
bool "STMicroelectronics STM32 SoCs on-chip UART"
-   depends on DM_SERIAL && (STM32F7 || STM32H7)
+   depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
help
- If you have a machine based on a STM32 F7 or H7 SoC you can
+ If you have a machine based on a STM32 F4, F7 or H7 SoC you can
  enable its onboard serial ports, say Y to this option.
  If unsure, say N.
 
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 19697e3..44e8b42 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -127,6 +127,7 @@ static int stm32_serial_probe(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id stm32_serial_id[] = {
+   { .compatible = "st,stm32-uart", .data = (ulong)_info},
{ .compatible = "st,stm32f7-uart", .data = (ulong)_info},
{ .compatible = "st,stm32h7-uart", .data = (ulong)_info},
{}
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
index ed8a3ee..b914edf 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32x7.h
@@ -27,6 +27,13 @@ struct stm32_uart_info {
bool has_fifo;
 };
 
+struct stm32_uart_info stm32f4_info = {
+   .stm32f4 = true,
+   .uart_enable_bit = 13,
+   .has_overrun_disable = false,
+   .has_fifo = false,
+};
+
 struct stm32_uart_info stm32f7_info = {
.uart_enable_bit = 0,
.stm32f4 = false,
-- 
1.9.1

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[U-Boot] [PATCH v1 6/6] serial: stm32x7: remove useless CONFIG_CLK and OF_CONTROL flag

[patrice.chotard]

From: Patrice Chotard 

This driver is currently used by STM32F7 and STM32H7 SoCs.
As CONFIG_CLK and OF_CONTROL flags are set by default for these
2 SoCs, this flag becomes useless in this driver, so remove it.

Signed-off-by: Patrice Chotard 
---
 drivers/serial/serial_stm32x7.c | 9 ++---
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 44e8b42..a5d529c 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -83,7 +83,9 @@ static int stm32_serial_pending(struct udevice *dev, bool 
input)
 static int stm32_serial_probe(struct udevice *dev)
 {
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+   struct clk clk;
fdt_addr_t base = plat->base;
+   int ret;
bool stm32f4;
u8 uart_enable_bit;
 
@@ -91,10 +93,6 @@ static int stm32_serial_probe(struct udevice *dev)
stm32f4 = plat->uart_info->stm32f4;
uart_enable_bit = plat->uart_info->uart_enable_bit;
 
-#ifdef CONFIG_CLK
-   int ret;
-   struct clk clk;
-
ret = clk_get_by_index(dev, 0, );
if (ret < 0)
return ret;
@@ -104,7 +102,6 @@ static int stm32_serial_probe(struct udevice *dev)
dev_err(dev, "failed to enable clock\n");
return ret;
}
-#endif
 
plat->clock_rate = clk_get_rate();
if (plat->clock_rate < 0) {
@@ -125,7 +122,6 @@ static int stm32_serial_probe(struct udevice *dev)
return 0;
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id stm32_serial_id[] = {
{ .compatible = "st,stm32-uart", .data = (ulong)_info},
{ .compatible = "st,stm32f7-uart", .data = (ulong)_info},
@@ -143,7 +139,6 @@ static int stm32_serial_ofdata_to_platdata(struct udevice 
*dev)
 
return 0;
 }
-#endif
 
 static const struct dm_serial_ops stm32_serial_ops = {
.putc = stm32_serial_putc,
-- 
1.9.1

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[U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to STM32F4 support

[patrice.chotard]

From: Patrice Chotard 

STM32F4 serial IP is similar to F7 and H7, but registers
are not located at the same offset and some feature are
only supported by F7 and H7 version.

Registers offset must be added for each version and also
some flags indicated the supported feature.

Update registers name to match with datasheet (sr to isr,
rx_dr to rdr and tx_dr to tdr) and remove unused regs
(cr2, gtpr, rtor, and rqr).

Signed-off-by: Patrice Chotard 
---
 drivers/serial/serial_stm32x7.c | 72 -
 drivers/serial/serial_stm32x7.h | 38 ++
 2 files changed, 66 insertions(+), 44 deletions(-)

diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index bafcc36..81a2308 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -17,67 +17,79 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
 {
-   struct stm32x7_serial_platdata *plat = dev->platdata;
-   struct stm32_usart *const usart = plat->base;
+   struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+   bool stm32f4 = plat->uart_info->stm32f4;
+   fdt_addr_t base = plat->base;
u32 int_div, mantissa, fraction, oversampling;
 
int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
 
if (int_div < 16) {
oversampling = 8;
-   setbits_le32(>cr1, USART_CR1_OVER8);
+   setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
} else {
oversampling = 16;
-   clrbits_le32(>cr1, USART_CR1_OVER8);
+   clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
}
 
mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
fraction = int_div % oversampling;
 
-   writel(mantissa | fraction, >brr);
+   writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
 
return 0;
 }
 
 static int stm32_serial_getc(struct udevice *dev)
 {
-   struct stm32x7_serial_platdata *plat = dev->platdata;
-   struct stm32_usart *const usart = plat->base;
+   struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+   bool stm32f4 = plat->uart_info->stm32f4;
+   fdt_addr_t base = plat->base;
 
-   if ((readl(>sr) & USART_SR_FLAG_RXNE) == 0)
+   if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
return -EAGAIN;
 
-   return readl(>rd_dr);
+   return readl(base + RDR_OFFSET(stm32f4));
 }
 
 static int stm32_serial_putc(struct udevice *dev, const char c)
 {
-   struct stm32x7_serial_platdata *plat = dev->platdata;
-   struct stm32_usart *const usart = plat->base;
+   struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+   bool stm32f4 = plat->uart_info->stm32f4;
+   fdt_addr_t base = plat->base;
 
-   if ((readl(>sr) & USART_SR_FLAG_TXE) == 0)
+   if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
return -EAGAIN;
 
-   writel(c, >tx_dr);
+   writel(c, base + TDR_OFFSET(stm32f4));
 
return 0;
 }
 
 static int stm32_serial_pending(struct udevice *dev, bool input)
 {
-   struct stm32x7_serial_platdata *plat = dev->platdata;
-   struct stm32_usart *const usart = plat->base;
+   struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+   bool stm32f4 = plat->uart_info->stm32f4;
+   fdt_addr_t base = plat->base;
 
if (input)
-   return readl(>sr) & USART_SR_FLAG_RXNE ? 1 : 0;
+   return readl(base + ISR_OFFSET(stm32f4)) &
+   USART_SR_FLAG_RXNE ? 1 : 0;
else
-   return readl(>sr) & USART_SR_FLAG_TXE ? 0 : 1;
+   return readl(base + ISR_OFFSET(stm32f4)) &
+   USART_SR_FLAG_TXE ? 0 : 1;
 }
 
 static int stm32_serial_probe(struct udevice *dev)
 {
-   struct stm32x7_serial_platdata *plat = dev->platdata;
-   struct stm32_usart *const usart = plat->base;
+   struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+   fdt_addr_t base = plat->base;
+   bool stm32f4;
+   u8 uart_enable_bit;
+
+   plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
+   stm32f4 = plat->uart_info->stm32f4;
+   uart_enable_bit = plat->uart_info->uart_enable_bit;
 
 #ifdef CONFIG_CLK
int ret;
@@ -100,32 +112,32 @@ static int stm32_serial_probe(struct udevice *dev)
return plat->clock_rate;
};
 
-   /* Disable usart-> disable overrun-> enable usart */
-   clrbits_le32(>cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
-   setbits_le32(>cr3, USART_CR3_OVRDIS);
-   setbits_le32(>cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
+   /* Disable uart-> disable overrun-> enable uart */
+   clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ 

[U-Boot] [PATCH v1 4/6] serial: stm32x7: add fifo support for STM32H7

[patrice.chotard]

From: Patrice Chotard 

Add fifo mode support for rx and tx.
As only STM32H7 supports this feature, add has_fifo flag
to uart configuration to use fifo only when possible.

Signed-off-by: Patrice Chotard 
---
 drivers/serial/serial_stm32x7.c |  6 --
 drivers/serial/serial_stm32x7.h | 12 +++-
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 81a2308..19697e3 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -117,6 +117,8 @@ static int stm32_serial_probe(struct udevice *dev)
 BIT(uart_enable_bit));
if (plat->uart_info->has_overrun_disable)
setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
+   if (plat->uart_info->has_fifo)
+   setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
 BIT(uart_enable_bit));
 
@@ -125,8 +127,8 @@ static int stm32_serial_probe(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id stm32_serial_id[] = {
-   { .compatible = "st,stm32f7-uart", .data = (ulong)_info},
-   { .compatible = "st,stm32h7-uart", .data = (ulong)_info},
+   { .compatible = "st,stm32f7-uart", .data = (ulong)_info},
+   { .compatible = "st,stm32h7-uart", .data = (ulong)_info},
{}
 };
 
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
index 4c6b7d4..ed8a3ee 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32x7.h
@@ -24,12 +24,21 @@ struct stm32_uart_info {
u8 uart_enable_bit; /* UART_CR1_UE */
bool stm32f4;   /* true for STM32F4, false otherwise */
bool has_overrun_disable;
+   bool has_fifo;
 };
 
-struct stm32_uart_info stm32x7_info = {
+struct stm32_uart_info stm32f7_info = {
.uart_enable_bit = 0,
.stm32f4 = false,
.has_overrun_disable = true,
+   .has_fifo = false,
+};
+
+struct stm32_uart_info stm32h7_info = {
+   .uart_enable_bit = 0,
+   .stm32f4 = false,
+   .has_overrun_disable = true,
+   .has_fifo = true,
 };
 
 /* Information about a serial port */
@@ -39,6 +48,7 @@ struct stm32x7_serial_platdata {
unsigned long int clock_rate;
 };
 
+#define USART_CR1_FIFOEN   BIT(29)
 #define USART_CR1_OVER8BIT(15)
 #define USART_CR1_TE   BIT(3)
 #define USART_CR1_RE   BIT(2)
-- 
1.9.1

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[U-Boot] [PATCH v1 1/6] serial: stm32x7: cleanup code

[patrice.chotard]

From: Patrice Chotard 

Use BIT() macro and GENMASK() macro

Signed-off-by: Patrice Chotard 
Reviewed-by: Vikas Manocha 
---
 drivers/serial/serial_stm32x7.h | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
index 9fe37af..6d36b74 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32x7.h
@@ -28,18 +28,18 @@ struct stm32x7_serial_platdata {
unsigned long int clock_rate;
 };
 
-#define USART_CR1_OVER8(1 << 15)
-#define USART_CR1_TE   (1 << 3)
-#define USART_CR1_RE   (1 << 2)
-#define USART_CR1_UE   (1 << 0)
+#define USART_CR1_OVER8BIT(15)
+#define USART_CR1_TE   BIT(3)
+#define USART_CR1_RE   BIT(2)
+#define USART_CR1_UE   BIT(0)
 
-#define USART_CR3_OVRDIS   (1 << 12)
+#define USART_CR3_OVRDIS   BIT(12)
 
-#define USART_SR_FLAG_RXNE (1 << 5)
-#define USART_SR_FLAG_TXE  (1 << 7)
+#define USART_SR_FLAG_RXNE BIT(5)
+#define USART_SR_FLAG_TXE  BIT(7)
 
-#define USART_BRR_F_MASK   0xFF
+#define USART_BRR_F_MASK   GENMASK(7, 0)
 #define USART_BRR_M_SHIFT  4
-#define USART_BRR_M_MASK   0xFFF0
+#define USART_BRR_M_MASK   GENMASK(15, 4)
 
 #endif
-- 
1.9.1

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Re: [U-Boot] [PULL] u-boot-usb/master

[Marek Vasut]

The following changes since commit 9241265f29f3670e380a9859a343ddc14873c46f:

  Merge git://www.denx.de/git/u-boot-cfi-flash (2017-09-26 19:38:04 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git master

for you to fetch changes up to a939af0c748e2ea1eeb8cf47fa9771a95786de70:

  usb: dwc2: Align size of invalidating dcache before starting DMA
(2017-09-27 12:12:23 +0200)


Bin Meng (6):
  dm: usb: Add a new USB controller operation 'get_max_xfer_size'
  dm: usb: xhci: Implement get_max_xfer_size() operation
  dm: usb: ehci: Implement get_max_xfer_size() operation
  usb: storage: Refactor to use max_xfer_blk from struct us_data
  dm: usb: storage: Fix broken read/write when both EHCD and xHCD
are enabled
  usb: kbd: Set a default polling mechanism for USB keyboard



Marek Vasut (1):

  usb: xhci: Set number of event segments and entries to 1



Philipp Tomsich (3):
  rockchip: xhci: Convert to livetree
  usb: dwc2: convert to livetree
  usb: host: ehci-generic: convert to livetree

Seung-Woo Kim (1):
  usb: dwc2: Align size of invalidating dcache before starting DMA

 common/usb_storage.c   | 64
+---
 configs/Cyrus_P5020_defconfig  |  1 -
 configs/Cyrus_P5040_defconfig  |  1 -
 configs/MPC8610HPCD_defconfig  |  1 -
 configs/MPC8641HPCN_36BIT_defconfig|  1 -
 configs/MPC8641HPCN_defconfig  |  1 -
 configs/apalis_imx6_defconfig  |  1 -
 configs/apalis_imx6_nospl_com_defconfig|  1 -
 configs/apalis_imx6_nospl_it_defconfig |  1 -
 configs/colibri_imx6_defconfig |  1 -
 configs/colibri_imx6_nospl_defconfig   |  1 -
 configs/firefly-rk3288_defconfig   |  1 -
 configs/mx6cuboxi_defconfig|  1 -
 configs/rpi_2_defconfig|  1 -
 configs/rpi_3_32b_defconfig|  1 -
 configs/rpi_3_defconfig|  1 -
 configs/rpi_defconfig  |  1 -
 configs/sandbox_defconfig  |  1 -
 configs/sandbox_flattree_defconfig |  1 -
 configs/sandbox_noblk_defconfig|  1 -
 configs/sandbox_spl_defconfig  |  1 -
 configs/seaboard_defconfig |  1 -
 configs/ventana_defconfig  |  1 -
 drivers/usb/Kconfig|  2 +-
 drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c |  3 ++-
 drivers/usb/host/dwc2.c|  2 +-
 drivers/usb/host/ehci-generic.c|  2 +-
 drivers/usb/host/ehci-hcd.c| 12 
 drivers/usb/host/usb-uclass.c  | 11 +++
 drivers/usb/host/xhci-rockchip.c   |  4 +---
 drivers/usb/host/xhci.c| 15 +++
 drivers/usb/host/xhci.h|  4 ++--
 include/usb.h  | 22 +-
 33 files changed, 112 insertions(+), 51 deletions(-)
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Re: [U-Boot] [PATCH 1/1] sunxi: Fix A20-OLinuXino-MICRO dts for LAN8710

[Maxime Ripard]

Hi Stefan,

You should also put Jagan Teki as recipients.

On Wed, Sep 27, 2017 at 07:19:10AM +, Stefan Mavrodiev wrote:
> From revision J the board uses new phy chip LAN8710. Compared
> with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
> not to work. To fix this PA17 is muxed with GMAC function. This
> makes the pin output-low.
> 
> Signed-off-by: Stefan Mavrodiev 
> ---
>  arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 9 -
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts 
> b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
> index 7e3006f..0bc5ea9 100644
> --- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
> +++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
> @@ -95,7 +95,7 @@
>  
>   {
>   pinctrl-names = "default";
> - pinctrl-0 = <_pins_mii_a>;
> + pinctrl-0 = <_pins_mii_a>,<_txerr>;
>   phy = <>;
>   phy-mode = "mii";
>   status = "okay";
> @@ -226,6 +226,13 @@
>  };
>  
>   {
> + gmac_txerr: gmac_txerr@0 {
> + allwinner,pins = "PA17";
> + allwinner,function = "gpio_out";
> + allwinner,drive = ;
> + allwinner,pull = ;
> + };
> +

There's two issues with that patch:
  - In general we try to sync the DT with Linux when we can, and the
patch that ended up in Linux wasn't this one.
  - And we don't have any pinctrl support in U-Boot, that patch will
basically do nothing

The code that changes the muxing is here:
http://git.denx.de/?p=u-boot.git;a=blob;f=board/sunxi/gmac.c#l34

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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[U-Boot] [PATCH 8/8] rockchip: rk3128: add sdram driver

[Kever Yang]

RK3128 support up to 2GB DDR3 sdram, one channel, 32bit data width.

This patch is only used for U-Boot, but not for SPL which will
comes later, maybe after we merge all the common code into a common
file.

Signed-off-by: Kever Yang 
---

 drivers/ram/rockchip/Makefile   |  1 +
 drivers/ram/rockchip/sdram_rk3128.c | 60 +
 2 files changed, 61 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram_rk3128.c

diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 45b5fe7..1a1e557 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -5,6 +5,7 @@
 #
 
 obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
+obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
diff --git a/drivers/ram/rockchip/sdram_rk3128.c 
b/drivers/ram/rockchip/sdram_rk3128.c
new file mode 100644
index 000..04ad2bb
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3128.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+struct dram_info {
+   struct ram_info info;
+   struct rk3128_grf *grf;
+};
+
+static int rk3128_dmc_probe(struct udevice *dev)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   printf("%s: grf=%p\n", __func__, priv->grf);
+   priv->info.base = CONFIG_SYS_SDRAM_BASE;
+   priv->info.size = rockchip_sdram_size(
+   (phys_addr_t)>grf->os_reg[1]);
+
+   return 0;
+}
+
+static int rk3128_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   *info = priv->info;
+
+   return 0;
+}
+
+static struct ram_ops rk3128_dmc_ops = {
+   .get_info = rk3128_dmc_get_info,
+};
+
+
+static const struct udevice_id rk3128_dmc_ids[] = {
+   { .compatible = "rockchip,rk3128-dmc" },
+   { }
+};
+
+U_BOOT_DRIVER(dmc_rk3128) = {
+   .name = "rockchip_rk3128_dmc",
+   .id = UCLASS_RAM,
+   .of_match = rk3128_dmc_ids,
+   .ops = _dmc_ops,
+   .probe = rk3128_dmc_probe,
+   .priv_auto_alloc_size = sizeof(struct dram_info),
+};
-- 
1.9.1

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[U-Boot] [PATCH 7/8] rockchip: rk3128: add defconfig for evb-rk3128

[Kever Yang]

Enable board config for evb-rk3128.
Serial output and eMMC works in this version.

Signed-off-by: Kever Yang 
---

 configs/evb-rk3128_defconfig | 42 ++
 1 file changed, 42 insertions(+)
 create mode 100644 configs/evb-rk3128_defconfig

diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
new file mode 100644
index 000..e704305
--- /dev/null
+++ b/configs/evb-rk3128_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3128=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_FASTBOOT_BUF_ADDR=0x60800800
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RK3128=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_DEBUG_UART_BASE=0x20068000
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x310c
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y
-- 
1.9.1

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[U-Boot] [PATCH 6/8] rockchip: rk3128: add evb-rk3128 support

[Kever Yang]

evb-rk3128 is an evb from Rockchip based on rk3128 SoC:
- 2 USB2.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3128/Kconfig  | 23 +++
 board/rockchip/evb_rk3128/Kconfig  | 15 +++
 board/rockchip/evb_rk3128/MAINTAINERS  |  6 ++
 board/rockchip/evb_rk3128/Makefile |  7 +++
 board/rockchip/evb_rk3128/evb-rk3128.c |  9 +
 include/configs/evb_rk3128.h   | 23 +++
 6 files changed, 83 insertions(+)
 create mode 100644 board/rockchip/evb_rk3128/Kconfig
 create mode 100644 board/rockchip/evb_rk3128/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3128/Makefile
 create mode 100644 board/rockchip/evb_rk3128/evb-rk3128.c
 create mode 100644 include/configs/evb_rk3128.h

diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig 
b/arch/arm/mach-rockchip/rk3128/Kconfig
index e69de29..a6e8722 100644
--- a/arch/arm/mach-rockchip/rk3128/Kconfig
+++ b/arch/arm/mach-rockchip/rk3128/Kconfig
@@ -0,0 +1,23 @@
+if ROCKCHIP_RK3128
+
+choice
+   prompt "RK3128 board select"
+
+config TARGET_EVB_RK3128
+   bool "RK3128 evaluation board"
+   help
+ RK3128evb is a evaluation board for Rockchip rk3128,
+ with full function and phisical connectors support like
+ usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
+
+endchoice
+
+config SYS_SOC
+   default "rockchip"
+
+config SYS_MALLOC_F_LEN
+   default 0x0800
+
+source "board/rockchip/evb_rk3128/Kconfig"
+
+endif
diff --git a/board/rockchip/evb_rk3128/Kconfig 
b/board/rockchip/evb_rk3128/Kconfig
new file mode 100644
index 000..5b3095a
--- /dev/null
+++ b/board/rockchip/evb_rk3128/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3128
+
+config SYS_BOARD
+   default "evb_rk3128"
+
+config SYS_VENDOR
+   default "rockchip"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3128"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3128/MAINTAINERS 
b/board/rockchip/evb_rk3128/MAINTAINERS
new file mode 100644
index 000..f5145d1
--- /dev/null
+++ b/board/rockchip/evb_rk3128/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3128
+M:  Kever Yang 
+S:  Maintained
+F:  board/rockchip/evb_rk3128
+F:  include/configs/evb_rk3128.h
+F:  configs/evb-rk3128_defconfig
diff --git a/board/rockchip/evb_rk3128/Makefile 
b/board/rockchip/evb_rk3128/Makefile
new file mode 100644
index 000..6040891
--- /dev/null
+++ b/board/rockchip/evb_rk3128/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evb-rk3128.o
diff --git a/board/rockchip/evb_rk3128/evb-rk3128.c 
b/board/rockchip/evb_rk3128/evb-rk3128.c
new file mode 100644
index 000..bf36e25
--- /dev/null
+++ b/board/rockchip/evb_rk3128/evb-rk3128.c
@@ -0,0 +1,9 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
diff --git a/include/configs/evb_rk3128.h b/include/configs/evb_rk3128.h
new file mode 100644
index 000..f60e22c
--- /dev/null
+++ b/include/configs/evb_rk3128.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EVB_RK3128_H
+#define __EVB_RK3128_H
+
+#include 
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+/*
+ * SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+
+#define CONFIG_CONSOLE_SCROLL_LINES10
+
+#endif
-- 
1.9.1

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[U-Boot] [PATCH 3/8] rockchip: rk3128: add clock driver

[Kever Yang]

Add rk3128 clock driver and cru structure definition.

Signed-off-by: Kever Yang 
---

 arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 173 
 arch/arm/mach-rockchip/rk3128/Makefile  |   1 +
 arch/arm/mach-rockchip/rk3128/clk_rk3128.c  |  32 +++
 drivers/clk/rockchip/Makefile   |   3 +-
 drivers/clk/rockchip/clk_rk3128.c   | 350 
 5 files changed, 558 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3128.h
 create mode 100644 arch/arm/mach-rockchip/rk3128/clk_rk3128.c
 create mode 100644 drivers/clk/rockchip/clk_rk3128.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
new file mode 100644
index 000..f511bd0
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3128_H
+#define _ASM_ARCH_CRU_RK3128_H
+
+#include 
+
+#define MHz100
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(600 * MHz)
+#define GPLL_HZ(594 * MHz)
+
+#define CORE_PERI_HZ   15000
+#define CORE_ACLK_HZ   3
+
+#define BUS_ACLK_HZ14850
+#define BUS_HCLK_HZ14850
+#define BUS_PCLK_HZ7425
+
+#define PERI_ACLK_HZ   14850
+#define PERI_HCLK_HZ   14850
+#define PERI_PCLK_HZ   7425
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3128_clk_priv {
+   struct rk3128_cru *cru;
+   ulong rate;
+};
+
+struct rk3128_cru {
+   struct rk3128_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   } pll[4];
+   unsigned int cru_mode_con;
+   unsigned int cru_clksel_con[35];
+   unsigned int cru_clkgate_con[11];
+   unsigned int reserved;
+   unsigned int cru_glb_srst_fst_value;
+   unsigned int cru_glb_srst_snd_value;
+   unsigned int reserved1[2];
+   unsigned int cru_softrst_con[9];
+   unsigned int cru_misc_con;
+   unsigned int reserved2[2];
+   unsigned int cru_glb_cnt_th;
+   unsigned int reserved3[3];
+   unsigned int cru_glb_rst_st;
+   unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
+   unsigned int cru_sdmmc_con[2];
+   unsigned int cru_sdio_con[2];
+   unsigned int reserved5[2];
+   unsigned int cru_emmc_con[2];
+   unsigned int reserved6[4];
+   unsigned int cru_pll_prg_en;
+};
+check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
+
+struct pll_div {
+   u32 refdiv;
+   u32 fbdiv;
+   u32 postdiv1;
+   u32 postdiv2;
+   u32 frac;
+};
+
+enum {
+   /* PLLCON0*/
+   PLL_POSTDIV1_SHIFT  = 12,
+   PLL_POSTDIV1_MASK   = 7 << PLL_POSTDIV1_SHIFT,
+   PLL_FBDIV_SHIFT = 0,
+   PLL_FBDIV_MASK  = 0xfff,
+
+   /* PLLCON1 */
+   PLL_RST_SHIFT   = 14,
+   PLL_PD_SHIFT= 13,
+   PLL_PD_MASK = 1 << PLL_PD_SHIFT,
+   PLL_DSMPD_SHIFT = 12,
+   PLL_DSMPD_MASK  = 1 << PLL_DSMPD_SHIFT,
+   PLL_LOCK_STATUS_SHIFT   = 10,
+   PLL_LOCK_STATUS_MASK= 1 << PLL_LOCK_STATUS_SHIFT,
+   PLL_POSTDIV2_SHIFT  = 6,
+   PLL_POSTDIV2_MASK   = 7 << PLL_POSTDIV2_SHIFT,
+   PLL_REFDIV_SHIFT= 0,
+   PLL_REFDIV_MASK = 0x3f,
+
+   /* CRU_MODE */
+   GPLL_MODE_SHIFT = 12,
+   GPLL_MODE_MASK  = 3 << GPLL_MODE_SHIFT,
+   GPLL_MODE_SLOW  = 0,
+   GPLL_MODE_NORM,
+   GPLL_MODE_DEEP,
+   DPLL_MODE_SHIFT = 4,
+   DPLL_MODE_MASK  = 1 << DPLL_MODE_SHIFT,
+   DPLL_MODE_SLOW  = 0,
+   DPLL_MODE_NORM,
+   APLL_MODE_SHIFT = 0,
+   APLL_MODE_MASK  = 1 << APLL_MODE_SHIFT,
+   APLL_MODE_SLOW  = 0,
+   APLL_MODE_NORM,
+
+   /* CRU_CLK_SEL0_CON */
+   BUS_ACLK_PLL_SEL_SHIFT  = 14,
+   BUS_ACLK_PLL_SEL_MASK   = 3 << BUS_ACLK_PLL_SEL_SHIFT,
+   BUS_ACLK_PLL_SEL_CPLL   = 0,
+   BUS_ACLK_PLL_SEL_GPLL,
+   BUS_ACLK_PLL_SEL_GPLL_DIV2,
+   BUS_ACLK_PLL_SEL_GPLL_DIV3,
+   BUS_ACLK_DIV_SHIFT  = 8,
+   BUS_ACLK_DIV_MASK   = 0x1f << BUS_ACLK_DIV_SHIFT,
+   CORE_CLK_PLL_SEL_SHIFT  = 7,
+   CORE_CLK_PLL_SEL_MASK   = 1 << CORE_CLK_PLL_SEL_SHIFT,
+   CORE_CLK_PLL_SEL_APLL   = 0,
+   CORE_CLK_PLL_SEL_GPLL_DIV2,
+   CORE_DIV_CON_SHIFT  = 0,
+   CORE_DIV_CON_MASK   = 0x1f << CORE_DIV_CON_SHIFT,
+
+   /* CRU_CLK_SEL1_CON */
+   BUS_PCLK_DIV_SHIFT  = 12,
+   BUS_PCLK_DIV_MASK   = 7 << BUS_PCLK_DIV_SHIFT,
+   BUS_HCLK_DIV_SHIFT  = 8,
+   BUS_HCLK_DIV_MASK   = 3 << BUS_HCLK_DIV_SHIFT,
+   CORE_ACLK_DIV_SHIFT = 4,

[U-Boot] [PATCH 4/8] rockchip: rk3128: add pinctrl driver

[Kever Yang]

Add rk3128 pinctrl driver and grf/iomux structure definition.

Signed-off-by: Kever Yang 
---

 arch/arm/include/asm/arch-rockchip/grf_rk3128.h | 551 
 drivers/pinctrl/Kconfig |  10 +
 drivers/pinctrl/rockchip/Makefile   |   4 +-
 drivers/pinctrl/rockchip/pinctrl_rk3128.c   | 192 +
 4 files changed, 755 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3128.h
 create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3128.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h
new file mode 100644
index 000..5da6cd2
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h
@@ -0,0 +1,551 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK3128_H
+#define _ASM_ARCH_GRF_RK3128_H
+
+#include 
+
+struct rk3128_grf {
+   unsigned int reserved[0x2a];
+   unsigned int gpio0a_iomux;
+   unsigned int gpio0b_iomux;
+   unsigned int gpio0c_iomux;
+   unsigned int gpio0d_iomux;
+   unsigned int gpio1a_iomux;
+   unsigned int gpio1b_iomux;
+   unsigned int gpio1c_iomux;
+   unsigned int gpio1d_iomux;
+   unsigned int gpio2a_iomux;
+   unsigned int gpio2b_iomux;
+   unsigned int gpio2c_iomux;
+   unsigned int gpio2d_iomux;
+   unsigned int gpio3a_iomux;
+   unsigned int gpio3b_iomux;
+   unsigned int gpio3c_iomux;
+   unsigned int gpio3d_iomux;
+   unsigned int gpio2c_iomux2;
+   unsigned int grf_cif_iomux;
+   unsigned int grf_cif_iomux1;
+   unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
+   unsigned int gpio0l_pull;
+   unsigned int gpio0h_pull;
+   unsigned int gpio1l_pull;
+   unsigned int gpio1h_pull;
+   unsigned int gpio2l_pull;
+   unsigned int gpio2h_pull;
+   unsigned int gpio3l_pull;
+   unsigned int gpio3h_pull;
+   unsigned int reserved2;
+   unsigned int soc_con0;
+   unsigned int soc_con1;
+   unsigned int soc_con2;
+   unsigned int soc_status0;
+   unsigned int reserved3[6];
+   unsigned int mac_con0;
+   unsigned int mac_con1;
+   unsigned int reserved4[4];
+   unsigned int uoc0_con0;
+   unsigned int reserved5;
+   unsigned int uoc1_con1;
+   unsigned int uoc1_con2;
+   unsigned int uoc1_con3;
+   unsigned int uoc1_con4;
+   unsigned int uoc1_con5;
+   unsigned int reserved6;
+   unsigned int ddrc_stat;
+   unsigned int reserved9;
+   unsigned int soc_status1;
+   unsigned int cpu_con0;
+   unsigned int cpu_con1;
+   unsigned int cpu_con2;
+   unsigned int cpu_con3;
+   unsigned int reserved10;
+   unsigned int reserved11;
+   unsigned int cpu_status0;
+   unsigned int cpu_status1;
+   unsigned int os_reg[8];
+   unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
+   unsigned int usbphy0_con[8];
+   unsigned int usbphy1_con[8];
+   unsigned int uoc_status0;
+   unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
+   unsigned int chip_tag;
+   unsigned int sdmmc_det_cnt;
+};
+check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
+
+struct rk3128_pmu {
+   unsigned int wakeup_cfg;
+   unsigned int pwrdn_con;
+   unsigned int pwrdn_st;
+   unsigned int idle_req;
+   unsigned int idle_st;
+   unsigned int pwrmode_con;
+   unsigned int pwr_state;
+   unsigned int osc_cnt;
+   unsigned int core_pwrdwn_cnt;
+   unsigned int core_pwrup_cnt;
+   unsigned int sft_con;
+   unsigned int ddr_sref_st;
+   unsigned int int_con;
+   unsigned int int_st;
+   unsigned int sys_reg[4];
+};
+check_member(rk3128_pmu, int_st, 0x34);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+   GPIO0A7_SHIFT   = 14,
+   GPIO0A7_MASK= 3 << GPIO0A7_SHIFT,
+   GPIO0A7_GPIO= 0,
+   GPIO0A7_I2C3_SDA,
+
+   GPIO0A6_SHIFT   = 12,
+   GPIO0A6_MASK= 3 << GPIO0A6_SHIFT,
+   GPIO0A6_GPIO= 0,
+   GPIO0A6_I2C3_SCL,
+
+   GPIO0A3_SHIFT   = 6,
+   GPIO0A3_MASK= 3 << GPIO0A3_SHIFT,
+   GPIO0A3_GPIO= 0,
+   GPIO0A3_I2C1_SDA,
+
+   GPIO0A2_SHIFT   = 4,
+   GPIO0A2_MASK= 1 << GPIO0A2_SHIFT,
+   GPIO0A2_GPIO= 0,
+   GPIO0A2_I2C1_SCL,
+
+   GPIO0A1_SHIFT   = 2,
+   GPIO0A1_MASK= 1 << GPIO0A1_SHIFT,
+   GPIO0A1_GPIO= 0,
+   GPIO0A1_I2C0_SDA,
+
+   GPIO0A0_SHIFT   = 0,
+   GPIO0A0_MASK= 1 << GPIO0A0_SHIFT,
+   GPIO0A0_GPIO= 0,
+   GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+   GPIO0B6_SHIFT   = 12,
+   GPIO0B6_MASK= 3 << GPIO0B6_SHIFT,
+   

[U-Boot] [PATCH 2/8] rockchip: rk3128: add soc basic support

[Kever Yang]

RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU
and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host
and device, HDMI/LVDS/MIPI display.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/Kconfig|  10 ++
 arch/arm/mach-rockchip/Makefile   |   2 +
 arch/arm/mach-rockchip/rk3128-board.c | 146 ++
 arch/arm/mach-rockchip/rk3128/Kconfig |   0
 arch/arm/mach-rockchip/rk3128/Makefile|   8 ++
 arch/arm/mach-rockchip/rk3128/rk3128.c|  12 +++
 arch/arm/mach-rockchip/rk3128/syscon_rk3128.c |  21 
 include/configs/rk3128_common.h   |  70 
 8 files changed, 269 insertions(+)
 create mode 100644 arch/arm/mach-rockchip/rk3128-board.c
 create mode 100644 arch/arm/mach-rockchip/rk3128/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3128/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3128/rk3128.c
 create mode 100644 arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
 create mode 100644 include/configs/rk3128_common.h

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index e1bc947..7a4f2a1 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,6 +11,15 @@ config ROCKCHIP_RK3036
  and video codec support. Peripherals include Gigabit Ethernet,
  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
 
+config ROCKCHIP_RK3128
+   bool "Support Rockchip RK3128"
+   select CPU_V7
+   help
+ The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
+ including NEON and GPU, Mali-400 graphics, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
 config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7
@@ -173,6 +182,7 @@ config SPL_MMC_SUPPORT
default y if !SPL_ROCKCHIP_BACK_TO_BROM
 
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3128/Kconfig"
 source "arch/arm/mach-rockchip/rk3188/Kconfig"
 source "arch/arm/mach-rockchip/rk322x/Kconfig"
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5ef0938..3974c5e 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -24,6 +24,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o 
spl-boot-order.o
 
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
@@ -36,6 +37,7 @@ obj-y += rk_timer.o
 endif
 
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
 ifndef CONFIG_TPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
 endif
diff --git a/arch/arm/mach-rockchip/rk3128-board.c 
b/arch/arm/mach-rockchip/rk3128-board.c
new file mode 100644
index 000..70eda6f
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128-board.c
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PMU_BASE   0x100a
+
+static void setup_boot_mode(void)
+{
+   struct rk3128_pmu *const pmu = (void *)PMU_BASE;
+   int boot_mode = readl(>sys_reg[0]);
+
+   debug("boot mode %x.\n", boot_mode);
+
+   /* Clear boot mode */
+   writel(BOOT_NORMAL, >sys_reg[0]);
+
+   switch (boot_mode) {
+   case BOOT_FASTBOOT:
+   printf("enter fastboot!\n");
+   env_set("preboot", "setenv preboot; fastboot usb0");
+   break;
+   case BOOT_UMS:
+   printf("enter UMS!\n");
+   env_set("preboot", "setenv preboot; ums mmc 0");
+   break;
+   case BOOT_LOADER:
+   printf("enter Rockusb!\n");
+   env_set("preboot", "setenv preboot; rockusb 0 mmc 0");
+   break;
+   }
+}
+
+__weak int rk_board_late_init(void)
+{
+   return 0;
+}
+
+int board_late_init(void)
+{
+   setup_boot_mode();
+
+   return rk_board_late_init();
+}
+
+int board_init(void)
+{
+   rockchip_timer_init();
+
+   return 0;
+}
+
+int dram_init_banksize(void)
+{
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   gd->bd->bi_dram[0].size = 0x840;
+   /* Reserve 0x20 for OPTEE */
+   gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+   + gd->bd->bi_dram[0].size + 0x20;
+   gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+   + gd->ram_size - 

[U-Boot] [PATCH 5/8] rockchip: rk3128: add sysreset driver

[Kever Yang]

Add rk3128 sysreset driver.

Signed-off-by: Kever Yang 
---

 drivers/sysreset/Makefile  |  1 +
 drivers/sysreset/sysreset_rk3128.c | 45 ++
 2 files changed, 46 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_rk3128.c

diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index ce161a7..e3a0ab1 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
 endif
+obj-$(CONFIG_ROCKCHIP_RK3128) += sysreset_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += sysreset_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
diff --git a/drivers/sysreset/sysreset_rk3128.c 
b/drivers/sysreset/sysreset_rk3128.c
new file mode 100644
index 000..5aab8ec
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk3128.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int rk3128_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+   struct rk3128_cru *cru = rockchip_get_cru();
+
+   if (IS_ERR(cru))
+   return PTR_ERR(cru);
+   switch (type) {
+   case SYSRESET_WARM:
+   writel(0xeca8, >cru_glb_srst_snd_value);
+   break;
+   case SYSRESET_COLD:
+   writel(0xfdb9, >cru_glb_srst_fst_value);
+   break;
+   default:
+   return -EPROTONOSUPPORT;
+   }
+
+   return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3128_sysreset = {
+   .request= rk3128_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3128) = {
+   .name   = "rk3128_sysreset",
+   .id = UCLASS_SYSRESET,
+   .ops= _sysreset,
+};
-- 
1.9.1

___
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[U-Boot] [PATCH 1/8] rockchip: rk3128: add device tree file

[Kever Yang]

Add dts binding header for rk3128, files origin from kernel.

Signed-off-by: Kever Yang 
---

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3128-evb.dts|  77 
 arch/arm/dts/rk3128.dtsi   | 756 +
 include/dt-bindings/clock/rk3128-cru.h | 187 
 4 files changed, 1021 insertions(+)
 create mode 100644 arch/arm/dts/rk3128-evb.dts
 create mode 100644 arch/arm/dts/rk3128.dtsi
 create mode 100644 include/dt-bindings/clock/rk3128-cru.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 762429c..9fc8127 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
+   rk3128-evb.dtb \
rk3188-radxarock.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts
new file mode 100644
index 000..5ef51c9
--- /dev/null
+++ b/arch/arm/dts/rk3128-evb.dts
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "rk3128.dtsi"
+
+/ {
+   model = "Rockchip RK3128 Evaluation board";
+   compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
+
+   chosen {
+   stdout-path = 
+   };
+
+   vcc5v0_otg: vcc5v0-otg-drv {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_otg";
+   gpio = < 26 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_vbus_drv>;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc5v0_host: vcc5v0-host-drv {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_host";
+   gpio = < 23 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_vbus_drv>;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
+};
+
+ {
+   status = "okay";
+
+hym8563: hym8563@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   };
+};
+
+_host {
+   status = "okay";
+};
+
+_otg {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   usb_otg {
+   otg_vbus_drv: host-vbus-drv {
+   rockchip,pins = <0 26 RK_FUNC_GPIO _pull_none>;
+   };
+   };
+
+   usb_host {
+   host_vbus_drv: host-vbus-drv {
+   rockchip,pins = <2 23 RK_FUNC_GPIO _pull_none>;
+   };
+   };
+};
diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
new file mode 100644
index 000..e7710b7
--- /dev/null
+++ b/arch/arm/dts/rk3128.dtsi
@@ -0,0 +1,756 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "skeleton.dtsi"
+
+/ {
+   compatible = "rockchip,rk3128";
+   rockchip,sram = <>;
+   interrupt-parent = <>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   gpio3 = 
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   i2c3 = 
+   spi0 = 
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   mmc0 = 
+   mmc1 = 
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x6000 0x4000>;
+   };
+
+arm-pmu {
+compatible = "arm,cortex-a7-pmu";
+interrupts = ,
+ ,
+,
+;
+};
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   enable-method = "rockchip,rk3128-smp";
+
+   cpu0:cpu@0x000 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x000>;
+   operating-points = <
+   /* KHzuV */
+816000 100
+   >;
+   #cooling-cells = <2>; /* min followed by max */
+   clock-latency = <4>;
+   clocks = < ARMCLK>;
+   };
+
+   cpu1:cpu@0x001 {
+  

[U-Boot] [PATCH 0/8] rockchip: add new SoC support for RK3128

[Kever Yang]

RK3128 is a quad-core ARM Cortex-A7 SoC, this patch set add basic
support for it, it does not support SPL/TPL now, and the sdram driver
only support get dram size from sysreg in U-Boot stage. Most of basic
driver like clock, pinctrl, sysreset have been implement, and more
drivers like mac and display will be later.



Kever Yang (8):
  rockchip: rk3128: add device tree file
  rockchip: rk3128: add soc basic support
  rockchip: rk3128: add clock driver
  rockchip: rk3128: add pinctrl driver
  rockchip: rk3128: add sysreset driver
  rockchip: rk3128: add evb-rk3128 support
  rockchip: rk3128: add defconfig for evb-rk3128
  rockchip: rk3128: add sdram driver

 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/rk3128-evb.dts |  77 +++
 arch/arm/dts/rk3128.dtsi| 756 
 arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 173 ++
 arch/arm/include/asm/arch-rockchip/grf_rk3128.h | 551 +
 arch/arm/mach-rockchip/Kconfig  |  10 +
 arch/arm/mach-rockchip/Makefile |   2 +
 arch/arm/mach-rockchip/rk3128-board.c   | 146 +
 arch/arm/mach-rockchip/rk3128/Kconfig   |  23 +
 arch/arm/mach-rockchip/rk3128/Makefile  |   9 +
 arch/arm/mach-rockchip/rk3128/clk_rk3128.c  |  32 +
 arch/arm/mach-rockchip/rk3128/rk3128.c  |  12 +
 arch/arm/mach-rockchip/rk3128/syscon_rk3128.c   |  21 +
 board/rockchip/evb_rk3128/Kconfig   |  15 +
 board/rockchip/evb_rk3128/MAINTAINERS   |   6 +
 board/rockchip/evb_rk3128/Makefile  |   7 +
 board/rockchip/evb_rk3128/evb-rk3128.c  |   9 +
 configs/evb-rk3128_defconfig|  42 ++
 drivers/clk/rockchip/Makefile   |   3 +-
 drivers/clk/rockchip/clk_rk3128.c   | 350 +++
 drivers/pinctrl/Kconfig |  10 +
 drivers/pinctrl/rockchip/Makefile   |   4 +-
 drivers/pinctrl/rockchip/pinctrl_rk3128.c   | 192 ++
 drivers/ram/rockchip/Makefile   |   1 +
 drivers/ram/rockchip/sdram_rk3128.c |  60 ++
 drivers/sysreset/Makefile   |   1 +
 drivers/sysreset/sysreset_rk3128.c  |  45 ++
 include/configs/evb_rk3128.h|  23 +
 include/configs/rk3128_common.h |  70 +++
 include/dt-bindings/clock/rk3128-cru.h  | 187 ++
 30 files changed, 2835 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/rk3128-evb.dts
 create mode 100644 arch/arm/dts/rk3128.dtsi
 create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3128.h
 create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3128.h
 create mode 100644 arch/arm/mach-rockchip/rk3128-board.c
 create mode 100644 arch/arm/mach-rockchip/rk3128/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3128/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3128/clk_rk3128.c
 create mode 100644 arch/arm/mach-rockchip/rk3128/rk3128.c
 create mode 100644 arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
 create mode 100644 board/rockchip/evb_rk3128/Kconfig
 create mode 100644 board/rockchip/evb_rk3128/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3128/Makefile
 create mode 100644 board/rockchip/evb_rk3128/evb-rk3128.c
 create mode 100644 configs/evb-rk3128_defconfig
 create mode 100644 drivers/clk/rockchip/clk_rk3128.c
 create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c
 create mode 100644 drivers/ram/rockchip/sdram_rk3128.c
 create mode 100644 drivers/sysreset/sysreset_rk3128.c
 create mode 100644 include/configs/evb_rk3128.h
 create mode 100644 include/configs/rk3128_common.h
 create mode 100644 include/dt-bindings/clock/rk3128-cru.h

-- 
1.9.1

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Re: [U-Boot] [GIT PULL] u-boot-sunxi/master

[Tom Rini]

On Wed, Sep 27, 2017 at 12:31:16PM +0200, Maxime Ripard wrote:
> Hi Tom,
> 
> Here is a pull request for the sunxi related changes for the next
> U-Boot version.
> 
> The diffstat is a bit scary, but mostly because of the Kconfig
> migration of the USB ethernet related options, which were enabled by a
> big number of boards. The fastboot options simplification is also one
> of the offenders.
> 
> This is my first pull request ever, so I might have done something
> wrong, let me know if it's the case.

Sorry, this is pretty broken:
$ make O=/tmp/T sandbox_config
make[1]: Entering directory `/tmp/T'
GEN ./Makefile
drivers/usb/Kconfig:1:error: recursive dependency detected!
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
drivers/usb/Kconfig:1:  symbol USB is selected by ARCH_SUNXI
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
arch/arm/Kconfig:674:   symbol ARCH_SUNXI is part of choice 
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
arch/arm/Kconfig:291:   choice  contains symbol ARCH_SUNXI
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
arch/arm/Kconfig:674:   symbol ARCH_SUNXI depends on USB_MUSB_GADGET
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
drivers/usb/musb-new/Kconfig:11:symbol USB_MUSB_GADGET depends on USB

-- 
Tom


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Re: [U-Boot] [U-Boot,v4,1/2] rockchip: rk322x: add sdram driver

[Philipp Tomsich]

> Add driver for rk322x to support sdram initialize in SPL.
> 
> Signed-off-by: Kever Yang 
> Acked-by: Philipp Tomsich 
> Reviewed-by: Philipp Tomsich 
> ---
> 
> Changes in v4:
> - rebase on u-boot-rockchip master with patchset "move rockchip sdram
>   driver to driver/ram"
> 
> Changes in v3:
> - move rk332x sdram driver to driver/ram
> - do the ram init in TPL instad of SPL
> 
>  arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 581 +++
>  drivers/ram/rockchip/Makefile |   1 +
>  drivers/ram/rockchip/sdram_rk322x.c   | 855 
> ++
>  3 files changed, 1437 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
>  create mode 100644 drivers/ram/rockchip/sdram_rk322x.c
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-Boot, v4, 2/2] rockchip: dts: rk3229: remove dram channel info

[Philipp Tomsich]

> The dram channel info will be auto detect by the driver,
> we do not need it.
> 
> Signed-off-by: Kever Yang 
> ---
> 
> Changes in v4: None
> Changes in v3: None
> 
>  arch/arm/dts/rk3229-evb.dts | 1 -
>  1 file changed, 1 deletion(-)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-Boot, v2, 2/4] rockchip: rk3188: move sdram driver to driver/ram

[Philipp Tomsich]

> Since we have CONFIG_RAM framwork and its driver folder, move the driver
> into it.
> 
> Signed-off-by: Kever Yang 
> Acked-by: Philipp Tomsich 
> Reviewed-by: Philipp Tomsich 
> ---
> 
>  arch/arm/mach-rockchip/rk3188/Makefile | 1 -
>  drivers/ram/rockchip/Makefile  | 1 +
>  {arch/arm/mach-rockchip/rk3188 => drivers/ram/rockchip}/sdram_rk3188.c | 0
>  3 files changed, 1 insertion(+), 1 deletion(-)
>  rename {arch/arm/mach-rockchip/rk3188 => 
> drivers/ram/rockchip}/sdram_rk3188.c (100%)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-Boot, v2, 4/4] rockchip: rk3328: move sdram driver to driver/ram

[Philipp Tomsich]

> Since we have CONFIG_RAM framwork and its driver folder, move the driver
> into it.
> 
> Signed-off-by: Kever Yang 
> Acked-by: Philipp Tomsich 
> Reviewed-by: Philipp Tomsich 
> ---
> 
>  arch/arm/mach-rockchip/rk3328/Makefile | 1 -
>  drivers/ram/rockchip/Makefile  | 1 +
>  {arch/arm/mach-rockchip/rk3328 => drivers/ram/rockchip}/sdram_rk3328.c | 0
>  3 files changed, 1 insertion(+), 1 deletion(-)
>  rename {arch/arm/mach-rockchip/rk3328 => 
> drivers/ram/rockchip}/sdram_rk3328.c (100%)
> 

Applied to u-boot-rockchip, thanks!
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