date:20180117

Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

2018-01-17 Thread Simon Goldschmidt

Pepperl+Fuchs GmbH, Mannheim
Geschaeftsfuehrer/Managing Directors: Dr.-Ing. Gunther Kegel (Vors./CEO),
Werner Guthier, Mehmet Hatiboglu
Vorsitzender des Aufsichtsrats/Chairman of the supervisory board: Claus Michael
Registergericht/Register Court: AG Mannheim HRB 4713
On 18.01.2018 06:07, Jason Rush wrote:

On 1/17/2018 7:46 AM, RB23 wrote:

i checked, and if you mean these patches:
https://patchwork.ozlabs.org/patch/765992/
https://patchwork.ozlabs.org/patch/765996/
https://patchwork.ozlabs.org/patch/765997/
https://patchwork.ozlabs.org/patch/765998/

i already applied them, and they didn't work as well.

i also found these patches which i didn't try yet:
https://lists.denx.de/pipermail/u-boot/2017-May/292230.html

should i try those instead?

2018-01-17 15:09 GMT+02:00 Marek Vasut :

On 01/17/2018 02:06 PM, Simon Goldschmidt wrote:

On 17.01.2018 14:01, RB23 wrote:

hey, i downloaded the september and november versions and i applied
the patches on both of them, re-compiled the u boot,
and still, it gives me the same error when trying the command "sf probe"
i'm not sure what to do, is it possible that i missed something? like
a define or something in the make menuconfig?
i did some debugging and it seems that the crash happens on this line:
div = DIV_ROUND_UP(ref_clk_hz, sclk-hz * 2) -1;
thanks.

I don't know exactly which patches you are talking about, but the
divide-by-zero problem is still present with all patches I applied. To
fix it, you need to set up your device tree correctly so that the speed
is initialized.

If I remember correctly, you need need to have a flash chip below the
qspi in the device tree. Check Jason's changes to the various socfpga
dts files.

Er, maybe a patch which checks this condition wouldn't hurt ?

--
Best regards,
Marek Vasut

I re-tested on a Cyclone V SoCKit devboard and a custom Arria V board using the
DTS
patches I submitted (the 4 you mentioned above) and Vignesh's patch to fix the
cache
invalidation problem, and I don't get the divide-by-zero problem. This looks
like the
clock rate for the flash part isn't getting set and is defaulting to 0 for some
reason.
I would look at your device tree. Are you using a stock device tree, or is
this a custom
board? Make sure the 'spi-max-frequency' is being set for the flash part that
is a child
to the cadence qspi node in the device tree.

Note that in addition to the 'spi-max-frequency' property, the flash
part (child of the cadence qspi node) also must have 'compatible =
"spi-flash";'.

This only seems to fail in U-Boot when loading the environment or
executing 'sf probe' without speed argument. SPL succeeds to load U-Boot
from qspi without a 'spi-max-frequency' because the cadence qspi driver
has a fallback to 500 kHz which gets overridden by the code from U-Boot.

Regards,
Simon

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Re: [U-Boot] [PATCH 3/3] clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks()

2018-01-17 Thread Patrice CHOTARD

Hi Vikas

On 01/17/2018 08:55 PM, Vikas Manocha wrote:
> Hi Patrice,
> 
> On 01/17/2018 12:46 AM, patrice.chot...@st.com wrote:
>> From: Patrice Chotard 
>>
>> Move SYSCFG clock setup into configure_clocks() instead of calling
>> clock_setup() from drivers.
> 
> It is in board configuration.

Yes, my comment is badly formulated.

The idea is to remove clock_setup() from clock driver.

> 
>> Move the RMII setup from board_early_init_f() to board_init()
>> to insure that RMII bit is set only when clock driver is initialized.
>>
>> Signed-off-by: Patrice Chotard 
>> ---
>>   arch/arm/include/asm/arch-stm32f7/stm32_periph.h |  1 -
>>   board/st/stm32f746-disco/stm32f746-disco.c   | 19 ++-
>>   drivers/clk/clk_stm32f.c | 10 --
>>   3 files changed, 10 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h 
>> b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
>> index 13f9c9b..7b8f66a 100644
>> --- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
>> +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
>> @@ -21,7 +21,6 @@ enum periph_id {
>>   };
>>   
>>   enum periph_clock {
>> -SYSCFG_CLOCK_CFG,
>>  TIMER2_CLOCK_CFG,
>>   };
>>   
>> diff --git a/board/st/stm32f746-disco/stm32f746-disco.c 
>> b/board/st/stm32f746-disco/stm32f746-disco.c
>> index 58a5ef0..8da7028 100644
>> --- a/board/st/stm32f746-disco/stm32f746-disco.c
>> +++ b/board/st/stm32f746-disco/stm32f746-disco.c
>> @@ -69,23 +69,10 @@ int dram_init_banksize(void)
>>  return 0;
>>   }
>>   
>> -#ifdef CONFIG_ETH_DESIGNWARE
>> -static int stmmac_setup(void)
>> -{
>> -clock_setup(SYSCFG_CLOCK_CFG);
>> -/* Set >RMII mode */
>> -STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
>> -
>> -return 0;
>> -}
>> -
>>   int board_early_init_f(void)
>>   {
>> -stmmac_setup();
>> -
>>  return 0;
>>   }
>> -#endif
>>   
>>   #ifdef CONFIG_SPL_BUILD
>>   #ifdef CONFIG_SPL_OS_BOOT
>> @@ -162,5 +149,11 @@ int board_late_init(void)
>>   int board_init(void)
>>   {
>>  gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
>> +
>> +#ifdef CONFIG_ETH_DESIGNWARE
>> +/* Set >RMII mode */
>> +STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
>> +#endif
>> +
>>  return 0;
>>   }
>> diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
>> index d0c7a90..1ae5b70 100644
>> --- a/drivers/clk/clk_stm32f.c
>> +++ b/drivers/clk/clk_stm32f.c
>> @@ -67,8 +67,6 @@
>>   #define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
>>   #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
>>   
>> -#define RCC_APB2ENR_SAI1EN  BIT(22)
>> -
>>   /*
>>* RCC AHB1ENR specific definitions
>>*/
>> @@ -86,9 +84,9 @@
>>* RCC APB2ENR specific definitions
>>*/
>>   #define RCC_APB2ENR_SYSCFGEN   BIT(14)
>> +#define RCC_APB2ENR_SAI1EN  BIT(22)
>>   
>>   enum periph_clock {
>> -SYSCFG_CLOCK_CFG,
>>  TIMER2_CLOCK_CFG,
>>   };
>>   
>> @@ -227,6 +225,9 @@ static int configure_clocks(struct udevice *dev)
>>  /* gate the SAI clock, needed for MMC 1&2 clocks */
>>  setbits_le32(>apb2enr, RCC_APB2ENR_SAI1EN);
>>   
>> +/* gate the SYSCFG clock, needed to set RMII ethernet interface */
> 
> RMII interface only required for f746 disco board.
> 
>> +setbits_le32(>apb2enr, RCC_APB2ENR_SYSCFGEN);
> 
> RMII & Syscfg is board specific requirement, here it will configure it for 
> all stm32f devices.

You are right, i will update this. As it is currently only needed for 
ethernet, i will add the CONFIG_ETH_DESIGNWARE flag around.

For information, i will add new stm32f429-evaluation board (already 
supported in kernel) which provide ethernet connection.

Thanks for reviewing

Patrice

> 
> Cheers,
> Vikas
> 
>> +
>>  return 0;
>>   }
>>   
>> @@ -352,9 +353,6 @@ static int stm32_clk_enable(struct clk *clk)
>>   void clock_setup(int peripheral)
>>   {
>>  switch (peripheral) {
>> -case SYSCFG_CLOCK_CFG:
>> -setbits_le32(_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
>> -break;
>>  case TIMER2_CLOCK_CFG:
>>  setbits_le32(_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
>>  break;
>>
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