Re: [U-Boot] FEC and EFI Simple Network

[Joe Hershberger]

Hi Patrick,

On Wed, Mar 28, 2018 at 4:54 PM, Fabio Estevam  wrote:
> Adding Joe in case he has some ideas.
>
> On Tue, Mar 27, 2018 at 9:12 AM, Patrick Wildt  wrote:
>> Hi,
>>
>> I have been debugging network issues when running an EFI Application
>> that uses the EFI Simple Network protocol on an i.MX6 machine (FEC).
>>
>> The symptom is that u-boot's (FEC) internal RX ring index is reset to 0,
>> while the controller is still at idx 3 (or something else).  This is
>> caused by the following circumstances:
>>
>> The Simple Network protocol offers methods like Start(), Stop(),
>> Initialize(), Shutdown(), Reset().  Also the protocol has a state.  The
>> states are Stopped, Started, Initialized.  The transition is as follows:
>>
>> Stopped ---Start()---> Started ---Initialize()--> Initialized
>>
>> Start() does some initialization, Initialize() allocates the TX/RX
>> descriptors and actually kicks off the network engine.
>>
>> So far, only Initialize() is implemented in our u-boot interface, and it
>> calls eth_init() which in the end calls fec_init().  Our network state
>> is _always_ Started.  This means that EFI Applications see that that the
>> state is Started and then call Initialize() to start the actual network
>> traffic.  There is no call to Stop()/Shutdown()/Reset() as it's supposed
>> to be in a sane state.
>>
>> In my case the FEC is already initialized since I booted using network
>> and the RX desc index is already non-zero.  Now the EFI Application sees
>> that the state is Started, calls Initialize() which makes u-boot call
>> eth_init() which then calls fec_init().
>>
>> fec_init() does not reset the controller so that the controller-internal
>> RX desc index is not reset to zero.  fec_init() calls fec_open() which
>> then resets the driver-internal RX desc index to zero.  Now they are out
>> of sync, boom.

Would it be reasonable for fec_init to use a state variable to keep
track of if it (and the HW) is already initialized and not call
fec_open in that case? Also, fec_halt would need to update that state
as well.

>>
>> This means that fec_init() without a previous fec_halt() breaks the
>> whole network if it was already running.  The Designware driver as used
>> by some sunxi platforms does a reset of the controller in the init
>> function.  Maybe calling fec_halt() at the start of fec_init() could be
>> a possible solution?
>>
>> Patrick
>>
>> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
>> index ff7ad91116..ba8bd9920d 100644
>> --- a/drivers/net/fec_mxc.c
>> +++ b/drivers/net/fec_mxc.c
>> @@ -522,6 +522,12 @@ static int fec_open(struct eth_device *edev)
>> return 0;
>>  }
>>
>> +#ifdef CONFIG_DM_ETH
>> +static void fecmxc_halt(struct udevice *dev);
>> +#else
>> +static void fec_halt(struct eth_device *dev);
>> +#endif
>> +
>>  #ifdef CONFIG_DM_ETH
>>  static int fecmxc_init(struct udevice *dev)
>>  #else
>> @@ -537,6 +543,15 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
>> u8 *i;
>> ulong addr;
>>
>> +#ifdef CONFIG_DM_ETH
>> +   fecmxc_halt(dev);
>> +#else
>> +   fec_halt(dev);
>> +#endif
>> +
>> +   writel(~FEC_TCNTRL_GTS & readl(>eth->x_cntrl),
>> +  >eth->x_cntrl);
>> +
>> /* Initialize MAC address */
>>  #ifdef CONFIG_DM_ETH
>> fecmxc_set_hwaddr(dev);
>> @@ -825,19 +840,12 @@ static int fec_recv(struct eth_device *dev)
>> }
>> if (ievent & FEC_IEVENT_HBERR) {
>> /* Heartbeat error */
>> -   writel(0x0001 | readl(>eth->x_cntrl),
>> +   writel(FEC_TCNTRL_GTS | readl(>eth->x_cntrl),
>>>eth->x_cntrl);
>> }
>> if (ievent & FEC_IEVENT_GRA) {
>> /* Graceful stop complete */
>> -   if (readl(>eth->x_cntrl) & 0x0001) {
>> -#ifdef CONFIG_DM_ETH
>> -   fecmxc_halt(dev);
>> -#else
>> -   fec_halt(dev);
>> -#endif
>> -   writel(~0x0001 & readl(>eth->x_cntrl),
>> -  >eth->x_cntrl);
>> +   if (readl(>eth->x_cntrl) & FEC_TCNTRL_GTS) {
>>  #ifdef CONFIG_DM_ETH
>> fecmxc_init(dev);
>>  #else
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Re: [U-Boot] [PATCH 4/4] phylib: Don't re-define CONFIG_PHY_MARVELL

[Joe Hershberger]

On Wed, Mar 28, 2018 at 7:38 AM, Mario Six  wrote:
> For certain boards, having CONFIG_PHY_MARVELL in the defconfig will
> result in a redefinition warning, because it is also defined in
> config_phylib_all_drivers.h.
>
> Add a check to stop this redefinition, but keep it for those boards that
> still don't have it in their defconfig.
>
> Signed-off-by: Mario Six 
> ---
>  include/config_phylib_all_drivers.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/include/config_phylib_all_drivers.h 
> b/include/config_phylib_all_drivers.h
> index 496ef58db0..264f220c5f 100644
> --- a/include/config_phylib_all_drivers.h
> +++ b/include/config_phylib_all_drivers.h
> @@ -15,7 +15,9 @@
>  #ifdef CONFIG_PHYLIB
>
>  #define CONFIG_PHY_VITESSE
> +#ifndef CONFIG_PHY_MARVELL
>  #define CONFIG_PHY_MARVELL
> +#endif

How many boards are we talking about? Why not just add it to the defconfig?

>  #define CONFIG_PHY_BROADCOM
>  #define CONFIG_PHY_DAVICOM
>  #define CONFIG_PHY_REALTEK
> --
> 2.16.1
>
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Re: [U-Boot] [PATCH 3/4] tsec: Fix reading phy registers from DT

[Joe Hershberger]

On Wed, Mar 28, 2018 at 7:38 AM, Mario Six  wrote:
> Bus translations should be applied when reading the address of the sgmii
> phy registers from the DT. Use ofnode_get_addr_index instead of the
> plain ofnode_read_u32_default to fix this.
>
> Signed-off-by: Mario Six 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 2/4] net: Initialize as many ethernet devices as possible

[Joe Hershberger]

On Wed, Mar 28, 2018 at 7:38 AM, Mario Six  wrote:
> On devices that have their first network interface provided by a FPGA,
> the initialization of further interfaces will fail if the FPGA is not
> yet programmed. This leads to problems during factory setup when the
> data is supposed to be loaded over secondary netowork interfaces.
>
> To avoid this, use the uclass_{first,next}_device_check functions to
> initialize as many ethernet devices as possible.
>
> Signed-off-by: Mario Six 

Seems reasonable.

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 1/4] net: Always align tx packets

[Joe Hershberger]

On Wed, Mar 28, 2018 at 7:38 AM, Mario Six  wrote:
> Make sure that TX packets are always cache-aligned.
>
> Signed-off-by: Mario Six 
> ---
>  net/arp.c  | 3 ++-
>  net/ping.c | 3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/net/arp.c b/net/arp.c
> index 4c79e09ccb..191434f5e2 100644
> --- a/net/arp.c
> +++ b/net/arp.c
> @@ -182,7 +182,8 @@ void arp_receive(struct ethernet_hdr *et, struct 
> ip_udp_hdr *ip, int len)
> (net_read_ip(>ar_spa).s_addr & net_netmask.s_addr))
> udelay(5000);
>  #endif
> -   net_send_packet((uchar *)et, eth_hdr_size + ARP_HDR_SIZE);
> +   memcpy(net_tx_packet, et, eth_hdr_size + ARP_HDR_SIZE);
> +   net_send_packet(net_tx_packet, eth_hdr_size + ARP_HDR_SIZE);

Rather than always incurring a copy here, why not have the device
driver that requires this do the copy?

> return;
>
> case ARPOP_REPLY:   /* arp reply */
> diff --git a/net/ping.c b/net/ping.c
> index 9508cf1160..db14209bf6 100644
> --- a/net/ping.c
> +++ b/net/ping.c
> @@ -107,7 +107,8 @@ void ping_receive(struct ethernet_hdr *et, struct 
> ip_udp_hdr *ip, int len)
> icmph->type = ICMP_ECHO_REPLY;
> icmph->checksum = 0;
> icmph->checksum = compute_ip_checksum(icmph, len - 
> IP_HDR_SIZE);
> -   net_send_packet((uchar *)et, eth_hdr_size + len);
> +   memcpy(net_tx_packet, et, eth_hdr_size + len);
> +   net_send_packet(net_tx_packet, eth_hdr_size + len);
> return;
>  /* default:
> return;*/
> --
> 2.16.1
>
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Re: [U-Boot] [PATCH] axi: ethernet: Added support for 64 bit addressing for axi-ethernet

[Joe Hershberger]

On Wed, Mar 28, 2018 at 9:35 AM, Michal Simek  wrote:
> From: Vipul Kumar 
>
> This patch uses writeq() function to enable greater than 32 bit
> addressing of axi-ethernet for the ZynqMP devices.
>
> Signed-off-by: Vipul Kumar 
> Signed-off-by: Michal Simek 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 2/3] fpga: zynqmp: Update zynqmp_load() as per latest xilfpga

[Joe Hershberger]

On Wed, Mar 28, 2018 at 9:30 AM, Michal Simek  wrote:
> From: Siva Durga Prasad Paladugu 
>
> Latest xilfpga expects to set BIT5 of flags for nonsecure
> bitsream and also expects length in bytes instead of words
> This patch does the same.
>
> Signed-off-by: Siva Durga Prasad Paladugu 
> Signed-off-by: Michal Simek 

Reviewed-by: Joe Hershberger 
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Re: [U-Boot] [PATCH] net: phy: xilinx_phy: Read phytype using property xlnx, phy-type

[Joe Hershberger]

On Wed, Mar 28, 2018 at 9:36 AM, Michal Simek  wrote:
> From: Siva Durga Prasad Paladugu 
>
> This patch reads phytype from property "xlnx,phy-type" instead
> od simply looking for "phy-type". This is to be inline with
> Linux and also fixes the issue of detecting it wrongly in
> u-boot.
>
> Signed-off-by: Siva Durga Prasad Paladugu 
> Signed-off-by: Michal Simek 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH V3 6/6] net: fec: Fix issue in DM probe timeout

[Joe Hershberger]

On Wed, Mar 28, 2018 at 7:54 AM, Peng Fan  wrote:
> From: Ye Li 
>
> Since the probe function has changed to reset FEC controller prior than
> setup PHY. If reset FEC controller timeout, the priv->phydev is not
> initialized, so can't free it.
>
> Signed-off-by: Ye Li 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 4/9] net: Improve menu options and help for BOOTP options

[Chris Packham]

On Thu, Mar 29, 2018 at 4:18 PM, Chris Packham  wrote:
> On Thu, Mar 29, 2018 at 9:51 AM, Joe Hershberger  
> wrote:
>> The options were pretty unhelpful, so improve them some.
>>
>> Signed-off-by: Joe Hershberger 
>> ---
>
> Couple of questions below. But with or without changes
>
> Reviewed-by: Chris Packham 
>
>>
>>  cmd/Kconfig | 19 ++-
>>  1 file changed, 14 insertions(+), 5 deletions(-)
>>
>> diff --git a/cmd/Kconfig b/cmd/Kconfig
>> index 7ef9501..76fd111 100644
>> --- a/cmd/Kconfig
>> +++ b/cmd/Kconfig
>> @@ -1031,23 +1031,32 @@ config CMD_DHCP
>>   Boot image via network using DHCP/TFTP protocol
>>
>>  config BOOTP_BOOTPATH
>> -   bool "Enable BOOTP BOOTPATH"
>> +   bool "Request & store 'rootpath' from BOOTP/DHCP server"
>> depends on CMD_BOOTP
>> +   help
>> + Even though the config is called BOOTP_BOOTPATH, it stores the
>> + path in the variable 'rootpath'.
>>
>>  config BOOTP_DNS
>> -   bool "Enable bootp DNS"
>> +   bool "Request & store 'dnsip' from BOOTP/DHCP server"
>> depends on CMD_BOOTP
>> +   help
>> + The primary DNS server is stored as 'dnsip'. If two servers are
>> + returned, you must set BOOTP_DNS2 to store that second server IP
>> + also.
>>
>>  config BOOTP_GATEWAY
>> -   bool "Enable BOOTP gateway"
>> +   bool "Request & store 'gatewayip' from BOOTP/DHCP server"
>> depends on CMD_BOOTP
>
> Should this be default y? It would be pretty annoying if you were to
> turn on bootp/dhcp and forget to enable this as well.
>

Never-mind. Should have looked at the whole series :)

>>
>>  config BOOTP_HOSTNAME
>> -   bool "Enable BOOTP hostname"
>> +   bool "Request & store 'hostname' from BOOTP/DHCP server"
>> depends on CMD_BOOTP
>> +   help
>> + The name may or may not be qualified with the local domain name.
>>
>>  config BOOTP_SUBNETMASK
>> -   bool "Enable BOOTP subnetmask"
>> +   bool "Request & store 'netmask' from BOOTP/DHCP server"
>> depends on CMD_BOOTP
>
> Should this be default y?
>
>>
>>  config BOOTP_PXE
>> --
>> 1.7.11.5
>>
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Re: [U-Boot] [PATCH 5/9] net: Add the BOOTP_DNS2 option to Kconfig

[Chris Packham]

On Thu, Mar 29, 2018 at 9:51 AM, Joe Hershberger  wrote:
> Commit 3b3ea2c56ec4bc5 ("Kconfig: cmd: Make networking command dependent on 
> NET")
> removed the help documentation from the README but didn't add it back to 
> Kconfig.
>
> Signed-off-by: Joe Hershberger 

Reviewed-by: Chris Packham 

> ---
>
>  cmd/Kconfig | 11 +++
>  1 file changed, 11 insertions(+)
>
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 76fd111..db75759 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -1045,6 +1045,17 @@ config BOOTP_DNS
>   returned, you must set BOOTP_DNS2 to store that second server IP
>   also.
>
> +config BOOTP_DNS2
> +   bool "Store 'dnsip2' from BOOTP/DHCP server"
> +   depends on BOOTP_DNS
> +   help
> + If a DHCP client requests the DNS server IP from a DHCP server,
> + it is possible that more than one DNS serverip is offered to the
> + client. If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
> + server IP will be stored in the additional environment
> + variable "dnsip2". The first DNS serverip is always
> + stored in the variable "dnsip", when BOOTP_DNS is defined.
> +
>  config BOOTP_GATEWAY
> bool "Request & store 'gatewayip' from BOOTP/DHCP server"
> depends on CMD_BOOTP
> --
> 1.7.11.5
>
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Re: [U-Boot] [PATCH 4/9] net: Improve menu options and help for BOOTP options

[Chris Packham]

On Thu, Mar 29, 2018 at 9:51 AM, Joe Hershberger  wrote:
> The options were pretty unhelpful, so improve them some.
>
> Signed-off-by: Joe Hershberger 
> ---

Couple of questions below. But with or without changes

Reviewed-by: Chris Packham 

>
>  cmd/Kconfig | 19 ++-
>  1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 7ef9501..76fd111 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -1031,23 +1031,32 @@ config CMD_DHCP
>   Boot image via network using DHCP/TFTP protocol
>
>  config BOOTP_BOOTPATH
> -   bool "Enable BOOTP BOOTPATH"
> +   bool "Request & store 'rootpath' from BOOTP/DHCP server"
> depends on CMD_BOOTP
> +   help
> + Even though the config is called BOOTP_BOOTPATH, it stores the
> + path in the variable 'rootpath'.
>
>  config BOOTP_DNS
> -   bool "Enable bootp DNS"
> +   bool "Request & store 'dnsip' from BOOTP/DHCP server"
> depends on CMD_BOOTP
> +   help
> + The primary DNS server is stored as 'dnsip'. If two servers are
> + returned, you must set BOOTP_DNS2 to store that second server IP
> + also.
>
>  config BOOTP_GATEWAY
> -   bool "Enable BOOTP gateway"
> +   bool "Request & store 'gatewayip' from BOOTP/DHCP server"
> depends on CMD_BOOTP

Should this be default y? It would be pretty annoying if you were to
turn on bootp/dhcp and forget to enable this as well.

>
>  config BOOTP_HOSTNAME
> -   bool "Enable BOOTP hostname"
> +   bool "Request & store 'hostname' from BOOTP/DHCP server"
> depends on CMD_BOOTP
> +   help
> + The name may or may not be qualified with the local domain name.
>
>  config BOOTP_SUBNETMASK
> -   bool "Enable BOOTP subnetmask"
> +   bool "Request & store 'netmask' from BOOTP/DHCP server"
> depends on CMD_BOOTP

Should this be default y?

>
>  config BOOTP_PXE
> --
> 1.7.11.5
>
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Re: [U-Boot] [PATCH 3/9] net: Move the DHCP command below the BOOTP command

[Chris Packham]

On Thu, Mar 29, 2018 at 9:51 AM, Joe Hershberger  wrote:
> Move DHCP to directly follow BOOTP so that Kconfig can show the
> dependency as a hierarchy.
>
> Signed-off-by: Joe Hershberger 
> ---

I never quite understood the distinction between bootp and dhcp. I
know technically bootp was an earlier version of what eventually
became bootp but isn't dhcp fully backwards compatible with the bootp
protocol? Code-wise it looks like bootp is dhcp without the option
processing. Do we save much by keeping the separate?

Regardless ...

Reviewed-by: Chris Packham 

>
>  cmd/Kconfig | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index d714f73..7ef9501 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -1024,6 +1024,12 @@ config CMD_BOOTP
> help
>   bootp - boot image via network using BOOTP/TFTP protocol
>
> +config CMD_DHCP
> +   bool "dhcp"
> +   depends on CMD_BOOTP
> +   help
> + Boot image via network using DHCP/TFTP protocol
> +
>  config BOOTP_BOOTPATH
> bool "Enable BOOTP BOOTPATH"
> depends on CMD_BOOTP
> @@ -1097,12 +1103,6 @@ config CMD_RARP
> help
>   Boot image via network using RARP/TFTP protocol
>
> -config CMD_DHCP
> -   bool "dhcp"
> -   depends on CMD_BOOTP
> -   help
> - Boot image via network using DHCP/TFTP protocol
> -
>  config CMD_PXE
> bool "pxe"
> select MENU
> --
> 1.7.11.5
>
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Re: [U-Boot] [PATCH 2/9] net: Move net command options to the cmd menu

[Chris Packham]

On Thu, Mar 29, 2018 at 9:51 AM, Joe Hershberger  wrote:
> Options that controlled the tftp and bootp commands depended on their
> commands, but lived in the net menu.
>
> Move them so they are in a consistent location.
>
> Signed-off-by: Joe Hershberger 
> ---

Reviewed-by: Chris Packham 

>  cmd/Kconfig | 50 ++
>  net/Kconfig | 50 --
>  2 files changed, 50 insertions(+), 50 deletions(-)
>
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index f2a12ce..d714f73 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -1024,6 +1024,45 @@ config CMD_BOOTP
> help
>   bootp - boot image via network using BOOTP/TFTP protocol
>
> +config BOOTP_BOOTPATH
> +   bool "Enable BOOTP BOOTPATH"
> +   depends on CMD_BOOTP
> +
> +config BOOTP_DNS
> +   bool "Enable bootp DNS"
> +   depends on CMD_BOOTP
> +
> +config BOOTP_GATEWAY
> +   bool "Enable BOOTP gateway"
> +   depends on CMD_BOOTP
> +
> +config BOOTP_HOSTNAME
> +   bool "Enable BOOTP hostname"
> +   depends on CMD_BOOTP
> +
> +config BOOTP_SUBNETMASK
> +   bool "Enable BOOTP subnetmask"
> +   depends on CMD_BOOTP
> +
> +config BOOTP_PXE
> +   bool "Enable BOOTP PXE"
> +   depends on CMD_BOOTP
> +
> +config BOOTP_PXE_CLIENTARCH
> +   hex
> +   depends on CMD_BOOTP
> +   default 0x16 if ARM64
> +   default 0x15 if ARM
> +   default 0 if X86
> +
> +config BOOTP_VCI_STRING
> +   string
> +   depends on CMD_BOOTP
> +   default "U-Boot.armv7" if CPU_V7 || CPU_V7M
> +   default "U-Boot.armv8" if ARM64
> +   default "U-Boot.arm" if ARM
> +   default "U-Boot"
> +
>  config CMD_TFTPBOOT
> bool "tftpboot"
> default y
> @@ -1042,6 +1081,17 @@ config CMD_TFTPSRV
> help
>   Act as a TFTP server and boot the first received file
>
> +config NET_TFTP_VARS
> +   bool "Control TFTP timeout and count through environment"
> +   depends on CMD_TFTPBOOT
> +   default y
> +   help
> + If set, allows controlling the TFTP timeout through the
> + environment variable tftptimeout, and the TFTP maximum
> + timeout count through the variable tftptimeoutcountmax.
> + If unset, timeout and maximum are hard-defined as 1 second
> + and 10 timouts per TFTP transfer.
> +
>  config CMD_RARP
> bool "rarpboot"
> help
> diff --git a/net/Kconfig b/net/Kconfig
> index d421a34..f2363e5 100644
> --- a/net/Kconfig
> +++ b/net/Kconfig
> @@ -22,54 +22,4 @@ config NETCONSOLE
>   Support the 'nc' input/output device for networked console.
>   See README.NetConsole for details.
>
> -config NET_TFTP_VARS
> -   bool "Control TFTP timeout and count through environment"
> -   depends on CMD_TFTPBOOT
> -   default y
> -   help
> - If set, allows controlling the TFTP timeout through the
> - environment variable tftptimeout, and the TFTP maximum
> - timeout count through the variable tftptimeoutcountmax.
> - If unset, timeout and maximum are hard-defined as 1 second
> - and 10 timouts per TFTP transfer.
> -
> -config BOOTP_BOOTPATH
> -   bool "Enable BOOTP BOOTPATH"
> -   depends on CMD_BOOTP
> -
> -config BOOTP_DNS
> -   bool "Enable bootp DNS"
> -   depends on CMD_BOOTP
> -
> -config BOOTP_GATEWAY
> -   bool "Enable BOOTP gateway"
> -   depends on CMD_BOOTP
> -
> -config BOOTP_HOSTNAME
> -   bool "Enable BOOTP hostname"
> -   depends on CMD_BOOTP
> -
> -config BOOTP_PXE
> -   bool "Enable BOOTP PXE"
> -   depends on CMD_BOOTP
> -
> -config BOOTP_SUBNETMASK
> -   bool "Enable BOOTP subnetmask"
> -   depends on CMD_BOOTP
> -
> -config BOOTP_PXE_CLIENTARCH
> -   hex
> -   depends on CMD_BOOTP
> -default 0x16 if ARM64
> -default 0x15 if ARM
> -default 0 if X86
> -
> -config BOOTP_VCI_STRING
> -   string
> -   depends on CMD_BOOTP
> -   default "U-Boot.armv7" if CPU_V7 || CPU_V7M
> -   default "U-Boot.armv8" if ARM64
> -   default "U-Boot.arm" if ARM
> -   default "U-Boot"
> -
>  endif   # if NET
> --
> 1.7.11.5
>
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Re: [U-Boot] [PATCH 1/9] net: Make CMD_NET a menuconfig

[Chris Packham]

On Thu, Mar 29, 2018 at 9:51 AM, Joe Hershberger  wrote:
> Previously, CMD_NET was an alias for 2 commands (bootp and tftpboot) and
> they we not able to be disabled. Separate out those 2 commands and move
> CMD_NET up to the menu level, which more accurately represents the code.
>
> Signed-off-by: Joe Hershberger 
> ---

Reviewed-by: Chris Packham 

>
>  cmd/Kconfig  | 25 +
>  cmd/net.c|  4 
>  net/Kconfig  | 19 +--
>  net/Makefile |  4 ++--
>  4 files changed, 32 insertions(+), 20 deletions(-)
>
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 136836d..f2a12ce 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -1010,25 +1010,35 @@ config CMD_SETEXPR
>
>  endmenu
>
> -menu "Network commands"
> -
>  if NET
>
> -config CMD_NET
> -   bool "bootp, tftpboot"
> +menuconfig CMD_NET
> +   bool "Network commands"
> +   default y
> +
> +if CMD_NET
> +
> +config CMD_BOOTP
> +   bool "bootp"
> default y
> help
> - Network commands.
>   bootp - boot image via network using BOOTP/TFTP protocol
> +
> +config CMD_TFTPBOOT
> +   bool "tftpboot"
> +   default y
> +   help
>   tftpboot - boot image via network using TFTP protocol
>
>  config CMD_TFTPPUT
> bool "tftp put"
> +   depends on CMD_TFTPBOOT
> help
>   TFTP put command, for uploading files to a server
>
>  config CMD_TFTPSRV
> bool "tftpsrv"
> +   depends on CMD_TFTPBOOT
> help
>   Act as a TFTP server and boot the first received file
>
> @@ -1039,13 +1049,12 @@ config CMD_RARP
>
>  config CMD_DHCP
> bool "dhcp"
> -   depends on CMD_NET
> +   depends on CMD_BOOTP
> help
>   Boot image via network using DHCP/TFTP protocol
>
>  config CMD_PXE
> bool "pxe"
> -   depends on CMD_NET
> select MENU
> help
>   Boot image via network using PXE protocol
> @@ -1096,7 +1105,7 @@ config CMD_ETHSW
>
>  endif
>
> -endmenu
> +endif
>
>  menu "Misc commands"
>
> diff --git a/cmd/net.c b/cmd/net.c
> index d7c776a..67888d4 100644
> --- a/cmd/net.c
> +++ b/cmd/net.c
> @@ -14,6 +14,7 @@
>
>  static int netboot_common(enum proto_t, cmd_tbl_t *, int, char * const []);
>
> +#ifdef CONFIG_CMD_BOOTP
>  static int do_bootp(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
> argv[])
>  {
> return netboot_common(BOOTP, cmdtp, argc, argv);
> @@ -24,7 +25,9 @@ U_BOOT_CMD(
> "boot image via network using BOOTP/TFTP protocol",
> "[loadAddress] [[hostIPaddr:]bootfilename]"
>  );
> +#endif
>
> +#ifdef CONFIG_CMD_TFTPBOOT
>  int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>  {
> int ret;
> @@ -40,6 +43,7 @@ U_BOOT_CMD(
> "boot image via network using TFTP protocol",
> "[loadAddress] [[hostIPaddr:]bootfilename]"
>  );
> +#endif
>
>  #ifdef CONFIG_CMD_TFTPPUT
>  static int do_tftpput(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
> argv[])
> diff --git a/net/Kconfig b/net/Kconfig
> index 143c441..d421a34 100644
> --- a/net/Kconfig
> +++ b/net/Kconfig
> @@ -24,7 +24,7 @@ config NETCONSOLE
>
>  config NET_TFTP_VARS
> bool "Control TFTP timeout and count through environment"
> -   depends on CMD_NET
> +   depends on CMD_TFTPBOOT
> default y
> help
>   If set, allows controlling the TFTP timeout through the
> @@ -35,39 +35,38 @@ config NET_TFTP_VARS
>
>  config BOOTP_BOOTPATH
> bool "Enable BOOTP BOOTPATH"
> -   depends on CMD_NET
> +   depends on CMD_BOOTP
>
>  config BOOTP_DNS
> bool "Enable bootp DNS"
> -   depends on CMD_NET
> +   depends on CMD_BOOTP
>
>  config BOOTP_GATEWAY
> bool "Enable BOOTP gateway"
> -   depends on CMD_NET
> +   depends on CMD_BOOTP
>
>  config BOOTP_HOSTNAME
> bool "Enable BOOTP hostname"
> -   depends on CMD_NET
> +   depends on CMD_BOOTP
>
>  config BOOTP_PXE
> bool "Enable BOOTP PXE"
> -   depends on CMD_NET
> +   depends on CMD_BOOTP
>
>  config BOOTP_SUBNETMASK
> bool "Enable BOOTP subnetmask"
> -   depends on CMD_NET
> -   depends on CMD_NET
> +   depends on CMD_BOOTP
>
>  config BOOTP_PXE_CLIENTARCH
> hex
> -   depends on CMD_NET
> +   depends on CMD_BOOTP
>  default 0x16 if ARM64
>  default 0x15 if ARM
>  default 0 if X86
>
>  config BOOTP_VCI_STRING
> string
> -   depends on CMD_NET
> +   depends on CMD_BOOTP
> default "U-Boot.armv7" if CPU_V7 || CPU_V7M
> default "U-Boot.armv8" if ARM64
> default "U-Boot.arm" if ARM
> diff --git a/net/Makefile b/net/Makefile
> index ae54eee..ed102ec 100644
> --- a/net/Makefile
> +++ b/net/Makefile
> @@ -9,7 +9,7 @@
>
>  obj-y += checksum.o
>  obj-$(CONFIG_CMD_NET)  += arp.o
> -obj-$(CONFIG_CMD_NET)  += bootp.o
> 

[U-Boot] Marvell Armada-38x DDR training code

[Chris Packham]

Hi,

I've posted a couple of improvements to the in-tree ddr training code
but we've known for a while that u-boot proper is a bit behind
Marvell's code for ddr training. And now I really do have a problem on
my board that is fixed by using Marvell's code.

Yesterday I got hold of patches from Marvell for their "standalone"
mv_ddr code. It's under a tri-license Proprietary/GPL/BSD-3c so I've
exercised my rights under the GPL and made it available on github
https://github.com/cpackham/mv_ddr.git

This standalone code looks the most u-boot-ish of any code I've gotten
out of Marvell. In fact I suspect it was based on the work that Stefan
did initially.

The question how do I get this upstream I could submit 475 odd patches
preserving the authorship, I could submit one big roll-up of changes.
Neither option is particularly appealing. It would be hard to narrow
down the subset of changes that fixes my particular problem.

Any suggestions on how to proceed?
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[U-Boot] [PATCH] riscv: ae250: Support DT provided by the board at runtime

[Andes]

From: Rick Chen 

Enable CONFIG_OF_BOAD to support delivery dtb to u-boot
at run time instead of embedded.

There are two methods to delivery dtb.
 1 Pass from loader:
   When u-boot boot from RAM, gdb or loader can pass dtb
   via a2 to u-boot dynamically. Of course gdb or loader
   shall be in charge of dtb delivery.

 2 Configure CONFIG_SYS_FDT_BASE:
   It can be configured as RAM or ROM base statically,
   no mater u-boot boot from RAM or ROM.
   If it was configured as ROM base, dtb can be burned
   into ROM(spi flash) by spi driver.

Meanwhile remove CONFIG_SKIP_LOWLEVEL_INIT which is
useless in nx25-ae250 configuration.

Signed-off-by: Rick Chen 
Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/nx25/start.S |  2 ++
 board/AndesTech/nx25-ae250/nx25-ae250.c |  9 +
 configs/nx25-ae250_defconfig|  1 +
 include/configs/nx25-ae250.h| 12 +++-
 4 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/cpu/nx25/start.S b/arch/riscv/cpu/nx25/start.S
index 6a07663..cd0a663 100644
--- a/arch/riscv/cpu/nx25/start.S
+++ b/arch/riscv/cpu/nx25/start.S
@@ -45,6 +45,8 @@ trap_vector:
 
 .global trap_entry
 handle_reset:
+   li t0, CONFIG_SYS_SDRAM_BASE
+   SREG a2, 0(t0)
la t0, trap_entry
csrw mtvec, t0
csrwi mstatus, 0
diff --git a/board/AndesTech/nx25-ae250/nx25-ae250.c 
b/board/AndesTech/nx25-ae250/nx25-ae250.c
index a965218..6e31be3 100644
--- a/board/AndesTech/nx25-ae250/nx25-ae250.c
+++ b/board/AndesTech/nx25-ae250/nx25-ae250.c
@@ -64,3 +64,12 @@ ulong board_flash_get_legacy(ulong base, int banknum, 
flash_info_t *info)
 {
return 0;
 }
+
+void *board_fdt_blob_setup(void)
+{
+   void **ptr = (void *)CONFIG_SYS_SDRAM_BASE;
+   if (fdt_magic(*ptr) == FDT_MAGIC)
+   return (void *)*ptr;
+
+   return (void *)CONFIG_SYS_FDT_BASE;
+}
diff --git a/configs/nx25-ae250_defconfig b/configs/nx25-ae250_defconfig
index eb41d71..4f9bd58 100644
--- a/configs/nx25-ae250_defconfig
+++ b/configs/nx25-ae250_defconfig
@@ -16,6 +16,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
diff --git a/include/configs/nx25-ae250.h b/include/configs/nx25-ae250.h
index 3c888fd..0e4c431 100644
--- a/include/configs/nx25-ae250.h
+++ b/include/configs/nx25-ae250.h
@@ -11,18 +11,9 @@
 /*
  * CPU and Board Configuration Options
  */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_SERVERIP
 
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#ifdef CONFIG_OF_CONTROL
-#undef CONFIG_OF_SEPARATE
-#define CONFIG_OF_EMBED
-#endif
-#endif
-
 /*
  * Miscellaneous configurable options
  */
@@ -50,6 +41,9 @@
  */
 #define CONFIG_SYS_MALLOC_LEN   (512 << 10)
 
+/* DT blob (fdt) address */
+#define CONFIG_SYS_FDT_BASE0x000f
+
 /*
  * Physical Memory Map
  */
-- 
2.7.4

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[U-Boot] [PATCH] timer: Add High Precision Event Timers (HPET) support

[Ivan Gorinov]

Adding HPET as an alternative timer for x86 (default is TSC).
HPET main counter has constant clock frequency, calibration is not required.
This change also makes TSC timer driver optional on x86 platforms.
If X86_TSC is disabled, early timer functions are provided by HPET.

HPET can be selected as the tick timer in the Device Tree "chosen" node:

  /include/ "hpet.dtsi"

  chosen {
tick-timer = "/hpet0";
  };

Signed-off-by: Ivan Gorinov 
---
 arch/Kconfig   |   2 +-
 arch/x86/dts/hpet.dtsi |   7 ++
 drivers/timer/Kconfig  |   6 ++
 drivers/timer/Makefile |   1 +
 drivers/timer/hpet_timer.c | 197 +
 5 files changed, 212 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/dts/hpet.dtsi
 create mode 100644 drivers/timer/hpet_timer.c

diff --git a/arch/Kconfig b/arch/Kconfig
index e599e7a..37dabae 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -104,7 +104,7 @@ config X86
select DM_PCI
select PCI
select TIMER
-   select X86_TSC_TIMER
+   imply X86_TSC_TIMER
imply BLK
imply DM_ETH
imply DM_GPIO
diff --git a/arch/x86/dts/hpet.dtsi b/arch/x86/dts/hpet.dtsi
new file mode 100644
index 000..037dc7e
--- /dev/null
+++ b/arch/x86/dts/hpet.dtsi
@@ -0,0 +1,7 @@
+/ {
+   hpet0: hpet@fed0 {
+   compatible = "hpet-x86";
+   u-boot,dm-pre-reloc;
+   reg = <0xfed0 0x1000>;
+   };
+};
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 2c96896..72ae6c5 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -65,6 +65,12 @@ config X86_TSC_TIMER
help
  Select this to enable Time-Stamp Counter (TSC) timer for x86.
 
+config HPET_TIMER
+   bool "High Precision Event Timers (HPET) support"
+   depends on TIMER && X86
+   help
+ Select this to enable High Precision Event Timers (HPET) for x86.
+
 config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index a6e7832..557fecc 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -8,6 +8,7 @@ obj-y += timer-uclass.o
 obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
 obj-$(CONFIG_SANDBOX_TIMER)+= sandbox_timer.o
 obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
+obj-$(CONFIG_HPET_TIMER)   += hpet_timer.o
 obj-$(CONFIG_OMAP_TIMER)   += omap-timer.o
 obj-$(CONFIG_AST_TIMER)+= ast_timer.o
 obj-$(CONFIG_STI_TIMER)+= sti-timer.o
diff --git a/drivers/timer/hpet_timer.c b/drivers/timer/hpet_timer.c
new file mode 100644
index 000..66462a6
--- /dev/null
+++ b/drivers/timer/hpet_timer.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HPET_PERIOD_REG 0x004
+#define HPET_CONFIG_REG 0x010
+#define HPET_MAIN_COUNT_L 0x0f0
+#define HPET_MAIN_COUNT_H 0x0f4
+
+#define HPET_MAX_PERIOD 1
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct hpet_timer_priv {
+   void *regs;
+};
+
+static inline u32 freq_hz(u32 period)
+{
+   u64 d = 1000ull;
+
+   d += period / 2;
+
+   return d / period;
+}
+
+static int hpet_timer_get_count(struct udevice *dev, u64 *count)
+{
+   struct hpet_timer_priv *priv = dev_get_priv(dev);
+   u64 now_tick;
+   u32 tl, th, th0;
+
+   th = readl(priv->regs + HPET_MAIN_COUNT_H);
+   do {
+   th0 = th;
+   tl = readl(priv->regs + HPET_MAIN_COUNT_L);
+   th = readl(priv->regs + HPET_MAIN_COUNT_H);
+   } while (th != th0);
+
+   now_tick = th;
+   now_tick <<= 32;
+   now_tick |= tl;
+
+   *count = now_tick;
+
+   return 0;
+}
+
+static int hpet_timer_probe(struct udevice *dev)
+{
+   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct hpet_timer_priv *priv = dev_get_priv(dev);
+   u32 period, config;
+
+   period = readl(priv->regs + HPET_PERIOD_REG);
+   if (period == 0)
+   return -ENODEV;
+   if (period > HPET_MAX_PERIOD)
+   return -ENODEV;
+
+   config = readl(priv->regs + HPET_CONFIG_REG);
+   config &= ~1;
+   writel(config, priv->regs + HPET_CONFIG_REG);
+   writel(0, priv->regs + HPET_MAIN_COUNT_L);
+   writel(0, priv->regs + HPET_MAIN_COUNT_H);
+   config |= 1;
+   writel(config, priv->regs + HPET_CONFIG_REG);
+
+   uc_priv->clock_rate = freq_hz(period);
+
+   return 0;
+}
+
+#ifndef CONFIG_X86_TSC_TIMER
+
+#define EARLY_HPET_BASE 0xfed0
+
+unsigned long notrace timer_early_get_rate(void)
+{
+   void *regs = (void *) EARLY_HPET_BASE;
+   u32 period, config;
+
+   period = readl(regs + HPET_PERIOD_REG);
+   if (period == 0)
+   return -ENODEV;
+   if (period > HPET_MAX_PERIOD)
+ 

Re: [U-Boot] FEC and EFI Simple Network

[Fabio Estevam]

Adding Joe in case he has some ideas.

On Tue, Mar 27, 2018 at 9:12 AM, Patrick Wildt  wrote:
> Hi,
>
> I have been debugging network issues when running an EFI Application
> that uses the EFI Simple Network protocol on an i.MX6 machine (FEC).
>
> The symptom is that u-boot's (FEC) internal RX ring index is reset to 0,
> while the controller is still at idx 3 (or something else).  This is
> caused by the following circumstances:
>
> The Simple Network protocol offers methods like Start(), Stop(),
> Initialize(), Shutdown(), Reset().  Also the protocol has a state.  The
> states are Stopped, Started, Initialized.  The transition is as follows:
>
> Stopped ---Start()---> Started ---Initialize()--> Initialized
>
> Start() does some initialization, Initialize() allocates the TX/RX
> descriptors and actually kicks off the network engine.
>
> So far, only Initialize() is implemented in our u-boot interface, and it
> calls eth_init() which in the end calls fec_init().  Our network state
> is _always_ Started.  This means that EFI Applications see that that the
> state is Started and then call Initialize() to start the actual network
> traffic.  There is no call to Stop()/Shutdown()/Reset() as it's supposed
> to be in a sane state.
>
> In my case the FEC is already initialized since I booted using network
> and the RX desc index is already non-zero.  Now the EFI Application sees
> that the state is Started, calls Initialize() which makes u-boot call
> eth_init() which then calls fec_init().
>
> fec_init() does not reset the controller so that the controller-internal
> RX desc index is not reset to zero.  fec_init() calls fec_open() which
> then resets the driver-internal RX desc index to zero.  Now they are out
> of sync, boom.
>
> This means that fec_init() without a previous fec_halt() breaks the
> whole network if it was already running.  The Designware driver as used
> by some sunxi platforms does a reset of the controller in the init
> function.  Maybe calling fec_halt() at the start of fec_init() could be
> a possible solution?
>
> Patrick
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index ff7ad91116..ba8bd9920d 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -522,6 +522,12 @@ static int fec_open(struct eth_device *edev)
> return 0;
>  }
>
> +#ifdef CONFIG_DM_ETH
> +static void fecmxc_halt(struct udevice *dev);
> +#else
> +static void fec_halt(struct eth_device *dev);
> +#endif
> +
>  #ifdef CONFIG_DM_ETH
>  static int fecmxc_init(struct udevice *dev)
>  #else
> @@ -537,6 +543,15 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
> u8 *i;
> ulong addr;
>
> +#ifdef CONFIG_DM_ETH
> +   fecmxc_halt(dev);
> +#else
> +   fec_halt(dev);
> +#endif
> +
> +   writel(~FEC_TCNTRL_GTS & readl(>eth->x_cntrl),
> +  >eth->x_cntrl);
> +
> /* Initialize MAC address */
>  #ifdef CONFIG_DM_ETH
> fecmxc_set_hwaddr(dev);
> @@ -825,19 +840,12 @@ static int fec_recv(struct eth_device *dev)
> }
> if (ievent & FEC_IEVENT_HBERR) {
> /* Heartbeat error */
> -   writel(0x0001 | readl(>eth->x_cntrl),
> +   writel(FEC_TCNTRL_GTS | readl(>eth->x_cntrl),
>>eth->x_cntrl);
> }
> if (ievent & FEC_IEVENT_GRA) {
> /* Graceful stop complete */
> -   if (readl(>eth->x_cntrl) & 0x0001) {
> -#ifdef CONFIG_DM_ETH
> -   fecmxc_halt(dev);
> -#else
> -   fec_halt(dev);
> -#endif
> -   writel(~0x0001 & readl(>eth->x_cntrl),
> -  >eth->x_cntrl);
> +   if (readl(>eth->x_cntrl) & FEC_TCNTRL_GTS) {
>  #ifdef CONFIG_DM_ETH
> fecmxc_init(dev);
>  #else
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Re: [U-Boot] [U-Boot,2/3] rockchip: mmc: update MAINTAINERS

[Philipp Tomsich]

> The Rockchip-specific wrappers to the DW-MMC and the SDHCI driver
> were not covered as part of what's maintained by the architecture
> maintainers.  Add them here.
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  MAINTAINERS | 2 ++
>  1 file changed, 2 insertions(+)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-Boot,3/3] rockchip: sdhci: support 8bit bus-width

[Philipp Tomsich]

> The Rockchip-specific SDHCI wrapper does not process the 'bus-width'
> property in the SDHCI node. Consequently, the bus is always kept in
> 4bit mode, even if 8bit wide operation is available, supported and
> requested in the DTS.
> 
> This change adds processing of the 'bus-width' property and sets the
> host capability flag for an 8bit wide bus, if set to 8. As the logic
> in sdhci.c does not support clearing the 4bit capability, we assume
> that 4bit operation is always supported.
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  drivers/mmc/rockchip_sdhci.c | 8 
>  1 file changed, 8 insertions(+)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-Boot, 1/3] rockchip: defconfig: puma-rk3399: enable DMA for SDHCI controller

[Philipp Tomsich]

> For the RK3399-Q7, we have a fast eMMC connected in an 8 bit wide
> configuration to the SDHCI controller (sdhci@fe33).  Enable DMA
> within the SDHCI driver to get the best performance out of it.
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  configs/puma-rk3399_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-Boot, 2/2] video: rk3399_mipi: Combine NULL check into IS_ERR_OR_NULL()

[Philipp Tomsich]

> Signed-off-by: Punit Agrawal 
> Acked-by: Philipp Tomsich 
> Reviewed-by: Philipp Tomsich 
> ---
>  drivers/video/rockchip/rk3399_mipi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-Boot, 1/2] video: rk3288_mipi: Combine NULL check into IS_ERR_OR_NULL()

[Philipp Tomsich]

> Signed-off-by: Punit Agrawal 
> Acked-by: Philipp Tomsich 
> Reviewed-by: Philipp Tomsich 
> ---
>  drivers/video/rockchip/rk3288_mipi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-Boot, 2/2] video: rk3399_mipi: Combine NULL check into IS_ERR_OR_NULL()

[Philipp Tomsich]

> Signed-off-by: Punit Agrawal 
> ---
>  drivers/video/rockchip/rk3399_mipi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, 1/2] video: rk3288_mipi: Combine NULL check into IS_ERR_OR_NULL()

[Philipp Tomsich]

> Signed-off-by: Punit Agrawal 
> ---
>  drivers/video/rockchip/rk3288_mipi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, 2/2] video: rk3399_mipi: Combine NULL check into IS_ERR_OR_NULL()

[Philipp Tomsich]

> Signed-off-by: Punit Agrawal 
> ---
>  drivers/video/rockchip/rk3399_mipi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, 1/2] video: rk3288_mipi: Combine NULL check into IS_ERR_OR_NULL()

[Philipp Tomsich]

> Signed-off-by: Punit Agrawal 
> ---
>  drivers/video/rockchip/rk3288_mipi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] rockchip: rk3399: set fdtfile

[Philipp Tomsich]

> Signed-off-by: Mark Kettenis 
> Acked-by: Philipp Tomsich 
> Tested-by: Klaus Goger 
> Reviewed-by: Philipp Tomsich 
> ---
>  include/configs/rk3399_common.h | 1 +
>  1 file changed, 1 insertion(+)
> 

Applied to u-boot-rockchip, thanks!
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[U-Boot] [PATCH 6/9] net: Improve BOOTP PXE config option

[Joe Hershberger]

Improve the documentation and correct the listed dependencies.

Signed-off-by: Joe Hershberger 
---

 cmd/Kconfig | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index db75759..cc059c4 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1071,12 +1071,14 @@ config BOOTP_SUBNETMASK
depends on CMD_BOOTP
 
 config BOOTP_PXE
-   bool "Enable BOOTP PXE"
-   depends on CMD_BOOTP
+   bool "Send PXE client arch to BOOTP/DHCP server"
+   depends on CMD_BOOTP && CMD_PXE
+   help
+ Supported for ARM, ARM64, and x86 for now.
 
 config BOOTP_PXE_CLIENTARCH
hex
-   depends on CMD_BOOTP
+   depends on BOOTP_PXE
default 0x16 if ARM64
default 0x15 if ARM
default 0 if X86
-- 
1.7.11.5

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[U-Boot] [PATCH 9/9] Revert "Kconfig: cmd: Make networking command dependent on NET"

[Joe Hershberger]

This reverts the parts of commit 3b3ea2c56ec4bc5588281fd103c744e608f8b25c
where it changed the EFI dependency on NET.

Signed-off-by: Joe Hershberger 

---

 Kconfig  | 2 +-
 cmd/bootefi.c| 4 ++--
 lib/efi_loader/Makefile  | 2 +-
 lib/efi_loader/efi_device_path.c | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/Kconfig b/Kconfig
index 17e6212..89f685b 100644
--- a/Kconfig
+++ b/Kconfig
@@ -70,7 +70,7 @@ config DISTRO_DEFAULTS
select CMD_BOOTZ if ARM && !ARM64
select CMD_BOOTI if ARM64
select CMD_DHCP if NET && CMD_NET
-   select CMD_PXE if NET && CMD_NET
+   select CMD_PXE if NET
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 6546272..7b1c09f 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -42,7 +42,7 @@ static void efi_init_obj_list(void)
 #if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
efi_gop_register();
 #endif
-#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_NET
efi_net_register();
 #endif
 #ifdef CONFIG_GENERATE_SMBIOS_TABLE
@@ -450,7 +450,7 @@ void efi_set_bootdev(const char *dev, const char *devnr, 
const char *path)
 
bootefi_device_path = efi_dp_from_part(desc, part);
} else {
-#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_NET
bootefi_device_path = efi_dp_from_eth();
 #endif
}
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 2a87d9e..2722265 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -21,5 +21,5 @@ obj-y += efi_file.o efi_variable.o efi_bootmgr.o 
efi_watchdog.o
 obj-$(CONFIG_LCD) += efi_gop.o
 obj-$(CONFIG_DM_VIDEO) += efi_gop.o
 obj-$(CONFIG_PARTITIONS) += efi_disk.o
-obj-$(CONFIG_CMD_NET) += efi_net.o
+obj-$(CONFIG_NET) += efi_net.o
 obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 3c735e6..ecc4eda 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -746,7 +746,7 @@ struct efi_device_path *efi_dp_from_file(struct blk_desc 
*desc, int part,
return start;
 }
 
-#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_NET
 struct efi_device_path *efi_dp_from_eth(void)
 {
struct efi_device_path_mac_addr *ndp;
-- 
1.7.11.5

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[U-Boot] [PATCH 8/9] net: Make core net code depend on NET instead of CMD_NET

[Joe Hershberger]

No commands are necessary to have a network stack.

Signed-off-by: Joe Hershberger 
---

 net/Makefile | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/net/Makefile b/net/Makefile
index ed102ec..95e9f63 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -8,18 +8,18 @@
 #ccflags-y += -DDEBUG
 
 obj-y += checksum.o
-obj-$(CONFIG_CMD_NET)  += arp.o
+obj-$(CONFIG_NET)  += arp.o
 obj-$(CONFIG_CMD_BOOTP) += bootp.o
 obj-$(CONFIG_CMD_CDP)  += cdp.o
 obj-$(CONFIG_CMD_DNS)  += dns.o
 ifdef CONFIG_DM_ETH
-obj-$(CONFIG_CMD_NET)  += eth-uclass.o
+obj-$(CONFIG_NET)  += eth-uclass.o
 else
-obj-$(CONFIG_CMD_NET)  += eth_legacy.o
+obj-$(CONFIG_NET)  += eth_legacy.o
 endif
-obj-$(CONFIG_CMD_NET)  += eth_common.o
+obj-$(CONFIG_NET)  += eth_common.o
 obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
-obj-$(CONFIG_CMD_NET)  += net.o
+obj-$(CONFIG_NET)  += net.o
 obj-$(CONFIG_CMD_NFS)  += nfs.o
 obj-$(CONFIG_CMD_PING) += ping.o
 obj-$(CONFIG_CMD_RARP) += rarp.o
-- 
1.7.11.5

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[U-Boot] [PATCH 7/9] net: Make the BOOTP options default

[Joe Hershberger]

The BOOTP options used to be and should still be default for all boards
with CMD_NET enabled. One should not be forced to use DISTRO_DEFAULTS to
get them.

Signed-off-by: Joe Hershberger 
---

 Kconfig | 6 --
 cmd/Kconfig | 6 ++
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/Kconfig b/Kconfig
index 6670913..17e6212 100644
--- a/Kconfig
+++ b/Kconfig
@@ -79,12 +79,6 @@ config DISTRO_DEFAULTS
select CMD_PING if NET
select CMD_PART if PARTITIONS
select HUSH_PARSER
-   select BOOTP_BOOTPATH if NET && CMD_NET
-   select BOOTP_DNS if NET && CMD_NET
-   select BOOTP_GATEWAY if NET && CMD_NET
-   select BOOTP_HOSTNAME if NET && CMD_NET
-   select BOOTP_PXE if NET && CMD_NET
-   select BOOTP_SUBNETMASK if NET && CMD_NET
select CMDLINE_EDITING
select AUTO_COMPLETE
select SYS_LONGHELP
diff --git a/cmd/Kconfig b/cmd/Kconfig
index cc059c4..6eff18f 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1032,6 +1032,7 @@ config CMD_DHCP
 
 config BOOTP_BOOTPATH
bool "Request & store 'rootpath' from BOOTP/DHCP server"
+   default y
depends on CMD_BOOTP
help
  Even though the config is called BOOTP_BOOTPATH, it stores the
@@ -1039,6 +1040,7 @@ config BOOTP_BOOTPATH
 
 config BOOTP_DNS
bool "Request & store 'dnsip' from BOOTP/DHCP server"
+   default y
depends on CMD_BOOTP
help
  The primary DNS server is stored as 'dnsip'. If two servers are
@@ -1058,20 +1060,24 @@ config BOOTP_DNS2
 
 config BOOTP_GATEWAY
bool "Request & store 'gatewayip' from BOOTP/DHCP server"
+   default y
depends on CMD_BOOTP
 
 config BOOTP_HOSTNAME
bool "Request & store 'hostname' from BOOTP/DHCP server"
+   default y
depends on CMD_BOOTP
help
  The name may or may not be qualified with the local domain name.
 
 config BOOTP_SUBNETMASK
bool "Request & store 'netmask' from BOOTP/DHCP server"
+   default y
depends on CMD_BOOTP
 
 config BOOTP_PXE
bool "Send PXE client arch to BOOTP/DHCP server"
+   default y
depends on CMD_BOOTP && CMD_PXE
help
  Supported for ARM, ARM64, and x86 for now.
-- 
1.7.11.5

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[U-Boot] [PATCH 1/9] net: Make CMD_NET a menuconfig

[Joe Hershberger]

Previously, CMD_NET was an alias for 2 commands (bootp and tftpboot) and
they we not able to be disabled. Separate out those 2 commands and move
CMD_NET up to the menu level, which more accurately represents the code.

Signed-off-by: Joe Hershberger 
---

 cmd/Kconfig  | 25 +
 cmd/net.c|  4 
 net/Kconfig  | 19 +--
 net/Makefile |  4 ++--
 4 files changed, 32 insertions(+), 20 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 136836d..f2a12ce 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1010,25 +1010,35 @@ config CMD_SETEXPR
 
 endmenu
 
-menu "Network commands"
-
 if NET
 
-config CMD_NET
-   bool "bootp, tftpboot"
+menuconfig CMD_NET
+   bool "Network commands"
+   default y
+
+if CMD_NET
+
+config CMD_BOOTP
+   bool "bootp"
default y
help
- Network commands.
  bootp - boot image via network using BOOTP/TFTP protocol
+
+config CMD_TFTPBOOT
+   bool "tftpboot"
+   default y
+   help
  tftpboot - boot image via network using TFTP protocol
 
 config CMD_TFTPPUT
bool "tftp put"
+   depends on CMD_TFTPBOOT
help
  TFTP put command, for uploading files to a server
 
 config CMD_TFTPSRV
bool "tftpsrv"
+   depends on CMD_TFTPBOOT
help
  Act as a TFTP server and boot the first received file
 
@@ -1039,13 +1049,12 @@ config CMD_RARP
 
 config CMD_DHCP
bool "dhcp"
-   depends on CMD_NET
+   depends on CMD_BOOTP
help
  Boot image via network using DHCP/TFTP protocol
 
 config CMD_PXE
bool "pxe"
-   depends on CMD_NET
select MENU
help
  Boot image via network using PXE protocol
@@ -1096,7 +1105,7 @@ config CMD_ETHSW
 
 endif
 
-endmenu
+endif
 
 menu "Misc commands"
 
diff --git a/cmd/net.c b/cmd/net.c
index d7c776a..67888d4 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -14,6 +14,7 @@
 
 static int netboot_common(enum proto_t, cmd_tbl_t *, int, char * const []);
 
+#ifdef CONFIG_CMD_BOOTP
 static int do_bootp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
return netboot_common(BOOTP, cmdtp, argc, argv);
@@ -24,7 +25,9 @@ U_BOOT_CMD(
"boot image via network using BOOTP/TFTP protocol",
"[loadAddress] [[hostIPaddr:]bootfilename]"
 );
+#endif
 
+#ifdef CONFIG_CMD_TFTPBOOT
 int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
int ret;
@@ -40,6 +43,7 @@ U_BOOT_CMD(
"boot image via network using TFTP protocol",
"[loadAddress] [[hostIPaddr:]bootfilename]"
 );
+#endif
 
 #ifdef CONFIG_CMD_TFTPPUT
 static int do_tftpput(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[])
diff --git a/net/Kconfig b/net/Kconfig
index 143c441..d421a34 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -24,7 +24,7 @@ config NETCONSOLE
 
 config NET_TFTP_VARS
bool "Control TFTP timeout and count through environment"
-   depends on CMD_NET
+   depends on CMD_TFTPBOOT
default y
help
  If set, allows controlling the TFTP timeout through the
@@ -35,39 +35,38 @@ config NET_TFTP_VARS
 
 config BOOTP_BOOTPATH
bool "Enable BOOTP BOOTPATH"
-   depends on CMD_NET
+   depends on CMD_BOOTP
 
 config BOOTP_DNS
bool "Enable bootp DNS"
-   depends on CMD_NET
+   depends on CMD_BOOTP
 
 config BOOTP_GATEWAY
bool "Enable BOOTP gateway"
-   depends on CMD_NET
+   depends on CMD_BOOTP
 
 config BOOTP_HOSTNAME
bool "Enable BOOTP hostname"
-   depends on CMD_NET
+   depends on CMD_BOOTP
 
 config BOOTP_PXE
bool "Enable BOOTP PXE"
-   depends on CMD_NET
+   depends on CMD_BOOTP
 
 config BOOTP_SUBNETMASK
bool "Enable BOOTP subnetmask"
-   depends on CMD_NET
-   depends on CMD_NET
+   depends on CMD_BOOTP
 
 config BOOTP_PXE_CLIENTARCH
hex
-   depends on CMD_NET
+   depends on CMD_BOOTP
 default 0x16 if ARM64
 default 0x15 if ARM
 default 0 if X86
 
 config BOOTP_VCI_STRING
string
-   depends on CMD_NET
+   depends on CMD_BOOTP
default "U-Boot.armv7" if CPU_V7 || CPU_V7M
default "U-Boot.armv8" if ARM64
default "U-Boot.arm" if ARM
diff --git a/net/Makefile b/net/Makefile
index ae54eee..ed102ec 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -9,7 +9,7 @@
 
 obj-y += checksum.o
 obj-$(CONFIG_CMD_NET)  += arp.o
-obj-$(CONFIG_CMD_NET)  += bootp.o
+obj-$(CONFIG_CMD_BOOTP) += bootp.o
 obj-$(CONFIG_CMD_CDP)  += cdp.o
 obj-$(CONFIG_CMD_DNS)  += dns.o
 ifdef CONFIG_DM_ETH
@@ -24,7 +24,7 @@ obj-$(CONFIG_CMD_NFS)  += nfs.o
 obj-$(CONFIG_CMD_PING) += ping.o
 obj-$(CONFIG_CMD_RARP) += rarp.o
 obj-$(CONFIG_CMD_SNTP) += sntp.o
-obj-$(CONFIG_CMD_NET)  += tftp.o
+obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
 
 # Disable this warning as it is triggered by:
 # sprintf(buf, index ? "foo%d" : "foo", index)
-- 
1.7.11.5

[U-Boot] [PATCH 4/9] net: Improve menu options and help for BOOTP options

[Joe Hershberger]

The options were pretty unhelpful, so improve them some.

Signed-off-by: Joe Hershberger 
---

 cmd/Kconfig | 19 ++-
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 7ef9501..76fd111 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1031,23 +1031,32 @@ config CMD_DHCP
  Boot image via network using DHCP/TFTP protocol
 
 config BOOTP_BOOTPATH
-   bool "Enable BOOTP BOOTPATH"
+   bool "Request & store 'rootpath' from BOOTP/DHCP server"
depends on CMD_BOOTP
+   help
+ Even though the config is called BOOTP_BOOTPATH, it stores the
+ path in the variable 'rootpath'.
 
 config BOOTP_DNS
-   bool "Enable bootp DNS"
+   bool "Request & store 'dnsip' from BOOTP/DHCP server"
depends on CMD_BOOTP
+   help
+ The primary DNS server is stored as 'dnsip'. If two servers are
+ returned, you must set BOOTP_DNS2 to store that second server IP
+ also.
 
 config BOOTP_GATEWAY
-   bool "Enable BOOTP gateway"
+   bool "Request & store 'gatewayip' from BOOTP/DHCP server"
depends on CMD_BOOTP
 
 config BOOTP_HOSTNAME
-   bool "Enable BOOTP hostname"
+   bool "Request & store 'hostname' from BOOTP/DHCP server"
depends on CMD_BOOTP
+   help
+ The name may or may not be qualified with the local domain name.
 
 config BOOTP_SUBNETMASK
-   bool "Enable BOOTP subnetmask"
+   bool "Request & store 'netmask' from BOOTP/DHCP server"
depends on CMD_BOOTP
 
 config BOOTP_PXE
-- 
1.7.11.5

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[U-Boot] [PATCH 0/9] net: Clean up the menus and dependencies among commands and options

[Joe Hershberger]

There have been a few issues persisting in the net menus and a recent
change that went in (Kconfig: cmd: Make networking command dependent on NET)
caused a few new issues. Clean up these things and further move to separate
CMD_NET from NET along appropriate boundaries.


Joe Hershberger (9):
  net: Make CMD_NET a menuconfig
  net: Move net command options to the cmd menu
  net: Move the DHCP command below the BOOTP command
  net: Improve menu options and help for BOOTP options
  net: Add the BOOTP_DNS2 option to Kconfig
  net: Improve BOOTP PXE config option
  net: Make the BOOTP options default
  net: Make core net code depend on NET instead of CMD_NET
  Revert "Kconfig: cmd: Make networking command dependent on NET"

 Kconfig  |   8 +--
 cmd/Kconfig  | 113 ++-
 cmd/bootefi.c|   4 +-
 cmd/net.c|   4 ++
 lib/efi_loader/Makefile  |   2 +-
 lib/efi_loader/efi_device_path.c |   2 +-
 net/Kconfig  |  51 --
 net/Makefile |  14 ++---
 8 files changed, 116 insertions(+), 82 deletions(-)

-- 
1.7.11.5

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[U-Boot] [PATCH 5/9] net: Add the BOOTP_DNS2 option to Kconfig

[Joe Hershberger]

Commit 3b3ea2c56ec4bc5 ("Kconfig: cmd: Make networking command dependent on 
NET")
removed the help documentation from the README but didn't add it back to 
Kconfig.

Signed-off-by: Joe Hershberger 
---

 cmd/Kconfig | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 76fd111..db75759 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1045,6 +1045,17 @@ config BOOTP_DNS
  returned, you must set BOOTP_DNS2 to store that second server IP
  also.
 
+config BOOTP_DNS2
+   bool "Store 'dnsip2' from BOOTP/DHCP server"
+   depends on BOOTP_DNS
+   help
+ If a DHCP client requests the DNS server IP from a DHCP server,
+ it is possible that more than one DNS serverip is offered to the
+ client. If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
+ server IP will be stored in the additional environment
+ variable "dnsip2". The first DNS serverip is always
+ stored in the variable "dnsip", when BOOTP_DNS is defined.
+
 config BOOTP_GATEWAY
bool "Request & store 'gatewayip' from BOOTP/DHCP server"
depends on CMD_BOOTP
-- 
1.7.11.5

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[U-Boot] [PATCH 2/9] net: Move net command options to the cmd menu

[Joe Hershberger]

Options that controlled the tftp and bootp commands depended on their
commands, but lived in the net menu.

Move them so they are in a consistent location.

Signed-off-by: Joe Hershberger 
---

 cmd/Kconfig | 50 ++
 net/Kconfig | 50 --
 2 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index f2a12ce..d714f73 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1024,6 +1024,45 @@ config CMD_BOOTP
help
  bootp - boot image via network using BOOTP/TFTP protocol
 
+config BOOTP_BOOTPATH
+   bool "Enable BOOTP BOOTPATH"
+   depends on CMD_BOOTP
+
+config BOOTP_DNS
+   bool "Enable bootp DNS"
+   depends on CMD_BOOTP
+
+config BOOTP_GATEWAY
+   bool "Enable BOOTP gateway"
+   depends on CMD_BOOTP
+
+config BOOTP_HOSTNAME
+   bool "Enable BOOTP hostname"
+   depends on CMD_BOOTP
+
+config BOOTP_SUBNETMASK
+   bool "Enable BOOTP subnetmask"
+   depends on CMD_BOOTP
+
+config BOOTP_PXE
+   bool "Enable BOOTP PXE"
+   depends on CMD_BOOTP
+
+config BOOTP_PXE_CLIENTARCH
+   hex
+   depends on CMD_BOOTP
+   default 0x16 if ARM64
+   default 0x15 if ARM
+   default 0 if X86
+
+config BOOTP_VCI_STRING
+   string
+   depends on CMD_BOOTP
+   default "U-Boot.armv7" if CPU_V7 || CPU_V7M
+   default "U-Boot.armv8" if ARM64
+   default "U-Boot.arm" if ARM
+   default "U-Boot"
+
 config CMD_TFTPBOOT
bool "tftpboot"
default y
@@ -1042,6 +1081,17 @@ config CMD_TFTPSRV
help
  Act as a TFTP server and boot the first received file
 
+config NET_TFTP_VARS
+   bool "Control TFTP timeout and count through environment"
+   depends on CMD_TFTPBOOT
+   default y
+   help
+ If set, allows controlling the TFTP timeout through the
+ environment variable tftptimeout, and the TFTP maximum
+ timeout count through the variable tftptimeoutcountmax.
+ If unset, timeout and maximum are hard-defined as 1 second
+ and 10 timouts per TFTP transfer.
+
 config CMD_RARP
bool "rarpboot"
help
diff --git a/net/Kconfig b/net/Kconfig
index d421a34..f2363e5 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -22,54 +22,4 @@ config NETCONSOLE
  Support the 'nc' input/output device for networked console.
  See README.NetConsole for details.
 
-config NET_TFTP_VARS
-   bool "Control TFTP timeout and count through environment"
-   depends on CMD_TFTPBOOT
-   default y
-   help
- If set, allows controlling the TFTP timeout through the
- environment variable tftptimeout, and the TFTP maximum
- timeout count through the variable tftptimeoutcountmax.
- If unset, timeout and maximum are hard-defined as 1 second
- and 10 timouts per TFTP transfer.
-
-config BOOTP_BOOTPATH
-   bool "Enable BOOTP BOOTPATH"
-   depends on CMD_BOOTP
-
-config BOOTP_DNS
-   bool "Enable bootp DNS"
-   depends on CMD_BOOTP
-
-config BOOTP_GATEWAY
-   bool "Enable BOOTP gateway"
-   depends on CMD_BOOTP
-
-config BOOTP_HOSTNAME
-   bool "Enable BOOTP hostname"
-   depends on CMD_BOOTP
-
-config BOOTP_PXE
-   bool "Enable BOOTP PXE"
-   depends on CMD_BOOTP
-
-config BOOTP_SUBNETMASK
-   bool "Enable BOOTP subnetmask"
-   depends on CMD_BOOTP
-
-config BOOTP_PXE_CLIENTARCH
-   hex
-   depends on CMD_BOOTP
-default 0x16 if ARM64
-default 0x15 if ARM
-default 0 if X86
-
-config BOOTP_VCI_STRING
-   string
-   depends on CMD_BOOTP
-   default "U-Boot.armv7" if CPU_V7 || CPU_V7M
-   default "U-Boot.armv8" if ARM64
-   default "U-Boot.arm" if ARM
-   default "U-Boot"
-
 endif   # if NET
-- 
1.7.11.5

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[U-Boot] [PATCH 3/9] net: Move the DHCP command below the BOOTP command

[Joe Hershberger]

Move DHCP to directly follow BOOTP so that Kconfig can show the
dependency as a hierarchy.

Signed-off-by: Joe Hershberger 
---

 cmd/Kconfig | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index d714f73..7ef9501 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1024,6 +1024,12 @@ config CMD_BOOTP
help
  bootp - boot image via network using BOOTP/TFTP protocol
 
+config CMD_DHCP
+   bool "dhcp"
+   depends on CMD_BOOTP
+   help
+ Boot image via network using DHCP/TFTP protocol
+
 config BOOTP_BOOTPATH
bool "Enable BOOTP BOOTPATH"
depends on CMD_BOOTP
@@ -1097,12 +1103,6 @@ config CMD_RARP
help
  Boot image via network using RARP/TFTP protocol
 
-config CMD_DHCP
-   bool "dhcp"
-   depends on CMD_BOOTP
-   help
- Boot image via network using DHCP/TFTP protocol
-
 config CMD_PXE
bool "pxe"
select MENU
-- 
1.7.11.5

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Re: [U-Boot] [PATCH v2 2/2] warp7: include/configs: use generic fs commands in CONFIG_EXTRA_ENV_SETTINGS

[Fabio Estevam]

On Wed, Mar 28, 2018 at 5:27 PM, Pierre-Jean TEXIER
 wrote:
> use the generic filesystem command 'load' rather
> than 'fatload' to avoid per-fs specific commands.
>
> Signed-off-by: Pierre-Jean TEXIER 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH v2 1/2] warp7: configs: enable CONFIG_CMD_FS_GENERIC

[Fabio Estevam]

On Wed, Mar 28, 2018 at 5:27 PM, Pierre-Jean TEXIER
 wrote:
> This enable generic file system commands (load, ls).
>
> Signed-off-by: Pierre-Jean TEXIER 

Reviewed-by: Fabio Estevam 
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[U-Boot] [PATCH v2 2/2] warp7: include/configs: use generic fs commands in CONFIG_EXTRA_ENV_SETTINGS

[Pierre-Jean TEXIER]

use the generic filesystem command 'load' rather
than 'fatload' to avoid per-fs specific commands.

Signed-off-by: Pierre-Jean TEXIER 
---
Changes for v2:
- apply modications into warp7.h
- replace fatload command in CONFIG_EXTRA_ENV_SETTINGS (prefer 'load')

 include/configs/warp7.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index fe96988..82dc629 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -45,11 +45,11 @@
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
-   "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+   "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+   "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+   "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run finduuid; " \
"run mmcargs; " \
-- 
2.7.4

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[U-Boot] [PATCH v2 1/2] warp7: configs: enable CONFIG_CMD_FS_GENERIC

[Pierre-Jean TEXIER]

This enable generic file system commands (load, ls).

Signed-off-by: Pierre-Jean TEXIER 
---
Changes for v2:
- None

 configs/warp7_defconfig| 1 +
 configs/warp7_secure_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 29c4512..3856918 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DFU_MMC=y
 CONFIG_USB=y
diff --git a/configs/warp7_secure_defconfig b/configs/warp7_secure_defconfig
index 7310855..e894578 100644
--- a/configs/warp7_secure_defconfig
+++ b/configs/warp7_secure_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DFU_MMC=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
-- 
2.7.4

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Re: [U-Boot] [PATCH v2 1/3] Move CONFIG_PHY_ADDR to Kconfig

[Joe Hershberger]

On Sun, Mar 25, 2018 at 8:40 PM, Bin Meng  wrote:
> Hi Joe,
>
> On Sat, Mar 24, 2018 at 1:11 AM, Joe Hershberger  
> wrote:
>> On Thu, Mar 22, 2018 at 9:46 AM, Bin Meng  wrote:
>>> Hi,
>>>
>>> On Fri, Feb 2, 2018 at 9:53 PM, Stefan Mavrodiev  wrote:
 CONFIG_PHY_ADDR is used for old-style configuration. This makes
 impossible changing the PHY address, if multiple boards share a same
 config header file (for example include/configs/sunxi-common.h).

 Moving this to Kconfig helps overcoming this issue. It's defined
 as entry inside PHYLIB section.

 After the implemention, moveconfig was run. The issues are:
 - edb9315a  - CONFIG_PHYLIB is not enabled. Entry is
   deleted.

 - ds414 - CONFIG_PHYLIB is in incompatible format:
   { 0x1, 0x0 }. This entry is also deleted.

 - devkit3250- The PHY_ADDR is in hex format (0x1F).
   Manually CONFIG_PHY_ADDR=31 is added in
   the defconfig.

 After the changes the suspicious defconfigs passes building.

 Signed-off-by: Stefan Mavrodiev 
 Acked-by: Maxime Ripard 
 ---
  Changes for v2:
- Replaced CONFIG_SUNXI_PHY_ADDR with a common one
  CONFIG_PHY_ADDR, using moveconfig.

  README | 4 
  configs/devkit3250_defconfig   | 1 +
  configs/khadas-vim_defconfig   | 1 +
  configs/libretech-cc_defconfig | 1 +
  configs/p212_defconfig | 1 +
  drivers/net/phy/Kconfig| 7 +++
  include/configs/am335x_shc.h   | 1 -
  include/configs/baltos.h   | 1 -
  include/configs/devkit3250.h   | 1 -
  include/configs/ds414.h| 1 -
  include/configs/edb93xx.h  | 1 -
  include/configs/khadas-vim.h   | 2 --
  include/configs/libretech-cc.h | 2 --
  include/configs/p212.h | 2 --
  include/configs/pepper.h   | 1 -
  include/configs/sunxi-common.h | 2 --
  include/configs/work_92105.h   | 1 -
  include/configs/x600.h | 1 -
  scripts/config_whitelist.txt   | 1 -
  19 files changed, 11 insertions(+), 21 deletions(-)

>>>
>>> [snip]
>>>
 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
 index 95b7534..c934aed 100644
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
 @@ -12,6 +12,13 @@ menuconfig PHYLIB

  if PHYLIB

 +config PHY_ADDR
 +   int "PHY address"
 +   default 1 if ARCH_SUNXI
 +   default 0
 +   help
 + The address of PHY on MII bus. Usually in range of 0 to 31.
 +
>>>
>>> Sorry for jumping out so late, but this commit breaks Intel Galileo
>>> ethernet. Previously the board boots with the following log:
>>>
>>> Net: eth0: eth_designware#0, eth1: eth_designware#1
>>>
>>> With this commit it becomes:
>>>
>>> Net:   No ethernet found.
>>>
>>> The reason is that the board has two designware ethernet controllers,
>>> and PHY_ADDR has been set to zero for both. A simple fix is to:
>>>
>>> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
>>> index 43670a7..1394119 100644
>>> --- a/drivers/net/designware.c
>>> +++ b/drivers/net/designware.c
>>> @@ -471,10 +471,6 @@ static int dw_phy_init(struct dw_eth_dev *priv, void 
>>> *dev)
>>> struct phy_device *phydev;
>>> int mask = 0x, ret;
>>>
>>> -#ifdef CONFIG_PHY_ADDR
>>> -   mask = 1 << CONFIG_PHY_ADDR;
>>> -#endif
>>> -
>>> phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
>>> if (!phydev)
>>> return -ENODEV;
>>>
>>> But the real question is that: why do we introduce this PHY_ADDR
>>> Kconfig? It for sure won't work for multiple ethernet controllers.This
>>> should be eliminated IMHO. Comments?
>>
>> This should be able to come from the device tree, ultimately. Can you
>> undefine the phy addr for the Galileo board?
>>
>>> [snip]
>>>
>
> #undf the PHY_ADDR in Galileo board looks weird. This to me is a workaround.

I didn't mean to add a #undef. I was just saying that if the "default
0" in the Kconfig were instead "default 0 if !X86" or something (or
maybe if the board defconfig explicitly does unselects it).

> Since the designware ethernet controller driver supports finding any
> PHY attached to its mdio bus, the changes suggested above can be a
> proper fix.

That is good for your board, but some board may have more than one phy
and want to specify which to use in U-Boot.

Ultimately it should be possible to read it from the DT.

Cheers,
-Joe

> Regards,
> Bin
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Re: [U-Boot] [PATCH v4 13/19] sunxi: DT: A64: update board .dts files from Linux

[Jagan Teki]

On Wed, Mar 28, 2018 at 4:45 PM, Maxime Ripard
 wrote:
> On Wed, Mar 28, 2018 at 03:22:20PM +0530, Jagan Teki wrote:
>> >> May it's good option to look at v3 changes, since DM_MMC Migration
>> >> expires in coming release, dt changes which are related to MMC we can
>> >> wait for proper supported feature get IN(like pinctrl, clock, reset),
>> >> that means we should anyway need to move DM_MMC but with working dt
>> >> changes.
>> >>
>> >> The big question for me here is about SPL, I'm sure we can get the
>> >> size issues. May be we try platdata but in any case we need to enable
>> >> DM ie increase the size (atleast for A64, H5)
>> >
>> > So my understanding is that those DM_ defines are just for
>> > U-Boot proper, and the SPL needs extra symbols to be also "DMed".
>>
>> I don't think so, Idea about migrating to BLK, DM_MMC should remove
>> #ifdef code with DM vs non-DM such that the driver should have DM
>> version with DT along with PLATDATA
>
> I'm not even sure what is the point of having the DM in the SPL. We
> won't be able to have any of the benefits due to our size constraint.

True, but what if MIGRATION.txt intention is to remove old or non-dm
code after v2018.05?

Jagan.
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Re: [U-Boot] [PATCH v2] Kconfig: cmd: Make networking command dependent on NET

[Joe Hershberger]

On Wed, Mar 28, 2018 at 2:45 AM, Michal Simek  wrote:
> On 28.3.2018 01:28, Joe Hershberger wrote:
>> Hi Heinrich,
>>
>> On Wed, Feb 28, 2018 at 5:05 PM, Heinrich Schuchardt
>>  wrote:
>>> On 02/28/2018 02:09 AM, Tom Rini wrote:

 On Mon, Feb 26, 2018 at 04:01:02PM +0100, Michal Simek wrote:

> Enable networking command only when NET is enabled.
> And remove selecting NET for CMD_NET
>
> Signed-off-by: Michal Simek 
> ---
>
> Changes in v2:
> - Check several boards by hand.
>
> There is a huge impact on defconfigs because of select NET.
> But this change makes sense to do but it just needs to be syncup
> properly. Do we have a tool for this kind of change?


 So, I've applied this patch, with a good bit of modification.  What I
 wasn't clear about before, sorry, was that we need to make NET default y
 in here too.  However, we also have some decent areas of the code that
 use "CONFIG_CMD_NET" when it really means "CONFIG_NET", at least
 conceptually.  But in order to make everything work as-is today, and
 leave these fixes to a later point in time (as they are fixes and should
 happen) we change some areas today that reference CONFIG_NET to
 reference CONFIG_CMD_NET.  Once net/ gets cleaned up, we can use
 CONFIG_NET without CONFIG_CMD_NET in more area.  It's also not quite
 100% size-neutral as the topic_miami* boards were playing some games
 that can't quite be done as they were before, but I believe the end
 result is they can now more easily and thoroughly disable the networking
 stuff that intended to be removed.


>>>
>>> Hello Tom,
>>>
>>> in spite of you comments above I do not understand why you changed
>>> cmd/bootefi.c to depend on CONFIG_CMD_NET instead of CONFIG_NET.
>>>
>>> This was not part of Michal's patch.
>>>
>>> I would prefer if changes would be sent to the list for review *before*
>>> being applied.
>>>
>>> As the patch that you applied is not Michal's patch your authorship should
>>> be documented in the git log.
>>>
>>> I cannot see any reason why network support should be disabled in bootefi if
>>> there are no network commands available.
>>
>> I think there is a fair amount of conflation since some of the basic
>> functions like bootp and dhcp are only accessible through the
>> commands, but you're right that it should be possible to use
>> networking with a static IP and no network commands.
>
> Can you please be more specific how you can use network without network
> commands?

In this case, if EFI is using the network, then U-Boot need not have
any commands that use it. NetConsole is probably another example.

-Joe
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Re: [U-Boot] [PATCH] warp7: configs: enable CONFIG_CMD_FS_GENERIC

[Pierre-Jean Texier]

Hi Fabio


Le 28/03/2018 à 03:02, Fabio Estevam a écrit :

Hi Pierre-Jean,

On Tue, Mar 27, 2018 at 4:50 PM, Pierre-Jean TEXIER
 wrote:

This enable generic file system commands (load, ls).

Signed-off-by: Pierre-Jean TEXIER 
---
  configs/warp7_defconfig| 1 +
  configs/warp7_secure_defconfig | 1 +
  2 files changed, 2 insertions(+)

diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 29c4512..3856918 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_EXT2=y
  CONFIG_CMD_EXT4=y
  CONFIG_CMD_EXT4_WRITE=y
  CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y

It is OK to make this change, but please also change


Ok thanks !


include/configs/warp.h so that is uses 'load' instead of 'fatload'.


No problem, I will submit a patch for this part.



Also, please run ./scripts/get_maintainer.pl so that you do not miss
to Cc the board maintainer and also Stefano Babic.


Indeed, sorry for that, this is an oversight.



Thanks


Thanks

---
Pierre-Jean
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Re: [U-Boot] [PATCH] arm: stm32mp1: add PSCI support

[Mark Rutland]

Hi,

On Tue, Mar 20, 2018 at 01:59:03PM +0100, Patrick Delaunay wrote:
> Add minimal PSCI support for Linux.
> 
> Signed-off-by: Patrick Delaunay 

> +int __secure psci_features(unsigned int psci_fid)
> +{
> + switch (psci_fid) {
> + case ARM_PSCI_0_2_FN_PSCI_VERSION:
> + case ARM_PSCI_0_2_FN_CPU_ON:
> + case ARM_PSCI_0_2_FN_CPU_OFF:
> + case ARM_PSCI_0_2_FN_SYSTEM_RESET:
> + return 0x0;
> + }
> + return ARM_PSCI_RET_NI;
> +}
>
> +unsigned int __secure psci_version(void)
> +{
> + return ARM_PSCI_VER_1_0;
> +}

I'm a bit worried, because while PSCI_VERSION reports PSCI 1.0, this
does not appear to be conformant with teh PSCI 1.0 spec, as some
mandatory functions are missing:

* AFFINITY_INFO -- Linux relies on this to ensure that CPUs have exited
  the kernel when calling CPU_OFF (e.g. so that we don't free any data /
  code that said CPU may be using on the path to calling CPU_OFF).

* SYSTEM_OFF -- Can you implement this similarly to SYSTEM_RESET?

> +int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
> +{

What about the context_id? PSCI 0.2+ mandates it, and some project rely
upon it (though Linux currently does not).

> + u32 cpu = (mpidr & 0x3);
> +
> + /* store target PC */
> + psci_save_target_pc(cpu, pc);
> +
> + /* write entrypoint in backup RAM register */
> + writel((u32)_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS);
> +
> + /* write magic number in backup register */
> + writel(BOOT_API_A7_CORE1_MAGIC_NUMBER, TAMP_BACKUP_MAGIC_NUMBER);
> + stm32mp_smp_kick_all_cpus();
> +
> + return ARM_PSCI_RET_SUCCESS;

Does some other part of U-Boot do some state tracking? What happens if
this is called for a CPU that's already online?

Thanks,
Mark.
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[U-Boot] [PATCH 2/6] arm64: zynqmp: Add support for zc1751 dc3

[Michal Simek]

zc1751 is based board with dc3 extenstion card which is used for silicon
validation.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts   | 210 +
 .../zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c  | 900 +
 configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig   |  86 ++
 include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h   |  20 +
 5 files changed, 1217 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
 create mode 100644 configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3efdd67e2e80..54d325ac89a7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -154,6 +154,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu102-rev1.0.dtb\
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
+   zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts 
b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
new file mode 100644
index ..d6a010355bb8
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm017-dc3
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek 
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+   model = "ZynqMP zc1751-xm017-dc3 RevA";
+   compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+   aliases {
+   ethernet0 = 
+   gpio0 = 
+   i2c0 = 
+   i2c1 = 
+   mmc0 = 
+   rtc0 = 
+   serial0 = 
+   serial1 = 
+   usb0 = 
+   usb1 = 
+   };
+
+   chosen {
+   bootargs = "earlycon";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>, <0x8 0x 0x0 0x8000>;
+   };
+};
+
+_dma_chan1 {
+   status = "okay";
+};
+
+_dma_chan2 {
+   status = "okay";
+};
+
+_dma_chan3 {
+   status = "okay";
+};
+
+_dma_chan4 {
+   status = "okay";
+};
+
+_dma_chan5 {
+   status = "okay";
+};
+
+_dma_chan6 {
+   status = "okay";
+};
+
+_dma_chan7 {
+   status = "okay";
+};
+
+_dma_chan8 {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   phy-handle = <>;
+   phy-mode = "rgmii-id";
+   phy0: phy@0 { /* VSC8211 */
+   reg = <0>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+/* just eeprom here */
+ {
+   status = "okay";
+   clock-frequency = <40>;
+
+   tca6416_u26: gpio@20 {
+   compatible = "ti,tca6416";
+   reg = <0x20>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   /* IRQ not connected */
+   };
+
+   rtc@68 {
+   compatible = "dallas,ds1339";
+   reg = <0x68>;
+   };
+};
+
+/* eeprom24c02 and SE98A temp chip pca9306 */
+ {
+   status = "okay";
+   clock-frequency = <40>;
+};
+
+/* MT29F64G08AECDBJ4-6 */
+ {
+   status = "okay";
+   arasan,has-mdma;
+   num-cs = <2>;
+
+   partition@0 {   /* for testing purpose */
+   label = "nand-fsbl-uboot";
+   reg = <0x0 0x0 0x40>;
+   };
+   partition@1 {   /* for testing purpose */
+   label = "nand-linux";
+   reg = <0x0 0x40 0x140>;
+   };
+   partition@2 {   /* for testing purpose */
+   label = "nand-device-tree";
+   reg = <0x0 0x180 0x40>;
+   };
+   partition@3 {   /* for testing purpose */
+   label = "nand-rootfs";
+   reg = <0x0 0x1C0 0x140>;
+   };
+   partition@4 {   /* for testing purpose */
+   label = "nand-bitstream";
+   reg = <0x0 0x300 0x40>;
+   };
+   partition@5 {   /* for testing purpose */
+   label = "nand-misc";
+   reg = <0x0 0x340 0xFCC0>;
+   };
+
+   partition@6 {   /* for testing purpose */
+   label = "nand1-fsbl-uboot";
+   reg = <0x1 0x0 0x40>;
+   };
+   partition@7 {   /* for testing purpose */
+   label = "nand1-linux";
+   reg = <0x1 0x40 0x140>;
+   };
+   partition@8 {   /* for testing purpose */
+   label = 

[U-Boot] [PATCH 6/6] arm64: zynqmp: Add support for Xilinx zcu111-revA

[Michal Simek]

Xilinx zcu111 is a customer board. It is reusing some parts from zcu102.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/zynqmp-zcu111-revA.dts | 763 
 configs/xilinx_zynqmp_zcu111_revA_defconfig |  95 
 include/configs/xilinx_zynqmp_zcu111.h  |  50 ++
 4 files changed, 909 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-zcu111-revA.dts
 create mode 100644 configs/xilinx_zynqmp_zcu111_revA_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_zcu111.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aa768935719d..77a0f8a30833 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -155,6 +155,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu104-revA.dtb  \
zynqmp-zcu104-revC.dtb  \
zynqmp-zcu106-revA.dtb  \
+   zynqmp-zcu111-revA.dtb  \
zynqmp-zc1232-revA.dtb  \
zynqmp-zc1254-revA.dtb  \
zynqmp-zc1275-revA.dtb  \
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts 
b/arch/arm/dts/zynqmp-zcu111-revA.dts
new file mode 100644
index ..1bb28de90b21
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -0,0 +1,763 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU111
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek 
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   model = "ZynqMP ZCU111 RevA";
+   compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", 
"xlnx,zynqmp";
+
+   aliases {
+   ethernet0 = 
+   gpio0 = 
+   i2c0 = 
+   i2c1 = 
+   mmc0 = 
+   rtc0 = 
+   serial0 = 
+   serial1 = 
+   spi0 = 
+   usb0 = 
+   };
+
+   chosen {
+   bootargs = "earlycon";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>, <0x8 0x 0x0 0x8000>;
+   /* Another 4GB connected to PL */
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   autorepeat;
+   sw19 {
+   label = "sw19";
+   gpios = < 22 GPIO_ACTIVE_HIGH>;
+   linux,code = ;
+   gpio-key,wakeup;
+   autorepeat;
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   heartbeat_led {
+   label = "heartbeat";
+   gpios = < 23 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+_dma_chan1 {
+   status = "okay";
+};
+
+_dma_chan2 {
+   status = "okay";
+};
+
+_dma_chan3 {
+   status = "okay";
+};
+
+_dma_chan4 {
+   status = "okay";
+};
+
+_dma_chan5 {
+   status = "okay";
+};
+
+_dma_chan6 {
+   status = "okay";
+};
+
+_dma_chan7 {
+   status = "okay";
+};
+
+_dma_chan8 {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   phy-handle = <>;
+   phy-mode = "rgmii-id";
+   pinctrl-names = "default";
+   pinctrl-0 = <_gem3_default>;
+   phy0: phy@c {
+   reg = <0xc>;
+   ti,rx-internal-delay = <0x8>;
+   ti,tx-internal-delay = <0xa>;
+   ti,fifo-depth = <0x1>;
+   };
+};
+
+ {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_gpio_default>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   clock-frequency = <40>;
+   pinctrl-names = "default", "gpio";
+   pinctrl-0 = <_i2c0_default>;
+   pinctrl-1 = <_i2c0_gpio>;
+   scl-gpios = < 14 GPIO_ACTIVE_HIGH>;
+   sda-gpios = < 15 GPIO_ACTIVE_HIGH>;
+
+   tca6416_u22: gpio@20 {
+   compatible = "ti,tca6416";
+   reg = <0x20>;
+   gpio-controller; /* interrupt not connected */
+   #gpio-cells = <2>;
+   /*
+* IRQ not connected
+* Lines:
+* 0 - MAX6643_OT_B
+* 1 - MAX6643_FANFAIL_B
+* 2 - MIO26_PMU_INPUT_LS
+* 4 - SFP_SI5382_INT_ALM
+* 5 - IIC_MUX_RESET_B
+* 6 - GEM3_EXP_RESET_B
+* 10 - FMCP_HSPC_PRSNT_M2C_B
+* 11 - CLK_SPI_MUX_SEL0
+* 12 - CLK_SPI_MUX_SEL1
+* 16 - IRPS5401_ALERT_B
+* 17 - 

[U-Boot] [PATCH 5/6] arm64: zynqmp: Add support for Xilinx zcu106-revA

[Michal Simek]

Xilinx zcu106 is a customer board. It is reusing some parts from zcu102.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/zynqmp-zcu106-revA.dts| 884 +
 .../zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c   | 802 +++
 configs/xilinx_zynqmp_zcu106_revA_defconfig| 104 +++
 include/configs/xilinx_zynqmp_zcu106.h |  47 ++
 5 files changed, 1838 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-zcu106-revA.dts
 create mode 100644 board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
 create mode 100644 configs/xilinx_zynqmp_zcu106_revA_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_zcu106.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0c71a3cdd495..aa768935719d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -154,6 +154,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu102-rev1.0.dtb\
zynqmp-zcu104-revA.dtb  \
zynqmp-zcu104-revC.dtb  \
+   zynqmp-zcu106-revA.dtb  \
zynqmp-zc1232-revA.dtb  \
zynqmp-zc1254-revA.dtb  \
zynqmp-zc1275-revA.dtb  \
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts 
b/arch/arm/dts/zynqmp-zcu106-revA.dts
new file mode 100644
index ..f425806902a2
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -0,0 +1,884 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU106
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek 
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   model = "ZynqMP ZCU106 RevA";
+   compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", 
"xlnx,zynqmp";
+
+   aliases {
+   ethernet0 = 
+   gpio0 = 
+   i2c0 = 
+   i2c1 = 
+   mmc0 = 
+   rtc0 = 
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   spi0 = 
+   usb0 = 
+   };
+
+   chosen {
+   bootargs = "earlycon";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>, <0x8 0x 0x0 0x8000>;
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   autorepeat;
+   sw19 {
+   label = "sw19";
+   gpios = < 22 GPIO_ACTIVE_HIGH>;
+   linux,code = ;
+   gpio-key,wakeup;
+   autorepeat;
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   heartbeat_led {
+   label = "heartbeat";
+   gpios = < 23 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+};
+
+ {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_can1_default>;
+};
+
+ {
+   status = "okay";
+};
+
+_dma_chan1 {
+   status = "okay";
+};
+
+_dma_chan2 {
+   status = "okay";
+};
+
+_dma_chan3 {
+   status = "okay";
+};
+
+_dma_chan4 {
+   status = "okay";
+};
+
+_dma_chan5 {
+   status = "okay";
+};
+
+_dma_chan6 {
+   status = "okay";
+};
+
+_dma_chan7 {
+   status = "okay";
+};
+
+_dma_chan8 {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   phy-handle = <>;
+   phy-mode = "rgmii-id";
+   pinctrl-names = "default";
+   pinctrl-0 = <_gem3_default>;
+   phy0: phy@c {
+   reg = <0xc>;
+   ti,rx-internal-delay = <0x8>;
+   ti,tx-internal-delay = <0xa>;
+   ti,fifo-depth = <0x1>;
+   };
+};
+
+ {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_gpio_default>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   clock-frequency = <40>;
+   pinctrl-names = "default", "gpio";
+   pinctrl-0 = <_i2c0_default>;
+   pinctrl-1 = <_i2c0_gpio>;
+   scl-gpios = < 14 GPIO_ACTIVE_HIGH>;
+   sda-gpios = < 15 GPIO_ACTIVE_HIGH>;
+
+   tca6416_u97: gpio@20 {
+   compatible = "ti,tca6416";
+   reg = <0x20>;
+   gpio-controller; /* interrupt not connected */
+   #gpio-cells = <2>;
+   /*
+* IRQ not connected
+* Lines:
+* 0 - SFP_SI5328_INT_ALM
+* 1 - HDMI_SI5328_INT_ALM
+* 5 - IIC_MUX_RESET_B
+* 6 - GEM3_EXP_RESET_B
+* 10 - 

[U-Boot] [PATCH 3/6] arm64: zynqmp: Add support for zc12xx boards

[Michal Simek]

Add support for zc12xx boards. All of them are internal boards for
silicon validation and share very similar base platforms.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/Makefile  |   3 +
 arch/arm/dts/zynqmp-zc1232-revA.dts|  87 +++
 arch/arm/dts/zynqmp-zc1254-revA.dts|  72 ++
 arch/arm/dts/zynqmp-zc1275-revA.dts|  72 ++
 .../zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c   | 745 +
 .../zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c   | 467 +
 board/xilinx/zynqmp/zynqmp-zc1275-revA |   1 +
 configs/xilinx_zynqmp_zc1232_revA_defconfig|  53 ++
 configs/xilinx_zynqmp_zc1254_revA_defconfig|  53 ++
 configs/xilinx_zynqmp_zc1275_revA_defconfig|  53 ++
 10 files changed, 1606 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-zc1232-revA.dts
 create mode 100644 arch/arm/dts/zynqmp-zc1254-revA.dts
 create mode 100644 arch/arm/dts/zynqmp-zc1275-revA.dts
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
 create mode 12 board/xilinx/zynqmp/zynqmp-zc1275-revA
 create mode 100644 configs/xilinx_zynqmp_zc1232_revA_defconfig
 create mode 100644 configs/xilinx_zynqmp_zc1254_revA_defconfig
 create mode 100644 configs/xilinx_zynqmp_zc1275_revA_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 54d325ac89a7..f0829ee7bab9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -152,6 +152,9 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu102-revA.dtb  \
zynqmp-zcu102-revB.dtb  \
zynqmp-zcu102-rev1.0.dtb\
+   zynqmp-zc1232-revA.dtb  \
+   zynqmp-zc1254-revA.dtb  \
+   zynqmp-zc1275-revA.dtb  \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm017-dc3.dtb \
diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts 
b/arch/arm/dts/zynqmp-zc1232-revA.dts
new file mode 100644
index ..ea1ca561a163
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1232
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek 
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include 
+
+/ {
+   model = "ZynqMP ZC1232 RevA";
+   compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", 
"xlnx,zynqmp";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   spi0 = 
+   };
+
+   chosen {
+   bootargs = "earlycon";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   flash@0 {
+   compatible = "m25p80"; /* 32MB FIXME */
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x0>;
+   spi-tx-bus-width = <1>;
+   spi-rx-bus-width = <4>;
+   spi-max-frequency = <10800>; /* Based on DC1 spec */
+   partition@qspi-fsbl-uboot { /* for testing purpose */
+   label = "qspi-fsbl-uboot";
+   reg = <0x0 0x10>;
+   };
+   partition@qspi-linux { /* for testing purpose */
+   label = "qspi-linux";
+   reg = <0x10 0x50>;
+   };
+   partition@qspi-device-tree { /* for testing purpose */
+   label = "qspi-device-tree";
+   reg = <0x60 0x2>;
+   };
+   partition@qspi-rootfs { /* for testing purpose */
+   label = "qspi-rootfs";
+   reg = <0x62 0x5E>;
+   };
+   };
+};
+
+ {
+   status = "okay";
+   /* SATA OOB timing settings */
+   ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+   ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+   ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+   ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+   ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+   ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+   ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+   ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+   phy-names = "sata-phy";
+   phys = < PHY_TYPE_SATA 0 0 12500>, < PHY_TYPE_SATA 1 1 
12500>;
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts 

[U-Boot] [PATCH 4/6] arm64: zynqmp: Add support for zcu104 customer board

[Michal Simek]

Xilinx zcu104 is another customer board. It is sort of zcu102 clone with
some differences.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/Makefile  |   2 +
 arch/arm/dts/zynqmp-zcu104-revA.dts| 481 +++
 arch/arm/dts/zynqmp-zcu104-revC.dts| 482 +++
 .../zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c   | 878 +
 board/xilinx/zynqmp/zynqmp-zcu104-revC |   1 +
 configs/xilinx_zynqmp_zcu104_revA_defconfig|  95 +++
 configs/xilinx_zynqmp_zcu104_revC_defconfig|  95 +++
 include/configs/xilinx_zynqmp_zcu104.h |  36 +
 8 files changed, 2070 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-zcu104-revA.dts
 create mode 100644 arch/arm/dts/zynqmp-zcu104-revC.dts
 create mode 100644 board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
 create mode 12 board/xilinx/zynqmp/zynqmp-zcu104-revC
 create mode 100644 configs/xilinx_zynqmp_zcu104_revA_defconfig
 create mode 100644 configs/xilinx_zynqmp_zcu104_revC_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_zcu104.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f0829ee7bab9..0c71a3cdd495 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -152,6 +152,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu102-revA.dtb  \
zynqmp-zcu102-revB.dtb  \
zynqmp-zcu102-rev1.0.dtb\
+   zynqmp-zcu104-revA.dtb  \
+   zynqmp-zcu104-revC.dtb  \
zynqmp-zc1232-revA.dtb  \
zynqmp-zc1254-revA.dtb  \
zynqmp-zc1275-revA.dtb  \
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts 
b/arch/arm/dts/zynqmp-zcu104-revA.dts
new file mode 100644
index ..9724ed4180a3
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU104
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek 
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include 
+#include 
+#include 
+
+/ {
+   model = "ZynqMP ZCU104 RevA";
+   compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", 
"xlnx,zynqmp";
+
+   aliases {
+   ethernet0 = 
+   gpio0 = 
+   i2c0 = 
+   mmc0 = 
+   rtc0 = 
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   spi0 = 
+   usb0 = 
+   };
+
+   chosen {
+   bootargs = "earlycon";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>;
+   };
+};
+
+ {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_can1_default>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   phy-handle = <>;
+   phy-mode = "rgmii-id";
+   pinctrl-names = "default";
+   pinctrl-0 = <_gem3_default>;
+   phy0: phy@c {
+   reg = <0xc>;
+   ti,rx-internal-delay = <0x8>;
+   ti,tx-internal-delay = <0xa>;
+   ti,fifo-depth = <0x1>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   clock-frequency = <40>;
+   pinctrl-names = "default", "gpio";
+   pinctrl-0 = <_i2c1_default>;
+   pinctrl-1 = <_i2c1_gpio>;
+   scl-gpios = < 16 GPIO_ACTIVE_HIGH>;
+   sda-gpios = < 17 GPIO_ACTIVE_HIGH>;
+
+   /* Another connection to this bus via PL i2c via PCA9306 - u45 */
+   i2c-mux@74 { /* u34 */
+   compatible = "nxp,pca9548";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x74>;
+   i2c@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+   /*
+* IIC_EEPROM 1kB memory which uses 256B blocks
+* where every block has different address.
+*0 - 256B address 0x54
+* 256B - 512B address 0x55
+* 512B - 768B address 0x56
+* 768B - 1024B address 0x57
+*/
+   eeprom: eeprom@54 { /* u23 */
+   compatible = "atmel,24c08";
+   reg = <0x54>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   };
+   };
+
+   i2c@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+  

[U-Boot] [PATCH 1/6] arm64: zynqmp: Add support for zcu100 aka 96ultra board

[Michal Simek]

Add support for Xilinx zcu100.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/zynqmp-zcu100-revC.dts| 580 
 .../zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c   | 993 +
 configs/xilinx_zynqmp_zcu100_revC_defconfig|  83 ++
 include/configs/xilinx_zynqmp_zcu100.h |  39 +
 5 files changed, 1696 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-zcu100-revC.dts
 create mode 100644 board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
 create mode 100644 configs/xilinx_zynqmp_zcu100_revC_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_zcu100.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 27cedba6eb66..3efdd67e2e80 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -148,6 +148,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc.dtb\
zynqmp-mini-nand.dtb\
+   zynqmp-zcu100-revC.dtb  \
zynqmp-zcu102-revA.dtb  \
zynqmp-zcu102-revB.dtb  \
zynqmp-zcu102-rev1.0.dtb\
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts 
b/arch/arm/dts/zynqmp-zcu100-revC.dts
new file mode 100644
index ..158f13a40ba4
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU100 revC
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek 
+ * Nathalie Chan King Choy
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   model = "ZynqMP ZCU100 RevC";
+   compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", 
"xlnx,zynqmp";
+
+   aliases {
+   gpio0 = 
+   i2c0 = 
+   rtc0 = 
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   spi0 = 
+   spi1 = 
+   usb0 = 
+   usb1 = 
+   mmc0 = 
+   mmc1 = 
+   };
+
+   chosen {
+   bootargs = "earlycon";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>;
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   autorepeat;
+   sw4 {
+   label = "sw4";
+   gpios = < 23 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   gpio-key,wakeup;
+   autorepeat;
+   };
+   };
+
+   iio-hwmon {
+   compatible = "iio-hwmon";
+   io-channels = <_ams 0>, <_ams 1>, <_ams 2>,
+ <_ams 3>, <_ams 4>, <_ams 5>,
+ <_ams 6>, <_ams 7>, <_ams 8>,
+ <_ams 9>, <_ams 10>,
+ <_ams 11>, <_ams 12>;
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   ds2 {
+   label = "ds2";
+   gpios = < 20 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+
+   ds3 {
+   label = "ds3";
+   gpios = < 19 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "phy0tx"; /* WLAN tx */
+   default-state = "off";
+   };
+
+   ds4 {
+   label = "ds4";
+   gpios = < 18 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "phy0rx"; /* WLAN rx */
+   default-state = "off";
+   };
+
+   ds5 {
+   label = "ds5";
+   gpios = < 17 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "bluetooth-power";
+   };
+
+   vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
+   label = "vbus_det";
+   gpios = < 25 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+   };
+
+   ltc2954: ltc2954 { /* U7 */
+   compatible = "lltc,ltc2954", "lltc,ltc2952";
+   trigger-gpios = < 26 GPIO_ACTIVE_LOW>; /* INT line - input 
*/
+   /* If there is HW watchdog on mezzanine this signal should be 
connected there */
+   watchdog-gpios = < 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */
+   kill-gpios = < 34 GPIO_ACTIVE_LOW>; /* KILL signal - 
output */
+   };
+
+   wmmcsdio_fixed: 

[U-Boot] [PATCH 0/6] arm64: zynqmp: Add new platforms to u-boot

[Michal Simek]

Hi,

all these platforms are waiting in linux-next for merging that's why
make sense to support them also in uboot.
zcu100, zcu104, zcu106, zcu111 are customer boards
zc12XX and zc1751 are internal boards.

Thanks,
Michal


Michal Simek (6):
  arm64: zynqmp: Add support for zcu100 aka 96ultra board
  arm64: zynqmp: Add support for zc1751 dc3
  arm64: zynqmp: Add support for zc12xx boards
  arm64: zynqmp: Add support for zcu104 customer board
  arm64: zynqmp: Add support for Xilinx zcu106-revA
  arm64: zynqmp: Add support for Xilinx zcu111-revA

 arch/arm/dts/Makefile  |   9 +
 arch/arm/dts/zynqmp-zc1232-revA.dts|  87 ++
 arch/arm/dts/zynqmp-zc1254-revA.dts|  72 ++
 arch/arm/dts/zynqmp-zc1275-revA.dts|  72 ++
 arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts   | 210 +
 arch/arm/dts/zynqmp-zcu100-revC.dts| 580 
 arch/arm/dts/zynqmp-zcu104-revA.dts| 481 ++
 arch/arm/dts/zynqmp-zcu104-revC.dts| 482 ++
 arch/arm/dts/zynqmp-zcu106-revA.dts| 884 ++
 arch/arm/dts/zynqmp-zcu111-revA.dts| 763 
 .../zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c   | 745 
 .../zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c   | 467 ++
 board/xilinx/zynqmp/zynqmp-zc1275-revA |   1 +
 .../zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c  | 900 +++
 .../zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c   | 993 +
 .../zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c   | 878 ++
 board/xilinx/zynqmp/zynqmp-zcu104-revC |   1 +
 .../zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c   | 802 +
 configs/xilinx_zynqmp_zc1232_revA_defconfig|  53 ++
 configs/xilinx_zynqmp_zc1254_revA_defconfig|  53 ++
 configs/xilinx_zynqmp_zc1275_revA_defconfig|  53 ++
 configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig   |  86 ++
 configs/xilinx_zynqmp_zcu100_revC_defconfig|  83 ++
 configs/xilinx_zynqmp_zcu104_revA_defconfig|  95 ++
 configs/xilinx_zynqmp_zcu104_revC_defconfig|  95 ++
 configs/xilinx_zynqmp_zcu106_revA_defconfig| 104 +++
 configs/xilinx_zynqmp_zcu111_revA_defconfig|  95 ++
 include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h   |  20 +
 include/configs/xilinx_zynqmp_zcu100.h |  39 +
 include/configs/xilinx_zynqmp_zcu104.h |  36 +
 include/configs/xilinx_zynqmp_zcu106.h |  47 +
 include/configs/xilinx_zynqmp_zcu111.h |  50 ++
 32 files changed, 9336 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-zc1232-revA.dts
 create mode 100644 arch/arm/dts/zynqmp-zc1254-revA.dts
 create mode 100644 arch/arm/dts/zynqmp-zc1275-revA.dts
 create mode 100644 arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
 create mode 100644 arch/arm/dts/zynqmp-zcu100-revC.dts
 create mode 100644 arch/arm/dts/zynqmp-zcu104-revA.dts
 create mode 100644 arch/arm/dts/zynqmp-zcu104-revC.dts
 create mode 100644 arch/arm/dts/zynqmp-zcu106-revA.dts
 create mode 100644 arch/arm/dts/zynqmp-zcu111-revA.dts
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
 create mode 12 board/xilinx/zynqmp/zynqmp-zc1275-revA
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
 create mode 100644 board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
 create mode 100644 board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
 create mode 12 board/xilinx/zynqmp/zynqmp-zcu104-revC
 create mode 100644 board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
 create mode 100644 configs/xilinx_zynqmp_zc1232_revA_defconfig
 create mode 100644 configs/xilinx_zynqmp_zc1254_revA_defconfig
 create mode 100644 configs/xilinx_zynqmp_zc1275_revA_defconfig
 create mode 100644 configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
 create mode 100644 configs/xilinx_zynqmp_zcu100_revC_defconfig
 create mode 100644 configs/xilinx_zynqmp_zcu104_revA_defconfig
 create mode 100644 configs/xilinx_zynqmp_zcu104_revC_defconfig
 create mode 100644 configs/xilinx_zynqmp_zcu106_revA_defconfig
 create mode 100644 configs/xilinx_zynqmp_zcu111_revA_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h
 create mode 100644 include/configs/xilinx_zynqmp_zcu100.h
 create mode 100644 include/configs/xilinx_zynqmp_zcu104.h
 create mode 100644 include/configs/xilinx_zynqmp_zcu106.h
 create mode 100644 include/configs/xilinx_zynqmp_zcu111.h

-- 
1.9.1

___
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[U-Boot] [PATCH 1/2] arm64: zynqmp: Add low level initialization for zcu102-revA

[Michal Simek]

Add psu init for zcu102-revA.

Signed-off-by: Michal Simek 
---

 .../zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c   | 826 +
 1 file changed, 826 insertions(+)
 create mode 100644 board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c

diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c 
b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
new file mode 100644
index ..aa6496c0b883
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
@@ -0,0 +1,826 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+
+static unsigned long psu_pll_init_data(void)
+{
+   psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+   psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+   psu_mask_write(0xFF5E0030, 0x0008U, 0x0008U);
+   psu_mask_write(0xFF5E0030, 0x0001U, 0x0001U);
+   psu_mask_write(0xFF5E0030, 0x0001U, 0xU);
+   mask_poll(0xFF5E0040, 0x0002U);
+   psu_mask_write(0xFF5E0030, 0x0008U, 0xU);
+   psu_mask_write(0xFF5E0048, 0x3F00U, 0x0300U);
+   psu_mask_write(0xFF5E0038, 0x8000U, 0xU);
+   psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+   psu_mask_write(0xFF5E0020, 0x00717F00U, 0x2D00U);
+   psu_mask_write(0xFF5E0020, 0x0008U, 0x0008U);
+   psu_mask_write(0xFF5E0020, 0x0001U, 0x0001U);
+   psu_mask_write(0xFF5E0020, 0x0001U, 0xU);
+   mask_poll(0xFF5E0040, 0x0001U);
+   psu_mask_write(0xFF5E0020, 0x0008U, 0xU);
+   psu_mask_write(0xFF5E0044, 0x3F00U, 0x0300U);
+   psu_mask_write(0xFF5E0028, 0x8000U, 0xU);
+   psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+   psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+   psu_mask_write(0xFD1A0020, 0x0008U, 0x0008U);
+   psu_mask_write(0xFD1A0020, 0x0001U, 0x0001U);
+   psu_mask_write(0xFD1A0020, 0x0001U, 0xU);
+   mask_poll(0xFD1A0044, 0x0001U);
+   psu_mask_write(0xFD1A0020, 0x0008U, 0xU);
+   psu_mask_write(0xFD1A0048, 0x3F00U, 0x0300U);
+   psu_mask_write(0xFD1A0028, 0x8000U, 0xU);
+   psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+   psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+   psu_mask_write(0xFD1A002C, 0x0008U, 0x0008U);
+   psu_mask_write(0xFD1A002C, 0x0001U, 0x0001U);
+   psu_mask_write(0xFD1A002C, 0x0001U, 0xU);
+   mask_poll(0xFD1A0044, 0x0002U);
+   psu_mask_write(0xFD1A002C, 0x0008U, 0xU);
+   psu_mask_write(0xFD1A004C, 0x3F00U, 0x0300U);
+   psu_mask_write(0xFD1A0034, 0x8000U, 0xU);
+   psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E514C62U);
+   psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00013900U);
+   psu_mask_write(0xFD1A0038, 0x0008U, 0x0008U);
+   psu_mask_write(0xFD1A0038, 0x0001U, 0x0001U);
+   psu_mask_write(0xFD1A0038, 0x0001U, 0xU);
+   mask_poll(0xFD1A0044, 0x0004U);
+   psu_mask_write(0xFD1A0038, 0x0008U, 0xU);
+   psu_mask_write(0xFD1A0050, 0x3F00U, 0x0300U);
+   psu_mask_write(0xFD1A0040, 0x8000U, 0x8000820CU);
+
+   return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+   psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+   psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+   psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+   psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+   psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
+   psu_mask_write(0xFF18030C, 0x0002U, 0xU);
+   psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+   psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+   psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+   psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+   psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+   psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+   psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+   psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+   psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+   psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+   psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+   psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+   psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+   psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+   psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U);
+   psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010302U);
+   psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+   psu_mask_write(0xFF5E0104, 0x0007U, 0xU);
+ 

[U-Boot] [PATCH 0/2] arm64: zynqmp: Add missing psu_init configuration files

[Michal Simek]

Hi,

this patchset is adding missing low level configuration files for
current boards supported by U-Boot.

Thanks,
Michal


Michal Simek (2):
  arm64: zynqmp: Add low level initialization for zcu102-revA
  arm64: zynqmp: Add low level initialization for zc1751

 .../zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c  | 912 
 .../zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c  | 900 
 .../zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c  | 900 
 .../zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c  | 926 +
 .../zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c   | 826 ++
 5 files changed, 4464 insertions(+)
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
 create mode 100644 board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
 create mode 100644 board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c

-- 
1.9.1

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[U-Boot] [PATCH 4/4] arm64: zynqmp: Enable Fixed link support

[Michal Simek]

This patch enables the fixed link support for
all ZynqMP boards.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
 configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 +
 configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 +
 configs/xilinx_zynqmp_zcu102_revA_defconfig  | 1 +
 configs/xilinx_zynqmp_zcu102_revB_defconfig  | 1 +
 6 files changed, 6 insertions(+)

diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 208e3e97c0a2..74a10b737d56 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -69,6 +69,7 @@ CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI=y
 CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 392efbb4156b..5876718fd2a3 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -65,6 +65,7 @@ CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI=y
 CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 456916b57288..51bccedbf58e 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -57,6 +57,7 @@ CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI=y
 CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 58c404e332fa..4e7f394f8a3b 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -75,6 +75,7 @@ CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI=y
 CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index 90ac04825450..a018398abb89 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -75,6 +75,7 @@ CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI=y
 CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 3a9d011cf3f6..9e6a1be60db5 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -75,6 +75,7 @@ CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI=y
 CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
-- 
1.9.1

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[U-Boot] [PATCH 2/4] arm64: zynqmp: Enable ethernet phys for zc1751 dc5

[Michal Simek]

Enable ethernet phys for zc1751 dc5.

Signed-off-by: Michal Simek 
---

 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 3dca21dc1650..ab6262f6df34 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -45,6 +45,12 @@ CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
-- 
1.9.1

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[U-Boot] [PATCH 3/4] arm64: zynqmp: Enable mac address randomization for zc1751 dc5

[Michal Simek]

There is no memory which stores mac address that's why generate it.

Signed-off-by: Michal Simek 
---

 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index ab6262f6df34..a8fab109f8aa 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_CLK_ZYNQMP=y
-- 
1.9.1

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[U-Boot] [PATCH 1/4] arm64: zynqmp: Enable booting to ATF

[Michal Simek]

From: Luca Ceresoli 

U-Boot is now able to boot to ARM Trusted Firmware (ATF). The boot
flow is SPL(EL3) loads ATF and full u-boot and jump to ATF(EL3) which
pass control to full u-boot(EL2). This has been tested on zcu106, so
enable it in this defconfig.

To generate an image that triggers this booting flow, you need to pass
'-O arm-trusted-firmware' to mkimage.

Signed-off-by: Luca Ceresoli 
Signed-off-by: Michal Simek 
---

 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
 configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 +
 configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 +
 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 +
 configs/xilinx_zynqmp_zcu102_revA_defconfig  | 1 +
 configs/xilinx_zynqmp_zcu102_revB_defconfig  | 1 +
 7 files changed, 7 insertions(+)

diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 1125ebda8a9f..208e3e97c0a2 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -18,6 +18,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_FASTBOOT=y
 CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 8fc13ef0ecc4..392efbb4156b 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_FASTBOOT=y
 CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 0a057bf3fefd..456916b57288 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -15,6 +15,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 47edf519f953..3dca21dc1650 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index cb3e2f5ca9f2..58c404e332fa 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -18,6 +18,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_FASTBOOT=y
 CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index 19b9683f023b..90ac04825450 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -18,6 +18,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_FASTBOOT=y
 CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index b660200508f9..3a9d011cf3f6 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -18,6 +18,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_FASTBOOT=y
 CONFIG_FASTBOOT_FLASH=y
-- 
1.9.1

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[U-Boot] [PATCH 0/4] arm64: zynqmp: Enable various kconfig features

[Michal Simek]

This patchset is enabling missing options were the most interesting one
is SPL_ATF which permits to boot system from one fit image file.

Thanks,
Michal


Luca Ceresoli (1):
  arm64: zynqmp: Enable booting to ATF

Michal Simek (3):
  arm64: zynqmp: Enable ethernet phys for zc1751 dc5
  arm64: zynqmp: Enable mac address randomization for zc1751 dc5
  arm64: zynqmp: Enable Fixed link support

 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 2 ++
 configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 2 ++
 configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 2 ++
 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 8 
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 2 ++
 configs/xilinx_zynqmp_zcu102_revA_defconfig  | 2 ++
 configs/xilinx_zynqmp_zcu102_revB_defconfig  | 2 ++
 7 files changed, 20 insertions(+)

-- 
1.9.1

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[U-Boot] [PATCH] arm64: zynqmp: Enable pxe and dhcp if commands are enabled

[Michal Simek]

Targets without net can't use pxe or dhcp boot methods.

Signed-off-by: Michal Simek 
---

 include/configs/xilinx_zynqmp.h | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 8c0b5d9c06ae..635e2d1292df 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -174,12 +174,24 @@
 # define BOOT_TARGET_DEVICES_USB(func)
 #endif
 
+#if defined(CONFIG_CMD_PXE)
+# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#if defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_DHCP(func)func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
 #define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
-   func(PXE, pxe, na) \
-   func(DHCP, dhcp, na)
+   BOOT_TARGET_DEVICES_PXE(func) \
+   BOOT_TARGET_DEVICES_DHCP(func)
 
 #include 
 
-- 
1.9.1

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[U-Boot] [PATCH] net: phy: xilinx_phy: Read phytype using property xlnx, phy-type

[Michal Simek]

From: Siva Durga Prasad Paladugu 

This patch reads phytype from property "xlnx,phy-type" instead
od simply looking for "phy-type". This is to be inline with
Linux and also fixes the issue of detecting it wrongly in
u-boot.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 drivers/net/phy/xilinx_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c
index 3f80f0495e8d..7142a99ce580 100644
--- a/drivers/net/phy/xilinx_phy.c
+++ b/drivers/net/phy/xilinx_phy.c
@@ -105,7 +105,7 @@ static int xilinxphy_of_init(struct phy_device *phydev)
 
debug("%s\n", __func__);
phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
-"phy-type", -1);
+"xlnx,phy-type", -1);
if (phytype == XAE_PHY_TYPE_1000BASE_X)
phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
 
-- 
1.9.1

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[U-Boot] [PATCH] axi: ethernet: Added support for 64 bit addressing for axi-ethernet

[Michal Simek]

From: Vipul Kumar 

This patch uses writeq() function to enable greater than 32 bit
addressing of axi-ethernet for the ZynqMP devices.

Signed-off-by: Vipul Kumar 
Signed-off-by: Michal Simek 
---

 drivers/net/xilinx_axi_emac.c | 33 +
 1 file changed, 25 insertions(+), 8 deletions(-)

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 70a2e95a8ec1..80ed06ac66c9 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -78,9 +78,10 @@ static u8 rxframe[PKTSIZE_ALIGN] 
__attribute((aligned(DMAALIGN)));
 struct axidma_reg {
u32 control; /* DMACR */
u32 status; /* DMASR */
-   u32 current; /* CURDESC */
-   u32 reserved;
-   u32 tail; /* TAILDESC */
+   u32 current; /* CURDESC low 32 bit */
+   u32 current_hi; /* CURDESC high 32 bit */
+   u32 tail; /* TAILDESC low 32 bit */
+   u32 tail_hi; /* TAILDESC high 32 bit */
 };
 
 /* Private driver structures */
@@ -168,6 +169,22 @@ static inline int mdio_wait(struct axi_regs *regs)
return 0;
 }
 
+/**
+ * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
+ * @bd:pointer to BD descriptor structure
+ * @desc:  Address offset of DMA descriptors
+ *
+ * This function writes the value into the corresponding Axi DMA register.
+ */
+static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
+{
+#if defined(CONFIG_PHYS_64BIT)
+   writeq(bd, desc);
+#else
+   writel((u32)bd, desc);
+#endif
+}
+
 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
   u16 *val)
 {
@@ -465,7 +482,7 @@ static int axiemac_start(struct udevice *dev)
writel(temp, >dmarx->control);
 
/* Start DMA RX channel. Now it's ready to receive data.*/
-   writel((u32)_bd, >dmarx->current);
+   axienet_dma_write(_bd, >dmarx->current);
 
/* Setup the BD. */
memset(_bd, 0, sizeof(rx_bd));
@@ -485,7 +502,7 @@ static int axiemac_start(struct udevice *dev)
writel(temp, >dmarx->control);
 
/* Rx BD is ready - start */
-   writel((u32)_bd, >dmarx->tail);
+   axienet_dma_write(_bd, >dmarx->tail);
 
/* Enable TX */
writel(XAE_TC_TX_MASK, >tc);
@@ -527,7 +544,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int 
len)
 
if (readl(>dmatx->status) & XAXIDMA_HALTED_MASK) {
u32 temp;
-   writel((u32)_bd, >dmatx->current);
+   axienet_dma_write(_bd, >dmatx->current);
/* Start the hardware */
temp = readl(>dmatx->control);
temp |= XAXIDMA_CR_RUNSTOP_MASK;
@@ -535,7 +552,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int 
len)
}
 
/* Start transfer */
-   writel((u32)_bd, >dmatx->tail);
+   axienet_dma_write(_bd, >dmatx->tail);
 
/* Wait for transmission to complete */
debug("axiemac: Waiting for tx to be done\n");
@@ -626,7 +643,7 @@ static int axiemac_free_pkt(struct udevice *dev, uchar 
*packet, int length)
flush_cache((u32), sizeof(rxframe));
 
/* Rx BD is ready - start again */
-   writel((u32)_bd, >dmarx->tail);
+   axienet_dma_write(_bd, >dmarx->tail);
 
debug("axiemac: RX completed, framelength = %d\n", length);
 
-- 
1.9.1

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[U-Boot] [PATCH] nand: arasan_nfc: Fixed NAND write issue

[Michal Simek]

From: Vipul Kumar 

In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0x and the same macro is used in nand write and so that getting
nand write error.
This patch reverted this macro to the 0x and used
ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function
which is equal to 0x.

Signed-off-by: Vipul Kumar 
Signed-off-by: Michal Simek 
---

 drivers/mtd/nand/arasan_nfc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 9c82c7db33fb..3be66efb73f6 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -86,7 +86,7 @@ struct arasan_nand_command_format {
 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x7000
 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT28
 
-#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK0x
+#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK0x
 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0x
 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT   16
 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK0xFF
@@ -796,7 +796,7 @@ static int arasan_nand_erase(struct 
arasan_nand_command_format *curr_cmd,
writel(reg_val, _nand_base->cmd_reg);
 
page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
-   ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
+   ARASAN_NAND_MEM_ADDR1_COL_MASK;
column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
   _nand_base->memadr_reg1);
-- 
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[U-Boot] [PATCH] fpga: zynq: Add delay after PCFG_PROG_B change

[Michal Simek]

From: Siva Durga Prasad Paladugu 

There is delay needed after PCFG_PROGB change if
AES key source is efuse. This fixes the issue of
encrypted bitstream loading with AES efuse as key
source.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 drivers/fpga/zynqpl.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 2ff716c25228..db9bd12992f9 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -17,6 +17,7 @@
 #include 
 
 #define DEVCFG_CTRL_PCFG_PROG_B0x4000
+#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK0x1000
 #define DEVCFG_ISR_FATAL_ERROR_MASK0x00740040
 #define DEVCFG_ISR_ERROR_FLAGS_MASK0x00340840
 #define DEVCFG_ISR_RX_FIFO_OV  0x0004
@@ -205,9 +206,24 @@ static int zynq_dma_xfer_init(bitstream_type bstype)
/* Setting PCFG_PROG_B signal to high */
control = readl(_base->ctrl);
writel(control | DEVCFG_CTRL_PCFG_PROG_B, _base->ctrl);
+
+   /*
+* Delay is required if AES efuse is selected as
+* key source.
+*/
+   if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+   mdelay(5);
+
/* Setting PCFG_PROG_B signal to low */
writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, _base->ctrl);
 
+   /*
+* Delay is required if AES efuse is selected as
+* key source.
+*/
+   if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+   mdelay(5);
+
/* Polling the PCAP_INIT status for Reset */
ts = get_timer(0);
while (readl(_base->status) & DEVCFG_STATUS_PCFG_INIT) {
-- 
1.9.1

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[U-Boot] [PATCH 2/3] fpga: zynqmp: Update zynqmp_load() as per latest xilfpga

[Michal Simek]

From: Siva Durga Prasad Paladugu 

Latest xilfpga expects to set BIT5 of flags for nonsecure
bitsream and also expects length in bytes instead of words
This patch does the same.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 ++
 drivers/fpga/zynqmppl.c  | 6 +-
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h 
b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index ad3dc9aba50d..3daf0e81d80c 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -14,6 +14,8 @@
 #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD  0xC22D
 #define KEY_PTR_LEN32
 
+#define ZYNQMP_FPGA_BIT_NS 5
+
 enum {
IDCODE,
VERSION,
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 80388ae7f2cf..aae0efc7348e 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -209,13 +209,9 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, 
size_t bsize,
debug("%s called!\n", __func__);
flush_dcache_range(bin_buf, bin_buf + bsize);
 
-   if (bsize % 4)
-   bsize = bsize / 4 + 1;
-   else
-   bsize = bsize / 4;
-
buf_lo = (u32)bin_buf;
buf_hi = upper_32_bits(bin_buf);
+   bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize,
 bstype, ret_payload);
if (ret)
-- 
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[U-Boot] [PATCH 3/3] fpga: zynqmp: Fix the nonsecure bitstream loading issue

[Michal Simek]

From: Siva Durga Prasad Paladugu 

Xilfpga library expects the size of bitstream in a pointer
but currenly we are passing the size as a value. This patch
fixes this issue.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Nava kishore Manne 
Signed-off-by: Michal Simek 
---

 drivers/fpga/zynqmppl.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index aae0efc7348e..43e8b2520e35 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define DUMMY_WORD 0x
 
@@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, 
const void *buf,
 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 bitstream_type bstype)
 {
+   ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
u32 swap;
ulong bin_buf;
int ret;
@@ -205,15 +207,17 @@ static int zynqmp_load(xilinx_desc *desc, const void 
*buf, size_t bsize,
return FPGA_FAIL;
 
bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
+   bsizeptr = (u32 *)
 
debug("%s called!\n", __func__);
flush_dcache_range(bin_buf, bin_buf + bsize);
+   flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
 
buf_lo = (u32)bin_buf;
buf_hi = upper_32_bits(bin_buf);
bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
-   ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize,
-bstype, ret_payload);
+   ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+(u32)(uintptr_t)bsizeptr, bstype, ret_payload);
if (ret)
debug("PL FPGA LOAD fail\n");
 
-- 
1.9.1

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[U-Boot] [PATCH 1/3] fpga: zynqmp: Add support to get the PCAP status for fpga info command

[Michal Simek]

From: Nitin Jain 

This patch adds support for ZynqMP platform to print FPGA PCAP status
for "fpga status" command.

Signed-off-by: Nitin Jain 
Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 drivers/fpga/zynqmppl.c | 14 ++
 include/zynqmppl.h  |  1 +
 2 files changed, 15 insertions(+)

diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 57a4e6c88e7a..80388ae7f2cf 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -224,6 +224,20 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, 
size_t bsize,
return ret;
 }
 
+static int zynqmp_pcap_info(xilinx_desc *desc)
+{
+   int ret;
+   u32 ret_payload[PAYLOAD_ARG_CNT];
+
+   ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
+0, ret_payload);
+   if (!ret)
+   printf("PCAP status\t0x%x\n", ret_payload[1]);
+
+   return ret;
+}
+
 struct xilinx_fpga_op zynqmp_op = {
.load = zynqmp_load,
+   .info = zynqmp_pcap_info,
 };
diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index 4c8c2f88f04c..8b3ce8ef7706 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -12,6 +12,7 @@
 
 #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID  0xC218
 #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD0xC216
+#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS  0xC217
 #define ZYNQMP_FPGA_OP_INIT(1 << 0)
 #define ZYNQMP_FPGA_OP_LOAD(1 << 1)
 #define ZYNQMP_FPGA_OP_DONE(1 << 2)
-- 
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[U-Boot] [PATCH 0/3] fpga: zynqmp: Fpga changes

[Michal Simek]

Hi,

these patches are syncing latest firmware expectation and showing
information about fpga status.

Thanks,
Michal


Nitin Jain (1):
  fpga: zynqmp: Add support to get the PCAP status for fpga info command

Siva Durga Prasad Paladugu (2):
  fpga: zynqmp: Update zynqmp_load() as per latest xilfpga
  fpga: zynqmp: Fix the nonsecure bitstream loading issue

 arch/arm/include/asm/arch-zynqmp/sys_proto.h |  2 ++
 drivers/fpga/zynqmppl.c  | 28 +---
 include/zynqmppl.h   |  1 +
 3 files changed, 24 insertions(+), 7 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH] clk: zynqmp: Add new compatible string for clock driver

[Michal Simek]

New and old clk drivers are sharing IDs and descriptions.

Signed-off-by: Michal Simek 
---

 drivers/clk/clk_zynqmp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 4ef8662af560..d0d6c898bc58 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -702,6 +702,7 @@ static struct clk_ops zynqmp_clk_ops = {
 };
 
 static const struct udevice_id zynqmp_clk_ids[] = {
+   { .compatible = "xlnx,zynqmp-clk" },
{ .compatible = "xlnx,zynqmp-clkc" },
{ }
 };
-- 
1.9.1

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[U-Boot] [PATCH 2/6] arm: zynq: Sync up licenses with mainline kernel

[Michal Simek]

Use different location for SPDX line. Also update dates for new mainline
DTS files.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynq-cc108.dts   | 5 ++---
 arch/arm/dts/zynq-zc702.dts   | 5 +
 arch/arm/dts/zynq-zc706.dts   | 5 +
 arch/arm/dts/zynq-zc770-xm010.dts | 5 ++---
 arch/arm/dts/zynq-zc770-xm011.dts | 5 ++---
 arch/arm/dts/zynq-zc770-xm012.dts | 5 ++---
 arch/arm/dts/zynq-zc770-xm013.dts | 3 +--
 arch/arm/dts/zynq-zed.dts | 5 +
 arch/arm/dts/zynq-zybo.dts| 5 +
 9 files changed, 13 insertions(+), 30 deletions(-)

diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts
index b9cc000a33e9..5f8a0d255529 100644
--- a/arch/arm/dts/zynq-cc108.dts
+++ b/arch/arm/dts/zynq-cc108.dts
@@ -1,13 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Xilinx CC108 board DTS
  *
- * (C) Copyright 2007-2013 Xilinx, Inc.
+ * (C) Copyright 2007-2018 Xilinx, Inc.
  * (C) Copyright 2007-2013 Michal Simek
  * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
  *
  * Michal SIMEK 
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 /dts-v1/;
 /include/ "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index da698a19ccd1..b95c1608d220 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Xilinx ZC702 board DTS
- *
  *  Copyright (C) 2011 - 2015 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index a88a83c16650..dbb57445ca7c 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Xilinx ZC706 board DTS
- *
  *  Copyright (C) 2011 - 2015 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts 
b/arch/arm/dts/zynq-zc770-xm010.dts
index cc5ba98d6bd9..0c364dfcc14f 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Xilinx ZC770 XM010 board DTS
  *
- * Copyright (C) 2013 - 2015 Xilinx, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
+ * Copyright (C) 2013-2018 Xilinx, Inc.
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts 
b/arch/arm/dts/zynq-zc770-xm011.dts
index 7f08961491a6..f711675dd88e 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Xilinx ZC770 XM013 board DTS
  *
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
+ * Copyright (C) 2013-2018 Xilinx, Inc.
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts 
b/arch/arm/dts/zynq-zc770-xm012.dts
index 699cd2c0fb1c..ee6809d51bcf 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Xilinx ZC770 XM012 board DTS
  *
- * Copyright (C) 2013 - 2015 Xilinx, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
+ * Copyright (C) 2013-2018 Xilinx, Inc.
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts 
b/arch/arm/dts/zynq-zc770-xm013.dts
index 81a6aa562a94..88a7ef068219 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Xilinx ZC770 XM013 board DTS
  *
  * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index a9ff0e6fa814..24eccf1633d8 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Xilinx ZED board DTS
- *
  *  Copyright (C) 2011 - 2015 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index 52ec5a45667a..38448223055c 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Digilent ZYBO board DTS
- *
  *  Copyright (C) 2011 - 2015 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
-- 
1.9.1

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[U-Boot] [PATCH 5/6] arm: zynq: Fix eeprom dt nodes

[Michal Simek]

- Use eeprom for node name
- Use atmel compatible string instead of at.
- Add missing labels

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynq-zc770-xm010.dts | 4 ++--
 arch/arm/dts/zynq-zc770-xm011.dts | 4 ++--
 arch/arm/dts/zynq-zc770-xm012.dts | 8 
 arch/arm/dts/zynq-zc770-xm013.dts | 2 +-
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/dts/zynq-zc770-xm010.dts 
b/arch/arm/dts/zynq-zc770-xm010.dts
index 0c364dfcc14f..2c594b7ecc6c 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -54,8 +54,8 @@
status = "okay";
clock-frequency = <40>;
 
-   m24c02_eeprom@52 {
-   compatible = "at,24c02";
+   eeprom: eeprom@52 {
+   compatible = "atmel,24c02";
reg = <0x52>;
};
 
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts 
b/arch/arm/dts/zynq-zc770-xm011.dts
index f711675dd88e..3fe6eb559ea7 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -41,8 +41,8 @@
status = "okay";
clock-frequency = <40>;
 
-   m24c02_eeprom@52 {
-   compatible = "at,24c02";
+   eeprom: eeprom@52 {
+   compatible = "atmel,24c02";
reg = <0x52>;
};
 };
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts 
b/arch/arm/dts/zynq-zc770-xm012.dts
index ee6809d51bcf..19d5b275ae06 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -37,8 +37,8 @@
status = "okay";
clock-frequency = <40>;
 
-   m24c02_eeprom@52 {
-   compatible = "at,24c02";
+   eeprom0: eeprom@52 {
+   compatible = "atmel,24c02";
reg = <0x52>;
};
 };
@@ -47,8 +47,8 @@
status = "okay";
clock-frequency = <40>;
 
-   m24c02_eeprom@52 {
-   compatible = "at,24c02";
+   eeprom1: eeprom@52 {
+   compatible = "atmel,24c02";
reg = <0x52>;
};
 };
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts 
b/arch/arm/dts/zynq-zc770-xm013.dts
index 88a7ef068219..efd0833eab91 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -67,7 +67,7 @@
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
-   eeprom: at25@0 {
+   eeprom: eeprom@0 {
at25,byte-len = <8192>;
at25,addr-mode = <2>;
at25,page-size = <32>;
-- 
1.9.1

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[U-Boot] [PATCH 4/6] ARM: dts: zynq: Add generic compatible string for I2C EEPROM

[Michal Simek]

From: Javier Martinez Canillas 

The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.

But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.

So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.

Signed-off-by: Javier Martinez Canillas 
Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynq-zc702.dts | 2 +-
 arch/arm/dts/zynq-zc706.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 1410c4d7b6bd..bb224662bb77 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -151,7 +151,7 @@
#size-cells = <0>;
reg = <2>;
eeprom@54 {
-   compatible = "at,24c08";
+   compatible = "atmel,24c08";
reg = <0x54>;
};
};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index c782064a8036..f24364b3853a 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -102,7 +102,7 @@
#size-cells = <0>;
reg = <2>;
eeprom@54 {
-   compatible = "at,24c08";
+   compatible = "atmel,24c08";
reg = <0x54>;
};
};
-- 
1.9.1

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[U-Boot] [PATCH 3/6] arm: zynq: Use i2c-mux instead of i2cswitch for pca9548

[Michal Simek]

i2c muxes should described like this.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynq-zc702.dts | 2 +-
 arch/arm/dts/zynq-zc706.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index b95c1608d220..1410c4d7b6bd 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -111,7 +111,7 @@
scl-gpios = < 50 0>;
sda-gpios = < 51 0>;
 
-   i2cswitch@74 {
+   i2c-mux@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index dbb57445ca7c..c782064a8036 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -62,7 +62,7 @@
pinctrl-names = "default";
pinctrl-0 = <_i2c0_default>;
 
-   i2cswitch@74 {
+   i2c-mux@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
-- 
1.9.1

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[U-Boot] [PATCH 6/6] arm: zynq: Use fixed partitions for spi flash for zc770 xm010

[Michal Simek]

Sync with mainline.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynq-zc770-xm010.dts | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/zynq-zc770-xm010.dts 
b/arch/arm/dts/zynq-zc770-xm010.dts
index 2c594b7ecc6c..a779672f3add 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -74,14 +74,17 @@
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
-   compatible = "sst25wf080";
+   compatible = "sst25wf080", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <100>;
-   #address-cells = <1>;
-   #size-cells = <1>;
-   partition@test {
-   label = "spi-flash";
-   reg = <0x0 0x10>;
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   partition@0 {
+   label = "data";
+   reg = <0x0 0x10>;
+   };
};
};
 };
-- 
1.9.1

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[U-Boot] [PATCH 1/6] arm: zynq: Remove 0x prefixes from cc108

[Michal Simek]

The patch fixing issues reported by DTC:
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x40 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x80 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xc0 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xd0 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xf0 unit name should not have
leading "0x"

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynq-cc108.dts | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts
index 4804da5235dd..b9cc000a33e9 100644
--- a/arch/arm/dts/zynq-cc108.dts
+++ b/arch/arm/dts/zynq-cc108.dts
@@ -70,23 +70,23 @@
label = "qspi-fsbl-uboot-bs";
reg = <0x0 0x40>; /* 4MB */
};
-   partition@0x40 {
+   partition@40 {
label = "qspi-linux";
reg = <0x40 0x40>; /* 4MB */
};
-   partition@0x80 {
+   partition@80 {
label = "qspi-rootfs";
reg = <0x80 0x40>; /* 4MB */
};
-   partition@0xc0 {
+   partition@c0 {
label = "qspi-devicetree";
reg = <0xc0 0x10>; /* 1MB */
};
-   partition@0xd0 {
+   partition@d0 {
label = "qspi-scratch";
reg = <0xd0 0x20>; /* 2MB */
};
-   partition@0xf0 {
+   partition@f0 {
label = "qspi-uboot-env";
reg = <0xf0 0x10>; /* 1MB */
};
-- 
1.9.1

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[U-Boot] [PATCH 0/6] arm: Fix zynq DTS file with mainline Linux kernel

[Michal Simek]

Hi,

with reviewing new Xilinx platforms for Linux kernel some issues were
found which should be fixed.
Also Kernel adopted SPDX that's why position has changed.
Based on my talk with Tom it is not a problem to adopt Linux kernel
style and keep these dts in sync.

Thanks,
Michal


Javier Martinez Canillas (1):
  ARM: dts: zynq: Add generic compatible string for I2C EEPROM

Michal Simek (5):
  arm: zynq: Remove 0x prefixes from cc108
  arm: zynq: Sync up licenses with mainline kernel
  arm: zynq: Use i2c-mux instead of i2cswitch for pca9548
  arm: zynq: Fix eeprom dt nodes
  arm: zynq: Use fixed partitions for spi flash for zc770 xm010

 arch/arm/dts/zynq-cc108.dts   | 15 +++
 arch/arm/dts/zynq-zc702.dts   |  9 +++--
 arch/arm/dts/zynq-zc706.dts   |  9 +++--
 arch/arm/dts/zynq-zc770-xm010.dts | 24 +---
 arch/arm/dts/zynq-zc770-xm011.dts |  9 -
 arch/arm/dts/zynq-zc770-xm012.dts | 13 ++---
 arch/arm/dts/zynq-zc770-xm013.dts |  5 ++---
 arch/arm/dts/zynq-zed.dts |  5 +
 arch/arm/dts/zynq-zybo.dts|  5 +
 9 files changed, 40 insertions(+), 54 deletions(-)

-- 
1.9.1

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Re: [U-Boot] [PATCH v4 13/19] sunxi: DT: A64: update board .dts files from Linux

[Andre Przywara]

Hi,

On 28/03/18 10:52, Jagan Teki wrote:
> On Wed, Mar 28, 2018 at 4:23 AM, André Przywara  
> wrote:
>> On 27/03/18 18:58, Jagan Teki wrote:
>>> On Sat, Mar 24, 2018 at 6:37 AM, André Przywara  
>>> wrote:
 On 23/03/18 18:14, Jagan Teki wrote:
> On Wed, Mar 14, 2018 at 7:27 AM, Andre Przywara  
> wrote:
>> Update the .dts files for the various boards with an Allwinner A64 SoC.
>> This is as of v4.15-rc9, exactly Linux commit:

 

>>
>>   {
>> pinctrl-names = "default";
>> pinctrl-0 = <_pins>;
>> -   vmmc-supply = <_vcc3v3>;
>> +   vmmc-supply = <_dcdc1>;
>
> These AXP regulator stuff need to wait until the relevant driver
> supported through dt

 Well, we could take the two patches I had in v3 that revert this change.
 As mentioned before, DCDC1 is an always-on regulator anyways.
>>>
>>> May it's good option to look at v3 changes, since DM_MMC Migration
>>> expires in coming release, dt changes which are related to MMC we can
>>> wait for proper supported feature get IN(like pinctrl, clock, reset),
>>> that means we should anyway need to move DM_MMC but with working dt
>>> changes.
>>>
>>> The big question for me here is about SPL, I'm sure we can get the
>>> size issues. May be we try platdata but in any case we need to enable
>>> DM ie increase the size (atleast for A64, H5)
>>
>> So my understanding is that those DM_ defines are just for
>> U-Boot proper, and the SPL needs extra symbols to be also "DMed".
> 
> I don't think so, Idea about migrating to BLK, DM_MMC should remove
> #ifdef code with DM vs non-DM such that the driver should have DM
> version with DT along with PLATDATA

Yes, but how do you want to make this happen in the one remaining week
of the merge window? For some reason I was totally unaware of this
deadline, and we should have started working on this months ago. But my
DeLorean is in the garage, so we can only look forward from here.

Which means we start with just DM_MMC, but not DM_SPL_MMC, and hope that
this threat of "Boards not converted by this time may be removed in a
subsequent release." does not really apply to sunxi as strictly as put
in this file.

The rest comes over time, giving us opportunity to find solutions for
the space constraint problems.

>> See the definition of CONFIG_IS_ENABLED().
>> So by just #defining CONFIG_DM_MMC the SPL still looks the same (using
>> the non-DM code), and indeed I don't run into size issues with the SPL.
> 
> Even to use DM_MMC in SPL we should enable SPL_DM so I'm unable to
> build SPL even with SPL_DM=y

??? I said we should *not* #define DM_SPL_MMC, because of (not only)
this reason. If we follow Heinrich's patch, it just selects DM_MMC, so
no changes for the SPL.

> SPL build, with SPL_DM_, SPL_DM_MMC, SPL_OF_PLATDATA
> 
> aarch64-linux-gnu-ld.bfd: address 0x18d18 of u-boot-spl section
> `.text' is not within region `.sram'
> aarch64-linux-gnu-ld.bfd: u-boot-spl section `.rodata' will not fit in
> region `.sram'
> aarch64-linux-gnu-ld.bfd: address 0x18d18 of u-boot-spl section
> `.text' is not within region `.sram'
> aarch64-linux-gnu-ld.bfd: address 0x18d18 of u-boot-spl section
> `.text' is not within region `.sram'
> aarch64-linux-gnu-ld.bfd: region `.sram' overflowed by 11104 bytes

Sure, no surprise.

>> Given the uniformity of at least the MMC device in sunxi, I think in the
>> medium term  we get away with some simple platdata, without pulling the
>> DT into SPL. The clocks might be a bit more hairy here, though. But
>> that's nothing for *now* to solve.
> 
> platdata available only for SPL, not for U-Boot proper.

Yes, that's what I meant: fixed platdata for SPL, U-Boot proper gets the
full DT glory.

> I agree that clock might be more hairy for now. and we can go with DT
> for U-Boot proper and just grab the minimum properties which are
> required for probe and rest we can use the driver as before, so-that
> regulator, clock, gpio, reset, pinctrl we use step by step.

That is what I was trying to say ;-)

Cheers,
Andre.
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Re: [U-Boot] [PATCH 0/4] Meson clock driver

[Neil Armstrong]

On 28/03/2018 12:52, Beniamino Galvani wrote:
> 2018-03-28 10:59 GMT+02:00 Neil Armstrong :
> 
>> Do you plan to re-send the driver soon ?
> 
> Yes, I plan to submit it again in the next days.
> 
> Beniamino
> 
Cool ! Thanks !

Can you base it after my "ARM: meson: rename GXBB to GX" patch ?

It will be simpler to merge everything !

Thanks,
Neil
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[U-Boot] [PATCH V3 1/6] net: fec_mxc: Fix DM driver issue in recv

[Peng Fan]

From: Ye Li 

When using ethernet DM driver, the recv interface has a
change with non-DM interface, that driver needs to set
the packet pointer and provide it to upper layer to process.

In fec driver, the fecmxc_recv functions does not handle the
packet pointer parameter. This may cause crash in upper layer
processing because the packet pointer is not set.

This patch allocates a buffer for the packet pointer and free it
through free_pkt interface.

Signed-off-by: Ye Li 
Reviewed-by: Peng Fan 
Acked-by: Joe Hershberger 
---

V3: None
V2:
 Fix build warning for mx28

 drivers/net/fec_mxc.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ff7ad91116..617e504293 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -806,7 +806,16 @@ static int fec_recv(struct eth_device *dev)
uint16_t bd_status;
ulong addr, size, end;
int i;
+
+#ifdef CONFIG_DM_ETH
+   *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
+   if (*packetp == 0) {
+   printf("%s: error allocating packetp\n", __func__);
+   return -ENOMEM;
+   }
+#else
ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
+#endif
 
/* Check if any critical events have happened */
ievent = readl(>eth->ievent);
@@ -882,8 +891,13 @@ static int fec_recv(struct eth_device *dev)
 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)addr, frame_length);
 #endif
+
+#ifdef CONFIG_DM_ETH
+   memcpy(*packetp, (char *)addr, frame_length);
+#else
memcpy(buff, (char *)addr, frame_length);
net_process_received_packet(buff, frame_length);
+#endif
len = frame_length;
} else {
if (bd_status & FEC_RBD_ERR)
@@ -1201,10 +1215,19 @@ static int fecmxc_read_rom_hwaddr(struct udevice *dev)
return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
 }
 
+static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+   if (packet)
+   free(packet);
+
+   return 0;
+}
+
 static const struct eth_ops fecmxc_ops = {
.start  = fecmxc_init,
.send   = fecmxc_send,
.recv   = fecmxc_recv,
+   .free_pkt   = fecmxc_free_pkt,
.stop   = fecmxc_halt,
.write_hwaddr   = fecmxc_set_hwaddr,
.read_rom_hwaddr= fecmxc_read_rom_hwaddr,
-- 
2.14.1

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[U-Boot] [PATCH V3 6/6] net: fec: Fix issue in DM probe timeout

[Peng Fan]

From: Ye Li 

Since the probe function has changed to reset FEC controller prior than
setup PHY. If reset FEC controller timeout, the priv->phydev is not
initialized, so can't free it.

Signed-off-by: Ye Li 
---

V3: New

 drivers/net/fec_mxc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 765226e3ab..4caeddb34d 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1291,12 +1291,11 @@ static int fecmxc_probe(struct udevice *dev)
 
return 0;
 
-err_timeout:
-   free(priv->phydev);
 err_phy:
mdio_unregister(bus);
free(bus);
 err_mii:
+err_timeout:
fec_free_descs(priv);
return ret;
 }
-- 
2.14.1

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[U-Boot] [PATCH V3 3/6] net: fec: set dev->seq to priv->dev_id

[Peng Fan]

To platforms has two enet interface, using dev->seq could
avoid conflict.

i.MX6UL/ULL evk board net get the wrong MAC address from fuse,
eth1 get MAC0 address, eth0 get MAC1 address from fuse. Set the
priv->dev_id to device->seq as the real net interface alias id then
.fec_get_hwaddr() read the related MAC address from fuse.

Signed-off-by: Peng Fan 
Acked-by: Joe Hershberger 
---

V3: None
V2: None

 drivers/net/fec_mxc.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 953252a92e..4f1c906a72 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1250,7 +1250,6 @@ static int fecmxc_probe(struct udevice *dev)
struct eth_pdata *pdata = dev_get_platdata(dev);
struct fec_priv *priv = dev_get_priv(dev);
struct mii_dev *bus = NULL;
-   int dev_id = -1;
uint32_t start;
int ret;
 
@@ -1271,9 +1270,9 @@ static int fecmxc_probe(struct udevice *dev)
}
 
fec_reg_setup(priv);
-   priv->dev_id = (dev_id == -1) ? 0 : dev_id;
 
-   bus = fec_get_miibus((ulong)priv->eth, dev_id);
+   priv->dev_id = dev->seq;
+   bus = fec_get_miibus((ulong)priv->eth, dev->seq);
if (!bus) {
ret = -ENOMEM;
goto err_mii;
-- 
2.14.1

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[U-Boot] [PATCH V3 5/6] net: fex_mxc: add i.MX6UL/SX/SL compatible

[Peng Fan]

Add i.MX6UL/SX/SL compatible.

Signed-off-by: Peng Fan 
Acked-by: Joe Hershberger 
---

V3: None
V2: None

 drivers/net/fec_mxc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ba66c2f95a..765226e3ab 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1342,6 +1342,9 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev)
 
 static const struct udevice_id fecmxc_ids[] = {
{ .compatible = "fsl,imx6q-fec" },
+   { .compatible = "fsl,imx6sl-fec" },
+   { .compatible = "fsl,imx6sx-fec" },
+   { .compatible = "fsl,imx6ul-fec" },
{ }
 };
 
-- 
2.14.1

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[U-Boot] [PATCH V3 4/6] net: fec: sharing MDIO for two enet controllers

[Peng Fan]

On i.MX6SX, 6UL and 7D, there are two enet controllers each has a
MDIO port. But Some boards share one MDIO port for the two enets. So
introduce a configuration CONFIG_FEC_MXC_MDIO_BASE to indicate
the MDIO port for sharing.
In Kconfig, user needs enable CONFIG_FEC_MXC_SHARE_MDIO first to enter
the CONFIG_FEC_MXC_MDIO_BASE.

To i.MX28, adapt to use the new config

Signed-off-by: Peng Fan 
Acked-by: Joe Hershberger 
Cc: Fabio Estevam 
---

V3:
 Fix build error. Add a new FEC_MXC_SHARE_MDIO Kconfig for MDIO.

 drivers/net/Kconfig   | 13 -
 drivers/net/fec_mxc.c |  8 ++--
 include/configs/mx28evk.h |  1 +
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index de1947ccc1..c4cbe34798 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -147,9 +147,20 @@ config ETHOC
help
  This MAC is present in OpenRISC and Xtensa XTFPGA boards.
 
+config FEC_MXC_SHARE_MDIO
+   bool "Share the MDIO bus for FEC controller"
+   depends on FEC_MXC
+
+config FEC_MXC_MDIO_BASE
+   hex "MDIO base address for the FEC controller"
+   depends on FEC_MXC_SHARE_MDIO
+   help
+ This specifies the MDIO registers base address. It is used when
+ two FEC controllers share MDIO bus.
+
 config FEC_MXC
bool "FEC Ethernet controller"
-   depends on MX5 || MX6
+   depends on MX5 || MX6 || MX7
help
  This driver supports the 10/100 Fast Ethernet controller for
  NXP i.MX processors.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4f1c906a72..ba66c2f95a 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1145,12 +1145,12 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int 
phy_id, uint32_t addr)
 #endif
int ret;
 
-#ifdef CONFIG_MX28
+#ifdef CONFIG_FEC_MXC_MDIO_BASE
/*
 * The i.MX28 has two ethernet interfaces, but they are not equal.
 * Only the first one can access the MDIO bus.
 */
-   base_mii = MXS_ENET0_BASE;
+   base_mii = CONFIG_FEC_MXC_MDIO_BASE;
 #else
base_mii = addr;
 #endif
@@ -1272,7 +1272,11 @@ static int fecmxc_probe(struct udevice *dev)
fec_reg_setup(priv);
 
priv->dev_id = dev->seq;
+#ifdef CONFIG_FEC_MXC_MDIO_BASE
+   bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
+#else
bus = fec_get_miibus((ulong)priv->eth, dev->seq);
+#endif
if (!bus) {
ret = -ENOMEM;
goto err_mii;
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index bc58ca5c62..79d4c9b2ce 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -65,6 +65,7 @@
 /* FEC Ethernet on SoC */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE
 #define CONFIG_MX28_FEC_MAC_IN_OCOTP
 #endif
 
-- 
2.14.1

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[U-Boot] [PATCH 3/4] tsec: Fix reading phy registers from DT

[Mario Six]

Bus translations should be applied when reading the address of the sgmii
phy registers from the DT. Use ofnode_get_addr_index instead of the
plain ofnode_read_u32_default to fix this.

Signed-off-by: Mario Six 
---
 drivers/net/tsec.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 6829e32dae..7a7ae1dccc 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -797,8 +797,9 @@ int tsec_probe(struct udevice *dev)
 
parent = ofnode_get_parent(phandle_args.node);
if (ofnode_valid(parent)) {
-   int reg = ofnode_read_u32_default(parent, "reg", 0);
-   priv->phyregs_sgmii = (struct tsec_mii_mng *)(reg + 0x520);
+   int reg = ofnode_get_addr_index(parent, 0);
+
+   priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
} else {
debug("No parent node for PHY?\n");
return -ENOENT;
-- 
2.16.1

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[U-Boot] [PATCH] mtd: cfi_flash: Make live-tree compatible

[Mario Six]

Make the cfi_flash driver compatible with a live device tree.

Signed-off-by: Mario Six 
---
 drivers/mtd/cfi_flash.c | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index da44e6184e..e5509fe353 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2461,27 +2461,28 @@ unsigned long flash_init(void)
 #ifdef CONFIG_CFI_FLASH /* for driver model */
 static int cfi_flash_probe(struct udevice *dev)
 {
-   void *blob = (void *)gd->fdt_blob;
-   int node = dev_of_offset(dev);
const fdt32_t *cell;
-   phys_addr_t addr;
-   int parent, addrc, sizec;
+   int addrc, sizec;
int len, idx;
 
-   parent = fdt_parent_offset(blob, node);
-   fdt_support_default_count_cells(blob, parent, , );
-   /* decode regs, there may be multiple reg tuples. */
-   cell = fdt_getprop(blob, node, "reg", );
+   addrc = dev_read_addr_cells(dev);
+   sizec = dev_read_size_cells(dev);
+
+   /* decode regs; there may be multiple reg tuples. */
+   cell = dev_read_prop(dev, "reg", );
if (!cell)
return -ENOENT;
idx = 0;
len /= sizeof(fdt32_t);
while (idx < len) {
-   addr = fdt_translate_address((void *)blob,
-node, cell + idx);
+   phys_addr_t addr;
+
+   addr = dev_translate_address(dev, cell + idx);
+
flash_info[cfi_flash_num_flash_banks].dev = dev;
flash_info[cfi_flash_num_flash_banks].base = addr;
cfi_flash_num_flash_banks++;
+
idx += addrc + sizec;
}
gd->bd->bi_flashstart = flash_info[0].base;
-- 
2.16.1

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[U-Boot] [PATCH 2/3] mpc83xx/pci: Register IMMR region

[Mario Six]

Register the IMMR region as a PCI region when PCI is used on MPC83xx.

Signed-off-by: Mario Six 
---
 drivers/pci/pci-uclass.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index ad43e8a27c..0778705f76 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -898,6 +898,11 @@ static int decode_regions(struct pci_controller *hose, 
ofnode parent_node,
   size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 #endif
 
+#if defined(MPC83xx) && defined(CONFIG_SYS_IMMR)
+   pci_set_region(hose->regions + hose->region_count++,
+  CONFIG_SYS_IMMR, CONFIG_SYS_IMMR, 0x10,
+  PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+#endif
return 0;
 }
 
-- 
2.16.1

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[U-Boot] [PATCH 6/7] video_display: Add power_on function

[Mario Six]

Add a power_on function to the display uclass to allow devices to be
probed and powered-on separately.

Signed-off-by: Mario Six 
---
 drivers/video/display-uclass.c | 10 ++
 include/display.h  | 18 ++
 2 files changed, 28 insertions(+)

diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
index e752eb07c4..4865057e94 100644
--- a/drivers/video/display-uclass.c
+++ b/drivers/video/display-uclass.c
@@ -57,6 +57,16 @@ int display_read_timing(struct udevice *dev, struct 
display_timing *timing)
return edid_get_timing(buf, ret, timing, _bits_per_colour);
 }
 
+int display_power_on(struct udevice *dev, void *data)
+{
+   struct dm_display_ops *ops = display_get_ops(dev);
+
+   if (!ops || !ops->power_on)
+   return -ENOSYS;
+
+   return ops->power_on(dev, data);
+}
+
 bool display_in_use(struct udevice *dev)
 {
struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
diff --git a/include/display.h b/include/display.h
index d0a08d4aaa..bb263be246 100644
--- a/include/display.h
+++ b/include/display.h
@@ -51,6 +51,15 @@ int display_enable(struct udevice *dev, int panel_bpp,
  */
 bool display_in_use(struct udevice *dev);
 
+/**
+ * display_power_on() - Power on display port device
+ *
+ * @dev:   Device to power on
+ * @data:  Optional data needed to power on the display correctly
+ * @return 0 if OK, -ve on error
+ */
+int display_power_on(struct udevice *dev, void *data);
+
 struct dm_display_ops {
/**
 * read_timing() - Read information directly
@@ -81,6 +90,15 @@ struct dm_display_ops {
 */
int (*enable)(struct udevice *dev, int panel_bpp,
  const struct display_timing *timing);
+
+   /**
+* power_on() - Power on display port device
+*
+* @dev:Device to power on
+* @data:   Optional data needed to power on the display correctly
+* @return 0 if OK, -ve on error
+*/
+   int (*power_on)(struct udevice *dev, void *data);
 };
 
 #define display_get_ops(dev)   ((struct dm_display_ops *)(dev)->driver->ops)
-- 
2.16.1

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[U-Boot] [PATCH 3/7] sandbox: Add and build AXI bus and device

[Mario Six]

Add test AXI drivers to the sandbox.

Signed-off-by: Mario Six 
---
 arch/sandbox/dts/sandbox.dts | 11 +++
 arch/sandbox/dts/test.dts| 11 +++
 configs/sandbox_defconfig|  3 +++
 3 files changed, 25 insertions(+)

diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 1fb8225fbb..c419e3f98b 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -12,6 +12,7 @@
i2c0 = _0;
pci0 = 
rtc0 = _0;
+   axi0 = 
};
 
chosen {
@@ -311,6 +312,16 @@
};
};
};
+
+   axi: axi@0 {
+   compatible = "sandbox,axi";
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+   store@0 {
+   compatible = "sandbox,sandbox_store";
+   reg = <0x0 0x400>;
+   };
+   };
 };
 
 #include "cros-ec-keyboard.dtsi"
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index b0f0ca8f19..5b05207bed 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -30,6 +30,7 @@
usb0 = _0;
usb1 = _1;
usb2 = _2;
+   axi0 = 
};
 
a-test {
@@ -479,6 +480,16 @@
compatible = "sandbox,wdt";
};
 
+   axi: axi@0 {
+   compatible = "sandbox,axi";
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+   store@0 {
+   compatible = "sandbox,sandbox_store";
+   reg = <0x0 0x400>;
+   };
+   };
+
chosen {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 063828333d..e6b2a84789 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -45,6 +45,7 @@ CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_AXI=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
@@ -81,6 +82,8 @@ CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
+CONFIG_AXI=y
+CONFIG_AXI_SANDBOX=y
 CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
-- 
2.16.1

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[U-Boot] [PATCH] clk: Add ICS8N3QV01 driver

[Mario Six]

Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO.

Signed-off-by: Mario Six 
---
 drivers/clk/Kconfig  |   8 ++
 drivers/clk/Makefile |   1 +
 drivers/clk/ics8n3qv01.c | 231 +++
 3 files changed, 240 insertions(+)
 create mode 100644 drivers/clk/ics8n3qv01.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index c382e8865f..60a6859c24 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -89,4 +89,12 @@ source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/renesas/Kconfig"

+config ICS8N3QV01
+   bool "Enable ICS8N3QV01 VCXO driver"
+   depends on CLK
+   help
+ Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
+ Crystal Oscillator). The output frequency can be programmed via an
+ I2C interface.
+
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e05c607223..0b4f38527a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
 obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
+obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
 obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
diff --git a/drivers/clk/ics8n3qv01.c b/drivers/clk/ics8n3qv01.c
new file mode 100644
index 00..d7ca63e7e9
--- /dev/null
+++ b/drivers/clk/ics8n3qv01.c
@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario@gdsys.cc
+ *
+ * based on the gdsys osd driver, which is
+ *
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eib...@gdsys.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+const long long ICS8N3QV01_FREF = 114285000;
+const long long ICS8N3QV01_FREF_LL = 114285000LL;
+const long long ICS8N3QV01_F_DEFAULT_0 = 15625LL;
+const long long ICS8N3QV01_F_DEFAULT_1 = 12500LL;
+const long long ICS8N3QV01_F_DEFAULT_2 = 1LL;
+const long long ICS8N3QV01_F_DEFAULT_3 = 25175000LL;
+
+const uint MAX_FREQ_INDEX = 3;
+
+struct ics8n3qv01_priv {
+   ulong rate;
+};
+
+static int ics8n3qv01_get_fout_calc(struct udevice *dev, uint index,
+   uint *fout_calc)
+{
+   u64 n, mint, mfrac;
+   u8 reg_a, reg_b, reg_c, reg_d, reg_f;
+   int val[6];
+   int i;
+
+   if (index > MAX_FREQ_INDEX)
+   return -EINVAL;
+
+   for (i = 0; i <= 5; ++i) {
+   int tmp = dm_i2c_reg_read(dev, 4 * i + index);
+
+   if (tmp < 0) {
+   debug("%s: Error while reading i2c register %d.\n",
+ dev->name, 4 * i + index);
+   return tmp;
+   }
+
+   val[i] = tmp;
+   }
+
+   reg_a = val[0]; /* Register 0 + index */
+   reg_b = val[1]; /* Register 4 + index */
+   reg_c = val[2]; /* Register 8 + index */
+   reg_d = val[3]; /* Register 12 + index */
+   reg_f = val[5]; /* Register 20 + index */
+
+   mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
+   mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
+   | (reg_d >> 7);
+   n = reg_d & 0x7f;
+
+   *fout_calc = (mint * ICS8N3QV01_FREF_LL
+ + mfrac * ICS8N3QV01_FREF_LL / 262144LL
+ + ICS8N3QV01_FREF_LL / 524288LL
+ + n / 2)
+   / n
+   * 100
+   / (100 - 100);
+
+   return 0;
+}
+
+static int ics8n3qv01_calc_parameters(uint fout, uint *_mint, uint *_mfrac,
+  uint *_n)
+{
+   uint n, foutiic, fvcoiic, mint;
+   u64 mfrac;
+
+   n = (221500U + fout / 2) / fout;
+   if (fout < 41700U)
+   n = 2 * ((221500U / 2 + fout / 2) / fout);
+   else
+   n = (221500U + fout / 2) / fout;
+
+
+
+   if ((n & 1) && (n > 5))
+   n -= 1;
+
+   foutiic = fout - (fout / 1);
+   fvcoiic = foutiic * n;
+
+   mint = fvcoiic / 114285000;
+   if ((mint < 17) || (mint > 63)) {
+   return -EINVAL;
+   }
+
+   mfrac = ((u64)fvcoiic % 114285000LL) * 262144LL
+   / 114285000LL;
+
+   *_mint = mint;
+   *_mfrac = mfrac;
+   *_n = n;
+
+   return 0;
+}
+
+static ulong ics8n3qv01_set_rate(struct clk *clk, ulong fout)
+{
+   struct ics8n3qv01_priv *priv = dev_get_priv(clk->dev);
+   uint n, mint, mfrac;
+   uint fout_calc = 0;
+   u64 fout_prog;
+   long long off_ppm;
+   int res, i;
+   u8 reg[6];
+   int tmp;
+   int addr[] = {0, 4, 8, 12, 18, 20};
+
+   priv->rate = fout;
+
+   res = ics8n3qv01_get_fout_calc(clk->dev, 1, _calc);
+
+   

[U-Boot] [PATCH 3/3] pci: Add MPC83xx PCIe driver

[Mario Six]

Add a PCIe driver for the MPC83xx architecture.

Signed-off-by: Mario Six 
---
 arch/powerpc/cpu/mpc83xx/pcie.c |   4 +
 drivers/pci/Kconfig |  16 ++
 drivers/pci/Makefile|   1 +
 drivers/pci/pcie_mpc83xx.c  | 442 
 4 files changed, 463 insertions(+)
 create mode 100644 drivers/pci/pcie_mpc83xx.c

diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 28c25e5feb..ed9c3d5d9d 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -8,6 +8,8 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#ifndef CONFIG_PCIE_MPC83XX
+
 #include 
 #include 
 #include 
@@ -333,3 +335,5 @@ void mpc83xx_pcie_init(int num_buses, struct pci_region 
**reg)
for (i = 0; i < num_buses; i++)
mpc83xx_pcie_init_bus(i, reg[i]);
 }
+
+#endif /* !CONFIG_PCIE_MPC83XX */
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index da6421f35c..8385fa5c9b 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -59,6 +59,22 @@ config PCI_RCAR_GEN2
  Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is
  also used to access EHCI USB controller on the SoC.
 
+config PCIE_MPC83XX
+   bool "MPC83xx PCIe driver support"
+   depends on DM_PCI
+   help
+ Say Y here if you want to enable support for the PCIe controller on
+ MPC83xx SoCs.
+
+if PCIE_MPC83XX
+
+config 83XX_GENERIC_PCIE_REGISTER_HOSES
+   bool "Register generic hoses"
+   help
+ Register generic PCIe hoses when probing the PCIe device.
+
+endif
+
 config PCI_SANDBOX
bool "Sandbox PCI support"
depends on SANDBOX && DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 8fbab462a4..c6452e6f42 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -33,4 +33,5 @@ obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
+obj-$(CONFIG_PCIE_MPC83XX) += pcie_mpc83xx.o
 obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
diff --git a/drivers/pci/pcie_mpc83xx.c b/drivers/pci/pcie_mpc83xx.c
new file mode 100644
index 00..19abf225b0
--- /dev/null
+++ b/drivers/pci/pcie_mpc83xx.c
@@ -0,0 +1,442 @@
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario@gdsys.cc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct pex_inbound_window {
+   u32 ar;
+   u32 tar;
+   u32 barl;
+   u32 barh;
+};
+
+struct pex_outbound_window {
+   u32 ar;
+   u32 bar;
+   u32 tarl;
+   u32 tarh;
+};
+
+struct pex_csb_bridge {
+   u32 pex_csb_ver;
+   u32 pex_csb_cab;
+   u32 pex_csb_ctrl;
+   u8 res0[8];
+   u32 pex_dms_dstmr;
+   u8 res1[4];
+   u32 pex_cbs_stat;
+   u8 res2[0x20];
+   u32 pex_csb_obctrl;
+   u32 pex_csb_obstat;
+   u8 res3[0x98];
+   u32 pex_csb_ibctrl;
+   u32 pex_csb_ibstat;
+   u8 res4[0xb8];
+   u32 pex_wdma_ctrl;
+   u32 pex_wdma_addr;
+   u32 pex_wdma_stat;
+   u8 res5[0x94];
+   u32 pex_rdma_ctrl;
+   u32 pex_rdma_addr;
+   u32 pex_rdma_stat;
+   u8 res6[0xd4];
+   u32 pex_ombcr;
+   u32 pex_ombdr;
+   u8 res7[0x38];
+   u32 pex_imbcr;
+   u32 pex_imbdr;
+   u8 res8[0x38];
+   u32 pex_int_enb;
+   u32 pex_int_stat;
+   u32 pex_int_apio_vec1;
+   u32 pex_int_apio_vec2;
+   u8 res9[0x10];
+   u32 pex_int_ppio_vec1;
+   u32 pex_int_ppio_vec2;
+   u32 pex_int_wdma_vec1;
+   u32 pex_int_wdma_vec2;
+   u32 pex_int_rdma_vec1;
+   u32 pex_int_rdma_vec2;
+   u32 pex_int_misc_vec;
+   u8 res10[4];
+   u32 pex_int_axi_pio_enb;
+   u32 pex_int_axi_wdma_enb;
+   u32 pex_int_axi_rdma_enb;
+   u32 pex_int_axi_misc_enb;
+   u32 pex_int_axi_pio_stat;
+   u32 pex_int_axi_wdma_stat;
+   u32 pex_int_axi_rdma_stat;
+   u32 pex_int_axi_misc_stat;
+   u8 res11[0xa0];
+   struct pex_outbound_window pex_outbound_win[4];
+   u8 res12[0x100];
+   u32 pex_epiwtar0;
+   u32 pex_epiwtar1;
+   u32 pex_epiwtar2;
+   u32 pex_epiwtar3;
+   u8 res13[0x70];
+   struct pex_inbound_window pex_inbound_win[4];
+};
+
+struct pcie_mpc83xx_regs {
+   u8 pex_cfg_header[0x404];
+   u32 pex_ltssm_stat;
+   u8 res0[0x30];
+   u32 pex_ack_replay_timeout;
+   u8 res1[4];
+   u32 pex_gclk_ratio;
+   u8 res2[0xc];
+   u32 pex_pm_timer;
+   u32 pex_pme_timeout;
+   u8 res3[4];
+   u32 pex_aspm_req_timer;
+   u8 res4[0x18];
+   u32 pex_ssvid_update;
+   u8 res5[0x34];
+   u32 pex_cfg_ready;
+   u8 res6[0x24];
+   u32 pex_bar_sizel;
+   u8 res7[4];
+   u32 pex_bar_sel;
+   u8 res8[0x20];
+  

[U-Boot] [PATCH] cmd: ximg: Respect cache line size for flushing

[Mario Six]

Make sure that the cache line size if respected when flushing the cache.

Signed-off-by: Mario Six 
---
 cmd/ximg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/ximg.c b/cmd/ximg.c
index 21b5c37721..069c6ad39a 100644
--- a/cmd/ximg.c
+++ b/cmd/ximg.c
@@ -249,7 +249,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * 
const argv[])
puts("OK\n");
}
 
-   flush_cache(dest, len);
+   flush_cache(dest, ALIGN(len, ARCH_DMA_MINALIGN));
 
env_set_hex("fileaddr", data);
env_set_hex("filesize", len);
-- 
2.16.1

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[U-Boot] [PATCH 1/7] drivers: Add AXI uclass and ihs_axi driver

[Mario Six]

Add a uclass for AXI (Advanced eXtensible Interface) busses, and a
driver for the gdsys IHS AXI bus on IHS FPGAs.

Signed-off-by: Mario Six 
---
 drivers/Kconfig  |   2 +
 drivers/Makefile |   1 +
 drivers/axi/Kconfig  |  24 ++
 drivers/axi/Makefile |   9 +++
 drivers/axi/axi-uclass.c |  40 ++
 drivers/axi/ihs_axi.c| 199 +++
 include/axi.h|  75 ++
 include/dm/uclass-id.h   |   1 +
 8 files changed, 351 insertions(+)
 create mode 100644 drivers/axi/Kconfig
 create mode 100644 drivers/axi/Makefile
 create mode 100644 drivers/axi/axi-uclass.c
 create mode 100644 drivers/axi/ihs_axi.c
 create mode 100644 include/axi.h

diff --git a/drivers/Kconfig b/drivers/Kconfig
index c2e813f5ad..eeaaa7575c 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -8,6 +8,8 @@ source "drivers/adc/Kconfig"

 source "drivers/ata/Kconfig"

+source "drivers/axi/Kconfig"
+
 source "drivers/block/Kconfig"

 source "drivers/bootcount/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 6846d181aa..f54a10f3ad 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -100,6 +100,7 @@ obj-y += input/
 obj-y += soc/
 obj-$(CONFIG_REMOTEPROC) += remoteproc/
 obj-y += thermal/
+obj-y += axi/

 obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
 endif
diff --git a/drivers/axi/Kconfig b/drivers/axi/Kconfig
new file mode 100644
index 00..19e1b7fd2f
--- /dev/null
+++ b/drivers/axi/Kconfig
@@ -0,0 +1,24 @@
+menuconfig AXI
+   bool "AXI bus drivers"
+   help
+ Support AXI (Advanced eXtensible Interface) busses, a on-chip
+ interconnect specification for managing functional blocks in SoC
+ designs, which is also often used in designs involving FPGAs (e.g.
+ communication with IP cores in Xilinx FPGAs).
+
+ These types of busses expose a virtual address space that can be
+ accessed using different address widths (8, 16, and 32 are supported
+ for now).
+
+ Other similar bus architectures may be compatible as well.
+
+if AXI
+
+config IHS_AXI
+   bool "Enable IHS AXI driver"
+   depends on DM
+   help
+ Support for IHS AXI bus on a gdsys IHS FPGA used to communicate with
+ IP cores in the FPGA (e.g. video transmitter cores).
+
+endif
diff --git a/drivers/axi/Makefile b/drivers/axi/Makefile
new file mode 100644
index 00..18d9380e9b
--- /dev/null
+++ b/drivers/axi/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2017
+# Mario Six,  Guntermann & Drunck GmbH, mario@gdsys.cc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_AXI) += axi-uclass.o
+obj-$(CONFIG_IHS_AXI) += ihs_axi.o
diff --git a/drivers/axi/axi-uclass.c b/drivers/axi/axi-uclass.c
new file mode 100644
index 00..3a5ddf3a46
--- /dev/null
+++ b/drivers/axi/axi-uclass.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario@gdsys.cc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+int axi_read(struct udevice *dev, ulong address, void *data,
+enum axi_size_t size)
+{
+   struct axi_ops *ops = axi_get_ops(dev);
+
+   if (!ops->read)
+   return -ENOSYS;
+
+   return ops->read(dev, address, data, size);
+}
+
+int axi_write(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+   struct axi_ops *ops = axi_get_ops(dev);
+
+   if (!ops->write)
+   return -ENOSYS;
+
+   return ops->write(dev, address, data, size);
+}
+
+UCLASS_DRIVER(axi) = {
+   .id = UCLASS_AXI,
+   .name   = "axi",
+   .post_bind  = dm_scan_fdt_dev,
+   .flags  = DM_UC_FLAG_SEQ_ALIAS,
+};
+
diff --git a/drivers/axi/ihs_axi.c b/drivers/axi/ihs_axi.c
new file mode 100644
index 00..71bb67421f
--- /dev/null
+++ b/drivers/axi/ihs_axi.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2016
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eib...@gdsys.cc
+ *
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario@gdsys.cc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include "../misc/gdsys_soc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+   REG_INTERRUPT_STATUS = 0x00,
+   REG_INTERRUPT_ENABLE_CONTROL = 0x02,
+   REG_ADDRESS_LSB = 0x04,
+   REG_ADDRESS_MSB = 0x06,
+   REG_WRITE_DATA_LSB = 0x08,
+   REG_WRITE_DATA_MSB = 0x0A,
+   REG_READ_DATA_LSB = 0x0C,
+   REG_READ_DATA_MSB = 0x0E,
+};
+
+struct ihs_axi_priv {
+   fdt_addr_t addr;
+};
+
+enum {
+   STATUS_EVENT_MASK = GENMASK(15, 12),
+
+   STATUS_READ_COMPLETE_EVENT = BIT(15),
+   STATUS_WRITE_COMPLETE_EVENT = BIT(14),
+   STATUS_TIMEOUT_EVENT = BIT(13),
+   STATUS_ERROR_EVENT = BIT(12),
+   STATUS_AXI_INT = BIT(11),
+   STATUS_READ_DATA_AVAILABLE = BIT(7),
+   

[U-Boot] [PATCH 1/4] net: Always align tx packets

[Mario Six]

Make sure that TX packets are always cache-aligned.

Signed-off-by: Mario Six 
---
 net/arp.c  | 3 ++-
 net/ping.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/net/arp.c b/net/arp.c
index 4c79e09ccb..191434f5e2 100644
--- a/net/arp.c
+++ b/net/arp.c
@@ -182,7 +182,8 @@ void arp_receive(struct ethernet_hdr *et, struct ip_udp_hdr 
*ip, int len)
(net_read_ip(>ar_spa).s_addr & net_netmask.s_addr))
udelay(5000);
 #endif
-   net_send_packet((uchar *)et, eth_hdr_size + ARP_HDR_SIZE);
+   memcpy(net_tx_packet, et, eth_hdr_size + ARP_HDR_SIZE);
+   net_send_packet(net_tx_packet, eth_hdr_size + ARP_HDR_SIZE);
return;

case ARPOP_REPLY:   /* arp reply */
diff --git a/net/ping.c b/net/ping.c
index 9508cf1160..db14209bf6 100644
--- a/net/ping.c
+++ b/net/ping.c
@@ -107,7 +107,8 @@ void ping_receive(struct ethernet_hdr *et, struct 
ip_udp_hdr *ip, int len)
icmph->type = ICMP_ECHO_REPLY;
icmph->checksum = 0;
icmph->checksum = compute_ip_checksum(icmph, len - IP_HDR_SIZE);
-   net_send_packet((uchar *)et, eth_hdr_size + len);
+   memcpy(net_tx_packet, et, eth_hdr_size + len);
+   net_send_packet(net_tx_packet, eth_hdr_size + len);
return;
 /* default:
return;*/
--
2.16.1

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[U-Boot] [PATCH 4/4] phylib: Don't re-define CONFIG_PHY_MARVELL

[Mario Six]

For certain boards, having CONFIG_PHY_MARVELL in the defconfig will
result in a redefinition warning, because it is also defined in
config_phylib_all_drivers.h.

Add a check to stop this redefinition, but keep it for those boards that
still don't have it in their defconfig.

Signed-off-by: Mario Six 
---
 include/config_phylib_all_drivers.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/config_phylib_all_drivers.h 
b/include/config_phylib_all_drivers.h
index 496ef58db0..264f220c5f 100644
--- a/include/config_phylib_all_drivers.h
+++ b/include/config_phylib_all_drivers.h
@@ -15,7 +15,9 @@
 #ifdef CONFIG_PHYLIB
 
 #define CONFIG_PHY_VITESSE
+#ifndef CONFIG_PHY_MARVELL
 #define CONFIG_PHY_MARVELL
+#endif
 #define CONFIG_PHY_BROADCOM
 #define CONFIG_PHY_DAVICOM
 #define CONFIG_PHY_REALTEK
-- 
2.16.1

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Re: [U-Boot] [PATCH] vxworks: fixed cpu enable using PSCI on armv8

[Vasyl Vavrychuk]

Hi, Bin Meng,

Thanks for your suggestions. Please find my comments below

On Wed, Mar 28, 2018 at 7:36 AM, Bin Meng  wrote:
>
> >
> > Tested on VxWorks 7 release SR0520 2017-12-08.
> >
>
> On what board?

Intel Stratix 10 DevKit

> As I mentioned before, why do you want to use 'bootvx' to boot a
> VxWorks 7 kernel? I believe VxWorks 7 ARM kernel is loaded via
> 'bootm'. See doc/README.vxworks.

I have just tried what I found first, but I can add support of ARMv8
PSCI to the bootm for vxworks 7 too.

Anyway, if we add support of ARMv8 PSCI to bootm for vxworks 7, then
do you think that bootvx should not support this feature?

>
> > +#if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI)
> > +   armv8_setup_psci();
> > +   smp_kick_all_cpus();
>
> What about ARMv8 32-bit?
Do you mean ARMv8 32-bit U-Boot or ARMv8 32-bit VxWorks under ARMv8
64-bit U-Boot?

> What about ARMv7? Should we call smp_kick_all_cpus() for ARMv7 as well?
As far as I understand from U-Boot code gic_wait_for_interrupt is
called only for ARMv8. I think this is related to the difference how
cpu cores start from reset on armv7 and armv8.

On armv7 usually only core0 starts after power on and other cores are
started by the platform specific means. On armv8 usually all cores
starts after power on.

> Seems to me the logic of #ifdefs here needs to be tuned.
I have made a minimal set of changes need to implement functionality
that are required for our customer, i.e. booting 64-bit vxworks on
armv8.

I am not very willing to generalize it without a need. Maybe just no
one will require it at all.

Kind regards,
Vasyl
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[U-Boot] [PATCH 1/3] drivers: Add OSD uclass

[Mario Six]

Some devices offer a text-based OSD (on-screen display) that can be
programmatically controlled (i.e. text displayed on).

Add a uclass to support such devices.

Signed-off-by: Mario Six 
---
 drivers/video/Kconfig|   8 +++
 drivers/video/Makefile   |   2 +
 drivers/video/video_osd-uclass.c |  47 +
 include/dm/uclass-id.h   |   1 +
 include/video_osd.h  | 145 +++
 5 files changed, 203 insertions(+)
 create mode 100644 drivers/video/video_osd-uclass.c
 create mode 100644 include/video_osd.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0defcd0..da60bbe692 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -660,4 +660,12 @@ config VIDEO_DT_SIMPLEFB
  The video output is initialized by U-Boot, and kept by the
  kernel.
 
+config OSD
+   bool "Enable OSD support"
+   depends on DM
+   default n
+   help
+  This supports drivers that provide a OSD (on-screen display), which
+  is a (usually text-oriented) graphics buffer to show information on
+  a display.
 endmenu
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08fc5..209d5e3a75 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -58,5 +58,7 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
 obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
 obj-${CONFIG_VIDEO_STM32} += stm32/
 
+obj-${CONFIG_OSD} += video_osd-uclass.o
+
 obj-y += bridge/
 obj-y += sunxi/
diff --git a/drivers/video/video_osd-uclass.c b/drivers/video/video_osd-uclass.c
new file mode 100644
index 00..b6dd7e59b1
--- /dev/null
+++ b/drivers/video/video_osd-uclass.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario@gdsys.cc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+int video_osd_get_data(struct udevice *dev, void *data)
+{
+   struct video_osd_ops *ops = video_osd_get_ops(dev);
+
+   return ops->get_data(dev, data);
+}
+
+int video_osd_set_mem(struct udevice *dev, uint x, uint y, u8 *buf,
+ size_t buflen, uint count)
+{
+   struct video_osd_ops *ops = video_osd_get_ops(dev);
+
+   return ops->set_mem(dev, x, y, buf, buflen, count);
+}
+
+int video_osd_set_size(struct udevice *dev, uint x, uint y)
+{
+   struct video_osd_ops *ops = video_osd_get_ops(dev);
+
+   return ops->set_size(dev, x, y);
+}
+
+int video_osd_print(struct udevice *dev, uint x, uint y, ulong color,
+   char *text)
+{
+   struct video_osd_ops *ops = video_osd_get_ops(dev);
+
+   return ops->print(dev, x, y, color, text);
+}
+
+UCLASS_DRIVER(video_osd) = {
+   .id = UCLASS_VIDEO_OSD,
+   .name   = "video_osd",
+   .flags  = DM_UC_FLAG_SEQ_ALIAS,
+};
+
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 07fabc3ce6..685f22550a 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -89,6 +89,7 @@ enum uclass_id {
UCLASS_VIDEO,   /* Video or LCD device */
UCLASS_VIDEO_BRIDGE,/* Video bridge, e.g. DisplayPort to LVDS */
UCLASS_VIDEO_CONSOLE,   /* Text console driver for video device */
+   UCLASS_VIDEO_OSD,   /* On-screen displays */
UCLASS_WDT, /* Watchdot Timer driver */
 
UCLASS_COUNT,
diff --git a/include/video_osd.h b/include/video_osd.h
new file mode 100644
index 00..1ab5ff9b21
--- /dev/null
+++ b/include/video_osd.h
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario@gdsys.cc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _VIDEO_OSD_H_
+#define _VIDEO_OSD_H_
+
+/**
+ * struct video_osd_ops - driver operations for OSD uclass
+ *
+ * Drivers should support these operations unless otherwise noted. These
+ * operations are intended to be used by uclass code, not directly from
+ * other code.
+ */
+struct video_osd_ops {
+   /**
+* get_data() - Get information about a OSD instance
+*
+* A OSD instance may keep some internal data about itself. This
+* function can be used to access this data.
+*
+* @dev:OSD instance to query.
+* @data:   Pointer to a buffer that takes the information read
+*  from the OSD instance.
+* @return 0 if OK, -ve on error.
+*/
+   int (*get_data)(struct udevice *dev, void *data);
+
+   /**
+* set_mem() - Write pixel data to OSD memory
+*
+* The passed data are device-specific, and it's up to the driver how
+* to interpret them. How the count parameter is interpreted is also
+* driver-specific; most likely the given data will be written to the
+* OSD count times back-to-back, which is e.g. convenient for filling
+* areas of the OSD with a single 

[U-Boot] [PATCH] gpio: uclass: Fix debug string

[Mario Six]

A debug string still has the old name of a function being called; update
it.

Signed-off-by: Mario Six 
---
 drivers/gpio/gpio-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 9faf3357af..1fbfdef477 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -655,7 +655,7 @@ static int gpio_request_tail(int ret, ofnode node,
ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
  >dev);
if (ret) {
-   debug("%s: uclass_get_device_by_of_offset failed\n", __func__);
+   debug("%s: uclass_get_device_by_ofnode failed\n", __func__);
goto err;
}
ret = gpio_find_and_xlate(desc, args);
-- 
2.16.1

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