Re: [U-Boot] [PATCH 4/4] configs: socfpga: socrates: enable rtc support
On 12.03.19 22:01, Simon Goldschmidt wrote: This enables DM_RTC and RTC_M41T62 to enable support for the rtc on the socrates board. Signed-off-by: Simon Goldschmidt Reviewed-by: Stefan Roese Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] arm: socfpga: socrates: make rtc work
On 12.03.19 22:01, Simon Goldschmidt wrote: This patch makes the on-board RTC work on the socfpga_socrates board. This rtc is present on the board, but it does not work (fails with a timeout). This patch adds a weak pull-up on the I2C0-SCL pin connected to the m41t82 RTC on this board. While the SDA line has a pull-up on the pcb, the pull-up on the SCL line seems to be missing. To work around this, enable the weak-pull-up feature on this pin. After applying this patch, the rtc timeout is gone and the 'date' command can access the rtc chip. Signed-off-by: Simon Goldschmidt Reviewed-by: Stefan Roese Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] rtc: m41t62: add compatible for m41t82
On 12.03.19 22:01, Simon Goldschmidt wrote: This adds a compatible string for m41t82. This ensures that this driver can be used for m41t82 in DM mode, too (as it was usable for this model in non-DM mode before). This patch ensures this driver works on socfpga_socrates. Signed-off-by: Simon Goldschmidt Reviewed-by: Stefan Roese Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] i2c: designware: fix reset handling on socfpga gen5
Hello Simon,
Am 12.03.2019 um 22:01 schrieb Simon Goldschmidt:
Using this driver on socfpga gen5 with DM_I2C enabled leads to a data abort
as the 'i2c' reset property cannot be found (the gen5 dtsi does not provide
reset-names).
The actual bug was to check 'if (>reset_ctl)', which is never false.
While at it, convert the driver to use 'reset_get_bulk' instead of looking
at a specific named reset and also make it release the reset on driver
remove before starting the OS.
Fixes: 622597dee4f6 ("i2c: designware: add reset ctrl to driver")
Signed-off-by: Simon Goldschmidt
---
drivers/i2c/designware_i2c.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
Reviewed-by: Heiko Schocher
bye,
Heiko
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [PATCH] test/py: Fix pytest4 deprecation warnings
Fix the following spit from pytest:
u-boot/test/py/conftest.py:438: RemovedInPytest4Warning: MarkInfo objects are
deprecated as they contain merged marks which are hard to deal with correctly.
Please use node.get_closest_marker(name) or node.iter_markers(name).
Docs: https://docs.pytest.org/en/latest/mark.html#updating-code
for board in mark.args:
In both cases, the later suggestion is applicable.
Signed-off-by: Marek Vasut
Cc: Igor Opaniuk
Cc: Tom Rini
Cc: Simon Glass
---
test/py/conftest.py | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/test/py/conftest.py b/test/py/conftest.py
index e40cbf0ba1..745ca5ac4a 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -431,11 +431,9 @@ def setup_boardspec(item):
Nothing.
"""
-mark = item.get_marker('boardspec')
-if not mark:
-return
required_boards = []
-for board in mark.args:
+for boards in item.iter_markers('boardspec'):
+board = boards.args[0]
if board.startswith('!'):
if ubconfig.board_type == board[1:]:
pytest.skip('board "%s" not supported' % ubconfig.board_type)
@@ -459,10 +457,8 @@ def setup_buildconfigspec(item):
Nothing.
"""
-mark = item.get_marker('buildconfigspec')
-if not mark:
-return
-for option in mark.args:
+for options in item.iter_markers('buildconfigspec'):
+option = options.args[0]
if not ubconfig.buildconfig.get('config_' + option.lower(), None):
pytest.skip('.config feature "%s" not enabled' % option.lower())
--
2.20.1
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Re: [U-Boot] [PATCH] ARM: dts: socfpga: Add missing altr, sysmgr-syscon for EMAC
On 3/13/19 4:03 AM, Ley Foon Tan wrote: > Syscon register is required in dts to select correct > PHY interface. > > Fix error below: > > Net: Failed to get syscon: -2 > > Signed-off-by: Ley Foon Tan Is this fixed in mainline Linux too ? > --- > arch/arm/dts/socfpga_stratix10.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/dts/socfpga_stratix10.dtsi > b/arch/arm/dts/socfpga_stratix10.dtsi > index ccd3f32301..ee93725d64 100644 > --- a/arch/arm/dts/socfpga_stratix10.dtsi > +++ b/arch/arm/dts/socfpga_stratix10.dtsi > @@ -95,6 +95,7 @@ > mac-address = [00 00 00 00 00 00]; > resets = < EMAC0_RESET>, < EMAC0_OCP_RESET>; > reset-names = "stmmaceth"; > + altr,sysmgr-syscon = < 0x44 0>; > status = "disabled"; > }; > > @@ -106,6 +107,7 @@ > mac-address = [00 00 00 00 00 00]; > resets = < EMAC1_RESET>, < EMAC1_OCP_RESET>; > reset-names = "stmmaceth"; > + altr,sysmgr-syscon = < 0x48 0>; > status = "disabled"; > }; > > @@ -117,6 +119,7 @@ > mac-address = [00 00 00 00 00 00]; > resets = < EMAC2_RESET>, < EMAC2_OCP_RESET>; > reset-names = "stmmaceth"; > + altr,sysmgr-syscon = < 0x4c 0>; > status = "disabled"; > }; > > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: dts: socfpga: Add missing altr, sysmgr-syscon for EMAC
Syscon register is required in dts to select correct PHY interface. Fix error below: Net: Failed to get syscon: -2 Signed-off-by: Ley Foon Tan --- arch/arm/dts/socfpga_stratix10.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ccd3f32301..ee93725d64 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -95,6 +95,7 @@ mac-address = [00 00 00 00 00 00]; resets = < EMAC0_RESET>, < EMAC0_OCP_RESET>; reset-names = "stmmaceth"; + altr,sysmgr-syscon = < 0x44 0>; status = "disabled"; }; @@ -106,6 +107,7 @@ mac-address = [00 00 00 00 00 00]; resets = < EMAC1_RESET>, < EMAC1_OCP_RESET>; reset-names = "stmmaceth"; + altr,sysmgr-syscon = < 0x48 0>; status = "disabled"; }; @@ -117,6 +119,7 @@ mac-address = [00 00 00 00 00 00]; resets = < EMAC2_RESET>, < EMAC2_OCP_RESET>; reset-names = "stmmaceth"; + altr,sysmgr-syscon = < 0x4c 0>; status = "disabled"; }; -- 2.19.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig
Thanks a lot, Stefano. Please let me know if you need me to do anything. Once they are picked up, I will start the work for driver cleaning up. Best regards, Yangbo Lu > -Original Message- > From: Stefano Babic > Sent: Wednesday, March 13, 2019 2:14 AM > To: Y.b. Lu ; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig > > Hi Y.B., > > On 01/03/19 04:15, Y.b. Lu wrote: > > Any comments on the patch-set? > > Thanks a lot. > > Patch is tin the right direction, it just touch (as it must be) a huge number > of > boards. I cannot pick it up now, so I will push it into my -next branch. > > Regards, > Stefano > > > > >> -Original Message- > >> From: Y.b. Lu > >> Sent: Thursday, February 21, 2019 3:55 PM > >> To: u-boot@lists.denx.de > >> Cc: Jaehoon Chung ; Prabhakar Kushwaha > >> ; Peng Fan ; Lukasz > >> Majewski ; Y.b. Lu > >> Subject: [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig > >> > >> Moved CONFIG_FSL_ESDHC from header files to defconfig files. > >> > >> Signed-off-by: Yangbo Lu > >> --- > >> configs/imx8mq_evk_defconfig | 1 + > >> configs/imx8qxp_mek_defconfig | 1 + > >> configs/kp_imx53_defconfig | 1 + > >> configs/kp_imx6q_tpc_defconfig | 1 + > >> configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + > >> configs/ls1012afrwy_qspi_defconfig | 1 + > >> configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + > >> configs/ls1012afrwy_tfa_defconfig | 1 + > >> include/configs/imx8mq_evk.h | 1 - > >> include/configs/imx8qxp_mek.h | 1 - > >> include/configs/kp_imx53.h | 1 - > >> include/configs/kp_imx6q_tpc.h | 1 - > >> include/configs/ls1012afrwy.h | 1 - > >> 13 files changed, 8 insertions(+), 5 deletions(-) > >> > >> diff --git a/configs/imx8mq_evk_defconfig > >> b/configs/imx8mq_evk_defconfig index 53025e45bc..8f6d66b741 100644 > >> --- a/configs/imx8mq_evk_defconfig > >> +++ b/configs/imx8mq_evk_defconfig > >> @@ -27,6 +27,7 @@ CONFIG_DM_GPIO=y > >> CONFIG_DM_I2C=y > >> CONFIG_SYS_I2C_MXC=y > >> CONFIG_DM_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_DM_ETH=y > >> CONFIG_PINCTRL=y > >> CONFIG_DM_REGULATOR=y > >> diff --git a/configs/imx8qxp_mek_defconfig > >> b/configs/imx8qxp_mek_defconfig index a94998b8b5..88da3ac784 100644 > >> --- a/configs/imx8qxp_mek_defconfig > >> +++ b/configs/imx8qxp_mek_defconfig > >> @@ -51,6 +51,7 @@ CONFIG_I2C_MUX=y > >> CONFIG_I2C_MUX_PCA954x=y > >> CONFIG_MISC=y > >> CONFIG_DM_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_PHYLIB=y > >> CONFIG_PHY_ADDR_ENABLE=y > >> CONFIG_PHY_ATHEROS=y > >> diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig > >> index > >> cfe96fcce5..d00c8cde62 100644 > >> --- a/configs/kp_imx53_defconfig > >> +++ b/configs/kp_imx53_defconfig > >> @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y > CONFIG_OF_CONTROL=y > >> CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" > >> CONFIG_ENV_IS_IN_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_I2C_SET_DEFAULT_BUS_NUM=y > >> CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 > >> CONFIG_PHYLIB=y > >> diff --git a/configs/kp_imx6q_tpc_defconfig > >> b/configs/kp_imx6q_tpc_defconfig index cb58ed6678..3f48463c0c 100644 > >> --- a/configs/kp_imx6q_tpc_defconfig > >> +++ b/configs/kp_imx6q_tpc_defconfig > >> @@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y # > CONFIG_ISO_PARTITION is > >> not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_PHYLIB=y > >> CONFIG_PHY_ATHEROS=y > >> CONFIG_FEC_MXC=y > >> diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > >> b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > >> index c273dc937e..35a606ce23 100644 > >> --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > >> +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > >> @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_DM=y # > >> CONFIG_BLK is not set CONFIG_DM_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_DM_SPI_FLASH=y > >> CONFIG_SPI_FLASH=y > >> CONFIG_SPI_FLASH_WINBOND=y > >> diff --git a/configs/ls1012afrwy_qspi_defconfig > >> b/configs/ls1012afrwy_qspi_defconfig > >> index 85523ba2d3..50068a12d7 100644 > >> --- a/configs/ls1012afrwy_qspi_defconfig > >> +++ b/configs/ls1012afrwy_qspi_defconfig > >> @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_DM=y # > >> CONFIG_BLK is not set CONFIG_DM_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_DM_SPI_FLASH=y > >> CONFIG_SPI_FLASH=y > >> CONFIG_SPI_FLASH_WINBOND=y > >> diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig > >> b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig > >> index d9020c5281..1b281c90a2 100644 > >> --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig > >> +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig > >> @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_DM=y # > >> CONFIG_BLK is not set CONFIG_DM_MMC=y > >>
Re: [U-Boot] [PATCH v2 7/9] riscv: do not rely on hart ID passed by previous boot stage
Hi Lukas 於 2019年3月12日 週二 下午7:04寫道： > > > > > -Original Message- > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de] > > Sent: Wednesday, March 06, 2019 6:53 AM > > To: u-boot@lists.denx.de > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer Dabbelt; > > Alexander Graf; Lukas Auer; Rick Jian-Zhi Chen(陳建志); Anup Patel > > Subject: [PATCH v2 7/9] riscv: do not rely on hart ID passed by previous > > boot > > stage > > > > RISC-V U-Boot expects the hart ID to be passed to it via register a0 by the > > previous boot stage. Machine mode firmware such as BBL and OpenSBI do this > > when starting their payload (U-Boot) in supervisor mode. If U-Boot is > > running in > > machine mode, this task must be handled by the boot ROM. Explicitly populate > > register a0 with the hart ID from the mhartid CSR to avoid possible > > problems on > > RISC-V processors with a boot ROM that does not handle this task. > > > > Suggested-by: Rick Chen > > Signed-off-by: Lukas Auer > > --- > > > > Changes in v2: > > - New patch to populate register a0 with the hart ID from the mhartid CSR in > > machine-mode > > > > arch/riscv/cpu/start.S | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index > > 79b753847c..d4daa6e0bf 100644 > > --- a/arch/riscv/cpu/start.S > > +++ b/arch/riscv/cpu/start.S > > @@ -36,6 +36,10 @@ > > .section .text > > .globl _start > > _start: > > +#ifdef CONFIG_RISCV_MMODE > > + csrra0, mhartid > > +#endif > > + > > /* save hart id and dtb pointer */ > > mv s0, a0 > > mv s1, a1 Reviewed-by: Rick Chen Tested-by: Rick Chen Thanks Rick ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] added uart1-3 support for the allwinner h3
---
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
arch/arm/mach-sunxi/board.c | 12
include/configs/sunxi-common.h | 8 +---
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 40a3f845d0..50010071ae 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -148,6 +148,9 @@ enum sunxi_gpio_number {
#define SUN6I_GPA_SDC2 5
#define SUN6I_GPA_SDC3 4
#define SUN8I_H3_GPA_UART0 2
+#define SUN8I_H3_GPG_UART1 2
+#define SUN8I_H3_GPA_UART2 2
+#define SUN8I_H3_GPA_UART3 3
#define SUN4I_GPB_PWM 2
#define SUN4I_GPB_TWI0 2
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index b74eaf2a0e..5ee14bd7aa 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -127,10 +127,22 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_H3_GPG_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_H3_GPG_UART1);
+ sunxi_gpio_set_pull(SUNXI_GPG(6), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
+ sunxi_gpio_set_pull(SUNXI_GPA(0), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(14), SUN8I_H3_GPA_UART3);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(13), SUN8I_H3_GPA_UART3);
+ sunxi_gpio_set_pull(SUNXI_GPA(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b01d1c3c84..561c799aa9 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -255,11 +255,13 @@ extern int soft_i2c_gpio_scl;
#else
#define OF_STDOUT_PATH "/soc@01c0/serial@01c28000:115200"
#endif
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
+#elif CONFIG_CONS_INDEX == 2 && ( defined(CONFIG_MACH_SUN5I) ||
defined(CONFIG_MACH_SUN8I_H3) )
#define OF_STDOUT_PATH "/soc@01c0/serial@01c28400:115200"
-#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
+#elif CONFIG_CONS_INDEX == 3 && ( defined(CONFIG_MACH_SUN8I) ||
defined(CONFIG_MACH_SUN8I_H3) )
#define OF_STDOUT_PATH "/soc@01c0/serial@01c28800:115200"
-#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
+#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_H3)
+#define OF_STDOUT_PATH "/soc@01c0/serial@01c28C00:115200"
+#elif CONFIG_CONS_INDEX == 5 && ( defined(CONFIG_MACH_SUN8I) ||
defined(CONFIG_MACH_SUN8I_H3) )
#define OF_STDOUT_PATH "/soc@01c0/serial@01f02800:115200"
#else
#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h.
--
2.11.0
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[U-Boot] [PATCH 1/1] board: tq mba7 tqma7d 1gb emmc support.
Add TQMa7D SoM support when mounted on MBa7 evaluation board.
Signed-off-by: Bruno Thomsen
---
arch/arm/mach-imx/Kconfig | 2 +-
arch/arm/mach-imx/cpu.c | 2 +-
arch/arm/mach-imx/mx7/Kconfig | 9 +
arch/arm/mach-imx/mx7/soc.c | 7 +
board/tqc/common/Kconfig | 4 +
board/tqc/common/Makefile | 10 +
board/tqc/common/tqc_bb.h | 30 ++
board/tqc/common/tqc_emmc.c | 78
board/tqc/common/tqc_emmc.h | 12 +
board/tqc/tqma7/Kconfig | 79
board/tqc/tqma7/MAINTAINERS | 8 +
board/tqc/tqma7/Makefile | 9 +
board/tqc/tqma7/README| 38 ++
board/tqc/tqma7/tqma7.c | 328 ++
board/tqc/tqma7/tqma7_mba7.c | 596 ++
board/tqc/tqma7/tqma7d.cfg| 68 +++
board/tqc/tqma7/tqma7d_ddr_1gb.cfg| 58 +++
board/tqc/tqma7/tqma7d_ddr_512mb.cfg | 58 +++
configs/tqma7d_1gb_mba7_mmc_defconfig | 50 +++
include/configs/tqma7.h | 426 ++
include/configs/tqma7_mba7.h | 35 ++
21 files changed, 1905 insertions(+), 2 deletions(-)
create mode 100644 board/tqc/common/Kconfig
create mode 100644 board/tqc/common/Makefile
create mode 100644 board/tqc/common/tqc_bb.h
create mode 100644 board/tqc/common/tqc_emmc.c
create mode 100644 board/tqc/common/tqc_emmc.h
create mode 100644 board/tqc/tqma7/Kconfig
create mode 100644 board/tqc/tqma7/MAINTAINERS
create mode 100644 board/tqc/tqma7/Makefile
create mode 100644 board/tqc/tqma7/README
create mode 100644 board/tqc/tqma7/tqma7.c
create mode 100644 board/tqc/tqma7/tqma7_mba7.c
create mode 100644 board/tqc/tqma7/tqma7d.cfg
create mode 100644 board/tqc/tqma7/tqma7d_ddr_1gb.cfg
create mode 100644 board/tqc/tqma7/tqma7d_ddr_512mb.cfg
create mode 100644 configs/tqma7d_1gb_mba7_mmc_defconfig
create mode 100644 include/configs/tqma7.h
create mode 100644 include/configs/tqma7_mba7.h
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 8631fbd481..0335c0e8db 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -46,7 +46,7 @@ config SECURE_BOOT
config CMD_BMODE
bool "Support the 'bmode' command"
default y
- depends on ARCH_MX6 || ARCH_MX5
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
help
This enables the 'bmode' (bootmode) command for forcing
a boot from specific media.
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 6b83f92662..113f228c86 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -251,7 +251,7 @@ int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
-#if defined(CONFIG_FEC_MXC)
+#if defined(CONFIG_FEC_MXC) && defined(CONFIG_FEC_MXC_PHYADDR)
rc = fecmxc_initialize(bis);
#endif
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 232f33285d..dfe1bedd3f 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -60,6 +60,14 @@ config TARGET_COLIBRI_IMX7
select DM_THERMAL
imply CMD_DM
+config TARGET_TQMA7
+ bool "tqma7"
+ select MX7D
+ select TQMA7
+ select DM
+ select DM_THERMAL
+ select TQC_EMMC
+
endchoice
config SYS_SOC
@@ -70,5 +78,6 @@ source "board/freescale/mx7dsabresd/Kconfig"
source "board/technexion/pico-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
source "board/warp7/Kconfig"
+source "board/tqc/tqma7/Kconfig"
endif
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 7cfdff0981..f4d697daea 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -128,6 +129,12 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
};
#endif
+#if defined(CONFIG_CMD_BMODE)
+const struct boot_mode soc_boot_modes[] = {
+ {NULL, 0},
+};
+#endif
+
static bool is_mx7d(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
diff --git a/board/tqc/common/Kconfig b/board/tqc/common/Kconfig
new file mode 100644
index 00..6d77ad6052
--- /dev/null
+++ b/board/tqc/common/Kconfig
@@ -0,0 +1,4 @@
+
+config TQC_EMMC
+ bool
+ default n
diff --git a/board/tqc/common/Makefile b/board/tqc/common/Makefile
new file mode 100644
index 00..d2f34f88db
--- /dev/null
+++ b/board/tqc/common/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2016, Markus Niebel
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# necessary to create built-in.o
+obj- := __dummy__.o
+
+obj-$(CONFIG_TQC_EMMC) += tqc_emmc.o
diff --git a/board/tqc/common/tqc_bb.h b/board/tqc/common/tqc_bb.h
new file mode 100644
index 00..d84d799c3b
--- /dev/null
+++ b/board/tqc/common/tqc_bb.h
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright
[U-Boot] [PATCH 0/1] board: imx7d tqma7d support
This work is based on the vendor BSP and an attempt to mainline tqma7 board support. The module is used by many long life products, so it would be nice with upstream supported bootloader. So it's easier to update when secure boot and TPM 2.0 support improves. This patch focus on core bootloader features and not whistles & bells. I have successfully booted a 4.19 mainline kernel with this patch and a device tree patch series currently under review [1]. It compiles without warnings against 2019.01, there are a few checkpatch warnings left that I have not found a valid solution for. Checkpatch does not like GPL-2.0+ and it results in a few: WARNING: Missing or malformed SPDX-License-Identifier tag in line 1 Using grep I have found many lines in the current tree with the same SPDX line. There are about 30 lines that I can refacture between the following two checkpatch warnings: WARNING: Avoid unnecessary line continuations WARNING: line over 80 characters Not sure which warning should be preferred. Any testing and/or review would be welcome. [1] https://www.spinics.net/lists/devicetree/msg277129.html Bruno Thomsen (1): board: tq mba7 tqma7d 1gb emmc support. arch/arm/mach-imx/Kconfig | 2 +- arch/arm/mach-imx/cpu.c | 2 +- arch/arm/mach-imx/mx7/Kconfig | 9 + arch/arm/mach-imx/mx7/soc.c | 7 + board/tqc/common/Kconfig | 4 + board/tqc/common/Makefile | 10 + board/tqc/common/tqc_bb.h | 30 ++ board/tqc/common/tqc_emmc.c | 78 board/tqc/common/tqc_emmc.h | 12 + board/tqc/tqma7/Kconfig | 79 board/tqc/tqma7/MAINTAINERS | 8 + board/tqc/tqma7/Makefile | 9 + board/tqc/tqma7/README| 38 ++ board/tqc/tqma7/tqma7.c | 328 ++ board/tqc/tqma7/tqma7_mba7.c | 596 ++ board/tqc/tqma7/tqma7d.cfg| 68 +++ board/tqc/tqma7/tqma7d_ddr_1gb.cfg| 58 +++ board/tqc/tqma7/tqma7d_ddr_512mb.cfg | 58 +++ configs/tqma7d_1gb_mba7_mmc_defconfig | 50 +++ include/configs/tqma7.h | 426 ++ include/configs/tqma7_mba7.h | 35 ++ 21 files changed, 1905 insertions(+), 2 deletions(-) create mode 100644 board/tqc/common/Kconfig create mode 100644 board/tqc/common/Makefile create mode 100644 board/tqc/common/tqc_bb.h create mode 100644 board/tqc/common/tqc_emmc.c create mode 100644 board/tqc/common/tqc_emmc.h create mode 100644 board/tqc/tqma7/Kconfig create mode 100644 board/tqc/tqma7/MAINTAINERS create mode 100644 board/tqc/tqma7/Makefile create mode 100644 board/tqc/tqma7/README create mode 100644 board/tqc/tqma7/tqma7.c create mode 100644 board/tqc/tqma7/tqma7_mba7.c create mode 100644 board/tqc/tqma7/tqma7d.cfg create mode 100644 board/tqc/tqma7/tqma7d_ddr_1gb.cfg create mode 100644 board/tqc/tqma7/tqma7d_ddr_512mb.cfg create mode 100644 configs/tqma7d_1gb_mba7_mmc_defconfig create mode 100644 include/configs/tqma7.h create mode 100644 include/configs/tqma7_mba7.h -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] ARM: renesas: Configure DRAM size from ATF DT fragment
On 3/12/19 8:30 PM, Eugeniu Rosca wrote: > Hi Marek cc: Michael Hi, > On Tue, Mar 5, 2019 at 4:37 AM Marek Vasut wrote: >> >> The ATF can pass additional information via the first four registers, >> x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer >> to a device tree with platform information. Parse this device tree and >> extract DRAM size information from it. This is useful on systems where >> the DRAM size can vary between configurations. > > 1. Do the ATF changes supporting this feature already exist in mainline ATF? Yes, for quite some time, see commit 1d85c4bd5b6291b99feb2409525c96f0c1744328 plat: rcar: Pass DTB with DRAM layout from BL2 to next stages > 2. I see more DRAM-related compile-time knobs in vanilla ATF: > ➜ arm-trusted-firmware (c48d02bade88) $ grep "DRAM.*:" > plat/renesas/rcar/platform.mk > RCAR_DRAM_SPLIT := 0 > RCAR_DRAM_LPDDR4_MEMCONF :=1 > RCAR_DRAM_DDR3L_MEMCONF :=1 > RCAR_DRAM_DDR3L_MEMDUAL :=1 > RCAR_DRAM_CHANNEL :=15 > > My understanding is that these are local to ATF and U-Boot can stay > agnostic about them? Yes, although the long term goal is to get rid of those and replace them with DT configuration too. So ATF BL2 would then parse supplied DT to figure out the DRAM layout instead of using those knobs. > IOW, DRAM start and size are totally enough for U-Boot? No, U-Boot needs to know start/size of each bank. That's what's in the DT that is passed in, plus a machine compatible string, so technically, you might be able to build one U-Boot for all boards already, but then you hit a size limit where the BL33 must be below 1 MiB. I'm looking into that one too. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] ARM: renesas: Save boot parameters passed in by ATF
On 3/12/19 9:29 PM, Eugeniu Rosca wrote: > Hi Tom, Hi, > On Tue, Mar 12, 2019 at 03:42:24PM -0400, Tom Rini wrote: >> On Tue, Mar 12, 2019 at 07:59:40PM +0100, Eugeniu Rosca wrote: >>> Hi Marek, >>> >>> On Tue, Mar 5, 2019 at 4:41 AM Marek Vasut wrote: >>> [..] +.align 8 +.globl rcar_atf_boot_args +rcar_atf_boot_args: + .dword 0 + .dword 0 + .dword 0 + .dword 0 + +ENTRY(save_boot_params) + adr x8, rcar_atf_boot_args + stp x0, x1, [x8], #16 + stp x2, x3, [x8], #16 + b save_boot_params_ret +ENDPROC(save_boot_params) >>> >>> What about relocating the function to C like in [1] and passing the 4 >>> arguments to it from ASM like in [2]? >>> This would allow to: >>> - reduce asm operations to minimum (mov and bl) and make code transparent. >>> - avoid custom globals and store the ATF information in some C-defined >>> struct. >>> >>> [1] >>> https://github.com/ARM-software/arm-trusted-firmware/blob/c48d02bade88b07fa7f43aa44e5217f68e5d047f/bl1/bl1_main.c#L263 >>> [2] >>> https://github.com/ARM-software/arm-trusted-firmware/blob/c48d02bade88b07fa7f43aa44e5217f68e5d047f/bl1/aarch32/bl1_exceptions.S#L133 >> >> This is super early in the boot process and I'm really not a fan in >> general of writing and calling C before we have things setup for C calls >> to actually work normally, even more so for small things that can be >> commented to be obvious as to what's going on. > > I don't have a strong preference about that. It is just my experience > that Renesas once rewrote the elaborate Bosch-contributed BL2 routine > of enabling the cntfrq_el0 system counter from ASM [1] to C [2]. At that point, BL2 already has a C runtime set up. This code is instead running without the C runtime and we want to make sure the correct registers get stored at the correct location, without the compiler interfering with it in any way. Keep in mind this code runs right at the beginning of U-Boot execution to make sure registers used to pass parameters stay intact (which I believe is what Tom meant by "early in the boot process"). > This > is at the BL1-BL2 boundary, while we are still in EL3, so much earlier > in the boot process. This implementation currently runs on the targets > of our customers. > > I am fine with any working solution. Thanks for commenting! > > [1] > https://github.com/renesas-rcar/arm-trusted-firmware/commit/e23524689abb637b14a2961a305f6cfb43909319 > [2] > https://github.com/renesas-rcar/arm-trusted-firmware/commit/867d84191319#diff-471251fb86bd634ba14891d950c1440eR177 > >> -- >> Tom > > Best regards, > Eugeniu. > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/4] configs: socfpga: socrates: enable rtc support
This enables DM_RTC and RTC_M41T62 to enable support for the rtc on the socrates board. Signed-off-by: Simon Goldschmidt --- configs/socfpga_socrates_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 45fd78a15c..242d938f9c 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -61,6 +61,8 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_DM_RTC=y +CONFIG_RTC_M41T62=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/4] i2c: designware: fix reset handling on socfpga gen5
Using this driver on socfpga gen5 with DM_I2C enabled leads to a data abort
as the 'i2c' reset property cannot be found (the gen5 dtsi does not provide
reset-names).
The actual bug was to check 'if (>reset_ctl)', which is never false.
While at it, convert the driver to use 'reset_get_bulk' instead of looking
at a specific named reset and also make it release the reset on driver
remove before starting the OS.
Fixes: 622597dee4f6 ("i2c: designware: add reset ctrl to driver")
Signed-off-by: Simon Goldschmidt
---
drivers/i2c/designware_i2c.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 63e40823f1..9ccc2411a6 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -34,7 +34,7 @@ static struct dw_scl_sda_cfg byt_config = {
struct dw_i2c {
struct i2c_regs *regs;
struct dw_scl_sda_cfg *scl_sda_cfg;
- struct reset_ctl reset_ctl;
+ struct reset_ctl_bulk resets;
};
#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
@@ -562,16 +562,22 @@ static int designware_i2c_probe(struct udevice *bus)
priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
}
- ret = reset_get_by_name(bus, "i2c", >reset_ctl);
+ ret = reset_get_bulk(bus, >resets);
if (ret)
- pr_info("reset_get_by_name() failed: %d\n", ret);
-
- if (>reset_ctl)
- reset_deassert(>reset_ctl);
+ dev_warn(bus, "Can't get reset: %d\n", ret);
+ else
+ reset_deassert_bulk(>resets);
return __dw_i2c_init(priv->regs, 0, 0);
}
+static int designware_i2c_remove(struct udevice *dev)
+{
+ struct dw_i2c *priv = dev_get_priv(dev);
+
+ return reset_release_bulk(>resets);
+}
+
static int designware_i2c_bind(struct udevice *dev)
{
static int num_cards;
@@ -613,6 +619,8 @@ U_BOOT_DRIVER(i2c_designware) = {
.bind = designware_i2c_bind,
.probe = designware_i2c_probe,
.priv_auto_alloc_size = sizeof(struct dw_i2c),
+ .remove = designware_i2c_remove,
+ .flags = DM_FLAG_OS_PREPARE,
.ops= _i2c_ops,
};
--
2.17.1
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[U-Boot] [PATCH 3/4] arm: socfpga: socrates: make rtc work
This patch makes the on-board RTC work on the socfpga_socrates board.
This rtc is present on the board, but it does not work (fails with a
timeout).
This patch adds a weak pull-up on the I2C0-SCL pin connected to the m41t82
RTC on this board. While the SDA line has a pull-up on the pcb, the pull-up
on the SCL line seems to be missing. To work around this, enable the
weak-pull-up feature on this pin.
After applying this patch, the rtc timeout is gone and the 'date' command
can access the rtc chip.
Signed-off-by: Simon Goldschmidt
---
board/ebv/socrates/qts/iocsr_config.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/ebv/socrates/qts/iocsr_config.h
b/board/ebv/socrates/qts/iocsr_config.h
index 011fa2bac3..18b9c6ce4d 100644
--- a/board/ebv/socrates/qts/iocsr_config.h
+++ b/board/ebv/socrates/qts/iocsr_config.h
@@ -108,7 +108,7 @@ const unsigned long iocsr_scan_chain2_table[] = {
0x00018004,
0x06001209,
0x4000,
- 0x20002412,
+ 0x20042412,
0x00904800,
0x0030,
0x8000,
--
2.17.1
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[U-Boot] [PATCH 2/4] rtc: m41t62: add compatible for m41t82
This adds a compatible string for m41t82. This ensures that this driver
can be used for m41t82 in DM mode, too (as it was usable for this model
in non-DM mode before).
This patch ensures this driver works on socfpga_socrates.
Signed-off-by: Simon Goldschmidt
---
drivers/rtc/m41t62.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c
index 2ee7e00b02..4b5bf8e7a0 100644
--- a/drivers/rtc/m41t62.c
+++ b/drivers/rtc/m41t62.c
@@ -163,6 +163,7 @@ static const struct rtc_ops m41t62_rtc_ops = {
static const struct udevice_id m41t62_rtc_ids[] = {
{ .compatible = "st,m41t62" },
+ { .compatible = "st,m41t82" },
{ .compatible = "microcrystal,rv4162" },
{ }
};
--
2.17.1
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[U-Boot] [PATCH 0/4] arm: socfpga: enable rtc support for the socrates board
This series contains fixes and config changes to enable the 'date' command talking to the rtc on the socrates board. It contains fixes to the designware i2c driver, enables DM support for the rtc used on the socrates board, adds a missing pull-up and changes the defconfig to enable rtc support by default. Simon Goldschmidt (4): i2c: designware: fix reset handling on socfpga gen5 rtc: m41t62: add compatible for m41t82 arm: socfpga: socrates: make rtc work configs: socfpga: socrates: enable rtc support board/ebv/socrates/qts/iocsr_config.h | 2 +- configs/socfpga_socrates_defconfig| 2 ++ drivers/i2c/designware_i2c.c | 20 ++-- drivers/rtc/m41t62.c | 1 + 4 files changed, 18 insertions(+), 7 deletions(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] spl: add Kconfig option to clear bss early
Am 12.03.2019 um 07:02 schrieb Stefan Roese: Hi Simon, On 11.03.19 22:35, Simon Goldschmidt wrote: This introduces a new Kconfig option SPL_CLEAR_BSS_F. If enabled, it clears the bss before calling board_init_f() instead of clearing it before calling board_init_r(). This also ensures that variables placed in BSS can be shared between board_init_f() and board_init_r() in SPL. Signed-off-by: Simon Goldschmidt --- common/spl/Kconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 206c24076d..5da8697994 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -156,6 +156,17 @@ config SPL_STACK_R_MALLOC_SIMPLE_LEN to give board_init_r() a larger heap then the initial heap in SRAM which is limited to SYS_MALLOC_F_LEN bytes. +config SPL_CLEAR_BSS_F + bool "Clear BSS section before calling board_init_f" + help + The BSS section is initialized to zero. In SPL, this is normally done + before calling board_init_r(). + For platforms using BSS in board_init_f() already, enable this to + clear the BSS section before calling board_init_f() instead of + clearing it before calling board_init_r(). This also ensures that + variables placed in BSS can be shared between board_init_f() and + board_init_r(). + You should probably depend this option on "ARM", as your implementation is currently only for this arch. Otherwise users might expect this to work on other platforms as well. Hmm, ok. I thought it might be worth leaving this visible for everyone. But you're right that people migh rely on this to work where it's not implemented... I'll add that dependency in v2. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] ARM: renesas: Save boot parameters passed in by ATF
Hi Tom, On Tue, Mar 12, 2019 at 03:42:24PM -0400, Tom Rini wrote: > On Tue, Mar 12, 2019 at 07:59:40PM +0100, Eugeniu Rosca wrote: > > Hi Marek, > > > > On Tue, Mar 5, 2019 at 4:41 AM Marek Vasut wrote: > > [..] > > > +.align 8 > > > +.globl rcar_atf_boot_args > > > +rcar_atf_boot_args: > > > + .dword 0 > > > + .dword 0 > > > + .dword 0 > > > + .dword 0 > > > + > > > +ENTRY(save_boot_params) > > > + adr x8, rcar_atf_boot_args > > > + stp x0, x1, [x8], #16 > > > + stp x2, x3, [x8], #16 > > > + b save_boot_params_ret > > > +ENDPROC(save_boot_params) > > > > What about relocating the function to C like in [1] and passing the 4 > > arguments to it from ASM like in [2]? > > This would allow to: > > - reduce asm operations to minimum (mov and bl) and make code transparent. > > - avoid custom globals and store the ATF information in some C-defined > > struct. > > > > [1] > > https://github.com/ARM-software/arm-trusted-firmware/blob/c48d02bade88b07fa7f43aa44e5217f68e5d047f/bl1/bl1_main.c#L263 > > [2] > > https://github.com/ARM-software/arm-trusted-firmware/blob/c48d02bade88b07fa7f43aa44e5217f68e5d047f/bl1/aarch32/bl1_exceptions.S#L133 > > This is super early in the boot process and I'm really not a fan in > general of writing and calling C before we have things setup for C calls > to actually work normally, even more so for small things that can be > commented to be obvious as to what's going on. I don't have a strong preference about that. It is just my experience that Renesas once rewrote the elaborate Bosch-contributed BL2 routine of enabling the cntfrq_el0 system counter from ASM [1] to C [2]. This is at the BL1-BL2 boundary, while we are still in EL3, so much earlier in the boot process. This implementation currently runs on the targets of our customers. I am fine with any working solution. Thanks for commenting! [1] https://github.com/renesas-rcar/arm-trusted-firmware/commit/e23524689abb637b14a2961a305f6cfb43909319 [2] https://github.com/renesas-rcar/arm-trusted-firmware/commit/867d84191319#diff-471251fb86bd634ba14891d950c1440eR177 > -- > Tom Best regards, Eugeniu. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] ARM: renesas: Save boot parameters passed in by ATF
On Tue, Mar 12, 2019 at 07:59:40PM +0100, Eugeniu Rosca wrote: > Hi Marek, > > On Tue, Mar 5, 2019 at 4:41 AM Marek Vasut wrote: > [..] > > +.align 8 > > +.globl rcar_atf_boot_args > > +rcar_atf_boot_args: > > + .dword 0 > > + .dword 0 > > + .dword 0 > > + .dword 0 > > + > > +ENTRY(save_boot_params) > > + adr x8, rcar_atf_boot_args > > + stp x0, x1, [x8], #16 > > + stp x2, x3, [x8], #16 > > + b save_boot_params_ret > > +ENDPROC(save_boot_params) > > What about relocating the function to C like in [1] and passing the 4 > arguments to it from ASM like in [2]? > This would allow to: > - reduce asm operations to minimum (mov and bl) and make code transparent. > - avoid custom globals and store the ATF information in some C-defined > struct. > > [1] > https://github.com/ARM-software/arm-trusted-firmware/blob/c48d02bade88b07fa7f43aa44e5217f68e5d047f/bl1/bl1_main.c#L263 > [2] > https://github.com/ARM-software/arm-trusted-firmware/blob/c48d02bade88b07fa7f43aa44e5217f68e5d047f/bl1/aarch32/bl1_exceptions.S#L133 This is super early in the boot process and I'm really not a fan in general of writing and calling C before we have things setup for C calls to actually work normally, even more so for small things that can be commented to be obvious as to what's going on. -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] ARM: renesas: Configure DRAM size from ATF DT fragment
Hi Marek cc: Michael On Tue, Mar 5, 2019 at 4:37 AM Marek Vasut wrote: > > The ATF can pass additional information via the first four registers, > x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer > to a device tree with platform information. Parse this device tree and > extract DRAM size information from it. This is useful on systems where > the DRAM size can vary between configurations. 1. Do the ATF changes supporting this feature already exist in mainline ATF? 2. I see more DRAM-related compile-time knobs in vanilla ATF: ➜ arm-trusted-firmware (c48d02bade88) $ grep "DRAM.*:" plat/renesas/rcar/platform.mk RCAR_DRAM_SPLIT := 0 RCAR_DRAM_LPDDR4_MEMCONF :=1 RCAR_DRAM_DDR3L_MEMCONF :=1 RCAR_DRAM_DDR3L_MEMDUAL :=1 RCAR_DRAM_CHANNEL :=15 My understanding is that these are local to ATF and U-Boot can stay agnostic about them? IOW, DRAM start and size are totally enough for U-Boot? TIA! Best regards, Eugeniu. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] ARM: renesas: Save boot parameters passed in by ATF
Hi Marek, On Tue, Mar 5, 2019 at 4:41 AM Marek Vasut wrote: [..] > +.align 8 > +.globl rcar_atf_boot_args > +rcar_atf_boot_args: > + .dword 0 > + .dword 0 > + .dword 0 > + .dword 0 > + > +ENTRY(save_boot_params) > + adr x8, rcar_atf_boot_args > + stp x0, x1, [x8], #16 > + stp x2, x3, [x8], #16 > + b save_boot_params_ret > +ENDPROC(save_boot_params) What about relocating the function to C like in [1] and passing the 4 arguments to it from ASM like in [2]? This would allow to: - reduce asm operations to minimum (mov and bl) and make code transparent. - avoid custom globals and store the ATF information in some C-defined struct. [1] https://github.com/ARM-software/arm-trusted-firmware/blob/c48d02bade88b07fa7f43aa44e5217f68e5d047f/bl1/bl1_main.c#L263 [2] https://github.com/ARM-software/arm-trusted-firmware/blob/c48d02bade88b07fa7f43aa44e5217f68e5d047f/bl1/aarch32/bl1_exceptions.S#L133 Best regards, Eugeniu. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2] Revert "pico-imx7d: Add LCD support"
Hi
On Mon, Mar 11, 2019 at 10:47 PM Joris Offouga wrote:
>
> This reverts commit 9e3c0174da842dd88f5feaffbf843ba332233897.
>
> This commit breaks U-Boot when is load with imx-usb-loader.
>
> Signed-off-by: Joris Offouga
Can you try just define CONFIG_SYS_MALLOC_F_LEN=0x2000.
What is the value on your platform? we found it important on some SPL boot
scenario
Michael
> ---
> Changes for v2:
> - Add missing signed-off
> ---
> board/technexion/pico-imx7d/pico-imx7d.c | 55
>
> configs/pico-hobbit-imx7d_defconfig | 1 -
> configs/pico-imx7d_defconfig | 1 -
> configs/pico-pi-imx7d_defconfig | 1 -
> include/configs/pico-imx7d.h | 12 ---
> 5 files changed, 70 deletions(-)
>
> diff --git a/board/technexion/pico-imx7d/pico-imx7d.c
> b/board/technexion/pico-imx7d/pico-imx7d.c
> index 767d13d..53e1469 100644
> --- a/board/technexion/pico-imx7d/pico-imx7d.c
> +++ b/board/technexion/pico-imx7d/pico-imx7d.c
> @@ -39,16 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
> #define I2C_PAD_CTRL(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
> PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
>
> -
> -#define LCD_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
> -PAD_CTL_DSE_3P3V_49OHM)
> -
> -#define LCD_SYNC_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
> - PAD_CTL_DSE_3P3V_196OHM)
> -
> #ifdef CONFIG_SYS_I2C_MXC
> #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> -
> /* I2C4 for PMIC */
> static struct i2c_pads_info i2c_pad_info4 = {
> .scl = {
> @@ -254,58 +246,11 @@ int board_early_init_f(void)
> return 0;
> }
>
> -#ifdef CONFIG_VIDEO_MXS
> -static iomux_v3_cfg_t const lcd_pads[] = {
> - MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
> - MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
> - MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
> - MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
> - MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
> -};
> -
> -void setup_lcd(void)
> -{
> - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
> - /* Set Brightness to high */
> - gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
> - /* Set LCD enable to high */
> - gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
> -}
> -#endif
> -
> int board_init(void)
> {
> /* address of boot parameters */
> gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>
> -#ifdef CONFIG_VIDEO_MXS
> - setup_lcd();
> -#endif
> #ifdef CONFIG_FEC_MXC
> setup_fec();
> #endif
> diff --git a/configs/pico-hobbit-imx7d_defconfig
> b/configs/pico-hobbit-imx7d_defconfig
> index f58d517..cb4a6bf 100644
> --- a/configs/pico-hobbit-imx7d_defconfig
> +++ b/configs/pico-hobbit-imx7d_defconfig
> @@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_CI_UDC=y
> -CONFIG_VIDEO=y
> CONFIG_OF_LIBFDT=y
> diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
> index 7e13923..f90d757 100644
Re: [U-Boot] [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig
Hi Y.B., On 01/03/19 04:15, Y.b. Lu wrote: > Any comments on the patch-set? > Thanks a lot. Patch is tin the right direction, it just touch (as it must be) a huge number of boards. I cannot pick it up now, so I will push it into my -next branch. Regards, Stefano > >> -Original Message- >> From: Y.b. Lu >> Sent: Thursday, February 21, 2019 3:55 PM >> To: u-boot@lists.denx.de >> Cc: Jaehoon Chung ; Prabhakar Kushwaha >> ; Peng Fan ; Lukasz >> Majewski ; Y.b. Lu >> Subject: [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig >> >> Moved CONFIG_FSL_ESDHC from header files to defconfig files. >> >> Signed-off-by: Yangbo Lu >> --- >> configs/imx8mq_evk_defconfig | 1 + >> configs/imx8qxp_mek_defconfig | 1 + >> configs/kp_imx53_defconfig | 1 + >> configs/kp_imx6q_tpc_defconfig | 1 + >> configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + >> configs/ls1012afrwy_qspi_defconfig | 1 + >> configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + >> configs/ls1012afrwy_tfa_defconfig | 1 + >> include/configs/imx8mq_evk.h | 1 - >> include/configs/imx8qxp_mek.h | 1 - >> include/configs/kp_imx53.h | 1 - >> include/configs/kp_imx6q_tpc.h | 1 - >> include/configs/ls1012afrwy.h | 1 - >> 13 files changed, 8 insertions(+), 5 deletions(-) >> >> diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig >> index 53025e45bc..8f6d66b741 100644 >> --- a/configs/imx8mq_evk_defconfig >> +++ b/configs/imx8mq_evk_defconfig >> @@ -27,6 +27,7 @@ CONFIG_DM_GPIO=y >> CONFIG_DM_I2C=y >> CONFIG_SYS_I2C_MXC=y >> CONFIG_DM_MMC=y >> +CONFIG_FSL_ESDHC=y >> CONFIG_DM_ETH=y >> CONFIG_PINCTRL=y >> CONFIG_DM_REGULATOR=y >> diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig >> index a94998b8b5..88da3ac784 100644 >> --- a/configs/imx8qxp_mek_defconfig >> +++ b/configs/imx8qxp_mek_defconfig >> @@ -51,6 +51,7 @@ CONFIG_I2C_MUX=y >> CONFIG_I2C_MUX_PCA954x=y >> CONFIG_MISC=y >> CONFIG_DM_MMC=y >> +CONFIG_FSL_ESDHC=y >> CONFIG_PHYLIB=y >> CONFIG_PHY_ADDR_ENABLE=y >> CONFIG_PHY_ATHEROS=y >> diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index >> cfe96fcce5..d00c8cde62 100644 >> --- a/configs/kp_imx53_defconfig >> +++ b/configs/kp_imx53_defconfig >> @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y >> CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" >> CONFIG_ENV_IS_IN_MMC=y >> +CONFIG_FSL_ESDHC=y >> CONFIG_I2C_SET_DEFAULT_BUS_NUM=y >> CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 >> CONFIG_PHYLIB=y >> diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig >> index cb58ed6678..3f48463c0c 100644 >> --- a/configs/kp_imx6q_tpc_defconfig >> +++ b/configs/kp_imx6q_tpc_defconfig >> @@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y # >> CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set >> CONFIG_ENV_IS_IN_MMC=y >> +CONFIG_FSL_ESDHC=y >> CONFIG_PHYLIB=y >> CONFIG_PHY_ATHEROS=y >> CONFIG_FEC_MXC=y >> diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig >> b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig >> index c273dc937e..35a606ce23 100644 >> --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig >> +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig >> @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y >> # CONFIG_BLK is not set CONFIG_DM_MMC=y >> +CONFIG_FSL_ESDHC=y >> CONFIG_DM_SPI_FLASH=y >> CONFIG_SPI_FLASH=y >> CONFIG_SPI_FLASH_WINBOND=y >> diff --git a/configs/ls1012afrwy_qspi_defconfig >> b/configs/ls1012afrwy_qspi_defconfig >> index 85523ba2d3..50068a12d7 100644 >> --- a/configs/ls1012afrwy_qspi_defconfig >> +++ b/configs/ls1012afrwy_qspi_defconfig >> @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y >> # CONFIG_BLK is not set CONFIG_DM_MMC=y >> +CONFIG_FSL_ESDHC=y >> CONFIG_DM_SPI_FLASH=y >> CONFIG_SPI_FLASH=y >> CONFIG_SPI_FLASH_WINBOND=y >> diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig >> b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig >> index d9020c5281..1b281c90a2 100644 >> --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig >> +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig >> @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y >> # CONFIG_BLK is not set CONFIG_DM_MMC=y >> +CONFIG_FSL_ESDHC=y >> CONFIG_DM_SPI_FLASH=y >> CONFIG_SPI_FLASH=y >> CONFIG_SPI_FLASH_WINBOND=y >> diff --git a/configs/ls1012afrwy_tfa_defconfig >> b/configs/ls1012afrwy_tfa_defconfig >> index 08b3692f97..060cf47156 100644 >> --- a/configs/ls1012afrwy_tfa_defconfig >> +++ b/configs/ls1012afrwy_tfa_defconfig >> @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y >> # CONFIG_BLK is not set CONFIG_DM_MMC=y >> +CONFIG_FSL_ESDHC=y >> CONFIG_DM_SPI_FLASH=y >> CONFIG_SPI_FLASH=y >> CONFIG_SPI_FLASH_WINBOND=y >> diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h >> index f0430224cb..492e89a20c
Re: [U-Boot] passing info from SPL to U-Boot
Dear Tom, In message <20190312173125.GP4690@bill-the-cat> you wrote: > > > I think you were misled by Heiko's description. What he really ment > > was just that the addresses where the boot ROM stored the > > information about the boot device etc. gets overwriteen when the SPL > > For clarity, that's not _quite_ it. The ROM passes the value in a > register and we move that to scratch space, see > arch/arm/mach-omap2/lowlevel_init.S and save_boot_params. This is done > on every 32bit Cortex-A TI platform. ... > OK, but here's the problem. We define off, iirc, 1KiB of that SRAM > space as not-stack but scratch space to store stuff in. The first > problem you will hit, if something else touches that scratch space is > what Heiko found, the boot value got blown away. I see. Well, I think it's best if Heiko explains in detail; what he has observed, and what when which part of the information got lost. I was just interpreting his mail, so I may easily have misunderstood this. @ Heiko: Can you please elucidate? > I agree here. Fixing things up such that we can pass things we know > =66rom one stage to another in a defined manner, rather than ad-hoc > manner, is good. We could even, probably, re-work most of that use of > scratch space to be done in another way, or make it safe to re-use > later. Thanks a lot! Let's go for it. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de No man knows what true happiness is until he gets married. By then, of course, its too late. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] imx8mq_evk_defconfig: Enable pinctrl driver
On 11/03/19 18:36, Chris Spencer wrote:
> On Sat, 2 Mar 2019 at 06:27, Peng Fan wrote:
>>> On Mon, 4 Feb 2019 at 10:05, Chris Spencer wrote:
From: Chris Spencer
The Ethernet controller is not able to initialise correctly without
the pinctrl driver.
This config setting was enabled in the initial version of this file,
but was removed by a savedefconfig resync because the parameter did
not actually exist at that point.
Fixes: 1bac199e8c87 ("configs: Resync with savedefconfig")
Signed-off-by: Chris Spencer
Reviewed-by: Fabio Estevam
---
Depends on this patch:
>>> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
>>> chwork.ozlabs.org%2Fpatch%2F1031817%2Fdata=02%7C01%7Cpeng.f
>>> an%40n
>>> xp.com%7Cffae7c0ab2494a20159008d69e40ed2d%7C686ea1d3bc2b4c6fa92
>>> cd99c5c
>>> 301635%7C0%7C0%7C636870399030578148sdata=0tJenqE8zP4dFhLs
>>> HJJ5WO3n
Tmiyz%2FAZWeclKFp8wso%3Dreserved=0
Changes in v2:
- Added Fabio's Reviewed-by.
- Corrected From address.
>>>
>>> Since there hasn't been any activity on the i.MX8MM patch series for a
>>> while,
>>> I wonder if the pinctrl driver [1] could be committed in isolation? This
>>> patch
>>> could then be applied so we can get the Ethernet working on the i.MX8MQ.
>>>
>>
>> The blocking issue for i.MX8MM is clock part, for the pinctrl that
>> could be reused by i.MX8MQ, I think it could be committed, but need Stefano
>> to decide.
>>
>> Regards,
>> Peng.
>
> Any thoughts on this, Stefano? Would be good to get the pinctrl driver
> + defconfig change into 2019.04 if we can.
>
Fine with me - I have picked up pinctrl driver (pathc 19/20) and this
one for my last PR to Tom before release.
Regards,
Stefano
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
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Re: [U-Boot] passing info from SPL to U-Boot
On Tue, Mar 12, 2019 at 06:08:32PM +0100, Wolfgang Denk wrote: > Dear Tom, > > In message <20190312140417.GJ4690@bill-the-cat> you wrote: > > > > To answer that, no, I don't suppose there's a problem with auditing the > > code to make sure that we can pass in gd, rather than U-Boot proper > > assuming it's the first thing to touch gd, if configured. > > > But that to > > me is a different ball of wax. On this SoC, if you're at the point > > where you're trampling over the defined scratch space that is used for > > other things that need scratch space, you may have other problems too. > > I think you were misled by Heiko's description. What he really ment > was just that the addresses where the boot ROM stored the > information about the boot device etc. gets overwriteen when the SPL For clarity, that's not _quite_ it. The ROM passes the value in a register and we move that to scratch space, see arch/arm/mach-omap2/lowlevel_init.S and save_boot_params. This is done on every 32bit Cortex-A TI platform. > sets up his stack. This is what Heiko meant when he wrote: "On > am437x the bootmode info get overwritten from SPL stack." But at > that time the SPL has already loaded this information and maintains > it elsewhere. OK, but here's the problem. We define off, iirc, 1KiB of that SRAM space as not-stack but scratch space to store stuff in. The first problem you will hit, if something else touches that scratch space is what Heiko found, the boot value got blown away. But there's other stuff we do in there, more on other SoCs than others, but you're asking for trouble. To be clearer, IMHO, arch/arm/mach-omap2/u-boot-spl.lds is missing a build-time check to make sure things can't bleed into that area. You can't use that scratch space for two non-cooperating uses. If we've malloced out that area, we better not need that allocated area when hw_data_init() scribbles in there. That's my point. > I am not aware of any other problems. Of course one has to re-think > where to place the GD - but this is the same problem as when using > the bloblist and spl_handoff data. > > I just feel it makes a lot of sense to use an existing mechanism > across all the boot stages SPL -> ( TPL -> ) U-Boot before > relocation -> U-Boot after relocation, instead of implementing > several different hooks for the same purpose. > > [And yes, it might be also time to clean up GD from a lot of mess > that has accumulated there over the last decade. I doubt many of > these data are really needed there. But that's another topic, IMO.] I agree here. Fixing things up such that we can pass things we know from one stage to another in a defined manner, rather than ad-hoc manner, is good. We could even, probably, re-work most of that use of scratch space to be done in another way, or make it safe to re-use later. -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: dm: fec: Support phy-reset-post-delay property
Hi Anatolij, On Tue, Mar 12, 2019 at 4:10 AM Anatolij Gustschin wrote: > > Hi Joe, > > On Tue, 5 Mar 2019 12:05:38 -0600 > Joe Hershberger joe.hershber...@ni.com wrote: > > > Hi Andrejs, > > > > https://patchwork.ozlabs.org/patch/1050177/ was applied to > > http://git.denx.de/?p=u-boot/u-boot-net.git > > This patch is not in mainline tree yet, but it is marked as accepted > on patchwork. Could you please check? This is part of a bug-fix for > broken ethernet on the board and should go into v2019.04 release. Yes, it should go into this release. Hopefully Tom will pull it in shortly. Thanks, -Joe > Thanks, > Anatolij > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-net.git master
Hi Tom, These patches passed the CI build here: https://travis-ci.org/jhershbe/u-boot/builds/501807294 The following changes since commit 2e8092d94f40a5692baf3ec768ce3216a7bf032a: Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2019-03-11 15:48:57 -0400) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to 85f05f72bacc2d047731fc64801e4f6b34cf: net: phy: aquantia: Set only autoneg on in register 4.c441 (2019-03-12 13:13:37 -0500) Andrejs Cainikovs (2): net: dm: fec: Support phy-reset-post-delay property dts: imx8qxp-mek: Add PHY post reset delay Carlo Caione (4): net: phy: realtek: Introduce quirk to mark RXC not stoppable net: phy: Add generic helpers to access MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Switch to generic helpers when accessing the registers James Byrne (2): net: phy: micrel: Use correct skew values on KSZ9021 net: phy: micrel: Find Micrel PHY node correctly Meenakshi Aggarwal (1): mc : Reduce MC memory size to 128M Murali Karicheri (7): ARM: k2g-gp-evm: update to rgmii pinmux configuration ARM: k2g-ice: Add pinmux support for rgmii interface net: netcp: add support for phy with rgmii ids ARM: k2g: add a workaround to reset the phy ARM: dts: k2g-evm: remove unused phy-mode property from phy node k2g: config enable ti phy dp83867 for k2g ARM: dts: k2g-ice: add dt node for netcp Pankaj Bansal (1): drivers: net: ldpaa_eth: fix resource leak Siva Durga Prasad Paladugu (2): net: phy: Reloc next and prev pointers inside phy_drivers net: phy: Fix return value check phy_probe Valentin-catalin Neacsu (1): net: phy: aquantia: Set only autoneg on in register 4.c441 Vladimir Oltean (6): net: phy: ar803x: Address packet drops at low traffic rate due to SmartEEE feature net: phy: ar803x: Make RGMII Tx delays actually configurable for AR8035 net: phy: ar803x: Use common functions for RGMII internal delays net: phy: ar803x: Clarify the configuration of the CLK_25M output pin net: phy: ar803x: Explicitly disable RGMII delays net: phy: ar803x: Clarify the intention of ar8021_config arch/arm/dts/fsl-imx8qxp-mek.dts | 1 + arch/arm/dts/keystone-k2g-evm.dts | 1 - arch/arm/dts/keystone-k2g-ice.dts | 35 ++ arch/arm/dts/sama5d3xcm.dtsi | 32 ++--- arch/arm/dts/sama5d3xcm_cmp.dtsi | 32 ++--- arch/arm/dts/socfpga_arria5_socdk.dts | 4 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 4 +- arch/arm/dts/socfpga_cyclone5_socdk.dts| 4 +- arch/arm/dts/socfpga_cyclone5_sockit.dts | 4 +- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 4 +- arch/arm/mach-keystone/include/mach/hardware-k2g.h | 3 + arch/arm/mach-keystone/include/mach/mux-k2g.h | 5 + board/ti/ks2_evm/board_k2g.c | 15 +++ board/ti/ks2_evm/mux-k2g.h | 51 +--- cmd/mdio.c | 27 +++-- configs/k2g_evm_defconfig | 1 + doc/device-tree-bindings/net/micrel-ksz90x1.txt| 27 + drivers/net/fec_mxc.c | 11 ++ drivers/net/fec_mxc.h | 1 + drivers/net/fsl-mc/mc.c| 22 +++- drivers/net/ldpaa_eth/ldpaa_eth.c | 1 + drivers/net/phy/Kconfig| 41 +++ drivers/net/phy/aquantia.c | 7 +- drivers/net/phy/atheros.c | 128 ++-- drivers/net/phy/micrel_ksz90x1.c | 24 +++- drivers/net/phy/phy.c | 21 +++- drivers/net/phy/realtek.c | 19 +++ drivers/net/phy/ti.c | 130 - drivers/net/ti/keystone_net.c | 22 +++- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 2 +- include/phy.h | 70 +++ 33 files changed, 526 insertions(+), 227 deletions(-) Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] passing info from SPL to U-Boot
Dear Tom, In message <20190312140417.GJ4690@bill-the-cat> you wrote: > > To answer that, no, I don't suppose there's a problem with auditing the > code to make sure that we can pass in gd, rather than U-Boot proper > assuming it's the first thing to touch gd, if configured. > But that to > me is a different ball of wax. On this SoC, if you're at the point > where you're trampling over the defined scratch space that is used for > other things that need scratch space, you may have other problems too. I think you were misled by Heiko's description. What he really ment was just that the addresses where the boot ROM stored the information about the boot device etc. gets overwriteen when the SPL sets up his stack. This is what Heiko meant when he wrote: "On am437x the bootmode info get overwritten from SPL stack." But at that time the SPL has already loaded this information and maintains it elsewhere. I am not aware of any other problems. Of course one has to re-think where to place the GD - but this is the same problem as when using the bloblist and spl_handoff data. I just feel it makes a lot of sense to use an existing mechanism across all the boot stages SPL -> ( TPL -> ) U-Boot before relocation -> U-Boot after relocation, instead of implementing several different hooks for the same purpose. [And yes, it might be also time to clean up GD from a lot of mess that has accumulated there over the last decade. I doubt many of these data are really needed there. But that's another topic, IMO.] Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You don't have to stay up nights to succeed; you have to stay awake days. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] board: tq mba7 tqma7d 1gb emmc support.
Hi Bruno,
On Tue, Mar 12, 2019 at 1:58 PM Bruno Thomsen wrote:
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 8631fbd481..0335c0e8db 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -46,7 +46,7 @@ config SECURE_BOOT
> config CMD_BMODE
> bool "Support the 'bmode' command"
> default y
> - depends on ARCH_MX6 || ARCH_MX5
> + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
This should be a separate patch.
> help
> This enables the 'bmode' (bootmode) command for forcing
> a boot from specific media.
> diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
> index 6b83f92662..113f228c86 100644
> --- a/arch/arm/mach-imx/cpu.c
> +++ b/arch/arm/mach-imx/cpu.c
> @@ -251,7 +251,7 @@ int cpu_eth_init(bd_t *bis)
> {
> int rc = -ENODEV;
>
> -#if defined(CONFIG_FEC_MXC)
> +#if defined(CONFIG_FEC_MXC) && defined(CONFIG_FEC_MXC_PHYADDR)
This one too.
Also, please consider converting this board to DM.
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Re: [U-Boot] [PATCH 4/4 v2] Makefile: Correct logic for DM_SCSI + unconverted drivers check
On Tue, Mar 12, 2019 at 07:46:35AM +0100, Stefan Roese wrote: > When checking for boards that are enabling a SATA driver that isn't > converted to DM yet we need to be sure to not also trip over boards that > do set CONFIG_AHCI & CONFIG_BLK by itself, as that is not a bug. > > This was detected when converting the Armada XP SATA driver sata_mv.c > to DM with AHCI & BLK support. This warning is still printed without > this patch applied here. > > Signed-off-by: Stefan Roese > Cc: Simon Glass > Cc: Tom Rini Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-sunxi/master
On Mon, Mar 11, 2019 at 10:59:35PM +0530, Jagan Teki wrote: > Hi Tom, > > Please pull this PR. > > Summary: > - axp818 fix > - fix warnings for ethernet clock code > > The following changes since commit f18b7b2798cc37b613b5d3dda2e1461857a913b8: > > Merge branch 'master' of git://git.denx.de/u-boot-spi (2019-03-06 20:25:09 > -0500) > > are available in the Git repository at: > > git://git.denx.de/u-boot-sunxi.git master > > for you to fetch changes up to aefc0b7a60b9147b79b7a735c045e28daba712f1: > > clk: sunxi: h3: Implement EPHY CLK and RESET (2019-03-09 13:16:35 +0530) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv2 3/6] dm: cache: Create a uclass for cache
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.
Add a uclass and a test for cache.
Signed-off-by: Dinh Nguyen
---
v2: separate out uclass patch from driver and add test
---
drivers/Kconfig | 2 ++
drivers/Makefile | 1 +
drivers/cache/Kconfig | 16
drivers/cache/Makefile| 3 +++
drivers/cache/cache-uclass.c | 13 +
drivers/cache/sandbox_cache.c | 34 ++
include/cache.h | 33 +
include/dm/uclass-id.h| 1 +
test/dm/cache.c | 19 +++
9 files changed, 122 insertions(+)
create mode 100644 drivers/cache/Kconfig
create mode 100644 drivers/cache/Makefile
create mode 100644 drivers/cache/cache-uclass.c
create mode 100644 drivers/cache/sandbox_cache.c
create mode 100644 include/cache.h
create mode 100644 test/dm/cache.c
diff --git a/drivers/Kconfig b/drivers/Kconfig
index f24351ac4f..842201b753 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
source "drivers/bootcount/Kconfig"
+source "drivers/cache/Kconfig"
+
source "drivers/clk/Kconfig"
source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..0a00096332 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
obj-y += block/
obj-y += board/
obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-$(CONFIG_FASTBOOT) += fastboot/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 00..8b7c9c7f9f
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,16 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+ bool "Enable Driver Model for Cache controllers"
+ depends on DM
+ help
+ Enable driver model for cache controllers that are found on
+ most CPU's. Cache is memory that the CPU can access directly and
+ is usually located on the same chip. This uclass can be used for
+ configuring settings that be found from a device tree file.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 00..2ba68060c1
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
new file mode 100644
index 00..dd72e3e00f
--- /dev/null
+++ b/drivers/cache/cache-uclass.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+#include
+#include
+
+UCLASS_DRIVER(cache) = {
+ .id = UCLASS_CACHE,
+ .name = "cache",
+ .post_bind = dm_scan_fdt_dev,
+};
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
new file mode 100644
index 00..b67ce31218
--- /dev/null
+++ b/drivers/cache/sandbox_cache.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+ info->base = 0;
+
+ return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+ .get_info = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+ { .compatible = "sandbox,cache" },
+ { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+ .name = "cache_sandbox",
+ .id = UCLASS_CACHE,
+ .of_match = sandbox_cache_ids,
+ .ops= _cache_ops,
+};
diff --git a/include/cache.h b/include/cache.h
new file mode 100644
index 00..7a6faaf11c
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+struct cache_info {
+ phys_addr_t base;
+};
+
+struct cache_ops {
+ /**
+* get_info() - Get basic cache info
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @info: Place to put info
+* @return 0 if OK, -ve on error
+*/
+ int (*get_info)(struct udevice *dev, struct cache_info *info);
+};
+
+/**
+ * cache_get_info() - Get information about a cache controller
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @info: Returns cache info
+ * @return 0 if OK, -ve on error
+ */
+int cache_get_info(struct udevice *dev, struct cache_info *info);
+
+#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 86e59781b0..09e0ad5391 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -34,6 +34,7
[U-Boot] [PATCHv2 5/6] ARM: socfpga: use the pl310 driver to configure the cache
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Reviewed-by: Marek Vasut
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/misc.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..34d8c4c51b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_enable(void)
{
- /* Disable the L2 cache */
- clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x0, >pl310_tag_latency_ctrl);
- writel(0x10, >pl310_data_latency_ctrl);
-
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+ struct udevice *dev;
- /* Enable the L2 cache */
- setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+ if (uclass_get_device(UCLASS_CACHE, 0, ))
+ pr_err("cache controller driver NOT found!\n");
}
void v7_outer_cache_disable(void)
--
2.20.0
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[U-Boot] [PATCHv2 4/6] dm: cache: add the pl310 cache controller driver
Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.
This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.
Signed-off-by: Dinh Nguyen
---
v2: split out patch and address comments from Simon Glass
---
drivers/cache/Kconfig | 9 +
drivers/cache/Makefile | 1 +
drivers/cache/cache-l2x0.c | 75 ++
3 files changed, 85 insertions(+)
create mode 100644 drivers/cache/cache-l2x0.c
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 8b7c9c7f9f..24def7ac0f 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -13,4 +13,13 @@ config CACHE
is usually located on the same chip. This uclass can be used for
configuring settings that be found from a device tree file.
+config L2X0_CACHE
+ tristate "PL310 cache driver"
+ select CACHE
+ depends on ARM
+ help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 2ba68060c1..9deb961d91 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_CACHE) += cache-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
new file mode 100644
index 00..a23a66c4a8
--- /dev/null
+++ b/drivers/cache/cache-l2x0.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+#include
+#include
+#include
+
+#include
+#include
+
+static void l2c310_of_parse(struct udevice *dev)
+{
+ u32 tag[3] = { 0, 0, 0 };
+ u32 saved_reg, prefetch;
+ struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+ /* Disable the L2 Cache */
+ clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+ saved_reg = readl(>pl310_aux_ctrl);
+ if (!dev_read_u32(dev, "prefetch-data", )) {
+ if (prefetch)
+ saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+ else
+ saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+ }
+
+ if (!dev_read_u32(dev, "prefetch-instr", )) {
+ if (prefetch)
+ saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+ else
+ saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+ }
+
+ saved_reg |= dev_read_bool(dev, "arm,shared-override");
+ writel(saved_reg, >pl310_aux_ctrl);
+
+ saved_reg = readl(>pl310_tag_latency_ctrl);
+ if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+ saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+ writel(saved_reg, >pl310_tag_latency_ctrl);
+
+ saved_reg = readl(>pl310_data_latency_ctrl);
+ if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+ saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+ writel(saved_reg, >pl310_data_latency_ctrl);
+
+ /* Enable the L2 cache */
+ setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+ l2c310_of_parse(dev);
+ return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+ { .compatible = "arm,pl310-cache" },
+ {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+ .name = "pl310_cache",
+ .id = UCLASS_CACHE,
+ .of_match = l2x0_ids,
+ .probe = l2x0_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.20.0
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[U-Boot] [PATCHv2 6/6] configs: socfpga: add imply pl310 cache controller
Select the PL310 UCLASS_CACHE driver for SoCFPGA. Reviewed-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f42eccef80..f4c6262bb0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -845,6 +845,7 @@ config ARCH_SOCFPGA imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE imply SPL_SPI_FLASH_SUPPORT imply SPL_SPI_SUPPORT + imply L2X0_CACHE config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" -- 2.20.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv2 1/6] Documentation: dts: Add pl310 cache controller dts documentation
Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")
Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt
Copied from Linux kernel v5.0.
"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."
Signed-off-by: Dinh Nguyen
---
.../devicetree/bindings/arm/l2c2x0.txt| 114 ++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt
b/Documentation/devicetree/bindings/arm/l2c2x0.txt
new file mode 100644
index 00..fbe6cb21f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -0,0 +1,114 @@
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as
PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various
implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+ "arm,pl310-cache"
+ "arm,l220-cache"
+ "arm,l210-cache"
+ "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+ "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+ "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+ "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+ "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+ registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3
cells of
+ read, write and setup latencies. Minimum valid values are 1. Controllers
+ without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells
of
+ read, write and setup latencies. Controllers without setup latency control
+ should use 0. Controllers without separate read and write Tag RAM latency
+ values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges : Starting address and length of window to
+ filter. Addresses in the filter window are directed to the M1 port. Other
+ addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+ I/O coherent mode. Valid only when the arm,pl310-cache compatible
+ string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+ if this is not specified, the line size is assumed to be equal to the
+ cache block size
+- cache-id-part: cache id part number to be used if it is not present
+ on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if
non-zero,
+ disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+ 0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+ controllers with respect to the shareable attribute is to transform "normal
+ memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+ or "write through no write allocate" (for writes).
+ On systems where this may cause DMA buffer corruption, this property must be
+ specified to indicate that such transforms are precluded.
+- arm,parity-enable : enable parity
[U-Boot] [PATCHv2 2/6] ARM: pl310: Add macro's for handling tag and data latency mask
Add the PL310 macros for latency control setup, read and write bits. Reviewed-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index b83978b1cc..f69e9e45f8 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -18,6 +18,9 @@ #define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22) #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) #define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) +#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) +#define L310_LATENCY_CTRL_RD(n)((n) << 4) +#define L310_LATENCY_CTRL_WR(n)((n) << 8) #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) -- 2.20.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv2 0/6] dm: cache: add dm cache driver
Hi, This is V2 of the series to add a UCLASS_CACHE dm driver to handling the configuration of cache settings. Place this new driver under /drivers/cache. In this initial revision, the driver is only configuring what I think are essential cache settings. The more comprehensive cache settings can be done in the OS. Diffs from v1: - Add a DTS bindings document from Linux for the PL310. - Split up the UCLASS_CACHE addition from the driver patches. - Add a sandbox cache driver. - Add a simple test in test/dm/cache.c - Address comments from Simon Glass. - Add Reviewed-by's from Marek Vasut. Dinh Nguyen (6): Documentation: dts: Add pl310 cache controller dts documentation ARM: pl310: Add macro's for handling tag and data latency mask dm: cache: Create a uclass for cache dm: cache: add the pl310 cache controller driver ARM: socfpga: use the pl310 driver to configure the cache configs: socfpga: add imply pl310 cache controller .../devicetree/bindings/arm/l2c2x0.txt| 114 ++ arch/arm/Kconfig | 1 + arch/arm/include/asm/pl310.h | 3 + arch/arm/mach-socfpga/misc.c | 16 +-- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/cache/Kconfig | 25 drivers/cache/Makefile| 4 + drivers/cache/cache-l2x0.c| 75 drivers/cache/cache-uclass.c | 13 ++ drivers/cache/sandbox_cache.c | 34 ++ include/cache.h | 33 + include/dm/uclass-id.h| 1 + test/dm/cache.c | 19 +++ 14 files changed, 328 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt create mode 100644 drivers/cache/Kconfig create mode 100644 drivers/cache/Makefile create mode 100644 drivers/cache/cache-l2x0.c create mode 100644 drivers/cache/cache-uclass.c create mode 100644 drivers/cache/sandbox_cache.c create mode 100644 include/cache.h create mode 100644 test/dm/cache.c -- 2.20.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 05/10] board: altera: Stratix10: Add board_get_usable_ram_top()
On 3/12/19 3:33 PM, Westergreen, Dalon wrote:
> On Tue, 2019-03-12 at 11:46 +0100, Marek Vasut wrote:
>> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
>>> Add board_get_usable_ram_top() function. Limit maximum usable
>>> ram top to 2GB.
>>
>> Why ? There are ARM64 platforms which can access the entire DRAM range
>> just fine, what's the problem ?
>>
>
> The issue is the gap in memory between 2GB and 4GB. There is some trickery
> you can use to gain access to the memory in that range, but in general, you
> dont have access. I believe just setting the banks up in the dts will
> resolve this.
E.g. the R8A779{5..9}* platforms also have gaps in memory and it all
works fine . So unless there's some other specialty, there should be no
problem.
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 05/10] board: altera: Stratix10: Add board_get_usable_ram_top()
On Tue, 2019-03-12 at 11:46 +0100, Marek Vasut wrote:
> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> > Add board_get_usable_ram_top() function. Limit maximum usable
> > ram top to 2GB.
>
> Why ? There are ARM64 platforms which can access the entire DRAM range
> just fine, what's the problem ?
>
The issue is the gap in memory between 2GB and 4GB. There is some trickery
you can use to gain access to the memory in that range, but in general, you
dont have access. I believe just setting the banks up in the dts will
resolve this.
--dalon
> > Signed-off-by: Dalon Westergreen
> > Signed-off-by: Ley Foon Tan
> > ---
> > board/altera/stratix10-socdk/socfpga.c | 12
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/board/altera/stratix10-socdk/socfpga.c
> > b/board/altera/stratix10-socdk/socfpga.c
> > index 043fc543f1..99c10d313c 100644
> > --- a/board/altera/stratix10-socdk/socfpga.c
> > +++ b/board/altera/stratix10-socdk/socfpga.c
> > @@ -5,3 +5,15 @@
> > */
> >
> > #include
> > +#include
> > +#include
> > +
> > +#ifdef CONFIG_ALTERA_SDRAM
> > +ulong board_get_usable_ram_top(ulong total_size)
> > +{
> > + if (sdram_calculate_size() > SZ_2G)
> > + return SZ_2G;
> > + else
> > + return sdram_calculate_size();
> > +}
> > +#endif
> >
>
>
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Re: [U-Boot] [PATCH 04/10] arm: socfpga: Update dram_init_banksize() for Stratix10
On Tue, 2019-03-12 at 11:45 +0100, Marek Vasut wrote:
> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> > Setup bi_dram struct based on returned from setup_memory_banks().
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> > arch/arm/mach-socfpga/board.c | 16 +++-
> > 1 file changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
> > index 7c8c05cc31..a0e9917e47 100644
> > --- a/arch/arm/mach-socfpga/board.c
> > +++ b/arch/arm/mach-socfpga/board.c
> > @@ -12,6 +12,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include
> > #include
> > @@ -48,8 +49,21 @@ int board_init(void)
> >
> > int dram_init_banksize(void)
> > {
> > - fdtdec_setup_memory_banksize();
> > +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) &&
> > defined(CONFIG_ALTERA_SDRAM)
> > + phys_addr_t bank_start[CONFIG_NR_DRAM_BANKS];
> > + phys_size_t bank_size[CONFIG_NR_DRAM_BANKS];
> > + int bank;
> > +
> > + gd->ram_size = sdram_calculate_size();
> > + setup_memory_banks(bank_start, bank_size);
> >
> > + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> > + gd->bd->bi_dram[bank].start = bank_start[bank];
> > + gd->bd->bi_dram[bank].size = bank_size[bank];
> > + }
> > +#else
> > + fdtdec_setup_memory_banksize();
> > +#endif
> > return 0;
> > }
>
> Split this out into separate file if this really needs to be different,
> but can't you somehow use fdtdec_setup_memory_size() on S10 and then
> apply sanity checking instead ?
>
yes, this can be done with fdtdec_setup_memory_size.
--dalon
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Re: [U-Boot] [PATCH v4 1/1] efi_loader: Patch non-runtime code out at ExitBootServices already
On Mon, Mar 11, 2019 at 12:44:24PM +0100, Heinrich Schuchardt wrote: > On 3/11/19 9:03 AM, Ard Biesheuvel wrote: > > On Mon, 11 Mar 2019 at 01:16, Heinrich Schuchardt > > wrote: > >> > >> From: Alexander Graf > >> > >> While discussing something compeltely different, Ard pointed out > >> that it might be legal to omit calling SetVirtualAddressMap altogether. > >> > >> There is even a patch on the Linux Kernel Mailing List that implements > >> such behavior by now: > >> > >> https://patchwork.kernel.org/patch/10782393/ > >> > >> While that sounds great, we currently rely on the SetVirtualAddressMap > >> call to remove all references to code that would not work outside of > >> boot services. > >> > >> So let's patch out those bits already on the call to ExitBootServices, > >> so that we can successfully run even when an OS chooses to omit > >> any call to SetVirtualAddressMap. > >> > >> Reported-by: Ard Biesheuvel > >> Signed-off-by: Alexander Graf > >> > >> OpenBSD is not calling SetVirtualAddressMap on ARM 32 bit. > >> > > > > I take it this means that OpenBSD does not support runtime services at > > all on 32-bit ARM? > > References to runtime services exist, e.g.: > > sys/arch/armv7/stand/efiboot/efiboot.c:666: > EFI_CALL(RS->ResetSystem, EfiResetShutdown, EFI_SUCCESS, 0, NULL); > > But from what I see at first glance it seems to be for the interactive > console before booting the kernel. Runtime services are used on OpenBSD/arm64 to be able to access the rtc on amd seattle machines. Not currently used by the kernel on any other platform (including amd64). > > Best regards > > Heinrich > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 03/10] ddr: altera: s10: Add multiple memory banks support
On Tue, 2019-03-12 at 11:44 +0100, Marek Vasut wrote:
> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> > Setup bank start address and size based on total SDRAM
> > memory size calculated from hardware. Update sdram_size_check()
> > to support multiple banks.
> >
> > Stratix10 supports up to 2 memory banks.
> >
> > Bank 0: Address 0, size 2GB
> > Bank 1: Address 0x1, size 124GB
> >
> > Signed-off-by: Dalon Westergreen
> > Signed-off-by: Ley Foon Tan
>
> Shouldn't Quartus generate some sort of DT which gives you all the DRAM
> layout information ? Then you won't need any of this
> CONFIG_NR_DRAM_BANKS stuff, but you would be able to extract such info
> from DT and apply the sanity check only on DRAM you know exists.
>
Yes, I think this can be much cleaner and the dts should provide the bank
information rather than creating the banks from the determined dram size.
The determined dram size can just be a check to validate the bank configuration
in the dts.
so
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
b/arch/arm/dts/socfpga_stratix10_socdk.dts
index 6e8ddcd9f4..94c71bb0ed 100644
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -36,7 +36,9 @@
memory {
device_type = "memory";
- reg = <0 0 0 0x8000>; /* 2GB */
+ /* 4GB */
+ reg = < 0 0x 0 0x8000
+ 1 0x8000 0 0x8000>;
u-boot,dm-pre-reloc;
};
};
--dalon
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Re: [U-Boot] passing info from SPL to U-Boot
On Tue, Mar 12, 2019 at 02:42:02PM +0100, Wolfgang Denk wrote: > Dear Tom, > > In message <20190312121957.GI4690@bill-the-cat> you wrote: > > > > > Yes, doable ... but the question is more, do we really want to read > > > such infos twice, instead reading them in SPL and passing them from > > > SPL to U-Boot ? > > > > Probably so, yes. Since we're talking about SPL and a "lots of > > features, medium sized SRAM" SoC where we've had to carefully tweak > > configs before to get all desired features within the limits. If you've > > bled into SRAM_SCRATCH_SPACE_ADDR range you may run into other problems > > too. > > I think you misunderstand. > > Heiko is not asking for any new data, We are already using the > struct global_data in SPL. And actually this is also where Simon > added the pointers for the bloblist and the spl_handoff data. > > The question is - why do we actually _need_ this spl_handoff, why > don;t we just make sure the global_data is passed from SPL (to TPL > and from there) to U-oot proper? > > We already have reserved this memory, we already have all needed > information, so why not just passing this on instead of throwing it > away? > > this will not grow data size, and it will not require any additional > code size compared to the spl_handoff stuff, which then would be no > longer needed (if I understnad the code correctly). To answer that, no, I don't suppose there's a problem with auditing the code to make sure that we can pass in gd, rather than U-Boot proper assuming it's the first thing to touch gd, if configured. But that to me is a different ball of wax. On this SoC, if you're at the point where you're trampling over the defined scratch space that is used for other things that need scratch space, you may have other problems too. I would swear the EEPROM reading stuff makes use of that but I suspect your platform doesn't bother with that path at all. The other thing that may bite you is the stuff around hw_data. -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] passing info from SPL to U-Boot
Dear Tom, In message <20190312121957.GI4690@bill-the-cat> you wrote: > > > Yes, doable ... but the question is more, do we really want to read > > such infos twice, instead reading them in SPL and passing them from > > SPL to U-Boot ? > > Probably so, yes. Since we're talking about SPL and a "lots of > features, medium sized SRAM" SoC where we've had to carefully tweak > configs before to get all desired features within the limits. If you've > bled into SRAM_SCRATCH_SPACE_ADDR range you may run into other problems > too. I think you misunderstand. Heiko is not asking for any new data, We are already using the struct global_data in SPL. And actually this is also where Simon added the pointers for the bloblist and the spl_handoff data. The question is - why do we actually _need_ this spl_handoff, why don;t we just make sure the global_data is passed from SPL (to TPL and from there) to U-oot proper? We already have reserved this memory, we already have all needed information, so why not just passing this on instead of throwing it away? this will not grow data size, and it will not require any additional code size compared to the spl_handoff stuff, which then would be no longer needed (if I understnad the code correctly). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "...one of the main causes of the fall of the Roman Empire was that, lacking zero, they had no way to indicate successful termination of their C programs." - Robert Firth ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V3 1/2] davinci: da850evm/omapl138-lcdk: Move BSS to SDRAM because SRAM is full
On Mon, Feb 25, 2019 at 9:54 PM Adam Ford wrote:
>
> In order to fully support SPL_OF_CONTROL, we need BSS to be a bit
> larger. This patch relocates BSS to SDRAM instead of SRAM which
> is similar to how ARMv7 boards (like OMAP2+) do it.
>
> This means two new variables are required:
> CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE
> CONFIG_SPL_BSS_MAX_SIZE is set to 0x108 which is 1 byte
> before the location where U-Boot will load.
>
> Signed-off-by: Adam Ford
> ---
> V2: No Change
> V3: Fix omapl138-lcdk so it builds.
>
Tom,
Is there any change to pick up V3 before the next release? Enabling
the DT support is my solution to some of the SPI churn and updates
which sort of expect DT support now. Since the DA850-evm boots from
SPI flash, I'd rather fix the issues with DT support than trying to
prolong the platdata format.
adam
> diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
> b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
> index 7b5fab7756..8f04911306 100644
> --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
> +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
> @@ -10,6 +10,9 @@
> MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
> LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
>
> +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
> +LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
> +
> OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> OUTPUT_ARCH(arm)
> ENTRY(_start)
> @@ -42,6 +45,15 @@ SECTIONS
> __rel_dyn_end = .;
> } >.sram
>
> + __image_copy_end = .;
> +
> + .end :
> + {
> + *(.__end)
> + }
> +
> + _image_binary_end = .;
> +
> .bss :
> {
> . = ALIGN(4);
> @@ -49,12 +61,5 @@ SECTIONS
> *(.bss*)
> . = ALIGN(4);
> __bss_end = .;
> - } >.sram
> -
> - __image_copy_end = .;
> -
> - .end :
> - {
> - *(.__end)
> - }
> + } >.sdram
> }
> diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
> index 14a3046f19..bb549e363a 100644
> --- a/include/configs/da850evm.h
> +++ b/include/configs/da850evm.h
> @@ -48,7 +48,8 @@
> #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
> #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
> #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
> -
> +#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x108
> /* memtest start addr */
> #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x200)
>
> diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
> index 2002444e42..e592df1aea 100644
> --- a/include/configs/omapl138_lcdk.h
> +++ b/include/configs/omapl138_lcdk.h
> @@ -43,6 +43,9 @@
> #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
> #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
>
> +#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x108
> +
> /* memtest start addr */
> #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x200)
>
> --
> 2.17.1
>
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[U-Boot] [PATCH v2 09/11] fdtdec: test: Use compound statement macros
From: Thierry Reding
This eliminates the need for intermediate helper functions and allow the
macros to return a value so that it can be used subsequently.
Signed-off-by: Thierry Reding
---
Changes in v2:
- new patch
lib/fdtdec_test.c | 64 ---
1 file changed, 22 insertions(+), 42 deletions(-)
diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c
index 065fed278cf3..928950918413 100644
--- a/lib/fdtdec_test.c
+++ b/lib/fdtdec_test.c
@@ -15,48 +15,28 @@
/* The size of our test fdt blob */
#define FDT_SIZE (16 * 1024)
-/**
- * Check if an operation failed, and if so, print an error
- *
- * @param oper_nameName of operation
- * @param err Error code to check
- *
- * @return 0 if ok, -1 if there was an error
- */
-static int fdt_checkerr(const char *oper_name, int err)
-{
- if (err) {
- printf("%s: %s: %s\n", __func__, oper_name, fdt_strerror(err));
- return -1;
- }
-
- return 0;
-}
-
-/**
- * Check the result of an operation and if incorrect, print an error
- *
- * @param oper_nameName of operation
- * @param expected Expected value
- * @param valueActual value
- *
- * @return 0 if ok, -1 if there was an error
- */
-static int checkval(const char *oper_name, int expected, int value)
-{
- if (expected != value) {
- printf("%s: %s: expected %d, but returned %d\n", __func__,
- oper_name, expected, value);
- return -1;
- }
-
- return 0;
-}
+#define CHECK(op) ({ \
+ int err = op; \
+ if (err < 0) { \
+ printf("%s: %s: %s\n", __func__, #op, \
+ fdt_strerror(err)); \
+ return err; \
+ } \
+ \
+ err;\
+ })
+
+#define CHECKVAL(op, expected) ({ \
+ int err = op; \
+ if (err != expected) { \
+ printf("%s: %s: expected %d, but returned %d\n",\
+ __func__, #op, expected, err); \
+ return err; \
+ } \
+ \
+ err;\
+ })
-#define CHECK(op) if (fdt_checkerr(#op, op)) return -1
-#define CHECKVAL(op, expected) \
- if (checkval(#op, expected, op)) \
- return -1
#define CHECKOK(op)CHECKVAL(op, 0)
/* maximum number of nodes / aliases to generate */
@@ -138,7 +118,7 @@ static int run_test(const char *aliases, const char *nodes,
const char *expect)
CHECKVAL(make_fdt(blob, FDT_SIZE, aliases, nodes), 0);
CHECKVAL(fdtdec_find_aliases_for_id(blob, "i2c",
COMPAT_UNKNOWN,
- list, ARRAY_SIZE(list)), strlen(expect));
+ list, ARRAY_SIZE(list)), (int)strlen(expect));
/* Check we got the right ones */
for (i = 0, s = expect; *s; s++, i++) {
--
2.20.1
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[U-Boot] [PATCH v2 10/11] fdtdec: test: Add carveout tests
From: Thierry Reding
Implement carveout tests for 32-bit and 64-bit builds.
Signed-off-by: Thierry Reding
---
Changes in v2:
- new patch
lib/fdtdec_test.c | 152 ++
1 file changed, 152 insertions(+)
diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c
index 928950918413..f6defe16c5a6 100644
--- a/lib/fdtdec_test.c
+++ b/lib/fdtdec_test.c
@@ -141,6 +141,156 @@ static int run_test(const char *aliases, const char
*nodes, const char *expect)
return 0;
}
+static int make_fdt_carveout_device(void *fdt, uint32_t na, uint32_t ns)
+{
+ const char *basename = "/display";
+ struct fdt_memory carveout = {
+#ifdef CONFIG_PHYS_64BIT
+ .start = 0x18000,
+ .end = 0x18fff,
+#else
+ .start = 0x8000,
+ .end = 0x8fff,
+#endif
+ };
+ fdt32_t cells[4], *ptr = cells;
+ uint32_t upper, lower;
+ char name[32];
+ int offset;
+
+ /* store one or two address cells */
+ lower = fdt_addr_unpack(carveout.start, );
+
+ if (na > 1 && upper > 0)
+ snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
+lower);
+ else
+ snprintf(name, sizeof(name), "%s@%x", basename, lower);
+
+ if (na > 1)
+ *ptr++ = cpu_to_fdt32(upper);
+
+ *ptr++ = cpu_to_fdt32(lower);
+
+ /* store one or two size cells */
+ lower = fdt_size_unpack(carveout.end - carveout.start + 1, );
+
+ if (ns > 1)
+ *ptr++ = cpu_to_fdt32(upper);
+
+ *ptr++ = cpu_to_fdt32(lower);
+
+ offset = CHECK(fdt_add_subnode(fdt, 0, name + 1));
+ CHECK(fdt_setprop(fdt, offset, "reg", cells, (na + ns) *
sizeof(*cells)));
+
+ return fdtdec_set_carveout(fdt, name, "memory-region", 0,
+ "framebuffer", );
+}
+
+static int check_fdt_carveout(void *fdt, uint32_t address_cells,
+ uint32_t size_cells)
+{
+#ifdef CONFIG_PHYS_64BIT
+ const char *name = "/display@1,8000";
+ const struct fdt_memory expected = {
+ .start = 0x18000,
+ .end = 0x18fff,
+ };
+#else
+ const char *name = "/display@8000";
+ const struct fdt_memory expected = {
+ .start = 0x8000,
+ .end = 0x8fff,
+ };
+#endif
+ struct fdt_memory carveout;
+
+ printf("carveout: %pap-%pap na=%u ns=%u: ", ,
+ , address_cells, size_cells);
+
+ CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, ));
+
+ if ((carveout.start != expected.start) ||
+ (carveout.end != expected.end)) {
+ printf("carveout: %pap-%pap, expected %pap-%pap\n",
+ , ,
+ , );
+ return 1;
+ }
+
+ printf("pass\n");
+ return 0;
+}
+
+static int make_fdt_carveout(void *fdt, int size, uint32_t address_cells,
+uint32_t size_cells)
+{
+ fdt32_t na = cpu_to_fdt32(address_cells);
+ fdt32_t ns = cpu_to_fdt32(size_cells);
+#if defined(DEBUG) && defined(CONFIG_SANDBOX)
+ char filename[512];
+ int fd;
+#endif
+ int err;
+
+ CHECK(fdt_create(fdt, size));
+ CHECK(fdt_finish_reservemap(fdt));
+ CHECK(fdt_begin_node(fdt, ""));
+ CHECK(fdt_property(fdt, "#address-cells", , sizeof(na)));
+ CHECK(fdt_property(fdt, "#size-cells", , sizeof(ns)));
+ CHECK(fdt_end_node(fdt));
+ CHECK(fdt_finish(fdt));
+ CHECK(fdt_pack(fdt));
+
+ CHECK(fdt_open_into(fdt, fdt, FDT_SIZE));
+
+ err = make_fdt_carveout_device(fdt, address_cells, size_cells);
+
+#if defined(DEBUG) && defined(CONFIG_SANDBOX)
+ snprintf(filename, sizeof(filename), "/tmp/fdtdec-carveout-%u-%u.dtb",
+address_cells, size_cells);
+
+ fd = os_open(filename, OS_O_CREAT | OS_O_WRONLY);
+ if (fd < 0) {
+ printf("could not open .dtb file to write\n");
+ goto out;
+ }
+
+ os_write(fd, fdt, size);
+ os_close(fd);
+
+out:
+#endif
+ return err;
+}
+
+static int check_carveout(void)
+{
+ void *fdt;
+
+ fdt = malloc(FDT_SIZE);
+ if (!fdt) {
+ printf("%s: out of memory\n", __func__);
+ return 1;
+ }
+
+#ifndef CONFIG_PHYS_64BIT
+ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 1, 1), 0);
+ CHECKOK(check_fdt_carveout(fdt, 1, 1));
+ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 1, 2), 0);
+ CHECKOK(check_fdt_carveout(fdt, 1, 2));
+#else
+ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 1, 1), -FDT_ERR_BADVALUE);
+ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 1, 2), -FDT_ERR_BADVALUE);
+#endif
+ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 2, 1), 0);
+ CHECKOK(check_fdt_carveout(fdt, 2, 1));
+ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 2, 2),
[U-Boot] [PATCH v2 06/11] fdtdec: Implement carveout support functions
From: Thierry Reding
The fdtdec_get_carveout() and fdtdec_set_carveout() function can be used
to read a carveout from a given node or add a carveout to a given node
using the standard device tree bindings (involving reserved-memory nodes
and the memory-region property).
Reviewed-by: Simon Glass
Signed-off-by: Thierry Reding
---
Changes in v2:
- use debug() instead of printf() to save code size
- fix carveout size computations, was off by one
- use fdtdec_get_addr_size_auto_noparent()
include/fdtdec.h | 39 ++
lib/fdtdec.c | 87
2 files changed, 126 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 5c23a9e5f104..14fff6806df2 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -1021,6 +1021,45 @@ int fdtdec_add_reserved_memory(void *blob, const char
*basename,
const struct fdt_memory *carveout,
uint32_t *phandlep);
+/**
+ * fdtdec_get_carveout() - reads a carveout from an FDT
+ *
+ * Reads information about a carveout region from an FDT. The carveout is a
+ * referenced by its phandle that is read from a given property in a given
+ * node.
+ *
+ * @param blob FDT blob
+ * @param node name of a node
+ * @param name name of the property in the given node that contains
+ * the phandle for the carveout
+ * @param indexindex of the phandle for which to read the
carveout
+ * @param carveout return location for the carveout information
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_get_carveout(const void *blob, const char *node, const char *name,
+ unsigned int index, struct fdt_memory *carveout);
+
+/**
+ * fdtdec_set_carveout() - sets a carveout region for a given node
+ *
+ * Sets a carveout region for a given node. If a reserved-memory node already
+ * exists for the carveout, the phandle for that node will be reused. If no
+ * such node exists, a new one will be created and a phandle to it stored in
+ * a specified property of the given node.
+ *
+ * @param blob FDT blob
+ * @param node name of the node to add the carveout to
+ * @param prop_namename of the property in which to store the phandle of
+ * the carveout
+ * @param indexindex of the phandle to store
+ * @param name base name of the reserved-memory node to create
+ * @param carveout information about the carveout to add
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
+ unsigned int index, const char *name,
+ const struct fdt_memory *carveout);
+
/**
* Set up the device tree ready for use
*/
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index bef331df9a08..8ab41682104e 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1409,6 +1409,93 @@ int fdtdec_add_reserved_memory(void *blob, const char
*basename,
return 0;
}
+int fdtdec_get_carveout(const void *blob, const char *node, const char *name,
+ unsigned int index, struct fdt_memory *carveout)
+{
+ const fdt32_t *prop;
+ uint32_t phandle;
+ int offset, len;
+ fdt_size_t size;
+
+ offset = fdt_path_offset(blob, node);
+ if (offset < 0)
+ return offset;
+
+ prop = fdt_getprop(blob, offset, name, );
+ if (!prop) {
+ debug("failed to get %s for %s\n", name, node);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ if ((len % sizeof(phandle)) != 0) {
+ debug("invalid phandle property\n");
+ return -FDT_ERR_BADPHANDLE;
+ }
+
+ if (len < (sizeof(phandle) * (index + 1))) {
+ debug("invalid phandle index\n");
+ return -FDT_ERR_BADPHANDLE;
+ }
+
+ phandle = fdt32_to_cpu(prop[index]);
+
+ offset = fdt_node_offset_by_phandle(blob, phandle);
+ if (offset < 0) {
+ debug("failed to find node for phandle %u\n", phandle);
+ return offset;
+ }
+
+ carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset,
+"reg", 0, ,
+true);
+ if (carveout->start == FDT_ADDR_T_NONE) {
+ debug("failed to read address/size from \"reg\" property\n");
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ carveout->end = carveout->start + size - 1;
+
+ return 0;
+}
+
+int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
+ unsigned int index, const char *name,
+ const struct fdt_memory *carveout)
+{
+ uint32_t phandle;
+ int err, offset;
+ fdt32_t value;
+
+ /*
[U-Boot] [PATCH v2 11/11] sandbox: Enable fdtdec tests
From: Thierry Reding Enable fdtdec tests on sandbox configurations so that they can be run to validate the fdtdec implementation. Signed-off-by: Thierry Reding --- Changes in v2: - new patch configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index da4bdced3105..c04ecd915ae7 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -194,6 +194,7 @@ CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y CONFIG_ERRNO_STR=y +CONFIG_TEST_FDTDEC=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 193e41896cb7..bb508a8d02e2 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -215,6 +215,7 @@ CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y CONFIG_ERRNO_STR=y +CONFIG_TEST_FDTDEC=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 08/11] fdtdec: test: Fix build warning
From: Thierry Reding
Hide the declaration of the "fd" variable When not building a DEBUG
configuration, to avoid the variable being unused.
Signed-off-by: Thierry Reding
---
Changes in v2:
- new patch
lib/fdtdec_test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c
index a82e27de942f..065fed278cf3 100644
--- a/lib/fdtdec_test.c
+++ b/lib/fdtdec_test.c
@@ -79,7 +79,9 @@ static int make_fdt(void *fdt, int size, const char *aliases,
{
char name[20], value[20];
const char *s;
+#if defined(DEBUG) && defined(CONFIG_SANDBOX)
int fd;
+#endif
CHECK(fdt_create(fdt, size));
CHECK(fdt_finish_reservemap(fdt));
--
2.20.1
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[U-Boot] [PATCH v2 07/11] fdtdec: Add Kconfig symbol for tests
From: Thierry Reding Runtime tests are provided as a test_fdtdec command implementation. Add a Kconfig symbol that allows this command to be built so that the tests can be used. Signed-off-by: Thierry Reding --- Changes in v2: - new patch lib/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/lib/Kconfig b/lib/Kconfig index 366d164cd760..b1fccf7e8dff 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -423,4 +423,8 @@ source lib/efi/Kconfig source lib/efi_loader/Kconfig source lib/optee/Kconfig +config TEST_FDTDEC + bool "enable fdtdec test" + depends on OF_LIBFDT + endmenu -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 05/11] fdtdec: Implement fdtdec_add_reserved_memory()
From: Thierry Reding
This function can be used to add subnodes in the /reserved-memory node.
Reviewed-by: Simon Glass
Signed-off-by: Thierry Reding
---
Changes in v2:
- split fdt_{addr,size}_unpack() helpers into separate patch
- use name@x,y notation only if the upper cell is > 0
- use debug() instead of printf() to save code size
- properly compute number of cells in reg property
- fix carveout size computations, was off by one
- use #size-cells where appropriate
include/fdtdec.h | 17 ++
lib/fdtdec.c | 131 +++
2 files changed, 148 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index eb076fc24bc9..5c23a9e5f104 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -1004,6 +1004,23 @@ int fdtdec_generate_phandle(const void *blob, uint32_t
*phandle);
*/
int fdtdec_set_phandle(void *blob, int node, uint32_t phandle);
+/**
+ * fdtdec_add_reserved_memory() - add or find a reserved-memory node
+ *
+ * If a reserved-memory node already exists for the given carveout, a phandle
+ * for that node will be returned. Otherwise a new node will be created and a
+ * phandle corresponding to it will be returned.
+ *
+ * @param blob FDT blob
+ * @param basename base name of the node to create
+ * @param carveout information about the carveout region
+ * @param phandlep return location for the phandle of the carveout region
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_add_reserved_memory(void *blob, const char *basename,
+ const struct fdt_memory *carveout,
+ uint32_t *phandlep);
+
/**
* Set up the device tree ready for use
*/
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 04d242cdf38e..bef331df9a08 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1278,6 +1278,137 @@ int fdtdec_set_phandle(void *blob, int node, uint32_t
phandle)
return fdt_setprop(blob, node, "phandle", , sizeof(value));
}
+static int fdtdec_init_reserved_memory(void *blob)
+{
+ int na, ns, node, err;
+ fdt32_t value;
+
+ /* inherit #address-cells and #size-cells from the root node */
+ na = fdt_address_cells(blob, 0);
+ ns = fdt_size_cells(blob, 0);
+
+ node = fdt_add_subnode(blob, 0, "reserved-memory");
+ if (node < 0)
+ return node;
+
+ err = fdt_setprop(blob, node, "ranges", NULL, 0);
+ if (err < 0)
+ return err;
+
+ value = cpu_to_fdt32(ns);
+
+ err = fdt_setprop(blob, node, "#size-cells", , sizeof(value));
+ if (err < 0)
+ return err;
+
+ value = cpu_to_fdt32(na);
+
+ err = fdt_setprop(blob, node, "#address-cells", , sizeof(value));
+ if (err < 0)
+ return err;
+
+ return node;
+}
+
+int fdtdec_add_reserved_memory(void *blob, const char *basename,
+ const struct fdt_memory *carveout,
+ uint32_t *phandlep)
+{
+ fdt32_t cells[4] = {}, *ptr = cells;
+ uint32_t upper, lower, phandle;
+ int parent, node, na, ns, err;
+ char name[64];
+
+ /* create an empty /reserved-memory node if one doesn't exist */
+ parent = fdt_path_offset(blob, "/reserved-memory");
+ if (parent < 0) {
+ parent = fdtdec_init_reserved_memory(blob);
+ if (parent < 0)
+ return parent;
+ }
+
+ /* only 1 or 2 #address-cells and #size-cells are supported */
+ na = fdt_address_cells(blob, parent);
+ if (na < 1 || na > 2)
+ return -FDT_ERR_BADNCELLS;
+
+ ns = fdt_size_cells(blob, parent);
+ if (ns < 1 || ns > 2)
+ return -FDT_ERR_BADNCELLS;
+
+ /* find a matching node and return the phandle to that */
+ fdt_for_each_subnode(node, blob, parent) {
+ const char *name = fdt_get_name(blob, node, NULL);
+ phys_addr_t addr, size;
+
+ addr = fdtdec_get_addr_size(blob, node, "reg", );
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("failed to read address/size for %s\n", name);
+ continue;
+ }
+
+ if (addr == carveout->start && (addr + size) == carveout->end) {
+ *phandlep = fdt_get_phandle(blob, node);
+ return 0;
+ }
+ }
+
+ /*
+* Unpack the start address and generate the name of the new node
+* base on the basename and the unit-address.
+*/
+ lower = fdt_addr_unpack(carveout->start, );
+
+ if (na > 1 && upper > 0)
+ snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
+lower);
+ else {
+ if (upper > 0) {
+ debug("address %08x:%08x exceeds addressable space\n",
+ upper, lower);
+
[U-Boot] [PATCH v2 04/11] fdtdec: Implement fdtdec_set_phandle()
From: Thierry Reding
This function can be used to set a phandle for a given node.
Signed-off-by: Thierry Reding
---
Changes in v2:
- don't emit deprecated linux,phandle property
include/fdtdec.h | 11 +++
lib/fdtdec.c | 7 +++
2 files changed, 18 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index b593c562584d..eb076fc24bc9 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -993,6 +993,17 @@ int fdtdec_setup_memory_banksize(void);
*/
int fdtdec_generate_phandle(const void *blob, uint32_t *phandle);
+/**
+ * fdtdec_set_phandle() - sets the phandle of a given node
+ *
+ * @param blob FDT blob
+ * @param node offset in the FDT blob of the node whose phandle is to
+ * be set
+ * @param phandle phandle to set for the given node
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_set_phandle(void *blob, int node, uint32_t phandle);
+
/**
* Set up the device tree ready for use
*/
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index d384c84feb33..04d242cdf38e 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1271,6 +1271,13 @@ int fdtdec_generate_phandle(const void *blob, uint32_t
*phandle)
return 0;
}
+int fdtdec_set_phandle(void *blob, int node, uint32_t phandle)
+{
+ fdt32_t value = cpu_to_fdt32(phandle);
+
+ return fdt_setprop(blob, node, "phandle", , sizeof(value));
+}
+
int fdtdec_setup(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
--
2.20.1
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[U-Boot] [PATCH v2 03/11] fdtdec: Implement fdtdec_generate_phandle()
From: Thierry Reding
This function generates a new, unused phandle by looking up the highest
phandle value stored in a device tree and adding one.
Signed-off-by: Thierry Reding
---
Changes in v2:
- rename to fdtdec_generate_phandle()
include/fdtdec.h | 12
lib/fdtdec.c | 28
2 files changed, 40 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a0ba57c6318b..b593c562584d 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -981,6 +981,18 @@ int fdtdec_setup_mem_size_base(void);
*/
int fdtdec_setup_memory_banksize(void);
+/**
+ * fdtdec_generate_phandle() - return a new, unused phandle for an FDT blob
+ *
+ * Returns a phandle that can be used to refer to a new device tree node. It
+ * is one higher than the currently highest phandle in the given FDT blob.
+ *
+ * @param blob FDT blob
+ * @param maxp return location for the new phandle
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_generate_phandle(const void *blob, uint32_t *phandle);
+
/**
* Set up the device tree ready for use
*/
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 09a7e133a539..d384c84feb33 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1243,6 +1243,34 @@ __weak void *board_fdt_blob_setup(void)
}
#endif
+int fdtdec_generate_phandle(const void *blob, uint32_t *phandle)
+{
+ uint32_t max = 0;
+ int offset = -1;
+
+ while (true) {
+ uint32_t value;
+
+ offset = fdt_next_node(blob, offset, NULL);
+ if (offset < 0) {
+ if (offset == -FDT_ERR_NOTFOUND)
+ break;
+
+ return offset;
+ }
+
+ value = fdt_get_phandle(blob, offset);
+
+ if (value > max)
+ max = value;
+ }
+
+ if (phandle)
+ *phandle = max + 1;
+
+ return 0;
+}
+
int fdtdec_setup(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
--
2.20.1
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[U-Boot] [PATCH v2 02/11] fdtdec: Add fdt_{addr, size}_unpack() helpers
From: Thierry Reding
These helpers can be used to unpack variables of type fdt_addr_t and
fdt_size_t into a pair of 32-bit variables. This is useful in cases
where such variables need to be written to properties (such as "reg")
of a device tree node where they need to be split into cells.
Signed-off-by: Thierry Reding
---
Changes in v2:
- new patch
include/fdtdec.h | 25 +
1 file changed, 25 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a965c33157c9..a0ba57c6318b 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -23,6 +23,31 @@
*/
typedef phys_addr_t fdt_addr_t;
typedef phys_size_t fdt_size_t;
+
+static inline fdt32_t fdt_addr_unpack(fdt_addr_t addr, fdt32_t *upper)
+{
+ if (upper)
+#ifdef CONFIG_PHYS_64BIT
+ *upper = addr >> 32;
+#else
+ *upper = 0;
+#endif
+
+ return addr;
+}
+
+static inline fdt32_t fdt_size_unpack(fdt_size_t size, fdt32_t *upper)
+{
+ if (upper)
+#ifdef CONFIG_PHYS_64BIT
+ *upper = size >> 32;
+#else
+ *upper = 0;
+#endif
+
+ return size;
+}
+
#ifdef CONFIG_PHYS_64BIT
#define FDT_ADDR_T_NONE (-1U)
#define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
--
2.20.1
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[U-Boot] [PATCH v2 01/11] fdtdec: Add cpu_to_fdt_{addr, size}() macros
From: Thierry Reding These macros are useful for converting the endianness of variables of type fdt_addr_t and fdt_size_t. Reviewed-by: Simon Glass Signed-off-by: Thierry Reding --- Changes in v2: - add Reviewed-by from Simon include/fdtdec.h | 4 1 file changed, 4 insertions(+) diff --git a/include/fdtdec.h b/include/fdtdec.h index b7e35cd87c55..a965c33157c9 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -27,11 +27,15 @@ typedef phys_size_t fdt_size_t; #define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be64_to_cpu(reg) #define fdt_size_to_cpu(reg) be64_to_cpu(reg) +#define cpu_to_fdt_addr(reg) cpu_to_be64(reg) +#define cpu_to_fdt_size(reg) cpu_to_be64(reg) typedef fdt64_t fdt_val_t; #else #define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be32_to_cpu(reg) #define fdt_size_to_cpu(reg) be32_to_cpu(reg) +#define cpu_to_fdt_addr(reg) cpu_to_be32(reg) +#define cpu_to_fdt_size(reg) cpu_to_be32(reg) typedef fdt32_t fdt_val_t; #endif -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/1] avb: add support for named persistent values
Reviewed-by: Sam Protsenko
On Thu, Feb 14, 2019 at 2:37 PM Igor Opaniuk wrote:
>
> AVB 2.0 spec. revision 1.1 introduces support for named persistent values
> that must be tamper evident and allows AVB to store arbitrary key-value
> pairs [1].
>
> Introduce implementation of two additional AVB operations
> read_persistent_value()/write_persistent_value() for retrieving/storing
> named persistent values.
>
> Correspondent pull request in the OP-TEE OS project repo [2].
>
> [1]:
> https://android.googlesource.com/platform/external/avb/+/android-9.0.0_r22
> [2]: https://github.com/OP-TEE/optee_os/pull/2699
>
> Reviewed-by: Simon Glass
> Signed-off-by: Igor Opaniuk
> ---
>
> v5:
> - fix failing test on sandbox_flattree target
> - keep all defined globally variables in a driver-private data struct, which
> permits to probe multiple tee sandbox devices
>
> v4:
> - extend tee sandbox tee driver to support persistent values
> - fix/re-test avb_persistent test on sandbox configuration
>
> v3:
> - fix possible mem lick in avb_read_persistent/avb_write_persistent
> - add additional sanity checks
> - cover avb read_pvalue/write_pvalue commands with python tests
>
> v2:
> - fix output format for avb read_pvalue/write_pvalue commands
> - fix issue with named value buffer size
>
> cmd/avb.c | 78
> common/avb_verify.c| 125
> +
> drivers/tee/sandbox.c | 121 ---
> include/sandboxtee.h | 15 --
> include/tee.h | 2 +
> include/tee/optee_ta_avb.h | 16 ++
> test/py/tests/test_avb.py | 16 ++
> 7 files changed, 351 insertions(+), 22 deletions(-)
>
> diff --git a/cmd/avb.c b/cmd/avb.c
> index ff00be4..c5af4a2 100644
> --- a/cmd/avb.c
> +++ b/cmd/avb.c
> @@ -340,6 +340,76 @@ int do_avb_is_unlocked(cmd_tbl_t *cmdtp, int flag,
> return CMD_RET_FAILURE;
> }
>
> +int do_avb_read_pvalue(cmd_tbl_t *cmdtp, int flag, int argc,
> + char * const argv[])
> +{
> + const char *name;
> + size_t bytes;
> + size_t bytes_read;
> + void *buffer;
> + char *endp;
> +
> + if (!avb_ops) {
> + printf("AVB 2.0 is not initialized, run 'avb init' first\n");
> + return CMD_RET_FAILURE;
> + }
> +
> + if (argc != 3)
> + return CMD_RET_USAGE;
> +
> + name = argv[1];
> + bytes = simple_strtoul(argv[2], , 10);
> + if (*endp && *endp != '\n')
> + return CMD_RET_USAGE;
> +
> + buffer = malloc(bytes);
> + if (!buffer)
> + return CMD_RET_FAILURE;
> +
> + if (avb_ops->read_persistent_value(avb_ops, name, bytes, buffer,
> + _read) == AVB_IO_RESULT_OK) {
> + printf("Read %ld bytes, value = %s\n", bytes_read,
> + (char *)buffer);
> + free(buffer);
> + return CMD_RET_SUCCESS;
> + }
> +
> + printf("Failed to read persistent value\n");
> +
> + free(buffer);
> +
> + return CMD_RET_FAILURE;
> +}
> +
> +int do_avb_write_pvalue(cmd_tbl_t *cmdtp, int flag, int argc,
> + char * const argv[])
> +{
> + const char *name;
> + const char *value;
> +
> + if (!avb_ops) {
> + printf("AVB 2.0 is not initialized, run 'avb init' first\n");
> + return CMD_RET_FAILURE;
> + }
> +
> + if (argc != 3)
> + return CMD_RET_USAGE;
> +
> + name = argv[1];
> + value = argv[2];
> +
> + if (avb_ops->write_persistent_value(avb_ops, name, strlen(value) + 1,
> + (const uint8_t *)value) ==
> + AVB_IO_RESULT_OK) {
> + printf("Wrote %ld bytes\n", strlen(value) + 1);
> + return CMD_RET_SUCCESS;
> + }
> +
> + printf("Failed to write persistent value\n");
> +
> + return CMD_RET_FAILURE;
> +}
> +
> static cmd_tbl_t cmd_avb[] = {
> U_BOOT_CMD_MKENT(init, 2, 0, do_avb_init, "", ""),
> U_BOOT_CMD_MKENT(read_rb, 2, 0, do_avb_read_rb, "", ""),
> @@ -350,6 +420,10 @@ static cmd_tbl_t cmd_avb[] = {
> U_BOOT_CMD_MKENT(read_part_hex, 4, 0, do_avb_read_part_hex, "", ""),
> U_BOOT_CMD_MKENT(write_part, 5, 0, do_avb_write_part, "", ""),
> U_BOOT_CMD_MKENT(verify, 1, 0, do_avb_verify_part, "", ""),
> +#ifdef CONFIG_OPTEE_TA_AVB
> + U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_avb_read_pvalue, "", ""),
> + U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_avb_write_pvalue, "", ""),
> +#endif
> };
>
> static int do_avb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> @@ -384,6 +458,10 @@ U_BOOT_CMD(
> "partition and print to stdout\n"
> "avb write_part - write bytes
> to\n"
> " by using data from \n"
> +#ifdef CONFIG_OPTEE_TA_AVB
> +
Re: [U-Boot] [PATCH] dm: check OF_LIVE is enabled
Hi Simon, > -Original Message- > From: Simon Glass > Sent: 10 March 2019 21:51 > To: Ibai Erkiaga Elorza > Cc: U-Boot Mailing List ; Patrick Delaunay > ; Andy Shevchenko > ; Bin Meng ; > Patrice Chotard > Subject: Re: [U-Boot][PATCH] dm: check OF_LIVE is enabled > > Hi Ibai, > > On Tue, 26 Feb 2019 at 02:26, Ibai Erkiaga > wrote: > > > > Livetree implemented functions does not have conditional compilation > > so check if CONFIG_IS_ENABLED prior using those functions. > > > > The issue does not report any error in a normal build as the toolchain > > optimize the code. Using -O0 triggers the error so the patch is > > intended to fix issues on a ongoing effor to build U-Boot with -O0. > > > > Signed-off-by: Ibai Erkiaga > > --- > > > > drivers/core/ofnode.c | 60 > > +- > > drivers/serial/serial-uclass.c | 2 +- > > 2 files changed, 31 insertions(+), 31 deletions(-) > > > > This is supposed to work by using of_live_active(), which is called from > ofnode_is_np(). Instead of changing all this code, is it possible to update > of_live_active() somehow? > I've been trying to figure out it but I think there is no way just changing of_live_active as the compiler does not discard branch statements with nested fixed return values. I was able to make it work just changing ofnode_is_np using pre-processor macro to set as false when OF_LIVE is not enabled, but not sure if it the right approach. I will take a deeper look to the entire OF code and maybe suggest a code refactoring. > Regards, > Simon Regards Ibai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] passing info from SPL to U-Boot
On Tue, Mar 12, 2019 at 12:37:20PM +0100, Heiko Schocher wrote: > Hello Tom, > > Am 12.03.2019 um 12:16 schrieb Tom Rini: > >On Tue, Mar 12, 2019 at 09:21:36AM +0100, Heiko Schocher wrote: > >>Hello Simon, Tom, > >> > >>I am just stumbeld on an am437x basd board over the problem to pass > >>the bootmode from SPL to U-Boot. On am437x the bootmode info get > >>overwritten from SPL stack, and I need this info in U-Boot. > >> > >>Hack would be to move SPL stack to another address, but we loose > >>than 0xa000 size for stack ... I do not want to go this way.. > > > >I think you need to fix it being over-written as it sounds like we're > >running over our pre-defined scratch space area and that can lead to > >other problems as well, depending on how much your platform is deviating > >from how the TI ref platforms are written. Thanks! > > Yes, doable ... but the question is more, do we really want to read > such infos twice, instead reading them in SPL and passing them from > SPL to U-Boot ? Probably so, yes. Since we're talking about SPL and a "lots of features, medium sized SRAM" SoC where we've had to carefully tweak configs before to get all desired features within the limits. If you've bled into SRAM_SCRATCH_SPACE_ADDR range you may run into other problems too. -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] passing info from SPL to U-Boot
Hello Tom, Am 12.03.2019 um 12:16 schrieb Tom Rini: On Tue, Mar 12, 2019 at 09:21:36AM +0100, Heiko Schocher wrote: Hello Simon, Tom, I am just stumbeld on an am437x basd board over the problem to pass the bootmode from SPL to U-Boot. On am437x the bootmode info get overwritten from SPL stack, and I need this info in U-Boot. Hack would be to move SPL stack to another address, but we loose than 0xa000 size for stack ... I do not want to go this way.. I think you need to fix it being over-written as it sounds like we're running over our pre-defined scratch space area and that can lead to other problems as well, depending on how much your platform is deviating from how the TI ref platforms are written. Thanks! Yes, doable ... but the question is more, do we really want to read such infos twice, instead reading them in SPL and passing them from SPL to U-Boot ? bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] passing info from SPL to U-Boot
On Tue, Mar 12, 2019 at 09:21:36AM +0100, Heiko Schocher wrote: > Hello Simon, Tom, > > I am just stumbeld on an am437x basd board over the problem to pass > the bootmode from SPL to U-Boot. On am437x the bootmode info get > overwritten from SPL stack, and I need this info in U-Boot. > > Hack would be to move SPL stack to another address, but we loose > than 0xa000 size for stack ... I do not want to go this way.. I think you need to fix it being over-written as it sounds like we're running over our pre-defined scratch space area and that can lead to other problems as well, depending on how much your platform is deviating from how the TI ref platforms are written. Thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 00/10] Update Stratix 10 SDRAM driver
On Tue, Mar 12, 2019 at 9:31 AM Ley Foon Tan wrote: > > This patchset update Stratix 10 SDRAM driver to support: > - Multi-banks memory (Patch [1-8]) > - Stratix 10 support up to 2 memory banks: > Bank 0: Address 0, size 2GB > Bank 1: Address 0x1, size 124GB > - Add warm reset boot checking function, to use in patch [10] (Patch[9]) > - Add ECC memory scrubbing support (Patch [10]) > - Use cache enabled + "DC ZVA" instruction to clear memory to zeros When working on this, would it make sense to move the S10 SDRAM driver to DM, using UCLASS_RAM, like I did for gen5 (see Marek's 'next' branch: http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=commit;h=4796a7d5a7fd965c02cf290edec17acb2c9af766) That might allow us to combine more of the code in mach-socfpga again in the future... Regards, Simon > > Ley Foon Tan (10): > ddr: altera: stratix10: Move SDRAM size check to SDRAM driver > arm: socfpga: Add sdram_s10.h to sdram.h > ddr: altera: s10: Add multiple memory banks support > arm: socfpga: Update dram_init_banksize() for Stratix10 > board: altera: Stratix10: Add board_get_usable_ram_top() > board: altera: Stratix10: Add ft_board_setup() > arm: socfpga: Enable OF_BOARD_SETUP for Stratix 10 > configs: stratix10: Change CONFIG_NR_DRAM_BANKS to 2 > arm: socfpga: stratix10: Add cpu_has_been_warmreset() > ddr: altera: Stratix10: Add ECC memory scrubbing > > arch/arm/mach-socfpga/Kconfig | 1 + > arch/arm/mach-socfpga/board.c | 16 +- > .../include/mach/reset_manager_s10.h | 3 + > arch/arm/mach-socfpga/include/mach/sdram.h| 2 + > .../arm/mach-socfpga/include/mach/sdram_s10.h | 10 + > arch/arm/mach-socfpga/reset_manager_s10.c | 9 + > arch/arm/mach-socfpga/spl_s10.c | 11 -- > board/altera/stratix10-socdk/socfpga.c| 37 > configs/socfpga_stratix10_defconfig | 2 +- > drivers/ddr/altera/sdram_s10.c| 178 ++ > 10 files changed, 256 insertions(+), 13 deletions(-) > > -- > 2.19.0 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 10/10] ddr: altera: Stratix10: Add ECC memory scrubbing
On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> Scrub memory content if ECC is enabled and it is not
> from warm reset boot.
>
> Enable icache and dcache before scrub memory
> and use "DC ZVA" instruction to clear memory
> to zeros. This instruction writes a cache line
> at a time and it can prevent false ECC error
> trigger if write cache line partially.
>
> Signed-off-by: Ley Foon Tan
> ---
> .../arm/mach-socfpga/include/mach/sdram_s10.h | 9 +++
> drivers/ddr/altera/sdram_s10.c| 76 +++
> 2 files changed, 85 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> index 89e355010d..354f80bfce 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> @@ -23,6 +23,7 @@ void setup_memory_banks(phys_addr_t bank_addr[],
> phys_size_t bank_size[]);
> #define ECCCTRL1 0x100
> #define ECCCTRL2 0x104
> #define ERRINTEN 0x110
> +#define ERRINTENS0x114
> #define INTMODE 0x11c
> #define INTSTAT 0x120
> #define AUTOWB_CORRADDR 0x138
> @@ -53,6 +54,10 @@ void setup_memory_banks(phys_addr_t bank_addr[],
> phys_size_t bank_size[]);
> #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
> #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
>
> +#define DDR_HMC_ERRINTEN_INTMASK\
> + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |\
> + DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
> +
> /* NOC DDR scheduler */
> #define DDR_SCH_ID_COREID0
> #define DDR_SCH_ID_REVID 0x4
> @@ -181,4 +186,8 @@ void setup_memory_banks(phys_addr_t bank_addr[],
> phys_size_t bank_size[]);
> #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
> (((x) >> 0) & 0xFF)
>
> +/* Firewall DDR scheduler MPFE */
> +#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
> +#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
> +
> #endif /* _SDRAM_S10_H_ */
> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> index ae4e5ea2fd..2c691d3bee 100644
> --- a/drivers/ddr/altera/sdram_s10.c
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -22,6 +22,8 @@ static const struct socfpga_system_manager *sysmgr_regs =
>
> #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8)
> | (R))
>
> +#define PGTABLE_OFF 0x4000
> +
> /* The followring are the supported configurations */
> u32 ddr_config[] = {
> /* DDR_CONFIG(Address order,Bank,Column,Row) */
> @@ -135,6 +137,71 @@ static int poll_hmc_clock_status(void)
>SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
> }
>
> +static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
> +{
> + phys_size_t i;
> +
> + if (addr % CONFIG_SYS_CACHELINE_SIZE) {
> + printf("DDR: address 0x%lx not cacheline size aligned.\n",
> +(ulong)addr);
Is the cast needed ?
> + hang();
> + }
> +
> + if (size % CONFIG_SYS_CACHELINE_SIZE) {
> + printf("DDR: size 0x%lx not multiple of cacheline size\n",
> +(ulong)size);
> + hang();
> + }
> +
> + /* Use DC ZVA instruction to clear memory to zeros by a cache line */
> + for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
> + asm("dc zva, %0"
> + :
> + : "r"(addr));
Should be asm volatile, so the compiler won't move this around.
Also, you want memory clobber here I think ?
> + addr += CONFIG_SYS_CACHELINE_SIZE;
> + }
> +}
> +
> +static void sdram_init_ecc_bits(phys_addr_t *bank_start, phys_size_t
> *bank_size)
> +{
> + phys_size_t size, size_init;
> + phys_addr_t start_addr;
> + int bank;
> + unsigned int start = get_timer(0);
> +
> + icache_enable();
> +
> + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> + start_addr = bank_start[bank];
> + size = bank_size[bank];
> +
> + if (bank == 0) {
> + /* Initialize small block for page table */
> + memset((void *)start_addr, 0,
> +PGTABLE_SIZE + PGTABLE_OFF);
> + gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
> + gd->arch.tlb_size = PGTABLE_SIZE;
> + start_addr += PGTABLE_SIZE + PGTABLE_OFF;
> + size -= (PGTABLE_OFF + PGTABLE_SIZE);
> + dcache_enable();
If it's only done for bank0, pull this code out of the loop ?
> + }
> +
> + while (size) {
> + size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
> +
Re: [U-Boot] [PATCH 06/10] board: altera: Stratix10: Add ft_board_setup()
On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> Add ft_board_setup() function to setup memory banks before
> boot to Linux.
Shouldn't bootm/booti be doing just that already ?
> Signed-off-by: Ley Foon Tan
> ---
> board/altera/stratix10-socdk/socfpga.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/board/altera/stratix10-socdk/socfpga.c
> b/board/altera/stratix10-socdk/socfpga.c
> index 99c10d313c..ca6e0e9085 100644
> --- a/board/altera/stratix10-socdk/socfpga.c
> +++ b/board/altera/stratix10-socdk/socfpga.c
> @@ -5,6 +5,7 @@
> */
>
> #include
> +#include
> #include
> #include
>
> @@ -17,3 +18,27 @@ ulong board_get_usable_ram_top(ulong total_size)
> return sdram_calculate_size();
> }
> #endif
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> + int ret = 0;
> +#ifdef CONFIG_OF_LIBFDT
> + int bank;
> + int actual_bank = 0;
> + u64 start[CONFIG_NR_DRAM_BANKS];
> + u64 size[CONFIG_NR_DRAM_BANKS];
> +
> + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> + if (bd->bi_dram[bank].size) {
> + start[actual_bank] = bd->bi_dram[bank].start;
> + size[actual_bank++] = bd->bi_dram[bank].size;
> + }
> + }
> +
> + ret = fdt_fixup_memory_banks(blob, start, size, actual_bank);
> +#endif /* CONFIG_OF_LIBFDT */
> +
> + return ret;
> +}
> +#endif
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 05/10] board: altera: Stratix10: Add board_get_usable_ram_top()
On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> Add board_get_usable_ram_top() function. Limit maximum usable
> ram top to 2GB.
Why ? There are ARM64 platforms which can access the entire DRAM range
just fine, what's the problem ?
> Signed-off-by: Dalon Westergreen
> Signed-off-by: Ley Foon Tan
> ---
> board/altera/stratix10-socdk/socfpga.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/board/altera/stratix10-socdk/socfpga.c
> b/board/altera/stratix10-socdk/socfpga.c
> index 043fc543f1..99c10d313c 100644
> --- a/board/altera/stratix10-socdk/socfpga.c
> +++ b/board/altera/stratix10-socdk/socfpga.c
> @@ -5,3 +5,15 @@
> */
>
> #include
> +#include
> +#include
> +
> +#ifdef CONFIG_ALTERA_SDRAM
> +ulong board_get_usable_ram_top(ulong total_size)
> +{
> + if (sdram_calculate_size() > SZ_2G)
> + return SZ_2G;
> + else
> + return sdram_calculate_size();
> +}
> +#endif
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 04/10] arm: socfpga: Update dram_init_banksize() for Stratix10
On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> Setup bi_dram struct based on returned from setup_memory_banks().
>
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/board.c | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
> index 7c8c05cc31..a0e9917e47 100644
> --- a/arch/arm/mach-socfpga/board.c
> +++ b/arch/arm/mach-socfpga/board.c
> @@ -12,6 +12,7 @@
> #include
> #include
> #include
> +#include
>
> #include
> #include
> @@ -48,8 +49,21 @@ int board_init(void)
>
> int dram_init_banksize(void)
> {
> - fdtdec_setup_memory_banksize();
> +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) && defined(CONFIG_ALTERA_SDRAM)
> + phys_addr_t bank_start[CONFIG_NR_DRAM_BANKS];
> + phys_size_t bank_size[CONFIG_NR_DRAM_BANKS];
> + int bank;
> +
> + gd->ram_size = sdram_calculate_size();
> + setup_memory_banks(bank_start, bank_size);
>
> + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> + gd->bd->bi_dram[bank].start = bank_start[bank];
> + gd->bd->bi_dram[bank].size = bank_size[bank];
> + }
> +#else
> + fdtdec_setup_memory_banksize();
> +#endif
> return 0;
> }
Split this out into separate file if this really needs to be different,
but can't you somehow use fdtdec_setup_memory_size() on S10 and then
apply sanity checking instead ?
--
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Marek Vasut
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Re: [U-Boot] [PATCH 01/10] ddr: altera: stratix10: Move SDRAM size check to SDRAM driver
On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> Move SDRAM size check to SDRAM driver. sdram_calculate_size()
> is called in SDRAM initialization already, avoid calling
> twice in size check function.
>
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/spl_s10.c | 11 ---
> drivers/ddr/altera/sdram_s10.c | 15 +++
> 2 files changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> index a3db20a819..a141ffe82a 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -181,17 +181,6 @@ void board_init_f(ulong dummy)
> hang();
> }
>
> - gd->ram_size = sdram_calculate_size();
> - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
> -
> - /* Sanity check ensure correct SDRAM size specified */
> - debug("DDR: Running SDRAM size sanity check\n");
> - if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> - puts("DDR: SDRAM size check failed!\n");
> - hang();
> - }
> - debug("DDR: SDRAM size check passed!\n");
> -
> mbox_init();
>
> #ifdef CONFIG_CADENCE_QSPI
> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> index a48567c109..8895813440 100644
> --- a/drivers/ddr/altera/sdram_s10.c
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void)
>SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
> }
>
> +static void sdram_size_check(void)
> +{
> + /* Sanity check ensure correct SDRAM size specified */
> + debug("DDR: Running SDRAM size sanity check\n");
> + if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> + puts("DDR: SDRAM size check failed!\n");
> + hang();
> + }
> + debug("DDR: SDRAM size check passed!\n");
> +}
> +
> /**
> * sdram_mmr_init_full() - Function to initialize SDRAM MMR
> *
> @@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused)
> else
> gd->ram_size = size;
>
> + printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
Is the type cast needed?
> /* Enable or disable the SDRAM ECC */
> if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
> setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
> @@ -361,6 +374,8 @@ int sdram_mmr_init_full(unsigned int unused)
> DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
> }
>
> + sdram_size_check();
> +
> debug("DDR: HMC init success\n");
> return 0;
> }
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 03/10] ddr: altera: s10: Add multiple memory banks support
On 3/12/19 9:31 AM, Ley Foon Tan wrote: > Setup bank start address and size based on total SDRAM > memory size calculated from hardware. Update sdram_size_check() > to support multiple banks. > > Stratix10 supports up to 2 memory banks. > > Bank 0: Address 0, size 2GB > Bank 1: Address 0x1, size 124GB > > Signed-off-by: Dalon Westergreen > Signed-off-by: Ley Foon Tan Shouldn't Quartus generate some sort of DT which gives you all the DRAM layout information ? Then you won't need any of this CONFIG_NR_DRAM_BANKS stuff, but you would be able to extract such info from DT and apply the sanity check only on DRAM you know exists. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 05/23] apalis_imx6: remove obsolete USB_GADGET_MASS_STORAGE configuration
Reviewed-by: Igor Opaniuk On Fri, 8 Feb 2019 at 19:16, Marcel Ziswiler wrote: > > From: Marcel Ziswiler > > Remove obsolete USB_GADGET_MASS_STORAGE configuration. > > Signed-off-by: Marcel Ziswiler > > --- > > Changes in v2: None > > include/configs/apalis_imx6.h | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h > index a1ba16fc79..785ab3 100644 > --- a/include/configs/apalis_imx6.h > +++ b/include/configs/apalis_imx6.h > @@ -82,8 +82,6 @@ > /* Client */ > #define CONFIG_USBD_HS > > -#define CONFIG_USB_GADGET_MASS_STORAGE > - > /* Framebuffer and LCD */ > #define CONFIG_VIDEO_IPUV3 > #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE > -- > 2.20.1 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 04/23] apalis_imx6: enable fit image, gpt, imx thermal, efi loader support
Hi Marcel, s/Enbale/Enable/g On Fri, 8 Feb 2019 at 19:13, Marcel Ziswiler wrote: > > From: Marcel Ziswiler > > Enbale FIT image, GPT command, i.MX thermal and EFI loader support. > > Signed-off-by: Marcel Ziswiler > > --- > > Changes in v2: None > > configs/apalis_imx6_defconfig | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig > index 098d791a62..b262bb88b9 100644 > --- a/configs/apalis_imx6_defconfig > +++ b/configs/apalis_imx6_defconfig > @@ -11,6 +11,7 @@ CONFIG_SPL=y > CONFIG_CMD_HDMIDETECT=y > CONFIG_DISTRO_DEFAULTS=y > CONFIG_NR_DRAM_BANKS=1 > +CONFIG_FIT=y > CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" > CONFIG_BOOTDELAY=1 > # CONFIG_CONSOLE_MUX is not set > @@ -36,6 +37,7 @@ CONFIG_CMD_MEMTEST=y > CONFIG_SYS_ALT_MEMTEST=y > CONFIG_CMD_DFU=y > CONFIG_CMD_GPIO=y > +CONFIG_CMD_GPT=y > CONFIG_CMD_I2C=y > CONFIG_CMD_MMC=y > CONFIG_CMD_USB=y > @@ -52,6 +54,7 @@ CONFIG_PHYLIB=y > CONFIG_PHY_MICREL=y > CONFIG_PHY_MICREL_KSZ90X1=y > CONFIG_MII=y > +CONFIG_IMX_THERMAL=y > CONFIG_USB=y > CONFIG_USB_KEYBOARD=y > CONFIG_USB_GADGET=y > @@ -65,4 +68,3 @@ CONFIG_VIDEO=y > CONFIG_FAT_WRITE=y > CONFIG_OF_LIBFDT=y > CONFIG_OF_LIBFDT_OVERLAY=y > -# CONFIG_EFI_LOADER is not set > -- > 2.20.1 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/3] sandbox: Use correct phys_{addr, size}_t for PHYS_64BIT=y
From: Thierry Reding If 64-bit physical addresses support is enabled, make sure the sandox defines the correct types for phys_addr_t and phys_size_t. Signed-off-by: Thierry Reding --- arch/sandbox/include/asm/types.h | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h index 7cd56b41474f..c1a5d2af8285 100644 --- a/arch/sandbox/include/asm/types.h +++ b/arch/sandbox/include/asm/types.h @@ -18,21 +18,21 @@ typedef unsigned short umode_t; /* * Number of bits in a C 'long' on this architecture. */ -#ifdef CONFIG_PHYS64 +#ifdef CONFIG_PHYS_64BIT #define BITS_PER_LONG 64 -#else /* CONFIG_PHYS64 */ +#else /* CONFIG_PHYS_64BIT */ #define BITS_PER_LONG 32 -#endif /* CONFIG_PHYS64 */ +#endif /* CONFIG_PHYS_64BIT */ -#ifdef CONFIG_PHYS64 +#ifdef CONFIG_PHYS_64BIT typedef unsigned long long dma_addr_t; typedef u64 phys_addr_t; typedef u64 phys_size_t; -#else /* CONFIG_PHYS64 */ +#else /* CONFIG_PHYS_64BIT */ typedef unsigned long dma_addr_t; typedef u32 phys_addr_t; typedef u32 phys_size_t; -#endif /* CONFIG_PHYS64 */ +#endif /* CONFIG_PHYS_64BIT */ #endif /* __KERNEL__ */ -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/3] sandbox: Properly print physical addresses
From: Thierry Reding
Use the %pap printf specifier to print physical addresses. The physical
address is passed by reference and hence avoids the need to play tricks
with the preprocessor to use the correct specifier.
Signed-off-by: Thierry Reding
---
arch/sandbox/lib/pci_io.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/sandbox/lib/pci_io.c b/arch/sandbox/lib/pci_io.c
index 5039973cd7af..01822c606956 100644
--- a/arch/sandbox/lib/pci_io.c
+++ b/arch/sandbox/lib/pci_io.c
@@ -34,7 +34,7 @@ int pci_map_physmem(phys_addr_t paddr, unsigned long *lenp,
return 0;
}
- debug("%s: failed: addr=%x\n", __func__, paddr);
+ debug("%s: failed: addr=%pap\n", __func__, );
return -ENOSYS;
}
--
2.20.1
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[U-Boot] [PATCH 1/3] vsprintf: Support phys_addr_t specifier unconditionally
From: Thierry Reding
When phys_addr_t printf specifier support was first introduced in commit
1eebd14b7902 ("vsprintf: Add modifier for phys_addr_t"), it was enabled
only if CONFIG_CMD_NET was selected. Since physical addresses are not
unique to networking support it doesn't make sense to conditionally add
it in those cases only. Move support for it outside of the CMD_NET guard
so that the specifier is always supported.
Signed-off-by: Thierry Reding
---
lib/vsprintf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 1b6c154d8d72..2403825dc98d 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -457,7 +457,6 @@ static char *pointer(const char *fmt, char *buf, char *end,
void *ptr,
return device_path_string(buf, end, ptr, field_width,
precision, flags);
#endif
-#ifdef CONFIG_CMD_NET
case 'a':
flags |= SPECIAL | ZEROPAD;
@@ -469,6 +468,7 @@ static char *pointer(const char *fmt, char *buf, char *end,
void *ptr,
break;
}
break;
+#ifdef CONFIG_CMD_NET
case 'm':
flags |= SPECIAL;
/* Fallthrough */
--
2.20.1
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Re: [U-Boot] passing info from SPL to U-Boot
Hello Simon, Tom,
Am 12.03.2019 um 09:21 schrieb Heiko Schocher:
Hello Simon, Tom,
I am just stumbeld on an am437x basd board over the problem to pass
the bootmode from SPL to U-Boot. On am437x the bootmode info get
overwritten from SPL stack, and I need this info in U-Boot.
Hack would be to move SPL stack to another address, but we loose
than 0xa000 size for stack ... I do not want to go this way..
I thought gd info is passed from SPL to U-Boot, but this is not the case!
Looking into
...
75 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
76 mov sp, r0
77 bl board_init_f_alloc_reserve
78 mov sp, r0
79 /* set up gd here, outside any C code */
80 mov r9, r0
81 bl board_init_f_init_reserve
and common/init/board_init.c:
99 void board_init_f_init_reserve(ulong base)
100 {
101 struct global_data *gd_ptr;
102
103 /*
104 * clear GD entirely and set it up.
105 * Use gd_ptr, as gd may not be properly set yet.
106 */
107
108 gd_ptr = (struct global_data *)base;
109 /* zero the area */
110 memset(gd_ptr, '\0', sizeof(*gd));
111 /* set GD unless architecture did it already */
112 #if !defined(CONFIG_ARM)
113 arch_setup_gd(gd_ptr);
114 #endif
gd is always initialized with zeros, no chance for passing infos from
SPL to U-Boot...
I really thought, that gd_t was intentionally designed for passing data
between different U-Boot states, but looking into gd_t definiton in
include/asm-generic/global_data.h it is a big ifdef mess and not useable
as an "API" between TPL/SPL and U-Boot ...
I thought also, that SPL detects for example ramsize and than passes
this info to U-Boot ...
But Ok, I found "common/init/handoff.c" which seems now the way to go, but:
./common/board_f.c
281 static int setup_spl_handoff(void)
282 {
283 #if CONFIG_IS_ENABLED(HANDOFF)
284 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
285 sizeof(struct spl_handoff));
286 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
287 #endif
288
289 return 0;
290 }
There is gd->spl_handoff used ... how could this work at least on arm,
if gd is set to zeros on init ?
Do I miss something obvious?
Sorry for being so stupid, with:
common/board_f.c
853 #ifdef CONFIG_BLOBLIST
854 bloblist_init,
855 #endif
856 setup_spl_handoff,
and common/bloblist.c
216 int bloblist_init(void)
217 {
218 bool expected;
219 int ret = -ENOENT;
220
221 /**
222 * Wed expect to find an existing bloblist in the first phase of
U-Boot
223 * that runs
224 */
225 expected = !u_boot_first_phase();
226 if (expected)
227 ret = bloblist_check(CONFIG_BLOBLIST_ADDR,
228 CONFIG_BLOBLIST_SIZE);
gd->spl_handoff gets setup through bloblist_find() ...
But beside sandbox there is no current user currently, or?
$ grep -lr BLOBLIST_ADDR .
./test/bloblist.c
./include/bloblist.h
./common/bloblist.c
./common/Kconfig
./board/sandbox/README.sandbox
$
bye,
Heiko
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[U-Boot] [PATCH] net: mscc: ocelot: Fix reset of the phys
The function mscc_miim_reset resets all the phys, but it is called for
each phy separetely. One consequence of this is that the boot time
is increased by 2 seconds.
The fix consists for calling the mscc_miim_reset function only once for
all phys.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/ocelot_switch.c | 27 ++-
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
index bf08c35..815c2da 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -142,18 +142,16 @@ static const unsigned long ocelot_regs_ana_table[] = {
static struct mscc_miim_dev miim[NUM_PHY];
-static int mscc_miim_reset(struct mii_dev *bus)
+static void mscc_phy_reset(void)
{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
-
- if (miim->phy_regs) {
- writel(0, miim->phy_regs + PHY_CFG);
- writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
- | PHY_CFG_ENA, miim->phy_regs + PHY_CFG);
- mdelay(500);
+ writel(0, miim[INTERNAL].phy_regs + PHY_CFG);
+ writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
+ | PHY_CFG_ENA, miim[INTERNAL].phy_regs + PHY_CFG);
+ if (wait_for_bit_le32(miim[INTERNAL].phy_regs + PHY_STAT,
+ PHY_STAT_SUPERVISOR_COMPLETE,
+ true, 2000, false)) {
+ pr_err("Timeout in phy reset\n");
}
-
- return 0;
}
/* For now only setup the internal mdio bus */
@@ -194,7 +192,6 @@ static struct mii_dev *ocelot_mdiobus_init(struct udevice
*dev)
miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);
miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);
bus->priv = [INTERNAL];
- bus->reset = mscc_miim_reset;
bus->read = mscc_miim_read;
bus->write = mscc_miim_write;
@@ -210,13 +207,8 @@ __weak void mscc_switch_reset(void)
static void ocelot_stop(struct udevice *dev)
{
- struct ocelot_private *priv = dev_get_priv(dev);
- int i;
-
mscc_switch_reset();
- for (i = 0; i < NUM_PHY; i++)
- if (priv->bus[i])
- mscc_miim_reset(priv->bus[i]);
+ mscc_phy_reset();
}
static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
@@ -473,6 +465,7 @@ static int ocelot_probe(struct udevice *dev)
}
priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);
+ mscc_phy_reset();
for (i = 0; i < 4; i++) {
phy_connect(priv->bus[INTERNAL], i, dev,
--
2.7.4
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Re: [U-Boot] dts: imx8qxp-mek: Add PHY post reset delay
Hi Joe, On Tue, 5 Mar 2019 12:05:42 -0600 Joe Hershberger joe.hershber...@ni.com wrote: > Hi Andrejs, > > https://patchwork.ozlabs.org/patch/1050178/ was applied to > http://git.denx.de/?p=u-boot/u-boot-net.git This patch is marked as accepted on patchwork, but it is not in mainline tree yet. It should go into v2019.04 release, too. Could you please check? Thanks, Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: dm: fec: Support phy-reset-post-delay property
Hi Joe, On Tue, 5 Mar 2019 12:05:38 -0600 Joe Hershberger joe.hershber...@ni.com wrote: > Hi Andrejs, > > https://patchwork.ozlabs.org/patch/1050177/ was applied to > http://git.denx.de/?p=u-boot/u-boot-net.git This patch is not in mainline tree yet, but it is marked as accepted on patchwork. Could you please check? This is part of a bug-fix for broken ethernet on the board and should go into v2019.04 release. Thanks, Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v7 00/15] SiFive FU540 Support
On Mon, 11 Mar 2019 07:33:25 PDT (-0700), bmeng...@gmail.com wrote: On Thu, Feb 14, 2019 at 7:58 AM Kevin Hilman wrote: Kevin Hilman writes: > Hi Anup, > > Anup Patel writes: > >> This patchset adds SiFive Freedom Unleashed (FU540) support >> to RISC-V U-Boot. >> >> The patches are based upon latest U-Boot source tree >> (git://git.denx.de/u-boot.git) at commit id >> dbe70c7d4e3d5c705a98d82952e05a591efd0683 >> >> All drivers namely: SiFive PRCI, SiFive Serial, and Cadance >> MACB Ethernet work fine on actual SiFive Unleashed board and >> QEMU sifive_u machine. > > I tested u-boot networking (DHCP, TFTP) on my desk with a gigE switch > and it worked fine. Then, I moved it to a lab with a 100Mb switch, > and DHCP doesn't work anymore. And to be clear, neither does TFTP if setting static ipaddr/netmask/gatewayip etc. Sound to me a bug of the GEM driver on SiFive FU540 board. It looks to me like u-boot is missing a driver for the GEM clockmux in the FU540. This is necessary to switch between the clock for 1G operation and 100M operation. Without this you'll just get whatever clock was set up by the previous boot stage (or even worse, reset). ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [BUG] cb8af8af5ba0 "fs: fat: support write with non-zero offset" fatwrite followed by fatload and then cmp fails
Hi Akashi,
On 11/09/18 12:29 PM, Akashi, Takahiro wrote:
> From: AKASHI Takahiro
>
> The current write implementation is quite simple: remove existing clusters
> and then allocating new ones and filling them with data. This, inevitably,
> enforces always writing from the beginning of a file.
>
> As the first step to lift this restriction, fat_file_write() and
> set_contents() are modified to accept an additional parameter, file offset
> and further re-factored so that, in the next patch, all the necessary code
> will be put into set_contents().
>
> Signed-off-by: AKASHI Takahiro
> ---
My fatwrite, fatload and compare tests are failing in MMC with this
commit. This is what I see:
=> fatwrite mmc 0 ${loadaddr} test 0x200
33554432 bytes written
=> fatload mmc 0 8400 test
33554432 bytes read in 2149 ms (14.9 MiB/s)
=> cmp.b 8200 8400 0x200
byte at 0x820c5000 (0x85) != byte at 0x840c5000 (0x9d)
Total of 806912 byte(s) were the same
=>
Reverting this commit fixes this issue for me.
Thanks,
Faiz
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[U-Boot] [PATCH v2 2/2] tools: fit_image: Add the loadable property to configs
When running mkimage with "-f auto", the loadable property needs to be set in order to allow SPL FIT support to boot. Signed-off-by: Abel Vesa --- tools/fit_image.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/fit_image.c b/tools/fit_image.c index 4b62635..3b867e0 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -298,6 +298,7 @@ static void fit_write_configs(struct image_tool_params *params, char *fdt) typename = genimg_get_type_short_name(params->fit_image_type); snprintf(str, sizeof(str), "%s-1", typename); fdt_property_string(fdt, typename, str); + fdt_property_string(fdt, FIT_LOADABLE_PROP, str); if (params->fit_ramdisk) fdt_property_string(fdt, FIT_RAMDISK_PROP, -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled
If FIT_IMAGE_TINY is enabled, spl_fit_image_get_os returns -ENOTSUPP.
In this case, we should default to IH_OS_U_BOOT not to IH_OS_INVALID.
Signed-off-by: Abel Vesa
---
Changes since v1:
* added the #if FIT_IMAGE_TINY as suggested by Mark Vasut
common/spl/spl_fit.c | 4
1 file changed, 4 insertions(+)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index db43626..c9bfe0c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -491,6 +491,10 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
if (!spl_fit_image_get_os(fit, node, _type))
debug("Loadable is %s\n", genimg_get_os_name(os_type));
+#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
+ else
+ os_type = IH_OS_U_BOOT;
+#endif
if (os_type == IH_OS_U_BOOT) {
spl_fit_append_fdt(_info, info, sector,
--
2.7.4
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[U-Boot] [PATCH 10/10] ddr: altera: Stratix10: Add ECC memory scrubbing
Scrub memory content if ECC is enabled and it is not
from warm reset boot.
Enable icache and dcache before scrub memory
and use "DC ZVA" instruction to clear memory
to zeros. This instruction writes a cache line
at a time and it can prevent false ECC error
trigger if write cache line partially.
Signed-off-by: Ley Foon Tan
---
.../arm/mach-socfpga/include/mach/sdram_s10.h | 9 +++
drivers/ddr/altera/sdram_s10.c| 76 +++
2 files changed, 85 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
index 89e355010d..354f80bfce 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -23,6 +23,7 @@ void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t
bank_size[]);
#define ECCCTRL1 0x100
#define ECCCTRL2 0x104
#define ERRINTEN 0x110
+#define ERRINTENS 0x114
#define INTMODE0x11c
#define INTSTAT0x120
#define AUTOWB_CORRADDR0x138
@@ -53,6 +54,10 @@ void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t
bank_size[]);
#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK0x001f1f1f
+#defineDDR_HMC_ERRINTEN_INTMASK\
+ (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |\
+DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
+
/* NOC DDR scheduler */
#define DDR_SCH_ID_COREID 0
#define DDR_SCH_ID_REVID 0x4
@@ -181,4 +186,8 @@ void setup_memory_banks(phys_addr_t bank_addr[],
phys_size_t bank_size[]);
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
(((x) >> 0) & 0xFF)
+/* Firewall DDR scheduler MPFE */
+#define FW_HMC_ADAPTOR_REG_ADDR0xf8020004
+#define FW_HMC_ADAPTOR_MPU_MASKBIT(0)
+
#endif /* _SDRAM_S10_H_ */
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index ae4e5ea2fd..2c691d3bee 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -22,6 +22,8 @@ static const struct socfpga_system_manager *sysmgr_regs =
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define PGTABLE_OFF0x4000
+
/* The followring are the supported configurations */
u32 ddr_config[] = {
/* DDR_CONFIG(Address order,Bank,Column,Row) */
@@ -135,6 +137,71 @@ static int poll_hmc_clock_status(void)
SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
}
+static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
+{
+ phys_size_t i;
+
+ if (addr % CONFIG_SYS_CACHELINE_SIZE) {
+ printf("DDR: address 0x%lx not cacheline size aligned.\n",
+ (ulong)addr);
+ hang();
+ }
+
+ if (size % CONFIG_SYS_CACHELINE_SIZE) {
+ printf("DDR: size 0x%lx not multiple of cacheline size\n",
+ (ulong)size);
+ hang();
+ }
+
+ /* Use DC ZVA instruction to clear memory to zeros by a cache line */
+ for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
+ asm("dc zva, %0"
+:
+: "r"(addr));
+ addr += CONFIG_SYS_CACHELINE_SIZE;
+ }
+}
+
+static void sdram_init_ecc_bits(phys_addr_t *bank_start, phys_size_t
*bank_size)
+{
+ phys_size_t size, size_init;
+ phys_addr_t start_addr;
+ int bank;
+ unsigned int start = get_timer(0);
+
+ icache_enable();
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start_addr = bank_start[bank];
+ size = bank_size[bank];
+
+ if (bank == 0) {
+ /* Initialize small block for page table */
+ memset((void *)start_addr, 0,
+ PGTABLE_SIZE + PGTABLE_OFF);
+ gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ start_addr += PGTABLE_SIZE + PGTABLE_OFF;
+ size -= (PGTABLE_OFF + PGTABLE_SIZE);
+ dcache_enable();
+ }
+
+ while (size) {
+ size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
+ sdram_clear_mem(start_addr, size_init);
+ size -= size_init;
+ start_addr += size_init;
+ WATCHDOG_RESET();
+ }
+ }
+
+ dcache_disable();
+ icache_disable();
+
+ printf("SDRAM-ECC: Initialized success with %d ms\n",
+ (unsigned int)get_timer(start));
+}
+
static void
[U-Boot] [PATCH 08/10] configs: stratix10: Change CONFIG_NR_DRAM_BANKS to 2
Stratix 10 SoC support 2 DRAM banks. Signed-off-by: Ley Foon Tan --- configs/socfpga_stratix10_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 9e6d582ee3..4a14ea039e 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -6,7 +6,7 @@ CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_SPL=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y -CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=2 CONFIG_BOOTDELAY=5 CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y -- 2.19.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/10] board: altera: Stratix10: Add ft_board_setup()
Add ft_board_setup() function to setup memory banks before
boot to Linux.
Signed-off-by: Ley Foon Tan
---
board/altera/stratix10-socdk/socfpga.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/board/altera/stratix10-socdk/socfpga.c
b/board/altera/stratix10-socdk/socfpga.c
index 99c10d313c..ca6e0e9085 100644
--- a/board/altera/stratix10-socdk/socfpga.c
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
@@ -17,3 +18,27 @@ ulong board_get_usable_ram_top(ulong total_size)
return sdram_calculate_size();
}
#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int ret = 0;
+#ifdef CONFIG_OF_LIBFDT
+ int bank;
+ int actual_bank = 0;
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ if (bd->bi_dram[bank].size) {
+ start[actual_bank] = bd->bi_dram[bank].start;
+ size[actual_bank++] = bd->bi_dram[bank].size;
+ }
+ }
+
+ ret = fdt_fixup_memory_banks(blob, start, size, actual_bank);
+#endif /* CONFIG_OF_LIBFDT */
+
+ return ret;
+}
+#endif
--
2.19.0
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[U-Boot] [PATCH 07/10] arm: socfpga: Enable OF_BOARD_SETUP for Stratix 10
Enable OF_BOARD_SETUP for Stratix 10. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5e87371f8c..990e46fe06 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -36,6 +36,7 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_SET_SMPEN select ARMV8_SPIN_TABLE select FPGA_STRATIX10 + select OF_BOARD_SETUP choice prompt "Altera SOCFPGA board select" -- 2.19.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 09/10] arm: socfpga: stratix10: Add cpu_has_been_warmreset()
Add helper function cpu_has_been_warmreset() to check
if CPU is from warm reset boot.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | 3 +++
arch/arm/mach-socfpga/reset_manager_s10.c | 9 +
2 files changed, 12 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 31b73edabe..e186296791 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -9,6 +9,7 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+int cpu_has_been_warmreset(void);
void socfpga_bridges_reset(int enable);
@@ -47,6 +48,8 @@ struct socfpga_reset_manager {
#define RSTMGR_MPUMODRST_CORE0 0
#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X0040
+/* Watchdogs and MPU warm reset mask */
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
/*
* Define a reset identifier, from which a permodrst bank ID
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index f176c38495..f8dd787cc6 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -103,3 +103,12 @@ void reset_deassert_peripherals_handoff(void)
writel(~RSTMGR_PER0MODRST_OCP_MASK, _manager_base->per0modrst);
writel(0, _manager_base->per0modrst);
}
+
+/*
+ * Return non-zero if the CPU has been warm reset
+ */
+int cpu_has_been_warmreset(void)
+{
+ return readl(_manager_base->status) &
+ RSTMGR_L4WD_MPU_WARMRESET_MASK;
+}
--
2.19.0
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[U-Boot] [PATCH 05/10] board: altera: Stratix10: Add board_get_usable_ram_top()
Add board_get_usable_ram_top() function. Limit maximum usable
ram top to 2GB.
Signed-off-by: Dalon Westergreen
Signed-off-by: Ley Foon Tan
---
board/altera/stratix10-socdk/socfpga.c | 12
1 file changed, 12 insertions(+)
diff --git a/board/altera/stratix10-socdk/socfpga.c
b/board/altera/stratix10-socdk/socfpga.c
index 043fc543f1..99c10d313c 100644
--- a/board/altera/stratix10-socdk/socfpga.c
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -5,3 +5,15 @@
*/
#include
+#include
+#include
+
+#ifdef CONFIG_ALTERA_SDRAM
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ if (sdram_calculate_size() > SZ_2G)
+ return SZ_2G;
+ else
+ return sdram_calculate_size();
+}
+#endif
--
2.19.0
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[U-Boot] [PATCH 04/10] arm: socfpga: Update dram_init_banksize() for Stratix10
Setup bi_dram struct based on returned from setup_memory_banks().
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/board.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 7c8c05cc31..a0e9917e47 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
@@ -48,8 +49,21 @@ int board_init(void)
int dram_init_banksize(void)
{
- fdtdec_setup_memory_banksize();
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) && defined(CONFIG_ALTERA_SDRAM)
+ phys_addr_t bank_start[CONFIG_NR_DRAM_BANKS];
+ phys_size_t bank_size[CONFIG_NR_DRAM_BANKS];
+ int bank;
+
+ gd->ram_size = sdram_calculate_size();
+ setup_memory_banks(bank_start, bank_size);
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ gd->bd->bi_dram[bank].start = bank_start[bank];
+ gd->bd->bi_dram[bank].size = bank_size[bank];
+ }
+#else
+ fdtdec_setup_memory_banksize();
+#endif
return 0;
}
--
2.19.0
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[U-Boot] [PATCH 02/10] arm: socfpga: Add sdram_s10.h to sdram.h
Includes Stratix10 SDRAM header file. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/sdram.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 79cb9e6064..2c1f55a87a 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -11,6 +11,8 @@ #include #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include #endif #endif -- 2.19.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 03/10] ddr: altera: s10: Add multiple memory banks support
Setup bank start address and size based on total SDRAM
memory size calculated from hardware. Update sdram_size_check()
to support multiple banks.
Stratix10 supports up to 2 memory banks.
Bank 0: Address 0, size 2GB
Bank 1: Address 0x1, size 124GB
Signed-off-by: Dalon Westergreen
Signed-off-by: Ley Foon Tan
---
.../arm/mach-socfpga/include/mach/sdram_s10.h | 1 +
drivers/ddr/altera/sdram_s10.c| 93 ++-
2 files changed, 91 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
index ca68594445..89e355010d 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -10,6 +10,7 @@
phys_size_t sdram_calculate_size(void);
int sdram_mmr_init_full(unsigned int sdr_phy_reg);
int sdram_calibration_full(void);
+void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[]);
#define DDR_TWR15
#define DDR_READ_LATENCY_DELAY 40
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 8895813440..ae4e5ea2fd 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -134,17 +135,100 @@ static int poll_hmc_clock_status(void)
SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
}
-static void sdram_size_check(void)
+static void sdram_size_check(phys_addr_t bank_start[], phys_size_t bank_size[])
{
+ phys_size_t total_ram_check = 0;
+ phys_size_t ram_check = 0;
+ int bank;
+
/* Sanity check ensure correct SDRAM size specified */
debug("DDR: Running SDRAM size sanity check\n");
- if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ while (ram_check < bank_size[bank]) {
+ ram_check += get_ram_size((void *)(bank_start[bank]
+ + ram_check),
+ (phys_size_t)SZ_1G);
+ }
+ total_ram_check += ram_check;
+ ram_check = 0;
+ }
+
+ if (total_ram_check != gd->ram_size) {
puts("DDR: SDRAM size check failed!\n");
hang();
}
+
debug("DDR: SDRAM size check passed!\n");
}
+void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[])
+{
+ phys_size_t ram_alias;
+
+ bank_addr[0] = CONFIG_SYS_SDRAM_BASE;
+ bank_size[0] = min((phys_size_t)SZ_2G, (phys_size_t)gd->ram_size);
+
+ if (CONFIG_NR_DRAM_BANKS > 1) {
+ if (gd->ram_size > ((phys_size_t)SZ_2G * (phys_size_t)32)) {
+ /* With memories > 64GB it is not possible to
+* access the entire memory. You cannot avoid
+* the 2GB IO hole from 2GB to 4GB in the HPS
+* memory space. The dram banks must be configured
+* as :
+* dram[0].start = 0x0
+* dram[0].size = SZ_2GB
+* dram[1].start = SZ_2GB << 1 (or 4GB)
+* dram[1].size = gd->ram_size - SZ_2G
+*/
+ bank_addr[1] = (phys_addr_t)SZ_2G +
+ (phys_addr_t)SZ_2G;
+ bank_size[1] = gd->ram_size - SZ_2G;
+
+ /* reduce ram size as useable space is smaller.
+* We cannot avoid the IO hole.
+*/
+ gd->ram_size -= SZ_2G;
+
+ } else if (gd->ram_size > SZ_2G) {
+ /* We can use that the DRAM address space
+* is repeatedly aliased in the overall
+* 128GB of address space as the SDRAM NOC
+* ignores unused upper address bits.
+*
+* This means, a 4GB DDR is replicated every
+* 4GB in the address, and a 16GB DDR every
+* 16GB.
+*
+* So, we can access the entire memory, for
+* the 4GB case:
+* dram[0].start = 0x0
+* dram[0].size = SZ_2GB
+* dram[1].start = SZ_2GB << 1 + SZ_2GB (or 6GB)
+* dram[1].size = gd->ram_size - SZ_2G
+*
+* more interestingly, the 3GB case would be the same.
+*/
+
+ /* Now we need to find the appropriate alias
+* location.
+*/
+
[U-Boot] [PATCH 01/10] ddr: altera: stratix10: Move SDRAM size check to SDRAM driver
Move SDRAM size check to SDRAM driver. sdram_calculate_size()
is called in SDRAM initialization already, avoid calling
twice in size check function.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/spl_s10.c | 11 ---
drivers/ddr/altera/sdram_s10.c | 15 +++
2 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a3db20a819..a141ffe82a 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -181,17 +181,6 @@ void board_init_f(ulong dummy)
hang();
}
- gd->ram_size = sdram_calculate_size();
- printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
-
- /* Sanity check ensure correct SDRAM size specified */
- debug("DDR: Running SDRAM size sanity check\n");
- if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
- puts("DDR: SDRAM size check failed!\n");
- hang();
- }
- debug("DDR: SDRAM size check passed!\n");
-
mbox_init();
#ifdef CONFIG_CADENCE_QSPI
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index a48567c109..8895813440 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void)
SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
}
+static void sdram_size_check(void)
+{
+ /* Sanity check ensure correct SDRAM size specified */
+ debug("DDR: Running SDRAM size sanity check\n");
+ if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
+ puts("DDR: SDRAM size check failed!\n");
+ hang();
+ }
+ debug("DDR: SDRAM size check passed!\n");
+}
+
/**
* sdram_mmr_init_full() - Function to initialize SDRAM MMR
*
@@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused)
else
gd->ram_size = size;
+ printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
+
/* Enable or disable the SDRAM ECC */
if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
@@ -361,6 +374,8 @@ int sdram_mmr_init_full(unsigned int unused)
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
}
+ sdram_size_check();
+
debug("DDR: HMC init success\n");
return 0;
}
--
2.19.0
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[U-Boot] [PATCH 00/10] Update Stratix 10 SDRAM driver
This patchset update Stratix 10 SDRAM driver to support: - Multi-banks memory (Patch [1-8]) - Stratix 10 support up to 2 memory banks: Bank 0: Address 0, size 2GB Bank 1: Address 0x1, size 124GB - Add warm reset boot checking function, to use in patch [10] (Patch[9]) - Add ECC memory scrubbing support (Patch [10]) - Use cache enabled + "DC ZVA" instruction to clear memory to zeros Ley Foon Tan (10): ddr: altera: stratix10: Move SDRAM size check to SDRAM driver arm: socfpga: Add sdram_s10.h to sdram.h ddr: altera: s10: Add multiple memory banks support arm: socfpga: Update dram_init_banksize() for Stratix10 board: altera: Stratix10: Add board_get_usable_ram_top() board: altera: Stratix10: Add ft_board_setup() arm: socfpga: Enable OF_BOARD_SETUP for Stratix 10 configs: stratix10: Change CONFIG_NR_DRAM_BANKS to 2 arm: socfpga: stratix10: Add cpu_has_been_warmreset() ddr: altera: Stratix10: Add ECC memory scrubbing arch/arm/mach-socfpga/Kconfig | 1 + arch/arm/mach-socfpga/board.c | 16 +- .../include/mach/reset_manager_s10.h | 3 + arch/arm/mach-socfpga/include/mach/sdram.h| 2 + .../arm/mach-socfpga/include/mach/sdram_s10.h | 10 + arch/arm/mach-socfpga/reset_manager_s10.c | 9 + arch/arm/mach-socfpga/spl_s10.c | 11 -- board/altera/stratix10-socdk/socfpga.c| 37 configs/socfpga_stratix10_defconfig | 2 +- drivers/ddr/altera/sdram_s10.c| 178 ++ 10 files changed, 256 insertions(+), 13 deletions(-) -- 2.19.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] please pull u-boot-samsung master
Hi Tom, The following changes since commit e8e3f2d2d48f97b2c79b698eccedce8f4f880993: Merge branch '2019-03-08-master-imports' (2019-03-08 18:04:13 -0500) are available in the git repository at: git://git.denx.de/u-boot-samsung master for you to fetch changes up to 0fd36730396a86e5513b45221af60889e6028654: ARM: Odroid XU3: Enable driver I2C support for OdroidXU3 (2019-03-12 15:56:45 +0900) Anand Moon (1): ARM: Odroid XU3: Enable driver I2C support for OdroidXU3 Krzysztof Kozlowski (15): adc: exynos-adc: Fix wrong bit operation used to stop the ADC power: regulator: s2mps11: Fix step for LDO27 and LDO35 arm: exynos: Detect revision later, when all resources are ready arm: exynos: odroid-xu3: Display info late to have proper type arm: exynos: Wait till ADC stabilizes before checking Odroid HC1 revision regulator: Add support for ramp delay power: regulator: s2mps11: Add enable delay arm: dts: exynos: Add supply for ADC block to Odroid XU3 family arm: dts: exynos: Add ramp delay property to LDO regulators to Odroid XU3 family arm: exynos: arndale: Replace Chander Kashyap inactive maintainer configs: odroid_xu3: Use consistent syntax for #include configs: odroid_xu3: Unify indentation arm: exynos: Remove duplicated "boardname" env setting arm: dts: exynos: Adjust whitespace around status property arm: exynos: odroid: Fix build if BOARD_TYPES are not set Minkyu Kang (1): espresso7420: remove duplicated config arch/arm/dts/exynos5422-odroidxu3.dts| 22 +- board/samsung/arndale/MAINTAINERS| 4 ++-- board/samsung/common/board.c | 25 +++-- board/samsung/common/bootscripts/autoboot.cmd| 10 +- board/samsung/common/exynos5-dt-types.c | 54 ++ board/samsung/common/misc.c | 2 +- board/samsung/odroid/odroid.c| 35 +-- configs/odroid-xu3_defconfig | 3 +++ doc/device-tree-bindings/regulator/regulator.txt | 2 ++ drivers/adc/exynos-adc.c | 2 +- drivers/power/regulator/regulator-uclass.c | 47 +-- drivers/power/regulator/s2mps11_regulator.c | 15 ++- include/configs/espresso7420.h | 2 -- include/configs/odroid.h | 2 +- include/configs/odroid_xu3.h | 20 include/power/regulator.h| 2 ++ include/samsung/misc.h | 1 + 17 files changed, 212 insertions(+), 36 deletions(-) -- Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] passing info from SPL to U-Boot
Hello Simon, Tom,
I am just stumbeld on an am437x basd board over the problem to pass
the bootmode from SPL to U-Boot. On am437x the bootmode info get
overwritten from SPL stack, and I need this info in U-Boot.
Hack would be to move SPL stack to another address, but we loose
than 0xa000 size for stack ... I do not want to go this way..
I thought gd info is passed from SPL to U-Boot, but this is not the case!
Looking into
...
75 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
76 mov sp, r0
77 bl board_init_f_alloc_reserve
78 mov sp, r0
79 /* set up gd here, outside any C code */
80 mov r9, r0
81 bl board_init_f_init_reserve
and common/init/board_init.c:
99 void board_init_f_init_reserve(ulong base)
100 {
101 struct global_data *gd_ptr;
102
103 /*
104 * clear GD entirely and set it up.
105 * Use gd_ptr, as gd may not be properly set yet.
106 */
107
108 gd_ptr = (struct global_data *)base;
109 /* zero the area */
110 memset(gd_ptr, '\0', sizeof(*gd));
111 /* set GD unless architecture did it already */
112 #if !defined(CONFIG_ARM)
113 arch_setup_gd(gd_ptr);
114 #endif
gd is always initialized with zeros, no chance for passing infos from
SPL to U-Boot...
I really thought, that gd_t was intentionally designed for passing data
between different U-Boot states, but looking into gd_t definiton in
include/asm-generic/global_data.h it is a big ifdef mess and not useable
as an "API" between TPL/SPL and U-Boot ...
I thought also, that SPL detects for example ramsize and than passes
this info to U-Boot ...
But Ok, I found "common/init/handoff.c" which seems now the way to go, but:
./common/board_f.c
281 static int setup_spl_handoff(void)
282 {
283 #if CONFIG_IS_ENABLED(HANDOFF)
284 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
285 sizeof(struct spl_handoff));
286 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
287 #endif
288
289 return 0;
290 }
There is gd->spl_handoff used ... how could this work at least on arm,
if gd is set to zeros on init ?
Do I miss something obvious?
bye,
Heiko
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Re: [U-Boot] [PATCH] ARM: Odroid XU3: Enable driver I2C support for OdroidXU3
On 25/02/2019 17:42, Krzysztof Kozlowski wrote: > On Sun, 24 Feb 2019 at 13:41, Anand Moon wrote: >> >> This commit enables support for I2C S3C424X0 driver. >> >> Signed-off-by: Anand Moon >> --- >> >> ODROID-XU3 # i2c bus >> Bus 0: i2c@12C6 >> Bus 1: i2c@12C7 >> Bus 2: i2c@12C8 >> Bus 3: i2c@12C9 >> Bus 4: i2c@12CA (active 4) >>66: s2mps11_pmic@66, offset len 1, flags 0 >> Bus 5: i2c@12CB >> Bus 6: i2c@12CC >> Bus 7: i2c@12CD >> Bus 8: i2c@12E0 >> Bus 9: i2c@12E1 >> Bus 10: i2c@12E2 > > But that's exactly the same output as without this patch... > > Best regards, > Krzysztof > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot > applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
