Re: [U-Boot] [PATCH v2 6/6] arm: socfpga: a10: move SPL stack size to Kconfig

[Chee, Tien Fong]

On Tue, 2019-03-19 at 17:29 +0100, Simon Goldschmidt wrote:
> Am 19.03.2019 um 17:19 schrieb Chee, Tien Fong:
> > 
> > On Fri, 2019-03-15 at 21:13 +0100, Simon Goldschmidt wrote:
> > > 
> > > Instead of fixing the SPL stack to 64 KiB in the board config
> > > header
> > > via
> > > CONFIG_SYS_SPL_MALLOC_SIZE, let's just use
> > > CONFIG_SPL_SYS_MALLOC_F_LEN
> > > in the defconfig.
> > > 
> > > This also has the advandage that it removes sub-mach specific
> > > ifdefs
> > > in
> > > socfpga_common.h.
> > > 
> > > Signed-off-by: Simon Goldschmidt  > > >
> > > ---
> > Hi Simon,
> > 
> > I found the culprit in patch[5], you cannot put mem_malloc_init in
> > spl_common_init function because spl_common_init would be called in
> > board_init_f, then board_init_f would call mem_malloc_init,
> > mem_malloc_init would store start and end addresses to few global
> > variables such as mem_malloc_start, mem_malloc_end and
> > mem_malloc_brk.
> > By that time, global variables are unavailable yet.
> Thanks for testing. Patch 2/6 should make sure global variables are 
> available in board_init_f by clearing bss *before* calling that 
> function, not *after* calling it. Because technicaly, global
> variables 
> are always available for a10-SPL as they are located in SRAM. They
> only 
> got cleared after board_init_f...
Yes, you are right, memset would clear .BSS after mem_malloc_init.
> 
> Which gets me to my error: I forgot to enable the newly added 
> CONFIG_SPL_CLEAR_BSS_F in this patch. Could you probably try again
> with 
> CONFIG_SPL_CLEAR_BSS_F enabled? That would be great!
Tested, passing. May be force enabling it or compile error if full
malloc is used?

Thanks.
TF.
> 
> Regards,
> Simon
> 
> > 
> > 
> > Thanks.
> > TF
> > 
> > > 
> > > 
> > > Changes in v2: None
> > > 
> > >   configs/socfpga_arria10_defconfig |  1 +
> > >   include/configs/socfpga_common.h  | 14 --
> > >   2 files changed, 1 insertion(+), 14 deletions(-)
> > > 
> > > diff --git a/configs/socfpga_arria10_defconfig
> > > b/configs/socfpga_arria10_defconfig
> > > index f321a0ac3b..8d0479cc05 100644
> > > --- a/configs/socfpga_arria10_defconfig
> > > +++ b/configs/socfpga_arria10_defconfig
> > > @@ -2,6 +2,7 @@ CONFIG_ARM=y
> > >   CONFIG_ARCH_SOCFPGA=y
> > >   CONFIG_SYS_TEXT_BASE=0x0140
> > >   CONFIG_SYS_MALLOC_F_LEN=0x2000
> > > +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1
> > >   CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> > >   CONFIG_SPL=y
> > >   CONFIG_IDENT_STRING="socfpga_arria10"
> > > diff --git a/include/configs/socfpga_common.h
> > > b/include/configs/socfpga_common.h
> > > index 181af9b646..16c83900c3 100644
> > > --- a/include/configs/socfpga_common.h
> > > +++ b/include/configs/socfpga_common.h
> > > @@ -251,16 +251,6 @@ unsigned int
> > > cm_get_qspi_controller_clk_hz(void);
> > >   #define CONFIG_SPL_TEXT_BASECONFIG_SYS_INIT_RAM
> > > _ADDR
> > >   #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_
> > > SIZE
> > >   
> > > -#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > -/* SPL memory allocation configuration, this is for FAT
> > > implementation */
> > > -#ifndef CONFIG_SYS_SPL_MALLOC_START
> > > -#define CONFIG_SYS_SPL_MALLOC_SIZE   0x0001
> > > -#define CONFIG_SYS_SPL_MALLOC_START  (CONFIG_SYS_INIT_RAM_
> > > SIZE
> > > - \
> > > -  CONFIG_SYS_SPL_MALLOC_S
> > > IZE
> > > + \
> > > -  CONFIG_SYS_INIT_RAM_ADD
> > > R)
> > > -#endif
> > > -#endif
> > > -
> > >   /* SPL SDMMC boot support */
> > >   #ifdef CONFIG_SPL_MMC_SUPPORT
> > >   #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
> > > @@ -294,11 +284,7 @@ unsigned int
> > > cm_get_qspi_controller_clk_hz(void);
> > >   /*
> > >    * Stack setup
> > >    */
> > > -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > >   #define CONFIG_SPL_STACKCONFIG_SYS_INIT_SP_ADDR
> > > -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > -#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_ST
> > > ART
> > > -#endif
> > >   
> > >   /* Extra Environment */
> > >   #ifndef CONFIG_SPL_BUILD
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Re: [U-Boot] [PATCH v3 3/3] poplar: enable Ethernet driver support

[Shawn Guo]

On Tue, Mar 19, 2019 at 06:42:17PM +, Joe Hershberger wrote:
> On Sun, Mar 10, 2019 at 3:53 AM Shawn Guo  wrote:
> >
> > The 'phy' reset of gmac device in kernel device tree is not generic
> > enough for u-boot to use, so we need to overwrite the 'resets' property
> > as needed.  With this device tree fixup and poplar_defconfig changes,
> > Ethernet starts working on Poplar board.
> >
> > Signed-off-by: Shawn Guo 
> > Reviewed-by: Igor Opaniuk 
> > ---
> >  arch/arm/dts/hi3798cv200-u-boot.dtsi | 14 ++
> >  configs/poplar_defconfig |  3 +++
> >  2 files changed, 17 insertions(+)
> >
> > diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi 
> > b/arch/arm/dts/hi3798cv200-u-boot.dtsi
> > index 7844c5208c5d..2ca943f64e59 100644
> > --- a/arch/arm/dts/hi3798cv200-u-boot.dtsi
> > +++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi
> > @@ -8,7 +8,15 @@
> >   * (C) Copyright 2017 Jorge Ramirez-Ortiz 
> >   */
> >
> > +#include 
> 
> Where does this file come from?
> 
> > +
> >   {
> > +   rst: reset-controller@8a22000 {
> > +   compatible = "hisilicon,hi3798cv200-reset";
> > +   reg = <0x8a22000 0x1000>;
> 
> Would it not be reasonable to include the "0xcc" from below in this
> address instead of adding them at runtime?

In that case, if we have new client devices using other registers in the
reset controller, we will need to have multiple such nodes to be
defined.  This is less efficient and doesn't describe HW design well.

Shawn

> 
> 
> > +   #reset-cells = <3>;
> > +   };
> > +
> > usb2: ehci@989 {
> > compatible = "generic-ehci";
> > reg = <0x989 0x100>;
> > @@ -16,6 +24,12 @@
> > };
> >  };
> >
> > + {
> > +   resets = < 0xcc 9  HISI_RESET_ACTIVE_HIGH>,
> > +< 0xcc 11 HISI_RESET_ACTIVE_HIGH>,
> > +< 0xcc 13 HISI_RESET_ACTIVE_LOW>;
> > +};
> > +
> >   {
> > clock = <7500>;
> > status = "okay";
> > diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig
> > index 81bd3702e42a..76ab5eb70e7e 100644
> > --- a/configs/poplar_defconfig
> > +++ b/configs/poplar_defconfig
> > @@ -19,6 +19,9 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> >  CONFIG_DM_MMC=y
> >  CONFIG_MMC_DW=y
> >  CONFIG_MMC_DW_K3=y
> > +CONFIG_DM_ETH=y
> > +CONFIG_HIGMACV300_ETH=y
> > +CONFIG_RESET_HISILICON=y
> >  CONFIG_USB=y
> >  CONFIG_USB_EHCI_HCD=y
> >  CONFIG_USB_EHCI_GENERIC=y
> > --
> > 2.18.0
> >
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Re: [U-Boot] [PATCH v3 1/3] reset: add reset driver for HiSilicon platform

[Shawn Guo]

Hi Joe,

Thanks for the comments.

On Tue, Mar 19, 2019 at 06:42:06PM +, Joe Hershberger wrote:
> Hi Shawn,
> 
> On Sun, Mar 10, 2019 at 3:53 AM Shawn Guo  wrote:
> >
> > It adds a Driver Model compatible reset driver for HiSlicon platform.
> > The driver implements a custom .of_xlate function, and uses .data field
> > as reset register offset and .id field as bit shift.
> >
> > Signed-off-by: Shawn Guo 
> > Reviewed-by: Igor Opaniuk 
> > ---
> >  drivers/reset/Kconfig   |   6 ++
> >  drivers/reset/Makefile  |   1 +
> >  drivers/reset/reset-hisilicon.c | 111 
> >  3 files changed, 118 insertions(+)
> >  create mode 100644 drivers/reset/reset-hisilicon.c
> >
> > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> > index a81e76769604..6ec6f39c85f0 100644
> > --- a/drivers/reset/Kconfig
> > +++ b/drivers/reset/Kconfig
> > @@ -121,4 +121,10 @@ config RESET_SUNXI
> >   This enables support for common reset driver for
> >   Allwinner SoCs.
> >
> > +config RESET_HISILICON
> > +   bool "Reset controller driver for HiSilicon SoCs"
> > +   depends on DM_RESET
> > +   help
> > + Support for reset controller on HiSilicon SoCs.
> > +
> >  endmenu
> > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> > index 4fad7d412985..7fec75bb4923 100644
> > --- a/drivers/reset/Makefile
> > +++ b/drivers/reset/Makefile
> > @@ -19,3 +19,4 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o
> >  obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
> >  obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
> >  obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> > +obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
> > diff --git a/drivers/reset/reset-hisilicon.c 
> > b/drivers/reset/reset-hisilicon.c
> > new file mode 100644
> > index ..7b0c11fbc82e
> > --- /dev/null
> > +++ b/drivers/reset/reset-hisilicon.c
> > @@ -0,0 +1,111 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2019, Linaro Limited
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> 
> Where does this file come from?

Sorry, my bad.  It's a new file in my working tree, and I forgot to add
it.  It becomes unneeded in the next version though.

> 
> 
> > +#include 
> > +
> > +struct hisi_reset_priv {
> > +   void __iomem *base;
> > +};
> > +
> > +static int hisi_reset_deassert(struct reset_ctl *rst)
> > +{
> > +   struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
> > +   u32 offset = rst->data & 0x;
> > +   u32 shift = rst->data >> 16;
> > +   int polarity = rst->id;
> > +   u32 val;
> > +
> > +   val = readl(priv->base + offset);
> > +   if (polarity == HISI_RESET_ACTIVE_HIGH)
> > +   val &= ~BIT(shift);
> > +   else
> > +   val |= BIT(shift);
> > +   writel(val, priv->base + offset);
> > +
> > +   return 0;
> > +}
> > +
> > +static int hisi_reset_assert(struct reset_ctl *rst)
> > +{
> > +   struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
> > +   u32 offset = rst->data & 0x;
> > +   u32 shift = rst->data >> 16;
> > +   int polarity = rst->id;
> > +   u32 val;
> > +
> > +   val = readl(priv->base + offset);
> > +   if (polarity == HISI_RESET_ACTIVE_HIGH)
> > +   val |= BIT(shift);
> > +   else
> > +   val &= ~BIT(shift);
> > +   writel(val, priv->base + offset);
> > +
> > +   return 0;
> > +}
> > +
> > +static int hisi_reset_free(struct reset_ctl *rst)
> > +{
> > +   return 0;
> > +}
> > +
> > +static int hisi_reset_request(struct reset_ctl *rst)
> > +{
> > +   return 0;
> > +}
> > +
> > +static int hisi_reset_of_xlate(struct reset_ctl *rst,
> > +  struct ofnode_phandle_args *args)
> > +{
> > +   if (args->args_count != 3) {
> > +   debug("Invalid args_count: %d\n", args->args_count);
> > +   return -EINVAL;
> > +   }
> > +
> > +   /*
> > +* Encode register offset in .data[15..0] and bit shift in
> > +* .data[31..16], and use .id field as polarity.
> > +*/
> 
> I don't like going through these contortions to avoid changing the
> struct in reset.h
> 
> I think you should add a "polarity" field to that struct and instead
> of defining a specific constant for HISI_RESET_ACTIVE_HIGH, instead
> make a generic one that everyone can use, such as the ASSERT_CLEAR and
> friends in Linux.

Okay, will do in the next version.  As the ASSERT_CLEAR and friends are
defined in include/dt-bindings/reset/ti-syscon.h (already copied into
U-Boot from Linux), I will just use this header.

> 
> I also hope you can get rid of the register offset and either include
> it in the DT base address if it is something that needs to be selected
> or simply make a #define for the 0xCC for what the register is called
> and go from there.

Although the resets we need for GMAC happen to be in a single register,
the 

Re: [U-Boot] [PATCH 01/10] ddr: altera: stratix10: Move SDRAM size check to SDRAM driver

[Ley Foon Tan]

On Tue, Mar 19, 2019 at 5:47 PM Marek Vasut  wrote:
>
> On 3/19/19 10:46 AM, Ley Foon Tan wrote:
> > On Tue, Mar 19, 2019 at 5:39 PM Marek Vasut  wrote:
> >>
> >> On 3/19/19 4:26 AM, Ley Foon Tan wrote:
> >>> On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:
> 
>  On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> > Move SDRAM size check to SDRAM driver. sdram_calculate_size()
> > is called in SDRAM initialization already, avoid calling
> > twice in size check function.
> >
> > Signed-off-by: Ley Foon Tan 
> > ---
> >  arch/arm/mach-socfpga/spl_s10.c | 11 ---
> >  drivers/ddr/altera/sdram_s10.c  | 15 +++
> >  2 files changed, 15 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/spl_s10.c 
> > b/arch/arm/mach-socfpga/spl_s10.c
> > index a3db20a819..a141ffe82a 100644
> > --- a/arch/arm/mach-socfpga/spl_s10.c
> > +++ b/arch/arm/mach-socfpga/spl_s10.c
> > @@ -181,17 +181,6 @@ void board_init_f(ulong dummy)
> >   hang();
> >   }
> >
> > - gd->ram_size = sdram_calculate_size();
> > - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
> > -
> > - /* Sanity check ensure correct SDRAM size specified */
> > - debug("DDR: Running SDRAM size sanity check\n");
> > - if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> > - puts("DDR: SDRAM size check failed!\n");
> > - hang();
> > - }
> > - debug("DDR: SDRAM size check passed!\n");
> > -
> >   mbox_init();
> >
> >  #ifdef CONFIG_CADENCE_QSPI
> > diff --git a/drivers/ddr/altera/sdram_s10.c 
> > b/drivers/ddr/altera/sdram_s10.c
> > index a48567c109..8895813440 100644
> > --- a/drivers/ddr/altera/sdram_s10.c
> > +++ b/drivers/ddr/altera/sdram_s10.c
> > @@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void)
> >SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, 
> > false);
> >  }
> >
> > +static void sdram_size_check(void)
> > +{
> > + /* Sanity check ensure correct SDRAM size specified */
> > + debug("DDR: Running SDRAM size sanity check\n");
> > + if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> > + puts("DDR: SDRAM size check failed!\n");
> > + hang();
> > + }
> > + debug("DDR: SDRAM size check passed!\n");
> > +}
> > +
> >  /**
> >   * sdram_mmr_init_full() - Function to initialize SDRAM MMR
> >   *
> > @@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused)
> >   else
> >   gd->ram_size = size;
> >
> > + printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
> 
>  Is the type cast needed?
> >>> Yes, otherwise there is warning.
> >>
> >> Maybe the warning is justified and needs to be fixed instead of hidden ?
> >>
> >
> > drivers/ddr/altera/sdram_s10.c:461:16: warning: format ‘%d’ expects
> > argument of type ‘int’, but argument 2 has type ‘phys_size_t {aka
> > volatile long long unsigned int}’ [-Wformat=]
> >   printf("DDR: %d MiB\n", gd->ram_size >> 20);
> >~^ ~~
>
> That's %lld then.
Same as %llx, tiny printf in SPL doesn't support %ll.

Regards
Ley Foon
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Re: [U-Boot] [PATCH 1/1] efi_loader: correct parameter size in efi_allocate_pool

[Takahiro Akashi]

On Tue, Mar 19, 2019 at 07:59:37AM +0100, Heinrich Schuchardt wrote:
> On 3/19/19 1:19 AM, Takahiro Akashi wrote:
> > On Mon, Mar 18, 2019 at 08:32:23PM +0100, Heinrich Schuchardt wrote:
> >> efi_allocate_pages() expects a (uint64_t *) pointer to pass the address of
> >> the assigned memory. If we pass the address of a pointer here, an illegal
> >> memory access occurs on 32bit systems.
> >>
> >> Fixes: 282a06cbcae8 ("efi_loader: Expose U-Boot addresses in memory map
> >> for sandbox")
> >> Signed-off-by: Heinrich Schuchardt 
> >> ---
> >>  lib/efi_loader/efi_memory.c | 5 +++--
> >>  1 file changed, 3 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
> >> index ebd2b36c03..55622d2fb4 100644
> >> --- a/lib/efi_loader/efi_memory.c
> >> +++ b/lib/efi_loader/efi_memory.c
> >> @@ -440,6 +440,7 @@ efi_status_t efi_free_pages(uint64_t memory, 
> >> efi_uintn_t pages)
> >>  efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void 
> >> **buffer)
> >>  {
> >>efi_status_t r;
> >> +  u64 addr;
> >>struct efi_pool_allocation *alloc;
> >>u64 num_pages = efi_size_in_pages(size +
> >>  sizeof(struct efi_pool_allocation));
> >> @@ -453,9 +454,9 @@ efi_status_t efi_allocate_pool(int pool_type, 
> >> efi_uintn_t size, void **buffer)
> >>}
> >>  
> >>r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, pool_type, num_pages,
> >> - (uint64_t *));
> > 
> > I wonder why efi_allocate_pages() doesn't expect (void **) for the fourth
> > argument.
> 
> efi_allocate_pages implements the AllocatePages() boot time service. The
> UEFI spec mandates that the parameter is of type EFI_PHYSICAL_ADDRESS *
> i.e. u64 *.

But allocate_pool() takes "void **" for the third argument. Why?

> > If this is because the type of the argument is a pointer to "physical 
> > address,"
> > 
> >> -
> >> + );
> >>if (r == EFI_SUCCESS) {
> >> +  alloc = (struct efi_pool_allocation *)(uintptr_t)addr;
> > 
> > we should use map_sysmem() here.
> 
> This would create a bug on the sandbox.
> 
> map_sysmem() converts an address from the sandbox virtual address space
> to the address space that can be used by EFI binaries.
> 
> AllocatePool() and AllocatePages() both refer to the same address space.
> 
> Cf. commit 49759743bf09 ("efi_loader: eliminate sandbox addresses")

I don't know the case of sandbox, but What I have in mind is
LPAE, that is, the system have >32-bit physical address space,
but cpu can only access it via 32-bit pointer.

Thanks,
-Takahiro Akashi

> Best regards
> 
> Heinrich
> 
> > 
> > Thanks,
> > -Takahiro Akashi
> > 
> >>alloc->num_pages = num_pages;
> >>*buffer = alloc->data;
> >>}
> >> -- 
> >> 2.20.1
> >>
> > 
> 
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[U-Boot] [PATCH v4 1/1] efi_loader: bootmgr: support BootNext and BootCurrent variable behavior

[AKASHI Takahiro]

See UEFI v2.7, section 3.1.2 for details of the specification.

With efidebug command, you can run any EFI boot option as follows:
  => efi boot add 1 SHELL ...
  => efi boot add 2 HELLO ...
  => efi boot order 1 2
  => efi bootmgr
 (starting SHELL ...)

  => efi boot next 2
  => efi bootmgr
 (starting HELLO ...)
  => env print -e
  
  BootCurrent: {boot,run}(blob)
  :  02 00..
  BootOrder: {boot,run}(blob)
  :  01 00 02 00  

Signed-off-by: AKASHI Takahiro 
---
 lib/efi_loader/efi_bootmgr.c | 51 +---
 1 file changed, 47 insertions(+), 4 deletions(-)

diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 417016102b48..4fccadc5483d 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -141,6 +141,7 @@ static void *try_load_entry(uint16_t n, struct 
efi_device_path **device_path,
efi_deserialize_load_option(, load_option);
 
if (lo.attributes & LOAD_OPTION_ACTIVE) {
+   u32 attributes;
efi_status_t ret;
 
debug("%s: trying to load \"%ls\" from %pD\n",
@@ -151,6 +152,16 @@ static void *try_load_entry(uint16_t n, struct 
efi_device_path **device_path,
if (ret != EFI_SUCCESS)
goto error;
 
+   attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
+EFI_VARIABLE_RUNTIME_ACCESS;
+   size = sizeof(n);
+   ret = EFI_CALL(efi_set_variable(
+   L"BootCurrent",
+   (efi_guid_t *)_global_variable_guid,
+   attributes, size, ));
+   if (ret != EFI_SUCCESS)
+   goto error;
+
printf("Booting: %ls\n", lo.label);
efi_dp_split_file_path(lo.file_path, device_path, file_path);
}
@@ -162,21 +173,53 @@ error:
 }
 
 /*
- * Attempt to load, in the order specified by BootOrder EFI variable, the
- * available load-options, finding and returning the first one that can
- * be loaded successfully.
+ * Attempt to load from BootNext or in the order specified by BootOrder
+ * EFI variable, the available load-options, finding and returning
+ * the first one that can be loaded successfully.
  */
 void *efi_bootmgr_load(struct efi_device_path **device_path,
   struct efi_device_path **file_path)
 {
-   uint16_t *bootorder;
+   u16 bootnext, *bootorder;
efi_uintn_t size;
void *image = NULL;
int i, num;
+   efi_status_t ret;
 
bs = systab.boottime;
rs = systab.runtime;
 
+   /* BootNext */
+   bootnext = 0;
+   size = sizeof(bootnext);
+   ret = EFI_CALL(efi_get_variable(L"BootNext",
+   (efi_guid_t *)_global_variable_guid,
+   NULL, , ));
+   if (ret == EFI_SUCCESS || ret == EFI_BUFFER_TOO_SMALL) {
+   /* BootNext does exist here */
+   if (ret == EFI_BUFFER_TOO_SMALL || size != sizeof(u16))
+   printf("BootNext must be 16-bit integer\n");
+
+   /* delete BootNext */
+   ret = EFI_CALL(efi_set_variable(
+   L"BootNext",
+   (efi_guid_t *)_global_variable_guid,
+   0, 0, ));
+
+   /* load BootNext */
+   if (ret == EFI_SUCCESS) {
+   if (size == sizeof(u16)) {
+   image = try_load_entry(bootnext, device_path,
+  file_path);
+   if (image)
+   return image;
+   }
+   } else {
+   printf("Deleting BootNext failed\n");
+   }
+   }
+
+   /* BootOrder */
bootorder = get_var(L"BootOrder", _global_variable_guid, );
if (!bootorder) {
printf("BootOrder not defined\n");
-- 
2.20.1

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[U-Boot] [PATCH v4 0/1] efi_loader: support BootNext and BootCurrent

[AKASHI Takahiro]

This patch was originally posted as a single one, but then was
merged in my "run -e." Now I would like to post it on its own.

With this patch, EFI Boot Manager will handles BootNext and BootCurrent
variable as UEFI specification describes.

Changes in v4 (Mar 20, 2019)
* strictly check the size of BootNext

Changes in v3 (Mar 8, 2019)
* add error messages around BootNext
* delete BootNext anyway when processing BootOrder

Changes in v2 (Mar 5, 2019)
* extract this patch from my "run -e" patch set
* use efi_[get|set]_variable instead of 'rs->*'
* add EFI_CALL
* cosmetic changes

AKASHI Takahiro (1):
  efi_loader: bootmgr: support BootNext and BootCurrent variable
behavior

 lib/efi_loader/efi_bootmgr.c | 51 +---
 1 file changed, 47 insertions(+), 4 deletions(-)

-- 
2.20.1

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[U-Boot] [PATCH 2/2] fastboot: getvar_partition_type: Return 'raw' when FS-unaware

[Eugeniu Rosca]

Only a handful of Android/fastboot partitions (e.g. /system,
/vendor, /userdata) have filesystem:

host $> fastboot getvar partition-type:userdata
partition-type:userdata: ext4
Finished. Total time: 0.013s

Most of them (/misc, /pstore, /vbmeta, /dtb{o}, /boot, etc) don't.
And for the latter fastboot reports:

host $> fastboot getvar partition-type:misc
getvar:partition-type:misc FAILED (remote: failed to set partition)
Finished. Total time: 0.219s

Rather than creating pointless worries via error reporting, tell
the users they are dealing with a 'raw' partition:

host $> fastboot getvar partition-type:misc
partition-type:misc: raw
Finished. Total time: 0.017s

Fixes: f73a7df984a9 ("net: fastboot: Merge AOSP UDP fastboot")
Signed-off-by: Eugeniu Rosca 
---
 drivers/fastboot/fb_getvar.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
index 28e3e2fa1619..beadf7f98e5d 100644
--- a/drivers/fastboot/fb_getvar.c
+++ b/drivers/fastboot/fb_getvar.c
@@ -154,7 +154,7 @@ static void getvar_partition_type(char *part_name, char 
*response)
if (r >= 0) {
r = fs_set_blk_dev_with_part(dev_desc, r);
if (r < 0)
-   fastboot_fail("failed to set partition", response);
+   fastboot_okay("raw", response);
else
fastboot_okay(fs_get_type_name(), response);
}
-- 
2.21.0

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[U-Boot] [PATCH 1/2] fastboot: getvar_partition_{type, size}: Sanitize arguments

[Eugeniu Rosca]

Correct usage of "fastboot getvar_partition_{type,size}" is:

host $> fastboot getvar  partition-size:misc
partition-size:misc: 0x0400
Finished. Total time: 0.214s

When the partition name is omitted, current behavior is:

host $> fastboot getvar  partition-size
getvar:partition-size FAILED (remote: partition not found)
finished. total time: 0.005s
host $> fastboot getvar  partition-size:
getvar:partition-size: FAILED (remote: partition not found)
finished. total time: 0.006s
host $> fastboot getvar  partition-type
getvar:partition-type FAILED (remote: partition not found)
finished. total time: 0.005s
host $> fastboot getvar  partition-type:
getvar:partition-type: FAILED (remote: partition not found)
finished. total time: 0.006s

Tell the user the real cause of command failure:

host $> fastboot getvar  partition-size
getvar:partition-size FAILED (remote: missing partition name)
Finished. Total time: 0.003s
host $> fastboot getvar  partition-size:
getvar:partition-size: FAILED (remote: missing partition name)
Finished. Total time: 0.003s
host $> fastboot getvar  partition-type
getvar:partition-type FAILED (remote: missing partition name)
Finished. Total time: 0.003s
host $> fastboot getvar  partition-type:
getvar:partition-type: FAILED (remote: missing partition name)
Finished. Total time: 0.003s

Fixes: f73a7df984a9 ("net: fastboot: Merge AOSP UDP fastboot")
Signed-off-by: Eugeniu Rosca 
---
 drivers/fastboot/fb_getvar.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
index 4d264c985d7e..28e3e2fa1619 100644
--- a/drivers/fastboot/fb_getvar.c
+++ b/drivers/fastboot/fb_getvar.c
@@ -144,6 +144,11 @@ static void getvar_partition_type(char *part_name, char 
*response)
struct blk_desc *dev_desc;
disk_partition_t part_info;
 
+   if (!part_name || !strcmp(part_name, "")) {
+   fastboot_fail("missing partition name", response);
+   return;
+   }
+
r = fastboot_mmc_get_part_info(part_name, _desc, _info,
   response);
if (r >= 0) {
@@ -162,6 +167,11 @@ static void getvar_partition_size(char *part_name, char 
*response)
int r;
size_t size;
 
+   if (!part_name || !strcmp(part_name, "")) {
+   fastboot_fail("missing partition name", response);
+   return;
+   }
+
 #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
struct blk_desc *dev_desc;
disk_partition_t part_info;
-- 
2.21.0

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Re: [U-Boot] Pull request: u-boot-net.git master

[Tom Rini]

On Tue, Mar 12, 2019 at 01:15:46PM -0500, Joe Hershberger wrote:

> Hi Tom,
> 
> These patches passed the CI build here: 
> https://travis-ci.org/jhershbe/u-boot/builds/501807294
> 
> The following changes since commit 2e8092d94f40a5692baf3ec768ce3216a7bf032a:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2019-03-11 
> 15:48:57 -0400)
> 
> are available in the git repository at:
> 
> 
>   git://git.denx.de/u-boot-net.git master
> 
> for you to fetch changes up to 85f05f72bacc2d047731fc64801e4f6b34cf:
> 
>   net: phy: aquantia: Set only autoneg on in register 4.c441 (2019-03-12 
> 13:13:37 -0500)
> 

NAK.  One of:
The first bad commit could be any of:
30b2ca2e0fa274b875bb56f541b7dd33ce93c1d1
8860e1563f38d16f7ae29053018cd445c0fa111d
ebb5027d69196dd83fd0fa5bd91fca07acfd77be
09e0a36497c84273e5b22488d5af01bf0ba17469
841b9df209e37fe1bfefa5f44e837a0ad497443f
15e67d1cdc7258c0c07ad1fd6c2818f7e9f52447
7aadf5134f2f5771689d0657b69875d0a464859d
d35488518f3c16d305092c816a5129f45a0b62d7
Breaks am335x_evm ethernet:
18:39:52 => => dhcp
18:39:52 ethernet@4a10 Waiting for PHY auto negotiation to
complete... done
18:39:52 link up on port 0, speed 1000, full duplex
18:39:52 BOOTP broadcast 1
18:39:52 BOOTP broadcast 2
18:39:52 BOOTP broadcast 3
18:39:52 BOOTP broadcast 4
18:39:52 BOOTP broadcast 5
18:39:52 BOOTP broadcast 6
18:39:52 BOOTP broadcast 7
18:39:52 BOOTP broadcast 8
18:39:52 BOOTP broadcast 9
18:39:52 BOOTP broadcast 10
18:39:52 BOOTP broadcast 11
18:39:52 BOOTP broadcast 12
18:39:52 BOOTP broadcast 13
18:39:52 BOOTP broadcast 14
18:39:52 BOOTP broadcast 15
18:39:52 BOOTP broadcast 16
18:39:52 BOOTP broadcast 17

-- 
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Re: [U-Boot] [PULL] u-boot-socfpga/master

[Tom Rini]

On Mon, Mar 18, 2019 at 04:08:48AM +0100, Marek Vasut wrote:

> The following changes since commit 9659eb46af6249b6e4b3712e60a1eb2e87fc48a1:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-samsung (2019-03-14
> 11:37:11 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-socfpga.git master
> 
> for you to fetch changes up to 92a47459bb85ba3e835b11ddbdcdfb571280614f:
> 
>   arm: socfpga: make SPL_TEXT_BASE overridable (2019-03-16 13:30:09 +0100)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PULL] u-boot-usb/master

[Tom Rini]

On Mon, Mar 18, 2019 at 04:08:18AM +0100, Marek Vasut wrote:

> The following changes since commit 9659eb46af6249b6e4b3712e60a1eb2e87fc48a1:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-samsung (2019-03-14
> 11:37:11 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to f402d268e8e17e9d6d1d9bf8a8b1f6e0b07718ef:
> 
>   fastboot: common: fix default fastboot_boot on 64-bit (2019-03-16
> 13:29:43 +0100)
> 

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH 1/1] efi_selftest: fix test_hii_string_get_string()

[Heinrich Schuchardt]

The check testing the string result of get_string() returned the wrong
result. The result was ignored.

Use efi_st_strcmp_16_8() for the string comparison.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_selftest/efi_selftest_hii.c | 17 -
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/lib/efi_selftest/efi_selftest_hii.c 
b/lib/efi_selftest/efi_selftest_hii.c
index 8a0b3bc3536..f4b70f79508 100644
--- a/lib/efi_selftest/efi_selftest_hii.c
+++ b/lib/efi_selftest/efi_selftest_hii.c
@@ -783,19 +783,10 @@ static int test_hii_string_get_string(void)
goto out;
}

-#if 1
-   u16 *c1, *c2;
-
-   for (c1 = string, c2 = L"Japanese"; *c1 == *c2; c1++, c2++)
-   ;
-   if (!*c1 && !*c2)
-   result = EFI_ST_SUCCESS;
-   else
-   result = EFI_ST_FAILURE;
-#else
-   /* TODO: %ls */
-   efi_st_printf("got string is %s (can be wrong)\n", string);
-#endif
+   if (efi_st_strcmp_16_8(string, "Japanese")) {
+   efi_st_error("get_string returned incorrect string\n");
+   goto out;
+   }

result = EFI_ST_SUCCESS;

--
2.20.1

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Re: [U-Boot] [PATCH 5/6] spl: support using full malloc with SYS_MALLOC_F_LEN

[Simon Goldschmidt]

Hi Simon,

you were replying to v1 where v2 has already been sent. However, this 
patch hasn't changed, so I'm commenting here.


Am 19.03.2019 um 02:24 schrieb Simon Glass:

Hi Simon,

On Tue, 12 Mar 2019 at 05:35, Simon Goldschmidt
 wrote:


Some platforms (like socfpga A10) need a big hep before SDRAM is available
(e.g. because FAT is used). For such platforms, simple_malloc is often not
a good option as it does not support freeing memory. These platforms often
use the non-Kconfig defines CONFIG_SYS_SPL_MALLOC_START (and its SIZE).

This patch allows enabling CONFIG_SPL_SYS_MALLOC_F_LEN while leaving
CONFIG_SPL_SYS_MALLOC_SIMPLE disabled. In this case, the full malloc heap
is made available as early as the simple_malloc heap would be normally.

This way, platforms can drop the non-Kconfig options to set up the full
heap and rely on the same automatically calculated heap allocation used
for simple heap.

Signed-off-by: Simon Goldschmidt 
---

  common/spl/spl.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 88d4b8a9bf..b89340eb27 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -383,8 +383,13 @@ static int spl_common_init(bool setup_malloc)
  #ifdef CONFIG_MALLOC_F_ADDR
 gd->malloc_base = CONFIG_MALLOC_F_ADDR;
  #endif
+#if CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)


Can we use if() instead of #if here?


Yes, that should work. Noted for v3.




 gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN);
 gd->malloc_ptr = 0;
+#else
+   mem_malloc_init(gd->malloc_base, CONFIG_VAL(SYS_MALLOC_F_LEN));
+   gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+#endif
 }
  #endif
 ret = bootstage_init(true);
--
2.17.1



Also I feel some updates should be made to the README, or perhaps Kconfig help.


Yes, you're right. Honestly, I didn't want to go through all the 
documentation mess unless getting at least some slightly positive 
feedback to this. Searching the readme files and Kconfig help to get 
them consistent is probably more work than coding these patches :-)


Regards,
Simon
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Re: [U-Boot] [PATCH v3 3/3] poplar: enable Ethernet driver support

[Joe Hershberger]

On Sun, Mar 10, 2019 at 3:53 AM Shawn Guo  wrote:
>
> The 'phy' reset of gmac device in kernel device tree is not generic
> enough for u-boot to use, so we need to overwrite the 'resets' property
> as needed.  With this device tree fixup and poplar_defconfig changes,
> Ethernet starts working on Poplar board.
>
> Signed-off-by: Shawn Guo 
> Reviewed-by: Igor Opaniuk 
> ---
>  arch/arm/dts/hi3798cv200-u-boot.dtsi | 14 ++
>  configs/poplar_defconfig |  3 +++
>  2 files changed, 17 insertions(+)
>
> diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi 
> b/arch/arm/dts/hi3798cv200-u-boot.dtsi
> index 7844c5208c5d..2ca943f64e59 100644
> --- a/arch/arm/dts/hi3798cv200-u-boot.dtsi
> +++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi
> @@ -8,7 +8,15 @@
>   * (C) Copyright 2017 Jorge Ramirez-Ortiz 
>   */
>
> +#include 

Where does this file come from?

> +
>   {
> +   rst: reset-controller@8a22000 {
> +   compatible = "hisilicon,hi3798cv200-reset";
> +   reg = <0x8a22000 0x1000>;

Would it not be reasonable to include the "0xcc" from below in this
address instead of adding them at runtime?


> +   #reset-cells = <3>;
> +   };
> +
> usb2: ehci@989 {
> compatible = "generic-ehci";
> reg = <0x989 0x100>;
> @@ -16,6 +24,12 @@
> };
>  };
>
> + {
> +   resets = < 0xcc 9  HISI_RESET_ACTIVE_HIGH>,
> +< 0xcc 11 HISI_RESET_ACTIVE_HIGH>,
> +< 0xcc 13 HISI_RESET_ACTIVE_LOW>;
> +};
> +
>   {
> clock = <7500>;
> status = "okay";
> diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig
> index 81bd3702e42a..76ab5eb70e7e 100644
> --- a/configs/poplar_defconfig
> +++ b/configs/poplar_defconfig
> @@ -19,6 +19,9 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
>  CONFIG_DM_MMC=y
>  CONFIG_MMC_DW=y
>  CONFIG_MMC_DW_K3=y
> +CONFIG_DM_ETH=y
> +CONFIG_HIGMACV300_ETH=y
> +CONFIG_RESET_HISILICON=y
>  CONFIG_USB=y
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_EHCI_GENERIC=y
> --
> 2.18.0
>
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Re: [U-Boot] [PATCH v3 1/3] reset: add reset driver for HiSilicon platform

[Joe Hershberger]

Hi Shawn,

On Sun, Mar 10, 2019 at 3:53 AM Shawn Guo  wrote:
>
> It adds a Driver Model compatible reset driver for HiSlicon platform.
> The driver implements a custom .of_xlate function, and uses .data field
> as reset register offset and .id field as bit shift.
>
> Signed-off-by: Shawn Guo 
> Reviewed-by: Igor Opaniuk 
> ---
>  drivers/reset/Kconfig   |   6 ++
>  drivers/reset/Makefile  |   1 +
>  drivers/reset/reset-hisilicon.c | 111 
>  3 files changed, 118 insertions(+)
>  create mode 100644 drivers/reset/reset-hisilicon.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index a81e76769604..6ec6f39c85f0 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -121,4 +121,10 @@ config RESET_SUNXI
>   This enables support for common reset driver for
>   Allwinner SoCs.
>
> +config RESET_HISILICON
> +   bool "Reset controller driver for HiSilicon SoCs"
> +   depends on DM_RESET
> +   help
> + Support for reset controller on HiSilicon SoCs.
> +
>  endmenu
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 4fad7d412985..7fec75bb4923 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -19,3 +19,4 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o
>  obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
>  obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
>  obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> +obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
> diff --git a/drivers/reset/reset-hisilicon.c b/drivers/reset/reset-hisilicon.c
> new file mode 100644
> index ..7b0c11fbc82e
> --- /dev/null
> +++ b/drivers/reset/reset-hisilicon.c
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019, Linaro Limited
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 

Where does this file come from?


> +#include 
> +
> +struct hisi_reset_priv {
> +   void __iomem *base;
> +};
> +
> +static int hisi_reset_deassert(struct reset_ctl *rst)
> +{
> +   struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
> +   u32 offset = rst->data & 0x;
> +   u32 shift = rst->data >> 16;
> +   int polarity = rst->id;
> +   u32 val;
> +
> +   val = readl(priv->base + offset);
> +   if (polarity == HISI_RESET_ACTIVE_HIGH)
> +   val &= ~BIT(shift);
> +   else
> +   val |= BIT(shift);
> +   writel(val, priv->base + offset);
> +
> +   return 0;
> +}
> +
> +static int hisi_reset_assert(struct reset_ctl *rst)
> +{
> +   struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
> +   u32 offset = rst->data & 0x;
> +   u32 shift = rst->data >> 16;
> +   int polarity = rst->id;
> +   u32 val;
> +
> +   val = readl(priv->base + offset);
> +   if (polarity == HISI_RESET_ACTIVE_HIGH)
> +   val |= BIT(shift);
> +   else
> +   val &= ~BIT(shift);
> +   writel(val, priv->base + offset);
> +
> +   return 0;
> +}
> +
> +static int hisi_reset_free(struct reset_ctl *rst)
> +{
> +   return 0;
> +}
> +
> +static int hisi_reset_request(struct reset_ctl *rst)
> +{
> +   return 0;
> +}
> +
> +static int hisi_reset_of_xlate(struct reset_ctl *rst,
> +  struct ofnode_phandle_args *args)
> +{
> +   if (args->args_count != 3) {
> +   debug("Invalid args_count: %d\n", args->args_count);
> +   return -EINVAL;
> +   }
> +
> +   /*
> +* Encode register offset in .data[15..0] and bit shift in
> +* .data[31..16], and use .id field as polarity.
> +*/

I don't like going through these contortions to avoid changing the
struct in reset.h

I think you should add a "polarity" field to that struct and instead
of defining a specific constant for HISI_RESET_ACTIVE_HIGH, instead
make a generic one that everyone can use, such as the ASSERT_CLEAR and
friends in Linux.

I also hope you can get rid of the register offset and either include
it in the DT base address if it is something that needs to be selected
or simply make a #define for the 0xCC for what the register is called
and go from there. If both are not acceptable, I think it makes sense
to use "data" as the register.

> +   rst->data = (args->args[1] << 16) | (args->args[0] & 0x);
> +   rst->id = args->args[2];

I think "id" should be used to hold the "shift" or bit number of the reset.




> +
> +   return 0;
> +}
> +
> +static const struct reset_ops hisi_reset_reset_ops = {
> +   .of_xlate = hisi_reset_of_xlate,
> +   .request = hisi_reset_request,
> +   .free = hisi_reset_free,
> +   .rst_assert = hisi_reset_assert,
> +   .rst_deassert = hisi_reset_deassert,
> +};
> +
> +static const struct udevice_id hisi_reset_ids[] = {
> +   { .compatible = "hisilicon,hi3798cv200-reset" },
> +   { }
> +};
> +
> +static int hisi_reset_probe(struct udevice *dev)
> +{
> + 

Re: [U-Boot] [PATCH v3 2/3] net: add higmacv300 Ethernet driver for HiSilicon platform

[Joe Hershberger]

On Sun, Mar 10, 2019 at 3:52 AM Shawn Guo  wrote:
>
> It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon
> SoCs like Hi3798CV200.  It's based on a downstream U-Boot driver, but
> quite a lot of code gets rewritten and cleaned up to adopt driver model
> and PHY API.
>
> Signed-off-by: Shawn Guo 
> ---

Acked-by: Joe Hershberger 
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[U-Boot] [PATCH 1/1] efi_loader: remove superfluous check in efi_setup_loaded_image()

[Heinrich Schuchardt]

It does not make any sense to check if a pointer is NULL if we have
dereferenced it before.

Fixes Coverity CID 185827

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_boottime.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index bd8b8a17ae7..4fc550d9f37 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1581,10 +1581,8 @@ efi_status_t efi_setup_loaded_image(struct 
efi_device_path *device_path,
goto failure;
 #endif

-   if (info_ptr)
-   *info_ptr = info;
-   if (handle_ptr)
-   *handle_ptr = obj;
+   *info_ptr = info;
+   *handle_ptr = obj;

return ret;
 failure:
--
2.20.1

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[U-Boot] [PATCH 1/1] efi_loader: memory leak in efi_dump_single_var()

[Heinrich Schuchardt]

A misplaced return statement lead to a memory leak in
efi_dump_single_var().

Fixes Coverity CID 185829

Signed-off-by: Heinrich Schuchardt 
---
 cmd/nvedit_efi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c
index ca32566a615..e65b38dbf39 100644
--- a/cmd/nvedit_efi.c
+++ b/cmd/nvedit_efi.c
@@ -80,7 +80,6 @@ static void efi_dump_single_var(u16 *name, efi_guid_t *guid)
printf(", DataSize = 0x%zx\n", size);
print_hex_dump("", DUMP_PREFIX_OFFSET, 16, 1, data, size, true);

-   return;
 out:
free(data);
 }
--
2.20.1

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[U-Boot] [PATCH 1/1] efi_loader: missing return in efi_get_next_variable_name()

[Heinrich Schuchardt]

Add a missing return statement in efi_get_next_variable_name().

Fixes Coverity CID 185834

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_variable.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index e0d7f5736db..699f4184d93 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -335,7 +335,7 @@ efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t 
*variable_name_size,
EFI_ENTRY("%p \"%ls\" %pUl", variable_name_size, variable_name, vendor);

if (!variable_name_size || !variable_name || !vendor)
-   EFI_EXIT(EFI_INVALID_PARAMETER);
+   return EFI_EXIT(EFI_INVALID_PARAMETER);

if (variable_name[0]) {
/* check null-terminated string */
--
2.20.1

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Re: [U-Boot] [PATCH v2 15/15] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Stephen Warren]

On 3/18/19 5:24 PM, Thierry Reding wrote:

From: Thierry Reding 

The Jetson Nano Developer Kit is a Tegra X1 based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4 GB
of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot
used for storage.

HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity.

A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.



diff --git a/arch/arm/dts/tegra210-p3450-.dts 
b/arch/arm/dts/tegra210-p3450-.dts



+/ {
+   model = "NVIDIA Jetson Nano Development Kit";


Technically, it's marketed as a "Developer Kit", not a "Development Kit".


+   aliases {
+   i2c0 = "/i2c@7000d000";
+   i2c2 = "/i2c@7000c400";
+   i2c3 = "/i2c@7000c500";
+   i2c4 = "/i2c@7000c700";
+   sdhci0 = "/sdhci@700b0600";
+   sdhci1 = "/sdhci@700b";


SKU 0 (the - in the board name) only has 1 SD card slot and no eMMC.

I personally would prefer a different build of U-Boot for each SKU (or 
at least a separate DT), so that each U-Boot exposes exactly what's 
present, not the union of all SKUs. That said, I know there's resistance 
to that in our downstream builds of U-Boot for L4T.



diff --git a/arch/arm/mach-tegra/tegra210/Kconfig 
b/arch/arm/mach-tegra/tegra210/Kconfig
+config TARGET_P3450_
+   bool "NVIDIA Jetson Nano Development Kit"


Developer.


diff --git a/board/nvidia/p3450-/pinmux-config-p3450-.h 
b/board/nvidia/p3450-/pinmux-config-p3450-.h
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py p3450-".
+ */


I'd like to see the pinmux-scripts patches. And some questions there:
- Confirm this is for the A02 board revision.
- Confirm which pinmux spreadsheet version the data came from.
- Does this copy of the file delete the GPIO setup entries that are 
different between HW A01 and A02, so it will run on both boards, or does 
it contain everything so that it's only valid for A02 HW?


We are only shipping A02 publicly, so I think it makes sense to include 
the complete pinmux table here, and let internal NVIDIA users of A01 
just use only the downstream code.



diff --git a/include/configs/p3450-.h b/include/configs/p3450-.h



+#define CONFIG_PREBOOT
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+   "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
+   "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
+   "source ${scriptaddr}; " \
+   "fi\0"


We might want to hold off on that until we've discussed what we want to 
do for preboot scripts and environment in L4T, so that we don't 
introduce some downstream/upstream incompatibility split here?

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Re: [U-Boot] [PATCH] p2371-2180: Build position independent binary

[Stephen Warren]

On 3/19/19 6:12 AM, Thierry Reding wrote:

On Mon, Mar 18, 2019 at 12:31:32PM -0600, Stephen Warren wrote:

On 3/8/19 1:10 PM, Thierry Reding wrote:

From: Thierry Reding 

In order to support chainloading of U-Boot by an earlier bootloader,
make sure the binary is position independent, so that the earlier boot-
loader can relocate it if necessary.


Why not enable this for all 64-bit Tegra? They're all booted the exact same
way at least with recent L4T builds.


Yeah, I think that would make sense.


Also, U-Boot is typically linked to the address that cboot loads it to, and
cboot typically always loads to precisely that address. I'm not sure why
this patch is required.


I encountered this issue when I was trying to chainload U-Boot from
cboot on Jetson TX1. It seems like your above comment is no longer true,
though I suppose that could just mean that the link address for U-Boot
has become stale?


Looks like the upstream CONFIG_SYS_TEXT_BASE is indeed stale relative to 
the latest L4T builds:


Upstream:
Jetson TX1: CONFIG_SYS_TEXT_BASE=0x8011
Jetson TX2: CONFIG_SYS_TEXT_BASE=0x8008

L4T r32.1:
Jetson TX1: #define CONFIG_SYS_TEXT_BASE0x8008
Jetson TX2: #define CONFIG_SYS_TEXT_BASE0x8008


That said, it don't think it harms anything, so I'm fine with it being
applied.


I suppose there's a bit of extra code to do the indirect jumps, but
overall U-Boot seems to work well and not noticeably slower if this is
enabled. Might be nice for extra flexibility and to avoid any surprises
if we ever end up loading U-Boot to a location other than where it was
liked to.

My understanding is that this could happen on Tegra186 if cboot detects
bad memory blocks in the area where U-Boot was meant to be loaded to. I
guess this doesn't apply to earlier chips, but perhaps it's good to have
it there for consistency anyway.


Yes, this could happen on Jetson TX2i at least.
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Re: [U-Boot] [PATCH v2 6/6] arm: socfpga: a10: move SPL stack size to Kconfig

[Simon Goldschmidt]

Am 19.03.2019 um 17:19 schrieb Chee, Tien Fong:

On Fri, 2019-03-15 at 21:13 +0100, Simon Goldschmidt wrote:

Instead of fixing the SPL stack to 64 KiB in the board config header
via
CONFIG_SYS_SPL_MALLOC_SIZE, let's just use
CONFIG_SPL_SYS_MALLOC_F_LEN
in the defconfig.

This also has the advandage that it removes sub-mach specific ifdefs
in
socfpga_common.h.

Signed-off-by: Simon Goldschmidt 
---

Hi Simon,

I found the culprit in patch[5], you cannot put mem_malloc_init in
spl_common_init function because spl_common_init would be called in
board_init_f, then board_init_f would call mem_malloc_init,
mem_malloc_init would store start and end addresses to few global
variables such as mem_malloc_start, mem_malloc_end and mem_malloc_brk.
By that time, global variables are unavailable yet.


Thanks for testing. Patch 2/6 should make sure global variables are 
available in board_init_f by clearing bss *before* calling that 
function, not *after* calling it. Because technicaly, global variables 
are always available for a10-SPL as they are located in SRAM. They only 
got cleared after board_init_f...


Which gets me to my error: I forgot to enable the newly added 
CONFIG_SPL_CLEAR_BSS_F in this patch. Could you probably try again with 
CONFIG_SPL_CLEAR_BSS_F enabled? That would be great!


Regards,
Simon



Thanks.
TF



Changes in v2: None

  configs/socfpga_arria10_defconfig |  1 +
  include/configs/socfpga_common.h  | 14 --
  2 files changed, 1 insertion(+), 14 deletions(-)

diff --git a/configs/socfpga_arria10_defconfig
b/configs/socfpga_arria10_defconfig
index f321a0ac3b..8d0479cc05 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
  CONFIG_ARCH_SOCFPGA=y
  CONFIG_SYS_TEXT_BASE=0x0140
  CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1
  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
  CONFIG_SPL=y
  CONFIG_IDENT_STRING="socfpga_arria10"
diff --git a/include/configs/socfpga_common.h
b/include/configs/socfpga_common.h
index 181af9b646..16c83900c3 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -251,16 +251,6 @@ unsigned int
cm_get_qspi_controller_clk_hz(void);
  #define CONFIG_SPL_TEXT_BASE  CONFIG_SYS_INIT_RAM_ADDR
  #define CONFIG_SPL_MAX_SIZE   CONFIG_SYS_INIT_RAM_SIZE
  
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)

-/* SPL memory allocation configuration, this is for FAT
implementation */
-#ifndef CONFIG_SYS_SPL_MALLOC_START
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001
-#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_INIT_RAM_SIZE
- \
-    CONFIG_SYS_SPL_MALLOC_SIZE
+ \
-    CONFIG_SYS_INIT_RAM_ADDR)
-#endif
-#endif
-
  /* SPL SDMMC boot support */
  #ifdef CONFIG_SPL_MMC_SUPPORT
  #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
@@ -294,11 +284,7 @@ unsigned int
cm_get_qspi_controller_clk_hz(void);
  /*
   * Stack setup
   */
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  #define CONFIG_SPL_STACK  CONFIG_SYS_INIT_SP_ADDR
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SPL_STACK   CONFIG_SYS_SPL_MALLOC_START
-#endif
  
  /* Extra Environment */

  #ifndef CONFIG_SPL_BUILD


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Re: [U-Boot] [PATCH v2 6/6] arm: socfpga: a10: move SPL stack size to Kconfig

[Chee, Tien Fong]

On Fri, 2019-03-15 at 21:13 +0100, Simon Goldschmidt wrote:
> Instead of fixing the SPL stack to 64 KiB in the board config header
> via
> CONFIG_SYS_SPL_MALLOC_SIZE, let's just use
> CONFIG_SPL_SYS_MALLOC_F_LEN
> in the defconfig.
> 
> This also has the advandage that it removes sub-mach specific ifdefs
> in
> socfpga_common.h.
> 
> Signed-off-by: Simon Goldschmidt 
> ---
Hi Simon,

I found the culprit in patch[5], you cannot put mem_malloc_init in
spl_common_init function because spl_common_init would be called in
board_init_f, then board_init_f would call mem_malloc_init,
mem_malloc_init would store start and end addresses to few global
variables such as mem_malloc_start, mem_malloc_end and mem_malloc_brk.
By that time, global variables are unavailable yet.

Thanks.
TF

> 
> Changes in v2: None
> 
>  configs/socfpga_arria10_defconfig |  1 +
>  include/configs/socfpga_common.h  | 14 --
>  2 files changed, 1 insertion(+), 14 deletions(-)
> 
> diff --git a/configs/socfpga_arria10_defconfig
> b/configs/socfpga_arria10_defconfig
> index f321a0ac3b..8d0479cc05 100644
> --- a/configs/socfpga_arria10_defconfig
> +++ b/configs/socfpga_arria10_defconfig
> @@ -2,6 +2,7 @@ CONFIG_ARM=y
>  CONFIG_ARCH_SOCFPGA=y
>  CONFIG_SYS_TEXT_BASE=0x0140
>  CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1
>  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
>  CONFIG_SPL=y
>  CONFIG_IDENT_STRING="socfpga_arria10"
> diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_common.h
> index 181af9b646..16c83900c3 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -251,16 +251,6 @@ unsigned int
> cm_get_qspi_controller_clk_hz(void);
>  #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
>  #define CONFIG_SPL_MAX_SIZE  CONFIG_SYS_INIT_RAM_SIZE
>  
> -#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> -/* SPL memory allocation configuration, this is for FAT
> implementation */
> -#ifndef CONFIG_SYS_SPL_MALLOC_START
> -#define CONFIG_SYS_SPL_MALLOC_SIZE   0x0001
> -#define CONFIG_SYS_SPL_MALLOC_START  (CONFIG_SYS_INIT_RAM_SIZE
> - \
> -  CONFIG_SYS_SPL_MALLOC_SIZE
> + \
> -  CONFIG_SYS_INIT_RAM_ADDR)
> -#endif
> -#endif
> -
>  /* SPL SDMMC boot support */
>  #ifdef CONFIG_SPL_MMC_SUPPORT
>  #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
> @@ -294,11 +284,7 @@ unsigned int
> cm_get_qspi_controller_clk_hz(void);
>  /*
>   * Stack setup
>   */
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> -#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
> -#endif
>  
>  /* Extra Environment */
>  #ifndef CONFIG_SPL_BUILD
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[U-Boot] [PATCH 11/11] arm: at91: Add gardena-gateway-at91sam support

[Stefan Roese]

The GARDENA smart Gateway boards are equipped with an Atmel / Microchip
AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage.
This patch adds support for this board including SPL support. Therefore
the AT91Boostrap is not needed on this platform any more.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 .../arm/dts/gardena-smart-gateway-at91sam.dts | 104 ++
 arch/arm/mach-at91/Kconfig|   8 ++
 board/gardena/smart-gateway-at91sam/Kconfig   |  12 ++
 .../gardena/smart-gateway-at91sam/MAINTAINERS |   7 +
 board/gardena/smart-gateway-at91sam/Makefile  |   7 +
 board/gardena/smart-gateway-at91sam/board.c   |  59 
 board/gardena/smart-gateway-at91sam/spl.c | 135 ++
 .../gardena-smart-gateway-at91sam_defconfig   |  84 +++
 .../configs/gardena-smart-gateway-at91sam.h   |  88 
 9 files changed, 504 insertions(+)
 create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam.dts
 create mode 100644 board/gardena/smart-gateway-at91sam/Kconfig
 create mode 100644 board/gardena/smart-gateway-at91sam/MAINTAINERS
 create mode 100644 board/gardena/smart-gateway-at91sam/Makefile
 create mode 100644 board/gardena/smart-gateway-at91sam/board.c
 create mode 100644 board/gardena/smart-gateway-at91sam/spl.c
 create mode 100644 configs/gardena-smart-gateway-at91sam_defconfig
 create mode 100644 include/configs/gardena-smart-gateway-at91sam.h

diff --git a/arch/arm/dts/gardena-smart-gateway-at91sam.dts 
b/arch/arm/dts/gardena-smart-gateway-at91sam.dts
new file mode 100644
index 00..a6de7d02d5
--- /dev/null
+++ b/arch/arm/dts/gardena-smart-gateway-at91sam.dts
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the GARDENA smart Gateway (AT91SAM)
+ *
+ *  Copyright (C) 2012 Atmel,
+ *2012 Nicolas Ferre 
+ */
+
+/dts-v1/;
+
+#include "at91sam9g25.dtsi"
+#include "at91sam9x5ek.dtsi"
+
+/ {
+   model = "GARDENA smart Gateway (AT91SAM)";
+   compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9x5ek", 
"atmel,at91sam9x5", "atmel,at91sam9";
+
+   memory {
+   reg = <0x2000 0x800>;
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   power_blue {
+   label = "smartgw:power:blue";
+   gpios = < 21 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   power_green {
+   label = "smartgw:power:green";
+   gpios = < 20 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   power_red {
+   label = "smartgw:power:red";
+   gpios = < 19 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   radio_blue {
+   label = "smartgw:radio:blue";
+   gpios = < 18 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   radio_green {
+   label = "smartgw:radio:green";
+   gpios = < 17 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   radio_red {
+   label = "smartgw:radio:red";
+   gpios = < 16 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   internet_blue {
+   label = "smartgw:internet:blue";
+   gpios = < 15 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   internet_green {
+   label = "smartgw:internet:green";
+   gpios = < 14 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   internet_red {
+   label = "smartgw:internet:red";
+   gpios = < 13 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   phy-mode = "rmii";
+   status = "okay";
+};
+
+ {
+   status = "disabled";
+};
+
+ {
+   status = "disabled";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "disabled";
+};
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index a6329dc022..87b986ae38 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -147,6 +147,13 @@ config TARGET_AT91SAM9X5EK
select BOARD_LATE_INIT
select SUPPORT_SPL
 
+config TARGET_GARDENA_SMART_GATWAY_AT91SAM
+   bool "GARDENA smart Gateway (AT91SAM)"
+   select AT91SAM9X5
+   select BOARD_EARLY_INIT_F
+   select BOARD_LATE_INIT
+   select SUPPORT_SPL
+
 config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
  

[U-Boot] [PATCH 08/11] Makefile.spl: Move generate AT91SAM NAND image boot.bin to spl directory

[Stefan Roese]

This patch moves the AT91SAM NAND booting SPL image "boot.bin" which
includes the ECC values from the root directory into the spl directory,
where all SPL related images are located.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 scripts/Makefile.spl | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 9d5921606e..37be18da4b 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -179,10 +179,10 @@ MKIMAGEFLAGS_boot.bin = -T atmelimage
 ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y)
 MKIMAGEFLAGS_boot.bin += -n $(shell $(obj)/../tools/atmel_pmecc_params)
 
-boot.bin: $(obj)/../tools/atmel_pmecc_params
+$(obj)/boot.bin: $(obj)/../tools/atmel_pmecc_params
 endif
 
-boot.bin: $(obj)/u-boot-spl.bin FORCE
+$(obj)/boot.bin: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
 else
 ifdef CONFIG_ARCH_ZYNQ
@@ -225,7 +225,7 @@ endif
 endif
 
 ifeq ($(CONFIG_SYS_SOC),"at91")
-ALL-y  += boot.bin
+ALL-y  += $(obj)/boot.bin
 endif
 
 ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin
-- 
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[U-Boot] [PATCH 03/11] serial: atmel_usart: Use fixed clock value in SPL version

[Stefan Roese]

This patch adds an alterative SPL version of atmel_serial_enable_clk().
This enables the usage of this driver without full clock support (in
drivers and DT nodes). This saves some space in the SPL image.

If some boards need a different clock than the one provided with this
patch, then support for this needs to be added later.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 drivers/serial/atmel_usart.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index aa8cdff840..049172baef 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = {
.setbrg = atmel_serial_setbrg,
 };
 
+#ifdef CONFIG_SPL_BUILD
+static int atmel_serial_enable_clk(struct udevice *dev)
+{
+   struct atmel_serial_priv *priv = dev_get_priv(dev);
+
+   /* Use fixed clock value in SPL */
+   priv->usart_clk_rate = 132096000;
+
+   return 0;
+}
+#else
 static int atmel_serial_enable_clk(struct udevice *dev)
 {
struct atmel_serial_priv *priv = dev_get_priv(dev);
@@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
 
return 0;
 }
+#endif
 
 static int atmel_serial_probe(struct udevice *dev)
 {
-- 
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[U-Boot] [PATCH 09/11] Makefile: Add Kconfig option CONFIG_SPL_IMAGE to select the SPL binary

[Stefan Roese]

This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that
shall be used to generate the combined SPL + U-Boot image. The default
value is the current value "spl/u-boot-spl.bin".

This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets
which use SPL NAND support (boot from NAND).

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 Kconfig  | 10 ++
 Makefile |  4 +++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/Kconfig b/Kconfig
index 512c7beb89..6ad58926eb 100644
--- a/Kconfig
+++ b/Kconfig
@@ -224,6 +224,15 @@ config BUILD_ROM
  which are not shipped in the U-Boot source tree.
  Please, see doc/README.x86 for details.
 
+config SPL_IMAGE
+   string "SPL image filename that is generated"
+   default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
+   default "spl/u-boot-spl.bin"
+   help
+ The SPL image filename that is generated by the build process.
+ This image might be used to generated a combined image with
+ SPL and main U-Boot proper as well.
+
 config BUILD_TARGET
string "Build target special images"
default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
@@ -231,6 +240,7 @@ config BUILD_TARGET
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
default "u-boot.kwb" if KIRKWOOD
+   default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
help
  Some SoCs need special image types (e.g. U-Boot binary
  with a special header) as build targets. By defining
diff --git a/Makefile b/Makefile
index c52a33b403..7397724a2b 100644
--- a/Makefile
+++ b/Makefile
@@ -1219,9 +1219,11 @@ else
 SPL_PAYLOAD := u-boot.bin
 endif
 
+SPL_IMAGE := $(CONFIG_SPL_IMAGE:"%"=%)
+
 OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \
   --pad-to=$(CONFIG_SPL_PAD_TO)
-u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE
+u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE
$(call if_changed,pad_cat)
 
 ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
-- 
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[U-Boot] [PATCH 02/11] arm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabled

[Stefan Roese]

This patch adds a call to spl_early_init() to board_init_f() which is
needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for
the early SPL setup including the DTB setup for later usage.

Please note that this call might also be needed for non SPL_OF_CONTROL
board, like the smartweb target. But smartweb fails to build with this
call because its binary grows too big. So I disabled it for these kind
of targets for now.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 arch/arm/mach-at91/spl_at91.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index 23ebaa99b1..1065f090e0 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -75,6 +75,16 @@ void __weak spl_board_init(void)
 
 void board_init_f(ulong dummy)
 {
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+   int ret;
+
+   ret = spl_early_init();
+   if (ret) {
+   debug("spl_early_init() failed: %d\n", ret);
+   hang();
+   }
+#endif
+
lowlevel_clock_init();
 #if !defined(CONFIG_WDT_AT91)
at91_disable_wdt();
-- 
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[U-Boot] [PATCH 06/11] arm: at91: Enable watchdog support

[Stefan Roese]

This patch enables and starts the watchdog on the AT91 platform if
configured. Currently the WD timeout is configured to 16 seconds,
which is the longest value for this timer.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 arch/arm/mach-at91/clock.c | 41 ++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 64cbc3d1ed..2d442d0092 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -5,6 +5,8 @@
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -118,3 +120,42 @@ void at91_pllicpr_init(u32 icpr)
 
writel(icpr, >pllicpr);
 }
+
+#if defined(CONFIG_WATCHDOG) && !defined(CONFIG_SPL_BUILD)
+static struct udevice *watchdog_dev;
+
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+   static ulong next_reset;
+   ulong now;
+
+   if (!watchdog_dev)
+   return;
+
+   now = get_timer(0);
+
+   /* Do not reset the watchdog too often */
+   if (now > next_reset) {
+   next_reset = now + 1000;/* reset every 1000ms */
+   wdt_reset(watchdog_dev);
+   }
+}
+
+int arch_misc_init(void)
+{
+   /* Init watchdog */
+   if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
+   debug("Watchdog: Not found by seq!\n");
+   if (uclass_get_device(UCLASS_WDT, 0, _dev)) {
+   puts("Watchdog: Not found!\n");
+   return 0;
+   }
+   }
+
+   wdt_start(watchdog_dev, 16000, 0);  /* 16 seconds is max */
+   printf("Watchdog: Started\n");
+
+   return 0;
+}
+#endif
-- 
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[U-Boot] [PATCH 10/11] arm: at91: siemens: Add support to generate combined SPL+U-Boot image

[Stefan Roese]

This patch adds the necessary defines to the Siemens AT91SAM based
boards (smartweb, corvus and taurus) to generate the combined binary
image with SPL and main U-Boot image combined (u-boot-with-spl.bin).

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 include/configs/corvus.h   | 3 +++
 include/configs/smartweb.h | 4 
 include/configs/taurus.h   | 3 +++
 3 files changed, 10 insertions(+)

diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 5dd5c28e08..749a67d4b0 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -139,4 +139,7 @@
 #define CONFIG_SYS_MCKR0x1301
 #define CONFIG_SYS_MCKR_CSS0x1302
 
+#define CONFIG_SPL_PAD_TO  CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
+
 #endif
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 28af575bf2..f95b29480d 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -221,4 +221,8 @@
 #define CONFIG_SYS_ICACHE_OFF
 #define CONFIG_SYS_DCACHE_OFF
 #endif
+
+#define CONFIG_SPL_PAD_TO  CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index f283ab7fca..8e56e62282 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -177,4 +177,7 @@
 #define CONFIG_SYS_MCKR_CSS(0x02 | CONFIG_SYS_MCKR)
 #define CONFIG_SYS_AT91_PLLB   0x10193F05
 
+#define CONFIG_SPL_PAD_TO  CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
+
 #endif
-- 
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[U-Boot] [PATCH 07/11] arm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL lds

[Stefan Roese]

This patch adds _image_binary_end to the SPL linker script. This will be
used be the upcoming GARDENA AT91SAM based platform, which uses DT in
SPL and configures CONFIGURE_SPL_SEPARATE_BSS.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds 
b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
index f18b17dc93..3955bea23a 100644
--- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
@@ -39,6 +39,8 @@ SECTIONS
*(.__end)
} >.sram
 
+   _image_binary_end = .;
+
.bss :
{
. = ALIGN(4);
-- 
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[U-Boot] [PATCH 04/11] watchdog: Handle SPL build with watchdog disabled

[Stefan Roese]

This patch adds some checks, so that the watchdog can be enabled in main
U-Boot proper but can be disabled in SPL.

This will be used by some AT91SAM based boards, which might enable the
watchdog in the main U-Boot proper and not in SPL. It will be enabled in
SPL by default there, so no need to configure it there. This approach
saves some space in SPL.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 include/watchdog.h | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/watchdog.h b/include/watchdog.h
index 14073cfdd2..3a357de903 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -51,9 +51,15 @@ int init_func_watchdog_reset(void);
#if defined(__ASSEMBLY__)
#define WATCHDOG_RESET bl watchdog_reset
#else
-   extern void watchdog_reset(void);
+   /* Don't require the watchdog to be enabled in SPL */
+   #if defined(CONFIG_SPL_BUILD) &&\
+   !defined(CONFIG_SPL_WATCHDOG_SUPPORT)
+   #define WATCHDOG_RESET() {}
+   #else
+   extern void watchdog_reset(void);
 
-   #define WATCHDOG_RESET watchdog_reset
+   #define WATCHDOG_RESET watchdog_reset
+   #endif
#endif
#else
/*
-- 
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[U-Boot] [PATCH 01/11] arm: at91: Makefile: Compile lowlevel_init only when really necessary

[Stefan Roese]

Make sure that lowlevel_init is not compiled when
CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 arch/arm/mach-at91/arm926ejs/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-at91/arm926ejs/Makefile 
b/arch/arm/mach-at91/arm926ejs/Makefile
index 0639d7ea1e..6b0b28957a 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -24,8 +24,10 @@ obj-y+= timer.o
 endif
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 obj-y  += lowlevel_init.o
 endif
+endif
 
 ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
 ifndef CONFIG_HAS_THUMB2
-- 
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[U-Boot] [PATCH 05/11] watchdog: at91sam9_wdt: Fix WDT setup in at91_wdt_start()

[Stefan Roese]

This patch fixes the timer register setup in at91_wdt_start() to
correctly configure the register again. The input timeout value is
now in milli-seconds instead of seconds with the new watchdog API.
Make sure to take this into account and only use a max timeout
value of 16 seconds as appropriate for this SoC.

Also the check against a lower timeout value than 0 is removed. This
check makes no sense, as the timeout value is unsigned.

Signed-off-by: Stefan Roese 
Reported-by: Heiko Schocher 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
 drivers/watchdog/at91sam9_wdt.c | 26 ++
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index 13f8772e41..b0a3b4ed58 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -31,27 +32,30 @@ DECLARE_GLOBAL_DATA_PTR;
 #define WDT_SEC2TICKS(s)   (((s) << 8) - 1)
 
 /* Hardware timeout in seconds */
-#define WDT_MAX_TIMEOUT 16
-#define WDT_MIN_TIMEOUT 0
-#define WDT_DEFAULT_TIMEOUT 2
+#define WDT_MAX_TIMEOUT16
+#define WDT_DEFAULT_TIMEOUT2
 
 struct at91_wdt_priv {
void __iomem *regs;
-   u32 regval;
-   u32 timeout;
+   u32 regval;
+   u32 timeout;
 };
 
 /*
  * Set the watchdog time interval in 1/256Hz (write-once)
  * Counter is 12 bit.
  */
-static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags)
+static int at91_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
 {
struct at91_wdt_priv *priv = dev_get_priv(dev);
-   u32 timeout = WDT_SEC2TICKS(timeout_s);
+   u64 timeout;
+   u32 ticks;
 
-   if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT)
-   timeout = priv->timeout;
+   /* Calculate timeout in seconds and the resulting ticks */
+   timeout = timeout_ms;
+   do_div(timeout, 1000);
+   timeout = min_t(u64, timeout, WDT_MAX_TIMEOUT);
+   ticks = WDT_SEC2TICKS(timeout);
 
/* Check if disabled */
if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) {
@@ -65,12 +69,10 @@ static int at91_wdt_start(struct udevice *dev, u64 
timeout_s, ulong flags)
 * Since WDV is a 12-bit counter, the maximum period is
 * 4096 / 256 = 16 seconds.
 */
-
priv->regval = AT91_WDT_MR_WDRSTEN  /* causes watchdog reset */
| AT91_WDT_MR_WDDBGHLT  /* disabled in debug mode */
| AT91_WDT_MR_WDD(0xfff)/* restart at any time */
-   | AT91_WDT_MR_WDV(timeout); /* timer value */
-
+   | AT91_WDT_MR_WDV(ticks);   /* timer value */
writel(priv->regval, priv->regs + AT91_WDT_MR);
 
return 0;
-- 
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[U-Boot] [PATCH] spl: spl_nand.c: Add NAND loading message

[Stefan Roese]

This patch adds a short message to the SPL NAND loader, which displays
the source and destinations addresses including the size of the
loaded image, like this:

U-Boot SPL 2019.04-rc3-00113-g486efd8aaf (Mar 15 2019 - 14:18:02 +0100)
Trying to boot from NAND
Loading U-Boot from 0x0004 (size 0x000a) to 0x2290

I find this message quite helpful - hopefully others do so as well.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Tom Rini 
---
 common/spl/spl_nand.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 6eb190f1ea..47eaddc002 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -17,6 +17,11 @@ static int spl_nand_load_image(struct spl_image_info 
*spl_image,
 {
nand_init();
 
+#if defined(CONFIG_SPL_SERIAL_SUPPORT)
+   printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n",
+  CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
+  CONFIG_SYS_NAND_U_BOOT_DST);
+#endif
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE,
(void *)CONFIG_SYS_NAND_U_BOOT_DST);
-- 
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Re: [U-Boot] UCLASS_MISC bug

[Jean-Jacques Hiblot]

+ Simon Glass


Hi Serguey,

On 15/03/2019 22:55, Sergey Kubushyn wrote:

I would like to point that this was not a very good idea:

=== Cut ===
--- uboot-imx-next/drivers/misc/misc-uclass.c    2018-12-20 
20:35:22.505180339 -0800
+++ u-boot-imx/drivers/misc/misc-uclass.c    2019-03-13 
11:50:19.408982814 -0700

@@ -68,4 +68,7 @@ int misc_set_enabled(struct udevice *dev
 UCLASS_DRIVER(misc) = {
 .id    = UCLASS_MISC,
 .name    = "misc",
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+    .post_bind    = dm_scan_fdt_dev,
+#endif
 };
=== Cut ===

The problem comes up with all those "glue" layers like e.g. in 
usb/dwc3 and

everywhere else.

Those "glues" primarily bind drivers to e.g. USB interfaces like e.g.
dwc3-generic does. That is where it should stop because glue knows better
what to bind. However, after glue has bound appropriate drivers to their
interfaces that post_bind scans FDT again and finds yet another bunch of
drivers that it binds on top of what glue already bound. This happens 
e.g.
with DWC3 drivers that glues bind to interfaces depending on their 
declared

roles. However both peripheral and XHCI drivers are compatible with
"snps,dwc3" so they are bound on top creating a huge mess. Here is a 
dm tree

fragment of its action:

=== Cut ===
 phy  0  [ + ]   imx8mq_usb_phy    |-- phy@381f0040
 misc 0  [ + ]   imx8m_dwc3_glue   |-- usb@3810
 usb  0  [   ]   imx8m_dwc3_periphera  |   |-- dwc3
 usb  0  [   ]   xhci-dwc3 |   `-- dwc3
 phy  1  [   ]   imx8mq_usb_phy    |-- phy@382f0040
 misc 1  [   ]   imx8m_dwc3_glue   |-- usb@3820
 usb  1  [   ]   xhci-dwc3 |   |-- dwc3
 usb  2  [   ]   xhci-dwc3 |   `-- dwc3
=== Cut ===

The glue bound imx8m_dwc3_peripheral to USB0 then post_bind found yet
another "compatible" driver, xhci-dwc3 and bound it to the same 
interface.


Then glue bound xhci-dwc3 to USB1 but post_bind found yet another
"compatible" driver, xhci-dwc3 and bound it again so there are TWO xhci
drivers bound to the same interface.

This is simplified picture -- I removed "compatible" from my peripheral
driver so it only comes up once, under USB0. If I leave that "compatible"
with "snps,dwc3" there everything gets even weirder :(

That diff above is the latest 2019.04-rc3 u-boot-imx-next vs 2019.01-rc
something release.

We either need some additional special flag to disable that post_bind 
where
it is not needed or create a special new class for those binding 
"glues" or

this change should be reverted.


We can also see the problem on TI platforms.

Tested with a am57xx evm

JJ



P.S. I'm going to post imx8m USB glue, USB PHY, USB peripheral initial
drivers probably Monday late night as they still need some cleanup. It 
all

works with full Linux Kernel DTS files, picks power domains from there.

Don't know what to do with my board-specific DTS as there is (and 
probably
will not be) our board submitted -- it is not secret but used in our 
devices
only and not available to the public -- so it doesn't make sense to 
post a

full DTS. Will probably send a fragment.

---
**
*  KSI@home    KOI8 Net  < >  The impossible we do immediately.  *
*  Las Vegas   NV, USA   < >  Miracles require 24-hour notice.   *
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Re: [U-Boot] [PATCH] ARM: kirkwood: remove obsolete call to icache_enable

[Stefan Roese]

On 19.03.19 15:50, Leigh Brown wrote:

Commit 93b283d49f93 ("ARM: CPU: arm926ejs: Consolidate cache routines to
common file") changed cache setup for Kirkwood such that icache_enable()
is now called from enable_caches() which is called from initr_caches()
which is in the list of functions in init_sequence_r[] prior to
arch_misc_init().  This means the call to icache_enable() in
arch_misc_init() is no longer required, so remove it.

Signed-off-by: Leigh Brown 


Reviewed-by: Stefan Roese 

I'll push this patch with my next updates in a few days into mainline.

Thanks,
Stefan
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[U-Boot] [PATCH] ARM: kirkwood: remove obsolete call to icache_enable

[Leigh Brown]

Commit 93b283d49f93 ("ARM: CPU: arm926ejs: Consolidate cache routines to 
common file") changed cache setup for Kirkwood such that icache_enable() 
is now called from enable_caches() which is called from initr_caches() 
which is in the list of functions in init_sequence_r[] prior to 
arch_misc_init().  This means the call to icache_enable() in

arch_misc_init() is no longer required, so remove it.

Signed-off-by: Leigh Brown 
---

diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c
index d54de53f31..8a065d73ae 100644
--- a/arch/arm/mach-kirkwood/cpu.c
+++ b/arch/arm/mach-kirkwood/cpu.c
@@ -291,7 +291,6 @@ int arch_misc_init(void)
temp |= (1 << 22);
writefr_extra_feature_reg(temp);

-   icache_enable();
/* Change reset vector to address 0x0 */
temp = get_cr();
set_cr(temp & ~CR_V);
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[U-Boot] [PATCH] ARM: meson: display Amlogic SoC Information

[Julien Masson]

The Amlogic SoCs have a registers containing the die revision
and packaging type to determine the SoC family and package marketing
name like S905X for the GXL SoC Family.

This code is taken from the Linux meson-gx-socinfo driver and adapted
to U-Boot printing.

Signed-off-by: Julien Masson 
---
 arch/arm/mach-meson/board-common.c | 140 +
 configs/khadas-vim_defconfig   |   2 +-
 configs/libretech-cc_defconfig |   2 +-
 configs/odroid-c2_defconfig|   2 +-
 configs/p212_defconfig |   2 +-
 5 files changed, 144 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-meson/board-common.c 
b/arch/arm/mach-meson/board-common.c
index 8c41301..e766ebc 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -7,11 +7,59 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
+#include 
+#include 
+
+#define AO_SEC_SD_CFG8 0xe0
+#define AO_SEC_SOCINFO_OFFSET  AO_SEC_SD_CFG8
+
+#define SOCINFO_MAJOR  GENMASK(31, 24)
+#define SOCINFO_PACK   GENMASK(23, 16)
+#define SOCINFO_MINOR  GENMASK(15, 8)
+#define SOCINFO_MISC   GENMASK(7, 0)
+
+static const struct meson_gx_soc_id {
+   const char *name;
+   unsigned int id;
+} soc_ids[] = {
+   { "GXBB",   0x1f },
+   { "GXTVBB", 0x20 },
+   { "GXL",0x21 },
+   { "GXM",0x22 },
+   { "TXL",0x23 },
+   { "TXLX",   0x24 },
+   { "AXG",0x25 },
+   { "GXLX",   0x26 },
+   { "TXHD",   0x27 },
+};
+
+static const struct meson_gx_package_id {
+   const char *name;
+   unsigned int major_id;
+   unsigned int pack_id;
+} soc_packages[] = {
+   { "S905",   0x1f, 0 },
+   { "S905H",  0x1f, 0x13 },
+   { "S905M",  0x1f, 0x20 },
+   { "S905D",  0x21, 0 },
+   { "S905X",  0x21, 0x80 },
+   { "S905W",  0x21, 0xa0 },
+   { "S905L",  0x21, 0xc0 },
+   { "S905M2", 0x21, 0xe0 },
+   { "S912",   0x22, 0 },
+   { "962X",   0x24, 0x10 },
+   { "962E",   0x24, 0x20 },
+   { "A113X",  0x25, 0x37 },
+   { "A113D",  0x25, 0x22 },
+};
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -115,3 +163,95 @@ void reset_cpu(ulong addr)
 {
psci_system_reset();
 }
+
+static inline unsigned int socinfo_to_major(u32 socinfo)
+{
+   return FIELD_GET(SOCINFO_MAJOR, socinfo);
+}
+
+static inline unsigned int socinfo_to_minor(u32 socinfo)
+{
+   return FIELD_GET(SOCINFO_MINOR, socinfo);
+}
+
+static inline unsigned int socinfo_to_pack(u32 socinfo)
+{
+   return FIELD_GET(SOCINFO_PACK, socinfo);
+}
+
+static inline unsigned int socinfo_to_misc(u32 socinfo)
+{
+   return FIELD_GET(SOCINFO_MISC, socinfo);
+}
+
+static const char *socinfo_to_package_id(u32 socinfo)
+{
+   unsigned int pack = socinfo_to_pack(socinfo) & 0xf0;
+   unsigned int major = socinfo_to_major(socinfo);
+   int i;
+
+   for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) {
+   if (soc_packages[i].major_id == major &&
+   soc_packages[i].pack_id == pack)
+   return soc_packages[i].name;
+   }
+
+   return "Unknown";
+}
+
+static const char *socinfo_to_soc_id(u32 socinfo)
+{
+   unsigned int id = socinfo_to_major(socinfo);
+   int i;
+
+   for (i = 0 ; i < ARRAY_SIZE(soc_ids) ; ++i) {
+   if (soc_ids[i].id == id)
+   return soc_ids[i].name;
+   }
+
+   return "Unknown";
+}
+
+int show_board_info(void)
+{
+   struct regmap *regmap;
+   int nodeoffset, ret;
+   ofnode node;
+   unsigned int socinfo;
+
+   /* find the offset of compatible node */
+   nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+  
"amlogic,meson-gx-ao-secure");
+   if (nodeoffset < 0)
+   return 0;
+
+   /* check if chip-id is available */
+   if (!fdt_getprop(gd->fdt_blob, nodeoffset, "amlogic,has-chip-id", NULL))
+   return 0;
+
+   /* get regmap from the syscon node */
+   node = offset_to_ofnode(nodeoffset);
+   regmap = syscon_node_to_regmap(node);
+   if (IS_ERR(regmap)) {
+   printf("%s: failed to get regmap\n", __func__);
+   return 0;
+   }
+
+   /* read soc info */
+   ret = regmap_read(regmap, AO_SEC_SOCINFO_OFFSET, );
+   if (ret && !socinfo) {
+   printf("%s: invalid chipid value\n", __func__);
+   return 0;
+   }
+
+   /* print board information */
+   printf("Amlogic Meson %s (%s) Revision %x:%x (%x:%x)\n",
+  socinfo_to_soc_id(socinfo),
+  socinfo_to_package_id(socinfo),
+  socinfo_to_major(socinfo),
+  socinfo_to_minor(socinfo),
+  socinfo_to_pack(socinfo),
+  socinfo_to_misc(socinfo));
+
+   return 0;
+}
diff --git a/configs/khadas-vim_defconfig 

Re: [U-Boot] [PATCH] ti: am335x_evm: Enable CONFIG_SPL_OF_CONTROL

[Tom Rini]

On Tue, Mar 19, 2019 at 05:01:42PM +0530, Faiz Abbas wrote:
> Hi Tom,
> 
> On 19/03/19 4:49 PM, Tom Rini wrote:
> > Enable support for SPL_OF_CONTROL on this platform.  That means doing a
> > few things:
> > - Add u-boot,dm-pre-reloc to a number of nodes
> > - Drop static platdata in the board file.
> > - A lot of tweaks to the defconfig.  We remove some things such as
> >   SPL_USE_ARCH_MEMCPY/SET for space.  Increase our malloc len.
> > - Drop, for now at least, USB SPL support as it's causing a hang.
> > 
> > Cc: Faiz Abbas 
> > Cc: Lokesh Vutla 
> > Signed-off-by: Tom Rini 
> > ---
> >  arch/arm/dts/am335x-evm-u-boot.dtsi | 45 
> > +++--
> >  board/ti/am335x/board.c | 30 -
> >  configs/am335x_evm_defconfig| 14 
> >  3 files changed, 53 insertions(+), 36 deletions(-)
> > 
> > diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi 
> > b/arch/arm/dts/am335x-evm-u-boot.dtsi
> > index b6b97ed16d91..16a9f855ad1f 100644
> > --- a/arch/arm/dts/am335x-evm-u-boot.dtsi
> > +++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
> > @@ -3,11 +3,52 @@
> >   * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
> >   */
> >  
> > +#include "am33xx-u-boot.dtsi"
> >  
> > - {
> > -   status = "disabled";
> > +_wkup {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > + {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > +_pinmux {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > +_pins {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > + {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > + {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > + {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > +_pins {
> > +   u-boot,dm-pre-reloc;
> >  };
> >  
> >   {
> > dr_mode = "peripheral";
> >  };
> > +
> > + {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > +_pins {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > + {
> > +   status = "disabled";
> > +};
> > diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
> > index d67f94ad47ba..bfad1a75a456 100644
> > --- a/board/ti/am335x/board.c
> > +++ b/board/ti/am335x/board.c
> > @@ -1054,33 +1054,3 @@ void board_fit_image_post_process(void **p_image, 
> > size_t *p_size)
> > secure_boot_verify_image(p_image, p_size);
> >  }
> >  #endif
> > -
> > -#if !CONFIG_IS_ENABLED(OF_CONTROL)
> > -static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
> > -   .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
> > -   .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
> > -   .cfg.f_min = 40,
> > -   .cfg.f_max = 5200,
> > -   .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
> > -   .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
> > -};
> > -
> > -U_BOOT_DEVICE(am335x_mmc0) = {
> > -   .name = "omap_hsmmc",
> > -   .platdata = _mmc0_platdata,
> > -};
> > -
> > -static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
> > -   .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
> > -   .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
> > -   .cfg.f_min = 40,
> > -   .cfg.f_max = 5200,
> > -   .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
> > -   .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
> > -};
> > -
> > -U_BOOT_DEVICE(am335x_mmc1) = {
> > -   .name = "omap_hsmmc",
> > -   .platdata = _mmc1_platdata,
> > -};
> > -#endif
> 
> We also need to look at arch/arm/mach-omap2/board.c. Bunch of GPIO and
> I2C platdata there.

Yes, but that's all also guarded under a check for SPL_OF_CONTROL being
enabled.  The above is the board-specific part and why I dropped it.

> In general, if we are not able to fit all bootmodes with SPL_OF_CONTROL
> enabled, should we remove it and add back platdata or do something else?

I'm not sure we can fit all the boot modes with platdata either, nor am
I convinced that's the best thing to do.  Checking the TRM again, you
can only have 4 choices at most in a single hardware config, and we
already don't support some options such as SPI with everything else.

But I'd like to start with seeing everything working with
SPL_OF_CONTROL, even if it's not all enabled in the same binary and then
we can see what options are available to us to fit the most into a
single binary.

-- 
Tom


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Re: [U-Boot] [PATCH 1/3] thermal: Add multiple instance support

[keerthy]

On 3/19/2019 6:53 AM, Simon Glass wrote:

Hi Keerthy,

On Mon, 11 Mar 2019 at 14:13, Keerthy  wrote:


Currently single instance temperature read out is supported.
Enhance the same to support multiple instances.

Signed-off-by: Keerthy 
---
  arch/arm/mach-imx/cpu.c  |  2 +-
  drivers/mmc/omap_hsmmc.c |  2 +-
  drivers/thermal/imx_thermal.c|  2 +-
  drivers/thermal/thermal-uclass.c |  4 ++--
  drivers/thermal/ti-bandgap.c | 13 ++---
  include/thermal.h|  6 --
  6 files changed, 19 insertions(+), 10 deletions(-)


Please can you add a simple test for the thermal uclass in test/dm?


Okay. I will try to add that.





diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 6b83f92662..27d12b410e 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -231,7 +231,7 @@ int print_cpuinfo(void)
 printf("(%dC to %dC)", minc, maxc);
 ret = uclass_get_device(UCLASS_THERMAL, 0, _dev);
 if (!ret) {
-   ret = thermal_get_temp(thermal_dev, _tmp);
+   ret = thermal_get_temp(thermal_dev, 0, _tmp);

 if (!ret)
 printf(" at %dC\n", cpu_tmp);
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 826a39fad7..1872273dd9 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -642,7 +642,7 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, 
uint opcode)
 printf("Couldn't get thermal device for tuning\n");
 return ret;
 }
-   ret = thermal_get_temp(thermal_dev, );
+   ret = thermal_get_temp(thermal_dev, 0, );
 if (ret) {
 printf("Couldn't get temperature for tuning\n");
 return ret;
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index e50b85bd59..271a61356c 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -207,7 +207,7 @@ static int read_cpu_temperature(struct udevice *dev)
  }
  #endif

-int imx_thermal_get_temp(struct udevice *dev, int *temp)
+int imx_thermal_get_temp(struct udevice *dev, int instance, int *temp)
  {
 struct thermal_data *priv = dev_get_priv(dev);
 int cpu_tmp = 0;
diff --git a/drivers/thermal/thermal-uclass.c b/drivers/thermal/thermal-uclass.c
index a4ea1e2914..b4a31280cb 100644
--- a/drivers/thermal/thermal-uclass.c
+++ b/drivers/thermal/thermal-uclass.c
@@ -13,14 +13,14 @@
  #include 


-int thermal_get_temp(struct udevice *dev, int *temp)
+int thermal_get_temp(struct udevice *dev, u8 instance, int *temp)
  {
 const struct dm_thermal_ops *ops = device_get_ops(dev);

 if (!ops->get_temp)
 return -ENOSYS;

-   return ops->get_temp(dev, temp);
+   return ops->get_temp(dev, instance, temp);
  }

  UCLASS_DRIVER(thermal) = {
diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c
index b490391e96..6d3606b0fc 100644
--- a/drivers/thermal/ti-bandgap.c
+++ b/drivers/thermal/ti-bandgap.c
@@ -27,6 +27,7 @@
  struct ti_bandgap {
 ulong   base;
 int temperature;/* in mili degree celsius */
+   int sens_cnt;
  };

  /*
@@ -158,11 +159,16 @@ static int dra752_adc_to_temp[] = {
 123800, 124200, 124600, 124900, 125000, 125000,
  };

-static int ti_bandgap_get_temp(struct udevice *dev,  int *temp)
+static int ti_bandgap_get_temp(struct udevice *dev, u8 instance, int *temp)
  {
 struct ti_bandgap *bgp = dev_get_priv(dev);

-   bgp->temperature = 0x3ff & readl(bgp->base + CTRL_CORE_TEMP_SENSOR_MPU);
+   if (instance >= bgp->sens_cnt) {
+   printf("Only %d insatnces are supported\n", bgp->sens_cnt);
+   return -EINVAL;
+   }
+
+   bgp->temperature = 0x3ff & readl(bgp->base + instance * 4);
 *temp = dra752_adc_to_temp[bgp->temperature - DRA752_ADC_START_VALUE];

 return 0;
@@ -177,13 +183,14 @@ static int ti_bandgap_probe(struct udevice *dev)
 struct ti_bandgap *bgp = dev_get_priv(dev);

 bgp->base = devfdt_get_addr_index(dev, 1);
+   bgp->sens_cnt = dev_get_driver_data(dev);

 return 0;
  }

  static const struct udevice_id of_ti_bandgap_match[] = {
 {
-   .compatible = "ti,dra752-bandgap",
+   .compatible = "ti,dra752-bandgap", .data = 3,
 },
 {},
  };
diff --git a/include/thermal.h b/include/thermal.h
index 11d75256e0..82d80f3ded 100644
--- a/include/thermal.h
+++ b/include/thermal.h
@@ -9,7 +9,7 @@

  #include 

-int thermal_get_temp(struct udevice *dev, int *temp);
+int thermal_get_temp(struct udevice *dev, u8 instance, int *temp);


Please add function comment.


Okay.





  /**
   * struct dm_thermal_ops - Driver model Thermal operations
@@ -25,9 +25,11 @@ struct dm_thermal_ops {
  * It will enable and initialize any Thermal hardware as necessary.
  *
 

[U-Boot] [PATCH 2/3] arm64: zynqmp: Define label for flash node

[Michal Simek]

From: Siva Durga Prasad Paladugu 

Define a label for flash node so that it can be
referenced easily as required.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-mini-qspi.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts 
b/arch/arm/dts/zynqmp-mini-qspi.dts
index 49e8a42f6bfc..1716d5179ddf 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -63,7 +63,7 @@
 
  {
status = "okay";
-   flash@0 {
+   flash0: flash@0 {
compatible = "n25q512a11", "spi-flash";
#address-cells = <1>;
#size-cells = <1>;
-- 
1.9.1

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[U-Boot] [PATCH 3/3] arm64: xilinx: zynqmp: Remove unneeded configs

[Michal Simek]

From: Siva Durga Prasad Paladugu 

Remove unneeded configs from mini qspi configuration
so that it saves space for this mini configuration.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 configs/xilinx_zynqmp_mini_qspi_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig 
b/configs/xilinx_zynqmp_mini_qspi_defconfig
index ba521876b75f..ec92104f0cbf 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -6,8 +6,10 @@ CONFIG_ENV_SIZE=0x80
 CONFIG_SPL=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_ZYNQMP_NO_DDR=y
+# CONFIG_PSCI_RESET is not set
 # CONFIG_CMD_ZYNQMP is not set
 CONFIG_NR_DRAM_BANKS=1
+# CONFIG_EXPERT is not set
 # CONFIG_IMAGE_FORMAT_LEGACY is not set
 # CONFIG_BOARD_LATE_INIT is not set
 # CONFIG_DISPLAY_CPUINFO is not set
-- 
1.9.1

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[U-Boot] [PATCH 1/3] arm64: zynqmp: Add spi-flash compatible string to flash node

[Michal Simek]

From: Siva Durga Prasad Paladugu 

spi-flash compatible string is needed for reading tx and rx bus
widths, hence add this compatible string to flash node.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-mini-qspi.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts 
b/arch/arm/dts/zynqmp-mini-qspi.dts
index c235a5f731d9..49e8a42f6bfc 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -64,7 +64,7 @@
  {
status = "okay";
flash@0 {
-   compatible = "n25q512a11";
+   compatible = "n25q512a11", "spi-flash";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
-- 
1.9.1

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[U-Boot] Please pull u-boot-marvell/master

[Stefan Roese]

Hi Tom,

please pull the following Marvell related patches, mostly fixes
which should go into the upcoming release:


- Enable network interface on clearfog_gt_8k (Baruch)
- Fix dreamplug boot by adding an spi0 alias to the DT (Chris)
- Fix / enhance Marvell ddr3 setup / parameters (Chris)
- Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris)
- Enable SPL_FLASH_BAR on db-88f6820-amc (Chris)
- Use correct pcie controller name in Armada-38x dts files (Chris)
- Disable d-cache on Kirkwood platforms as currently needed (Chris)
- Add a more descriptive comment to pci_mvebu.c (Stefan)
- Update Marvell maintainers entry (Stefan)


Thanks,
Stefan


The following changes since commit 374bf7af033aa326a9585c5ff878d206e90c0c1c:

  Prepare v2019.04-rc4 (2019-03-18 21:14:02 -0400)

are available in the Git repository at:

  git://www.denx.de/git/u-boot-marvell.git

for you to fetch changes up to 599f7aa541bb5a658cbfd2af73bd9d2f6e828d43:

  ARM: kirkwood: disable dcache for Kirkwood boards (2019-03-19 09:22:05 +0100)


Baruch Siach (1):
  configs/clearfog_gt_8k: add network interface support

Chris Packham (7):
  ARM: kirkwood: add spi0 alias for dreamplug
  mv_ddr: ddr3: fix tRAS timimg parameter
  mv_ddr: ddr3: only use active chip-selects when tuning ODT
  ARM: mvebu: set CONFIG_SYS_MALLOC_F_LEN to 0x2000
  ARM: mvebu: db-88f6820-amc: enable SPI_FLASH_BAR
  ARM: mvebu: use correct name for pcie controller
  ARM: kirkwood: disable dcache for Kirkwood boards

Stefan Roese (2):
  pci: pci_mvebu: Add comment about missing of_n_addr_cells() call
  MAINTAINERS: Update u-boot-marvell entry

 MAINTAINERS  | 11 +++
 arch/arm/dts/armada-385-amc.dts  |  2 +-
 arch/arm/dts/armada-385-turris-omnia.dts |  2 +-
 arch/arm/dts/armada-388-clearfog.dts |  2 +-
 arch/arm/dts/armada-388-gp.dts   |  2 +-
 arch/arm/dts/armada-38x-controlcenterdc.dts  |  2 +-
 arch/arm/dts/kirkwood-dreamplug.dts  |  4 
 arch/arm/mach-kirkwood/include/mach/config.h |  6 ++
 configs/clearfog_gt_8k_defconfig |  4 +++-
 configs/db-88f6820-amc_defconfig |  2 ++
 drivers/ddr/marvell/a38x/ddr3_training_db.c  |  8 
 drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c |  3 ++-
 drivers/pci/pci_mvebu.c  |  6 ++
 13 files changed, 39 insertions(+), 15 deletions(-)
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Re: [U-Boot] [PATCH v2] ARM: kirkwood: disable dcache for Kirkwood boards

[Stefan Roese]

On 18.03.19 08:51, Chris Packham wrote:

Prior to commit 93b283d49f93 ("ARM: CPU: arm926ejs: Consolidate cache
routines to common file") the kirkwood boards didn't have and dcache
support. The network and usb drivers rely on this. Set
CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h.

Reported-by: Leigh Brown 
Signed-off-by: Chris Packham 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] ARM: mvebu: use correct name for pcie controller

[Stefan Roese]

On 16.03.19 08:46, Chris Packham wrote:

When armada-385.dtsi was sync'd from Linux the name of the node
describing the pcie controller was changed from pcie-controller to pcie.
Some of the boards that include armada-385.dtsi were missed in the
update retaining the old name. This updates the affected boards.

Reported-by: Влад Мао 
Signed-off-by: Chris Packham 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] ARM: mvebu: db-88f6820-amc: enable SPI_FLASH_BAR

[Stefan Roese]

On 02.03.19 08:45, Chris Packham wrote:

This board uses Micron N25Q256A SPI flash. Enable SPI_FLASH_BAR to allow
us to access the whole chip.

Signed-off-by: Chris Packham 
Cc: Vignesh R 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] ARM: mvebu: set CONFIG_SYS_MALLOC_F_LEN to 0x2000

[Stefan Roese]

On 01.03.19 02:30, Chris Packham wrote:

Set CONFIG_SYS_MALLOC_F_LEN to match the rest of the mvebu boards. The
default of 0x400 is not enough when booting from SPI.

Signed-off-by: Chris Packham 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH 2/2] mv_ddr: ddr3: only use active chip-selects when tuning ODT

[Stefan Roese]

On 28.02.19 22:11, Chris Packham wrote:

From: Chris Packham 

Inactive chip-selects will give invalid values for read_sample so don't
consider them when trying to determine the overall min/max read sample.

Signed-off-by: Chris Packham 

[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18]
Signed-off-by: Chris Packham 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/2] mv_ddr: ddr3: fix tRAS timimg parameter

[Stefan Roese]

On 28.02.19 22:11, Chris Packham wrote:

From: Chris Packham 

Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong
comparison was used in the initial implementation.

Signed-off-by: Chris Packham 

[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15]
Signed-off-by: Chris Packham 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] ARM: kirkwood: add spi0 alias for dreamplug

[Stefan Roese]

On 28.02.19 08:53, Chris Packham wrote:

The conversion to DM_SPI managed to break accessing the environment on
dreamplug. This is because the environment code relies on being to able
to select the SPI device based on the sequence number. Add an alias so
that the spi0 bus gets sequence number 0.

Reported-by: Leigh Brown 
Signed-off-by: Chris Packham 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] MAINTAINERS: Update u-boot-marvell entry

[Stefan Roese]

On 15.02.19 13:56, Stefan Roese wrote:

This patch does the following changes to the u-boot-marvell maintainers
entry:

- Add Armada-7k/8k to the list
- Remove Prafulla and Luka since they have been silent on the list for
   a long time. Please speak up, if you would like to continue or better
   start maintaining.
- Add multiple Marvell / MVEBU related driver directories and files

Signed-off-by: Stefan Roese 
Cc: Prafulla Wadaskar 
Cc: Luka Perkov 
Cc: Tom Rini 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] configs/clearfog_gt_8k: add network interface support

[Stefan Roese]

On 11.02.19 13:19, Baruch Siach wrote:

Enable the mvpp2 network driver for the Armada 8K SoC.

Enable the Marvell PHY driver for the on-board 1512 PHY.

Signed-off-by: Baruch Siach 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] pci: pci_mvebu: Add comment about missing of_n_addr_cells() call

[Stefan Roese]

On 11.02.19 07:53, Stefan Roese wrote:

This patch adds a comment to explain the use of the hardcoded value for
the number of address cells in mvebu_get_tgt_attr(). This should help to
rework this function, once CONFIG_OF_LIVE is enabled for MVEBU in
general.

Signed-off-by: Stefan Roese 
Cc: Bin Meng 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH 10/10] ddr: altera: Stratix10: Add ECC memory scrubbing

[Marek Vasut]

On 3/19/19 10:49 AM, Ley Foon Tan wrote:
> On Tue, Mar 19, 2019 at 5:39 PM Marek Vasut  wrote:
>>
>> On 3/19/19 4:14 AM, Ley Foon Tan wrote:
>>> On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:

 On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> Scrub memory content if ECC is enabled and it is not
> from warm reset boot.
>
> Enable icache and dcache before scrub memory
> and use "DC ZVA" instruction to clear memory
> to zeros. This instruction writes a cache line
> at a time and it can prevent false ECC error
> trigger if write cache line partially.
>
> Signed-off-by: Ley Foon Tan 
> ---
>  .../arm/mach-socfpga/include/mach/sdram_s10.h |  9 +++
>  drivers/ddr/altera/sdram_s10.c| 76 +++
>  2 files changed, 85 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h 
> b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> index 89e355010d..354f80bfce 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> @@ -23,6 +23,7 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
> phys_size_t bank_size[]);
>  #define ECCCTRL1 0x100
>  #define ECCCTRL2 0x104
>  #define ERRINTEN 0x110
> +#define ERRINTENS0x114
>  #define INTMODE  0x11c
>  #define INTSTAT  0x120
>  #define AUTOWB_CORRADDR  0x138
> @@ -53,6 +54,10 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
> phys_size_t bank_size[]);
>  #define DDR_HMC_SEQ2CORE_INT_RESP_MASK   BIT(3)
>  #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK  0x001f1f1f
>
> +#define  DDR_HMC_ERRINTEN_INTMASK\
> + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |\
> +  DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
> +
>  /* NOC DDR scheduler */
>  #define DDR_SCH_ID_COREID0
>  #define DDR_SCH_ID_REVID 0x4
> @@ -181,4 +186,8 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
> phys_size_t bank_size[]);
>  #define CALTIMING9_CFG_4_ACT_TO_ACT(x)   \
>   (((x) >> 0) & 0xFF)
>
> +/* Firewall DDR scheduler MPFE */
> +#define FW_HMC_ADAPTOR_REG_ADDR  0xf8020004
> +#define FW_HMC_ADAPTOR_MPU_MASK  BIT(0)
> +
>  #endif /* _SDRAM_S10_H_ */
> diff --git a/drivers/ddr/altera/sdram_s10.c 
> b/drivers/ddr/altera/sdram_s10.c
> index ae4e5ea2fd..2c691d3bee 100644
> --- a/drivers/ddr/altera/sdram_s10.c
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -22,6 +22,8 @@ static const struct socfpga_system_manager *sysmgr_regs 
> =
>
>  #define DDR_CONFIG(A, B, C, R)   (((A) << 24) | ((B) << 16) | ((C) 
> << 8) | (R))
>
> +#define PGTABLE_OFF  0x4000
> +
>  /* The followring are the supported configurations */
>  u32 ddr_config[] = {
>   /* DDR_CONFIG(Address order,Bank,Column,Row) */
> @@ -135,6 +137,71 @@ static int poll_hmc_clock_status(void)
>SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, 
> false);
>  }
>
> +static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
> +{
> + phys_size_t i;
> +
> + if (addr % CONFIG_SYS_CACHELINE_SIZE) {
> + printf("DDR: address 0x%lx not cacheline size aligned.\n",
> +(ulong)addr);

 Is the cast needed ?
>>> Yes, SPL doesn't support %llx, we need cast to ulong %lx.
>>
>> But that doesn't work for 64bit addresses ?
>> Isn't that limitation of tiny printf implementation instead of SPL ?
>>
> %lx still work for 64 bit address.
> 
> Yes, I think it is limitation of  tiny printf in SPL.

Can the tiny printf be fixed ? I think it should be easy.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] p2371-2180: Build position independent binary

[Thierry Reding]

On Mon, Mar 18, 2019 at 12:31:32PM -0600, Stephen Warren wrote:
> On 3/8/19 1:10 PM, Thierry Reding wrote:
> > From: Thierry Reding 
> > 
> > In order to support chainloading of U-Boot by an earlier bootloader,
> > make sure the binary is position independent, so that the earlier boot-
> > loader can relocate it if necessary.
> 
> Why not enable this for all 64-bit Tegra? They're all booted the exact same
> way at least with recent L4T builds.

Yeah, I think that would make sense.

> Also, U-Boot is typically linked to the address that cboot loads it to, and
> cboot typically always loads to precisely that address. I'm not sure why
> this patch is required.

I encountered this issue when I was trying to chainload U-Boot from
cboot on Jetson TX1. It seems like your above comment is no longer true,
though I suppose that could just mean that the link address for U-Boot
has become stale?

> That said, it don't think it harms anything, so I'm fine with it being
> applied.

I suppose there's a bit of extra code to do the indirect jumps, but
overall U-Boot seems to work well and not noticeably slower if this is
enabled. Might be nice for extra flexibility and to avoid any surprises
if we ever end up loading U-Boot to a location other than where it was
liked to.

My understanding is that this could happen on Tegra186 if cboot detects
bad memory blocks in the area where U-Boot was meant to be loaded to. I
guess this doesn't apply to earlier chips, but perhaps it's good to have
it there for consistency anyway.

Thierry


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[U-Boot] [PATCH 1/1] efi_loader: endless loop in add_strings_package()

[Heinrich Schuchardt]

Avoid an endless loop in add_strings_package().

Fixes Coverity CID 185833

Suggested-by: Takahiro Akashi 
Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_hii.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c
index 3a966fa4dff..61b71dec621 100644
--- a/lib/efi_loader/efi_hii.c
+++ b/lib/efi_loader/efi_hii.c
@@ -227,9 +227,8 @@ out:
 error:
if (stbl) {
free(stbl->language);
-   if (idx > 0)
-   while (--idx >= 0)
-   free(stbl->strings[idx].string);
+   while (idx > 0)
+   free(stbl->strings[--idx].string);
free(stbl->strings);
}
free(stbl);
--
2.20.1

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Re: [U-Boot] [PATCH] ti: am335x_evm: Enable CONFIG_SPL_OF_CONTROL

[Faiz Abbas]

Hi Tom,

On 19/03/19 4:49 PM, Tom Rini wrote:
> Enable support for SPL_OF_CONTROL on this platform.  That means doing a
> few things:
> - Add u-boot,dm-pre-reloc to a number of nodes
> - Drop static platdata in the board file.
> - A lot of tweaks to the defconfig.  We remove some things such as
>   SPL_USE_ARCH_MEMCPY/SET for space.  Increase our malloc len.
> - Drop, for now at least, USB SPL support as it's causing a hang.
> 
> Cc: Faiz Abbas 
> Cc: Lokesh Vutla 
> Signed-off-by: Tom Rini 
> ---
>  arch/arm/dts/am335x-evm-u-boot.dtsi | 45 
> +++--
>  board/ti/am335x/board.c | 30 -
>  configs/am335x_evm_defconfig| 14 
>  3 files changed, 53 insertions(+), 36 deletions(-)
> 
> diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi 
> b/arch/arm/dts/am335x-evm-u-boot.dtsi
> index b6b97ed16d91..16a9f855ad1f 100644
> --- a/arch/arm/dts/am335x-evm-u-boot.dtsi
> +++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
> @@ -3,11 +3,52 @@
>   * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
>   */
>  
> +#include "am33xx-u-boot.dtsi"
>  
> - {
> - status = "disabled";
> +_wkup {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_pinmux {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_pins {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_pins {
> + u-boot,dm-pre-reloc;
>  };
>  
>   {
>   dr_mode = "peripheral";
>  };
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_pins {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + status = "disabled";
> +};
> diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
> index d67f94ad47ba..bfad1a75a456 100644
> --- a/board/ti/am335x/board.c
> +++ b/board/ti/am335x/board.c
> @@ -1054,33 +1054,3 @@ void board_fit_image_post_process(void **p_image, 
> size_t *p_size)
>   secure_boot_verify_image(p_image, p_size);
>  }
>  #endif
> -
> -#if !CONFIG_IS_ENABLED(OF_CONTROL)
> -static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
> - .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
> - .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
> - .cfg.f_min = 40,
> - .cfg.f_max = 5200,
> - .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
> - .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
> -};
> -
> -U_BOOT_DEVICE(am335x_mmc0) = {
> - .name = "omap_hsmmc",
> - .platdata = _mmc0_platdata,
> -};
> -
> -static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
> - .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
> - .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
> - .cfg.f_min = 40,
> - .cfg.f_max = 5200,
> - .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
> - .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
> -};
> -
> -U_BOOT_DEVICE(am335x_mmc1) = {
> - .name = "omap_hsmmc",
> - .platdata = _mmc1_platdata,
> -};
> -#endif

We also need to look at arch/arm/mach-omap2/board.c. Bunch of GPIO and
I2C platdata there.

In general, if we are not able to fit all bootmodes with SPL_OF_CONTROL
enabled, should we remove it and add back platdata or do something else?

Thanks,
Faiz
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Re: [U-Boot] [PATCH] hikey: Take peripherals out of reset during board init

[Peter Griffin]

Hi Mani,

This looks like a bug in the Linux kernel. The kernel driver should be
correctly
handling the reset lines of the I2C or SPI peripheral rather than replying
on
the bootloader to have already taken it out of reset.

Peter.

On Fri, 8 Mar 2019 at 08:57, Manivannan Sadhasivam <
manivannan.sadhasi...@linaro.org> wrote:

> Peripherals like I2C and SPI needs to be taken out of reset during
> board init for functioning properly. Hence, add `hi6220_periph_reset`
> function for doing the same. For instance without this function, I2C
> will fail like below while booting linux:
>
> [0.608033] i2c_designware f710.i2c: Unknown Synopsys component
> type:
> 0x
> [0.621378] i2c_designware f7101000.i2c: Unknown Synopsys component
> type:
> 0x
> [0.633818] i2c_designware f7102000.i2c: Unknown Synopsys component
> type:
> 0x
>
> Signed-off-by: Manivannan Sadhasivam 
> ---
>  board/hisilicon/hikey/hikey.c | 16 
>  1 file changed, 16 insertions(+)
>
> diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
> index 940ae82c45b..f8b8c372bfd 100644
> --- a/board/hisilicon/hikey/hikey.c
> +++ b/board/hisilicon/hikey/hikey.c
> @@ -364,6 +364,20 @@ static void hi6220_pmussi_init(void)
> gpio_direction_output(0, 1);
>  }
>
> +static void hi6220_periph_reset(void)
> +{
> +   u32 data, bits;
> +
> +   /* Bring I2C0/I2C1/I2C2/SPI0 out of reset */
> +   bits = PERI_RST3_I2C0 | PERI_RST3_I2C1 | PERI_RST3_I2C2 |
> PERI_RST3_SSP;
> +   writel(bits, _sc->rst3_dis);
> +
> +   /* Wait until the peripherals are out of reset */
> +   do {
> +   data = readl(_sc->rst3_dis);
> +   } while (data & bits);
> +}
> +
>  int misc_init_r(void)
>  {
> return 0;
> @@ -371,6 +385,8 @@ int misc_init_r(void)
>
>  int board_init(void)
>  {
> +   hi6220_periph_reset();
> +
> return 0;
>  }
>
> --
> 2.17.1
>
>
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[U-Boot] [PATCH] ti: am335x_evm: Enable CONFIG_SPL_OF_CONTROL

[Tom Rini]

Enable support for SPL_OF_CONTROL on this platform.  That means doing a
few things:
- Add u-boot,dm-pre-reloc to a number of nodes
- Drop static platdata in the board file.
- A lot of tweaks to the defconfig.  We remove some things such as
  SPL_USE_ARCH_MEMCPY/SET for space.  Increase our malloc len.
- Drop, for now at least, USB SPL support as it's causing a hang.

Cc: Faiz Abbas 
Cc: Lokesh Vutla 
Signed-off-by: Tom Rini 
---
 arch/arm/dts/am335x-evm-u-boot.dtsi | 45 +++--
 board/ti/am335x/board.c | 30 -
 configs/am335x_evm_defconfig| 14 
 3 files changed, 53 insertions(+), 36 deletions(-)

diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi 
b/arch/arm/dts/am335x-evm-u-boot.dtsi
index b6b97ed16d91..16a9f855ad1f 100644
--- a/arch/arm/dts/am335x-evm-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
@@ -3,11 +3,52 @@
  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
+#include "am33xx-u-boot.dtsi"
 
- {
-   status = "disabled";
+_wkup {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+_pinmux {
+   u-boot,dm-pre-reloc;
+};
+
+_pins {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+_pins {
+   u-boot,dm-pre-reloc;
 };
 
  {
dr_mode = "peripheral";
 };
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+_pins {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "disabled";
+};
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index d67f94ad47ba..bfad1a75a456 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -1054,33 +1054,3 @@ void board_fit_image_post_process(void **p_image, size_t 
*p_size)
secure_boot_verify_image(p_image, p_size);
 }
 #endif
-
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
-   .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
-   .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
-   .cfg.f_min = 40,
-   .cfg.f_max = 5200,
-   .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
-   .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-
-U_BOOT_DEVICE(am335x_mmc0) = {
-   .name = "omap_hsmmc",
-   .platdata = _mmc0_platdata,
-};
-
-static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
-   .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
-   .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
-   .cfg.f_min = 40,
-   .cfg.f_max = 5200,
-   .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
-   .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-
-U_BOOT_DEVICE(am335x_mmc1) = {
-   .name = "omap_hsmmc",
-   .platdata = _mmc1_platdata,
-};
-#endif
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 924116835251..dd690dcb495c 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -1,23 +1,26 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_AM33XX=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run 
findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_LOGLEVEL=3
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_ARCH_MISC_INIT=y
 # CONFIG_SPL_FS_EXT4 is not set
 CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
 CONFIG_SPL_NET_SUPPORT=y
 CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL"
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
 CONFIG_CMD_SPL=y
 CONFIG_CMD_SPL_NAND_OFS=0x0008
 # CONFIG_CMD_FLASH is not set
@@ -28,10 +31,12 @@ CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
 
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk 
am335x-bonegreen am335x-icev2"
+CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_BLK is not set
+CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_NAND=y
@@ -68,5 +73,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
 CONFIG_USB_ETHER=y
 CONFIG_DYNAMIC_CRC_TABLE=y
+CONFIG_SPL_TINY_MEMSET=y
 CONFIG_RSA=y
 CONFIG_LZO=y
-- 
2.7.4

[U-Boot] [PATCHv2 1/2] ti: keystone2: Move CONFIG_ISW_ENTRY_ADDR to a common place

[Tom Rini]

The ISW_ENTRY_ADDR Kconfig option under mach-omap2 isn't a SoC specific
notion but rather "where is our previous stage loaded in memory?"
option.  Make use of this on ARCH_KEYSTONE rather than SPL_TEXT_BASE for
our HS builds that are not using SPL anyhow.

Cc: Vitaly Andrianov 
Cc: Andrew F. Davis 
Cc: Lokesh Vutla 
Signed-off-by: Tom Rini 
---
On a related note, can we please move SRAM_SCRATCH_SPACE_ADDR to a more
fixed location?  The build logic here is going to break again when more
SPL symbols move to Kconfig, thanks!
---
 arch/arm/Kconfig | 15 +++
 arch/arm/mach-omap2/Kconfig  | 15 ---
 configs/k2e_evm_defconfig|  1 +
 configs/k2e_hs_evm_defconfig |  1 +
 configs/k2g_evm_defconfig|  1 +
 configs/k2g_hs_evm_defconfig |  1 +
 configs/k2hk_evm_defconfig   |  1 +
 configs/k2hk_hs_evm_defconfig|  1 +
 configs/k2l_evm_defconfig|  1 +
 configs/k2l_hs_evm_defconfig |  1 +
 include/configs/k2e_evm.h|  4 
 include/configs/k2g_evm.h|  3 ---
 include/configs/k2hk_evm.h   |  3 ---
 include/configs/k2l_evm.h|  3 ---
 include/configs/ti_armv7_keystone2.h |  5 +++--
 15 files changed, 26 insertions(+), 30 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f42eccef80dd..49904cac670e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1465,6 +1465,21 @@ config TI_SECURE_DEVICE
  authenticated) and the code. See the doc/README.ti-secure
  file for further details.
 
+if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
+config ISW_ENTRY_ADDR
+   hex "Address in memory or XIP address of bootloader entry point"
+   default 0x402F4000 if AM43XX
+   default 0x402F0400 if AM33XX
+   default 0x40301350 if OMAP54XX
+   help
+ After any reset, the boot ROM searches the boot media for a valid
+ boot image. For non-XIP devices, the ROM then copies the image into
+ internal memory. For all boot modes, after the ROM processes the
+ boot image it eventually computes the entry point address depending
+ on the device type (secure/non-secure), boot media (xip/non-xip) and
+ image headers.
+endif
+
 source "arch/arm/mach-aspeed/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1cac4437d72c..d29f1ca0b58b 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -167,21 +167,6 @@ config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
  using hardware memory firewalls. This value must be smaller than the
  TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
 
-if AM43XX || AM33XX || OMAP54XX
-config ISW_ENTRY_ADDR
-   hex "Address in memory or XIP address of bootloader entry point"
-   default 0x402F4000 if AM43XX
-   default 0x402F0400 if AM33XX
-   default 0x40301350 if OMAP54XX
-   help
- After any reset, the boot ROM searches the boot media for a valid
- boot image. For non-XIP devices, the ROM then copies the image into
- internal memory. For all boot modes, after the ROM processes the
- boot image it eventually computes the entry point address depending
- on the device type (secure/non-secure), boot media (xip/non-xip) and
- image headers.
-endif
-
 source "arch/arm/mach-omap2/omap3/Kconfig"
 
 source "arch/arm/mach-omap2/omap4/Kconfig"
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index a108f88dfd32..b16740173cf6 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_KEYSTONE=y
+CONFIG_ISW_ENTRY_ADDR=0xC10
 CONFIG_SYS_TEXT_BASE=0xC00
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index 67f6fb1da5f4..682c2f4523dc 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_KEYSTONE=y
+CONFIG_ISW_ENTRY_ADDR=0xC10
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_TEXT_BASE=0xC60
 CONFIG_TI_COMMON_CMD_OPTIONS=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 838b6f14b6d1..7401c4baf811 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_KEYSTONE=y
+CONFIG_ISW_ENTRY_ADDR=0xC0A
 CONFIG_SYS_TEXT_BASE=0xC00
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 93fa2360ad11..42fc68308eda 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_TI_SECURE_DEVICE=y
+CONFIG_ISW_ENTRY_ADDR=0xC0A
 CONFIG_SYS_TEXT_BASE=0xC60
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_TARGET_K2G_EVM=y
diff --git a/configs/k2hk_evm_defconfig 

Re: [U-Boot] [PATCH 01/10] ddr: altera: stratix10: Move SDRAM size check to SDRAM driver

[Ley Foon Tan]

On Tue, Mar 19, 2019 at 5:39 PM Marek Vasut  wrote:
>
> On 3/19/19 4:26 AM, Ley Foon Tan wrote:
> > On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:
> >>
> >> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> >>> Move SDRAM size check to SDRAM driver. sdram_calculate_size()
> >>> is called in SDRAM initialization already, avoid calling
> >>> twice in size check function.
> >>>
> >>> Signed-off-by: Ley Foon Tan 
> >>> ---
> >>>  arch/arm/mach-socfpga/spl_s10.c | 11 ---
> >>>  drivers/ddr/altera/sdram_s10.c  | 15 +++
> >>>  2 files changed, 15 insertions(+), 11 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-socfpga/spl_s10.c 
> >>> b/arch/arm/mach-socfpga/spl_s10.c
> >>> index a3db20a819..a141ffe82a 100644
> >>> --- a/arch/arm/mach-socfpga/spl_s10.c
> >>> +++ b/arch/arm/mach-socfpga/spl_s10.c
> >>> @@ -181,17 +181,6 @@ void board_init_f(ulong dummy)
> >>>   hang();
> >>>   }
> >>>
> >>> - gd->ram_size = sdram_calculate_size();
> >>> - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
> >>> -
> >>> - /* Sanity check ensure correct SDRAM size specified */
> >>> - debug("DDR: Running SDRAM size sanity check\n");
> >>> - if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> >>> - puts("DDR: SDRAM size check failed!\n");
> >>> - hang();
> >>> - }
> >>> - debug("DDR: SDRAM size check passed!\n");
> >>> -
> >>>   mbox_init();
> >>>
> >>>  #ifdef CONFIG_CADENCE_QSPI
> >>> diff --git a/drivers/ddr/altera/sdram_s10.c 
> >>> b/drivers/ddr/altera/sdram_s10.c
> >>> index a48567c109..8895813440 100644
> >>> --- a/drivers/ddr/altera/sdram_s10.c
> >>> +++ b/drivers/ddr/altera/sdram_s10.c
> >>> @@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void)
> >>>SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, 
> >>> false);
> >>>  }
> >>>
> >>> +static void sdram_size_check(void)
> >>> +{
> >>> + /* Sanity check ensure correct SDRAM size specified */
> >>> + debug("DDR: Running SDRAM size sanity check\n");
> >>> + if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> >>> + puts("DDR: SDRAM size check failed!\n");
> >>> + hang();
> >>> + }
> >>> + debug("DDR: SDRAM size check passed!\n");
> >>> +}
> >>> +
> >>>  /**
> >>>   * sdram_mmr_init_full() - Function to initialize SDRAM MMR
> >>>   *
> >>> @@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused)
> >>>   else
> >>>   gd->ram_size = size;
> >>>
> >>> + printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
> >>
> >> Is the type cast needed?
> > Yes, otherwise there is warning.
>
> Maybe the warning is justified and needs to be fixed instead of hidden ?
>

drivers/ddr/altera/sdram_s10.c:461:16: warning: format ‘%d’ expects
argument of type ‘int’, but argument 2 has type ‘phys_size_t {aka
volatile long long unsigned int}’ [-Wformat=]
  printf("DDR: %d MiB\n", gd->ram_size >> 20);
   ~^ ~~

Regards
Ley Foon
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Re: [U-Boot] [PATCH v2] arm: fix hvc call

[Ibai Erkiaga Elorza]

Hi Tom

> -Original Message-
> From: Tom Rini 
> Sent: 15 March 2019 16:08
> To: Ibai Erkiaga Elorza 
> Cc: Alexander Graf ; u-boot@lists.denx.de; Sumit Garg
> ; Heinrich Schuchardt ; Albert
> Aribaud 
> Subject: Re: [U-Boot][PATCH v2] arm: fix hvc call
> 
> On Fri, Mar 15, 2019 at 12:13:11PM +, Ibai Erkiaga Elorza wrote:
> > Hi Alex,
> >
> > > -Original Message-
> > > From: Alexander Graf 
> > > Sent: 25 February 2019 13:09
> > > To: Ibai Erkiaga Elorza 
> > > Cc: u-boot@lists.denx.de; Sumit Garg ;
> > > Heinrich Schuchardt ; Tom Rini
> > > ; Albert Aribaud 
> > > Subject: Re: [U-Boot][PATCH v2] arm: fix hvc call
> > >
> > >
> > >
> > > > Am 25.02.2019 um 02:11 schrieb Ibai Erkiaga  > > elo...@xilinx.com>:
> > > >
> > > > HVC call makes use of 6 mandatory arguments rather than 7 in the
> > > > same way as SMC calls. The 7th argument is optional (Client ID)
> > > > for both HVC and SMC but is implemented as 16-bit parameter and
> > > > register R7 or W7. The aim of this patch is just fix compilation
> > > > error due to an invalid asm code in the HVC call so that's why the 7th
> argument is removed.
> > > >
> > > > The issue does not report any error in a normal build as hvc_call
> > > > is not used at all and is optimized by the compiler. Using -O0
> > > > triggers the error so the patch is intended to fix issues on a
> > > > ongoing effor to build U-Boot with -O0.
> > > >
> > > > Signed-off-by: Ibai Erkiaga 
> > >
> > > Reviewed-by: Alexander Graf 
> >
> > Thanks for the review. Do I need to CC somebody else to the patch be
> accepted?
> 
> No, but I'm inclined currently to take for for the next release rather than 
> right
> now, unless there's an important argument I'm missing?  Which happens more
> than I'd care to admit ;)
> 
No rush, I'm pretty new contributor and just wondering if something else was 
missing after Alexander's Review.

> --
> Tom

Ibai
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Re: [U-Boot] [PATCH 10/10] ddr: altera: Stratix10: Add ECC memory scrubbing

[Ley Foon Tan]

On Tue, Mar 19, 2019 at 5:39 PM Marek Vasut  wrote:
>
> On 3/19/19 4:14 AM, Ley Foon Tan wrote:
> > On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:
> >>
> >> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> >>> Scrub memory content if ECC is enabled and it is not
> >>> from warm reset boot.
> >>>
> >>> Enable icache and dcache before scrub memory
> >>> and use "DC ZVA" instruction to clear memory
> >>> to zeros. This instruction writes a cache line
> >>> at a time and it can prevent false ECC error
> >>> trigger if write cache line partially.
> >>>
> >>> Signed-off-by: Ley Foon Tan 
> >>> ---
> >>>  .../arm/mach-socfpga/include/mach/sdram_s10.h |  9 +++
> >>>  drivers/ddr/altera/sdram_s10.c| 76 +++
> >>>  2 files changed, 85 insertions(+)
> >>>
> >>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h 
> >>> b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> >>> index 89e355010d..354f80bfce 100644
> >>> --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> >>> +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> >>> @@ -23,6 +23,7 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
> >>> phys_size_t bank_size[]);
> >>>  #define ECCCTRL1 0x100
> >>>  #define ECCCTRL2 0x104
> >>>  #define ERRINTEN 0x110
> >>> +#define ERRINTENS0x114
> >>>  #define INTMODE  0x11c
> >>>  #define INTSTAT  0x120
> >>>  #define AUTOWB_CORRADDR  0x138
> >>> @@ -53,6 +54,10 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
> >>> phys_size_t bank_size[]);
> >>>  #define DDR_HMC_SEQ2CORE_INT_RESP_MASK   BIT(3)
> >>>  #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK  0x001f1f1f
> >>>
> >>> +#define  DDR_HMC_ERRINTEN_INTMASK\
> >>> + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |\
> >>> +  DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
> >>> +
> >>>  /* NOC DDR scheduler */
> >>>  #define DDR_SCH_ID_COREID0
> >>>  #define DDR_SCH_ID_REVID 0x4
> >>> @@ -181,4 +186,8 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
> >>> phys_size_t bank_size[]);
> >>>  #define CALTIMING9_CFG_4_ACT_TO_ACT(x)   \
> >>>   (((x) >> 0) & 0xFF)
> >>>
> >>> +/* Firewall DDR scheduler MPFE */
> >>> +#define FW_HMC_ADAPTOR_REG_ADDR  0xf8020004
> >>> +#define FW_HMC_ADAPTOR_MPU_MASK  BIT(0)
> >>> +
> >>>  #endif /* _SDRAM_S10_H_ */
> >>> diff --git a/drivers/ddr/altera/sdram_s10.c 
> >>> b/drivers/ddr/altera/sdram_s10.c
> >>> index ae4e5ea2fd..2c691d3bee 100644
> >>> --- a/drivers/ddr/altera/sdram_s10.c
> >>> +++ b/drivers/ddr/altera/sdram_s10.c
> >>> @@ -22,6 +22,8 @@ static const struct socfpga_system_manager *sysmgr_regs 
> >>> =
> >>>
> >>>  #define DDR_CONFIG(A, B, C, R)   (((A) << 24) | ((B) << 16) | ((C) 
> >>> << 8) | (R))
> >>>
> >>> +#define PGTABLE_OFF  0x4000
> >>> +
> >>>  /* The followring are the supported configurations */
> >>>  u32 ddr_config[] = {
> >>>   /* DDR_CONFIG(Address order,Bank,Column,Row) */
> >>> @@ -135,6 +137,71 @@ static int poll_hmc_clock_status(void)
> >>>SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, 
> >>> false);
> >>>  }
> >>>
> >>> +static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
> >>> +{
> >>> + phys_size_t i;
> >>> +
> >>> + if (addr % CONFIG_SYS_CACHELINE_SIZE) {
> >>> + printf("DDR: address 0x%lx not cacheline size aligned.\n",
> >>> +(ulong)addr);
> >>
> >> Is the cast needed ?
> > Yes, SPL doesn't support %llx, we need cast to ulong %lx.
>
> But that doesn't work for 64bit addresses ?
> Isn't that limitation of tiny printf implementation instead of SPL ?
>
%lx still work for 64 bit address.

Yes, I think it is limitation of  tiny printf in SPL.

Regards
Ley Foon
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[U-Boot] [PATCH] ARM: HYP/non-sec: Don't enable ARMV7_LPAE for old sunxi kernels

[Jonathan Liu]

Old sunxi kernels fail to boot with ARMV7_LPAE enabled.

Signed-off-by: Jonathan Liu 
---
 arch/arm/cpu/armv7/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 73d57a2aae..cdb7e402b4 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -53,7 +53,7 @@ config ARMV7_PSCI_NR_CPUS
 config ARMV7_LPAE
bool "Use LPAE page table format" if EXPERT
depends on CPU_V7A
-   default y if ARMV7_VIRT
+   default y if ARMV7_VIRT && !OLD_SUNXI_KERNEL_COMPAT
---help---
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
-- 
2.21.0

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Re: [U-Boot] [PATCH 06/10] board: altera: Stratix10: Add ft_board_setup()

[Ley Foon Tan]

On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:
>
> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> > Add ft_board_setup() function to setup memory banks before
> > boot to Linux.
>
> Shouldn't bootm/booti be doing just that already ?
Don't need this if we use fdtdec_setup_memory_banksize().

>
> > Signed-off-by: Ley Foon Tan 
> > ---
> >  board/altera/stratix10-socdk/socfpga.c | 25 +
> >  1 file changed, 25 insertions(+)
> >
> > diff --git a/board/altera/stratix10-socdk/socfpga.c 
> > b/board/altera/stratix10-socdk/socfpga.c
> > index 99c10d313c..ca6e0e9085 100644
> > --- a/board/altera/stratix10-socdk/socfpga.c
> > +++ b/board/altera/stratix10-socdk/socfpga.c
> > @@ -5,6 +5,7 @@
> >   */
> >
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >
> > @@ -17,3 +18,27 @@ ulong board_get_usable_ram_top(ulong total_size)
> >   return sdram_calculate_size();
> >  }
> >  #endif
> > +
> > +#ifdef CONFIG_OF_BOARD_SETUP
> > +int ft_board_setup(void *blob, bd_t *bd)
> > +{
> > + int ret = 0;
> > +#ifdef CONFIG_OF_LIBFDT
> > + int bank;
> > + int actual_bank = 0;
> > + u64 start[CONFIG_NR_DRAM_BANKS];
> > + u64 size[CONFIG_NR_DRAM_BANKS];
> > +
> > + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> > + if (bd->bi_dram[bank].size) {
> > + start[actual_bank] = bd->bi_dram[bank].start;
> > + size[actual_bank++] = bd->bi_dram[bank].size;
> > + }
> > + }
> > +
> > + ret = fdt_fixup_memory_banks(blob, start, size, actual_bank);
> > +#endif /* CONFIG_OF_LIBFDT */
> > +
> > + return ret;
> > +}
> > +#endif
> >
Regards
Ley Foon
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Re: [U-Boot] [PATCH 05/10] board: altera: Stratix10: Add board_get_usable_ram_top()

[Ley Foon Tan]

On Tue, Mar 12, 2019 at 10:40 PM Marek Vasut  wrote:
>
> On 3/12/19 3:33 PM, Westergreen, Dalon wrote:
> > On Tue, 2019-03-12 at 11:46 +0100, Marek Vasut wrote:
> >> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> >>> Add board_get_usable_ram_top() function. Limit maximum usable
> >>> ram top to 2GB.
> >>
> >> Why ? There are ARM64 platforms which can access the entire DRAM range
> >> just fine, what's the problem ?
> >>
> >
> > The issue is the gap in memory between 2GB and 4GB.  There is some trickery
> > you can use to gain access to the memory in that range, but in general, you
> > dont have access.  I believe just setting the banks up in the dts will
> > resolve this.
>
> E.g. the R8A779{5..9}* platforms also have gaps in memory and it all
> works fine . So unless there's some other specialty, there should be no
> problem.
>
Yes, we don't need this.

Regards
Ley Foon
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Re: [U-Boot] [PATCH 01/10] ddr: altera: stratix10: Move SDRAM size check to SDRAM driver

[Ley Foon Tan]

On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:
>
> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> > Move SDRAM size check to SDRAM driver. sdram_calculate_size()
> > is called in SDRAM initialization already, avoid calling
> > twice in size check function.
> >
> > Signed-off-by: Ley Foon Tan 
> > ---
> >  arch/arm/mach-socfpga/spl_s10.c | 11 ---
> >  drivers/ddr/altera/sdram_s10.c  | 15 +++
> >  2 files changed, 15 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/spl_s10.c 
> > b/arch/arm/mach-socfpga/spl_s10.c
> > index a3db20a819..a141ffe82a 100644
> > --- a/arch/arm/mach-socfpga/spl_s10.c
> > +++ b/arch/arm/mach-socfpga/spl_s10.c
> > @@ -181,17 +181,6 @@ void board_init_f(ulong dummy)
> >   hang();
> >   }
> >
> > - gd->ram_size = sdram_calculate_size();
> > - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
> > -
> > - /* Sanity check ensure correct SDRAM size specified */
> > - debug("DDR: Running SDRAM size sanity check\n");
> > - if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> > - puts("DDR: SDRAM size check failed!\n");
> > - hang();
> > - }
> > - debug("DDR: SDRAM size check passed!\n");
> > -
> >   mbox_init();
> >
> >  #ifdef CONFIG_CADENCE_QSPI
> > diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> > index a48567c109..8895813440 100644
> > --- a/drivers/ddr/altera/sdram_s10.c
> > +++ b/drivers/ddr/altera/sdram_s10.c
> > @@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void)
> >SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, 
> > false);
> >  }
> >
> > +static void sdram_size_check(void)
> > +{
> > + /* Sanity check ensure correct SDRAM size specified */
> > + debug("DDR: Running SDRAM size sanity check\n");
> > + if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> > + puts("DDR: SDRAM size check failed!\n");
> > + hang();
> > + }
> > + debug("DDR: SDRAM size check passed!\n");
> > +}
> > +
> >  /**
> >   * sdram_mmr_init_full() - Function to initialize SDRAM MMR
> >   *
> > @@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused)
> >   else
> >   gd->ram_size = size;
> >
> > + printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
>
> Is the type cast needed?
Yes, otherwise there is warning.
>
> >   /* Enable or disable the SDRAM ECC */
> >   if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
> >   setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
> > @@ -361,6 +374,8 @@ int sdram_mmr_init_full(unsigned int unused)
> > DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
> >   }
> >
> > + sdram_size_check();
> > +
> >   debug("DDR: HMC init success\n");
> >   return 0;
> >  }
> >
>
Regards
Ley Foon
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Re: [U-Boot] [PATCH 10/10] ddr: altera: Stratix10: Add ECC memory scrubbing

[Ley Foon Tan]

On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:
>
> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> > Scrub memory content if ECC is enabled and it is not
> > from warm reset boot.
> >
> > Enable icache and dcache before scrub memory
> > and use "DC ZVA" instruction to clear memory
> > to zeros. This instruction writes a cache line
> > at a time and it can prevent false ECC error
> > trigger if write cache line partially.
> >
> > Signed-off-by: Ley Foon Tan 
> > ---
> >  .../arm/mach-socfpga/include/mach/sdram_s10.h |  9 +++
> >  drivers/ddr/altera/sdram_s10.c| 76 +++
> >  2 files changed, 85 insertions(+)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h 
> > b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> > index 89e355010d..354f80bfce 100644
> > --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> > @@ -23,6 +23,7 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
> > phys_size_t bank_size[]);
> >  #define ECCCTRL1 0x100
> >  #define ECCCTRL2 0x104
> >  #define ERRINTEN 0x110
> > +#define ERRINTENS0x114
> >  #define INTMODE  0x11c
> >  #define INTSTAT  0x120
> >  #define AUTOWB_CORRADDR  0x138
> > @@ -53,6 +54,10 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
> > phys_size_t bank_size[]);
> >  #define DDR_HMC_SEQ2CORE_INT_RESP_MASK   BIT(3)
> >  #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK  0x001f1f1f
> >
> > +#define  DDR_HMC_ERRINTEN_INTMASK\
> > + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |\
> > +  DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
> > +
> >  /* NOC DDR scheduler */
> >  #define DDR_SCH_ID_COREID0
> >  #define DDR_SCH_ID_REVID 0x4
> > @@ -181,4 +186,8 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
> > phys_size_t bank_size[]);
> >  #define CALTIMING9_CFG_4_ACT_TO_ACT(x)   \
> >   (((x) >> 0) & 0xFF)
> >
> > +/* Firewall DDR scheduler MPFE */
> > +#define FW_HMC_ADAPTOR_REG_ADDR  0xf8020004
> > +#define FW_HMC_ADAPTOR_MPU_MASK  BIT(0)
> > +
> >  #endif /* _SDRAM_S10_H_ */
> > diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> > index ae4e5ea2fd..2c691d3bee 100644
> > --- a/drivers/ddr/altera/sdram_s10.c
> > +++ b/drivers/ddr/altera/sdram_s10.c
> > @@ -22,6 +22,8 @@ static const struct socfpga_system_manager *sysmgr_regs =
> >
> >  #define DDR_CONFIG(A, B, C, R)   (((A) << 24) | ((B) << 16) | ((C) << 
> > 8) | (R))
> >
> > +#define PGTABLE_OFF  0x4000
> > +
> >  /* The followring are the supported configurations */
> >  u32 ddr_config[] = {
> >   /* DDR_CONFIG(Address order,Bank,Column,Row) */
> > @@ -135,6 +137,71 @@ static int poll_hmc_clock_status(void)
> >SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, 
> > false);
> >  }
> >
> > +static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
> > +{
> > + phys_size_t i;
> > +
> > + if (addr % CONFIG_SYS_CACHELINE_SIZE) {
> > + printf("DDR: address 0x%lx not cacheline size aligned.\n",
> > +(ulong)addr);
>
> Is the cast needed ?
Yes, SPL doesn't support %llx, we need cast to ulong %lx.
>
> > + hang();
> > + }
> > +
> > + if (size % CONFIG_SYS_CACHELINE_SIZE) {
> > + printf("DDR: size 0x%lx not multiple of cacheline size\n",
> > +(ulong)size);
> > + hang();
> > + }
> > +
> > + /* Use DC ZVA instruction to clear memory to zeros by a cache line */
> > + for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
> > + asm("dc zva, %0"
> > +  :
> > +  : "r"(addr));
>
> Should be asm volatile, so the compiler won't move this around.
Okay.
> Also, you want memory clobber here I think ?
Yes, will add "memory" clobber here.
>
> > + addr += CONFIG_SYS_CACHELINE_SIZE;
> > + }
> > +}
> > +
> > +static void sdram_init_ecc_bits(phys_addr_t *bank_start, phys_size_t 
> > *bank_size)
> > +{
> > + phys_size_t size, size_init;
> > + phys_addr_t start_addr;
> > + int bank;
> > + unsigned int start = get_timer(0);
> > +
> > + icache_enable();
> > +
> > + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> > + start_addr = bank_start[bank];
> > + size = bank_size[bank];
> > +
> > + if (bank == 0) {
> > + /* Initialize small block for page table */
> > + memset((void *)start_addr, 0,
> > +PGTABLE_SIZE + PGTABLE_OFF);
> > + gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
> > + gd->arch.tlb_size = PGTABLE_SIZE;
> > +   

Re: [U-Boot] [PATCH v3 3/7] common: Implement A/B metadata

[Eugeniu Rosca]

Hi Praneeth, Igor,

On Mon, Mar 18, 2019 at 04:20:16PM -0500, Bajjuri, Praneeth wrote:
> Eugeniu,
[..]
> Not a glitch, Igor's linaro email id is no longer active. He might respond
> with updated email
> address soon.

Great news. Looking forward for v4 of this series.

Many thanks,
Eugeniu.
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[U-Boot] [PATCH] rsa: check that pointer checksum isn't NULL before using it

[Philippe Reynes]

The pointer checksum were used before checking that it
isn't NULL. We move the code that use it after the check.

Reported-by: Coverity (CID: 185835)
Signed-off-by: Philippe Reynes 
---
 lib/rsa/rsa-verify.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index 9734f6d..287fcc4 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -295,7 +295,7 @@ static int rsa_verify_key(struct image_sign_info *info,
 #endif
struct checksum_algo *checksum = info->checksum;
struct padding_algo *padding = info->padding;
-   int hash_len = checksum->checksum_len;
+   int hash_len;
 
if (!prop || !sig || !hash || !checksum)
return -EIO;
@@ -315,6 +315,7 @@ static int rsa_verify_key(struct image_sign_info *info,
}
 
uint8_t buf[sig_len];
+   hash_len = checksum->checksum_len;
 
 #if !defined(USE_HOSTCC)
ret = uclass_get_device(UCLASS_MOD_EXP, 0, _exp_dev);
-- 
2.7.4

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Re: [U-Boot] [PATCH 01/10] ddr: altera: stratix10: Move SDRAM size check to SDRAM driver

[Marek Vasut]

On 3/19/19 10:46 AM, Ley Foon Tan wrote:
> On Tue, Mar 19, 2019 at 5:39 PM Marek Vasut  wrote:
>>
>> On 3/19/19 4:26 AM, Ley Foon Tan wrote:
>>> On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:

 On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> Move SDRAM size check to SDRAM driver. sdram_calculate_size()
> is called in SDRAM initialization already, avoid calling
> twice in size check function.
>
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/spl_s10.c | 11 ---
>  drivers/ddr/altera/sdram_s10.c  | 15 +++
>  2 files changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/spl_s10.c 
> b/arch/arm/mach-socfpga/spl_s10.c
> index a3db20a819..a141ffe82a 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -181,17 +181,6 @@ void board_init_f(ulong dummy)
>   hang();
>   }
>
> - gd->ram_size = sdram_calculate_size();
> - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
> -
> - /* Sanity check ensure correct SDRAM size specified */
> - debug("DDR: Running SDRAM size sanity check\n");
> - if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> - puts("DDR: SDRAM size check failed!\n");
> - hang();
> - }
> - debug("DDR: SDRAM size check passed!\n");
> -
>   mbox_init();
>
>  #ifdef CONFIG_CADENCE_QSPI
> diff --git a/drivers/ddr/altera/sdram_s10.c 
> b/drivers/ddr/altera/sdram_s10.c
> index a48567c109..8895813440 100644
> --- a/drivers/ddr/altera/sdram_s10.c
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void)
>SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, 
> false);
>  }
>
> +static void sdram_size_check(void)
> +{
> + /* Sanity check ensure correct SDRAM size specified */
> + debug("DDR: Running SDRAM size sanity check\n");
> + if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> + puts("DDR: SDRAM size check failed!\n");
> + hang();
> + }
> + debug("DDR: SDRAM size check passed!\n");
> +}
> +
>  /**
>   * sdram_mmr_init_full() - Function to initialize SDRAM MMR
>   *
> @@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused)
>   else
>   gd->ram_size = size;
>
> + printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));

 Is the type cast needed?
>>> Yes, otherwise there is warning.
>>
>> Maybe the warning is justified and needs to be fixed instead of hidden ?
>>
> 
> drivers/ddr/altera/sdram_s10.c:461:16: warning: format ‘%d’ expects
> argument of type ‘int’, but argument 2 has type ‘phys_size_t {aka
> volatile long long unsigned int}’ [-Wformat=]
>   printf("DDR: %d MiB\n", gd->ram_size >> 20);
>~^ ~~

That's %lld then.

-- 
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Marek Vasut
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Re: [U-Boot] [PATCH v3] usb: host: Print device name when scanning

[Marek Vasut]

On 3/19/19 10:01 AM, Ismael Luceno Cortes wrote:
> On 19/Mar/2019 02:14, Marek Vasut wrote:
>> On 3/18/19 2:21 PM, Ismael Luceno Cortes wrote:
>>> Drop the counter, it has no meaning other than being the order in which
>>> the interface is found; the name assigned to the USB host controller
>>> interface is a better indicator.
>>>
>>> Example of the original output:
 USB0:   USB EHCI 1.10
 scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
>>>
>>> Patched output:
 Bus usb@ee080100:   USB EHCI 1.10
 scanning bus 0 for devices... 2 USB Device(s) found
>> ^
>> '-- here it still says 0, why ?
>> it's not very consistent :)
> 
> Good point, I'll remove that one, it seems it used to be the same thing
> but now comes from dev->seq.

Thanks!

-- 
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Re: [U-Boot] Odroid U3 - Upgrade to latest u-boot kernel load fails.

[Anand Moon]

Hi Krzysztof,


On Tue, 19 Mar 2019 at 01:54, Anand Moon  wrote:
>
> Hi Krzysztof,
>
> On Mon, 18 Mar 2019 at 23:33, Krzysztof Kozlowski  wrote:
> >
> > On Mon, 18 Mar 2019 at 18:49, Anand Moon  wrote:
> > >
> > > Hi Krzysztof,
> > >
> > > On Mon, 18 Mar 2019 at 18:20, Krzysztof Kozlowski  wrote:
> > > >
> > > > On Mon, 18 Mar 2019 at 13:32, Anand Moon  wrote:
> > > > >
> > > > > Hi Krzysztof / Marek,
> > > > >
> > > > > After I update the latest u-boot on my Odroud U3+ it fails to load the
> > > > > kernel it hangs.
> > > > > I am using Archlinux on Odroid U3.
> > > > >
> > > > > U-Boot 2019.04-rc3-00131-g8303467e80d-dirty (Mar 18 2019 - 12:12:23 
> > > > > +)
> > > > >
> > > > > CPU:   Exynos4412 @ 1 GHz
> > > > > Model: Odroid based on Exynos4412
> > > > > Type:  u3
> > > > > DRAM:  2 GiB
> > > > > LDO20@VDDQ_EMMC_1.8V: set 180 uV; enabling
> > > > > LDO22@VDDQ_EMMC_2.8V: set 280 uV; enabling
> > > > > LDO21@TFLASH_2.8V: set 280 uV; enabling
> > > > > MMC:   SAMSUNG SDHCI: 1, EXYNOS DWMMC: 0
> > > > > Loading Environment from MMC... Card did not respond to voltage 
> > > > > select!
> > > > > *** Warning - No block device, using default environment
> > > > >
> > > > > Net:   No ethernet found.
> > > > > Hit any key to stop autoboot:  0
> > > > > switch to partitions #0, OK
> > > > > mmc1 is current device
> > > > > Scanning mmc 1:1...
> > > > > Found U-Boot script /boot/boot.scr
> > > > > 769 bytes read in 6 ms (125 KiB/s)
> > > > > ## Executing script at 4200
> > > > > 6901856 bytes read in 253 ms (26 MiB/s)
> > > > > 53078 bytes read in 19 ms (2.7 MiB/s)
> > > > > 6590950 bytes read in 240 ms (26.2 MiB/s)
> > > > > Kernel image @ 0x4100 [ 0x00 - 0x695060 ]
> > > > > ## Flattened Device Tree blob at 4080
> > > > >Booting using the fdt blob at 0x4080
> > > > >Loading Ramdisk to 4f9b6000, end 41e6 ... OK
> > > > >Loading Device Tree to 4f9a6000, end 4f9b5f55 ... OK
> > > > >
> > > > > Starting kernel ...
> > > >
> > > > Can you attach your boot.init file (the source of boot.scr)?
> > > >
> > > > By the size of DTB you can see that different DTB is loaded. I assume
> > > > you tried to boot the same kernel, then it could mean that boardname
> > > > was used instead of board_name to choose DTB. Suspicious is that
> > > > kernel size also differs... so maybe you booted something else? As
> > > > usual debugging practice, reduce number of unknown factors. Do not
> > > > change kernel and U-Boot at the same time.
> > > >
> > > > Also, you can try reverting commit e6b1467081d3 ("arm: exynos: Remove
> > > > duplicated "boardname" env setting") and see if it helps. Or just try
> > > > to bisect around changes coming from u-boot samsung tree. Try booting
> > > > v2019.01 and paste the results as well.
> > > >
> > > > Best regards,
> > > > Krzysztof
> > > >
> > >
> > > I have tested with pre-compiled image and the cross compiled kernel image
> > > both failed to load the kernel.
> > >
> > > No revert of the commit e6b1467081d3 did not help.
> > >
> > > Yes it seem strange that that load address is changes some how in the 
> > > u-boot env
> > >
> > > printenv setting of the latest u-boot U-Boot
> > > 2019.04-rc3-00131-g8303467e80d-dirty
> > > [0] https://pastebin.com/1Hgc5xxC  (newu-boot.txt)
> > >
> > > printenv setting for the old u-boot.  U-Boot 2018.01-1
> > > [1] https://pastebin.com/wD6zK6eG(oldu-boot.txt)
> > >
> > > Attach is the boot.txt (boot.scr), also the u-boot env old and u-boot-env 
> > > new
> >
> > And does 2019.01 work?
> >
> > Krzysztof
>
> It looks like Archlinux uboot for Odroid U3 set some extra environment 
> variable to make this work.
>
> [0] 
> https://github.com/archlinuxarm/PKGBUILDs/blob/master/alarm/uboot-odroid/0001-Convert-odroid-to-use-distro_bootcmd.patch
> [1] 
> https://github.com/archlinuxarm/PKGBUILDs/blob/master/alarm/uboot-odroid/0002-odroid-x-support.patch
>
> I gave these patches a try but no success
>
> Best Regards
> -Anand

If found out the commit that break the boot on Odroid U3
Revert of below commit breaks the booting of the kernel.

From: Seung-Woo Kim 
Date: Tue, 20 Nov 2018 14:54:39 +0900
Subject: [PATCH] Revert "arm: config: fix default console only to specify the
 device"

This reverts commit 232ed3ca534708527a9515c7c41bc3542949525c.

In exynos boards, ${console} is used to set bootargs but it sets
without "console=", so CONFIG_DEFAULT_CONSOLE for these boards is
designated with "console=" but it is removed. So revert the commit.

References for using ${console} in
   board/samsung/common/bootscripts/autoboot.cmd
   board/samsung/common/bootscripts/bootzimg.cmd

Please let me know it how to resolve this issue.

Best Regards
-Anand
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Re: [U-Boot] [PATCH 10/10] ddr: altera: Stratix10: Add ECC memory scrubbing

[Marek Vasut]

On 3/19/19 4:14 AM, Ley Foon Tan wrote:
> On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:
>>
>> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
>>> Scrub memory content if ECC is enabled and it is not
>>> from warm reset boot.
>>>
>>> Enable icache and dcache before scrub memory
>>> and use "DC ZVA" instruction to clear memory
>>> to zeros. This instruction writes a cache line
>>> at a time and it can prevent false ECC error
>>> trigger if write cache line partially.
>>>
>>> Signed-off-by: Ley Foon Tan 
>>> ---
>>>  .../arm/mach-socfpga/include/mach/sdram_s10.h |  9 +++
>>>  drivers/ddr/altera/sdram_s10.c| 76 +++
>>>  2 files changed, 85 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h 
>>> b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
>>> index 89e355010d..354f80bfce 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
>>> @@ -23,6 +23,7 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
>>> phys_size_t bank_size[]);
>>>  #define ECCCTRL1 0x100
>>>  #define ECCCTRL2 0x104
>>>  #define ERRINTEN 0x110
>>> +#define ERRINTENS0x114
>>>  #define INTMODE  0x11c
>>>  #define INTSTAT  0x120
>>>  #define AUTOWB_CORRADDR  0x138
>>> @@ -53,6 +54,10 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
>>> phys_size_t bank_size[]);
>>>  #define DDR_HMC_SEQ2CORE_INT_RESP_MASK   BIT(3)
>>>  #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK  0x001f1f1f
>>>
>>> +#define  DDR_HMC_ERRINTEN_INTMASK\
>>> + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |\
>>> +  DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
>>> +
>>>  /* NOC DDR scheduler */
>>>  #define DDR_SCH_ID_COREID0
>>>  #define DDR_SCH_ID_REVID 0x4
>>> @@ -181,4 +186,8 @@ void setup_memory_banks(phys_addr_t bank_addr[], 
>>> phys_size_t bank_size[]);
>>>  #define CALTIMING9_CFG_4_ACT_TO_ACT(x)   \
>>>   (((x) >> 0) & 0xFF)
>>>
>>> +/* Firewall DDR scheduler MPFE */
>>> +#define FW_HMC_ADAPTOR_REG_ADDR  0xf8020004
>>> +#define FW_HMC_ADAPTOR_MPU_MASK  BIT(0)
>>> +
>>>  #endif /* _SDRAM_S10_H_ */
>>> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
>>> index ae4e5ea2fd..2c691d3bee 100644
>>> --- a/drivers/ddr/altera/sdram_s10.c
>>> +++ b/drivers/ddr/altera/sdram_s10.c
>>> @@ -22,6 +22,8 @@ static const struct socfpga_system_manager *sysmgr_regs =
>>>
>>>  #define DDR_CONFIG(A, B, C, R)   (((A) << 24) | ((B) << 16) | ((C) << 
>>> 8) | (R))
>>>
>>> +#define PGTABLE_OFF  0x4000
>>> +
>>>  /* The followring are the supported configurations */
>>>  u32 ddr_config[] = {
>>>   /* DDR_CONFIG(Address order,Bank,Column,Row) */
>>> @@ -135,6 +137,71 @@ static int poll_hmc_clock_status(void)
>>>SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, 
>>> false);
>>>  }
>>>
>>> +static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
>>> +{
>>> + phys_size_t i;
>>> +
>>> + if (addr % CONFIG_SYS_CACHELINE_SIZE) {
>>> + printf("DDR: address 0x%lx not cacheline size aligned.\n",
>>> +(ulong)addr);
>>
>> Is the cast needed ?
> Yes, SPL doesn't support %llx, we need cast to ulong %lx.

But that doesn't work for 64bit addresses ?
Isn't that limitation of tiny printf implementation instead of SPL ?

[...]

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 01/10] ddr: altera: stratix10: Move SDRAM size check to SDRAM driver

[Marek Vasut]

On 3/19/19 4:26 AM, Ley Foon Tan wrote:
> On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut  wrote:
>>
>> On 3/12/19 9:31 AM, Ley Foon Tan wrote:
>>> Move SDRAM size check to SDRAM driver. sdram_calculate_size()
>>> is called in SDRAM initialization already, avoid calling
>>> twice in size check function.
>>>
>>> Signed-off-by: Ley Foon Tan 
>>> ---
>>>  arch/arm/mach-socfpga/spl_s10.c | 11 ---
>>>  drivers/ddr/altera/sdram_s10.c  | 15 +++
>>>  2 files changed, 15 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/spl_s10.c 
>>> b/arch/arm/mach-socfpga/spl_s10.c
>>> index a3db20a819..a141ffe82a 100644
>>> --- a/arch/arm/mach-socfpga/spl_s10.c
>>> +++ b/arch/arm/mach-socfpga/spl_s10.c
>>> @@ -181,17 +181,6 @@ void board_init_f(ulong dummy)
>>>   hang();
>>>   }
>>>
>>> - gd->ram_size = sdram_calculate_size();
>>> - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
>>> -
>>> - /* Sanity check ensure correct SDRAM size specified */
>>> - debug("DDR: Running SDRAM size sanity check\n");
>>> - if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
>>> - puts("DDR: SDRAM size check failed!\n");
>>> - hang();
>>> - }
>>> - debug("DDR: SDRAM size check passed!\n");
>>> -
>>>   mbox_init();
>>>
>>>  #ifdef CONFIG_CADENCE_QSPI
>>> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
>>> index a48567c109..8895813440 100644
>>> --- a/drivers/ddr/altera/sdram_s10.c
>>> +++ b/drivers/ddr/altera/sdram_s10.c
>>> @@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void)
>>>SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, 
>>> false);
>>>  }
>>>
>>> +static void sdram_size_check(void)
>>> +{
>>> + /* Sanity check ensure correct SDRAM size specified */
>>> + debug("DDR: Running SDRAM size sanity check\n");
>>> + if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
>>> + puts("DDR: SDRAM size check failed!\n");
>>> + hang();
>>> + }
>>> + debug("DDR: SDRAM size check passed!\n");
>>> +}
>>> +
>>>  /**
>>>   * sdram_mmr_init_full() - Function to initialize SDRAM MMR
>>>   *
>>> @@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused)
>>>   else
>>>   gd->ram_size = size;
>>>
>>> + printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
>>
>> Is the type cast needed?
> Yes, otherwise there is warning.

Maybe the warning is justified and needs to be fixed instead of hidden ?

[...]

-- 
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Marek Vasut
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Re: [U-Boot] [PATCH v2] ARM: kirkwood: disable dcache for Kirkwood boards

[Stefan Roese]

Hi Leigh,

On 19.03.19 10:29, Leigh Brown wrote:




 While collecting the queued fixes for the upcoming release, I do
 have one question regarding this Kirkwood cache issue (I don't
have
 such a board here, so I can't test anything):

 Do we need this patch applied [1], if the patch from this thread
is
 applied [2]?

 Thanks,
 Stefan

 [1] http://patchwork.ozlabs.org/patch/1048863/
 [2] http://patchwork.ozlabs.org/patch/1057716/


I'm pretty sure you just need [2]. I've tested with just that on it's
own and Ethernet works on the kirkwood db. Functionally it's the same
change as Michael's just for more boards.

Leigh, can you see if [2] above works for you?


Patch [1] from Leigh also removes icache_enable() in
arch/arm/mach-kirkwood/cpu.c.

Not sure if this is still needed? Did any of you run into issues with
[1] not applied but with CONFIG_SYS_DCACHE_OFF set?


When the cache consolidation patch was applied, it added code to enable
the
icache much earlier in the process.  Therefore, this line of code to
enable
it became superfluous (assuming enabling the icache multiple times does
nothing).

I'd suggest removing it if you agree with that statement, to reduce
possible future confusion.


You mean to remove the icache_enable() call in arch/arm/mach-kirkwood/cpu.c?
Yes, with your explanation above I agree with it. Unfortunately your patch
also sets CONFIG_SYS_DCACHE_OFF for dreamplug which is not needed any more
with Chris's generic approach for Kirkwood. Also I find your patch subject:

Commit "ARM: CPU: arm926ejs: Consolidate cache routines to common file" breaks 
u-boot on Dreamplug

not optimal. Could you please send a new patch with a short subject and
a small commit message with the background (icache is enabled earlier
in the common code now) to the list? That would be great.
 
Thanks,

Stefan
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Re: [U-Boot] [PATCH v2] ARM: kirkwood: disable dcache for Kirkwood boards

[Leigh Brown]

Hi Stefan,

On 2019-03-19 08:04, Stefan Roese wrote:

On 19.03.19 09:00, Chris Packham wrote:



On Tue, 19 Mar 2019, 8:39 PM Stefan Roese, > wrote:




On 18.03.19 08:51, Chris Packham wrote:
 > Prior to commit 93b283d49f93 ("ARM: CPU: arm926ejs: Consolidate 
cache
 > routines to common file") the kirkwood boards didn't have and 
dcache

 > support. The network and usb drivers rely on this. Set
 > CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h.
 >
 > Reported-by: Leigh Brown >
 > Signed-off-by: Chris Packham >

 > ---
 >
 > Changes in v2:
 > - expand the comment in config.h to provide more info
 >
 >   arch/arm/mach-kirkwood/include/mach/config.h | 6 ++
 >   1 file changed, 6 insertions(+)
 >
 > diff --git a/arch/arm/mach-kirkwood/include/mach/config.h 
b/arch/arm/mach-kirkwood/include/mach/config.h

 > index fcd903887bff..aea60688c2d3 100644
 > --- a/arch/arm/mach-kirkwood/include/mach/config.h
 > +++ b/arch/arm/mach-kirkwood/include/mach/config.h
 > @@ -26,6 +26,12 @@
 >   #define CONFIG_KIRKWOOD_EGIGA_INIT  /* Enable GbePort0/1 for 
kernel */
 >   #define CONFIG_KIRKWOOD_RGMII_PAD_1V8       /* Set RGMII Pad 
voltage to 1.8V */
 >   #define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 
for kernel */

 > +/*
 > + * Disable the dcache. Currently the network driver (mvgbe.c) 
and USB
 > + * EHCI driver (ehci-marvell.c) and possibly others rely on 
the data

 > + * cache being disabled.
 > + */
 > +#define CONFIG_SYS_DCACHE_OFF

While collecting the queued fixes for the upcoming release, I do
have one question regarding this Kirkwood cache issue (I don't 
have

such a board here, so I can't test anything):

Do we need this patch applied [1], if the patch from this thread 
is

applied [2]?

Thanks,
Stefan

[1] http://patchwork.ozlabs.org/patch/1048863/
[2] http://patchwork.ozlabs.org/patch/1057716/


I'm pretty sure you just need [2]. I've tested with just that on it's
own and Ethernet works on the kirkwood db. Functionally it's the same
change as Michael's just for more boards.

Leigh, can you see if [2] above works for you?


Patch [1] from Leigh also removes icache_enable() in
arch/arm/mach-kirkwood/cpu.c.

Not sure if this is still needed? Did any of you run into issues with
[1] not applied but with CONFIG_SYS_DCACHE_OFF set?


When the cache consolidation patch was applied, it added code to enable 
the
icache much earlier in the process.  Therefore, this line of code to 
enable

it became superfluous (assuming enabling the icache multiple times does
nothing).

I'd suggest removing it if you agree with that statement, to reduce
possible future confusion.



Thanks,
Stefan


Regards,

Leigh.
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[U-Boot] [PATCH v4] usb: host: Print device name when scanning

[Ismael Luceno Cortes]

Drop the counter, it has no meaning other than being the order in which
the interface is found; the name assigned to the USB host controller
interface is a better indicator.

Example of the original output:
> USB0:   USB EHCI 1.10
> scanning bus 0 for devices... 2 USB Device(s) found
>scanning usb for storage devices... 1 Storage Device(s) found

Patched output:
> Bus usb@ee080100: USB EHCI 1.10
> scanning bus usb@ee080100 for devices... 2 USB Device(s) found
>scanning usb for storage devices... 1 Storage Device(s) found

Signed-off-by: Ismael Luceno 
---

Notes:
Changes since v3:
- Replaced dev->seq with dev->name in usb_scan_bus

Changes since v2:
- Dropped counter altogether.

Changes since v1:
- Improved commit message.

 drivers/usb/host/usb-uclass.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 611ea97a72..6e118b5a8f 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -210,7 +210,7 @@ static void usb_scan_bus(struct udevice *bus, bool recurse)
 
assert(recurse);/* TODO: Support non-recusive */
 
-   printf("scanning bus %d for devices... ", bus->seq);
+   printf("scanning bus %s for devices... ", bus->name);
debug("\n");
ret = usb_scan_device(bus, 0, USB_SPEED_FULL, );
if (ret)
@@ -242,7 +242,6 @@ int usb_init(void)
struct usb_bus_priv *priv;
struct udevice *bus;
struct uclass *uc;
-   int count = 0;
int ret;
 
asynch_allowed = 1;
@@ -255,8 +254,7 @@ int usb_init(void)
 
uclass_foreach_dev(bus, uc) {
/* init low_level USB */
-   printf("USB%d:   ", count);
-   count++;
+   printf("Bus %s: ", bus->name);
 
 #ifdef CONFIG_SANDBOX
/*
@@ -327,10 +325,8 @@ int usb_init(void)
remove_inactive_children(uc, bus);
 
/* if we were not able to find at least one working bus, bail out */
-   if (!count)
-   printf("No controllers found\n");
-   else if (controllers_initialized == 0)
-   printf("USB error: all controllers failed lowlevel init\n");
+   if (controllers_initialized == 0)
+   printf("No working controllers found\n");
 
return usb_started ? 0 : -1;
 }

base-commit: 9ba5e5bc261a16f51662490da0cf620dc7f29013
prerequisite-patch-id: 8ebbc14087da985e5db35ef02335fbfdb4add60a
-- 
2.19.1
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[U-Boot] [PATCH 9/9] riscv: ae350: enable SMP

[Andes]

From: Rick Chen 

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 board/AndesTech/ax25-ae350/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/AndesTech/ax25-ae350/Kconfig 
b/board/AndesTech/ax25-ae350/Kconfig
index 44cb302..5e682b6 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -24,5 +24,6 @@ config ENV_OFFSET
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
+   imply SMP
 
 endif
-- 
2.7.4

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[U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.

[Andes]

From: Rick Chen 

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/dts/ae350_32.dts | 81 +
 arch/riscv/dts/ae350_64.dts | 47 +++---
 2 files changed, 101 insertions(+), 27 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0679827..0b4d966 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -25,17 +25,50 @@
reg = <0>;
status = "okay";
compatible = "riscv";
-   riscv,isa = "rv32imafdc";
+   riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
mmu-type = "riscv,sv32";
clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
+   next-level-cache = <>;
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
+   CPU1: cpu@1 {
+   device_type = "cpu";
+   reg = <1>;
+   status = "okay";
+   compatible = "riscv";
+   riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
+   mmu-type = "riscv,sv32";
+   clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
+   d-cache-size = <0x8000>;
+   d-cache-line-size = <32>;
+   next-level-cache = <>;
+   CPU1_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "riscv,cpu-intc";
+   };
+   };
+
+   L2: l2-cache@e050 {
+   compatible = "cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0x0 0xe050 0x0 0x4>;
+   };
};
 
memory@0 {
@@ -49,29 +82,29 @@
compatible = "andestech,riscv-ae350-soc";
ranges;
 
-   plic0: interrupt-controller@e400 {
-   compatible = "riscv,plic0";
-   #address-cells = <1>;
-   #interrupt-cells = <1>;
-   interrupt-controller;
-   reg = <0xe400 0x200>;
-   riscv,ndev=<71>;
-   interrupts-extended = <_intc 11 _intc 9>;
-   };
+   plic0: interrupt-controller@e400 {
+   compatible = "riscv,plic0";
+   #address-cells = <1>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   reg = <0xe400 0x200>;
+   riscv,ndev=<71>;
+   interrupts-extended = <_intc 11 _intc 9 
_intc 11 _intc 9>;
+   };
 
-   plic1: interrupt-controller@e640 {
-   compatible = "riscv,plic1";
-   #address-cells = <1>;
-   #interrupt-cells = <1>;
-   interrupt-controller;
-   reg = <0xe640 0x40>;
-   riscv,ndev=<1>;
-   interrupts-extended = <_intc 3>;
-   };
+   plic1: interrupt-controller@e640 {
+   compatible = "riscv,plic1";
+   #address-cells = <1>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   reg = <0xe640 0x40>;
+   riscv,ndev=<2>;
+   interrupts-extended = <_intc 3 _intc 3>;
+   };
 
-   plmt0@e600 {
-   compatible = "riscv,plmt0";
-   interrupts-extended = <_intc 7>;
+   plmt0@e600 {
+   compatible = "riscv,plmt0";
+   interrupts-extended = <_intc 7 _intc 7>;
reg = <0xe600 0x10>;
};
};
@@ -146,6 +179,10 @@
interrupt-parent = <>;
};
 
+   pmu {
+   compatible = "riscv,base-pmu";
+   };
+
virtio_mmio@fe007000 {
interrupts = <0x17 0x4>;
interrupt-parent = <0x2>;
diff 

[U-Boot] [PATCH 6/9] riscv: ax25: Add platform-specific Kconfig options

[Andes]

From: Rick Chen 

Add ax25 RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/ax25/Kconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index e9dbca2..0901709 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,5 +1,11 @@
 config RISCV_NDS
bool
+   select ARCH_EARLY_INIT_R
+   imply CPU
+   imply CPU_RISCV
+   imply RISCV_TIMER
+   imply NDS_PLIC if RISCV_MMODE
+   imply NDS_PLMT if RISCV_MMODE
help
  Run U-Boot on AndeStar V5 platforms and use some specific features
  which are provided by Andes Technology AndeStar V5 families.
-- 
2.7.4

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[U-Boot] [PATCH 5/9] riscv: ae350: disable ATCPIT100 timer

[Andes]

From: Rick Chen 

Disable ATCPIT100 SoC timer and replace by PLMT.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 configs/ae350_rv32_defconfig | 1 -
 configs/ae350_rv64_defconfig | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index 5837b48..e13c7de 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -33,4 +33,3 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
-CONFIG_ATCPIT100_TIMER=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index b250d3f..a41f918 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -34,4 +34,3 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
-CONFIG_ATCPIT100_TIMER=y
-- 
2.7.4

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[U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.

[Andes]

From: Rick Chen 

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/ax25/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 0901709..e030df4 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -14,6 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
+   depends on RISCV_MMODE
help
  Provide Andes Technology AndeStar V5 families specific cache support.
 
-- 
2.7.4

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[U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT

[Andes]

From: Rick Chen 

The platform-Level Machine Timer(PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time()which
are required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/Kconfig   |  9 ++
 arch/riscv/include/asm/global_data.h |  3 ++
 arch/riscv/include/asm/syscon.h  |  1 +
 arch/riscv/lib/Makefile  |  1 +
 arch/riscv/lib/nds_plmt.c| 53 
 5 files changed, 67 insertions(+)
 create mode 100644 arch/riscv/lib/nds_plmt.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fef11dd..697892e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -118,6 +118,15 @@ config NDS_PLIC
  The Andes PLIC block holds memory-mapped claim and pending registers
  associated with software interrupt.
 
+config NDS_PLMT
+   bool
+   depends on RISCV_MMODE
+   select REGMAP
+   select SYSCON
+   help
+ The Andes PLMT block holds memory-mapped mtime register
+ associated with timer tick.
+
 config RISCV_RDTIME
bool
default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index 15867f5..0695ae3 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,6 +21,9 @@ struct arch_global_data {
 #ifdef CONFIG_NDS_PLIC
void __iomem *plic; /* plic base address */
 #endif
+#ifdef CONFIG_NDS_PLMT
+   void __iomem *plmt; /* plmt base address */
+#endif
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index 0229989..9fdee09 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -14,6 +14,7 @@ enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
RISCV_SYSCON_PLIC,  /* Platform Level Interrup Controller (PLIC) */
+   RISCV_SYSCON_PLMT,  /* Platform Level Machine Timer (PLMT) */
 };
 
 #endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 8187c2b..383eed3 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -12,6 +12,7 @@ obj-y += cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_NDS_PLIC) += nds_plic.o
+obj-$(CONFIG_NDS_PLMT) += nds_plmt.o
 obj-y  += interrupts.o
 obj-y  += reset.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/nds_plmt.c b/arch/riscv/lib/nds_plmt.c
new file mode 100644
index 000..12d7e0e
--- /dev/null
+++ b/arch/riscv/lib/nds_plmt.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen 
+ *
+ * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
+ * The PLMT block holds memory-mapped mtime register
+ * associated with timer tick.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* mtime register */
+#define MTIME_REG(base)((ulong)(base))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLMT_BASE_GET(void)\
+   do {\
+   long *ret;  \
+   \
+   if (!gd->arch.plmt) {   \
+   ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
+   if (IS_ERR(ret))\
+   return PTR_ERR(ret);\
+   gd->arch.plmt = ret;\
+   }   \
+   } while (0)
+
+int riscv_get_time(u64 *time)
+{
+   PLMT_BASE_GET();
+
+   *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+
+   return 0;
+}
+
+static const struct udevice_id nds_plmt_ids[] = {
+   { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
+   { }
+};
+
+U_BOOT_DRIVER(nds_plmt) = {
+   .name   = "nds_plmt",
+   .id = UCLASS_SYSCON,
+   .of_match   = nds_plmt_ids,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.7.4

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[U-Boot] [PATCH 4/9] riscv: ae350: initialize PLIC

[Andes]

From: Rick Chen 

Initialize PLIC when ae350 board startup.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index d343453..ebeb4b8 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,10 +11,17 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 extern phys_addr_t prior_stage_fdt_address;
+extern int plic_init(int harts);
+
 /*
  * Miscellaneous platform dependent initializations
  */
@@ -97,9 +104,32 @@ int smc_init(void)
return 0;
 }
 
+#ifdef CONFIG_NDS_PLIC
+int init_plic(void)
+{
+   struct udevice *dev;
+   int ret;
+
+   ret = uclass_find_first_device(UCLASS_CPU, );
+   if (ret)
+   return ret;
+
+   if (ret == 0 && dev != NULL) {
+   ret = cpu_get_count(dev);
+   plic_init(ret);
+   return 0;
+   }
+
+   return -ENODEV;
+}
+#endif
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
+#ifdef CONFIG_NDS_PLIC
+   init_plic();
+#endif
smc_init();
 
return 0;
-- 
2.7.4

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[U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC

[Andes]

From: Rick Chen 

The Platform-Level Interrupt Controller(PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt.It is required
for handling IPI.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/Kconfig   |  9 
 arch/riscv/include/asm/global_data.h |  3 ++
 arch/riscv/include/asm/syscon.h  |  2 +-
 arch/riscv/lib/Makefile  |  1 +
 arch/riscv/lib/nds_plic.c| 84 
 5 files changed, 98 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/lib/nds_plic.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3a4470d..fef11dd 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -109,6 +109,15 @@ config SIFIVE_CLINT
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
+config NDS_PLIC
+   bool
+   depends on RISCV_MMODE
+   select REGMAP
+   select SYSCON
+   help
+ The Andes PLIC block holds memory-mapped claim and pending registers
+ associated with software interrupt.
+
 config RISCV_RDTIME
bool
default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index 80e3165..15867f5 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,6 +18,9 @@ struct arch_global_data {
 #ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint;/* clint base address */
 #endif
+#ifdef CONFIG_NDS_PLIC
+   void __iomem *plic; /* plic base address */
+#endif
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index d311ee6..0229989 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -9,11 +9,11 @@
 /*
  * System controllers in a RISC-V system
  *
- * So far only SiFive's Core Local Interruptor (CLINT) is defined.
  */
 enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
+   RISCV_SYSCON_PLIC,  /* Platform Level Interrup Controller (PLIC) */
 };
 
 #endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 35dbf64..8187c2b 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_NDS_PLIC) += nds_plic.o
 obj-y  += interrupts.o
 obj-y  += reset.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/nds_plic.c b/arch/riscv/lib/nds_plic.c
new file mode 100644
index 000..563da7d
--- /dev/null
+++ b/arch/riscv/lib/nds_plic.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen 
+ *
+ * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
+ * The PLIC block holds memory-mapped claim and pending registers
+ * associated with software interrupt.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* pending register */
+#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + (hart) * 8)
+/* enable register */
+#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
+/* claim register */
+#define CLAIM_REG(base, hart)  ((ulong)(base) + 0x24 + (hart) * 0x1000)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLIC_BASE_GET(void)\
+   do {\
+   long *ret;  \
+   \
+   if (!gd->arch.plic) {   \
+   ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
+   if (IS_ERR(ret))\
+   return PTR_ERR(ret);\
+   gd->arch.plic = ret;\
+   }   \
+   } while (0)
+
+int plic_init(int harts)
+{
+   int i;
+   int en = 0x80808080;
+
+   PLIC_BASE_GET();
+   for(i=0;i> i;
+   writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
+   }
+
+   return 0;
+}
+
+int riscv_send_ipi(int hart)
+{
+   PLIC_BASE_GET();
+
+   writel((0x80>>hart), (void __iomem *)PENDING_REG(gd->arch.plic, 
gd->arch.boot_hart));
+
+   return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+   u32 source_id;
+
+   PLIC_BASE_GET();
+
+   source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+   writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+
+   return 0;
+}
+
+static const struct 

[U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node

[Andes]

From: Rick Chen 

To enumerate devices on the /soc/ node, create a "simple-bus"
driver to match "andestech,riscv-ae350-soc".

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/ax25/cpu.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index 76689b2..e6e7404 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -7,6 +7,7 @@
 /* CPU specific code */
 #include 
 #include 
+#include 
 
 /*
  * cleanup_before_linux() is called just before we call linux
@@ -25,3 +26,18 @@ int cleanup_before_linux(void)
 
return 0;
 }
+
+/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */
+static const struct udevice_id riscv_ae350_soc_ids[] = {
+   {
+   .compatible = "andestech,riscv-ae350-soc",
+   },
+   { }
+};
+
+U_BOOT_DRIVER(riscv_ae350_soc_ids) = {
+   .name = "andestech,riscv-ae350-soc",
+   .id = UCLASS_SIMPLE_BUS,
+   .of_match = riscv_ae350_soc_ids,
+   .flags = DM_FLAG_PRE_RELOC,
+};
-- 
2.7.4

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[U-Boot] [PATCH 0/9] AE350 SMP support RISC-V

[Andes]

From: Rick Chen 

This patch series was based on Lukas's patchsets of SMP support for RISC-V.
Add Andestech's PLIC for IPI handling and PLMT to replace Soc timer.
It has been verified on AE350 SMP platform in M-mode and boot SMP kernel ok.

Verification in S-mode is still on-going.

Rick Chen (9):
  riscv: ax25: Create a simple-bus driver for the soc node
  riscv: Add a SYSCON driver for Andestech's PLIC
  riscv: Add a SYSCON driver for Andestech's PLMT
  riscv: ae350: initialize PLIC
  riscv: ae350: disable ATCPIT100 timer
  riscv: ax25: Add platform-specific Kconfig options
  riscv: ax25: Andes specific cache shall only support in M-mode.
  riscv: dts: ae350 support SMP.
  riscv: ae350: enable SMP

 arch/riscv/Kconfig  | 18 +++
 arch/riscv/cpu/ax25/Kconfig |  7 +++
 arch/riscv/cpu/ax25/cpu.c   | 16 +++
 arch/riscv/dts/ae350_32.dts | 81 ++-
 arch/riscv/dts/ae350_64.dts | 47 --
 arch/riscv/include/asm/global_data.h|  6 +++
 arch/riscv/include/asm/syscon.h |  3 +-
 arch/riscv/lib/Makefile |  2 +
 arch/riscv/lib/nds_plic.c   | 84 +
 arch/riscv/lib/nds_plmt.c   | 53 +
 board/AndesTech/ax25-ae350/Kconfig  |  1 +
 board/AndesTech/ax25-ae350/ax25-ae350.c | 30 
 configs/ae350_rv32_defconfig|  1 -
 configs/ae350_rv64_defconfig|  1 -
 14 files changed, 320 insertions(+), 30 deletions(-)
 create mode 100644 arch/riscv/lib/nds_plic.c
 create mode 100644 arch/riscv/lib/nds_plmt.c

-- 
2.7.4

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Re: [U-Boot] [PATCH v3] usb: host: Print device name when scanning

[Ismael Luceno Cortes]

On 19/Mar/2019 02:14, Marek Vasut wrote:
> On 3/18/19 2:21 PM, Ismael Luceno Cortes wrote:
> > Drop the counter, it has no meaning other than being the order in which
> > the interface is found; the name assigned to the USB host controller
> > interface is a better indicator.
> > 
> > Example of the original output:
> >> USB0:   USB EHCI 1.10
> >> scanning bus 0 for devices... 2 USB Device(s) found
> >>scanning usb for storage devices... 1 Storage Device(s) found
> > 
> > Patched output:
> >> Bus usb@ee080100:   USB EHCI 1.10
> >> scanning bus 0 for devices... 2 USB Device(s) found
> ^
> '-- here it still says 0, why ?
> it's not very consistent :)

Good point, I'll remove that one, it seems it used to be the same thing
but now comes from dev->seq.
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Re: [U-Boot] [PATCH] misc: fs_loader: Replace label with DT phandle

[Chee, Tien Fong]

On Tue, 2019-03-19 at 09:22 +0800, Simon Glass wrote:
> Hi Tien Fong,
> 
> On Mon, 11 Mar 2019 at 12:28, Chee, Tien Fong  om> wrote:
> > 
> > 
> > On Sun, 2019-03-10 at 15:51 -0600, Simon Glass wrote:
> > > 
> > > Hi Tien Fong,
> > > 
> > > On Tue, 26 Feb 2019 at 05:37, Chee, Tien Fong  > > el.c
> > > om> wrote:
> > > > 
> > > > 
> > > > 
> > > > On Fri, 2019-02-15 at 14:35 +0800, tien.fong.c...@intel.com
> > > > wrote:
> > > > > 
> > > > > 
> > > > > From: Tien Fong Chee 
> > > > > 
> > > > > In previously label which will be expanded to the node's full
> > > > > path
> > > > > was
> > > > > used, and now replacing label with most commonly used DT
> > > > > phandle.
> > > > > The
> > > > > codes were changed accordingly to the use of DT phandle and
> > > > > supporting
> > > > > multiple instances.
> > > > > 
> > > > > Signed-off-by: Tien Fong Chee 
> > > > > ---
> > > > >  doc/driver-model/fs_firmware_loader.txt |   58
> > > > > +--
> > > > >  drivers/misc/fs_loader.c|   36 -
> > > > > 
> > > > > --
> > > > >  2 files changed, 62 insertions(+), 32 deletions(-)
> > > This seems OK to me, but I think this feature needs a test.
> > Yes, i have ran the test passed with FPGA driver.
> No I mean that you should add a test in test/py/tests
Okay, noted.
> 
> Regards,
> Simon
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[U-Boot] [PATCH v12 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK

[tien . fong . chee]

From: Tien Fong Chee 

Update the default configuration file to enable the necessary functionality
the get the kit working.

Signed-off-by: Tien Fong Chee 

---

changes for v12
- No changes.

changes for v11
- No changes.

changes for v10
- No changes.

changes for v9
- No changes.

changes for v8
- Moved the FIT related configs to the patch of configuration for FPGA
  SoCFPGA A10 SoCDK.

changes for v7
- Keep minimal configs.
---
 configs/socfpga_arria10_defconfig | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
index 192cf7e05f..759fc771e6 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -10,11 +10,14 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
 # CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_VERSION_VARIABLE=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_FPGA_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
@@ -23,9 +26,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_ENV_SUPPORT=y
@@ -33,7 +34,6 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_DM_MMC=y
 CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_FS_LOADER=y
@@ -44,11 +44,14 @@ CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MTD_DEVICE=y
+CONFIG_MMC_DW=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_DESIGNWARE_APB_TIMER=y
-CONFIG_USE_TINY_PRINTF=y
-- 
2.13.0

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[U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading

[tien . fong . chee]

From: Tien Fong Chee 

Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.

Signed-off-by: Tien Fong Chee 

---

changes for v12
- No changes.

changes for v11
- No changes.

changes for v10
-Cleaned up the codes.
-Return -EPERM when programing core on non early IO release mode.
-Using live function to get rid of gd->
-Removed @0 for fs-loader node

changes for v9
- Support data offset
- Added default DDR load address
- Squashed the image.h
- Changed to phandle
- Ensure the DDR is fully up running by checking the gd->ram

changes for v8
- Added codes to discern bitstream type based on fpga node name.

changes for v7
- Restructure the FPGA driver to support both peripheral bitstream and core
  bitstream bundled into FIT image.
- Support loadable property for core bitstream. User can set loadable
  in DDR for better performance. This loading would be done in one large
  chunk instead of chunk by chunk loading with small memory buffer.
---
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  17 +
 .../include/mach/fpga_manager_arria10.h|  39 +-
 drivers/fpga/socfpga_arria10.c | 497 -
 include/image.h|   4 +
 4 files changed, 542 insertions(+), 15 deletions(-)

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts 
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index 998d811210..cc761967c7 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -18,6 +18,23 @@
 /dts-v1/;
 #include "socfpga_arria10_socdk.dtsi"
 
+/ {
+   chosen {
+   firmware-loader = <_loader0>;
+   };
+
+   fs_loader0: fs-loader {
+   u-boot,dm-pre-reloc;
+   compatible = "u-boot,fs-loader";
+   phandlepart = < 1>;
+   };
+};
+
+_mgr {
+   u-boot,dm-pre-reloc;
+   altr,bitstream = "fit_spl_fpga.itb";
+};
+
  {
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 09d13f6fd3..c5f67714aa 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -1,9 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2017 Intel Corporation 
+ * Copyright (C) 2017-2019 Intel Corporation 
  * All rights reserved.
  */
 
+#include 
+#include 
+#include 
+
 #ifndef _FPGA_MANAGER_ARRIA10_H_
 #define _FPGA_MANAGER_ARRIA10_H_
 
@@ -51,6 +55,10 @@
 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB  16
 
+#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED   0xa65c
+#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
+#define FPGA_SOCFPGA_A10_RBF_PERIPH0x0001
+#define FPGA_SOCFPGA_A10_RBF_CORE  0x8001
 #ifndef __ASSEMBLY__
 
 struct socfpga_fpga_manager {
@@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
u32  imgcfg_fifo_status;
 };
 
+enum rbf_type {
+   unknown,
+   periph_section,
+   core_section
+};
+
+enum rbf_security {
+   invalid,
+   unencrypted,
+   encrypted
+};
+
+struct rbf_info {
+   enum rbf_type section;
+   enum rbf_security security;
+};
+
+struct fpga_loadfs_info {
+   fpga_fs_info *fpga_fsinfo;
+   u32 remaining;
+   u32 offset;
+   struct rbf_info rbfinfo;
+};
+
 /* Functions */
 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
 int fpgamgr_program_finish(void);
 int is_fpgamgr_user_mode(void);
 int fpgamgr_wait_early_user_mode(void);
-
+const char *get_fpga_filename(void);
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+ u32 offset);
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
 #endif /* __ASSEMBLY__ */
 
 #endif /* _FPGA_MANAGER_ARRIA10_H_ */
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 9499d1a014..9df2c430d7 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -1,8 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2017 Intel Corporation 
+ * Copyright (C) 2017-2019 Intel Corporation 
  */
-
 #include 
 #include 
 #include 
@@ -10,8 +9,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 
@@ -21,6 +23,9 @@
 #define COMPRESSION_OFFSET 229
 #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT   0x100
+#define DEFAULT_DDR_LOAD_ADDRESS   0x400
+
+DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_fpga_manager *fpga_manager_base =
(void 

[U-Boot] [PATCH v12 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs

[tien . fong . chee]

From: Tien Fong Chee 

Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.

Signed-off-by: Tien Fong Chee 

---

changes for v12
- No changes.

changes for v11
- No changes.

changes for v10
- Removed the static so the function can be referred by other c file.

changes for v9
- Used ALLOC_CACHE_ALIGN_BUFFER
- De-duplicated the same chunks of codes

changes for v8
- No changes.

changes for v7
- Removed casting for get_fpga_filename
- Removed hard coding DDR address for loading core bistream, using loadable
  property from FIT.
- Added checking for config_pins, return if error.
---
 .../include/mach/fpga_manager_arria10.h|  1 +
 arch/arm/mach-socfpga/spl_a10.c| 31 +-
 drivers/fpga/socfpga_arria10.c |  2 +-
 3 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index c5f67714aa..62249b3695 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -126,6 +126,7 @@ int fpgamgr_program_finish(void);
 int is_fpgamgr_user_mode(void);
 int fpgamgr_wait_early_user_mode(void);
 const char *get_fpga_filename(void);
+int is_fpgamgr_early_user_mode(void);
 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
  u32 offset);
 void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c8e73d47c0..b466307f98 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2019 Altera Corporation 
  */
 
 #include 
@@ -23,6 +23,11 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+
+#define FPGA_BUFSIZ16 * 1024
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -68,11 +73,35 @@ u32 spl_boot_mode(const u32 boot_device)
 
 void spl_board_init(void)
 {
+   ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
+
/* enable console uart printing */
preloader_console_init();
WATCHDOG_RESET();
 
arch_early_init_r();
+
+   /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+   if (is_fpgamgr_user_mode()) {
+   int ret = config_pins(gd->fdt_blob, "shared");
+
+   if (ret)
+   return;
+
+   ret = config_pins(gd->fdt_blob, "fpga");
+   if (ret)
+   return;
+   } else if (!is_fpgamgr_early_user_mode()) {
+   /* Program IOSSM(early IO release) or full FPGA */
+   fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+   }
+
+   /* If the IOSSM/full FPGA is already loaded, start DDR */
+   if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+   ddr_calibration_sequence();
+
+   if (!is_fpgamgr_user_mode())
+   fpgamgr_program(buf, FPGA_BUFSIZ, 0);
 }
 
 void board_init_f(ulong dummy)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 9df2c430d7..285280e507 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -69,7 +69,7 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
 }
 
-static int is_fpgamgr_early_user_mode(void)
+int is_fpgamgr_early_user_mode(void)
 {
return (readl(_manager_base->imgcfg_stat) &
ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
-- 
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[U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

[tien . fong . chee]

From: Tien Fong Chee 

Increasing Malloc pool size up to 0x15000 is required to support FAT in SPL
. The result of calculation is come from after applying some few patches
which are required for optimizing vfat and maximizing resusable of the
memory pool, and then followed by the size required come from default max
cluster(0x1) + others(0x2000) + additional memory for headroom(0x3000).
Previous records of describing these few patches can be checked from here
[v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg314511.html .

Signed-off-by: Tien Fong Chee 

---

changes for v12
- Improved the commit messages.

changes for v11
- No changes.

changes for v10
- No changes.

changes for v9
- No changes.

changes for v8
- Moved the FIT related configs to the patch of configuration for FPGA
  SoCFPGA A10 SoCDK.

changes for v7
- Keep minimal configs.
---
 include/configs/socfpga_common.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 181af9b646..22533036ed 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2019 Altera Corporation 
  */
 #ifndef __CONFIG_SOCFPGA_COMMON_H__
 #define __CONFIG_SOCFPGA_COMMON_H__
@@ -254,7 +254,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 /* SPL memory allocation configuration, this is for FAT implementation */
 #ifndef CONFIG_SYS_SPL_MALLOC_START
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
 #define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_INIT_RAM_SIZE - \
 CONFIG_SYS_SPL_MALLOC_SIZE + \
 CONFIG_SYS_INIT_RAM_ADDR)
-- 
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[U-Boot] [PATCH v12 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

[tien . fong . chee]

From: Tien Fong Chee 

Update the default configuration file to enable the necessary functionality
to get the SoCFPGA loadfs driver support. This would enable the
implementation of programming bitstream into FPGA from MMC.

Signed-off-by: Tien Fong Chee 

---

changes for v12
- No changes.

changes for v11
- No changes.

changes for v10
- No changes.

changes for v9
- No changes.

changes for v8
- Added FIT related configs

changes for v7
- Removed limit set for CONFIG_FS_FAT_MAX_CLUSTSIZE
---
 configs/socfpga_arria10_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
index f321a0ac3b..192cf7e05f 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -28,9 +28,18 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 # CONFIG_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_DM_MMC=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_FS_LOADER=y
 CONFIG_FPGA_SOCFPGA=y
+CONFIG_SPL_FIT=y
+CONFIG_FIT=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
-- 
2.13.0

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[U-Boot] [PATCH v12 3/9] ARM: socfpga: Cleaning up and ensuring consistent format messages in driver

[tien . fong . chee]

From: Tien Fong Chee 

Ensure all the debug messages are always prefix with "FPGA: " and comment
beginning with uppercase letter.

Signed-off-by: Tien Fong Chee 

---

changes for v12
- Improved the commit messages.

changes for v11
- No changes.

changes for v10
- This patch was split out from [PATCH v10 5/9]
  ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
---
 drivers/fpga/socfpga_arria10.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 114dd910ab..b0abe1955c 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -94,7 +94,7 @@ int fpgamgr_wait_early_user_mode(void)
i++;
}
 
-   debug("Additional %i sync word needed\n", i);
+   debug("FPGA: Additional %i sync word needed\n", i);
 
/* restoring original CDRATIO */
fpgamgr_set_cd_ratio(cd_ratio);
@@ -172,9 +172,10 @@ static int fpgamgr_set_cdratio_cdwidth(unsigned int 
cfg_width, u32 *rbf_data,
compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
compress = !compress;
 
-   debug("header word %d = %08x\n", 69, rbf_data[69]);
-   debug("header word %d = %08x\n", 229, rbf_data[229]);
-   debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, 
compress);
+   debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
+   debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
+   debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
+compress);
 
/*
 * from the register map description of cdratio in imgcfg_ctrl_02:
@@ -455,10 +456,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
 {
int status;
 
-   /* disable all signals from hps peripheral controller to fpga */
+   /* Disable all signals from hps peripheral controller to fpga */
writel(0, _manager_base->fpgaintf_en_global);
 
-   /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+   /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset();
 
/* Initialize the FPGA Manager */
-- 
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[U-Boot] [PATCH v12 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

[tien . fong . chee]

From: Tien Fong Chee 

Add default fitImage file bundling FPGA bitstreams for Arria10.

Signed-off-by: Tien Fong Chee 

---

changes for v12
- No changes.

changes for v11
- Replaced core image node "-2" with "-1",
  the numeric associates the core and periph images in case where there
  are multiple.

changes for v10
- Replaced both image nodes "@1" and "@2" with "-1" and "-2" respectively.

changes for v9
- Reordered the images and fpga configurations.
- Removed the load property at core image.

changes for v8
- Changed the FPGA node name to fpga-core and fpga-periph for both core and
  periph bitstreams respectively.

changes for v7
- No changes.
---
 board/altera/arria10-socdk/fit_spl_fpga.its | 38 +
 1 file changed, 38 insertions(+)
 create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its

diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its 
b/board/altera/arria10-socdk/fit_spl_fpga.its
new file mode 100644
index 00..adae997213
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_spl_fpga.its
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+/dts-v1/;
+
+/ {
+   description = "FIT image with FPGA bistream";
+   #address-cells = <1>;
+
+   images {
+   fpga-periph-1 {
+   description = "FPGA peripheral bitstream";
+   data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+
+   fpga-core-1 {
+   description = "FPGA core bitstream";
+   data = /incbin/("../../../ghrd_10as066n2.core.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   };
+
+   configurations {
+   default = "config-1";
+   config-1 {
+   description = "Boot with FPGA early IO release config";
+   fpga = "fpga-periph-1", "fpga-core-1";
+   };
+   };
+};
-- 
2.13.0

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