Re: [U-Boot] [PATCH v2 03/10] tiny-printf: Reorder code to support %p
Faiz, On 31/01/20 11:44 pm, Simon Glass wrote: > Hi Vignesh, > > On Thu, 30 Jan 2020 at 22:12, Vignesh Raghavendra wrote: >> >> Hi Simon, >> >> On 31/01/20 7:57 am, Simon Glass wrote: >>> Hi Faiz, >>> >>> On Thu, 30 Jan 2020 at 08:22, Faiz Abbas wrote: Hi Simon, On 22/10/19 4:56 am, Simon Glass wrote: > With a bit of code reordering we can support %p using the existing code > for ulong. > > Move the %p code up and adjust the logic accordingly. > >> >> [...] Retry time exceeded; starting again Problem booting with BOOTP SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Reverting this patch on the latest U-boot master fixes the issue for me. I'll look into this more deeply tomorrow. Let me know if you see something obviously wrong with the patch. >>> >>> Well one thing is that eth_env_set_enetaddr() called from the board's >>> board.c has this: >>> >>> sprintf(buf, "%pM", enetaddr); >>> >>> which is not supported with tiny-printf. >> >> That is not true. %pM is supported when SPL_NET_SUPPORT is enabled. See: >> >> https://gitlab.denx.de/u-boot/u-boot/blob/master/lib/tiny-printf.c#L183 >> >> I added this specifically to support Ethernet Boot usecases on TI platforms >> >> But above commit seems to move pointer() function that formats the >> output under #ifdef DEBUG which definitely breaks %pM > > OK I see. I think it is too confusing to use #ifdef DEBUG in this code. > > One fix would be to change pointer() to return true if it actually > does something. I'll take a look. > > This code needs tests also. Vignesh, do you feel like writing something? > Is there a testcase for full printf()? I am not sure where to look for. Is test/print_ut.c the right place to add new test? -- Regards Vignesh
RE: [EXT] Re: [Patch v4 0/7] Transition of fsl qspi driver to spi-mem framework
++Joe Hi, > -Original Message- > From: Jagan Teki > Sent: Monday, January 27, 2020 3:44 PM > To: Schrempf Frieder ; Kuldeep Singh > > Cc: U-Boot-Denx ; Priyanka Jain > ; Ashish Kumar ; Stefan > Roese ; Vignesh R > Subject: Re: [EXT] Re: [Patch v4 0/7] Transition of fsl qspi driver to spi-mem > framework > > Caution: EXT Email > > On Mon, Jan 27, 2020 at 3:17 PM Schrempf Frieder > wrote: > > > > Hi, > > > > On 27.01.20 10:20, Kuldeep Singh wrote: > > > Hi Jagan, > > > > > >> -Original Message- > > >> From: Jagan Teki > > >> Sent: Monday, January 27, 2020 12:50 PM > > >> To: Kuldeep Singh > > >> Cc: U-Boot-Denx ; Priyanka Jain > > >> ; Ashish Kumar ; > > >> Stefan Roese ; Schrempf Frieder > > >> ; Vignesh R > > >> Subject: [EXT] Re: [Patch v4 0/7] Transition of fsl qspi driver to > > >> spi-mem framework > > >> > > >> Caution: EXT Email > > >> > > >> Hi Kuldeep, > > >> > > >> On Mon, Jan 13, 2020 at 12:57 PM Kuldeep Singh > > >> > > >> wrote: > > >>> > > >>> This entire patch series migrate freescale qspi driver to spi-mem > > >>> framework. > > >>> > > >>> v4 version of series include removal of buildman failure on > > >>> LS2080AQDS build which was observed in cleanup patches. Also, more > > >>> clear commit message of patch 5. > > >>> > > >>> v3 version of series includes correction of copyright in qspi > > >>> driver and also move SPI_FLASH_SPANSION from header to > defconfigs > > >>> in same > > >> patch. > > >>> > > >>> v2 version of series includes changes in qspi driver to have 1k > > >>> size instead of complete flash size so as to make driver > > >>> independent of flash size. This also makes it align with linux version > > >>> of > driver. > > >>> Also added support for imx platforms to set TDH bits correctly. > > >>> There are other minor changes in commit messages. > > >>> > > >>> Dependency on patches[1][2]. These patches are required to resolve > > >>> booting crash observed in LS1012ARDB. One crash was related to pfe > > >>> driver as it was accessing flash memory directly and other was > > >>> based on > > >> environment. > > >>> [1] > > >>> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F > > >>> patc > > >>> > > >> > hwork.ozlabs.org%2Fpatch%2F1219462%2Fdata=02%7C01%7Ckulde > ep.s > > >> ingh > > >>> %40nxp.com%7C94b5e5528efc47df25ea08d7a2f94efd%7C686ea1d3 > bc2b4c6 > > >> fa92cd9 > > >>> > > >> > 9c5c301635%7C0%7C0%7C637157063972042137sdata=DZFAEmt0sA > 4c > > >> cCPmu%2F > > >>> cArl99B02G2KmiAUYou1RXXBI%3Dreserved=0 > > >>> [2] > > >>> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F > > >>> patc > > >>> > > >> > hwork.ozlabs.org%2Fpatch%2F1208299%2Fdata=02%7C01%7Ckulde > ep.s > > >> ingh > > >>> %40nxp.com%7C94b5e5528efc47df25ea08d7a2f94efd%7C686ea1d3 > bc2b4c6 > > >> fa92cd9 > > >>> > > >> > 9c5c301635%7C0%7C0%7C637157063972042137sdata=3qr7QKERZg > k8 > > >> V83QbYMM > > >>> Nb4xM4rUaqm2v3lZ5gzsGAQ%3Dreserved=0 > > >>> > > >>> Patch 1 adds new qspi driver incorporating spi-mem framework and > > >>> also removal of old driver which was based on spi-nor. The driver > > >>> is a ported version of linux qspi driver. Initial port was done by > > >>> Frieder. > > >>> Now, no more direct memory access to spi-nor memory is possible > > >>> i.e accessing flash memory using absolute address is not possible. > > >>> > > >>> Patch 2 removes unused qspi config options. > > >>> > > >>> Patch 3 moves FSL_QSPI to defconfig instead of defining it in header > files. > > >>> > > >>> Patch 4 removes unused num-cs property from imx platforms. > > >>> > > >>> Patch 5 enables SPI_FLASH_SPANSION in ls1012a defconfig as > > >>> FSL_QSPI is already enabled. > > >>> > > >>> Patch 6 enables SPI_FLASH_SPANSION in defconfigs of LS1046a > boards > > >>> instead of defining in header files. > > >>> > > >>> Patch 7 updates the device-tree properties treewide for layerscape > > >>> boards by aligning with linux device-tree properties. > > >>> > > >>> Frieder Schrempf (1): > > >>>imx: imx6sx: Remove unused 'num-cs' property > > >>> > > >>> Kuldeep Singh (6): > > >>>spi: Transform the FSL QuadSPI driver to use the SPI MEM API > > >>>treewide: Remove unused FSL QSPI config options > > >>>configs: ls1043a: Move CONFIG_FSL_QSPI to defconfig > > >>>configs: ls1012a: Enable CONFIG_SPI_FLASH_SPANSION in > defconfigs > > >>>configs: ls1046a: Move SPI_FLASH_SPANSION to defconfig > > >>>treewide: Update fsl qspi node dt properties as per spi-mem > > >>> driver > > >> > > >> Seems like defconfig changes of these were depends on net changes > > >> isn't it? if yes, we need to wait for them to merge first. > > > > > > Actually, net change is required to resolve the booting crash on > LS1012ARDB with this driver. > > > This series can be applied even without net pfe patch. > > > > It could be applied without and as you sad it would break the boot for > > LS1012ARDB. > > > > Therefore no, I don't think we should apply patches that
Re: [PATCH v2 07/17] x86: apl: Drop the I2C config in FSP-S
On Tue, Feb 4, 2020 at 8:20 AM Simon Glass wrote: > > This config is not actually used here and in U-Boot it seems better to set > this using the device tree for each individual controller. The monolithic > config of the FSP-S is only necessary if the FSP is actually configuring > something, but here it is not. > > The FSP-S does enable/disable the various I2C ports. It might be nice to > handle this using the okay/disabled property of each port, but that can be > considered later. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > arch/x86/cpu/apollolake/fsp_s.c | 58 - > 1 file changed, 58 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v2 05/17] x86: Add a clock driver for Intel devices
On Tue, Feb 4, 2020 at 8:20 AM Simon Glass wrote: > > So far we have avoided adding a clock driver for Intel devices. But the > Designware I2C driver needs a different clock (133MHz) on Intel devices > than on others (166MHz). Add a simple driver that provides this > information. > > This driver can be expanded later as needed. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > drivers/clk/Kconfig | 10 ++ > drivers/clk/Makefile| 1 + > drivers/clk/intel/Makefile | 6 > drivers/clk/intel/clk_intel.c | 41 + > include/dt-bindings/clock/intel-clock.h | 15 + > 5 files changed, 73 insertions(+) > create mode 100644 drivers/clk/intel/Makefile > create mode 100644 drivers/clk/intel/clk_intel.c > create mode 100644 include/dt-bindings/clock/intel-clock.h > Reviewed-by: Bin Meng
Re: [PATCH v2 08/17] x86: coral: Update i2c and rtc status
On Tue, Feb 4, 2020 at 8:20 AM Simon Glass wrote: > > These are actually working correctly, so update the status. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > doc/board/google/chromebook_coral.rst | 2 -- > 1 file changed, 2 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v2 04/17] tegra: i2c: Change driver to use helper function
On Tue, Feb 4, 2020 at 8:20 AM Simon Glass wrote: > > Now that we have uclass_first_device_drvdata(), use it from the I2C driver > to reduce code duplication. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Add new patch to change tegra driver to use helper function > > drivers/i2c/tegra_i2c.c | 13 + > 1 file changed, 1 insertion(+), 12 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v2 03/17] dm: core: Change syscon to use helper function
On Tue, Feb 4, 2020 at 8:20 AM Simon Glass wrote: > > Now that we have uclass_first_device_drvdata(), use it from syscon to > reduce code duplication. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Add new patch to change syscon to use helper function > > drivers/core/syscon-uclass.c | 15 --- > 1 file changed, 4 insertions(+), 11 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v2 02/17] dm: core: Add a function to find a device by drvdata
On Tue, Feb 4, 2020 at 8:20 AM Simon Glass wrote: > > It is sometimes useful to find a device in a uclass using only its driver > data. The driver data often indicates the 'subtype' of the device, e,g, > via its compatible string. > > Add a function to handle this. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Add new patch to find a device by drvdata > > drivers/core/uclass.c | 17 + > include/dm/test.h | 2 ++ > include/dm/uclass.h | 14 ++ > test/dm/test-fdt.c| 21 + > 4 files changed, 54 insertions(+) > Reviewed-by: Bin Meng
Re: [PATCH v2 01/17] dm: core: Allow iterating devices without uclass_get()
On Tue, Feb 4, 2020 at 8:20 AM Simon Glass wrote: > > At present we have uclass_foreach_dev() which requires that uclass_get() > be called beforehand to find the uclass. This is good if we suspect that > that function might fail, but often we know that the uclass is available. > > Add a new helper which does this uclass_get() automatically, so that only > the uclass ID is needed. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Add new patch to allow iterating devices without uclass_get() > > include/dm/uclass.h | 17 + > test/dm/test-fdt.c | 21 + > 2 files changed, 38 insertions(+) > Reviewed-by: Bin Meng
Re: [PATCH v2] dm: uclass: don't assign aliased seq numbers
On 03. 02. 20 18:16, Michael Walle wrote:
> Hi Simon,
>
> Am 2020-01-30 03:16, schrieb Simon Glass:
>> Hi Michael,
>>
>> On Fri, 20 Dec 2019 at 06:29, Michael Walle wrote:
>>>
>>> If there are aliases for an uclass, set the base for the "dynamically"
>>> allocated numbers next to the highest alias.
>>>
>>> Please note, that this might lead to holes in the sequences, depending
>>> on the device tree. For example if there is only an alias "ethernet1",
>>> the next device seq number would be 2.
>>>
>>> In particular this fixes a problem with boards which are using ethernet
>>> aliases but also might have network add-in cards like the E1000. If the
>>> board is started with the add-in card and depending on the order of the
>>> drivers, the E1000 might occupy the first ethernet device and mess up
>>> all the hardware addresses, because the devices are now shifted by one.
>>>
>>> Cc: Thomas Fitzsimmons
>>> Cc: Michal Simek
>>> Signed-off-by: Michael Walle
>>> Reviewed-by: Alex Marginean
>>> Tested-by: Alex Marginean
>>> Acked-by: Vladimir Oltean
>>> ---
>>>
>>> As a side effect, this should also make the following commits
>>> superfluous:
>>> - 7f3289bf6d ("dm: device: Request next sequence number")
>>> - 61607225d1 ("i2c: Fill req_seq in i2c_post_bind()")
>>> Although I don't understand the root cause of the said problem.
>>>
>>> Thomas, Michal, could you please test this and then I'd add a second
>>> patch removing the old code.
>>
>> I think this is reasonable. We have discussed a possible rework of the
>> logic to merge seq and req_seq, but I don't think we have any patches
>> yet.
>>
>> Please can you add a test to your patch? You can put it in test-fdt.c
>> for example.
>
> Just did a new version.
>
>> If you are reverting the other patches, could you please send patches
>> for those?
>
> Unfortunatly, neither Thomas nor Michal has responded, so there would be
> no test if that would work. But I could certainly prepare two patches.
I still have this in my inbox to take a look and retest. I just don't
have time to take a look at it now. I have tested this code on board
with i2c mux where I was trying to change aliases.
Thanks,
Michal
Re: [RFC PATCH 03/10] i2c: mmc: add nexell driver (gpio, i2c, mmc, pwm)
Hello Stefan,
Am 03.02.2020 um 21:40 schrieb Stefan Bosch:
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- i2c/nx_i2c.c: Some adaptions mainly because of changes in
"struct udevice".
- mmc: nexell_dw_mmc.c changed to nexell_dw_mmc_dm.c (switched to DM).
Signed-off-by: Stefan Bosch
---
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/nx_gpio.c | 252 +++
drivers/i2c/Kconfig| 9 +
drivers/i2c/Makefile | 1 +
drivers/i2c/nx_i2c.c | 537 +
drivers/mmc/Kconfig| 6 +
drivers/mmc/Makefile | 1 +
drivers/mmc/nexell_dw_mmc_dm.c | 350 +++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-nexell.c | 252 +++
drivers/pwm/pwm-nexell.h | 54 +
Could you please split this patch into 4 parts (i2c, gpio, mmc and
pwm) ?
Thanks!
12 files changed, 1473 insertions(+)
create mode 100644 drivers/gpio/nx_gpio.c
create mode 100644 drivers/i2c/nx_i2c.c
create mode 100644 drivers/mmc/nexell_dw_mmc_dm.c
create mode 100644 drivers/pwm/pwm-nexell.c
create mode 100644 drivers/pwm/pwm-nexell.h
[...]
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 449046b..e3340de 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
+obj-$(CONFIG_NX_GPIO) += nx_gpio.o
Please keep lists sorted.
diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c
new file mode 100644
index 000..86472f6
--- /dev/null
+++ b/drivers/gpio/nx_gpio.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Nexell
+ * DeokJin, Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct nx_gpio_regs {
+ u32 data; /* Data register */
+ u32 outputenb; /* Output Enable register */
+ u32 detmode[2]; /* Detect Mode Register */
+ u32 intenb; /* Interrupt Enable Register */
+ u32 det;/* Event Detect Register */
+ u32 pad;/* Pad Status Register */
+};
+
+struct nx_alive_gpio_regs {
+ u32 pwrgate;/* Power Gating Register */
+ u32 reserved0[28]; /* Reserved0 */
+ u32 outputenb_reset;/* Alive GPIO Output Enable Reset Register */
+ u32 outputenb; /* Alive GPIO Output Enable Register */
+ u32 outputenb_read; /* Alive GPIO Output Read Register */
+ u32 reserved1[3]; /* Reserved1 */
+ u32 pad_reset; /* Alive GPIO Output Reset Register */
+ u32 data; /* Alive GPIO Output Register */
+ u32 pad_read; /* Alive GPIO Pad Read Register */
+ u32 reserved2[33]; /* Reserved2 */
+ u32 pad;/* Alive GPIO Input Value Register */
+};
+
+struct nx_gpio_platdata {
+ void *regs;
+ int gpio_count;
+ const char *bank_name;
+};
+
+static int nx_alive_gpio_is_check(struct udevice *dev)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ const char *bank_name = plat->bank_name;
+
+ if (!strcmp(bank_name, "gpio_alv"))
+ return 1;
+
+ return 0;
+}
+
+static int nx_alive_gpio_direction_input(struct udevice *dev, unsigned int pin)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+
+ setbits_le32(>outputenb_reset, 1 << pin);
+
+ return 0;
+}
+
+static int nx_alive_gpio_direction_output(struct udevice *dev, unsigned int
pin,
+ int val)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+
+ if (val)
+ setbits_le32(>data, 1 << pin);
+ else
+ setbits_le32(>pad_reset, 1 << pin);
+
+ setbits_le32(>outputenb, 1 << pin);
+
+ return 0;
+}
+
+static int nx_alive_gpio_get_value(struct udevice *dev, unsigned int pin)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+ unsigned int mask = 1UL << pin;
+ unsigned int value;
+
+ value = (readl(>pad_read) & mask) >> pin;
+
+ return value;
+}
+
+static int nx_alive_gpio_set_value(struct udevice *dev, unsigned int pin,
+ int val)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+
+ if (val)
+ setbits_le32(>data, 1 << pin);
+ else
+
Please pull u-boot-x86
Hi Tom,
This PR includes the following changes for v2020.04:
- Various minor fixes for x86
- Switch to ACPI mode on Intel edison
- Support run-time configuration for NS16550 driver
- Update coreboot and slimbootloader serial drivers to use NS16550
run-time configuration
- ICH SPI driver fixes to hardware sequencing erase case
- Move ITSS from Apollo Lake to a more generic location
- Intel GPIO driver bug fixes
- Move to vs2017-win2016 platform build host for Azure pipelines
Azure pipelines result:
https://dev.azure.com/bmeng/GitHub/_build/results?buildId=154=results
It just took 1h 57m 0s for Azure to complete the build, but GitLab's
pipelines is still pending. I don't know why.
The following changes since commit 31a790bee939e227dfc7e6a6a323b2b13180707f:
Merge branch 'master' of git://git.denx.de/u-boot-usb (2020-02-02
15:26:53 -0500)
are available in the git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-x86
for you to fetch changes up to 9e0c131a32028547cc4834f238c614af2675c66d:
azure: Move to vs2017-win2016 platform build host (2020-02-04 12:54:55 +0800)
Andy Shevchenko (1):
x86: edison: Switch to ACPI mode
Heinrich Schuchardt (1):
doc: Chromebook Coral: fix build warnings
Marek Vasut (1):
x86: edison: Enable command line editing
Masahiro Yamada (2):
x86: use invd instead of wbinvd in real mode start code
x86: limit the fs segment to the pointer size
Park, Aiden (2):
x86: serial: Use NS16550_DYNAMIC in Slim Bootloader
doc: intel: Update serial driver changes in slimbootloader.rst
Simon Glass (4):
serial: ns16550: Support run-time configuration
x86: Update coreboot serial table struct
x86: serial: Add a coreboot serial driver
x86: Move coreboot over to use the coreboot UART
Tom Rini (1):
azure: Move to vs2017-win2016 platform build host
Wolfgang Wallner (9):
spi: ich: Drop while loop in hardware sequencing erase case
x86: apl: Add the term "Interrupt Timer Subsystem" to ITSS files
x86: Move itss.h from Apollo Lake to the generic x86 include directory
x86: Move itss.c from Apollo Lake to a more generic location
x86: itss: Add a Kconfig option to enable/disable ITSS driver
x86: itss: Remove apl-prefix
gpio: intel_gpio: Pass pinctrl device to pcr_clrsetbits32()
gpio: intel_gpio: Clear tx state bit when setting output
gpio: intel_gpio: Fix register/bit offsets intel_gpio_get_value()
.azure-pipelines.yml | 2 +-
arch/x86/Kconfig | 6 ++
arch/x86/cpu/apollolake/Kconfig | 1 +
arch/x86/cpu/apollolake/Makefile | 1 -
arch/x86/cpu/i386/cpu.c | 10 +++---
arch/x86/cpu/intel_common/Makefile| 1 +
arch/x86/cpu/{apollolake => intel_common}/itss.c | 60
++--
arch/x86/cpu/slimbootloader/serial.c | 13 +
arch/x86/cpu/start.S | 2 +-
arch/x86/cpu/start16.S| 2 +-
arch/x86/dts/chromebook_coral.dts | 2 +-
arch/x86/dts/coreboot.dts | 6 +-
arch/x86/include/asm/coreboot_tables.h| 19 +++
arch/x86/include/asm/{arch-apollolake => }/itss.h | 2 ++
configs/edison_defconfig | 2 +-
doc/board/google/chromebook_coral.rst | 90
++
doc/board/intel/slimbootloader.rst| 35
---
drivers/gpio/intel_gpio.c | 10 +-
drivers/pinctrl/intel/pinctrl.c | 2 +-
drivers/serial/Kconfig| 32
drivers/serial/Makefile | 1 +
drivers/serial/ns16550.c | 79
+++
drivers/serial/serial_coreboot.c | 46
++
drivers/spi/ich.c | 12 ++--
include/configs/slimbootloader.h | 13 -
include/ns16550.h | 16 +++-
26 files changed, 308 insertions(+), 157 deletions(-)
rename arch/x86/cpu/{apollolake => intel_common}/itss.c (73%)
rename arch/x86/include/asm/{arch-apollolake => }/itss.h (97%)
create mode 100644 drivers/serial/serial_coreboot.c
Regards,
Bin
[PATCH] configs: lx2160a: Define ENV_SECT_SIZE
LX2160ARDB/QDS has mt35xu512aba flash with 128K sector size. Define ENV_SECT_SIZE value as 0x2. Signed-off-by: Kuldeep Singh --- configs/lx2160aqds_tfa_defconfig | 3 ++- configs/lx2160ardb_tfa_defconfig | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 36e7bbd..e09417b 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -4,6 +4,7 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x8200 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x2 CONFIG_ENV_OFFSET=0x50 CONFIG_DM_GPIO=y CONFIG_FSPI_AHB_EN_4BYTE=y @@ -59,8 +60,8 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index fdeacd8..15567d2 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -4,6 +4,7 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x8200 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x2 CONFIG_ENV_OFFSET=0x50 CONFIG_DM_GPIO=y CONFIG_EMC2305=y @@ -58,8 +59,8 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -- 2.7.4
Re: [PATCH v2 04/10] mmc: sdhci: Expose sdhci_init() as non-static
Hi, On 31/01/20 3:55 am, Simon Goldschmidt wrote: > Am 30.01.2020 um 23:21 schrieb Jaehoon Chung: >> Hi Simon, >> >> On 1/29/20 11:16 PM, Simon Goldschmidt wrote: >>> On Wed, Jan 29, 2020 at 12:00 AM Jaehoon Chung >>> wrote: On 1/24/20 8:52 PM, Faiz Abbas wrote: > Expose sdhci_init() as non-static. Does it need to change to non-static? >>> >>> And even if it needs to, can we have a reason *why* in the commit >>> message? >> >> When i read entire your series, it seems that doesn't need to change >> to non-static. >> All of change that touched MMC code are only for your board. >> I don't know Peng's opinion, but it's not my prefer. > > +1! > > We need to keep the core code clean of such hacks in order to keep the > size small for constrained targets! > Peng can you comment on this? Jaehoon, I am not sure what you mean by "it doesn't need to change to non-static". How would I call the sdhci_init() function from my platform driver otherwise? Thanks, Faiz
[PATCH v7 08/10] include: configs: j721e_evm: Add env variables for mcu_r5fss0_core0 & main_r5fss0_core0
Add env variables for mcu_r5fss0_core0 & main_r5fss0_core0 firmware
loadaddr and name.
Signed-off-by: Keerthy
---
include/configs/j721e_evm.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 4371c471e5..fc73a9c932 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -88,6 +88,10 @@
"mmcdev=1\0"\
"bootpart=1:2\0"\
"bootdir=/boot\0" \
+ "addr_mainr5f0_0load=8800\0"
\
+ "name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \
+ "addr_mcur5f0_0load=8900\0" \
+ "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" \
"rd_spec=-\0" \
"init_mmc=run args_all args_mmc\0" \
"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
--
2.17.1
[PATCH v7 10/10] configs: j721e_evm_r5_defconfig: Remove saving ENV in eMMC
Remove saving ENV in eMMC in R5 as the power domains are not setup. Environment in eMMC cannot be read if we do not boot from eMMC. Signed-off-by: Keerthy --- configs/j721e_evm_r5_defconfig | 4 1 file changed, 4 deletions(-) diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index b1fc919f6a..67fde3bc5d 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -7,7 +7,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x7 CONFIG_SOC_K3_J721E=y CONFIG_TARGET_J721E_R5_EVM=y CONFIG_ENV_SIZE=0x2 -CONFIG_ENV_OFFSET=0x68 CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y @@ -52,9 +51,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_OFFSET_REDUND=0x70 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y -- 2.17.1
[PATCH v7 09/10] configs: j721e_evm_r5: Enable R5F remoteproc support
Enable R5F remoteproc support in R5 defconfig so that R5s can be started in SPL. While at it enable the SPL_FS_EXT4 config option to load the firmwares from file system. Signed-off-by: Keerthy Signed-off-by: Lokesh Vutla --- configs/j721e_evm_r5_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 19fbd450c7..b1fc919f6a 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y @@ -96,6 +97,7 @@ CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_TPS65941=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y -- 2.17.1
[PATCH v7 05/10] armv7R: K3: Add support for jumping to firmware
MCU Domain rf50 is currently shutting down after loading the ATF.
Load elf firmware and jump to firmware post loading ATF.
ROM doesn't enable ATCM memory, so make sure that firmware that
is being loaded doesn't use ATCM memory or override SPL.
Signed-off-by: Keerthy
Signed-off-by: Lokesh Vutla
---
arch/arm/mach-k3/common.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index bddb62ea5e..5c5eedb6eb 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -132,8 +132,10 @@ __weak void start_non_linux_remote_cores(void)
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
+ typedef void __noreturn (*image_entry_noargs_t)(void);
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
- int ret;
+ u32 loadaddr = 0;
+ int ret, size;
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
@@ -144,6 +146,9 @@ void __noreturn jump_to_image_no_args(struct spl_image_info
*spl_image)
init_env();
start_non_linux_remote_cores();
+ size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
+);
+
/*
* It is assumed that remoteproc device 1 is the corresponding
@@ -159,13 +164,18 @@ void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
ret = rproc_start(1);
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
+ if (!(size > 0 && valid_elf_image(loadaddr))) {
+ debug("Shutting down...\n");
+ release_resources_for_core_shutdown();
+
+ while (1)
+ asm volatile("wfe");
+ }
- debug("Releasing resources...\n");
- release_resources_for_core_shutdown();
+ image_entry_noargs_t image_entry =
+ (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
- debug("Finalizing core shutdown...\n");
- while (1)
- asm volatile("wfe");
+ image_entry();
}
#endif
--
2.17.1
[PATCH v7 06/10] arm: dts: k3-j721e-r5-u-boot: Add fs_loader node
Add fs_loader node which will be needed for loading firmwares
from the boot media/filesystem.
Signed-off-by: Keerthy
Reviewed-by: Tom Rini
---
.../dts/k3-j721e-r5-common-proc-board-u-boot.dtsi | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
new file mode 100644
index 00..f98be993e8
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/ {
+ chosen {
+ firmware-loader = _loader0;
+ };
+
+ fs_loader0: fs_loader@0 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ };
+};
--
2.17.1
[PATCH v7 07/10] arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL
Enable MAIN domain r5fss0 cluster and its core0 in R5 spl.
Signed-off-by: Keerthy
Reviewed-by: Tom Rini
---
.../dts/k3-j721e-r5-common-proc-board-u-boot.dtsi| 12
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 2 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
index f98be993e8..526f42e3a9 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
@@ -13,3 +13,15 @@
compatible = "u-boot,fs-loader";
};
};
+
+_r5fss0 {
+ u-boot,dm-spl;
+};
+
+_r5fss0_core0 {
+ u-boot,dm-spl;
+};
+
+_r5fss0_core1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 1f14d71438..ba2a312602 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -13,6 +13,8 @@
aliases {
remoteproc0 =
remoteproc1 = _0;
+ remoteproc2 = _r5fss0_core0;
+ remoteproc3 = _r5fss0_core1;
};
chosen {
--
2.17.1
[PATCH v7 03/10] arm: k3: Add support for loading non linux remote cores
Add MAIN domain R5FSS0 remoteproc support from spl. This enables
loading the elf firmware in SPL and starting the remotecore.
In order to start the core, there should be a file with path
"/lib/firmware/j7-main-r5f0_0-fw" under filesystem
of respective boot mode.
Signed-off-by: Keerthy
Signed-off-by: Lokesh Vutla
[Guard start_non_linux_remote_cores under CONFIG_FS_LOADER]
Signed-off-by: Andreas Dannenberg
---
arch/arm/mach-k3/common.c | 84 ---
arch/arm/mach-k3/common.h | 2 +
arch/arm/mach-k3/j721e_init.c | 34 ++
3 files changed, 115 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 2f82edb970..bddb62ea5e 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -17,6 +17,10 @@
#include
#include
#include
+#include
+#include
+#include
+#include
struct ti_sci_handle *get_ti_sci_handle(void)
{
@@ -58,6 +62,74 @@ int early_console_init(void)
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF
+
+void init_env(void)
+{
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ char *part;
+
+ env_init();
+ env_load();
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC2:
+ part = env_get("bootpart");
+ env_set("storage_interface", "mmc");
+ env_set("fw_dev_part", part);
+ break;
+ case BOOT_DEVICE_SPI:
+ env_set("storage_interface", "ubi");
+ env_set("fw_ubi_mtdpart", "UBI");
+ env_set("fw_ubi_volume", "UBI0");
+ break;
+ default:
+ printf("%s from device %u not supported!\n",
+ __func__, spl_boot_device());
+ return;
+ }
+#endif
+}
+
+#ifdef CONFIG_FS_LOADER
+int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
+{
+ struct udevice *fsdev;
+ char *name = NULL;
+ int size = 0;
+
+ *loadaddr = 0;
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC2:
+ name = env_get(name_fw);
+ *loadaddr = env_get_hex(name_loadaddr, *loadaddr);
+ break;
+ default:
+ printf("Loading rproc fw image from device %u not supported!\n",
+ spl_boot_device());
+ return 0;
+ }
+#endif
+ if (!*loadaddr)
+ return 0;
+
+ if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, )) {
+ size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
+0, 0);
+ }
+
+ return size;
+}
+#else
+int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
+{
+ return 0;
+}
+#endif
+
+__weak void start_non_linux_remote_cores(void)
+{
+}
+
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
@@ -66,15 +138,17 @@ void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
+ ret = rproc_init();
+ if (ret)
+ panic("rproc failed to be initialized (%d)\n", ret);
+
+ init_env();
+ start_non_linux_remote_cores();
+
/*
* It is assumed that remoteproc device 1 is the corresponding
* Cortex-A core which runs ATF. Make sure DT reflects the same.
*/
- ret = rproc_dev_init(1);
- if (ret)
- panic("%s: ATF failed to initialize on rproc (%d)\n", __func__,
- ret);
-
ret = rproc_load(1, spl_image->entry_point, 0x200);
if (ret)
panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index d8b34fe060..42fb8ee6e7 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -24,3 +24,5 @@ void setup_k3_mpu_regions(void);
int early_console_init(void);
void disable_linefill_optimization(void);
void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
+void start_non_linux_remote_cores(void);
+int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index f7f7398081..13f3791823 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_K3_LOAD_SYSFW
@@ -295,3 +296,36 @@ void release_resources_for_core_shutdown(void)
}
}
#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+void start_non_linux_remote_cores(void)
+{
+ int size = 0, ret;
+ u32 loadaddr = 0;
+
+ size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
+);
+
[PATCH v7 01/10] env: nowhere: set default enviroment
In case only CONFIG_ENV_IS_NOWHERE without any of the memory
based configs like CONFIG_ENV_IS_IN_MMC the env_set function
fails as the gd->flags & GD_FLG_ENV_READY check fails.
Set default enviroment so that set_env calls succeed when only
ENV_IS_NOWHERE set.
Signed-off-by: Keerthy
Reviewed-by: Tom Rini
---
env/nowhere.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/env/nowhere.c b/env/nowhere.c
index f5b0a17652..70c3b3e011 100644
--- a/env/nowhere.c
+++ b/env/nowhere.c
@@ -23,6 +23,7 @@ static int env_nowhere_init(void)
{
gd->env_addr= (ulong)_environment[0];
gd->env_valid = ENV_INVALID;
+ env_set_default(NULL, 0);
return 0;
}
--
2.17.1
[PATCH v7 02/10] lib: elf: Move the generic elf loading/validating functions to lib
Move the generic elf loading/validating functions to lib/
so that they can be re-used and accessed by code existing
outside cmd.
While at it remove the duplicate static version of load_elf_image_phdr
under arch/arm/mach-imx/imx_bootaux.c.
Signed-off-by: Keerthy
Suggested-by: Simon Goldschmidt
Reviewed-by: Simon Goldschmidt
---
arch/arm/mach-imx/imx_bootaux.c | 46 --
cmd/Kconfig | 1 +
cmd/elf.c | 229 -
include/elf.h | 4 +
lib/Kconfig | 6 +
lib/Makefile| 1 +
lib/elf.c | 246
7 files changed, 258 insertions(+), 275 deletions(-)
create mode 100644 lib/elf.c
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 21e96f8c88..8092268a3b 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -28,52 +28,6 @@ static const struct rproc_att *get_host_mapping(unsigned
long auxcore)
return NULL;
}
-
-/*
- * A very simple elf loader, assumes the image is valid, returns the
- * entry point address.
- */
-static unsigned long load_elf_image_phdr(unsigned long addr)
-{
- Elf32_Ehdr *ehdr; /* ELF header structure pointer */
- Elf32_Phdr *phdr; /* Program header structure pointer */
- int i;
-
- ehdr = (Elf32_Ehdr *)addr;
- phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
-
- /* Load each program header */
- for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) {
- const struct rproc_att *mmap = get_host_mapping(phdr->p_paddr);
- void *dst, *src;
-
- if (phdr->p_type != PT_LOAD)
- continue;
-
- if (!mmap) {
- printf("Invalid aux core address: %08x",
- phdr->p_paddr);
- return 0;
- }
-
- dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa;
- src = (void *)addr + phdr->p_offset;
-
- debug("Loading phdr %i to 0x%p (%i bytes)\n",
- i, dst, phdr->p_filesz);
-
- if (phdr->p_filesz)
- memcpy(dst, src, phdr->p_filesz);
- if (phdr->p_filesz != phdr->p_memsz)
- memset(dst + phdr->p_filesz, 0x00,
- phdr->p_memsz - phdr->p_filesz);
- flush_cache((unsigned long)dst &
- ~(CONFIG_SYS_CACHELINE_SIZE - 1),
- ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE));
- }
-
- return ehdr->e_entry;
-}
#endif
int arch_auxiliary_core_up(u32 core_id, ulong addr)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index e6ba57035e..9819dd1aaf 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -399,6 +399,7 @@ config CMD_ABOOTIMG
config CMD_ELF
bool "bootelf, bootvx"
default y
+ select LIB_ELF
help
Boot an ELF/vxWorks image from the memory.
diff --git a/cmd/elf.c b/cmd/elf.c
index ba06df06cf..c129077e20 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -27,211 +27,6 @@
#include
#endif
-/*
- * A very simple ELF64 loader, assumes the image is valid, returns the
- * entry point address.
- *
- * Note if U-Boot is 32-bit, the loader assumes the to segment's
- * physical address and size is within the lower 32-bit address space.
- */
-static unsigned long load_elf64_image_phdr(unsigned long addr)
-{
- Elf64_Ehdr *ehdr; /* Elf header structure pointer */
- Elf64_Phdr *phdr; /* Program header structure pointer */
- int i;
-
- ehdr = (Elf64_Ehdr *)addr;
- phdr = (Elf64_Phdr *)(addr + (ulong)ehdr->e_phoff);
-
- /* Load each program header */
- for (i = 0; i < ehdr->e_phnum; ++i) {
- void *dst = (void *)(ulong)phdr->p_paddr;
- void *src = (void *)addr + phdr->p_offset;
-
- debug("Loading phdr %i to 0x%p (%lu bytes)\n",
- i, dst, (ulong)phdr->p_filesz);
- if (phdr->p_filesz)
- memcpy(dst, src, phdr->p_filesz);
- if (phdr->p_filesz != phdr->p_memsz)
- memset(dst + phdr->p_filesz, 0x00,
- phdr->p_memsz - phdr->p_filesz);
- flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN),
- roundup(phdr->p_memsz, ARCH_DMA_MINALIGN));
- ++phdr;
- }
-
- if (ehdr->e_machine == EM_PPC64 && (ehdr->e_flags &
- EF_PPC64_ELFV1_ABI)) {
- /*
-* For the 64-bit PowerPC ELF V1 ABI, e_entry is a function
-* descriptor pointer with the first double word being the
-* address of the entry point of the function.
-*/
- uintptr_t addr = ehdr->e_entry;
-
-
[PATCH v7 04/10] armv7R: K3: r5_mpu: Enable execute permission for MCU0 BTCM
Enable execute permission for mcu_r5fss0_core0 BTCM so that we can jump
to a firmware directly from SPL.
Signed-off-by: Keerthy
---
arch/arm/mach-k3/r5_mpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c
index ee076ed877..3d2ff6775a 100644
--- a/arch/arm/mach-k3/r5_mpu.c
+++ b/arch/arm/mach-k3/r5_mpu.c
@@ -26,7 +26,9 @@ struct mpu_region_config k3_mpu_regions[16] = {
/* U-Boot's code area marking it as WB and Write allocate */
{CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_2GB},
- {0x0, 3, 0x0, 0x0, 0x0, 0x0},
+ /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
+ {0x4101, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,
+REGION_8MB},
{0x0, 4, 0x0, 0x0, 0x0, 0x0},
{0x0, 5, 0x0, 0x0, 0x0, 0x0},
{0x0, 6, 0x0, 0x0, 0x0, 0x0},
--
2.17.1
[PATCH v7 00/10] Add support for loading main_r5fss0_core0
This patch series enables mcu_r5fss0_core0 & main_r5fss0_core0. Tested for firmware loading and execution on J721e. Changes in v7: * Added BSD-2 SPDX on lib/elf.c file. * Added Tom's Reviewed-by for the relevant patches. Changes in v6: * Fixed the imx build issue. Changes in v5: * Moved the fs_loader node under r5-common-proc-board-u-boot.dtsi * Added more information on the envnowhere patch. * Added help LIB_ELF option and removed user configurable description. Changes in v4: * Changed env variable names, config names and enhanced commit logs. Changes in v3: * Removed saving env in MMC and fixed env saving in SPL when nowhere option is set. Changes in v2: * Factored out all the generic elf handling functions under lib/elf.c Keerthy (10): env: nowhere: set default enviroment lib: elf: Move the generic elf loading/validating functions to lib arm: k3: Add support for loading non linux remote cores armv7R: K3: r5_mpu: Enable execute permission for MCU0 BTCM armv7R: K3: Add support for jumping to firmware arm: dts: k3-j721e-r5-u-boot: Add fs_loader node arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL include: configs: j721e_evm: Add env variables for mcu_r5fss0_core0 & main_r5fss0_core0 configs: j721e_evm_r5: Enable R5F remoteproc support configs: j721e_evm_r5_defconfig: Remove saving ENV in eMMC .../k3-j721e-r5-common-proc-board-u-boot.dtsi | 27 ++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 2 + arch/arm/mach-imx/imx_bootaux.c | 46 arch/arm/mach-k3/common.c | 106 +++- arch/arm/mach-k3/common.h | 2 + arch/arm/mach-k3/j721e_init.c | 34 +++ arch/arm/mach-k3/r5_mpu.c | 4 +- cmd/Kconfig | 1 + cmd/elf.c | 229 configs/j721e_evm_r5_defconfig| 6 +- env/nowhere.c | 1 + include/configs/j721e_evm.h | 4 + include/elf.h | 4 + lib/Kconfig | 6 + lib/Makefile | 1 + lib/elf.c | 246 ++ 16 files changed, 428 insertions(+), 291 deletions(-) create mode 100644 arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi create mode 100644 lib/elf.c -- 2.17.1
[PATCH] configs: lx2160a: Define ENV_ADDR value
CONFIG_ENV_ADDR helps in picking environment from flash before DDR init. Define the value as 0x2050 for lx2160ardb and lx2160aqds. Signed-off-by: Kuldeep Singh --- Hi Priyanka, This patch can be applied after applying below patch. https://patchwork.ozlabs.org/project/uboot/list/?series=141023 configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 987b8c3..36e7bbd 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -33,6 +33,7 @@ CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x2050 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 0b0a2b2..fdeacd8 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -34,6 +34,7 @@ CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x2050 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -- 2.7.4
Re: [PATCH v5 02/10] lib: elf: Move the generic elf loading/validating functions to lib
On 29/01/20 9:27 pm, Tom Rini wrote: On Tue, Jan 28, 2020 at 04:21:07PM +0530, Keerthy wrote: Move the generic elf loading/validating functions to lib/ so that they can be re-used and accessed by code existing outside cmd. Signed-off-by: Keerthy Suggested-by: Simon Goldschmidt Reviewed-by: Simon Goldschmidt [snip] diff --git a/lib/elf.c b/lib/elf.c new file mode 100644 index 00..c2097305ec --- /dev/null +++ b/lib/elf.c @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2001 William L. Pitts + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ Ah, I see. cmd/elf.c is missing the SPDX tag, which this also needs. I looked and I don't think it's fair to ask you to put the SDPX tag on cmd/elf.c so I'm going to update it to BSD-2-Clause. You should depend on that patch and use the same tag here. Tom, I fixed that myself for lib/elf.c. Sending v7 with that fixed and with your Reviewed-by for the relevant patches. Let me know if that version looks good. Thanks, Keerthy
[PATCH v2 12/12] configs: j721e_hs_evm: Enable OSPI related configs
Enable OSPI related configs for J721e HS variant. Signed-off-by: Vignesh Raghavendra --- configs/j721e_hs_evm_a72_defconfig | 8 +++- configs/j721e_hs_evm_r5_defconfig | 7 +++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index dd552c5d1a22..ef8e1fb50eb6 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -35,6 +35,8 @@ CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 CONFIG_SPL_YMODEM_SUPPORT=y @@ -53,7 +55,8 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0,nor0=47034000.hyperbus" -CONFIG_MTDPARTS_DEFAULT="mtdparts=47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=4704.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)" +CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y @@ -107,7 +110,10 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_HBMC_AM654=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_TI=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig index 9348be332012..784b51b1d2aa 100644 --- a/configs/j721e_hs_evm_r5_defconfig +++ b/configs/j721e_hs_evm_r5_defconfig @@ -27,6 +27,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y @@ -36,6 +37,8 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x8 CONFIG_SPL_YMODEM_SUPPORT=y @@ -63,6 +66,8 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y @@ -79,6 +84,7 @@ CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set @@ -97,6 +103,7 @@ CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y -- 2.25.0
[PATCH v2 11/12] configs: ama65x_hs_evm: Enable OSPI related configs
Enable OSPI related defconfigs for AM65x HS variant. Signed-off-by: Vignesh Raghavendra --- configs/am65x_hs_evm_a53_defconfig | 26 ++ configs/am65x_hs_evm_r5_defconfig | 19 +++ 2 files changed, 45 insertions(+) diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 6097a0224718..29d9f2b16873 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -15,6 +15,8 @@ CONFIG_SPL_STACK_R_ADDR=0x8200 CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0x8008 CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -28,16 +30,26 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=4704.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)" +CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y @@ -52,6 +64,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y @@ -66,6 +80,15 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y @@ -77,6 +100,9 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig index 0cdfc735b6ac..91178f87219d 100644 --- a/configs/am65x_hs_evm_r5_defconfig +++ b/configs/am65x_hs_evm_r5_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_STACK_R_ADDR=0x8200 CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0x41c0 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y @@ -27,6 +29,7 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y @@ -35,6 +38,10 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -58,10 +65,14 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y @@ -72,6 +83,10 @@ CONFIG_K3_SEC_PROXY=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y @@ -90,6 +105,10 @@ CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y -- 2.25.0
[PATCH v2 09/12] configs: am65x_evm_defconfig: Enable OSPI configs
Enable OSPI related defconfigs. Also enable SPL_DMA so that DMA is used during OSPI boot Signed-off-by: Vignesh Raghavendra --- configs/am65x_evm_a53_defconfig | 25 + configs/am65x_evm_r5_defconfig | 17 + 2 files changed, 42 insertions(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 079cd912ba34..f175d20a66c0 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -15,6 +15,8 @@ CONFIG_SPL_STACK_R_ADDR=0x8200 CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y # CONFIG_PSCI_RESET is not set CONFIG_SPL_TEXT_BASE=0x8008 CONFIG_DISTRO_DEFAULTS=y @@ -28,10 +30,17 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y @@ -40,9 +49,13 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=4704.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)" +CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -58,11 +71,13 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -78,6 +93,13 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_TI=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y @@ -102,6 +124,9 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 69055d553609..4dc5f384e7dd 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_STACK_R_ADDR=0x8200 CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0x41c0 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y @@ -26,6 +28,7 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y @@ -34,6 +37,10 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -63,6 +70,8 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y @@ -76,6 +85,10 @@ CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y @@ -95,6 +108,10 @@ CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y -- 2.25.0
[PATCH v2 07/12] configs: j721e_evm: Setup mtdparts for OSPI
Set up mtdparts cmdline argument to be passed to kernel
Signed-off-by: Vignesh Raghavendra
---
include/configs/j721e_evm.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 4371c471e5a9..0f8a9739a13f 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -74,7 +74,8 @@
"overlayaddr=0x8300\0" \
"name_kern=Image\0" \
"console=ttyS2,115200n8\0" \
- "args_all=setenv optargs earlycon=ns16550a,mmio32,0x0280\0" \
+ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x0280 " \
+ "${mtdparts}\0" \
"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
#define PARTS_DEFAULT \
@@ -124,6 +125,14 @@
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_OSPI
+#ifdef CONFIG_TARGET_J721E_A72_EVM
+#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"\
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#else
+#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD
+#endif
+
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_MMC_TI_ARGS \
@@ -132,7 +141,8 @@
EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
EXTRA_ENV_RPROC_SETTINGS\
EXTRA_ENV_DFUARGS \
- DEFAULT_UFS_TI_ARGS
+ DEFAULT_UFS_TI_ARGS \
+ EXTRA_ENV_J721E_BOARD_SETTINGS_MTD
/* Now for the remaining common defines */
#include
--
2.25.0
[PATCH v2 08/12] configs: j721e_evm_defconfig: Enable OSPI configs
Enable OSPI related defconfigs. Also enable SPL_DMA so that DMA is used during OSPI boot Signed-off-by: Vignesh Raghavendra --- configs/j721e_evm_a72_defconfig | 9 - configs/j721e_evm_r5_defconfig | 7 +++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 8355abbaa7f2..581a4c45402b 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y @@ -35,6 +36,8 @@ CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 CONFIG_SPL_USB_GADGET=y @@ -56,7 +59,8 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0,nor0=47034000.hyperbus" -CONFIG_MTDPARTS_DEFAULT="mtdparts=47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=4704.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)" +CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y @@ -113,7 +117,10 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_HBMC_AM654=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_TI=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 19fbd450c754..d31c116aa695 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -25,6 +25,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y @@ -34,6 +35,8 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x8 CONFIG_SPL_USB_GADGET=y @@ -64,6 +67,8 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y @@ -81,6 +86,7 @@ CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set @@ -99,6 +105,7 @@ CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y -- 2.25.0
[PATCH v2 10/12] board: ti: Update AM65x and J721e READMEs for OSPI boot
Update AM65x and J721e README files with instructions for flashing OSPI
images.
Signed-off-by: Vignesh Raghavendra
---
board/ti/am65x/README | 55 +++
board/ti/j721e/README | 47
2 files changed, 102 insertions(+)
diff --git a/board/ti/am65x/README b/board/ti/am65x/README
index 2e3fd9c4a810..86868e8c705f 100644
--- a/board/ti/am65x/README
+++ b/board/ti/am65x/README
@@ -262,6 +262,61 @@ To boot kernel from eMMC, use the following commands:
=> setenv bootpart 0
=> boot
+OSPI:
+-
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
+and sysfw.itb over tftp and then flash those to OSPI at their respective
+addresses.
+
+=> sf probe
+=> tftp ${loadaddr} tiboot3.bin
+=> sf update $loadaddr 0x0 $filesize
+=> tftp ${loadaddr} tispl.bin
+=> sf update $loadaddr 0x8 $filesize
+=> tftp ${loadaddr} u-boot.img
+=> sf update $loadaddr 0x28 $filesize
+=> tftp ${loadaddr} sysfw.itb
+=> sf update $loadaddr 0x6C $filesize
+
+Flash layout for OSPI:
+
+ 0x0 ++
+ | ospi.tiboot3(512K) |
+ ||
+ 0x8 ++
+ | ospi.tispl(2M) |
+ ||
+0x28 ++
+ | ospi.u-boot(4M)|
+ ||
+0x68 ++
+ | ospi.env(128K) |
+ ||
+0x6A ++
+| ospi.env.backup (128K) |
+||
+0x6C ++
+ | ospi.sysfw(1M)|
+ ||
+0x7C ++
+| padding (256k)|
+0x80 ++
+ | ospi.rootfs(UBIFS) |
+ ||
+ ++
+
+Kernel Image and DT are expected to be present in the /boot folder of UBIFS
+ospi.rootfs just like in SD card case. U-Boot looks for UBI volume named
+"rootfs" for rootfs.
+
+To boot kernel from OSPI, at the U-Boot prompt:
+=> setenv boot ubi
+=> boot
+
UART:
-
ROM supports booting from MCU_UART0 via X-Modem protocol. The entire UART-based
diff --git a/board/ti/j721e/README b/board/ti/j721e/README
index 5be7d099db96..739d4933fcf3 100644
--- a/board/ti/j721e/README
+++ b/board/ti/j721e/README
@@ -225,3 +225,50 @@ Image formats:
| |Secure config | |
| +---+ |
+---+
+
+OSPI:
+-
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
+and sysfw.itb over tftp and then flash those to OSPI at their respective
+addresses.
+
+=> sf probe
+=> tftp ${loadaddr} tiboot3.bin
+=> sf update $loadaddr 0x0 $filesize
+=> tftp ${loadaddr} tispl.bin
+=> sf update $loadaddr 0x8 $filesize
+=> tftp ${loadaddr} u-boot.img
+=> sf update $loadaddr 0x28 $filesize
+=> tftp ${loadaddr} sysfw.itb
+=> sf update $loadaddr 0x6C $filesize
+
+Flash layout for OSPI:
+
+ 0x0 ++
+ | ospi.tiboot3(512K) |
+ ||
+ 0x8 ++
+ | ospi.tispl(2M) |
+ ||
+0x28 ++
+ | ospi.u-boot(4M)|
+ ||
+0x68 ++
+ | ospi.env(128K) |
+ ||
+0x6A ++
+| ospi.env.backup (128K) |
+||
+0x6C ++
+ | ospi.sysfw(1M)|
+ ||
+0x7C ++
+| padding (256k)|
+0x80 ++
+ | ospi.rootfs(UBIFS) |
+ ||
+ ++
--
2.25.0
[PATCH v2 05/12] ARM: dts: k3-j721e: Add OSPI DT nodes
Add OSPI DT nodes to enable OSPI at U-Boot prompt and also to support
OSPI boot.
Signed-off-by: Vignesh Raghavendra
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 16
arch/arm/dts/k3-j721e-common-proc-board.dts | 33
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 31 +++
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 39 +++
arch/arm/dts/k3-j721e-som-p0.dtsi | 36 +
arch/arm/dts/k3-j721e.dtsi| 2 +
6 files changed, 157 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index a3a81932168e..d422100d42c5 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -349,3 +349,19 @@
{
u-boot,dm-spl;
};
+
+_fss0_ospi0_pins_default {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+
+ flash@0 {
+ u-boot,dm-spl;
+ };
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts
b/arch/arm/dts/k3-j721e-common-proc-board.dts
index d216b707fd2c..496a15e1d1ac 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -123,6 +123,19 @@
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24)
WKUP_I2C0_SDA */
>;
};
+
+ mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22)
MCU_OSPI1_CLK */
+ J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22)
MCU_OSPI1_CSn0 */
+ J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22)
MCU_OSPI1_D0 */
+ J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22)
MCU_OSPI1_D1 */
+ J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23)
MCU_OSPI1_D2 */
+ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23)
MCU_OSPI1_D3 */
+ J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23)
MCU_OSPI1_DQS */
+ J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23)
MCU_OSPI1_LBCLKO */
+ >;
+ };
};
{
@@ -172,3 +185,23 @@
#gpio-cells = <2>;
};
};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_fss0_ospi1_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <4000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index fe52fd1b2f9f..a9e97f219bd0 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -143,6 +143,37 @@
assigned-clocks = <_clks 102 0>;
assigned-clock-rates = <25000>;
};
+
+ ospi0: spi@4704 {
+ compatible = "ti,am654-ospi";
+ reg = <0x0 0x4704 0x0 0x100>,
+ <0x5 0x 0x1 0x000>;
+ interrupts = ;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <_clks 103 0>;
+ assigned-clocks = <_clks 103 0>;
+ assigned-clock-parents = <_clks 103 2>;
+ assigned-clock-rates = <1>;
+ power-domains = <_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ospi1: spi@4705 {
+ compatible = "ti,am654-ospi";
+ reg = <0x0 0x4705 0x0 0x100>,
+ <0x7 0x 0x1 0x>;
+ interrupts = ;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <_clks 104 0>;
+ power-domains = <_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
mcu_i2c0: i2c@40b0 {
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 1f14d71438b4..d243208c0b11 100644
---
[PATCH v2 06/12] configs: am65x_evm: Setup mtdparts for OSPI
Set up mtdparts cmdline argument to be passed to kernel
Signed-off-by: Vignesh Raghavendra
---
include/configs/am65x_evm.h | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 7d7f86a0598a..4e095342c0b3 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -73,7 +73,8 @@
"name_kern=Image\0" \
"console=ttyS2,115200n8\0" \
"stdin=serial,usbkbd\0" \
- "args_all=setenv optargs earlycon=ns16550a,mmio32,0x0280\0" \
+ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x0280 " \
+ "${mtdparts}\0" \
"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"\
/* U-Boot MMC-specific configuration */
@@ -106,6 +107,22 @@
"0 /lib/firmware/am65x-mcu-r5f0_0-fw " \
"1 /lib/firmware/am65x-mcu-r5f0_1-fw "
+#ifdef CONFIG_TARGET_AM654_A53_EVM
+#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"\
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#else
+#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD
+#endif
+
+#define EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \
+ "init_ubi=run args_all args_ubi; sf probe; "\
+ "ubi part ospi.rootfs; ubifsmount ubi:rootfs;\0"\
+ "get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \
+ "get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" \
+ "args_ubi=setenv bootargs console=${console} ${optargs} " \
+ "rootfstype=ubifs root=ubi0:rootfs rw ubi.mtd=ospi.rootfs\0"
+
#define EXTRA_ENV_DFUARGS \
"dfu_bufsiz=0x2\0" \
DFU_ALT_INFO_MMC\
@@ -118,6 +135,8 @@
DEFAULT_FIT_TI_ARGS \
EXTRA_ENV_AM65X_BOARD_SETTINGS \
EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \
+ EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \
+ EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \
EXTRA_ENV_RPROC_SETTINGS\
EXTRA_ENV_DFUARGS
--
2.25.0
[PATCH v2 00/12] TI: AM654/J721e: Add support to boot from OSPI
This series adds support to boot from OSPI on TI's AM654 and J721e SoCs. These EVMs have Micron MT35x flash and works in 1-1-8 mode. v2: Update READMEs for OSPI boot Update HS EVM defconfigs to fix build issues Lokesh Vutla (1): ARM: mach-k3: sysfw-loader: Use SPI memmapped addr when loading SYSFW Vignesh Raghavendra (11): drivers: Descend to drivers/soc unconditionally ARM: mach-k3: arm64-mmu: map 64bit FSS MMIO space in A53 MMU ARM: dts: k3-am65: Add OSPI DT nodes ARM: dts: k3-j721e: Add OSPI DT nodes configs: am65x_evm: Setup mtdparts for OSPI configs: j721e_evm: Setup mtdparts for OSPI configs: j721e_evm_defconfig: Enable OSPI configs configs: am65x_evm_defconfig: Enable OSPI configs board: ti: Update AM65x and J721e READMEs for OSPI boot configs: ama65x_hs_evm: Enable OSPI related configs configs: j721e_hs_evm: Enable OSPI related configs arch/arm/dts/k3-am65-mcu.dtsi | 38 + arch/arm/dts/k3-am65.dtsi | 13 - arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 19 +++ arch/arm/dts/k3-am654-base-board.dts | 36 arch/arm/dts/k3-am654-r5-base-board.dts | 39 + .../k3-j721e-common-proc-board-u-boot.dtsi| 16 ++ arch/arm/dts/k3-j721e-common-proc-board.dts | 33 +++ arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 31 +++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 39 + arch/arm/dts/k3-j721e-som-p0.dtsi | 36 arch/arm/dts/k3-j721e.dtsi| 2 + arch/arm/mach-k3/Kconfig | 8 +++ arch/arm/mach-k3/arm64-mmu.c | 7 +++ arch/arm/mach-k3/sysfw-loader.c | 31 ++- board/ti/am65x/README | 55 +++ board/ti/j721e/README | 47 configs/am65x_evm_a53_defconfig | 25 + configs/am65x_evm_r5_defconfig| 17 ++ configs/am65x_hs_evm_a53_defconfig| 26 + configs/am65x_hs_evm_r5_defconfig | 19 +++ configs/j721e_evm_a72_defconfig | 9 ++- configs/j721e_evm_r5_defconfig| 7 +++ configs/j721e_hs_evm_a72_defconfig| 8 ++- configs/j721e_hs_evm_r5_defconfig | 7 +++ drivers/Makefile | 3 +- include/configs/am65x_evm.h | 21 ++- include/configs/j721e_evm.h | 14 - 27 files changed, 597 insertions(+), 9 deletions(-) -- 2.25.0
[PATCH v2 04/12] ARM: dts: k3-am65: Add OSPI DT nodes
Add OSPI DT nodes to enable OSPI at U-Boot prompt and also to support
OSPI boot.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-am65-mcu.dtsi| 38 +++
arch/arm/dts/k3-am65.dtsi| 13 ++-
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 19 ++
arch/arm/dts/k3-am654-base-board.dts | 36 ++
arch/arm/dts/k3-am654-r5-base-board.dts | 39
5 files changed, 143 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
index c42e7553c78f..bc9a87210da9 100644
--- a/arch/arm/dts/k3-am65-mcu.dtsi
+++ b/arch/arm/dts/k3-am65-mcu.dtsi
@@ -64,4 +64,42 @@
loczrama = <1>;
};
};
+
+ fss: fss@4700 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ospi0: spi@4704 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x0 0x4704 0x0 0x100>,
+ <0x5 0x 0x1 0x000>;
+ interrupts = ;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <_clks 248 0>;
+ assigned-clocks = <_clks 248 0>;
+ assigned-clock-parents = <_clks 248 2>;
+ assigned-clock-rates = <1>;
+ power-domains = <_pds 248 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ospi1: spi@4705 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x0 0x4705 0x0 0x100>,
+ <0x7 0x 0x1 0x>;
+ interrupts = ;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <_clks 249 6>;
+ power-domains = <_pds 249 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
index 3ead944640a3..3d89bf32a9d1 100644
--- a/arch/arm/dts/k3-am65.dtsi
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -30,6 +30,8 @@
i2c3 = _i2c1;
i2c4 = _i2c2;
i2c5 = _i2c3;
+ spi0 =
+ spi1 =
};
chosen { };
@@ -79,7 +81,11 @@
<0x00 0x4204 0x00 0x4204 0x00 0x03ac2400>,
<0x00 0x4510 0x00 0x4510 0x00 0x00c24000>,
<0x00 0x4600 0x00 0x4600 0x00 0x0020>,
-<0x00 0x4700 0x00 0x4700 0x00 0x00068400>;
+<0x00 0x4700 0x00 0x4700 0x00 0x00068400>,
+<0x00 0x5000 0x00 0x5000 0x00 0x800>,
+<0x00 0x7000 0x00 0x7000 0x00 0x20>,
+<0x05 0x 0x05 0x 0x01 0x000>,
+<0x07 0x 0x07 0x 0x01 0x000>;
cbass_mcu: interconnect@2838 {
compatible = "simple-bus";
@@ -93,7 +99,10 @@
<0x00 0x4204 0x00 0x4204 0x00
0x03ac2400>, /* WKUP */
<0x00 0x4510 0x00 0x4510 0x00
0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x4600 0x00 0x4600 0x00
0x0020>, /* CPSW */
-<0x00 0x4700 0x00 0x4700 0x00
0x00068400>; /* OSPI space 1 */
+<0x00 0x4700 0x00 0x4700 0x00
0x00068400>, /* OSPI space 1 */
+<0x00 0x5000 0x00 0x5000 0x00
0x800>, /* FSS OSPI0 data region 1 */
+<0x05 0x 0x05 0x 0x01
0x000>, /* FSS OSPI0 data region 3*/
+<0x07 0x 0x07 0x 0x01
0x000>; /* FSS OSPI1 data region 3*/
cbass_wakeup: interconnect@4204 {
compatible = "simple-bus";
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index a349edcfa5fd..2cbe69ed1504 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -43,6 +43,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+
[PATCH v2 02/12] ARM: mach-k3: arm64-mmu: map 64bit FSS MMIO space in A53 MMU
Populate address mapping entries in A53 MMU for 4 GB of MMIO space
reserved for providing MMIO access to multiple flash devices through
OSPI/HBMC IPs within FSS.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/mach-k3/arm64-mmu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 7f908eee803b..b1d1d6e494fc 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -49,6 +49,13 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
.size = 0x8000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x5UL,
+ .phys = 0x5UL,
+ .size = 0x4UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
--
2.25.0
[PATCH v2 03/12] ARM: mach-k3: sysfw-loader: Use SPI memmapped addr when loading SYSFW
From: Lokesh Vutla
Since ROM configures OSPI controller to be in memory mapped mode in OSPI
boot, R5 SPL can directly pass the memory mapped pointer to ROM. With
this ROM can directly pull the SYSFW image from OSPI.
Signed-off-by: Lokesh Vutla
Signed-off-by: Vignesh Raghavendra
---
arch/arm/mach-k3/Kconfig| 8
arch/arm/mach-k3/sysfw-loader.c | 31 ++-
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 2e111bbf27ee..c98a5c66749f 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -126,6 +126,14 @@ config K3_SYSFW_IMAGE_SIZE_MAX
tree blob. Keep it as tight as possible, as this directly affects the
overall SPL memory footprint.
+config K3_SYSFW_IMAGE_SPI_OFFS
+ hex "SPI offset of SYSFW firmware and configuration blob"
+ depends on K3_LOAD_SYSFW
+ default 0x6C
+ help
+ Offset of the combined System Firmware and configuration image tree
+ blob to be loaded when booting from a SPI flash memory.
+
config SYS_K3_SPL_ATF
bool "Start Cortex-A from SPL"
depends on SPL && CPU_V7R
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 94dbeb9437d9..3677a37f55a2 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -14,6 +14,8 @@
#include
#include
#include
+#include
+#include
#include
#include "common.h"
@@ -197,12 +199,32 @@ exit:
}
#endif
+#if CONFIG_IS_ENABLED(SPI_LOAD)
+static void *k3_sysfw_get_spi_addr(void)
+{
+ struct udevice *dev;
+ fdt_addr_t addr;
+ int ret;
+
+ ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS,
+ true, );
+ if (ret)
+ return NULL;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS);
+}
+#endif
+
void k3_sysfw_loader(void (*config_pm_done_callback)(void))
{
struct spl_image_info spl_image = { 0 };
struct spl_boot_device bootdev = { 0 };
struct ti_sci_handle *ti_sci;
- int ret;
+ int ret = 0;
/* Reserve a block of aligned memory for loading the SYSFW image */
sysfw_load_address = memalign(ARCH_DMA_MINALIGN,
@@ -243,6 +265,13 @@ void k3_sysfw_loader(void (*config_pm_done_callback)(void))
#endif
break;
#endif
+#if CONFIG_IS_ENABLED(SPI_LOAD)
+ case BOOT_DEVICE_SPI:
+ sysfw_load_address = k3_sysfw_get_spi_addr();
+ if (!sysfw_load_address)
+ ret = -ENODEV;
+ break;
+#endif
#if CONFIG_IS_ENABLED(YMODEM_SUPPORT)
case BOOT_DEVICE_UART:
#ifdef CONFIG_K3_EARLY_CONS
--
2.25.0
[PATCH v2 01/12] drivers: Descend to drivers/soc unconditionally
Descend to drivers/soc directory unconditionally for SPL and U-Boot builds. Individual drivers can have their own config to check what needs to be built for SPL. There should be no increase in SPL code size due to this change. This is required on K3 SoCs to support DMA in SPL. Signed-off-by: Vignesh Raghavendra Reviewed-by: Tom Rini --- drivers/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/Makefile b/drivers/Makefile index 23501fd74388..420875042896 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -107,7 +107,6 @@ obj-y += reset/ obj-y += input/ # SOC specific infrastructure drivers. obj-y += smem/ -obj-y += soc/ obj-y += thermal/ obj-$(CONFIG_TEE) += tee/ obj-y += axi/ @@ -119,3 +118,5 @@ obj-$(CONFIG_MACH_PIC32) += ddr/microchip/ obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/ obj-$(CONFIG_DM_RNG) += rng/ endif + +obj-y += soc/ -- 2.25.0
Re: [PATCH v2 04/17] tegra: i2c: Change driver to use helper function
Hello Simon, Am 04.02.2020 um 01:19 schrieb Simon Glass: Now that we have uclass_first_device_drvdata(), use it from the I2C driver to reduce code duplication. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch to change tegra driver to use helper function drivers/i2c/tegra_i2c.c | 13 + 1 file changed, 1 insertion(+), 12 deletions(-) Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH 2/2] x86: apl: Include ITSS driver
On Mon, Feb 3, 2020 at 10:23 PM Bin Meng wrote: > > On Mon, Feb 3, 2020 at 9:07 PM Wolfgang Wallner > wrote: > > > > Atuomatically select the ITSS driver when building for Apollo Lake. > > > > Signed-off-by: Wolfgang Wallner > > > > --- > > > > arch/x86/cpu/apollolake/Kconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > Reviewed-by: Bin Meng Squashed into https://gitlab.denx.de/u-boot/custodians/u-boot-x86/commit/1d5bf32f0feaac806f85f128befd619cc81e7e08 for bisectability. Regards, Bin
Re: [PATCH 1/2] x86: itss: Add a Kconfig option to enable/disable ITSS driver
On Tue, Feb 4, 2020 at 10:35 AM Bin Meng wrote: > > Hi Wolfgang, > > On Mon, Feb 3, 2020 at 9:06 PM Wolfgang Wallner > wrote: > > > > Currently the ITSS driver is built unconditionally. Add a Kconfig option > > to support enabling/disabling the inclusion of the ITSS driver depending > > on the platform. > > > > Signed-off-by: Wolfgang Wallner > > --- > > > > arch/x86/Kconfig | 6 ++ > > arch/x86/cpu/intel_common/Makefile | 2 +- > > 2 files changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > > index 89b93e5de2..b733d2264e 100644 > > --- a/arch/x86/Kconfig > > +++ b/arch/x86/Kconfig > > @@ -709,6 +709,12 @@ config ROM_TABLE_SIZE > > hex > > default 0x1 > > > > +config HAVE_ITSS > > + bool "Enable ITSS" > > + help > > + Select this to include the driver for the Interrupt Timer > > + Subsystem (ITSS) which is found on several Intel devices. > > + > > menu "System tables" > > depends on !EFI && !SYS_COREBOOT > > > > diff --git a/arch/x86/cpu/intel_common/Makefile > > b/arch/x86/cpu/intel_common/Makefile > > index 266e6e26fa..e22c70781d 100644 > > --- a/arch/x86/cpu/intel_common/Makefile > > +++ b/arch/x86/cpu/intel_common/Makefile > > @@ -27,7 +27,7 @@ obj-y += microcode.o > > endif > > endif > > obj-y += pch.o > > -obj-y += itss.o > > +obj-$(CONFIG_HAVE_ITSS) += itss.o > > > > I will have to squash this patch into the previous one, because the > unconditional build causes issues for other x86 targets, see: > https://dev.azure.com/bmeng/GitHub/_build/results?buildId=153=logs=8a1d3be7-a4c9-55b6-774d-e7f1a8f80847=b2f224a7-1103-5b52-edbc-3784ae727e03 > Squashed in http://patchwork.ozlabs.org/patch/1232761/, and updated previous patch to conditionally built itss.o. see https://gitlab.denx.de/u-boot/custodians/u-boot-x86/commit/43709fa0888cc80648939ae1588307334e6cc267#ddd927c365d5269dbf9372226e38641da8d7c208_30_30 This way will keep bisectability. applied to u-boot-x86, thanks! Regards, Bin
Re: [PATCH 1/5] x86: fsp: Allow skipping init code when chain loading
Hi Simon,
On Tue, Feb 4, 2020 at 1:15 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Mon, 3 Feb 2020 at 10:10, Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Tue, Feb 4, 2020 at 12:20 AM Simon Glass wrote:
> > >
> > > Hi Bin,
> > >
> > > On Mon, 3 Feb 2020 at 04:05, Bin Meng wrote:
> > > >
> > > > Hi Simon,
> > > >
> > > > On Sun, Dec 22, 2019 at 12:13 AM Simon Glass wrote:
> > > > >
> > > > > When U-Boot is no the first-stage bootloader much of this code is not
> > > > > needed and can break booting. Add checks for this to the FSP code.
> > > > >
> > > > > Rather than checking for the amount of available SDRAM, just use 1GB
> > > > > in
> > > > > this situation, which should be safe. Using 2GB may run into a memory
> > > > > hole on some SoCs.
> > > > >
> > > > > Signed-off-by: Simon Glass
> > > > > ---
> > > > >
> > > > > arch/x86/lib/fsp/fsp_dram.c | 8
> > > > > arch/x86/lib/fsp/fsp_graphics.c | 3 +++
> > > > > arch/x86/lib/fsp2/fsp_dram.c| 10 ++
> > > > > arch/x86/lib/fsp2/fsp_init.c| 2 +-
> > > > > 4 files changed, 22 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
> > > > > index 9ce0ddf0d3..15e82de2fe 100644
> > > > > --- a/arch/x86/lib/fsp/fsp_dram.c
> > > > > +++ b/arch/x86/lib/fsp/fsp_dram.c
> > > > > @@ -44,6 +44,14 @@ int dram_init_banksize(void)
> > > > > phys_addr_t low_end;
> > > > > uint bank;
> > > > >
> > > > > + if (!ll_boot_init()) {
> > > > > + gd->bd->bi_dram[0].start = 0;
> > > > > + gd->bd->bi_dram[0].size = gd->ram_size;
> > > > > +
> > > > > + mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
> > > > > + return 0;
> > > > > + }
> > > > > +
> > > >
> > > > I wonder why this change is needed. When booting from other
> > > > bootloader, this dram_init_banksize() will not be called, no?
> > >
> > > How about this:
> > >
> > > It is useful to be able to boot the same x86 image on a device with or
> > > without a first-stage bootloader. For example, with chromebook_coral, it
> > > is helpful for testing to be able to boot the same U-Boot (complete with
> > > FSP) on bare metal and from coreboot. It allows checking of things like
> > > CPU speed, comparing registers, ACPI tables and the like.
> > >
> > > The idea is to change ll_boot_init() to false, and rebuild without
> > > changing
> > > anything else.
> >
> > This sounds like for a debugging purpose, instead of a supported
> > configuration. So when we boot from previous bootloader, we really
> > should use its configuration, for the coreboot case,
> > coreboot-x86_defconfig should be used, and we can compare the
> > registers, ACPI tables in that configuration, instead of "hacking"
> > current U-Boot codes like in this series.
>
> Well the problem is then that we cannot boot the same image with or
> without coreboot. Also there are various of device-tree things in
> coral that we need for the laptop to work properly. My idea is to
> detect coreboot and set ll_boot_init() dynamically if needed.
If so, why should we keep coreboot_defconfig for U-Boot as a supported target?
I am more interested in what you proposed here: "detect coreboot and
set ll_boot_init() dynamically if needed." The name ll_boot_init()
does not sound great. It's written like a function call but actually
it is a macro for true/false. Can we do something in the gd->flags to
indicate we are booting from previous stage bootloaders instead of
relying on ll_boot_init()?
Regards,
Bin
Re: [PATCH] board: stih410-b2260: remove fdt_high and initrd_high
On Mon, Feb 03, 2020 at 03:00:59PM +0100, Patrice Chotard wrote: > Remove fdt_high and initrd_high as they shouldn't be used, > this allows the fdt and initrd relocation. > This implies to set CONFIG_SYS_BOOTMAPSZ to indicate the > amount of memory available to contain kernel, device tree > and initrd for relocation. > > Signed-off-by: Patrice Chotard Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-socfpga/master
On Mon, Feb 03, 2020 at 09:47:04AM +0100, Marek Vasut wrote: > On 2/3/20 9:24 AM, Marek Vasut wrote: > > On 2/2/20 9:26 PM, Tom Rini wrote: > >> On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote: > >> > >>> The following changes since commit > >>> 80e99adbe47d1c8590f9b971ac52257fdc51a5ec: > >>> > >>> Merge tag 'uniphier-v2020.04-2' of > >>> https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31 > >>> 13:26:28 -0500) > >>> > >>> are available in the Git repository at: > >>> > >>> git://git.denx.de/u-boot-socfpga.git master > >>> > >>> for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa: > >>> > >>> ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100) > >>> > >> > >> A see a ton of failures: > >>aarch64: + socfpga_agilex > > OK, this one I see, let's add this patch > > diff --git a/include/configs/socfpga_soc64_common.h > b/include/configs/socfpga_soc64_common.h > index da81137e84..87c73457a0 100644 > --- a/include/configs/socfpga_soc64_common.h > +++ b/include/configs/socfpga_soc64_common.h > @@ -150,10 +150,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > /* > * L4 Watchdog > */ > -#ifdef CONFIG_SPL_BUILD > -#undef CONFIG_WATCHDOG > -#define CONFIG_HW_WATCHDOG > -#else > +#ifndef CONFIG_SPL_BUILD > #undef CONFIG_HW_WATCHDOG > #undef CONFIG_DESIGNWARE_WATCHDOG > #endif To be clear, I'm expecting a new PR, thanks. -- Tom signature.asc Description: PGP signature
Re: [PATCH] ls1043a: Remove "fdt_high" environment variable
On Mon, Feb 03, 2020 at 05:32:27PM +0800, Wen He wrote: > Remove "fdt_high" environment variable to use the bootm_size(or set > CONFIG_SYS_BOOTMAPSZ) to amount of memory available to safely contain > a kernel, device tree and initrd for relocation. > > Signed-off-by: Wen He > --- > include/configs/ls1043a_common.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/include/configs/ls1043a_common.h > b/include/configs/ls1043a_common.h > index 1670476..751117b 100644 > --- a/include/configs/ls1043a_common.h > +++ b/include/configs/ls1043a_common.h > @@ -234,7 +234,6 @@ > /* Initial environment variables */ > #define CONFIG_EXTRA_ENV_SETTINGS\ > "hwconfig=fsl_ddr:bank_intlv=auto\0"\ > - "fdt_high=0x\0" \ > "initrd_high=0x\0" \ > "fdt_addr=0x64f0\0" \ > "kernel_addr=0x6100\0" \ I don't see either bootm_size in context here nor CONFIG_SYS_BOOTMAPSZ, does this depend on some other patch? Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] ls1021a: Set CONFIG_SYS_BOOTMAPSZ to the memory for relocation
On Mon, Feb 03, 2020 at 03:25:19PM +0800, Alison Wang wrote: > This patch sets CONFIG_SYS_BOOTMAPSZ to the amount of memory available > to safely contain a kernel, device tree and initrd for relocation. The > way to set fdt_high as 0x to disable device tree relocation is > removed. > > Signed-off-by: Alison Wang Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH 0/7] J721e: Add support for DFU boot mode
On 27/01/20 5:59 PM, Vignesh Raghavendra wrote: > This series adds support to boot via USB DFU mode. Series pulled into u-boot-ti tree. Thanks and regards, Lokesh
Re: [PATCH 1/3] watchdog: omap_wdt: Fix WDT timeout configuration
On 24/01/20 10:14 AM, Marek Vasut wrote: > The timeout parameter of omap3_wdt_start() is in miliseconds, while > GET_WLDR_VAL() expects parameter in seconds. Fix this so the WDT > driver is actually usable. > > Signed-off-by: Marek Vasut > Cc: Grygorii Strashko > Cc: Sam Protsenko > Cc: Suniel Mahesh Series pulled into u-boot-ti tree. Thanks and regards, Lokesh
Re: [PATCH] gpio: pca953x_gpio: Add support for 24 bit IO expander
On 27/01/20 11:19 PM, Vignesh Raghavendra wrote: > J721e EVM has a TCA6424 IO expander that has 24 GPIOs. Add support for > the same > > Signed-off-by: Vignesh Raghavendra pulled into u-boot-ti tree. Thanks and regards, Lokesh
Re: [PATCH 0/4] J721e: Add I2C nodes
On 27/01/20 11:22 PM, Vignesh Raghavendra wrote: > Add I2C and I2C IO expander nodes Series pulled into u-boot-ti tree. Thanks and regards, Lokesh
Re: [PATCH v4 00/10] am57xx: Implement Android 10 boot flow
On 24/01/20 9:23 PM, Sam Protsenko wrote: > Android 10 brings a lot of new requirements for bootloaders: [1]. This > patch series attempts to implement such a boot process on BeagleBoard > X15 platform. Some common code is added too, which can be reused later > for other platforms (see "abootimg" command and associated C API). > > Changes in v4: > - fixed broken build due to recent load_addr -> image_load_addr >renaming > - added "doc: android: Convert to Sphinx format" patch to series > - addressed pending comments for v3 on mailing list > - rebased series on top of current master > > Changes in v3: > - rename command to "abootimg" (requested by Simon Glass) > - rework command interface (as discussed with Eugeniu) > - add command documentation > - address other comments > > [1] https://source.android.com/devices/bootloader Series pulled into u-boot-ti tree. Thanks and regards, Lokesh
[GIT PULL] TI changes for v2020.04-rc2
Hi Tom,
Please find the pull request for v2020.04-rc2 containing TI specific changes.
This PR is a re spin of previous PR[0] without mmc changes and fetched
few dt changes and watchdog fixes.
[0] https://patchwork.ozlabs.org/patch/1230709/
Travis-CI build: https://travis-ci.org/lokeshvutla/u-boot/builds/645566110
Thanks and regards,
Lokesh
The following changes since commit 31a790bee939e227dfc7e6a6a323b2b13180707f:
Merge branch 'master' of git://git.denx.de/u-boot-usb (2020-02-02 15:26:53
-0500)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git tags/ti-v2020.04-rc2
for you to fetch changes up to 4dd05933989f01bb38813f4a5f043b7dfa24e218:
watchdog: omap_wdt: Fix WDT coding style (2020-02-04 09:07:25 +0530)
Below are the major changes in this PR:
- DFU boot support for J721e
- I2C support for J721e
- GPIO support for J721e
- Android boot image updates on AM57XX
- OMAP watchdog fixes
Faiz Abbas (3):
configs: j721e_evm_a72: Fix redundant environment offset
arm: dts: k3-j721e-main: Add Support for gpio0
configs: j721e_evm_a72: Add GPIO support
Marek Vasut (3):
watchdog: omap_wdt: Fix WDT timeout configuration
watchdog: omap_wdt: Fix WDT reloading
watchdog: omap_wdt: Fix WDT coding style
Sam Protsenko (10):
image: android: Add functions for handling dtb field
image: android: Add routine to get dtbo params
cmd: abootimg: Add abootimg command
doc: android: Add documentation for Android Boot Image
doc: android: Convert to Sphinx format
test/py: android: Add test for abootimg
configs: am57xx_evm: Enable Android commands
env: ti: boot: Respect slot_suffix in AVB commands
env: ti: boot: Boot Android with dynamic partitions
arm: ti: boot: Use correct dtb and dtbo on Android boot
Vignesh Raghavendra (14):
arm: mach-k3: j721e: Rename BOOT_DEVICE_USB to BOOT_DEVICE_DFU
arm: mach-k3: sysfw-loader: Add support to download SYSFW via DFU
arm: dts: k3-j721e-common-proc-board: Enable USB0 in peripheral mode
configs: j721e_evm: Add DFU related variables
configs: j721e_evm_r5_defconfig: Increase early malloc size
configs: j721e_evm_r5/a72_defconfig: Enable USB Gadget related configs
configs: j721e_evm_r5/a72_defconfig: Enable DFU related configs
gpio: pca953x_gpio: Add support for 24 bit IO expander
arm: dts: k3-j721e: Add I2C nodes
arm: dts: k3-j721e-common-proc-board: Add I2C GPIO expander
arm: dts: k3-j721e-common-proc-board: Enable I2C expander for SPL
configs: j721e_evm_defconfig: Enable PCA953x IO expander
gpio: da8xx_gpio: Fix compiler warning
gpio: da8xx_gpio: Add "ti,keystone-gpio" compatible
MAINTAINERS| 4 +-
.../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 12 +
arch/arm/dts/k3-j721e-common-proc-board.dts| 27 ++
arch/arm/dts/k3-j721e-main.dtsi| 99
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 22 ++
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 45
arch/arm/dts/k3-j721e.dtsi | 10 +
arch/arm/mach-k3/include/mach/j721e_spl.h | 2 +-
arch/arm/mach-k3/sysfw-loader.c| 30 +++
cmd/Kconfig| 12 +-
cmd/Makefile | 1 +
cmd/abootimg.c | 258 +++
common/Makefile| 2 +-
common/image-android.c | 282 +
configs/am57xx_evm_defconfig | 6 +
configs/am57xx_hs_evm_defconfig| 6 +
configs/am57xx_hs_evm_usb_defconfig| 6 +
configs/j721e_evm_a72_defconfig| 13 +-
configs/j721e_evm_r5_defconfig | 18 +-
configs/sandbox_defconfig | 1 +
doc/android/{ab.txt => ab.rst} | 39 +--
doc/android/avb2.rst | 133 ++
doc/android/avb2.txt | 115 -
doc/android/bcb.rst| 100
doc/android/bcb.txt| 89 ---
doc/android/boot-image.rst | 154 +++
...fastboot-protocol.txt => fastboot-protocol.rst} | 45 ++--
doc/android/{fastboot.txt => fastboot.rst} | 92 +++
doc/android/index.rst | 14 +
doc/index.rst | 12 +
drivers/gpio/da8xx_gpio.c | 3 +-
drivers/gpio/pca953x_gpio.c| 11 +-
drivers/watchdog/omap_wdt.c| 56 ++--
Re: [PATCH 0/9] TI: AM654/J721e: Add support to boot from OSPI
On 29/01/20 5:48 PM, Vignesh Raghavendra wrote: > This series adds support to boot from OSPI on TI's AM654 and J721e SoCs. > These EVMs have Micron MT35x flash and works in 1-1-8 mode. This is causing build failures on hs configs. Can you fix it and repost? Thanks and regards, Lokesh > > Lokesh Vutla (1): > ARM: mach-k3: sysfw-loader: Use SPI memmapped addr when loading SYSFW > > Vignesh Raghavendra (8): > drivers: Descend to drivers/soc unconditionally > ARM: mach-k3: arm64-mmu: map 64bit FSS MMIO space in A53 MMU > ARM: dts: k3-am65: Add OSPI DT nodes > ARM: dts: k3-j721e: Add OSPI DT nodes > configs: am65x_evm: Setup mtdparts for OSPI > configs: j721e_evm: Setup mtdparts for OSPI > configs: j721e_evm_defconfig: Enable OSPI configs > configs: am65x_evm_defconfig: Enable OSPI configs > > arch/arm/dts/k3-am65-mcu.dtsi | 38 ++ > arch/arm/dts/k3-am65.dtsi | 13 ++- > arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 19 + > arch/arm/dts/k3-am654-base-board.dts | 36 + > arch/arm/dts/k3-am654-r5-base-board.dts | 39 +++ > .../k3-j721e-common-proc-board-u-boot.dtsi| 16 > arch/arm/dts/k3-j721e-common-proc-board.dts | 33 > arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 31 +++ > .../arm/dts/k3-j721e-r5-common-proc-board.dts | 39 +++ > arch/arm/dts/k3-j721e-som-p0.dtsi | 36 + > arch/arm/dts/k3-j721e.dtsi| 2 + > arch/arm/mach-k3/Kconfig | 8 > arch/arm/mach-k3/arm64-mmu.c | 7 > arch/arm/mach-k3/sysfw-loader.c | 31 ++- > configs/am65x_evm_a53_defconfig | 25 > configs/am65x_evm_r5_defconfig| 17 > configs/j721e_evm_a72_defconfig | 9 - > configs/j721e_evm_r5_defconfig| 7 > drivers/Makefile | 3 +- > include/configs/am65x_evm.h | 21 +- > include/configs/j721e_evm.h | 14 ++- > 21 files changed, 436 insertions(+), 8 deletions(-) >
Re: [PATCH 0/2] x86: serial: Use NS16550_DYNAMIC in Slim Bootloader
Hi Bin, > On Feb 3, 2020, at 7:03 PM, Bin Meng wrote: > > Hi Aiden, > >> On Wed, Dec 18, 2019 at 1:56 PM Park, Aiden wrote: >> >> Slim Bootloader provides serial port info in its HOB to support >> both IO or MMIO serial ports, but it's controlled by SYS_NS16550_MEM32 >> or SYS_NS16550_PORT_MAPPED in U-Boot. >> To support both serial port configurations dynamically at runtime, >> Slim Bootloader serial driver leverages NS16550_DYNAMIC. >> >> Aiden Park (2): >> x86: serial: Use NS16550_DYNAMIC in Slim Bootloader driver >> doc: intel: Update serial driver changes in slimbootloader.rst >> >> arch/x86/cpu/slimbootloader/serial.c | 5 >> doc/board/intel/slimbootloader.rst | 35 +++- >> include/configs/slimbootloader.h | 13 --- >> 3 files changed, 13 insertions(+), 40 deletions(-) > > One issue that needs your attention. > > It seems you have configured git email to send from different name > other than that in your SoB tag: > > See the following git log: > commit a6302b7085ce12cb967234e19f2ac2c2320528f1 > Author: Park, Aiden > Date: Wed Dec 18 05:56:29 2019 + > >doc: intel: Update serial driver changes in slimbootloader.rst > >Now, Slim Bootloader uses NS16550_DYNAMIC to support serial port >configuration at runtime, so no more code change is required. >Therefore, remove unnecessary steps and fix minor typo. > >Signed-off-by: Aiden Park > > checkpatch complains that: > WARNING: Missing Signed-off-by: line by nominal patch author 'Park, > Aiden ' > > Could you please fix your GIT settings so that both are "Aiden Park > "? > Thanks for giving me heads-up. Let me double check my configuration for further commits. Thanks again. > Regards, > Bin Best Regards, Aiden
Re: [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
Hi Jerome,
Thanks for your review comments,
On Mon, 3 Feb 2020 at 23:14, Jerome Brunet wrote:
>
>
> On Mon 03 Feb 2020 at 17:38, Anand Moon wrote:
>
> > Hi Jerome,
> >
> > Thanks for your review,
> >
> > On Mon, 3 Feb 2020 at 21:11, Jerome Brunet wrote:
> >>
> >>
> >> On Mon 03 Feb 2020 at 16:13, Anand Moon wrote:
> >>
> >> > As per mainline line kernel fix the clk tuning phase for mmc,
> >> > set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
>
> Which version ?
> I don't recall any version of mainline linux kernel which has used these
> default settings.
Ok typo, I was just referring the datasheet for the default values,
>
> >> > As per S905, S905X, AGX and S922X datasheet set the default
> >> > values for clk tuning.
> >> >
> >> > Signed-off-by: Anand Moon
> >> > ---
> >> > arch/arm/include/asm/arch-meson/sd_emmc.h | 28 --
> >> > drivers/mmc/meson_gx_mmc.c| 36 +++
> >> > 2 files changed, 50 insertions(+), 14 deletions(-)
> >> >
> >> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > index e3a72c8b66..b7a99947b3 100644
> >> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > @@ -7,6 +7,7 @@
> >> > #define __SD_EMMC_H__
> >> >
> >> > #include
> >> > +#include
> >> >
> >> > #define SDIO_PORT_A 0
> >> > #define SDIO_PORT_B 1
> >> > @@ -19,15 +20,24 @@
> >> > #define CLK_MAX_DIV63
> >> > #define CLK_SRC_24M(0 << 6)
> >> > #define CLK_SRC_DIV2 (1 << 6)
> >> > -#define CLK_CO_PHASE_000 (0 << 8)
> >> > -#define CLK_CO_PHASE_090 (1 << 8)
> >> > -#define CLK_CO_PHASE_180 (2 << 8)
> >> > -#define CLK_CO_PHASE_270 (3 << 8)
> >> > -#define CLK_TX_PHASE_000 (0 << 10)
> >> > -#define CLK_TX_PHASE_090 (1 << 10)
> >> > -#define CLK_TX_PHASE_180 (2 << 10)
> >> > -#define CLK_TX_PHASE_270 (3 << 10)
> >> > -#define CLK_ALWAYS_ON BIT(24)
> >> > +
> >> > +#define CRYSTAL_24MHZ 0
> >> > +#define CLK_PHASE_00
> >> > +#define CLK_PHASE_180 2
> >> > +
> >> > +#define CLK_DIV_MASK GENMASK(5, 0)
> >> > +#define CLK_SRC_MASK GENMASK(7, 6)
> >> > +#define CLK_CORE_PHASE_MASKGENMASK(9, 8)
> >> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> >> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> >> > +
> >> > +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
> >> > +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
> >> > +#define CLK_V2_ALWAYS_ON BIT(24)
> >> > +
> >> > +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
> >> > +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
> >> > +#define CLK_V3_ALWAYS_ON BIT(28)
> >> >
> >> > #define MESON_SD_EMMC_CFG0x44
> >> > #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
> >> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >> > index 86c1a7164a..03fb70e717 100644
> >> > --- a/drivers/mmc/meson_gx_mmc.c
> >> > +++ b/drivers/mmc/meson_gx_mmc.c
> >> > @@ -16,6 +16,10 @@
> >> > #include
> >> > #include
> >> >
> >> > +#include
> >> > +#include
> >> > +#include
> >> > +
> >> > static inline void *get_regbase(const struct mmc *mmc)
> >> > {
> >> > struct meson_mmc_platdata *pdata = mmc->priv;
> >> > @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >> > }
> >> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >> >
> >> > - /* 180 phase core clock */
> >> > - meson_mmc_clk |= CLK_CO_PHASE_180;
> >> > -
> >> > - /* 180 phase tx clock */
> >> > - meson_mmc_clk |= CLK_TX_PHASE_000;
> >> > + /* Clock divider */
> >> > + meson_mmc_clk |= CLK_DIV_MASK;
> >> > + /* Clock source : Crystal 24MHz */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >> > + /* Core clock phase 2:180 */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> >> > + /* TX clock phase 2:180 */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
> >>
> >> I think I mentionned already but this is not aligned with the setting
> >> used by the linux driver. If you have problems with these, please report
> >> it to the linux mailing list
> >
> > Yes I will try to send this changes to linux driver since these are
> > the recommend
> > default values as per the datasheets, see below.
> > Cfg_tx_phase: TX clock phase 0: 0 phase, 1: 90 phase, 2: 180 phase, 3:
> > 270 phase. Recommended value: 2
>
> Well we already had that discussion 2 years ago regarding the
> recommended setting. The fact is that
Re: [PATCH 0/2] x86: serial: Use NS16550_DYNAMIC in Slim Bootloader
Hi Aiden, On Wed, Dec 18, 2019 at 1:56 PM Park, Aiden wrote: > > Slim Bootloader provides serial port info in its HOB to support > both IO or MMIO serial ports, but it's controlled by SYS_NS16550_MEM32 > or SYS_NS16550_PORT_MAPPED in U-Boot. > To support both serial port configurations dynamically at runtime, > Slim Bootloader serial driver leverages NS16550_DYNAMIC. > > Aiden Park (2): > x86: serial: Use NS16550_DYNAMIC in Slim Bootloader driver > doc: intel: Update serial driver changes in slimbootloader.rst > > arch/x86/cpu/slimbootloader/serial.c | 5 > doc/board/intel/slimbootloader.rst | 35 +++- > include/configs/slimbootloader.h | 13 --- > 3 files changed, 13 insertions(+), 40 deletions(-) One issue that needs your attention. It seems you have configured git email to send from different name other than that in your SoB tag: See the following git log: commit a6302b7085ce12cb967234e19f2ac2c2320528f1 Author: Park, Aiden Date: Wed Dec 18 05:56:29 2019 + doc: intel: Update serial driver changes in slimbootloader.rst Now, Slim Bootloader uses NS16550_DYNAMIC to support serial port configuration at runtime, so no more code change is required. Therefore, remove unnecessary steps and fix minor typo. Signed-off-by: Aiden Park checkpatch complains that: WARNING: Missing Signed-off-by: line by nominal patch author 'Park, Aiden ' Could you please fix your GIT settings so that both are "Aiden Park "? Regards, Bin
Re: [PATCH v2 3/3] gpio: intel_gpio: Fix register/bit offsets intel_gpio_get_value()
Hi Andy,
On Mon, Feb 3, 2020 at 8:34 PM Andy Shevchenko
wrote:
>
> On Mon, Feb 3, 2020 at 12:38 PM Wolfgang Wallner
> wrote:
> >
> > Fix the following in intel_gpio_get_value():
> >
> > * The value of the register is contained in the variable 'reg', not in
> >'mode'. The variable 'mode' contains only the configuration whether
> >the gpio is currently an input or an output.
> >
> > * The correct bitmasks for the input and output value are
> >PAD_CFG0_RX_STATE and PAD_CFG0_TX_STATE.
> >Use them instead of the currently used PAD_CFG0_RX_STATE_BIT and
> >PAD_CFG0_TX_STATE_BIT.
>
> ...
>
> > if (!mode) {
> > rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
> > if (rx_tx == PAD_CFG0_TX_DISABLE)
> > - return mode & PAD_CFG0_RX_STATE_BIT ? 1 : 0;
> > + return reg & PAD_CFG0_RX_STATE ? 1 : 0;
>
> Is it style of U-Boot? Because
> return !!(...); will have same effect while consuming less characters.
checkpatch does not complain, so I assume it is okay for U-Boot.
>
> > else if (rx_tx == PAD_CFG0_RX_DISABLE)
>
> 'else' is redundant here
>
> > - return mode & PAD_CFG0_TX_STATE_BIT ? 1 : 0;
> > + return reg & PAD_CFG0_TX_STATE ? 1 : 0;
> > }
>
>
> --
Regards,
Bin
Re: [PATCH v2 3/3] gpio: intel_gpio: Fix register/bit offsets intel_gpio_get_value()
On Mon, Feb 3, 2020 at 6:38 PM Wolfgang Wallner wrote: > > Fix the following in intel_gpio_get_value(): > > * The value of the register is contained in the variable 'reg', not in >'mode'. The variable 'mode' contains only the configuration whether >the gpio is currently an input or an output. > > * The correct bitmasks for the input and output value are >PAD_CFG0_RX_STATE and PAD_CFG0_TX_STATE. >Use them instead of the currently used PAD_CFG0_RX_STATE_BIT and >PAD_CFG0_TX_STATE_BIT. > > Signed-off-by: Wolfgang Wallner > Reviewed-by: Simon Glass > Reviewed-by: Bin Meng > > --- > > Changes in v2: None > > drivers/gpio/intel_gpio.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > applied to u-boot-x86, thanks!
Re: [PATCH v2 2/3] gpio: intel_gpio: Clear tx state bit when setting output
On Mon, Feb 3, 2020 at 6:38 PM Wolfgang Wallner wrote: > > Add missing 'PAD_CFG0_TX_STATE' to the clear mask for pcr_clrsetbits32(). > Otherwise this bit cannot be cleared again after it has been set once. > > Signed-off-by: Wolfgang Wallner > Reviewed-by: Simon Glass > Reviewed-by: Bin Meng > > --- > > Changes in v2: > - Added reviewed-by tags > > drivers/gpio/intel_gpio.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > applied to u-boot-x86, thanks!
Re: [PATCH v2 1/3] gpio: intel_gpio: Pass pinctrl device to pcr_clrsetbits32()
On Mon, Feb 3, 2020 at 6:48 PM Bin Meng wrote: > > On Mon, Feb 3, 2020 at 6:38 PM Wolfgang Wallner > wrote: > > > > The function pcr_clrsetbits32() expects a device with a P2SB parent > > device. In intel_gpio_direction_output() and intel_gpio_set_value() > > the device 'dev' is passed to pcr_clrsetbits32(), which is a > > gpio-controller with a device 'pinctrl' as parent. This does not match > > the expectations of pcr_clrsetbits32(). But the 'pinctrl' device has a > > P2SB as parent. > > > > Pass the 'pinctrl' device instead of the 'dev' device to > > pcr_clrsetbits32(). > > > > Signed-off-by: Wolfgang Wallner > > > > --- > > > > Changes in v2: > > - Fixed typo in the commit description > > - Fixed the same error in both intel_gpio_direction_output() and > > intel_gpio_set_value() (Thanks to Bin Meng for catching this) > > - Reworded commit description > > > > drivers/gpio/intel_gpio.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > Reviewed-by: Bin Meng applied to u-boot-x86, thanks!
Re: [PATCH] azure: Move to vs2017-win2016 platform build host
On Mon, Feb 3, 2020 at 10:20 PM Bin Meng wrote: > > On Mon, Feb 3, 2020 at 8:25 PM Tom Rini wrote: > > > > Azure is moving to remove the vs2015-win2012r2 platform build host. The > > two suggested new platforms to use are vs2017-win2016 and windows-2019. > > For now, move up to vs2017-win2016. > > > > Cc: Bin Meng > > Signed-off-by: Tom Rini > > --- > > Changes in v1: > > - Sending this as non-RFC as Bin pointed out the backend issue has been > > resolved and I can confirm that as well. > > --- > > .azure-pipelines.yml | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > Reviewed-by: Bin Meng > Tested-by: Bin Meng applied to u-boot-x86, thanks!
Re: [PATCH 1/2] x86: itss: Add a Kconfig option to enable/disable ITSS driver
Hi Wolfgang, On Mon, Feb 3, 2020 at 9:06 PM Wolfgang Wallner wrote: > > Currently the ITSS driver is built unconditionally. Add a Kconfig option > to support enabling/disabling the inclusion of the ITSS driver depending > on the platform. > > Signed-off-by: Wolfgang Wallner > --- > > arch/x86/Kconfig | 6 ++ > arch/x86/cpu/intel_common/Makefile | 2 +- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index 89b93e5de2..b733d2264e 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -709,6 +709,12 @@ config ROM_TABLE_SIZE > hex > default 0x1 > > +config HAVE_ITSS > + bool "Enable ITSS" > + help > + Select this to include the driver for the Interrupt Timer > + Subsystem (ITSS) which is found on several Intel devices. > + > menu "System tables" > depends on !EFI && !SYS_COREBOOT > > diff --git a/arch/x86/cpu/intel_common/Makefile > b/arch/x86/cpu/intel_common/Makefile > index 266e6e26fa..e22c70781d 100644 > --- a/arch/x86/cpu/intel_common/Makefile > +++ b/arch/x86/cpu/intel_common/Makefile > @@ -27,7 +27,7 @@ obj-y += microcode.o > endif > endif > obj-y += pch.o > -obj-y += itss.o > +obj-$(CONFIG_HAVE_ITSS) += itss.o > I will have to squash this patch into the previous one, because the unconditional build causes issues for other x86 targets, see: https://dev.azure.com/bmeng/GitHub/_build/results?buildId=153=logs=8a1d3be7-a4c9-55b6-774d-e7f1a8f80847=b2f224a7-1103-5b52-edbc-3784ae727e03 Regards, Bin
Re: [PATCH v2 08/13] dm: irq: Add support for requesting interrupts
Hi Simon,
On Tue, Feb 4, 2020 at 8:19 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Mon, 3 Feb 2020 at 10:05, Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Sun, Dec 22, 2019 at 2:16 AM Simon Glass wrote:
> > >
> > > At present driver model supports the IRQ uclass but there is no way to
> > > request a particular interrupt for a driver.
> > >
> > > Add a mechanism, similar to clock and reset, to read the interrupts
> > > required by a device from the device tree and to request those interrupts.
> > >
> > > U-Boot itself does not have interrupt-driven handlers, so just provide a
> > > means to read and clear an interrupt. This can be useful to handle
> > > peripherals which must use an interrupt to determine when data is
> > > available, for example.
> > >
> > > Bring over the basic binding file as well, from Linux v5.4. Note that the
> > > older binding is not supported in U-Boot; the newer 'special form' must be
> > > used.
> > >
> > > Add a simple test of the new functionality.
> > >
> > > Signed-off-by: Simon Glass
> > > ---
> > >
> > > Changes in v2: None
> > >
> > > arch/sandbox/dts/test.dts | 5 +-
> > > .../interrupt-controller/interrupts.txt | 131 ++
> > > drivers/misc/irq-uclass.c | 116
> > > drivers/misc/irq_sandbox.c| 41 ++
> > > include/irq.h | 115 +++
> > > test/dm/irq.c | 31 +
> > > 6 files changed, 438 insertions(+), 1 deletion(-)
> > > create mode 100644
> > > doc/device-tree-bindings/interrupt-controller/interrupts.txt
> > >
>
> [..]
> > > diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
> > > index 38498a66a4..7d65192858 100644
> > > --- a/drivers/misc/irq-uclass.c
> > > +++ b/drivers/misc/irq-uclass.c
> > > @@ -4,8 +4,11 @@
> > > * Written by Simon Glass
> > > */
> > >
> > > +#define LOG_CATEGORY UCLASS_IRQ
> > > +
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > >
> > > @@ -49,6 +52,119 @@ int irq_restore_polarities(struct udevice *dev)
> > > return ops->restore_polarities(dev);
> > > }
> > >
> > > +int irq_read_and_clear(struct irq *irq)
> > > +{
> > > + const struct irq_ops *ops = irq_get_ops(irq->dev);
> > > +
> > > + if (!ops->read_and_clear)
> > > + return -ENOSYS;
> > > +
> > > + return ops->read_and_clear(irq);
> > > +}
> > > +
> > > +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> > > +int irq_get_by_index_platdata(struct udevice *dev, int index,
> > > + struct phandle_1_arg *cells, struct irq
> > > *irq)
> > > +{
> > > + int ret;
> > > +
> > > + if (index != 0)
> > > + return -ENOSYS;
> > > + ret = uclass_get_device(UCLASS_IRQ, 0, >dev);
> > > + if (ret)
> > > + return ret;
> > > + irq->id = cells[0].arg[0];
> > > +
> > > + return 0;
> > > +}
> > > +#else
> > > +static int irq_of_xlate_default(struct irq *irq,
> > > + struct ofnode_phandle_args *args)
> > > +{
> > > + log_debug("(irq=%p)\n", irq);
> > > +
> > > + if (args->args_count > 1) {
> > > + log_debug("Invaild args_count: %d\n", args->args_count);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + if (args->args_count)
> > > + irq->id = args->args[0];
> > > + else
> > > + irq->id = 0;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int irq_get_by_index_tail(int ret, ofnode node,
> >
> > It's odd to pass the return value of some other functions to this
> > function and check it here. Can we please remove ret, and check its
> > value at where we get that?
>
> This pattern is similar to how it is done in DM core. It routes all
> return paths through a single function where you can do error
> checking, etc. So I think this is better than the alternative. The
> only strange thing here is that this function is only used one. I did
> this since I suspected there would be others coming. But I could
> inline if it you like..
If that's the way how other DM codes do, I am okay with that.
>
> [..]
>
> > > +static int sandbox_irq_of_xlate(struct irq *irq,
> > > + struct ofnode_phandle_args *args)
> > > +{
> > > + irq->id = args->args[0];
> > > +
> > > + return 0;
> > > +}
> >
> > This
>
> ...?
I must have been working too long yesterday ...
Regards,
Bin
[PATCH v2 16/17] tpm: Add a driver for H1/Cr50
H1 is a Google security chip present in recent Chromebooks, Pixel phones
and other devices. Cr50 is the name of the software that runs on H1 in
Chromebooks.
This chip is used to handle TPM-like functionality and also has quite a
few additional features.
Add a driver for this.
Signed-off-by: Simon Glass
---
Changes in v2:
- Significant rewrite of cr50 init procedure
- Support use of interrupts
drivers/tpm/Kconfig| 10 +
drivers/tpm/Makefile | 1 +
drivers/tpm/cr50_i2c.c | 661 +
3 files changed, 672 insertions(+)
create mode 100644 drivers/tpm/cr50_i2c.c
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index 94629dffd2..00d7dc8e48 100644
--- a/drivers/tpm/Kconfig
+++ b/drivers/tpm/Kconfig
@@ -127,6 +127,16 @@ config TPM_V2
if TPM_V2
+config TPM2_CR50_I2C
+ bool "Enable support for Google cr50 TPM"
+ depends on DM_I2C
+ help
+ Cr50 is an implementation of a TPM on Google's H1 security chip.
+ This uses the same open-source firmware as the Chromium OS EC.
+ While Cr50 has other features, its primary role is as the root of
+ trust for a devuce, It operates like a TPM and can be used with
+ verified boot. Cr50 is used on recent Chromebooks (since 2017).
+
config TPM2_TIS_SANDBOX
bool "Enable sandbox TPMv2.x driver"
depends on TPM_V2 && SANDBOX
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index 94c337b8ed..4c866b37c5 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o
obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o
obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o
+obj-$(CONFIG_TPM2_CR50_I2C) += cr50_i2c.o
obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o
obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_spi.o
diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
new file mode 100644
index 00..ec40e8f735
--- /dev/null
+++ b/drivers/tpm/cr50_i2c.c
@@ -0,0 +1,661 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cr50 / H1 TPM support
+ *
+ * Copyright 2018 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_TPM
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum {
+ TIMEOUT_INIT_MS = 3, /* Very long timeout for TPM init */
+ TIMEOUT_LONG_US = 2 * 1000 * 1000,
+ TIMEOUT_SHORT_US= 2 * 1000,
+ TIMEOUT_NO_IRQ_US = 20 * 1000,
+ TIMEOUT_IRQ_US = 100 * 1000,
+};
+
+enum {
+ CR50_DID_VID = 0x00281ae0L
+};
+
+enum {
+ CR50_MAX_BUF_SIZE = 63,
+};
+
+struct cr50_priv {
+ struct gpio_desc ready_gpio;
+ struct irq irq;
+ int locality;
+ uint vendor;
+ bool use_irq;
+};
+
+/* Wait for interrupt to indicate TPM is ready */
+static int cr50_i2c_wait_tpm_ready(struct udevice *dev)
+{
+ struct cr50_priv *priv = dev_get_priv(dev);
+ ulong timeout, base;
+ int i;
+
+ if (!priv->use_irq && !dm_gpio_is_valid(>ready_gpio)) {
+ /* Fixed delay if interrupt not supported */
+ udelay(TIMEOUT_NO_IRQ_US);
+ return 0;
+ }
+
+ base = timer_get_us();
+ timeout = base + TIMEOUT_IRQ_US;
+
+ i = 0;
+ while (priv->use_irq ? !irq_read_and_clear(>irq) :
+ !dm_gpio_get_value(>ready_gpio)) {
+ i++;
+ if ((int)(timer_get_us() - timeout) >= 0) {
+ log_warning("Timeout\n");
+ /*
+* Use this instead of -ETIMEDOUT which is used by i2c
+*/
+ return -ETIME;
+ }
+ }
+ log_debug("i=%d\n", i);
+
+ return 0;
+}
+
+/* Clear pending interrupts */
+static void cr50_i2c_clear_tpm_irq(struct udevice *dev)
+{
+ struct cr50_priv *priv = dev_get_priv(dev);
+
+ if (priv->use_irq)
+ irq_read_and_clear(>irq);
+}
+
+/*
+ * cr50_i2c_read() - read from TPM register
+ *
+ * @tpm: TPM chip information
+ * @addr: register address to read from
+ * @buffer: provided by caller
+ * @len: number of bytes to read
+ *
+ * 1) send register address byte 'addr' to the TPM
+ * 2) wait for TPM to indicate it is ready
+ * 3) read 'len' bytes of TPM response into the provided 'buffer'
+ *
+ * Return 0 on success. -ve on error
+ */
+static int cr50_i2c_read(struct udevice *dev, u8 addr, u8 *buffer,
+size_t len)
+{
+ int ret;
+
+ /* Clear interrupt before starting transaction */
+ cr50_i2c_clear_tpm_irq(dev);
+
+ /* Send the register address byte to the TPM */
+ ret = dm_i2c_write(dev, 0, , 1);
+ if (ret) {
+ log_err("Address write failed (err=%d)\n", ret);
+ return ret;
+ }
+
+ /* Wait for TPM to be ready with response data */
+ ret =
[PATCH v2 14/17] x86: coral: Add I2C and TPM device-tree definitions
Add nodes to the device tree for Cr50 and other available I2C ports. Also
enable the ACPI interrupt driver.
Signed-off-by: Simon Glass
---
Changes in v2:
- Move intel-clock.h inclusion to the correct patch
arch/x86/cpu/apollolake/Kconfig | 1 +
arch/x86/dts/chromebook_coral.dts | 88 +++
2 files changed, 89 insertions(+)
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index ec9f993808..2ae6837f75 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -42,6 +42,7 @@ config INTEL_APOLLOLAKE
imply CLK
imply CMD_CLK
imply CLK_INTEL
+ imply ACPI_GPE
if INTEL_APOLLOLAKE
diff --git a/arch/x86/dts/chromebook_coral.dts
b/arch/x86/dts/chromebook_coral.dts
index a4a9e949e6..44a4619a66 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
/ {
model = "Google Coral";
@@ -29,6 +30,14 @@
cros-ec0 = _ec;
fsp = _s;
spi0 =
+ i2c0 = _0;
+ i2c1 = _1;
+ i2c2 = _2;
+ i2c3 = _3;
+ i2c4 = _4;
+ i2c5 = _5;
+ i2c6 = _6;
+ i2c7 = _7;
};
config {
@@ -80,6 +89,13 @@
};
+ acpi_gpe: general-purpose-events {
+ reg = ;
+ compatible = "intel,acpi-gpe";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
keyboard {
intel,duplicate-por;
};
@@ -248,6 +264,78 @@
};
};
+ i2c_0: i2c2@16,0 {
+ compatible = "intel,apl-i2c";
+ reg = <0x0200b010 0 0 0 0>;
+ clocks = < CLK_I2C>;
+ i2c-scl-rising-time-ns = <104>;
+ i2c-scl-falling-time-ns = <52>;
+ };
+
+ i2c_1: i2c2@16,1 {
+ compatible = "intel,apl-i2c";
+ reg = <0x0200b110 0 0 0 0>;
+ clocks = < CLK_I2C>;
+ status = "disabled";
+ };
+
+ i2c_2: i2c2@16,2 {
+ compatible = "intel,apl-i2c";
+ reg = <0x0200b210 0 0 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <40>;
+ clocks = < CLK_I2C>;
+ i2c-scl-rising-time-ns = <57>;
+ i2c-scl-falling-time-ns = <28>;
+ tpm@50 {
+ reg = <0x50>;
+ compatible = "google,cr50";
+ u-boot,i2c-offset-len = <0>;
+ ready-gpio = <_n 28 GPIO_ACTIVE_LOW>;
+ interrupts-extended = <_gpe 0x3c 0>;
+ };
+ };
+
+ i2c_3: i2c2@16,3 {
+ compatible = "intel,apl-i2c";
+ reg = <0x0200b110 0 0 0 0>;
+ clocks = < CLK_I2C>;
+ i2c-scl-rising-time-ns = <76>;
+ i2c-scl-falling-time-ns = <164>;
+ };
+
+ i2c_4: i2c2@17,0 {
+ compatible = "intel,apl-i2c";
+ reg = <0x0200b110 0 0 0 0>;
+ clocks = < CLK_I2C>;
+ i2c-sda-hold-time-ns = <350>;
+ i2c-scl-rising-time-ns = <114>;
+ i2c-scl-falling-time-ns = <164>;
+ };
+
+ i2c_5: i2c2@17,1 {
+ compatible = "intel,apl-i2c";
+ reg = <0x0200b110 0 0 0 0>;
+ clocks = < CLK_I2C>;
+ i2c-scl-rising-time-ns = <76>;
+ i2c-scl-falling-time-ns = <164>;
+ };
+
+ i2c_6: i2c2@17,2 {
+ compatible = "intel,apl-i2c";
+ reg = <0x0200b110 0 0 0 0>;
+ clocks = < CLK_I2C>;
+ status = "disabled";
+ };
+
+ i2c_7: i2c2@17,3 {
+ compatible = "intel,apl-i2c";
+ reg = <0x0200b110 0 0 0 0>;
+ clocks = < CLK_I2C>;
+ status = "disabled";
+ };
+
serial: serial@18,2 {
reg = <0x0200c210 0 0 0 0>;
u-boot,dm-pre-reloc;
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 15/17] tpm: Add more TPM2 definitions
Add definitions for access and status.
Need to drop the mixed case.
Signed-off-by: Simon Glass
---
Changes in v2: None
include/tpm-v2.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index ae00803f6d..d53d2e4023 100644
--- a/include/tpm-v2.h
+++ b/include/tpm-v2.h
@@ -161,6 +161,37 @@ enum tpm_index_attrs {
TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
};
+enum {
+ TPM_ACCESS_VALID= 1 << 7,
+ TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
+ TPM_ACCESS_REQUEST_PENDING = 1 << 2,
+ TPM_ACCESS_REQUEST_USE = 1 << 1,
+ TPM_ACCESS_ESTABLISHMENT= 1 << 0,
+};
+
+enum {
+ TPM_STS_FAMILY_SHIFT= 26,
+ TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
+ TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
+ TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
+ TPM_STS_COMMAND_CANCEL = 1 << 24,
+ TPM_STS_BURST_COUNT_SHIFT = 8,
+ TPM_STS_BURST_COUNT_MASK= 0x << TPM_STS_BURST_COUNT_SHIFT,
+ TPM_STS_VALID = 1 << 7,
+ TPM_STS_COMMAND_READY = 1 << 6,
+ TPM_STS_GO = 1 << 5,
+ TPM_STS_DATA_AVAIL = 1 << 4,
+ TPM_STS_DATA_EXPECT = 1 << 3,
+ TPM_STS_SELF_TEST_DONE = 1 << 2,
+ TPM_STS_RESPONSE_RETRY = 1 << 1,
+};
+
+enum {
+ TPM_CMD_COUNT_OFFSET= 2,
+ TPM_CMD_ORDINAL_OFFSET = 6,
+ TPM_MAX_BUF_SIZE= 1260,
+};
+
/**
* Issue a TPM2_Startup command.
*
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 17/17] x86: coral: Enable TPM
Enable TPM2 so that we can use cr50. Signed-off-by: Simon Glass --- Changes in v2: - Update the commit message - Add new patches to handle requesting interrupts and interrupt state configs/chromebook_coral_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index b156e837ee..a7b71d99a1 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -53,7 +53,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_SOUND=y CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_TPM=y -CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -90,6 +89,8 @@ CONFIG_SPI=y CONFIG_ICH_SPI=y CONFIG_TPL_SYSRESET=y CONFIG_TPM_TIS_LPC=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_CR50_I2C=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y -- 2.25.0.341.g760bfbb309-goog
[PATCH v2 11/17] x86: itss: Add of-platdata support
Allow this driver to be used in TPL by setting up the interrupt type
correctly.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x86/cpu/intel_common/itss.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c
index 33962cb9a0..b6b57cc9a0 100644
--- a/arch/x86/cpu/intel_common/itss.c
+++ b/arch/x86/cpu/intel_common/itss.c
@@ -146,6 +146,15 @@ static int route_pmc_gpio_gpe(struct udevice *dev, uint
pmc_gpe_num)
return -ENOENT;
}
+static int itss_bind(struct udevice *dev)
+{
+ /* This is not set with of-platdata, so set it manually */
+ if (CONFIG_IS_ENABLED(OF_PLATDATA))
+ dev->driver_data = X86_IRQT_ITSS;
+
+ return 0;
+}
+
static int itss_ofdata_to_platdata(struct udevice *dev)
{
struct itss_priv *priv = dev_get_priv(dev);
@@ -208,6 +217,7 @@ U_BOOT_DRIVER(itss_drv) = {
.id = UCLASS_IRQ,
.of_match = itss_ids,
.ops= _ops,
+ .bind = itss_bind,
.ofdata_to_platdata = itss_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct itss_platdata),
.priv_auto_alloc_size = sizeof(struct itss_priv),
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 13/17] x86: Add support for ACPI general-purpose events
ACPI GPEs are used to signal interrupts from peripherals that are accessed
via ACPI. In U-Boot these are modelled as interrupts using a separate
interrupt controller. Configuration is via the device tree.
Add a simple driver for this.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x86/Kconfig | 33 +++
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/acpi_gpe.c | 85 +++
.../interrupt-controller/intel,acpi-gpe.txt | 30 +++
4 files changed, 149 insertions(+)
create mode 100644 arch/x86/cpu/acpi_gpe.c
create mode 100644
doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 89b93e5de2..c4a9a9f624 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -910,4 +910,37 @@ config X86_OFFSET_SPL
depends on SPL && X86
default SPL_TEXT_BASE
+config ACPI_GPE
+ bool "Support ACPI general-purpose events"
+ help
+ Enable a driver for ACPI GPEs to allow peripherals to send interrupts
+ via ACPI to the OS. In U-Boot this is only used when U-Boot itself
+ needs access to these interrupts. This can happen when it uses a
+ peripheral that is set up to use GPEs and so cannot use the normal
+ GPIO mechanism for polling an input.
+
+ See https://queue.acm.org/blogposting.cfm?id=18977 for more info
+
+config SPL_ACPI_GPE
+ bool "Support ACPI general-purpose events in SPL"
+ help
+ Enable a driver for ACPI GPEs to allow peripherals to send interrupts
+ via ACPI to the OS. In U-Boot this is only used when U-Boot itself
+ needs access to these interrupts. This can happen when it uses a
+ peripheral that is set up to use GPEs and so cannot use the normal
+ GPIO mechanism for polling an input.
+
+ See https://queue.acm.org/blogposting.cfm?id=18977 for more info
+
+config TPL_ACPI_GPE
+ bool "Support ACPI general-purpose events in TPL"
+ help
+ Enable a driver for ACPI GPEs to allow peripherals to send interrupts
+ via ACPI to the OS. In U-Boot this is only used when U-Boot itself
+ needs access to these interrupts. This can happen when it uses a
+ peripheral that is set up to use GPEs and so cannot use the normal
+ GPIO mechanism for polling an input.
+
+ See https://queue.acm.org/blogposting.cfm?id=18977 for more info
+
endmenu
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 5b40838e60..307267a8fb 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-$(CONFIG_INTEL_TANGIER) += tangier/
obj-$(CONFIG_APIC) += lapic.o ioapic.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
+obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o
obj-$(CONFIG_QFW) += qfw_cpu.o
ifndef CONFIG_$(SPL_)X86_64
obj-$(CONFIG_SMP) += mp_init.o
diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c
new file mode 100644
index 00..55005455c0
--- /dev/null
+++ b/arch/x86/cpu/acpi_gpe.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google, LLC
+ * Written by Simon Glass
+ */
+
+#include
+#include
+#include
+#include
+
+/**
+ * struct acpi_gpe_priv - private driver information
+ *
+ * @acpi_base: Base I/O address of ACPI registers
+ */
+struct acpi_gpe_priv {
+ ulong acpi_base;
+};
+
+#define GPE0_STS(x)(0x20 + ((x) * 4))
+
+static int acpi_gpe_read_and_clear(struct irq *irq)
+{
+ struct acpi_gpe_priv *priv = dev_get_priv(irq->dev);
+ u32 mask, sts;
+ ulong start;
+ int ret = 0;
+ int bank;
+
+ bank = irq->id / 32;
+ mask = 1 << (irq->id % 32);
+
+ /* Wait up to 1ms for GPE status to clear */
+ start = get_timer(0);
+ do {
+ if (get_timer(start) > 1)
+ return ret;
+
+ sts = inl(priv->acpi_base + GPE0_STS(bank));
+ if (sts & mask) {
+ outl(mask, priv->acpi_base + GPE0_STS(bank));
+ ret = 1;
+ }
+ } while (sts & mask);
+
+ return ret;
+}
+
+static int acpi_gpe_ofdata_to_platdata(struct udevice *dev)
+{
+ struct acpi_gpe_priv *priv = dev_get_priv(dev);
+
+ priv->acpi_base = dev_read_addr(dev);
+ if (!priv->acpi_base || priv->acpi_base == FDT_ADDR_T_NONE)
+ return log_msg_ret("acpi_base", -EINVAL);
+
+ return 0;
+}
+
+static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
+{
+ irq->id = args->args[0];
+
+ return 0;
+}
+
+static const struct irq_ops acpi_gpe_ops = {
+ .read_and_clear = acpi_gpe_read_and_clear,
+ .of_xlate = acpi_gpe_of_xlate,
+};
+
+static const struct udevice_id acpi_gpe_ids[] = {
+ { .compatible = "intel,acpi-gpe",
[PATCH v2 10/17] x86: Give each driver an IRQ type
Add an IRQ type to each driver and use irq_first_device_type() to find
and probe the correct one.
Signed-off-by: Simon Glass
---
Changes in v2:
- Move 'success' comment into previous patch
arch/x86/cpu/apollolake/fsp_s.c | 4 ++--
arch/x86/cpu/i386/interrupt.c| 3 ++-
arch/x86/cpu/intel_common/itss.c | 2 +-
arch/x86/cpu/irq.c | 3 ++-
drivers/pinctrl/intel/pinctrl.c | 2 +-
5 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index f8fa4dec8f..b2d9130841 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -535,7 +535,7 @@ int arch_fsps_preinit(void)
struct udevice *itss;
int ret;
- ret = uclass_first_device_err(UCLASS_IRQ, );
+ ret = irq_first_device_type(X86_IRQT_ITSS, );
if (ret)
return log_msg_ret("no itss", ret);
/*
@@ -576,7 +576,7 @@ int arch_fsp_init_r(void)
if (ret)
return ret;
- ret = uclass_first_device_err(UCLASS_IRQ, );
+ ret = irq_first_device_type(X86_IRQT_ITSS, );
if (ret)
return log_msg_ret("no itss", ret);
/* Restore GPIO IRQ polarities back to previous settings */
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index 70edbe06e4..4c7e9ea215 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -264,7 +265,7 @@ int interrupt_init(void)
int ret;
/* Try to set up the interrupt router, but don't require one */
- ret = uclass_first_device_err(UCLASS_IRQ, );
+ ret = irq_first_device_type(X86_IRQT_BASE, );
if (ret && ret != -ENODEV)
return ret;
diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c
index 9df51adecc..33962cb9a0 100644
--- a/arch/x86/cpu/intel_common/itss.c
+++ b/arch/x86/cpu/intel_common/itss.c
@@ -199,7 +199,7 @@ static const struct irq_ops itss_ops = {
};
static const struct udevice_id itss_ids[] = {
- { .compatible = "intel,itss"},
+ { .compatible = "intel,itss", .data = X86_IRQT_ITSS },
{ }
};
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index ed9938f7f7..bafa031082 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -351,7 +352,7 @@ int irq_router_probe(struct udevice *dev)
}
static const struct udevice_id irq_router_ids[] = {
- { .compatible = "intel,irq-router" },
+ { .compatible = "intel,irq-router", .data = X86_IRQT_BASE },
{ }
};
diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c
index 5bf5d8b0e2..f4cc55aa3b 100644
--- a/drivers/pinctrl/intel/pinctrl.c
+++ b/drivers/pinctrl/intel/pinctrl.c
@@ -613,7 +613,7 @@ int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
log_err("Cannot find community for pid %d\n", pplat->pid);
return -EDOM;
}
- ret = uclass_first_device_err(UCLASS_IRQ, >itss);
+ ret = irq_first_device_type(X86_IRQT_ITSS, >itss);
if (ret)
return log_msg_ret("Cannot find ITSS", ret);
priv->comm = comm;
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 12/17] dm: irq: Add support for requesting interrupts
At present driver model supports the IRQ uclass but there is no way to
request a particular interrupt for a driver.
Add a mechanism, similar to clock and reset, to read the interrupts
required by a device from the device tree and to request those interrupts.
U-Boot itself does not have interrupt-driven handlers, so just provide a
means to read and clear an interrupt. This can be useful to handle
peripherals which must use an interrupt to determine when data is
available, for example.
Bring over the basic binding file as well, from Linux v5.4. Note that the
older binding is not supported in U-Boot; the newer 'special form' must be
used.
Add a simple test of the new functionality.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/sandbox/dts/test.dts | 5 +-
.../interrupt-controller/interrupts.txt | 131 ++
drivers/misc/irq-uclass.c | 116
drivers/misc/irq_sandbox.c| 41 ++
include/irq.h | 115 +++
test/dm/irq.c | 31 +
6 files changed, 438 insertions(+), 1 deletion(-)
create mode 100644 doc/device-tree-bindings/interrupt-controller/interrupts.txt
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index e529c54d8d..c228447431 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -93,6 +93,7 @@
<_b 9 0xc 3 2 1>;
int-value = <1234>;
uint-value = <(-1234)>;
+ interrupts-extended = < 3 0>;
};
junk {
@@ -357,8 +358,10 @@
vss-microvolts = <0>;
};
- irq {
+ irq: irq {
compatible = "sandbox,irq";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
lcd {
diff --git a/doc/device-tree-bindings/interrupt-controller/interrupts.txt
b/doc/device-tree-bindings/interrupt-controller/interrupts.txt
new file mode 100644
index 00..38a399a6b1
--- /dev/null
+++ b/doc/device-tree-bindings/interrupt-controller/interrupts.txt
@@ -0,0 +1,131 @@
+Specifying interrupt information for devices
+
+
+1) Interrupt client nodes
+-
+
+Nodes that describe devices which generate interrupts must contain an
+"interrupts" property, an "interrupts-extended" property, or both. If both are
+present, the latter should take precedence; the former may be provided simply
+for compatibility with software that does not recognize the latter. These
+properties contain a list of interrupt specifiers, one per output interrupt.
The
+format of the interrupt specifier is determined by the interrupt controller to
+which the interrupts are routed; see section 2 below for details.
+
+ Example:
+ interrupt-parent = <>;
+ interrupts = <5 0>, <6 0>;
+
+The "interrupt-parent" property is used to specify the controller to which
+interrupts are routed and contains a single phandle referring to the interrupt
+controller node. This property is inherited, so it may be specified in an
+interrupt client node or in any of its parent nodes. Interrupts listed in the
+"interrupts" property are always in reference to the node's interrupt parent.
+
+The "interrupts-extended" property is a special form; useful when a node needs
+to reference multiple interrupt parents or a different interrupt parent than
+the inherited one. Each entry in this property contains both the parent phandle
+and the interrupt specifier.
+
+ Example:
+ interrupts-extended = < 5 1>, < 1 0>;
+
+(NOTE: only this 'special form' is supported in U-Boot)
+
+
+2) Interrupt controller nodes
+-
+
+A device is marked as an interrupt controller with the "interrupt-controller"
+property. This is a empty, boolean property. An additional "#interrupt-cells"
+property defines the number of cells needed to specify a single interrupt.
+
+It is the responsibility of the interrupt controller's binding to define the
+length and format of the interrupt specifier. The following two variants are
+commonly used:
+
+ a) one cell
+ ---
+ The #interrupt-cells property is set to 1 and the single cell defines the
+ index of the interrupt within the controller.
+
+ Example:
+
+ vic: intc@1014 {
+ compatible = "arm,versatile-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1014 0x1000>;
+ };
+
+ sic: intc@10003000 {
+ compatible = "arm,versatile-sic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x10003000 0x1000>;
+ interrupt-parent = <>;
+ interrupts = <31>; /* Cascaded to vic */
+ };
+
+ b) two cells
+
+ The #interrupt-cells property is set to 2 and the first cell
[PATCH v2 07/17] x86: apl: Drop the I2C config in FSP-S
This config is not actually used here and in U-Boot it seems better to set
this using the device tree for each individual controller. The monolithic
config of the FSP-S is only necessary if the FSP is actually configuring
something, but here it is not.
The FSP-S does enable/disable the various I2C ports. It might be nice to
handle this using the okay/disabled property of each port, but that can be
considered later.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 58 -
1 file changed, 58 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 9804227f80..f8fa4dec8f 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -24,7 +24,6 @@
#define HIDE_BIT BIT(0)
#define INTEL_GSPI_MAX 3
-#define INTEL_I2C_DEV_MAX 8
#define MAX_USB2_PORTS 8
enum {
@@ -32,36 +31,6 @@ enum {
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
};
-enum i2c_speed {
- I2C_SPEED_STANDARD = 10,
- I2C_SPEED_FAST = 40,
- I2C_SPEED_FAST_PLUS = 100,
- I2C_SPEED_HIGH = 340,
- I2C_SPEED_FAST_ULTRA= 500,
-};
-
-/*
- * Timing values are in units of clock period, with the clock speed
- * provided by the SOC
- *
- * TODO(s...@chromium.org): Connect this up to the I2C driver
- */
-struct dw_i2c_speed_config {
- enum i2c_speed speed;
- /* SCL high and low period count */
- u16 scl_lcnt;
- u16 scl_hcnt;
- /*
-* SDA hold time should be 300ns in standard and fast modes
-* and long enough for deterministic logic level change in
-* fast-plus and high speed modes.
-*
-* [15:0] SDA TX Hold Time
-* [23:16] SDA RX Hold Time
-*/
- u32 sda_hold;
-};
-
/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
enum serirq_mode {
SERIRQ_QUIET,
@@ -69,32 +38,6 @@ enum serirq_mode {
SERIRQ_OFF,
};
-/*
- * This I2C controller has support for 3 independent speed configs but can
- * support both FAST_PLUS and HIGH speeds through the same set of speed
- * config registers. These are treated separately so the speed config values
- * can be provided via ACPI to the OS.
- */
-#define DW_I2C_SPEED_CONFIG_COUNT 4
-
-struct dw_i2c_bus_config {
- /* Bus should be enabled in TPL with temporary base */
- int early_init;
- /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
- enum i2c_speed speed;
- /*
-* If rise_time_ns is non-zero the calculations for lcnt and hcnt
-* registers take into account the times of the bus. However, if
-* there is a match in speed_config those register values take
-* precedence
-*/
- int rise_time_ns;
- int fall_time_ns;
- int data_hold_time_ns;
- /* Specific bus speed configuration */
- struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT];
-};
-
struct gspi_cfg {
/* Bus speed in MHz */
u32 speed_mhz;
@@ -110,7 +53,6 @@ struct gspi_cfg {
struct soc_intel_common_config {
int chipset_lockdown;
struct gspi_cfg gspi[INTEL_GSPI_MAX];
- struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX];
};
enum pnp_settings {
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 09/17] dm: irq: Add support for interrupt controller types
There can be different types of interrupt controllers in a system and some
drivers may need to distinguish between these. In general this can be
handled using the device tree by adding the interrupt information to
device nodes.
However on x86 devices we have interrupt controllers which are not tied
to any particular device and not really used in U-Boot. These still need
to be inited, so a convenient method is to give each controller a type
and allow a particular controller type to be probed.
Add support for this in sandbox along with a test.
Signed-off-by: Simon Glass
---
Changes in v2:
- Move 'success' comment into this patch
- Update to use the new DM helper function
arch/sandbox/include/asm/test.h | 4
drivers/misc/irq-uclass.c | 15 ++-
drivers/misc/irq_sandbox.c | 2 +-
include/irq.h | 23 +++
test/dm/irq.c | 14 ++
5 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index 2421922c9e..7775794eaa 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -45,6 +45,10 @@
#define PCI_EA_BAR2_MAGIC 0x72727272
#define PCI_EA_BAR4_MAGIC 0x74747474
+enum {
+ SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */
+};
+
/* System controller driver data */
enum {
SYSCON0 = 32,
diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
index d5182cf149..c52c813ff3 100644
--- a/drivers/misc/irq-uclass.c
+++ b/drivers/misc/irq-uclass.c
@@ -1,11 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2015, Bin Meng
+ * Copyright 2019 Google, LLC
+ * Written by Simon Glass
*/
#include
#include
#include
+#include
int irq_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
{
@@ -47,6 +49,17 @@ int irq_restore_polarities(struct udevice *dev)
return ops->restore_polarities(dev);
}
+int irq_first_device_type(enum irq_dev_t type, struct udevice **devp)
+{
+ int ret;
+
+ ret = uclass_first_device_drvdata(UCLASS_IRQ, type, devp);
+ if (ret)
+ return log_msg_ret("find", ret);
+
+ return 0;
+}
+
UCLASS_DRIVER(irq) = {
.id = UCLASS_IRQ,
.name = "irq",
diff --git a/drivers/misc/irq_sandbox.c b/drivers/misc/irq_sandbox.c
index 6dda1a4c44..011022ac62 100644
--- a/drivers/misc/irq_sandbox.c
+++ b/drivers/misc/irq_sandbox.c
@@ -43,7 +43,7 @@ static const struct irq_ops sandbox_irq_ops = {
};
static const struct udevice_id sandbox_irq_ids[] = {
- { .compatible = "sandbox,irq"},
+ { .compatible = "sandbox,irq", SANDBOX_IRQT_BASE },
{ }
};
diff --git a/include/irq.h b/include/irq.h
index 01ded64f16..8b4e2ecfc0 100644
--- a/include/irq.h
+++ b/include/irq.h
@@ -8,6 +8,17 @@
#ifndef __irq_H
#define __irq_H
+/*
+ * Interrupt controller types available. You can find a particular one with
+ * irq_first_device_type()
+ */
+enum irq_dev_t {
+ X86_IRQT_BASE, /* Base controller */
+ X86_IRQT_ITSS, /* ITSS controller, e.g. on APL */
+ X86_IRQT_ACPI_GPE, /* ACPI General-Purpose Events controller */
+ SANDBOX_IRQT_BASE, /* Sandbox testing */
+};
+
/**
* struct irq_ops - Operations for the IRQ
*/
@@ -85,4 +96,16 @@ int irq_snapshot_polarities(struct udevice *dev);
*/
int irq_restore_polarities(struct udevice *dev);
+/**
+ * irq_first_device_type() - Get a particular interrupt controller
+ *
+ * On success this returns an activated interrupt device.
+ *
+ * @type: Type to find
+ * @devp: Returns the device, if found
+ * @return 0 if OK, -ENODEV if not found, other -ve error if uclass failed to
+ * probe
+ */
+int irq_first_device_type(enum irq_dev_t type, struct udevice **devp);
+
#endif
diff --git a/test/dm/irq.c b/test/dm/irq.c
index 726189c59f..0f23f108a7 100644
--- a/test/dm/irq.c
+++ b/test/dm/irq.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
@@ -30,3 +31,16 @@ static int dm_test_irq_base(struct unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_irq_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test of irq_first_device_type() */
+static int dm_test_irq_type(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(irq_first_device_type(SANDBOX_IRQT_BASE, ));
+ ut_asserteq(-ENODEV, irq_first_device_type(X86_IRQT_BASE, ));
+
+ return 0;
+}
+DM_TEST(dm_test_irq_type, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 05/17] x86: Add a clock driver for Intel devices
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.
This driver can be expanded later as needed.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/clk/Kconfig | 10 ++
drivers/clk/Makefile| 1 +
drivers/clk/intel/Makefile | 6
drivers/clk/intel/clk_intel.c | 41 +
include/dt-bindings/clock/intel-clock.h | 15 +
5 files changed, 73 insertions(+)
create mode 100644 drivers/clk/intel/Makefile
create mode 100644 drivers/clk/intel/clk_intel.c
create mode 100644 include/dt-bindings/clock/intel-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 16d4237f89..1992d4a4b4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -73,6 +73,16 @@ config CLK_COMPOSITE_CCF
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] composite code in U-Boot's clock driver.
+config CLK_INTEL
+ bool "Enable clock driver for Intel x86"
+ depends on CLK && X86
+ help
+ This provides very basic support for clocks on Intel SoCs. The driver
+ is barely used at present but could be expanded as needs arise.
+ Much clock configuration in U-Boot is either set up by the FSP, or
+ set up by U-Boot itself but only statically. Thus the driver does not
+ support changing clock rates, only querying them.
+
config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 06131edb9f..e01783391d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_CLK_MVEBU) += mvebu/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
obj-$(CONFIG_CLK_EXYNOS) += exynos/
+obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_OWL) += owl/
diff --git a/drivers/clk/intel/Makefile b/drivers/clk/intel/Makefile
new file mode 100644
index 00..45e93d7024
--- /dev/null
+++ b/drivers/clk/intel/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2010 Google LLC
+#
+
+obj-y += clk_intel.o
diff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c
new file mode 100644
index 00..d2e15491a3
--- /dev/null
+++ b/drivers/clk/intel/clk_intel.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass
+ */
+
+#include
+#include
+#include
+#include
+
+static ulong intel_clk_get_rate(struct clk *clk)
+{
+ ulong rate;
+
+ switch (clk->id) {
+ case CLK_I2C:
+ /* Hard-coded to 133MHz on current platforms */
+ return 1;
+ default:
+ return -ENODEV;
+ }
+
+ return rate;
+}
+
+static struct clk_ops intel_clk_ops = {
+ .get_rate = intel_clk_get_rate,
+};
+
+static const struct udevice_id intel_clk_ids[] = {
+ { .compatible = "intel,apl-clk" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_intel) = {
+ .name = "clk_intel",
+ .id = UCLASS_CLK,
+ .of_match = intel_clk_ids,
+ .ops= _clk_ops,
+};
diff --git a/include/dt-bindings/clock/intel-clock.h
b/include/dt-bindings/clock/intel-clock.h
new file mode 100644
index 00..e1edd3c71d
--- /dev/null
+++ b/include/dt-bindings/clock/intel-clock.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for Intel clocks.
+ *
+ * The constants defined in this header are used in the device tree
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _DT_BINDINGS_CLK_INTEL_H
+#define _DT_BINDINGS_CLK_INTEL_H
+
+#define CLK_I2C1
+
+#endif
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 04/17] tegra: i2c: Change driver to use helper function
Now that we have uclass_first_device_drvdata(), use it from the I2C driver
to reduce code duplication.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to change tegra driver to use helper function
drivers/i2c/tegra_i2c.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 4be41ddbf0..142463ef44 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -499,18 +499,7 @@ static int tegra_i2c_xfer(struct udevice *bus, struct
i2c_msg *msg,
int tegra_i2c_get_dvc_bus(struct udevice **busp)
{
- struct udevice *bus;
-
- for (uclass_first_device(UCLASS_I2C, );
-bus;
-uclass_next_device()) {
- if (dev_get_driver_data(bus) == TYPE_DVC) {
- *busp = bus;
- return 0;
- }
- }
-
- return -ENODEV;
+ return uclass_first_device_drvdata(UCLASS_I2C, TYPE_DVC, busp);
}
static const struct dm_i2c_ops tegra_i2c_ops = {
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 08/17] x86: coral: Update i2c and rtc status
These are actually working correctly, so update the status. Signed-off-by: Simon Glass --- Changes in v2: None doc/board/google/chromebook_coral.rst | 2 -- 1 file changed, 2 deletions(-) diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst index 5dc3c97c3d..d10e0c4954 100644 --- a/doc/board/google/chromebook_coral.rst +++ b/doc/board/google/chromebook_coral.rst @@ -213,9 +213,7 @@ To do - left-side USB - USB-C - Cr50 (security chip: a basic driver is running but not included here) - - I2C (driver exists but not enabled in device tree) - Sound (Intel I2S support exists, but need da7219 driver) - - RTC (driver exists but not enabled in device tree) - Various minor features supported by LPC, etc. - Booting Chrome OS, e.g. with verified boot - Integrate with Chrome OS vboot -- 2.25.0.341.g760bfbb309-goog
[PATCH v2 03/17] dm: core: Change syscon to use helper function
Now that we have uclass_first_device_drvdata(), use it from syscon to
reduce code duplication.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to change syscon to use helper function
drivers/core/syscon-uclass.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 5bb38e329c..b9ae82174e 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -128,22 +128,15 @@ struct regmap *syscon_regmap_lookup_by_phandle(struct
udevice *dev,
int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
{
- struct udevice *dev;
- struct uclass *uc;
int ret;
*devp = NULL;
- ret = uclass_get(UCLASS_SYSCON, );
+
+ ret = uclass_first_device_drvdata(UCLASS_SYSCON, driver_data, devp);
if (ret)
- return ret;
- uclass_foreach_dev(dev, uc) {
- if (dev->driver_data == driver_data) {
- *devp = dev;
- return device_probe(dev);
- }
- }
+ return log_msg_ret("find", ret);
- return -ENODEV;
+ return 0;
}
struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data)
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 06/17] x86: apl: Use the clock driver
Enable the Intel clock driver and modify coral's device tree to use it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Move intel-clock.h inclusion to the correct patch
arch/x86/cpu/apollolake/Kconfig | 3 +++
arch/x86/dts/chromebook_coral.dts | 5 +
2 files changed, 8 insertions(+)
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index fcff176c27..ec9f993808 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -39,6 +39,9 @@ config INTEL_APOLLOLAKE
imply HAVE_X86_FIT
imply INTEL_GPIO
imply SMP
+ imply CLK
+ imply CMD_CLK
+ imply CLK_INTEL
if INTEL_APOLLOLAKE
diff --git a/arch/x86/dts/chromebook_coral.dts
b/arch/x86/dts/chromebook_coral.dts
index a1820fa187..a4a9e949e6 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -39,6 +39,11 @@
stdout-path =
};
+ clk: clock {
+ compatible = "intel,apl-clk";
+ #clock-cells = <1>;
+ };
+
cpus {
u-boot,dm-pre-reloc;
#address-cells = <1>;
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 01/17] dm: core: Allow iterating devices without uclass_get()
At present we have uclass_foreach_dev() which requires that uclass_get()
be called beforehand to find the uclass. This is good if we suspect that
that function might fail, but often we know that the uclass is available.
Add a new helper which does this uclass_get() automatically, so that only
the uclass ID is needed.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to allow iterating devices without uclass_get()
include/dm/uclass.h | 17 +
test/dm/test-fdt.c | 21 +
2 files changed, 38 insertions(+)
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 484d166013..74b8e2ecb5 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -365,6 +365,23 @@ int uclass_next_device_check(struct udevice **devp);
*/
int uclass_resolve_seq(struct udevice *dev);
+/**
+ * uclass_id_foreach_dev() - Helper function to iteration through devices
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass ID in order from start to end.
+ *
+ * If for some reason the uclass cannot be found, this does nothing.
+ *
+ * @id: enum uclass_id ID to use
+ * @pos: struct udevice * to hold the current device. Set to NULL when there
+ * are no more devices.
+ * @uc: temporary uclass variable (struct udevice *)
+ */
+#define uclass_id_foreach_dev(id, pos, uc) \
+ if (!uclass_get(id, )) \
+ list_for_each_entry(pos, >dev_head, uclass_node)
+
/**
* uclass_foreach_dev() - Helper function to iteration through devices
*
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index d59c449ce0..8ea536c309 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -448,6 +448,27 @@ static int dm_test_first_next_device(struct
unit_test_state *uts)
}
DM_TEST(dm_test_first_next_device, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+/* Test iteration through devices in a uclass */
+static int dm_test_uclass_foreach(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int count;
+
+ count = 0;
+ uclass_id_foreach_dev(UCLASS_TEST_FDT, dev, uc)
+ count++;
+ ut_asserteq(8, count);
+
+ count = 0;
+ uclass_foreach_dev(dev, uc)
+ count++;
+ ut_asserteq(8, count);
+
+ return 0;
+}
+DM_TEST(dm_test_uclass_foreach, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
/**
* check_devices() - Check return values and pointers
*
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 02/17] dm: core: Add a function to find a device by drvdata
It is sometimes useful to find a device in a uclass using only its driver
data. The driver data often indicates the 'subtype' of the device, e,g,
via its compatible string.
Add a function to handle this.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to find a device by drvdata
drivers/core/uclass.c | 17 +
include/dm/test.h | 2 ++
include/dm/uclass.h | 14 ++
test/dm/test-fdt.c| 21 +
4 files changed, 54 insertions(+)
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index c520ef113a..61192d8a9f 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -629,6 +629,23 @@ int uclass_next_device_check(struct udevice **devp)
return device_probe(*devp);
}
+int uclass_first_device_drvdata(enum uclass_id id, ulong driver_data,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(id, dev, uc) {
+ if (dev_get_driver_data(dev) == driver_data) {
+ *devp = dev;
+
+ return device_probe(dev);
+ }
+ }
+
+ return -ENODEV;
+}
+
int uclass_bind_device(struct udevice *dev)
{
struct uclass *uc;
diff --git a/include/dm/test.h b/include/dm/test.h
index 07385cd531..f0f36624ce 100644
--- a/include/dm/test.h
+++ b/include/dm/test.h
@@ -56,6 +56,8 @@ enum {
enum {
DM_TEST_TYPE_FIRST = 0,
DM_TEST_TYPE_SECOND,
+
+ DM_TEST_TYPE_COUNT,
};
/* The number added to the ping total on each probe */
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 74b8e2ecb5..70fca79b44 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -350,6 +350,20 @@ int uclass_first_device_check(enum uclass_id id, struct
udevice **devp);
*/
int uclass_next_device_check(struct udevice **devp);
+/**
+ * uclass_first_device_drvdata() - Find the first device with given driver data
+ *
+ * This searches through the devices for a particular uclass looking for one
+ * that has the given driver data.
+ *
+ * @id: Uclass ID to check
+ * @driver_data: Driver data to search for
+ * @devp: Returns pointer to the first matching device in that uclass, if found
+ * @return 0 if found, -ENODEV if not found, other -ve on error
+ */
+int uclass_first_device_drvdata(enum uclass_id id, ulong driver_data,
+ struct udevice **devp);
+
/**
* uclass_resolve_seq() - Resolve a device's sequence number
*
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 8ea536c309..698ca0e7cf 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -893,3 +893,24 @@ static int dm_test_read_int(struct unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_read_int, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test iteration through devices by drvdata */
+static int dm_test_uclass_drvdata(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_first_device_drvdata(UCLASS_TEST_FDT,
+ DM_TEST_TYPE_FIRST, ));
+ ut_asserteq_str("a-test", dev->name);
+
+ ut_assertok(uclass_first_device_drvdata(UCLASS_TEST_FDT,
+ DM_TEST_TYPE_SECOND, ));
+ ut_asserteq_str("d-test", dev->name);
+
+ ut_asserteq(-ENODEV, uclass_first_device_drvdata(UCLASS_TEST_FDT,
+DM_TEST_TYPE_COUNT,
+));
+
+ return 0;
+}
+DM_TEST(dm_test_uclass_drvdata, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
--
2.25.0.341.g760bfbb309-goog
[PATCH v2 00/17] x86: coral: Add support for Cr50
This series adds a driver for the Cr50 security chip and enables it on coral. This supports the 'tpm' command. In order to make this work a few other changes are included: - Additional UCLASS_IRQ operations to support requesting and reading interrupts, using the device tree - A driver for ACPI general-purpose events There are also a few small clean-ups to the recently landed Apollo Lake support. This series relies on this patch: http://patchwork.ozlabs.org/patch/1214541/ Changes in v2: - Add new patch to allow iterating devices without uclass_get() - Add new patch to find a device by drvdata - Add new patch to change syscon to use helper function - Add new patch to change tegra driver to use helper function - Move intel-clock.h inclusion to the correct patch - Move 'success' comment into this patch - Update to use the new DM helper function - Move 'success' comment into previous patch - Move intel-clock.h inclusion to the correct patch - Significant rewrite of cr50 init procedure - Support use of interrupts - Update the commit message - Add new patches to handle requesting interrupts and interrupt state Simon Glass (17): dm: core: Allow iterating devices without uclass_get() dm: core: Add a function to find a device by drvdata dm: core: Change syscon to use helper function tegra: i2c: Change driver to use helper function x86: Add a clock driver for Intel devices x86: apl: Use the clock driver x86: apl: Drop the I2C config in FSP-S x86: coral: Update i2c and rtc status dm: irq: Add support for interrupt controller types x86: Give each driver an IRQ type x86: itss: Add of-platdata support dm: irq: Add support for requesting interrupts x86: Add support for ACPI general-purpose events x86: coral: Add I2C and TPM device-tree definitions tpm: Add more TPM2 definitions tpm: Add a driver for H1/Cr50 x86: coral: Enable TPM arch/sandbox/dts/test.dts | 5 +- arch/sandbox/include/asm/test.h | 4 + arch/x86/Kconfig | 33 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/acpi_gpe.c | 85 +++ arch/x86/cpu/apollolake/Kconfig | 4 + arch/x86/cpu/apollolake/fsp_s.c | 62 +- arch/x86/cpu/i386/interrupt.c | 3 +- arch/x86/cpu/intel_common/itss.c | 12 +- arch/x86/cpu/irq.c| 3 +- arch/x86/dts/chromebook_coral.dts | 93 +++ configs/chromebook_coral_defconfig| 3 +- doc/board/google/chromebook_coral.rst | 2 - .../interrupt-controller/intel,acpi-gpe.txt | 30 + .../interrupt-controller/interrupts.txt | 131 drivers/clk/Kconfig | 10 + drivers/clk/Makefile | 1 + drivers/clk/intel/Makefile| 6 + drivers/clk/intel/clk_intel.c | 41 ++ drivers/core/syscon-uclass.c | 15 +- drivers/core/uclass.c | 17 + drivers/i2c/tegra_i2c.c | 13 +- drivers/misc/irq-uclass.c | 131 +++- drivers/misc/irq_sandbox.c| 43 +- drivers/pinctrl/intel/pinctrl.c | 2 +- drivers/tpm/Kconfig | 10 + drivers/tpm/Makefile | 1 + drivers/tpm/cr50_i2c.c| 661 ++ include/dm/test.h | 2 + include/dm/uclass.h | 31 + include/dt-bindings/clock/intel-clock.h | 15 + include/irq.h | 138 include/tpm-v2.h | 31 + test/dm/irq.c | 45 ++ test/dm/test-fdt.c| 42 ++ 35 files changed, 1633 insertions(+), 93 deletions(-) create mode 100644 arch/x86/cpu/acpi_gpe.c create mode 100644 doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt create mode 100644 doc/device-tree-bindings/interrupt-controller/interrupts.txt create mode 100644 drivers/clk/intel/Makefile create mode 100644 drivers/clk/intel/clk_intel.c create mode 100644 drivers/tpm/cr50_i2c.c create mode 100644 include/dt-bindings/clock/intel-clock.h -- 2.25.0.341.g760bfbb309-goog
Re: [PATCH v2 08/13] dm: irq: Add support for requesting interrupts
Hi Bin,
On Mon, 3 Feb 2020 at 10:05, Bin Meng wrote:
>
> Hi Simon,
>
> On Sun, Dec 22, 2019 at 2:16 AM Simon Glass wrote:
> >
> > At present driver model supports the IRQ uclass but there is no way to
> > request a particular interrupt for a driver.
> >
> > Add a mechanism, similar to clock and reset, to read the interrupts
> > required by a device from the device tree and to request those interrupts.
> >
> > U-Boot itself does not have interrupt-driven handlers, so just provide a
> > means to read and clear an interrupt. This can be useful to handle
> > peripherals which must use an interrupt to determine when data is
> > available, for example.
> >
> > Bring over the basic binding file as well, from Linux v5.4. Note that the
> > older binding is not supported in U-Boot; the newer 'special form' must be
> > used.
> >
> > Add a simple test of the new functionality.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v2: None
> >
> > arch/sandbox/dts/test.dts | 5 +-
> > .../interrupt-controller/interrupts.txt | 131 ++
> > drivers/misc/irq-uclass.c | 116
> > drivers/misc/irq_sandbox.c| 41 ++
> > include/irq.h | 115 +++
> > test/dm/irq.c | 31 +
> > 6 files changed, 438 insertions(+), 1 deletion(-)
> > create mode 100644
> > doc/device-tree-bindings/interrupt-controller/interrupts.txt
> >
[..]
> > diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
> > index 38498a66a4..7d65192858 100644
> > --- a/drivers/misc/irq-uclass.c
> > +++ b/drivers/misc/irq-uclass.c
> > @@ -4,8 +4,11 @@
> > * Written by Simon Glass
> > */
> >
> > +#define LOG_CATEGORY UCLASS_IRQ
> > +
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -49,6 +52,119 @@ int irq_restore_polarities(struct udevice *dev)
> > return ops->restore_polarities(dev);
> > }
> >
> > +int irq_read_and_clear(struct irq *irq)
> > +{
> > + const struct irq_ops *ops = irq_get_ops(irq->dev);
> > +
> > + if (!ops->read_and_clear)
> > + return -ENOSYS;
> > +
> > + return ops->read_and_clear(irq);
> > +}
> > +
> > +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> > +int irq_get_by_index_platdata(struct udevice *dev, int index,
> > + struct phandle_1_arg *cells, struct irq *irq)
> > +{
> > + int ret;
> > +
> > + if (index != 0)
> > + return -ENOSYS;
> > + ret = uclass_get_device(UCLASS_IRQ, 0, >dev);
> > + if (ret)
> > + return ret;
> > + irq->id = cells[0].arg[0];
> > +
> > + return 0;
> > +}
> > +#else
> > +static int irq_of_xlate_default(struct irq *irq,
> > + struct ofnode_phandle_args *args)
> > +{
> > + log_debug("(irq=%p)\n", irq);
> > +
> > + if (args->args_count > 1) {
> > + log_debug("Invaild args_count: %d\n", args->args_count);
> > + return -EINVAL;
> > + }
> > +
> > + if (args->args_count)
> > + irq->id = args->args[0];
> > + else
> > + irq->id = 0;
> > +
> > + return 0;
> > +}
> > +
> > +static int irq_get_by_index_tail(int ret, ofnode node,
>
> It's odd to pass the return value of some other functions to this
> function and check it here. Can we please remove ret, and check its
> value at where we get that?
This pattern is similar to how it is done in DM core. It routes all
return paths through a single function where you can do error
checking, etc. So I think this is better than the alternative. The
only strange thing here is that this function is only used one. I did
this since I suspected there would be others coming. But I could
inline if it you like..
[..]
> > +static int sandbox_irq_of_xlate(struct irq *irq,
> > + struct ofnode_phandle_args *args)
> > +{
> > + irq->id = args->args[0];
> > +
> > + return 0;
> > +}
>
> This
...?
Regards,
Simon
Re: [PATCH v3 05/12] dm: Add support for simple-pm-bus
> Please can you add a test for this new functionality? Should this be separate from test/dm/bus.c? As far as I can tell, that file tests the concept of busses, and not the bus uclass. --Sean
Re: [PATCH v3 04/12] reset: Add generic reset driver
> Is there a sandbox test for this driver somewhere in your series? There is not. Presumably if such a test were to exist, it would try asserting different resets, and then check to see if the associated register got changed. However, I am confused as to where such a test would be located. There doesn't seem to be a directory for driver tests under tests/. tests/dm seems to be for uclass testing, and tests/py seems to be for tests which can work via the console. --Sean
Re: [U-Boot] [PATCH] fit: Do not automatically decompress ramdisk images
On 08/08/2019 05.16, Tom Rini wrote:
> On Fri, Aug 02, 2019 at 03:52:28PM -0700, Julius Werner wrote:
>
>> The Linux ramdisk should always be decompressed by the kernel itself,
>> not by U-Boot. Therefore, the 'compression' node in the FIT image should
>> always be set to "none" for ramdisk images, since the only point of
>> using that node is if you want U-Boot to do the decompression itself.
>>
>> Yet some systems populate the node to the compression algorithm used by
>> the kernel instead. This used to be ignored, but now that we support
>> decompression of all image types it becomes a problem. Since ramdisks
>> should never be decompressed by U-Boot anyway, this patch adds a special
>> exception for them to avoid these issues. Still, setting the
>> 'compression' node like that is wrong in the first place, so we still
>> want to print out a warning so that third-party distributions doing this
>> can notice and fix it.
>>
>> Signed-off-by: Julius Werner
>> Reviewed-by: Heiko Schocher
>> Tested-by: Heiko Schocher
>> Reviewed-by: Simon Goldschmidt
This part
+ if (image_type == IH_TYPE_RAMDISK && comp != IH_COMP_NONE)
+ puts("WARNING: 'compression' nodes for ramdisks are deprecated,"
+" please fix your .its file!\n");
+
ends up being a little confusing, because when one dutifully removes the
compression = "foo" property, the warning is still there (because comp
ends up being (u8)-1) - the only way to silence it is by actually
_having_ a 'compression = "none"' property. (It also says node instead
of property).
So, what is the intention? Should ramdisk images not have a compression
property at all, or must it be present but set to "none", or are either
acceptable?
Rasmus
Re: [PATCH 4/4] rockchip: Enable HDMI output on rk3399 board w/ HDMI
On Mon, 3 Feb 2020 09:47:08 -0500 Tom Rini tr...@konsulko.com wrote: ... > > yes, this evb board config is common across most of the rk3399 > > defconfig boards. this patch enable hdmi on few rk3399 boards all use > > same config file, evb_rk3399.h > > Yes, the ROCKCHIP_DEVICE_SETTINGS part makes sense, but the rest looks > very much like part of we need to rework the commit I mentioned. I > don't object to this going in as-is. Anatolij, how goes the rework of > things however? I do want to see that get in sooner rather than later > so we can sort out other regressions from just a lack of CONFIG options > being enabled. Thanks! A patch [1] for this is under build testing. [1] http://patchwork.ozlabs.org/patch/1233033 -- Anatolij
[PATCH] video: add opt out option for VIDEO_BBP selection
Enable all BPP options by default to avoid empty video console
output (this was the case before commit 2cc393f32fd9 ("video: make
BPP and ANSI configs optional")). But also support optional selection
of only required VIDEO_BBP settings.
Signed-off-by: Anatolij Gustschin
---
drivers/video/Kconfig | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 50ab3650ee..62217fda08 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -35,9 +35,21 @@ config BACKLIGHT_GPIO
it understands the standard device tree
(leds/backlight/gpio-backlight.txt)
+config VIDEO_BPP_OPT_OUT
+ bool "Support manual selection of video console BPP"
+ depends on DM_VIDEO
+ help
+ Enabling this option allows manual selection of the required
+ VIDEO_BPPxx configuration. By default all BPP options are
+ enabled to avoid empty console output. Some boards do not use
+ all BPP options and want to avoid dead code to reduce binary
+ image size. Let them opt out and select the needed BPP in the
+ board defconfig file.
+
config VIDEO_BPP8
bool "Support 8-bit-per-pixel displays"
depends on DM_VIDEO
+ default y if DM_VIDEO && !VIDEO_BPP_OPT_OUT
help
Support drawing text and bitmaps onto a 8-bit-per-pixel display.
Enabling this will include code to support this display. Without
@@ -47,6 +59,7 @@ config VIDEO_BPP8
config VIDEO_BPP16
bool "Support 16-bit-per-pixel displays"
depends on DM_VIDEO
+ default y if DM_VIDEO && !VIDEO_BPP_OPT_OUT
help
Support drawing text and bitmaps onto a 16-bit-per-pixel display.
Enabling this will include code to support this display. Without
@@ -56,7 +69,7 @@ config VIDEO_BPP16
config VIDEO_BPP32
bool "Support 32-bit-per-pixel displays"
depends on DM_VIDEO
- default y if X86
+ default y if DM_VIDEO && !VIDEO_BPP_OPT_OUT
help
Support drawing text and bitmaps onto a 32-bit-per-pixel display.
Enabling this will include code to support this display. Without
--
2.17.1
[PATCH v2] cmd: Add command to dump drivers and compatible strings
This adds a subcommand to dm to dump out what drivers are installed, and their
compatible strings. I have found this useful in ensuring that I have the correct
drivers compiled, and that I have put in the correct compatible strings.
Signed-off-by: Sean Anderson
---
Changes for v2:
- Check if entry->of_match is NULL before accessing it
cmd/dm.c| 12 +++-
drivers/core/dump.c | 20
include/dm/util.h | 3 +++
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/cmd/dm.c b/cmd/dm.c
index 7b271db0bb..7a90685f8b 100644
--- a/cmd/dm.c
+++ b/cmd/dm.c
@@ -40,10 +40,19 @@ static int do_dm_dump_devres(cmd_tbl_t *cmdtp, int flag,
int argc,
return 0;
}
+static int do_dm_dump_drivers(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ dm_dump_drivers();
+
+ return 0;
+}
+
static cmd_tbl_t test_commands[] = {
U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""),
U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""),
U_BOOT_CMD_MKENT(devres, 1, 1, do_dm_dump_devres, "", ""),
+ U_BOOT_CMD_MKENT(drivers, 1, 1, do_dm_dump_drivers, "", ""),
};
static __maybe_unused void dm_reloc(void)
@@ -84,5 +93,6 @@ U_BOOT_CMD(
"Driver model low level access",
"tree Dump driver model tree ('*' = activated)\n"
"dm uclassDump list of instances for each uclass\n"
- "dm devresDump list of device resources for each device"
+ "dm devresDump list of device resources for each device\n"
+ "dm drivers Dump list of drivers and their compatible strings"
);
diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index 4704049aee..b5046398d4 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -96,3 +96,23 @@ void dm_dump_uclass(void)
puts("\n");
}
}
+
+void dm_dump_drivers(void)
+{
+ struct driver *d = ll_entry_start(struct driver, driver);
+ const int n_ents = ll_entry_count(struct driver, driver);
+ struct driver *entry;
+ const struct udevice_id *match;
+
+ puts("DriverCompatible\n");
+ puts("\n");
+ for (entry = d; entry < d + n_ents; entry++) {
+ for (match = entry->of_match;
+match && match->compatible; match++)
+ printf("%-20.20s %s\n",
+ match == entry->of_match ? entry->name : "",
+ match->compatible);
+ if (match == entry->of_match)
+ printf("%-20.20s\n", entry->name);
+ }
+}
diff --git a/include/dm/util.h b/include/dm/util.h
index 348c2ace3c..0ccb3fbadf 100644
--- a/include/dm/util.h
+++ b/include/dm/util.h
@@ -39,6 +39,9 @@ static inline void dm_dump_devres(void)
}
#endif
+/* Dump out a list of drivers */
+void dm_dump_drivers(void);
+
/**
* Check if an of node should be or was bound before relocation.
*
--
2.25.0
[RFC PATCH 10/10] arm: add (default) config for nanopi2 board
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - Configuration changed, mainly several "CONFIG_..." moved from s5p4418_nanopi2.h to s5p4418_nanopi2_defconfig. - s5p4418_nanopi2.h: "CONFIG_" removed from several s5p4418/nanopi2 specific defines because the appropriate values do not need to be configurable. Signed-off-by: Stefan Bosch --- MAINTAINERS | 19 +++ configs/s5p4418_nanopi2_defconfig | 177 + doc/README.s5p4418| 63 + include/configs/s5p4418_nanopi2.h | 270 ++ 4 files changed, 529 insertions(+) create mode 100644 configs/s5p4418_nanopi2_defconfig create mode 100644 doc/README.s5p4418 create mode 100644 include/configs/s5p4418_nanopi2.h diff --git a/MAINTAINERS b/MAINTAINERS index 7d2729d..9e5de66 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -258,6 +258,25 @@ F: arch/arm/mach-at91/ F: board/atmel/ F: drivers/misc/microchip_flexcom.c +ARM NEXELL S5P4418 +M: Stefan Bosch +S: Maintained +F: arch/arm/cpu/armv7/s5p4418/ +F: arch/arm/dts/s5p4418* +F: arch/arm/mach-nexell/ +F: board/friendlyarm/ +F: configs/s5p4418_nanopi2_defconfig +F: doc/README.s5p4418 +F: drivers/gpio/nx_gpio.c +F: drivers/i2c/nx_i2c.c +F: drivers/mmc/nexell_dw_mmc_dm.c +F: drivers/pwm/pwm-nexell* +F: drivers/video/nexell/ +F: drivers/pwm/pwm-nexell* +F: drivers/video/nexell/ +F: drivers/video/nexell_display.c +F: include/configs/s5p4418_nanopi2.h + ARM OWL M: Manivannan Sadhasivam S: Maintained diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig new file mode 100644 index 000..921470a --- /dev/null +++ b/configs/s5p4418_nanopi2_defconfig @@ -0,0 +1,177 @@ +CONFIG_ARM=y +CONFIG_ARCH_NEXELL=y +CONFIG_ARCH_S5P4418=y +CONFIG_TARGET_NANOPI2=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="s5p4418-nanopi2" +CONFIG_FIT=y + +# Must be set to 'n' (apparently "CONFIG_EFI_LOADER=y" per default) +# otherwise boot errors "efi_runtime_relocate: Unknown relocation type 0" +CONFIG_EFI_LOADER=n + +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set + +# CONFIG_CMD_NET is not set + +# Default is CONFIG_NET=y, in this case: +# Loading Environment from MMC... ## Warning: Unknown environment variable type 'm' +# OK +# CONFIG_CMD_NET=y must be set to avoid this Warning. But then: +# Net: Net Initialization Skipped +# No ethernet found. +# If CONFIG_NET=n is set additionally warning at "make s5p4418_nanopi2_defconfig": +#arch/../configs/s5p4418_nanopi2_defconfig:24:warning: override: reassigning to symbol CMD_NET +# +# --> CONFIG_NET=n set only +CONFIG_NET=n + +# CONFIG_CMD_NFS is not set +CONFIG_CMD_FDISK=y +CONFIG_CMD_EXT4_IMG_WRITE=y +CONFIG_CMD_SD_RECOVERY=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y + +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_NEXELL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_AXP228=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_AXP228=y +CONFIG_DM_PWM=n + +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y + +CONFIG_DISPLAY=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_CONSOLE_BG_COL=0xff +CONFIG_SYS_CONSOLE_FG_COL=0x00 +CONFIG_VIDEO_NX=y +CONFIG_VIDEO_NX_RGB=y +CONFIG_VIDEO_NX_LVDS=y + +CONFIG_VIDEO_NX_HDMI=y + +CONFIG_REGEX=y +CONFIG_ERRNO_STR=y + +CONFIG_SYS_TEXT_BASE=0x74C0 +CONFIG_SYS_RESERVE_MEM_SIZE=0x0040 +CONFIG_NR_DRAM_BANKS=1 + +## System initialize options (board_init_f) +# board_init_f->init_sequence, call board_early_init_f +CONFIG_BOARD_LATE_INIT=y +# board_init_f->init_sequence, call print_cpuinfo +CONFIG_DISPLAY_CPUINFO=y +# board_init_f->init_sequence, call show_board_info +CONFIG_DISPLAY_BOARDINFO=y +# board_init_f, CONFIG_SYS_ICACHE_OFF +CONFIG_SYS_DCACHE_OFF=y +# board_init_r, call arch_misc_init +CONFIG_ARCH_MISC_INIT=y + +CONFIG_BOOTDELAY=1 +CONFIG_ZERO_BOOTDELAY_CHECK=y + +## U-Boot Environments +## refer to common/env_common.c + +# CONFIG_ENV_IS_IN_MMC must be set here and not in s5p4418_nanopi2.h +# otherwise CONFIG_ENV_IS_NOWHERE is set by env/Kconfig and environment +# (bootargs) are not loaded +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_OFFSET=0x2E0200 +CONFIG_ENV_SIZE=0x4000 +CONFIG_CMD_SAVEENV=y + +## Etc Command definition +# image info +CONFIG_CMD_IMI=y +# add command line history +CONFIG_CMDLINE_EDITING=y +CONFIG_INITRD_TAG=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_REVISION_TAG=y +CONFIG_CMD_BOOTZ=y + +## serial console configuration +CONFIG_CONS_INDEX=0 +CONFIG_BAUDRATE=115200 + +## SD/MMC +CONFIG_BOUNCE_BUFFER=y +CONFIG_GENERIC_MMC=y +CONFIG_MMC=y +CONFIG_MMC_DW=y +CONFIG_NEXELL_DWMMC=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y + +CONFIG_DOS_PARTITION=y +CONFIG_CMD_FAT=y +CONFIG_FS_FAT=y +CONFIG_FAT_WRITE=y + +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_FS_EXT4=y
[RFC PATCH 09/10] arm: add support for SoC s5p4418 (cpu) / nanopi2 board
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- SPL not supported yet --> no spl-dir in arch/arm/cpu/armv7/s5p4418/.
Appropriate line in Makefile removed.
- cpu.c: '#include ' added.
- arch/arm/cpu/armv7/s5p4418/u-boot.lds removed, is not required
anylonger.
- s5p4418.dtsi: '#include "../../../include/generated/autoconf.h"'
removed, is not necessary, error at out-of-tree building.
'#ifdef CONFIG_CPU_NXP4330'-blocks (2x) removed. Some minor changes
regarding mmc. 'u-boot,dm-pre-reloc' added to dp0 because of added
DM_VIDEO support.
- board/s5p4418/ renamed to board/friendlyarm/
- All s5p4418-boards except nanopi2 removed because there is no
possibility to test the other boards.
- Kconfig: Changes to have a structure like mach-bcm283x (RaspberryPi),
e.g. "config ..." entries moved from/to other Kconfig.
- "CONFIG_" removed from several s5p4418/nanopi2 specific defines
because the appropriate values do not need to be configurable.
- nanopi2/board.c: All getenv(), getenv_ulong(), setenv() and saveenv()
renamed to env_get(), env_get_ulong(), env_set() and env_save(),
respectively. MACH_TYPE_S5P4418 is not defined anymore, therefore
appropriate code removed (not necessary for DT-kernels).
- nanopi2/onewire.c: All crc8() renamed to crc8_ow() because crc8() is
already defined in lib/crc8.c (with different parameters).
Signed-off-by: Stefan Bosch
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/s5p4418/Makefile | 6 +
arch/arm/cpu/armv7/s5p4418/cpu.c | 120 ++
arch/arm/dts/Makefile | 3 +
arch/arm/dts/s5p4418-nanopi2.dts | 109 ++
arch/arm/dts/s5p4418-pinctrl.dtsi | 66
arch/arm/dts/s5p4418.dtsi | 157
board/friendlyarm/Kconfig | 39 ++
board/friendlyarm/nanopi2/Kconfig | 12 +
board/friendlyarm/nanopi2/MAINTAINERS | 7 +
board/friendlyarm/nanopi2/Makefile| 6 +
board/friendlyarm/nanopi2/board.c | 581
board/friendlyarm/nanopi2/hwrev.c | 122 ++
board/friendlyarm/nanopi2/hwrev.h | 29 ++
board/friendlyarm/nanopi2/lcds.c | 703 ++
board/friendlyarm/nanopi2/nxp-fb.h| 99 +
board/friendlyarm/nanopi2/onewire.c | 323
board/friendlyarm/nanopi2/onewire.h | 29 ++
18 files changed, 2412 insertions(+)
create mode 100644 arch/arm/cpu/armv7/s5p4418/Makefile
create mode 100644 arch/arm/cpu/armv7/s5p4418/cpu.c
create mode 100644 arch/arm/dts/s5p4418-nanopi2.dts
create mode 100644 arch/arm/dts/s5p4418-pinctrl.dtsi
create mode 100644 arch/arm/dts/s5p4418.dtsi
create mode 100644 board/friendlyarm/Kconfig
create mode 100644 board/friendlyarm/nanopi2/Kconfig
create mode 100644 board/friendlyarm/nanopi2/MAINTAINERS
create mode 100644 board/friendlyarm/nanopi2/Makefile
create mode 100644 board/friendlyarm/nanopi2/board.c
create mode 100644 board/friendlyarm/nanopi2/hwrev.c
create mode 100644 board/friendlyarm/nanopi2/hwrev.h
create mode 100644 board/friendlyarm/nanopi2/lcds.c
create mode 100644 board/friendlyarm/nanopi2/nxp-fb.h
create mode 100644 board/friendlyarm/nanopi2/onewire.c
create mode 100644 board/friendlyarm/nanopi2/onewire.h
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 8c955d0..ee87417 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_VF610) += vf610/
+obj-$(CONFIG_ARCH_S5P4418) += s5p4418/
diff --git a/arch/arm/cpu/armv7/s5p4418/Makefile
b/arch/arm/cpu/armv7/s5p4418/Makefile
new file mode 100644
index 000..321b257
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5p4418/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 Nexell
+# Hyunseok, Jung
+
+obj-y += cpu.o
diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c
new file mode 100644
index 000..79c284f
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5p4418/cpu.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Nexell
+ * Hyunseok, Jung
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndefCONFIG_ARCH_CPU_INIT
+#error must be define the macro "CONFIG_ARCH_CPU_INIT"
+#endif
+
+void s_init(void)
+{
+}
+
+static void cpu_soc_init(void)
+{
+ /*
+* NOTE> ALIVE Power Gate must enable for Alive register access.
+* must be clear wfi jump address
+*/
+ writel(1, ALIVEPWRGATEREG);
+ writel(0x, SCR_ARM_SECOND_BOOT);
+
+ /* write 0xf0 on alive scratchpad reg for boot success check */
+ writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET));
+
+ /* set l2 cache tieoff */
+
[RFC PATCH 08/10] video: add nexell video driver (display/video driver)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- nexell_display.c: Changed to DM, CONFIG_FB_ADDR can not be used
anymore because framebuffer is allocated by video_reserve() in
video-uclass.c. Therefore code changed appropriately.
Signed-off-by: Stefan Bosch
---
drivers/video/Kconfig | 10 +
drivers/video/Makefile | 1 +
drivers/video/nexell/Kconfig | 27 ++
drivers/video/nexell/Makefile | 12 +
drivers/video/nexell/s5pxx18_dp.c | 338
drivers/video/nexell/s5pxx18_dp_hdmi.c | 543 ++
drivers/video/nexell/s5pxx18_dp_lvds.c | 274 +
drivers/video/nexell/s5pxx18_dp_mipi.c | 677 +
drivers/video/nexell/s5pxx18_dp_rgb.c | 69
drivers/video/nexell_display.c | 658
10 files changed, 2609 insertions(+)
create mode 100644 drivers/video/nexell/Kconfig
create mode 100644 drivers/video/nexell/Makefile
create mode 100644 drivers/video/nexell/s5pxx18_dp.c
create mode 100644 drivers/video/nexell/s5pxx18_dp_hdmi.c
create mode 100644 drivers/video/nexell/s5pxx18_dp_lvds.c
create mode 100644 drivers/video/nexell/s5pxx18_dp_mipi.c
create mode 100644 drivers/video/nexell/s5pxx18_dp_rgb.c
create mode 100644 drivers/video/nexell_display.c
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 50ab365..dd224ab 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -563,6 +563,16 @@ source "drivers/video/bridge/Kconfig"
source "drivers/video/imx/Kconfig"
+config VIDEO_NX
+ bool "Enable video support on Nexell SoC"
+ depends on ARCH_S5P6818 || ARCH_S5P4418
+ help
+ Nexell SoC supports many video output options including eDP and
+ HDMI. This option enables this support which can be used on devices
+ which have an eDP display connected.
+
+source "drivers/video/nexell/Kconfig"
+
config VIDEO
bool "Enable legacy video support"
depends on !DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index df7119d..3bacc64 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -61,6 +61,7 @@ obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
+obj-$(CONFIG_VIDEO_NX) += nexell_display.o videomodes.o nexell/
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
obj-$(CONFIG_VIDEO_DSI_HOST_SANDBOX) += sandbox_dsi_host.o
obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
diff --git a/drivers/video/nexell/Kconfig b/drivers/video/nexell/Kconfig
new file mode 100644
index 000..54b8ccb
--- /dev/null
+++ b/drivers/video/nexell/Kconfig
@@ -0,0 +1,27 @@
+if VIDEO_NX
+
+menu "LCD select"
+
+config VIDEO_NX_RGB
+ bool "RGB LCD"
+ help
+ Support for RGB lcd output.
+
+config VIDEO_NX_LVDS
+ bool "LVDS LCD"
+ help
+ Support for LVDS lcd output.
+
+config VIDEO_NX_MIPI
+ bool "MiPi"
+ help
+ Support for MiPi lcd output.
+
+config VIDEO_NX_HDMI
+ bool "HDMI"
+ help
+ Support for hdmi output.
+
+endmenu
+
+endif
diff --git a/drivers/video/nexell/Makefile b/drivers/video/nexell/Makefile
new file mode 100644
index 000..111ab45
--- /dev/null
+++ b/drivers/video/nexell/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 Nexell
+# Junghyun, kim
+
+obj-$(CONFIG_VIDEO_NX) += s5pxx18_dp.o
+obj-$(CONFIG_VIDEO_NX) += soc/
+
+obj-$(CONFIG_VIDEO_NX_RGB) += s5pxx18_dp_rgb.o
+obj-$(CONFIG_VIDEO_NX_LVDS) += s5pxx18_dp_lvds.o
+obj-$(CONFIG_VIDEO_NX_MIPI) += s5pxx18_dp_mipi.o
+obj-$(CONFIG_VIDEO_NX_HDMI) += s5pxx18_dp_hdmi.o
diff --git a/drivers/video/nexell/s5pxx18_dp.c
b/drivers/video/nexell/s5pxx18_dp.c
new file mode 100644
index 000..c69b69c
--- /dev/null
+++ b/drivers/video/nexell/s5pxx18_dp.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "soc/s5pxx18_soc_disptop.h"
+#include "soc/s5pxx18_soc_dpc.h"
+#include "soc/s5pxx18_soc_mlc.h"
+
+#defineMLC_LAYER_RGB_0 0 /* number of RGB layer 0 */
+#defineMLC_LAYER_RGB_1 1 /* number of RGB layer 1 */
+#defineMLC_LAYER_VIDEO 3 /* number of Video layer: 3 =
VIDEO */
+
+#define__io_address(a) (void *)(uintptr_t)(a)
+
+void dp_control_init(int module)
+{
+ void *base;
+
+ /* top */
+ base = __io_address(nx_disp_top_get_physical_address());
+ nx_disp_top_set_base_address(base);
+
+ /* control */
+ base = __io_address(nx_dpc_get_physical_address(module));
+ nx_dpc_set_base_address(module, base);
+
+ /* top controller */
+ nx_rstcon_setrst(RESET_ID_DISP_TOP,
[RFC PATCH 07/10] video: add nexell video driver (soc: dpc, makefile)
Low level functions for DPC (Display Controller) and Makefile for all
nexell video low level functions.
Signed-off-by: Stefan Bosch
---
drivers/video/nexell/soc/Makefile | 11 +
drivers/video/nexell/soc/s5pxx18_soc_dpc.c | 1569
drivers/video/nexell/soc/s5pxx18_soc_dpc.h | 444
3 files changed, 2024 insertions(+)
create mode 100644 drivers/video/nexell/soc/Makefile
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_dpc.c
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_dpc.h
diff --git a/drivers/video/nexell/soc/Makefile
b/drivers/video/nexell/soc/Makefile
new file mode 100644
index 000..a3036e5
--- /dev/null
+++ b/drivers/video/nexell/soc/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 Nexell
+# Junghyun, kim
+
+obj-$(CONFIG_VIDEO_NX) += s5pxx18_soc_dpc.o s5pxx18_soc_mlc.o \
+ s5pxx18_soc_disptop.o s5pxx18_soc_disptop_clk.o
+
+obj-$(CONFIG_VIDEO_NX_LVDS) += s5pxx18_soc_lvds.o
+obj-$(CONFIG_VIDEO_NX_MIPI) += s5pxx18_soc_mipi.o
+obj-$(CONFIG_VIDEO_NX_HDMI) += s5pxx18_soc_hdmi.o
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_dpc.c
b/drivers/video/nexell/soc/s5pxx18_soc_dpc.c
new file mode 100644
index 000..fc15d6b
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_dpc.c
@@ -0,0 +1,1569 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim
+ */
+
+#include
+#include
+
+#include "s5pxx18_soc_dpc.h"
+
+static struct {
+ struct nx_dpc_register_set *pregister;
+} __g_module_variables[NUMBER_OF_DPC_MODULE] = { { NULL,},};
+
+int nx_dpc_initialize(void)
+{
+ static int binit;
+ u32 i;
+
+ if (binit == 0) {
+ for (i = 0; i < NUMBER_OF_DPC_MODULE; i++)
+ __g_module_variables[i].pregister = NULL;
+ binit = 1;
+ }
+ return 1;
+}
+
+u32 nx_dpc_get_number_of_module(void)
+{
+ return NUMBER_OF_DPC_MODULE;
+}
+
+u32 nx_dpc_get_physical_address(u32 module_index)
+{
+ const u32 physical_addr[] = PHY_BASEADDR_DPC_LIST;
+
+ return physical_addr[module_index];
+}
+
+void nx_dpc_set_base_address(u32 module_index, void *base_address)
+{
+ __g_module_variables[module_index].pregister =
+ (struct nx_dpc_register_set *)base_address;
+}
+
+void *nx_dpc_get_base_address(u32 module_index)
+{
+ return (void *)__g_module_variables[module_index].pregister;
+}
+
+void nx_dpc_set_interrupt_enable(u32 module_index, int32_t int_num, int enable)
+{
+ const u32 intenb_pos = 11;
+ const u32 intenb_mask = 1ul << intenb_pos;
+ const u32 intpend_pos = 10;
+ const u32 intpend_mask = 1ul << intpend_pos;
+
+ register u32 regvalue;
+ register struct nx_dpc_register_set *pregister;
+
+ pregister = __g_module_variables[module_index].pregister;
+ regvalue = pregister->dpcctrl0;
+ regvalue &= ~(intenb_mask | intpend_mask);
+ regvalue |= (u32)enable << intenb_pos;
+
+ writel(regvalue, >dpcctrl0);
+}
+
+int nx_dpc_get_interrupt_enable(u32 module_index, int32_t int_num)
+{
+ const u32 intenb_pos = 11;
+ const u32 intenb_mask = 1ul << intenb_pos;
+
+ return (int)((__g_module_variables[module_index].pregister->dpcctrl0 &
+ intenb_mask) >> intenb_pos);
+}
+
+void nx_dpc_set_interrupt_enable32(u32 module_index, u32 enable_flag)
+{
+ const u32 intenb_pos = 11;
+ const u32 intenb_mask = 1 << intenb_pos;
+ const u32 intpend_pos = 10;
+ const u32 intpend_mask = 1 << intpend_pos;
+
+ register struct nx_dpc_register_set *pregister;
+ register u32 read_value;
+
+ pregister = __g_module_variables[module_index].pregister;
+ read_value = pregister->dpcctrl0 & ~(intpend_mask | intenb_mask);
+
+ writel((u32)(read_value | (enable_flag & 0x01) << intenb_pos),
+ >dpcctrl0);
+}
+
+u32 nx_dpc_get_interrupt_enable32(u32 module_index)
+{
+ const u32 intenb_pos = 11;
+ const u32 intenb_mask = 1 << intenb_pos;
+
+ return (u32)((__g_module_variables[module_index].pregister->dpcctrl0 &
+ intenb_mask) >> intenb_pos);
+}
+
+int nx_dpc_get_interrupt_pending(u32 module_index, int32_t int_num)
+{
+ const u32 intpend_pos = 10;
+ const u32 intpend_mask = 1ul << intpend_pos;
+
+ return (int)((__g_module_variables[module_index].pregister->dpcctrl0 &
+ intpend_mask) >> intpend_pos);
+}
+
+u32 nx_dpc_get_interrupt_pending32(u32 module_index)
+{
+ const u32 intpend_pos = 10;
+ const u32 intpend_mask = 1 << intpend_pos;
+
+ return (u32)((__g_module_variables[module_index].pregister->dpcctrl0 &
+ intpend_mask) >> intpend_pos);
+}
+
+void nx_dpc_clear_interrupt_pending(u32 module_index, int32_t int_num)
+{
+ const u32 intpend_pos = 10;
+ register struct
[RFC PATCH 06/10] video: add nexell video driver (soc: lvds, hdmi)
Low level functions for LVDS and HDMI display interfaces.
Signed-off-by: Stefan Bosch
---
drivers/video/nexell/soc/s5pxx18_soc_hdmi.c | 50 +++
drivers/video/nexell/soc/s5pxx18_soc_hdmi.h | 488
drivers/video/nexell/soc/s5pxx18_soc_lvds.c | 278
drivers/video/nexell/soc/s5pxx18_soc_lvds.h | 83 +
4 files changed, 899 insertions(+)
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_hdmi.c
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_hdmi.h
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_lvds.c
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_lvds.h
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_hdmi.c
b/drivers/video/nexell/soc/s5pxx18_soc_hdmi.c
new file mode 100644
index 000..7b8be7e
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_hdmi.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim
+ */
+
+#include
+#include
+
+#include "s5pxx18_soc_hdmi.h"
+
+static u32 *hdmi_base_addr;
+
+u32 nx_hdmi_get_reg(u32 module_index, u32 offset)
+{
+ u32 *reg_addr;
+ u32 regvalue;
+
+ reg_addr = hdmi_base_addr + (offset / sizeof(u32));
+ regvalue = readl((u32 *)reg_addr);
+
+ return regvalue;
+}
+
+void nx_hdmi_set_reg(u32 module_index, u32 offset, u32 regvalue)
+{
+ s64 offset_new = (s64)((int32_t)offset);
+ u32 *reg_addr;
+
+ reg_addr = hdmi_base_addr + (offset_new / sizeof(u32));
+ writel(regvalue, (u32 *)reg_addr);
+}
+
+void nx_hdmi_set_base_address(u32 module_index, void *base_address)
+{
+ hdmi_base_addr = (u32 *)base_address;
+}
+
+void *nx_hdmi_get_base_address(u32 module_index)
+{
+ return (u32 *)hdmi_base_addr;
+}
+
+u32 nx_hdmi_get_physical_address(u32 module_index)
+{
+ const u32 physical_addr[] = PHY_BASEADDR_HDMI_LIST;
+
+ return physical_addr[module_index];
+}
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_hdmi.h
b/drivers/video/nexell/soc/s5pxx18_soc_hdmi.h
new file mode 100644
index 000..a4c5ab5
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_hdmi.h
@@ -0,0 +1,488 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2016 Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim
+ */
+
+#ifndef _S5PXX18_SOC_HDMI_H_
+#define _S5PXX18_SOC_HDMI_H_
+
+#include "s5pxx18_soc_disptop.h"
+
+#define PHY_BASEADDR_HDMI_PHY_MODULE 0xc00f
+#define PHY_BASEADDR_HDMI_LIST \
+ { PHY_BASEADDR_HDMI_MODULE }
+
+#define HDMI_LINK_INTC_CON_0 (HDMI_ADDR_OFFSET + 0x)
+#define HDMI_LINK_INTC_FLAG_0 (HDMI_ADDR_OFFSET + 0x0004)
+#define HDMI_LINK_AESKEY_VALID (HDMI_ADDR_OFFSET + 0x0008)
+#define HDMI_LINK_HPD (HDMI_ADDR_OFFSET + 0x000C)
+#define HDMI_LINK_INTC_CON_1 (HDMI_ADDR_OFFSET + 0x0010)
+#define HDMI_LINK_INTC_FLAG_1 (HDMI_ADDR_OFFSET + 0x0014)
+#define HDMI_LINK_PHY_STATUS_0 (HDMI_ADDR_OFFSET + 0x0020)
+#define HDMI_LINK_PHY_STATUS_CMU (HDMI_ADDR_OFFSET + 0x0024)
+#define HDMI_LINK_PHY_STATUS_PLL (HDMI_ADDR_OFFSET + 0x0028)
+#define HDMI_LINK_PHY_CON_0(HDMI_ADDR_OFFSET + 0x0030)
+#define HDMI_LINK_HPD_CTRL (HDMI_ADDR_OFFSET + 0x0040)
+#define HDMI_LINK_HPD_STATUS (HDMI_ADDR_OFFSET + 0x0044)
+#define HDMI_LINK_HPD_TH_x (HDMI_ADDR_OFFSET + 0x0050)
+
+#define HDMI_LINK_HDMI_CON_0 (HDMI_ADDR_OFFSET + 0x0001)
+#define HDMI_LINK_HDMI_CON_1 (HDMI_ADDR_OFFSET + 0x00010004)
+#define HDMI_LINK_HDMI_CON_2 (HDMI_ADDR_OFFSET + 0x00010008)
+#define HDMI_LINK_STATUS (HDMI_ADDR_OFFSET + 0x00010010)
+#define HDMI_LINK_STATUS_EN(HDMI_ADDR_OFFSET + 0x00010020)
+
+#define HDMI_LINK_HDCP_SHA1_REN0 (HDMI_ADDR_OFFSET + 0x00010024)
+#define HDMI_LINK_HDCP_SHA1_REN1 (HDMI_ADDR_OFFSET + 0x00010028)
+
+#define HDMI_LINK_MODE_SEL (HDMI_ADDR_OFFSET + 0x00010040)
+#define HDMI_LINK_ENC_EN (HDMI_ADDR_OFFSET + 0x00010044)
+#define HDMI_LINK_HDMI_YMAX(HDMI_ADDR_OFFSET + 0x00010060)
+#define HDMI_LINK_HDMI_YMIN(HDMI_ADDR_OFFSET + 0x00010064)
+#define HDMI_LINK_HDMI_CMAX(HDMI_ADDR_OFFSET + 0x00010068)
+#define HDMI_LINK_HDMI_CMIN(HDMI_ADDR_OFFSET + 0x0001006C)
+#define HDMI_LINK_H_BLANK_0(HDMI_ADDR_OFFSET + 0x000100A0)
+#define HDMI_LINK_H_BLANK_1(HDMI_ADDR_OFFSET + 0x000100A4)
+#define HDMI_LINK_V2_BLANK_0 (HDMI_ADDR_OFFSET + 0x000100B0)
+#define HDMI_LINK_V2_BLANK_1 (HDMI_ADDR_OFFSET + 0x000100B4)
+#define HDMI_LINK_V1_BLANK_0 (HDMI_ADDR_OFFSET + 0x000100B8)
+#define HDMI_LINK_V1_BLANK_1 (HDMI_ADDR_OFFSET + 0x000100BC)
+#define HDMI_LINK_V_LINE_0
[RFC PATCH 05/10] video: add nexell video driver (soc: mlc, mipi)
Low level functions for MLC (Multi Layer Control) and MIPI (Mobile
Industry Processor Interface).
Signed-off-by: Stefan Bosch
---
drivers/video/nexell/soc/s5pxx18_soc_mipi.c | 580 +
drivers/video/nexell/soc/s5pxx18_soc_mipi.h | 291 +
drivers/video/nexell/soc/s5pxx18_soc_mlc.c | 1861 +++
drivers/video/nexell/soc/s5pxx18_soc_mlc.h | 429 ++
4 files changed, 3161 insertions(+)
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_mipi.c
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_mipi.h
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_mlc.c
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_mlc.h
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_mipi.c
b/drivers/video/nexell/soc/s5pxx18_soc_mipi.c
new file mode 100644
index 000..1000ddb
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_mipi.c
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim
+ */
+
+#include
+#include
+
+#include "s5pxx18_soc_disptop.h"
+#include "s5pxx18_soc_mipi.h"
+
+static struct nx_mipi_register_set *__g_pregister[NUMBER_OF_MIPI_MODULE];
+
+int nx_mipi_smoke_test(u32 module_index)
+{
+ register struct nx_mipi_register_set *pregister;
+
+ pregister = __g_pregister[module_index];
+
+ if (pregister->csis_config_ch0 != 0x00FC)
+ return false;
+
+ if (pregister->dsim_intmsk != 0xB337)
+ return false;
+
+ writel(0xDEADC0DE, >csis_dphyctrl);
+ writel(0x, >csis_ctrl2);
+ writel(0xDEADC0DE, >dsim_msync);
+
+ if (pregister->csis_dphyctrl != 0xDE80001E)
+ return false;
+
+ if ((pregister->csis_ctrl2 & (~1)) != 0xEEE00010)
+ return false;
+
+ if (pregister->dsim_msync != 0xDE80C0DE)
+ return false;
+
+ return true;
+}
+
+void nx_mipi_set_base_address(u32 module_index, void *base_address)
+{
+ __g_pregister[module_index] =
+ (struct nx_mipi_register_set *)base_address;
+}
+
+void *nx_mipi_get_base_address(u32 module_index)
+{
+ return (void *)__g_pregister[module_index];
+}
+
+u32 nx_mipi_get_physical_address(u32 module_index)
+{
+ const u32 physical_addr[] = PHY_BASEADDR_MIPI_LIST;
+
+ return physical_addr[module_index];
+}
+
+#define __nx_mipi_valid_dsi_intmask__ \
+ (~((1 << 26) | (1 << 23) | (1 << 22) | (1 << 19)))
+
+void nx_mipi_set_interrupt_enable(u32 module_index, u32 int_num, int enable)
+{
+ register struct nx_mipi_register_set *pregister;
+ register u32 regvalue;
+
+ pregister = __g_pregister[module_index];
+ if (int_num < 32) {
+ regvalue = pregister->csis_intmsk;
+ regvalue &= ~(1ul << int_num);
+ regvalue |= (u32)enable << int_num;
+ writel(regvalue, >csis_intmsk);
+ } else {
+ regvalue = pregister->dsim_intmsk;
+ regvalue &= ~(1ul << (int_num - 32));
+ regvalue |= (u32)enable << (int_num - 32);
+ writel(regvalue, >dsim_intmsk);
+ }
+}
+
+int nx_mipi_get_interrupt_enable(u32 module_index, u32 int_num)
+{
+ if (int_num < 32)
+ return (int)((__g_pregister[module_index]->csis_intmsk >>
+ int_num) & 0x01);
+ else
+ return (int)((__g_pregister[module_index]->dsim_intmsk >>
+ (int_num - 32)) & 0x01);
+}
+
+int nx_mipi_get_interrupt_pending(u32 module_index, u32 int_num)
+{
+ register struct nx_mipi_register_set *pregister;
+ register u32 regvalue;
+ int ret;
+
+ pregister = __g_pregister[module_index];
+ if (int_num < 32) {
+ regvalue = pregister->csis_intmsk;
+ regvalue &= pregister->csis_intsrc;
+ ret = (int)((regvalue >> int_num) & 0x01);
+ } else {
+ regvalue = pregister->dsim_intmsk;
+ regvalue &= pregister->dsim_intsrc;
+ ret = (int)((regvalue >> (int_num - 32)) & 0x01);
+ }
+
+ return ret;
+}
+
+void nx_mipi_clear_interrupt_pending(u32 module_index, u32 int_num)
+{
+ register struct nx_mipi_register_set *pregister;
+
+ pregister = __g_pregister[module_index];
+ if (int_num < 32)
+ writel(1ul << int_num, >csis_intsrc);
+ else
+ writel(1ul << (int_num - 32), >dsim_intsrc);
+}
+
+void nx_mipi_set_interrupt_enable_all(u32 module_index, int enable)
+{
+ register struct nx_mipi_register_set *pregister;
+
+ pregister = __g_pregister[module_index];
+ if (enable)
+ writel(__nx_mipi_valid_dsi_intmask__, >dsim_intmsk);
+ else
+ writel(0, >dsim_intmsk);
+}
+
+int nx_mipi_get_interrupt_enable_all(u32 module_index)
+{
+ if (__g_pregister[module_index]->csis_intmsk)
+ return true;
+
+ if
[RFC PATCH 04/10] video: add nexell video driver (soc: displaytop)
Low level functions for DisplayTop (Display Topology).
Signed-off-by: Stefan Bosch
---
drivers/video/nexell/soc/s5pxx18_soc_disptop.c | 185 ++
drivers/video/nexell/soc/s5pxx18_soc_disptop.h | 385 +
drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.c | 309 +
drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.h | 59
drivers/video/nexell/soc/s5pxx18_soc_disptype.h| 23 ++
5 files changed, 961 insertions(+)
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_disptop.c
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_disptop.h
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.c
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.h
create mode 100644 drivers/video/nexell/soc/s5pxx18_soc_disptype.h
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_disptop.c
b/drivers/video/nexell/soc/s5pxx18_soc_disptop.c
new file mode 100644
index 000..626e53a
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_disptop.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim
+ */
+
+#include
+#include
+
+#include "s5pxx18_soc_disptop.h"
+
+static struct {
+ struct nx_disp_top_register_set *pregister;
+} __g_module_variables = { NULL, };
+
+int nx_disp_top_initialize(void)
+{
+ static int binit;
+ u32 i;
+
+ if (binit == 0) {
+ for (i = 0; i < NUMBER_OF_DISPTOP_MODULE; i++)
+ __g_module_variables.pregister = NULL;
+ binit = 1;
+ }
+ return 1;
+}
+
+u32 nx_disp_top_get_number_of_module(void)
+{
+ return NUMBER_OF_DISPTOP_MODULE;
+}
+
+u32 nx_disp_top_get_physical_address(void)
+{
+ static const u32 physical_addr[] = PHY_BASEADDR_DISPTOP_LIST;
+
+ return (u32)(physical_addr[0] + PHY_BASEADDR_DISPLAYTOP_MODULE_OFFSET);
+}
+
+u32 nx_disp_top_get_size_of_register_set(void)
+{
+ return sizeof(struct nx_disp_top_register_set);
+}
+
+void nx_disp_top_set_base_address(void *base_address)
+{
+ __g_module_variables.pregister =
+ (struct nx_disp_top_register_set *)base_address;
+}
+
+void *nx_disp_top_get_base_address(void)
+{
+ return (void *)__g_module_variables.pregister;
+}
+
+void nx_disp_top_set_resconvmux(int benb, u32 sel)
+{
+ register struct nx_disp_top_register_set *pregister;
+ u32 regvalue;
+
+ pregister = __g_module_variables.pregister;
+ regvalue = (benb << 31) | (sel << 0);
+ writel((u32)regvalue, >resconv_mux_ctrl);
+}
+
+void nx_disp_top_set_hdmimux(int benb, u32 sel)
+{
+ register struct nx_disp_top_register_set *pregister;
+ u32 regvalue;
+
+ pregister = __g_module_variables.pregister;
+ regvalue = (benb << 31) | (sel << 0);
+ writel((u32)regvalue, >interconv_mux_ctrl);
+}
+
+void nx_disp_top_set_mipimux(int benb, u32 sel)
+{
+ register struct nx_disp_top_register_set *pregister;
+ u32 regvalue;
+
+ pregister = __g_module_variables.pregister;
+ regvalue = (benb << 31) | (sel << 0);
+ writel((u32)regvalue, >mipi_mux_ctrl);
+}
+
+void nx_disp_top_set_lvdsmux(int benb, u32 sel)
+{
+ register struct nx_disp_top_register_set *pregister;
+ u32 regvalue;
+
+ pregister = __g_module_variables.pregister;
+ regvalue = (benb << 31) | (sel << 0);
+ writel((u32)regvalue, >lvds_mux_ctrl);
+}
+
+void nx_disp_top_set_primary_mux(u32 sel)
+{
+ register struct nx_disp_top_register_set *pregister;
+
+ pregister = __g_module_variables.pregister;
+ writel((u32)sel, >tftmpu_mux);
+}
+
+void nx_disp_top_hdmi_set_vsync_start(u32 sel)
+{
+ register struct nx_disp_top_register_set *pregister;
+
+ pregister = __g_module_variables.pregister;
+ writel((u32)sel, >hdmisyncctrl0);
+}
+
+void nx_disp_top_hdmi_set_vsync_hsstart_end(u32 start, u32 end)
+{
+ register struct nx_disp_top_register_set *pregister;
+
+ pregister = __g_module_variables.pregister;
+ writel((u32)(end << 16) | (start << 0), >hdmisyncctrl3);
+}
+
+void nx_disp_top_hdmi_set_hactive_start(u32 sel)
+{
+ register struct nx_disp_top_register_set *pregister;
+
+ pregister = __g_module_variables.pregister;
+ writel((u32)sel, >hdmisyncctrl1);
+}
+
+void nx_disp_top_hdmi_set_hactive_end(u32 sel)
+{
+ register struct nx_disp_top_register_set *pregister;
+
+ pregister = __g_module_variables.pregister;
+ writel((u32)sel, >hdmisyncctrl2);
+}
+
+void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
+ u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr,
+ u32 field_use, u32 muxsel)
+{
+ register struct nx_disp_top_register_set *pregister;
+ u32 regvalue;
+
+ pregister = __g_module_variables.pregister;
+ regvalue = ((enable & 0x01) << 0) | ((init_val & 0x01) << 1) |
+
[RFC PATCH 03/10] i2c: mmc: add nexell driver (gpio, i2c, mmc, pwm)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- i2c/nx_i2c.c: Some adaptions mainly because of changes in
"struct udevice".
- mmc: nexell_dw_mmc.c changed to nexell_dw_mmc_dm.c (switched to DM).
Signed-off-by: Stefan Bosch
---
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/nx_gpio.c | 252 +++
drivers/i2c/Kconfig| 9 +
drivers/i2c/Makefile | 1 +
drivers/i2c/nx_i2c.c | 537 +
drivers/mmc/Kconfig| 6 +
drivers/mmc/Makefile | 1 +
drivers/mmc/nexell_dw_mmc_dm.c | 350 +++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-nexell.c | 252 +++
drivers/pwm/pwm-nexell.h | 54 +
12 files changed, 1473 insertions(+)
create mode 100644 drivers/gpio/nx_gpio.c
create mode 100644 drivers/i2c/nx_i2c.c
create mode 100644 drivers/mmc/nexell_dw_mmc_dm.c
create mode 100644 drivers/pwm/pwm-nexell.c
create mode 100644 drivers/pwm/pwm-nexell.h
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 1de6f52..febda89 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -421,4 +421,13 @@ config MT7621_GPIO
help
Say yes here to support MediaTek MT7621 compatible GPIOs.
+config NX_GPIO
+ bool "Nexell GPIO driver"
+ depends on DM_GPIO
+ help
+ Support GPIO access on Nexell SoCs. The GPIOs are arranged into
+ a number of banks (different for each SoC type) each with 32 GPIOs.
+ The GPIOs for a device are defined in the device tree with one node
+ for each bank.
+
endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 449046b..e3340de 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
+obj-$(CONFIG_NX_GPIO) += nx_gpio.o
diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c
new file mode 100644
index 000..86472f6
--- /dev/null
+++ b/drivers/gpio/nx_gpio.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Nexell
+ * DeokJin, Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct nx_gpio_regs {
+ u32 data; /* Data register */
+ u32 outputenb; /* Output Enable register */
+ u32 detmode[2]; /* Detect Mode Register */
+ u32 intenb; /* Interrupt Enable Register */
+ u32 det;/* Event Detect Register */
+ u32 pad;/* Pad Status Register */
+};
+
+struct nx_alive_gpio_regs {
+ u32 pwrgate;/* Power Gating Register */
+ u32 reserved0[28]; /* Reserved0 */
+ u32 outputenb_reset;/* Alive GPIO Output Enable Reset Register */
+ u32 outputenb; /* Alive GPIO Output Enable Register */
+ u32 outputenb_read; /* Alive GPIO Output Read Register */
+ u32 reserved1[3]; /* Reserved1 */
+ u32 pad_reset; /* Alive GPIO Output Reset Register */
+ u32 data; /* Alive GPIO Output Register */
+ u32 pad_read; /* Alive GPIO Pad Read Register */
+ u32 reserved2[33]; /* Reserved2 */
+ u32 pad;/* Alive GPIO Input Value Register */
+};
+
+struct nx_gpio_platdata {
+ void *regs;
+ int gpio_count;
+ const char *bank_name;
+};
+
+static int nx_alive_gpio_is_check(struct udevice *dev)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ const char *bank_name = plat->bank_name;
+
+ if (!strcmp(bank_name, "gpio_alv"))
+ return 1;
+
+ return 0;
+}
+
+static int nx_alive_gpio_direction_input(struct udevice *dev, unsigned int pin)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+
+ setbits_le32(>outputenb_reset, 1 << pin);
+
+ return 0;
+}
+
+static int nx_alive_gpio_direction_output(struct udevice *dev, unsigned int
pin,
+ int val)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+
+ if (val)
+ setbits_le32(>data, 1 << pin);
+ else
+ setbits_le32(>pad_reset, 1 << pin);
+
+ setbits_le32(>outputenb, 1 << pin);
+
+ return 0;
+}
+
+static int nx_alive_gpio_get_value(struct udevice *dev, unsigned int pin)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+ unsigned int mask = 1UL << pin;
+ unsigned int value;
+
+
[RFC PATCH 02/10] arm: add mach-nexell (all files except header files)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- SPL not supported yet --> no spl-directory in arch/arm/mach-nexell.
Appropriate line in Makefile removed.
- clock.c: 'section(".data")' added to declaration of clk_periphs[] and
core_hz.
- Kconfig: Changes to have a structure like in mach-bcm283x/Kconfig,
e.g. "config ..." entries moved from other Kconfig.
- timer.c: 'section(".data")' added to declaration of timestamp and
lastdec.
Signed-off-by: Stefan Bosch
---
arch/arm/Kconfig | 7 +
arch/arm/Makefile | 1 +
arch/arm/mach-nexell/Kconfig | 67 +++
arch/arm/mach-nexell/Makefile | 15 +
arch/arm/mach-nexell/clock.c | 869 ++
arch/arm/mach-nexell/cmd_boot_linux.c | 145 ++
arch/arm/mach-nexell/config.mk| 11 +
arch/arm/mach-nexell/nx_gpio.c| 352 ++
arch/arm/mach-nexell/nx_sec_reg.c | 82
arch/arm/mach-nexell/reg-call.S | 23 +
arch/arm/mach-nexell/reset.c | 33 ++
arch/arm/mach-nexell/serial.c | 262 ++
arch/arm/mach-nexell/tieoff.c | 109 +
arch/arm/mach-nexell/timer.c | 297
14 files changed, 2273 insertions(+)
create mode 100644 arch/arm/mach-nexell/Kconfig
create mode 100644 arch/arm/mach-nexell/Makefile
create mode 100644 arch/arm/mach-nexell/clock.c
create mode 100644 arch/arm/mach-nexell/cmd_boot_linux.c
create mode 100644 arch/arm/mach-nexell/config.mk
create mode 100644 arch/arm/mach-nexell/nx_gpio.c
create mode 100644 arch/arm/mach-nexell/nx_sec_reg.c
create mode 100644 arch/arm/mach-nexell/reg-call.S
create mode 100644 arch/arm/mach-nexell/reset.c
create mode 100644 arch/arm/mach-nexell/serial.c
create mode 100644 arch/arm/mach-nexell/tieoff.c
create mode 100644 arch/arm/mach-nexell/timer.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a623ef5..469aa65 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -875,6 +875,11 @@ config ARCH_MX5
select CPU_V7A
imply MXC_GPIO
+config ARCH_NEXELL
+ bool "Nexell S5P4418/S5P6818 SoC"
+ select ENABLE_ARM_SOC_BOOT0_HOOK
+ select DM
+
config ARCH_OWL
bool "Actions Semi OWL SoCs"
select ARM64
@@ -1797,6 +1802,8 @@ source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/mach-imx/Kconfig"
+source "arch/arm/mach-nexell/Kconfig"
+
source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1e60a9f..5a390b8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -67,6 +67,7 @@ machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
+machine-$(CONFIG_ARCH_NEXELL) += nexell
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_OWL) += owl
diff --git a/arch/arm/mach-nexell/Kconfig b/arch/arm/mach-nexell/Kconfig
new file mode 100644
index 000..5368909
--- /dev/null
+++ b/arch/arm/mach-nexell/Kconfig
@@ -0,0 +1,67 @@
+if ARCH_NEXELL
+
+config NEXELL_COMMON
+ bool "Nexell common options"
+
+config NEXELL_ARMV7_COMMON
+ bool "Nexell 32-bit common options"
+ select CPU_V7A
+ select NEXELL_COMMON
+ #select SUPPORT_SPL
+
+config NEXELL_ARMV8_COMMON
+ bool "Nexell 64-bit common options"
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select NEXELL_COMMON
+
+config ARCH_S5P4418
+ bool "Nexell S5P4418 SoC"
+ select NEXELL_ARMV7_COMMON
+ select OF_CONTROL
+ select OF_SEPARATE
+ select NX_GPIO
+ select PL011_SERIAL
+ select PL011_SERIAL_FLUSH_ON_INIT
+
+config ARCH_S5P6818
+ bool "Nexell S5P6818 SoC"
+ select NEXELL_ARMV8_COMMON
+
+menu "Nexell S5P4418/S5P6818"
+ #depends on ARCH_S5P4418
+ depends on ARCH_NEXELL
+
+choice
+ prompt "Nexell S5P4418/S5P6818 board select"
+ optional
+
+config TARGET_NANOPI2
+ bool "FriendlyARM NanoPi2 Board"
+ select ARCH_S5P4418
+
+endchoice
+
+config SYS_BOARD
+ default "nanopi2"
+
+config SYS_VENDOR
+ default "friendlyarm"
+
+config SYS_SOC
+ default "nexell"
+
+config SYS_CONFIG_NAME
+ default "s5p4418_nanopi2"
+
+endmenu
+
+config SYS_PLLFIN
+ int
+
+config TIMER_SYS_TICK_CH
+ int
+
+source "board/friendlyarm/Kconfig"
+
+endif
diff --git a/arch/arm/mach-nexell/Makefile b/arch/arm/mach-nexell/Makefile
new file mode 100644
index 000..e144196
--- /dev/null
+++ b/arch/arm/mach-nexell/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 Nexell
+# Hyunseok, Jung
+
+obj-y += clock.o
+obj-y += timer.o
+obj-y
[RFC PATCH 01/10] arm: add mach-nexell (header files)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- DM_VIDEO support (display_dev.h).
- boot0.h added, handles NSIH --> tools/nexell obsolete.
- gpio.h: Include-path to errno.h changed.
Signed-off-by: Stefan Bosch
---
arch/arm/mach-nexell/include/mach/boot0.h| 40 +++
arch/arm/mach-nexell/include/mach/clk.h | 24 ++
arch/arm/mach-nexell/include/mach/display.h | 273 +++
arch/arm/mach-nexell/include/mach/display_dev.h | 37 ++
arch/arm/mach-nexell/include/mach/ehci.h | 106 ++
arch/arm/mach-nexell/include/mach/gpio.h | 17 +
arch/arm/mach-nexell/include/mach/mipi_display.h | 219
arch/arm/mach-nexell/include/mach/nexell.h | 352 +++
arch/arm/mach-nexell/include/mach/nx_gpio.h | 103 ++
arch/arm/mach-nexell/include/mach/reset.h| 19 +
arch/arm/mach-nexell/include/mach/sec_reg.h | 15 +
arch/arm/mach-nexell/include/mach/tieoff.h | 423 +++
12 files changed, 1628 insertions(+)
create mode 100644 arch/arm/mach-nexell/include/mach/boot0.h
create mode 100644 arch/arm/mach-nexell/include/mach/clk.h
create mode 100644 arch/arm/mach-nexell/include/mach/display.h
create mode 100644 arch/arm/mach-nexell/include/mach/display_dev.h
create mode 100644 arch/arm/mach-nexell/include/mach/ehci.h
create mode 100644 arch/arm/mach-nexell/include/mach/gpio.h
create mode 100644 arch/arm/mach-nexell/include/mach/mipi_display.h
create mode 100644 arch/arm/mach-nexell/include/mach/nexell.h
create mode 100644 arch/arm/mach-nexell/include/mach/nx_gpio.h
create mode 100644 arch/arm/mach-nexell/include/mach/reset.h
create mode 100644 arch/arm/mach-nexell/include/mach/sec_reg.h
create mode 100644 arch/arm/mach-nexell/include/mach/tieoff.h
diff --git a/arch/arm/mach-nexell/include/mach/boot0.h
b/arch/arm/mach-nexell/include/mach/boot0.h
new file mode 100644
index 000..e05c07e
--- /dev/null
+++ b/arch/arm/mach-nexell/include/mach/boot0.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NSIH (Nexell System Information Header) for FriendlyArm nanopi2 board
+ *
+ * The NSIH (first 512 Bytes of u-boot.bin) is necessary for the
+ * 2nd-Bootloader to get information like load address of U-Boot.
+ *
+ * 0x400 must be added to CONFIG_SYS_TEXT_BASE to have the actual load and
+ * start address because 2nd-Bootloader loads with an offset of 0x400
+ * (NSIH + 0x200 bytes are not loaded into RAM).
+ *
+ * It has been tested / is working with the following 2nd-Bootloader:
+ * "BL1 by Nexell V1.0.0-gd551e13 [Built on 2018-01-25 16:58:29]"
+ *
+ * (C) Copyright 2020 Stefan Bosch
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+ ARM_VECTORS
+ .space 0x30
+ .word (_end - _start) + 20 * 1024 /* 0x50: load size
+* (bin + 20k for DTB) */
+ .space 0x4
+ .word CONFIG_SYS_TEXT_BASE + 0x400/* 0x58: load address */
+ .word 0x
+ .word CONFIG_SYS_TEXT_BASE + 0x400/* 0x60: start address */
+ .space 0x198
+ .byte 'N' /* 0x1FC: "NSIH" signature */
+ .byte 'S'
+ .byte 'I'
+ .byte 'H'
+
+ /* The NSIH + 0x200 bytes are omitted by the 2nd-Bootloader */
+ .space 0x200
+_start:
+ ARM_VECTORS
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/mach-nexell/include/mach/clk.h
b/arch/arm/mach-nexell/include/mach/clk.h
new file mode 100644
index 000..cc5589a
--- /dev/null
+++ b/arch/arm/mach-nexell/include/mach/clk.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * (C) Copyright 2016 Nexell
+ * Hyunseok, Jung
+ */
+
+#ifndef __ASM_ARM_ARCH_CLK_H_
+#define __ASM_ARM_ARCH_CLK_H_
+
+struct clk {
+ unsigned long rate;
+};
+
+void clk_init(void);
+
+struct clk *clk_get(const char *id);
+void clk_put(struct clk *clk);
+unsigned long clk_get_rate(struct clk *clk);
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_rate(struct clk *clk, unsigned long rate);
+int clk_enable(struct clk *clk);
+void clk_disable(struct clk *clk);
+
+#endif
diff --git a/arch/arm/mach-nexell/include/mach/display.h
b/arch/arm/mach-nexell/include/mach/display.h
new file mode 100644
index 000..b167e63
--- /dev/null
+++ b/arch/arm/mach-nexell/include/mach/display.h
@@ -0,0 +1,273 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2016 Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim
+ */
+
+#ifndef _NX__DISPLAY_H_
+#define _NX__DISPLAY_H_
+
+#defineDP_PLANS_NUM3
+
+/* the display output format. */
+#defineDPC_FORMAT_RGB555 0 /* RGB555 Format */
+#defineDPC_FORMAT_RGB565 1 /* RGB565 Format */
+#defineDPC_FORMAT_RGB666 2 /* RGB666 Format */
+#defineDPC_FORMAT_RGB888 3 /* RGB888 Format */
+#defineDPC_FORMAT_MRGB555A 4 /* MRGB555A Format
