Re: [PATCH 1/1] efi_loader: definition of GetNextVariableName()
On Sun, Mar 22, 2020 at 06:35:34PM +0100, Heinrich Schuchardt wrote:
> 'vendor' is both an input and an output parameter. So it cannot be
> constant.
The same fix must be applied to parse_uboot_variable().
-Takahiro Akashi
> Fixes: 0bda81bfdc5c ("efi_loader: use const efi_guid_t * for variable
> services")
> Signed-off-by: Heinrich Schuchardt
> ---
> include/efi_api.h | 2 +-
> include/efi_loader.h | 2 +-
> lib/efi_loader/efi_variable.c | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/efi_api.h b/include/efi_api.h
> index 4713da2e1d..1c40ffc4f5 100644
> --- a/include/efi_api.h
> +++ b/include/efi_api.h
> @@ -272,7 +272,7 @@ struct efi_runtime_services {
> efi_uintn_t *data_size, void *data);
> efi_status_t (EFIAPI *get_next_variable_name)(
> efi_uintn_t *variable_name_size,
> - u16 *variable_name, const efi_guid_t *vendor);
> + u16 *variable_name, efi_guid_t *vendor);
> efi_status_t (EFIAPI *set_variable)(u16 *variable_name,
> const efi_guid_t *vendor,
> u32 attributes,
> diff --git a/include/efi_loader.h b/include/efi_loader.h
> index 37c3f15da1..3f2792892f 100644
> --- a/include/efi_loader.h
> +++ b/include/efi_loader.h
> @@ -645,7 +645,7 @@ efi_status_t EFIAPI efi_get_variable(u16 *variable_name,
>efi_uintn_t *data_size, void *data);
> efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t
> *variable_name_size,
> u16 *variable_name,
> -const efi_guid_t *vendor);
> +efi_guid_t *vendor);
> efi_status_t EFIAPI efi_set_variable(u16 *variable_name,
>const efi_guid_t *vendor, u32 attributes,
>efi_uintn_t data_size, const void *data);
> diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> index 3bec2d0d17..fe2f264591 100644
> --- a/lib/efi_loader/efi_variable.c
> +++ b/lib/efi_loader/efi_variable.c
> @@ -330,7 +330,7 @@ static efi_status_t parse_uboot_variable(char *variable,
> */
> efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t
> *variable_name_size,
> u16 *variable_name,
> -const efi_guid_t *vendor)
> +efi_guid_t *vendor)
> {
> char *native_name, *variable;
> ssize_t name_len, list_len;
> @@ -598,7 +598,7 @@ efi_get_variable_runtime(u16 *variable_name, const
> efi_guid_t *vendor,
> */
> static efi_status_t __efi_runtime EFIAPI
> efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size,
> -u16 *variable_name, const efi_guid_t *vendor)
> +u16 *variable_name, efi_guid_t *vendor)
> {
> return EFI_UNSUPPORTED;
> }
> --
> 2.25.1
>
Re: [PATCH v7 04/22] clk: Fix clk_get_by_* handling of index
Hi Jagan > clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean > predicate instead of the index. Other clk_get_by_* functions got the clock > correctly, but passed a predicate instead of the index to clk_get_by_tail. > This could lead to confusing error messages. > > Signed-off-by: Sean Anderson > --- > > Changes in v7: > - New > > drivers/clk/clk-uclass.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c > index aa8dd9d027..c082fe95ff 100644 > --- a/drivers/clk/clk-uclass.c > +++ b/drivers/clk/clk-uclass.c Do you have any suggestions about this patch ? Thanks Rick > @@ -121,7 +121,7 @@ static int clk_get_by_indexed_prop(struct udevice *dev, > const char *prop_name, > > > return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks", > -index > 0, clk); > +index, clk); > } > > int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) > @@ -133,7 +133,7 @@ int clk_get_by_index(struct udevice *dev, int index, > struct clk *clk) > index, &args); > > return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks", > -index > 0, clk); > +index, clk); > } > > int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk) > @@ -142,10 +142,10 @@ int clk_get_by_index_nodev(ofnode node, int index, > struct clk *clk) > int ret; > > ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", > 0, > -index > 0, &args); > +index, &args); > > return clk_get_by_index_tail(ret, node, &args, "clocks", > -index > 0, clk); > +index, clk); > } > > int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) > -- > 2.25.1 >
Re: [PATCH 2/2] efi_selftest: check length report by GetNextVariableName()
On Fri, Mar 20, 2020 at 07:28:20PM +0100, Heinrich Schuchardt wrote:
> GetNextVariableName should report the length of the variable including the
> final 0x in bytes.
>
> Check this in the unit test.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/efi_selftest/efi_selftest_variables.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/lib/efi_selftest/efi_selftest_variables.c
> b/lib/efi_selftest/efi_selftest_variables.c
> index 5d98c029b8..b7ead340f5 100644
> --- a/lib/efi_selftest/efi_selftest_variables.c
> +++ b/lib/efi_selftest/efi_selftest_variables.c
> @@ -155,8 +155,14 @@ static int execute(void)
> return EFI_ST_FAILURE;
> }
> if (!memcmp(&guid, &guid_vendor0, sizeof(efi_guid_t)) &&
> - !efi_st_strcmp_16_8(varname, "efi_st_var0"))
> + !efi_st_strcmp_16_8(varname, "efi_st_var0")) {
> flag |= 1;
> + if (len != 24) {
> + efi_st_error("GetNextVariableName report wrong
> length %u, expected 24\n",
> + (unsigned int)len);
> + return EFI_ST_FAILURE;
> + }
> + }
> if (!memcmp(&guid, &guid_vendor1, sizeof(efi_guid_t)) &&
> !efi_st_strcmp_16_8(varname, "efi_st_var1"))
Logically, length check should be added here, too.
-Takahiro Akashi
> flag |= 2;
> --
> 2.25.1
>
Re: [PATCH 1/2] efi_loader: correct reported length in GetNextVariable()
On Fri, Mar 20, 2020 at 07:28:19PM +0100, Heinrich Schuchardt wrote:
> The runtime service GetNextVariable() returns the length of the next
> variable including the closing 0x. This length should be in bytes.
>
> Comparing the output of EDK2 and U-Boot shows that this is currently not
> correctly implemented:
>
> EDK2:
> OsIndicationsSupported: 46
> PlatformLang: 26
> PlatformLangCodes: 36
>
> U-Boot:
> OsIndicationsSupported: 23
> PlatformLang: 13
> PlatformLangCodes: 18
>
> Provide correct length in GetNextVariable().
Please also correct a function description of GetNextVariable().
-Takahiro Akashi
> Fixes: d99a87f84b75 ("efi_loader: implement GetNextVariableName()")
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/efi_loader/efi_variable.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> index c316bdfec0..04ead34c6f 100644
> --- a/lib/efi_loader/efi_variable.c
> +++ b/lib/efi_loader/efi_variable.c
> @@ -299,7 +299,7 @@ static efi_status_t parse_uboot_variable(char *variable,
> p = variable_name;
> utf8_utf16_strncpy(&p, name, name_len);
> variable_name[name_len] = 0;
> - *variable_name_size = name_len + 1;
> + *variable_name_size = sizeof(u16) * (name_len + 1);
>
> /* guid */
> c = *(name - 1);
> --
> 2.25.1
>
Re: [PATCH v4 7/8] libfdt: Make fdtdec_get_child_count() available for HOST
On 2020/3/30 下午1:29, Heinrich Schuchardt wrote:
On 3/30/20 5:56 AM, Kever Yang wrote:
The tool need to use fdtdec_get_child_count(), make it available for
HOST_CC.
Signed-off-by: Kever Yang
Reviewed-by: Punit Agrawal
---
Changes in v4:
- add function comment for fdtdec_get_child_count() in fdt_support.h
Changes in v3: None
Changes in v2: None
include/fdt_support.h | 9 +
lib/fdtdec.c | 11 ---
lib/fdtdec_common.c | 11 +++
3 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/include/fdt_support.h b/include/fdt_support.h
index ba14acd7f6..2eff311fa4 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -343,6 +343,15 @@ int fdt_get_cells_len(const void *blob, char
*nr_cells_name);
#ifdef USE_HOSTCC
int fdtdec_get_int(const void *blob, int node, const char *prop_name,
int default_val);
+
+/*
+ * Count child nodes of one parent node.
+ *
+ * @param blob FDT blob
+ * @param node parent node
+ * @return number of child node; 0 if there is not child node
Please, use Sphinx style for function comments. See
https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#function-documentation
This is a directly copy from include/fdtdec.h, maybe we need a clean up
after this patch?
Because at least many comment's style are like this in fdtdec.h and
fdt_support.h.
Thanks,
- Kever
Best regards
Heinrich
+ */
+int fdtdec_get_child_count(const void *blob, int node);
#endif
#ifdef CONFIG_FMAN_ENET
int fdt_update_ethernet_dt(void *blob);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index eb11fc898e..e13af283a1 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -810,17 +810,6 @@ int fdtdec_parse_phandle_with_args(const void
*blob, int src_node,
return rc;
}
-int fdtdec_get_child_count(const void *blob, int node)
-{
- int subnode;
- int num = 0;
-
- fdt_for_each_subnode(subnode, blob, node)
- num++;
-
- return num;
-}
-
int fdtdec_get_byte_array(const void *blob, int node, const char
*prop_name,
u8 *array, int count)
{
diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c
index 088e9e9063..5775992ef3 100644
--- a/lib/fdtdec_common.c
+++ b/lib/fdtdec_common.c
@@ -53,3 +53,14 @@ unsigned int fdtdec_get_uint(const void *blob, int
node, const char *prop_name,
debug("(not found)\n");
return default_val;
}
+
+int fdtdec_get_child_count(const void *blob, int node)
+{
+ int subnode;
+ int num = 0;
+
+ fdt_for_each_subnode(subnode, blob, node)
+ num++;
+
+ return num;
+}
Antwort: Re: [RFC PATCH v2] arch: x86: apl: Read FSP-M configuration from device-tree
Hi Simon, >> With this patch I moved the fsp-m configuration to the device-tree >> based on the baytrail boards. >> I have tried to build it so that only entries that differ from the >> default configuration need to be added. As a minimum the ddr >> configuration must be present. >> If you like this way of configuration, I am also willing to do the >> same >> for the fsp-s. >> Can you please provide me some feedback? >> >> Changes in v2: >> Added commit notes >> >> arch/x86/cpu/apollolake/fsp_m.c | 337 >+++--- >> arch/x86/dts/chromebook_coral.dts | 35 ++ >> .../asm/arch-apollolake/fsp/fsp_m_upd.h | 162 + >> 3 files changed, 414 insertions(+), 120 deletions(-) > >Reviewed-by: Simon Glass >Tested on chromebook_coral: >Tested-by: Simon Glass > >Do you think we should add a binding file for this though? Yes, I will create v3 with a binding file in doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt. Is that ok for you? Do you also agree to change the fsp-s configuration in the same way? Regards, Bernhard
Re: [PATCH v4 7/8] libfdt: Make fdtdec_get_child_count() available for HOST
On 3/30/20 5:56 AM, Kever Yang wrote:
The tool need to use fdtdec_get_child_count(), make it available for
HOST_CC.
Signed-off-by: Kever Yang
Reviewed-by: Punit Agrawal
---
Changes in v4:
- add function comment for fdtdec_get_child_count() in fdt_support.h
Changes in v3: None
Changes in v2: None
include/fdt_support.h | 9 +
lib/fdtdec.c | 11 ---
lib/fdtdec_common.c | 11 +++
3 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/include/fdt_support.h b/include/fdt_support.h
index ba14acd7f6..2eff311fa4 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -343,6 +343,15 @@ int fdt_get_cells_len(const void *blob, char
*nr_cells_name);
#ifdef USE_HOSTCC
int fdtdec_get_int(const void *blob, int node, const char *prop_name,
int default_val);
+
+/*
+ * Count child nodes of one parent node.
+ *
+ * @param blob FDT blob
+ * @param node parent node
+ * @return number of child node; 0 if there is not child node
Please, use Sphinx style for function comments. See
https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#function-documentation
Best regards
Heinrich
+ */
+int fdtdec_get_child_count(const void *blob, int node);
#endif
#ifdef CONFIG_FMAN_ENET
int fdt_update_ethernet_dt(void *blob);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index eb11fc898e..e13af283a1 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -810,17 +810,6 @@ int fdtdec_parse_phandle_with_args(const void *blob, int
src_node,
return rc;
}
-int fdtdec_get_child_count(const void *blob, int node)
-{
- int subnode;
- int num = 0;
-
- fdt_for_each_subnode(subnode, blob, node)
- num++;
-
- return num;
-}
-
int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
u8 *array, int count)
{
diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c
index 088e9e9063..5775992ef3 100644
--- a/lib/fdtdec_common.c
+++ b/lib/fdtdec_common.c
@@ -53,3 +53,14 @@ unsigned int fdtdec_get_uint(const void *blob, int node,
const char *prop_name,
debug("(not found)\n");
return default_val;
}
+
+int fdtdec_get_child_count(const void *blob, int node)
+{
+ int subnode;
+ int num = 0;
+
+ fdt_for_each_subnode(subnode, blob, node)
+ num++;
+
+ return num;
+}
RE: [PATCH 0/3] Program GIC LPI configuration table
Hi , Please help to review. Dependent patch https://patchwork.ozlabs.org/patch/1237847/ has already been accepted. > -Original Message- > From: Wasim Khan > Sent: Friday, February 14, 2020 11:05 AM > To: Priyanka Jain ; Udit Agarwal > ; Pankaj Bansal > Cc: u-boot@lists.denx.de; Wasim Khan > Subject: [PATCH 0/3] Program GIC LPI configuration table > > This patch set programs GIC LPI configuration table from Uboot for NXP's > LX2160A SoC. > > Wasim Khan (3): > board: fsl: lx2160a: Program GIC LPI configuration table > configs: lx2160a: Enable GIC_V3_ITS config > board: fsl: lx2160a: Add GIC LPI memory reserve fixup > > board/freescale/lx2160a/lx2160a.c| 26 +- > configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + > configs/lx2160aqds_tfa_defconfig | 1 + > configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + > configs/lx2160ardb_tfa_defconfig | 1 + > 5 files changed, 29 insertions(+), 1 deletion(-) > > -- > 2.7.4
[PATCH 3/4] cmd: mmc: display write protect state of boot partition
Boot partitions of eMMC devices can be power on or permanently write
protected. Let the 'mmc info' command display the protection state.
Signed-off-by: Heinrich Schuchardt
---
cmd/mmc.c | 24
1 file changed, 24 insertions(+)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 6f3cb85cc0..d62c85e439 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -54,6 +54,8 @@ static void print_mmcinfo(struct mmc *mmc)
if (!IS_SD(mmc) && mmc->version >= MMC_VERSION_4_41) {
bool has_enh = (mmc->part_support & ENHNCD_SUPPORT) != 0;
bool usr_enh = has_enh && (mmc->part_attr & EXT_CSD_ENH_USR);
+ u8 wp, ext_csd[MMC_MAX_BLOCK_LEN];
+ int ret;
#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
puts("HC WP Group Size: ");
@@ -90,6 +92,28 @@ static void print_mmcinfo(struct mmc *mmc)
putc('\n');
}
}
+ ret = mmc_send_ext_csd(mmc, ext_csd);
+ if (ret)
+ return;
+ wp = ext_csd[EXT_CSD_BOOT_WP_STATUS];
+ for (i = 0; i < 2; ++i) {
+ printf("Boot area %d is ", i);
+ switch (wp & 3) {
+ case 0:
+ printf("not write protected\n");
+ break;
+ case 1:
+ printf("power on protected\n");
+ break;
+ case 2:
+ printf("permanently protected\n");
+ break;
+ default:
+ printf("in reserved protection state\n");
+ break;
+ }
+ wp >>= 2;
+ }
}
}
static struct mmc *init_mmc_device(int dev, bool force_init)
--
2.25.1
[PATCH 1/4] mmc: EXT_CSD registers for write protection
Add the EXT_CSD register definition related to write protection. Signed-off-by: Heinrich Schuchardt --- include/mmc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/mmc.h b/include/mmc.h index e83c22423b..4ecd6c744c 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -223,6 +223,9 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define EXT_CSD_WR_REL_PARAM 166 /* R */ #define EXT_CSD_WR_REL_SET 167 /* R/W */ #define EXT_CSD_RPMB_MULT 168 /* RO */ +#define EXT_CSD_USER_WP171 /* R/W & R/W/C_P & R/W/E_P */ +#define EXT_CSD_BOOT_WP173 /* R/W & R/W/C_P */ +#define EXT_CSD_BOOT_WP_STATUS 174 /* R */ #define EXT_CSD_ERASE_GROUP_DEF175 /* R/W */ #define EXT_CSD_BOOT_BUS_WIDTH 177 #define EXT_CSD_PART_CONF 179 /* R/W */ -- 2.25.1
[PATCH 0/4] mmc: manage boot area protection
This patch series adds sub-command 'mmc wp' to set the power on boot area protection on eMMC devices and enhances command 'mmc info' to display the boot area protection status. Heinrich Schuchardt (4): mmc: EXT_CSD registers for write protection mmc: export mmc_send_ext_csd() cmd: mmc: display write protect state of boot partition cmd: mmc: provide boot area protection command cmd/mmc.c | 46 ++ drivers/mmc/mmc.c | 7 ++- include/mmc.h | 23 +++ 3 files changed, 75 insertions(+), 1 deletion(-) -- 2.25.1
[PATCH 2/4] mmc: export mmc_send_ext_csd()
Export function mmc_send_ext_csd() for reading the extended CSD register.
Signed-off-by: Heinrich Schuchardt
---
drivers/mmc/mmc.c | 2 +-
include/mmc.h | 11 +++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 3e36566693..bfcdaa665d 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -718,7 +718,7 @@ static int mmc_complete_op_cond(struct mmc *mmc)
}
-static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
+int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
{
struct mmc_cmd cmd;
struct mmc_data data;
diff --git a/include/mmc.h b/include/mmc.h
index 4ecd6c744c..85fc3497a1 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -896,6 +896,17 @@ int mmc_get_env_dev(void);
*/
struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
+/**
+ * mmc_send_ext_csd() - read the extended CSD register
+ *
+ * @mmc: MMC device
+ * @ext_csda cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by
+ * the caller, e.g. using
+ * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN)
+ * Return: 0 for success
+ */
+int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
+
static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
{
return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
--
2.25.1
[PATCH 4/4] cmd: mmc: provide boot area protection command
Provide command 'mmc wp' to power on write protect boot areas on eMMC
devices.
The B_PWR_WP_EN bit in the extended CSD register BOOT_WP is set. The boot
area are write protected until the next power cycle occurs.
Signed-off-by: Heinrich Schuchardt
---
cmd/mmc.c | 22 ++
drivers/mmc/mmc.c | 5 +
include/mmc.h | 9 +
3 files changed, 36 insertions(+)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index d62c85e439..80a32d9fa9 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -896,9 +896,30 @@ static int do_mmc_bkops_enable(cmd_tbl_t *cmdtp, int flag,
}
#endif
+static int do_mmc_boot_wp(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int err;
+ struct mmc *mmc;
+
+ mmc = init_mmc_device(curr_device, false);
+ if (!mmc)
+ return CMD_RET_FAILURE;
+ if (IS_SD(mmc)) {
+ printf("It is not an eMMC device\n");
+ return CMD_RET_FAILURE;
+ }
+ err = mmc_boot_wp(mmc);
+ if (err)
+ return CMD_RET_FAILURE;
+ printf("boot areas protected\n");
+ return CMD_RET_SUCCESS;
+}
+
static cmd_tbl_t cmd_mmc[] = {
U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""),
U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""),
+ U_BOOT_CMD_MKENT(wp, 1, 0, do_mmc_boot_wp, "", ""),
#if CONFIG_IS_ENABLED(MMC_WRITE)
U_BOOT_CMD_MKENT(write, 4, 0, do_mmc_write, "", ""),
U_BOOT_CMD_MKENT(erase, 3, 0, do_mmc_erase, "", ""),
@@ -968,6 +989,7 @@ U_BOOT_CMD(
"mmc part - lists available partition on current mmc device\n"
"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
"mmc list - lists available devices\n"
+ "mmc wp - power on write protect booot partitions\n"
#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
"mmc hwpartition [args...] - does hardware partitioning\n"
" arguments (sizes in 512-byte blocks):\n"
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index bfcdaa665d..fc3123c3c3 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -810,6 +810,11 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
return __mmc_switch(mmc, set, index, value, true);
}
+int mmc_boot_wp(struct mmc *mmc)
+{
+ return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
+}
+
#if !CONFIG_IS_ENABLED(MMC_TINY)
static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
bool hsdowngrade)
diff --git a/include/mmc.h b/include/mmc.h
index 85fc3497a1..e92e920560 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -907,6 +907,15 @@ struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
*/
int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
+/**
+ * mmc_boot_wp() - power on write protect boot partitions
+ *
+ * The boot partitions are write protected until the next power cycle.
+ *
+ * Return: 0 for success
+ */
+int mmc_boot_wp(struct mmc *mmc);
+
static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
{
return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
--
2.25.1
Re: [PATCHv2] kconfig / kbuild: Re-sync with Linux 4.19
Hi Tom,
On Sat, Mar 28, 2020 at 12:46 AM Tom Rini wrote:
>
> Align Kconfig and Kbuild logic to Linux 4.19 release with minimal impact
> on files outside of this scope.
>
> Our previous Kconfig sync was done by commit 5972ff077e0f ("kconfig /
> kbuild: re-sync with Linux 4.18").
>
> In this particular re-sync in order to keep clang support working a
> number of related changes needed to be pulled in that had been missed
> previously. Not all of these changes we easily traceable and so have
> been omitted from the list below.
>
> The imported Linux commits are:
> [From prior to v4.18]
> 9f3f1fd29976 kbuild: Add __cc-option macro
> d7f14c66c273 kbuild: Enable Large File Support for hostprogs
> 6d79a7b424a5 kbuild: suppress warnings from 'getconf LFS_*'
> 24403874316a Shared library support
> 86a9df597cdd kbuild: fix linker feature test macros when cross compiling with
> Clang
> 0294e6f4a000 kbuild: simplify ld-option implementation
>
> [From v4.18 to v4.19]
> 96f14fe738b6 kbuild: Rename HOSTCFLAGS to KBUILD_HOSTCFLAGS
> 10844aebf448 kbuild: Rename HOSTCXXFLAGS to KBUILD_HOSTCXXFLAGS
> b90a368000ab kbuild: Rename HOSTLDFLAGS to KBUILD_HOSTLDFLAGS
> 8377bd2b9ee1 kbuild: Rename HOST_LOADLIBES to KBUILD_HOSTLDLIBS
> f92d19e0ef9b kbuild: Use HOST*FLAGS options from the command line
> 4ab3b80159d4 kconfig: check for pkg-config on make {menu,n,g,x}config
> 693359f7ac90 kconfig: rename SYMBOL_AUTO to SYMBOL_NO_WRITE
> f60b992e30ff kbuild: replace $(LDFLAGS) $(ldflags-y) with $(ld_flags)
> 2fb9279f2c3e kbuild: change ld_flags to contain LDFLAGS_$(@F)
> c931d34ea085 arm64: build with baremetal linker target instead of Linux when
> available
> 5accd7f3360e kconfig: handle format string before calling
> conf_message_callback()
> a2ff4040151a kconfig: rename file_write_dep and move it to confdata.c
> 0608182ad542 kconfig: split out useful helpers in confdata.c
> adc18acf42a1 kconfig: remove unneeded directory generation from local*config
> 79123b1389cc kconfig: create directories needed for syncconfig by itself
> 16952b77d8b5 kconfig: make syncconfig update .config regardless of
> sym_change_count
> d6c6ab93e17f kbuild: remove deprecated host-progs variable
> 56869d45e364 kconfig: fix the rule of mainmenu_stmt symbol
> c151272d1687 kconfig: remove unused sym_get_env_prop() function
> 1880861226c1 kconfig: remove P_ENV property type
> e3fd9b5384f3 scripts/dtc: consolidate include path options in Makefile
> 4bf6a9af0e91 kconfig: add build-only configurator targets
> f1575595d156 kconfig: error out when seeing recursive dependency
> 5e8c5299d315 kconfig: report recursive dependency involving 'imply'
> f498926c47aa kconfig: improve the recursive dependency report
> 98a4afbfafd2 kconfig: fix "Can't open ..." in parallel build
> 9a9ddcf47831 kconfig: suppress "configuration written to .config" for
> syncconfig
> 87a32e624037 kbuild: pass LDFLAGS to recordmcount.pl
> d503ac531a52 kbuild: rename LDFLAGS to KBUILD_LDFLAGS
> 217c3e019675 disable stringop truncation warnings for now
> bc8d2e20a3eb kconfig: remove a spurious self-assignment
> fd65465b7016 kconfig: do not require pkg-config on make {menu,n}config
> 5a4630aadb9a ftrace: Build with CPPFLAGS to get -Qunused-arguments
It is difficult to review this list perfectly,
but I did not see anything odd in the code diff.
> Note that this adds new cleanup work to do in that we should adapt the
> shared library support we have to what is now upstream.
FYI:
Linux kernel is dropping the shared library support again.
Kees acked this.
https://patchwork.kernel.org/patch/11463979/
This removes .o -> .so build rules, and
I will queue it up for v5.7-rc1.
The gcc-plugin is the only user of the shared library support.
So, probably it should be moved to scripts/gcc-plugins/Makefile.
It may take more time for U-Boot to catch up,
but U-Boot can cope with it somehow, I think.
> Cc: Masahiro Yamada
Please feel free to replace Cc with:
Reviewed-by: Masahiro Yamada
Thanks!
--
Best Regards
Masahiro Yamada
Re: [PATCH 0/6] rockchip: rk3328: sync dts and add ROC-RK3328-CC board
On Sat, Mar 28, 2020 at 6:03 AM Kurt Miller wrote: > > On Sat, 2020-03-28 at 01:44 +0800, Chen-Yu Tsai wrote: > > Hi, > > > > On Fri, Mar 27, 2020 at 11:07 PM Kurt Miller > > wrote: > > > > > > > > > On Fri, 2020-03-27 at 12:41 +0800, Chen-Yu Tsai wrote: > > > > > > > > From: Chen-Yu Tsai > > > > > > > > Hi everyone, > > > > > > > > This series adds proper support for Firefly / Libre Computer > > > > ROC-RK3328-CC > > > > single board computer. > > > > > > > > The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit > > > > card size development board based on the Rockchip RK3328 SoC, with: > > > > > > > > - 1/2/4 GB DDR4 DRAM > > > > - eMMC connector for optional module > > > > - micro SD card slot > > > > - 1 x USB 3.0 host port > > > > - 2 x USB 2.0 host port > > > > - 1 x USB 2.0 OTG port > > > > - HDMI video output > > > > - TRRS connector with audio and composite video output > > > > - gigabit Ethernet > > > > - consumer IR receiver > > > > - debug UART pins > > > > > > > > Originally I started with Loic's patches, and syncing the device tree > > > > files from Linux. That didn't get very far, with SPL failing to detect > > > > the SD card. Examining the schematics and internal state of GRF and > > > > GPIOs, I realized that the logic for the SD card power enable switch > > > > is opposite that of what the SD card controller's SDMMC0_PWREN pin > > > > would use. Instead, directly using the GPIO is required. > > > > > > > > Thus this series creates a special target for this board to handle > > > > muxing this specific pin to GPIO state. The GPIO is left in input mode, > > > > letting the external pull-down work its magic. > > > > > > > > Along the way, there are some clean-ups of existing dts files, moving > > > > U-boot only features to -u-boot.dtsi files, and then a wholesale sync > > > > from Linux. Only boards already existing in U-boot are synced. DT > > > > binding header files are synced separately as there is already one > > > > patch floating around. The DT sync also includes clean-up changes only > > > > recently posted, and likely won't make it in for at least a few weeks. > > > > > > > > Please have a look, and test if possible. I cc-ed a couple people that > > > > showed interest in this board on mailing lists recently. > > > > > > > Thank you for updating the dts for rk3328. I have Rock64 v2 and v3 > > > boards and have tested your patchset with OpenBSD-current. The v2 board > > > is working and I have not noticed any regressions. The v3 board prior > > > to your patchset was not booting and continues to not boot. > > > > > > U-Boot TPL 2020.04-rc3-00172-gaf827140e5-dirty (Mar 27 2020 - 09:44:24) > > > LPDDR3, 800MHz > > > BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB > > > Trying to boot from BOOTROM > > > Returning to boot ROM... > > > > > > U-Boot SPL 2020.04-rc3-00172-gaf827140e5-dirty (Mar 27 2020 - 09:44:24 > > > -0400) > > > Trying to boot from MMC1 > > > Card did not respond to voltage select! > > > spl: mmc init failed with error: -95 > > > Trying to boot from MMC2 > > > Card did not respond to voltage select! > > > spl: mmc init failed with error: -95 > > > SPL: failed to boot from all boot devices > > > ### ERROR ### Please RESET the board ### > > > > > > The Rock64 v3 board issues are unrelated to your patch set, but I > > > believe it needs a similar approach as ROC-RK3328-CC. Here is some > > > info previously posted regarding this: > > > > > > https://marc.info/?t=15575150651&r=1&w=2 > > So based on the changes from Pine64, it looks like v3 follows a similar > > design as the ROC-RK3328-CC, that is use the SDMMC0_PWREN pin to control > > power to the SD card. On the Rock64 v3, there's no external pull-down, > > but the internal pull-down might be enough... > > > > You could try setting the target to ROC-RK3328-CC through menuconfig > > after you use the defconfig for rock64 and see if that works for you. > > > > Yes, that works for both the v2 and v3 boards. Thank you. > > Would you be able to create a patch 7 in your series to > apply this approch to the rock64? I took a look at the schematics again. The SDMMC0_PWREN pin is used to toggle the I/O signalling voltage. There is no power cut for the SD card. So configuring SDMMC0_PWREN to GPIO will get you through SPL, but why it works is slightly different for the Rock64 compared to the ROC-RK3328-CC. ChenYu
Re: [PATCH v8 00/12] Actions S700 SoC support
Hi Amit, On Sat, Mar 21, 2020 at 11:00:42PM +0530, Amit Singh Tomar wrote: > This adds Cubieboard7[1] support based on Action Semi's S700 SoC[2], It's > Quad-core ARMv8 SoC > with Cortex-A53 cores. Peripheral like UART seems to be compatible with S900 > SoC(basic support > for it is alreay present in u-boot). > > This series(v8) removes the SoC specific include instead just uses > owl-common. For this > patch 01/12 and 09/12 changes a bit. > > Previous series(v7) fixes a serious Bug that breaks S900, it was there since > v5.Thanks to Andre > for pointing it out. > > Series(v6)[3] does following changes: > > * [PATCH v5 06/11] becomes [PATCH v6 03/11] > * [PATCH v5 03/11] becomes [PATCH v6 04/11] > * Introduce a new patch to move defconfig options to Kconfig which is [PATCH > v6 10/12] > > Series(v5)[4] just re-orders the patches so that U-BOOT(with > bubblegum96_defconfig) builds > after every patch of the series(suggested by Andre). > > S700 support is tested[5] on Cubieboard7 board and S900 support is just > compiled tested. > > This patch series can be tested using below tree: > https://github.com/Atomar25/u-boot/commits/s700_v8 > Just tested v8 on bubblegum96 and it doesn't boot. I can't see any debug print on the console, so I'm guessing something basic going wrong. Will try to find the regression if I find some time and keep you posted. Thanks, Mani > [1]: http://www.cubietech.com/product-detail/cubieboard7/ > [2]: http://www.actions-semi.com/en/productview.aspx?id=225 > [3]: > http://u-boot.10912.n7.nabble.com/PATCH-v6-00-12-Actions-S700-SoC-support-td403562.html#a403567 > [4]: > http://u-boot.10912.n7.nabble.com/PATCH-v5-00-11-Actions-S700-SoC-support-td402752.html#a402762 > [5]: https://paste.ubuntu.com/p/xGYVbSytRS/ > > Amit Singh Tomar (12): > arm: actions: Add common framework for Actions Owl Semi SoCs > arm: actions: rename sysmap-s900 to sysmap-owl > serial: actions: add compatible string > arm: dts: sync dts for Action Semi S900 > arm: dts: actions: s900: add u-boot specific dtsi file > clk: actions: Add common clock driver > arm: actions: add S700 SoC device tree > arm: dts: actions: s700: add u-boot specific dtsi file > arm: add support Actions Semi S700 > actions: Move defconfig options to Kconfig > arm: add Cubieboard7 board support > doc: boards: add Cubieboard7 documentation > > MAINTAINERS| 2 + > arch/arm/Kconfig | 5 +- > arch/arm/dts/Makefile | 6 +- > arch/arm/dts/s700-cubieboard7.dts | 92 +++ > arch/arm/dts/s700-u-boot.dtsi | 18 ++ > arch/arm/dts/s700.dtsi | 248 +++ > arch/arm/dts/s900-u-boot.dtsi | 17 ++ > arch/arm/dts/s900.dtsi | 322 > +++-- > arch/arm/include/asm/arch-owl/clk_s900.h | 57 - > arch/arm/include/asm/arch-owl/regs_s700.h | 56 + > arch/arm/mach-owl/Kconfig | 50 ++-- > arch/arm/mach-owl/Makefile | 3 +- > arch/arm/mach-owl/soc.c| 57 + > arch/arm/mach-owl/sysmap-owl.c | 32 +++ > arch/arm/mach-owl/sysmap-s900.c| 32 --- > board/ucRobotics/bubblegum_96/Kconfig | 15 -- > board/ucRobotics/bubblegum_96/MAINTAINERS | 6 - > board/ucRobotics/bubblegum_96/Makefile | 3 - > board/ucRobotics/bubblegum_96/bubblegum_96.c | 57 - > configs/bubblegum_96_defconfig | 12 +- > configs/cubieboard7_defconfig | 9 + > doc/board/actions/cubieboard7.rst | 115 + > doc/board/actions/index.rst| 10 + > doc/board/index.rst| 1 + > drivers/clk/owl/Kconfig| 8 +- > drivers/clk/owl/Makefile | 2 +- > drivers/clk/owl/clk_owl.c | 153 > drivers/clk/owl/clk_owl.h | 65 + > drivers/clk/owl/clk_s900.c | 137 --- > drivers/serial/serial_owl.c| 2 +- > include/configs/bubblegum_96.h | 40 --- > include/configs/owl-common.h | 40 +++ > include/configs/s700.h | 13 + > include/configs/s900.h | 16 ++ > include/dt-bindings/clock/actions,s700-cmu.h | 118 + > include/dt-bindings/clock/actions,s900-cmu.h | 129 ++ > include/dt-bindings/clock/s900_cmu.h | 77 -- > include/dt-bindings/reset/actions,s700-reset.h | 34 +++ > include/dt-bindings/reset/actions,s900-reset.h | 65 + > 39 files changed, 1638 insertions(+), 486 deletions(-) > create mode 100644 arch/arm/dts/s700-cubieboard7.dts > create mode 100644 arch/arm/dts/s700-u-boot.dtsi > create mode 100644 arch/arm/dts
Re: [Patch V4 3/3] configs: rpi_4 : enable SDHCI_SDMA config
Hi Matthias, On 3/27/20 10:12 PM, Matthias Brugger wrote: > Hi Jaehoon, > > On 27/03/2020 05:08, Jaehoon Chung wrote: >> Enable SDHCI_SDMA configuration. >> >> Signed-off-by: Jaehoon Chung >> Reviewed-by: Peng Fan >> Reviewed-by: Minkyu Kang >> --- >> configs/rpi_4_32b_defconfig | 1 + >> configs/rpi_4_defconfig | 1 + >> 2 files changed, 2 insertions(+) >> > > Please address the comments I had in v3 of this patch: > https://protect2.fireeye.com/url?k=9b37681b-c6e760fe-9b36e354-000babff3563-8e3527bcf915de86&u=https://patchwork.ozlabs.org/patch/1261047/ Thanks for ping to me. I missed it. > > If you just send a new version of the patch that won't convince me to take it. > We will need to make sure that we are fine with patch. Especially I'm > concerned > about the limitation of the device to only be able to access the first GiB of > RAM for DMA. I'd like to see an explanation why this won't happen on U-Boot. It's why used phys_to_bus function.(arch/arm/mach-bcm283x/phys2bus.c) It's returned the bus address to access ram with DMA. Based at 0xc000 or 0x4000. Best Regards, Jaehoon Chung > > Regards, > Matthias > >> diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig >> index 72cda5d949..7189914606 100644 >> --- a/configs/rpi_4_32b_defconfig >> +++ b/configs/rpi_4_32b_defconfig >> @@ -25,6 +25,7 @@ CONFIG_DFU_MMC=y >> CONFIG_DM_KEYBOARD=y >> CONFIG_DM_MMC=y >> CONFIG_MMC_SDHCI=y >> +CONFIG_MMC_SDHCI_SDMA=y >> CONFIG_MMC_SDHCI_BCM2835=y >> CONFIG_DM_ETH=y >> CONFIG_BCMGENET=y >> diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig >> index 6d148dab07..454d28ea2b 100644 >> --- a/configs/rpi_4_defconfig >> +++ b/configs/rpi_4_defconfig >> @@ -25,6 +25,7 @@ CONFIG_DFU_MMC=y >> CONFIG_DM_KEYBOARD=y >> CONFIG_DM_MMC=y >> CONFIG_MMC_SDHCI=y >> +CONFIG_MMC_SDHCI_SDMA=y >> CONFIG_MMC_SDHCI_BCM2835=y >> CONFIG_DM_ETH=y >> CONFIG_BCMGENET=y >> > >
[PATCH v4 7/8] libfdt: Make fdtdec_get_child_count() available for HOST
The tool need to use fdtdec_get_child_count(), make it available for
HOST_CC.
Signed-off-by: Kever Yang
Reviewed-by: Punit Agrawal
---
Changes in v4:
- add function comment for fdtdec_get_child_count() in fdt_support.h
Changes in v3: None
Changes in v2: None
include/fdt_support.h | 9 +
lib/fdtdec.c | 11 ---
lib/fdtdec_common.c | 11 +++
3 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/include/fdt_support.h b/include/fdt_support.h
index ba14acd7f6..2eff311fa4 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -343,6 +343,15 @@ int fdt_get_cells_len(const void *blob, char
*nr_cells_name);
#ifdef USE_HOSTCC
int fdtdec_get_int(const void *blob, int node, const char *prop_name,
int default_val);
+
+/*
+ * Count child nodes of one parent node.
+ *
+ * @param blob FDT blob
+ * @param node parent node
+ * @return number of child node; 0 if there is not child node
+ */
+int fdtdec_get_child_count(const void *blob, int node);
#endif
#ifdef CONFIG_FMAN_ENET
int fdt_update_ethernet_dt(void *blob);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index eb11fc898e..e13af283a1 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -810,17 +810,6 @@ int fdtdec_parse_phandle_with_args(const void *blob, int
src_node,
return rc;
}
-int fdtdec_get_child_count(const void *blob, int node)
-{
- int subnode;
- int num = 0;
-
- fdt_for_each_subnode(subnode, blob, node)
- num++;
-
- return num;
-}
-
int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
u8 *array, int count)
{
diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c
index 088e9e9063..5775992ef3 100644
--- a/lib/fdtdec_common.c
+++ b/lib/fdtdec_common.c
@@ -53,3 +53,14 @@ unsigned int fdtdec_get_uint(const void *blob, int node,
const char *prop_name,
debug("(not found)\n");
return default_val;
}
+
+int fdtdec_get_child_count(const void *blob, int node)
+{
+ int subnode;
+ int num = 0;
+
+ fdt_for_each_subnode(subnode, blob, node)
+ num++;
+
+ return num;
+}
--
2.17.1
[PATCH v4 6/8] tool: use ALIGN() to align the size
Use the ALIGN() for size align so that the code is more readable. Signed-off-by: Kever Yang Reviewed-by: Punit Agrawal Reviewed-by: Tom Rini Reviewed-by: Heinrich Schuchardt --- Changes in v4: None Changes in v3: None Changes in v2: None tools/fit_image.c| 2 +- tools/socfpgaimage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/fit_image.c b/tools/fit_image.c index dd61a816c9..b7d615f8c8 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -547,7 +547,7 @@ static int fit_import_data(struct image_tool_params *params, const char *fname) if (fd < 0) return -EIO; fit_size = fdt_totalsize(old_fdt); - data_base = (fit_size + 3) & ~3; + data_base = ALIGN(fit_size, 4); /* Allocate space to hold the new FIT */ size = sbuf.st_size + 16384; diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c index 8fa098338b..6dfd64e31d 100644 --- a/tools/socfpgaimage.c +++ b/tools/socfpgaimage.c @@ -203,7 +203,7 @@ static int sfp_sign_buffer(uint8_t *buf, uint8_t ver, uint8_t flags, uint32_t calc_crc; /* Align the length up */ - len = (len + 3) & ~3; + len = ALIGN(len, 4); /* Build header, adding 4 bytes to length to hold the CRC32. */ sfp_build_header(buf + HEADER_OFFSET, ver, flags, len + 4); -- 2.17.1
[PATCH v4 8/8] mkimage: fit_image: Add option to make fit header align
The image is usually stored in block device like emmc, SD card, make the
offset of image data aligned to block(512 byte) can avoid data copy
during boot process.
eg. SPL boot from FIT image with external data:
- SPL read the first block of FIT image, and then parse the header;
- SPL read image data separately;
- The first image offset is the base_offset which is the header size;
- The second image offset is just after the first image;
- If the offset of imge does not aligned, SPL will do memcpy;
The header size is a ramdon number, which is very possible not aligned, so
add '-B size'to specify the align size in hex for better performance.
example usage:
./tools/mkimage -E -f u-boot.its -B 0x200 u-boot.itb
Signed-off-by: Kever Yang
Reviewed-by: Punit Agrawal
---
Changes in v4:
- update to clarify the size in hex format
Changes in v3:
- add common ALIGN() at imagetool.h
- migrate to use imagetool.h for all other files under tools/
Changes in v2:
- use '-B' to take a argument as a align block lenth;
- add new variable to indecate align_size
- address commens from Heinrich, Rasmus, Tom, Punit;
doc/uImage.FIT/source_file_format.txt | 5
tools/fit_image.c | 33 ---
tools/imagetool.h | 1 +
tools/mkimage.c | 14 ++--
4 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/doc/uImage.FIT/source_file_format.txt
b/doc/uImage.FIT/source_file_format.txt
index 18d2aedcb7..884a58456f 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -304,6 +304,11 @@ Normal kernel FIT image has data embedded within FIT
structure. U-Boot image
for SPL boot has external data. Existence of 'data-offset' can be used to
identify which format is used.
+For FIT image with external data, it would be better to align each blob of data
+to block(512 byte) for block device, so that we don't need to do the copy when
+read the image data in SPL. Pass '-B 0x200' to mkimage to align the FIT
+structure and data to 512 byte, other values available for other align size.
+
9) Examples
---
diff --git a/tools/fit_image.c b/tools/fit_image.c
index b7d615f8c8..06c32b3e71 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -422,7 +422,7 @@ err_buf:
*/
static int fit_extract_data(struct image_tool_params *params, const char
*fname)
{
- void *buf;
+ void *buf = NULL;
int buf_ptr;
int fit_size, new_size;
int fd;
@@ -431,26 +431,33 @@ static int fit_extract_data(struct image_tool_params
*params, const char *fname)
int ret;
int images;
int node;
+ int image_number;
+ int align_size;
+ align_size = params->bl_len ? params->bl_len : 4;
fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false, false);
if (fd < 0)
return -EIO;
fit_size = fdt_totalsize(fdt);
- /* Allocate space to hold the image data we will extract */
- buf = malloc(fit_size);
- if (!buf) {
- ret = -ENOMEM;
- goto err_munmap;
- }
- buf_ptr = 0;
-
images = fdt_path_offset(fdt, FIT_IMAGES_PATH);
if (images < 0) {
debug("%s: Cannot find /images node: %d\n", __func__, images);
ret = -EINVAL;
goto err_munmap;
}
+ image_number = fdtdec_get_child_count(fdt, images);
+
+ /*
+* Allocate space to hold the image data we will extract,
+* extral space allocate for image alignment to prevent overflow.
+*/
+ buf = malloc(fit_size + (align_size * image_number));
+ if (!buf) {
+ ret = -ENOMEM;
+ goto err_munmap;
+ }
+ buf_ptr = 0;
for (node = fdt_first_subnode(fdt, images);
node >= 0;
@@ -478,17 +485,17 @@ static int fit_extract_data(struct image_tool_params
*params, const char *fname)
buf_ptr);
}
fdt_setprop_u32(fdt, node, FIT_DATA_SIZE_PROP, len);
-
- buf_ptr += (len + 3) & ~3;
+ buf_ptr += ALIGN(len, align_size);
}
/* Pack the FDT and place the data after it */
fdt_pack(fdt);
+ new_size = fdt_totalsize(fdt);
+ new_size = ALIGN(new_size, align_size);
+ fdt_set_totalsize(fdt, new_size);
debug("Size reduced from %x to %x\n", fit_size, fdt_totalsize(fdt));
debug("External data size %x\n", buf_ptr);
- new_size = fdt_totalsize(fdt);
- new_size = (new_size + 3) & ~3;
munmap(fdt, sbuf.st_size);
if (ftruncate(fd, new_size)) {
diff --git a/tools/imagetool.h b/tools/imagetool.h
index 81e5cd0c5c..f54809cd57 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -79,6 +79,7 @@ struct image_tool_params {
bool external_data; /* Store data outside the FIT */
bool quie
[PATCH v4 4/8] tools: kwbimage: use common ALIGN to do the size align
The ALIGN() is now available at imagetool.h, migrate to use it.
Signed-off-by: Kever Yang
Reviewed-by: Punit Agrawal
Reviewed-by: Tom Rini
Reviewed-by: Stefan Roese
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
tools/kwbimage.c | 8
tools/kwbimage.h | 2 --
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index b8f8d38212..02fd0c949f 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1015,7 +1015,7 @@ static size_t image_headersz_v1(int *hasext)
* The payload should be aligned on some reasonable
* boundary
*/
- return ALIGN_SUP(headersz, 4096);
+ return ALIGN(headersz, 4096);
}
int add_binary_header_v1(uint8_t *cur)
@@ -1058,7 +1058,7 @@ int add_binary_header_v1(uint8_t *cur)
* up to a 4-byte boundary. Plus 4 bytes for the
* next-header byte and 3-byte alignment at the end.
*/
- binhdrsz = ALIGN_SUP(binhdrsz, 4) + 4;
+ binhdrsz = ALIGN(binhdrsz, 4) + 4;
hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0x);
hdr->headersz_msb = (binhdrsz & 0x) >> 16;
@@ -1082,7 +1082,7 @@ int add_binary_header_v1(uint8_t *cur)
fclose(bin);
- cur += ALIGN_SUP(s.st_size, 4);
+ cur += ALIGN(s.st_size, 4);
/*
* For now, we don't support more than one binary
@@ -1548,7 +1548,7 @@ static void kwbimage_set_header(void *ptr, struct stat
*sbuf, int ifd,
}
/* The MVEBU BootROM does not allow non word aligned payloads */
- sbuf->st_size = ALIGN_SUP(sbuf->st_size, 4);
+ sbuf->st_size = ALIGN(sbuf->st_size, 4);
version = image_get_version();
switch (version) {
diff --git a/tools/kwbimage.h b/tools/kwbimage.h
index 25bc08c5ce..0b6d05bef1 100644
--- a/tools/kwbimage.h
+++ b/tools/kwbimage.h
@@ -29,8 +29,6 @@
#define IBR_HDR_UART_ID0x69
#define IBR_DEF_ATTRIB 0x00
-#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
-
/* Structure of the main header, version 0 (Kirkwood, Dove) */
struct main_hdr_v0 {
uint8_t blockid; /* 0x0 */
--
2.17.1
[PATCH v4 5/8] tools: imx8mimage: remove redundant code
The align for fit_size has been done twice, remove the first one for it does not make any sense. Signed-off-by: Kever Yang Reviewed-by: Punit Agrawal Reviewed-by: Tom Rini --- Changes in v4: None Changes in v3: None Changes in v2: None tools/imx8mimage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index 7defb13962..bc4ee793cb 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -341,7 +341,6 @@ static int generate_ivt_for_fit(int fd, int fit_offset, uint32_t ep, } fit_size = fdt_totalsize(&image_header); - fit_size = (fit_size + 3) & ~3; fit_size = ALIGN(fit_size, ALIGN_SIZE); -- 2.17.1
[PATCH v4 2/8] tool: aisimage: use ALIGN instead of self defiend macro
The ALIGN() is available at imagetool.h, no need to self define one.
Signed-off-by: Kever Yang
Reviewed-by: Punit Agrawal
Reviewed-by: Tom Rini
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
tools/aisimage.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/aisimage.c b/tools/aisimage.c
index 4cd76ab843..b8b3ee3207 100644
--- a/tools/aisimage.c
+++ b/tools/aisimage.c
@@ -10,7 +10,6 @@
#define IS_FNC_EXEC(c) (cmd_table[c].AIS_cmd == AIS_CMD_FNLOAD)
#define WORD_ALIGN04
-#define WORD_ALIGN(len) (((len)+WORD_ALIGN0-1) & ~(WORD_ALIGN0-1))
#define MAX_CMD_BUFFER 4096
static uint32_t ais_img_size;
@@ -202,8 +201,9 @@ static uint32_t *ais_alloc_buffer(struct image_tool_params
*params)
* is not left to the main program, because after the datafile
* the header must be terminated with the Jump & Close command.
*/
- ais_img_size = WORD_ALIGN(sbuf.st_size) + MAX_CMD_BUFFER;
- ptr = (uint32_t *)malloc(WORD_ALIGN(sbuf.st_size) + MAX_CMD_BUFFER);
+ ais_img_size = ALIGN(sbuf.st_size, WORD_ALIGN0) + MAX_CMD_BUFFER;
+ ptr = (uint32_t *)malloc(ALIGN(sbuf.st_size, WORD_ALIGN0)
+ + MAX_CMD_BUFFER);
if (!ptr) {
fprintf(stderr, "%s: malloc return failure: %s\n",
params->cmdname, strerror(errno));
@@ -242,7 +242,7 @@ static uint32_t *ais_copy_image(struct image_tool_params
*params,
*aisptr++ = params->ep;
*aisptr++ = sbuf.st_size;
memcpy((void *)aisptr, ptr, sbuf.st_size);
- aisptr += WORD_ALIGN(sbuf.st_size) / sizeof(uint32_t);
+ aisptr += ALIGN(sbuf.st_size, WORD_ALIGN0) / sizeof(uint32_t);
(void) munmap((void *)ptr, sbuf.st_size);
(void) close(dfd);
--
2.17.1
[PATCH v4 3/8] tools: mkimage: use common ALIGN to do the size align
The ALIGN() is now available at imagetool.h, migrate to use it.
Signed-off-by: Kever Yang
Reviewed-by: Punit Agrawal
Reviewed-by: Tom Rini
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
tools/mkimage.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 5f51d2cc89..0279f6867e 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -7,6 +7,7 @@
* Wolfgang Denk, w...@denx.de
*/
+#include "imagetool.h"
#include "mkimage.h"
#include "imximage.h"
#include
@@ -557,8 +558,8 @@ int main(int argc, char **argv)
}
if (params.type == IH_TYPE_FIRMWARE_IVT) {
/* Add alignment and IVT */
- uint32_t aligned_filesize = (params.file_size + 0x1000
- - 1) & ~(0x1000 - 1);
+ uint32_t aligned_filesize = ALIGN(params.file_size,
+ 0x1000);
flash_header_v2_t ivt_header = { { 0xd1, 0x2000, 0x40 },
params.addr, 0, 0, 0, params.addr
+ aligned_filesize
--
2.17.1
[PATCH v4 1/8] tool: Move ALIGN_MASK to header as common MACRO
The ALIGN code is need by many files who need handle structure or image
align, so move the macro to imagetool.h file.
Signed-off-by: Kever Yang
Reviewed-by: Punit Agrawal
Reviewed-by: Tom Rini
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/imx8image.h | 1 -
tools/ifwitool.c| 4 +---
tools/imagetool.h | 3 +++
tools/imx8mimage.c | 2 --
tools/mksunxiboot.c | 4 +---
5 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/include/imx8image.h b/include/imx8image.h
index 68ec9f5fcd..00c614ab6c 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -11,7 +11,6 @@
#include
#include
#include "imagetool.h"
-#include "linux/kernel.h"
#define __packed __attribute__((packed))
diff --git a/tools/ifwitool.c b/tools/ifwitool.c
index 543e9d4e70..b2b06cc921 100644
--- a/tools/ifwitool.c
+++ b/tools/ifwitool.c
@@ -8,15 +8,13 @@
#include
#include
#include
+#include "imagetool.h"
#include "os_support.h"
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#define KiB1024
-#define ALIGN(x, a)__ALIGN_MASK((x), (typeof(x))(a) - 1)
-#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
/*
* min()/max()/clamp() macros that also do
diff --git a/tools/imagetool.h b/tools/imagetool.h
index e1c778b0df..81e5cd0c5c 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -25,6 +25,9 @@
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
+#define ALIGN(x, a)__ALIGN_MASK((x), (typeof(x))(a) - 1)
+
#define IH_ARCH_DEFAULTIH_ARCH_INVALID
/* Information about a file that needs to be placed into the FIT */
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index 2b0d946a7d..7defb13962 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -32,8 +32,6 @@ static uint32_t rom_version = ROM_V1;
#define HDMI_FW_SIZE 0x17000 /* Use Last 0x1000 for IVT and CSF */
#define ALIGN_SIZE 0x1000
-#define ALIGN(x,a) __ALIGN_MASK((x), (__typeof__(x))(a) - 1, a)
-#define __ALIGN_MASK(x,mask,mask2) (((x) + (mask)) / (mask2) * (mask2))
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 1c8701e75e..a18c9d98bc 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include "imagetool.h"
#include "../arch/arm/include/asm/arch-sunxi/spl.h"
#define STAMP_VALUE 0x5F0A6C39
@@ -44,9 +45,6 @@ int gen_check_sum(struct boot_file_head *head_p)
return 0;
}
-#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1)
-#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
-
#define SUNXI_SRAM_SIZE 0x8000 /* SoC with smaller size are limited before */
#define SRAM_LOAD_MAX_SIZE (SUNXI_SRAM_SIZE - sizeof(struct boot_file_head))
--
2.17.1
Re: [RFC 0/7] mx6cuboxi: enable OF_PLATDATA with MMC support
Hi Walter,
On Mon, Mar 30 2020, Walter Lozano wrote:
> The SPL in iMX6 boards is restricted to 68 KB as this is the free available
> space in OCRAM for most revisions. In this context, adding OF_CONTROL and DM
> increases the SPL size which could make it difficult to add specific features
> required for custom scenarios.
>
> These patches aim to take advantage of OF_PLATADATA in order to reduce the SPL
> size in this scenario, by parsing DT data to generate platdata structures,
> and thus removing the overhead caused by DT and related libraries.
>
> This series is focused in MMC driver, which is used for boot in boards such as
> Cubox-i. Also, in order to support CD, the OF_PLATDATA support is also
> implemented on GPIO driver.
>
> To make possible to link the CD information found in platdata with a GPIO,
> a new API is suggested, to find/get a device based on its platdata. This
> new API was discussed in [1] but the lack of context made the discussion
> not to progress. With this series, the general idea should be clearer,
> so a better solution could be discussed.
>
> Finally, in order to make use of these new features, enable OF_PLATADATA for
> Cubox-i board, for which OF_CONTROL support is being discussed in [2].
What is the net SPL size reduction of OF_PLATDATA in the Cubox-i case?
Thanks,
baruch
> [1] https://patchwork.ozlabs.org/patch/1249198/
> [2] https://patchwork.ozlabs.org/project/uboot/list/?series=163738
>
> Walter Lozano (7):
> mmc: fsl_esdhc_imx: add OF_PLATDATA support
> mmc: fsl_esdhc_imx: add ofdata_to_platdata support
> dtoc: update dtb_platdata to support cd-gpio
> dm: uclass: add functions to get device by platdata
> gpio: mxc_gpio: add OF_PLATDATA support
> mmc: fsl_esdhc_imx: add CD support when OF_PLATDATA is enabled
> mx6cuboxi: enable OF_PLATDATA
>
> configs/mx6cuboxi_defconfig | 2 +
> drivers/core/device.c| 19 +++
> drivers/core/uclass.c| 34
> drivers/gpio/mxc_gpio.c | 27 -
> drivers/mmc/fsl_esdhc_imx.c | 105 ++-
> include/dm/device.h | 11
> include/dm/uclass-internal.h | 15 +
> include/dm/uclass.h | 15 +
> tools/dtoc/dtb_platdata.py | 9 ++-
> 9 files changed, 218 insertions(+), 19 deletions(-)
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}ooO--U--Ooo{=
- bar...@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
[RFC 7/7] mx6cuboxi: enable OF_PLATDATA
Signed-off-by: Walter Lozano --- configs/mx6cuboxi_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 7ea79b9064..90aac8a284 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -42,6 +42,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-hummingboard2-emmc-som-v15" CONFIG_OF_LIST="imx6dl-hummingboard2-emmc-som-v15 imx6q-hummingboard2-emmc-som-v15" CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y @@ -64,3 +65,4 @@ CONFIG_USB_KEYBOARD=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_SPL_OF_LIBFDT is not set -- 2.20.1
[RFC 6/7] mmc: fsl_esdhc_imx: add CD support when OF_PLATDATA is enabled
Signed-off-by: Walter Lozano
---
drivers/mmc/fsl_esdhc_imx.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 049a1b6ea8..a3a9e5ff96 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#if !CONFIG_IS_ENABLED(BLK)
#include "mmc_private.h"
@@ -1490,7 +1491,30 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->bus_width = 4;
else
priv->bus_width = 1;
- priv->non_removable = 1;
+
+ if (dtplat->non_removable)
+ priv->non_removable = 1;
+ else
+ priv->non_removable = 0;
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ if (!priv->non_removable) {
+ struct udevice *gpiodev;
+
+ ret = uclass_get_device_by_platdata(UCLASS_GPIO, (void
*)dtplat->cd_gpios->node, &gpiodev);
+
+ if (ret)
+ return ret;
+
+ ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
+dtplat->cd_gpios->arg[0],
GPIOD_IS_IN,
+dtplat->cd_gpios->arg[1],
&priv->cd_gpio);
+
+ if (ret)
+ return ret;
+
+ }
+#endif
#endif
if (data)
--
2.20.1
[RFC 5/7] gpio: mxc_gpio: add OF_PLATDATA support
Signed-off-by: Walter Lozano
---
drivers/gpio/mxc_gpio.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index c924e52f07..ba63c0b76a 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -13,6 +13,8 @@
#include
#include
#include
+#include
+#include
enum mxc_gpio_direction {
MXC_GPIO_DIRECTION_IN,
@@ -22,6 +24,10 @@ enum mxc_gpio_direction {
#define GPIO_PER_BANK 32
struct mxc_gpio_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_fsl_imx6q_gpio dtplat;
+#endif
int bank_index;
struct gpio_regs *regs;
};
@@ -303,8 +309,16 @@ static int mxc_gpio_bind(struct udevice *dev)
* is statically initialized in U_BOOT_DEVICES.Here
* will return.
*/
- if (plat)
+
+ if (plat) {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_fsl_imx6q_gpio *dtplat = &plat->dtplat;
+
+ plat->regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+ plat->bank_index = dev->req_seq;
+#endif
return 0;
+ }
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@@ -347,6 +361,17 @@ U_BOOT_DRIVER(gpio_mxc) = {
.bind = mxc_gpio_bind,
};
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+U_BOOT_DRIVER(fsl_imx6q_gpio) = {
+ .name = "fsl_imx6q_gpio",
+ .id = UCLASS_GPIO,
+ .ops= &gpio_mxc_ops,
+ .probe = mxc_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
+ .bind = mxc_gpio_bind,
+};
+#endif
+
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct mxc_gpio_plat mxc_plat[] = {
{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
--
2.20.1
[RFC 4/7] dm: uclass: add functions to get device by platdata
When OF_PLATDATA is enabled DT information is parsed and platdata
structures are populated. In this context the links between DT nodes are
represented as pointers to platdata structures, and there is no clear way
to access to the device which owns the structure.
This patch implements a set of functions:
- device_find_by_platdata
- uclass_find_device_by_platdata
to access to the device.
Signed-off-by: Walter Lozano
---
drivers/core/device.c| 19 +++
drivers/core/uclass.c| 34 ++
include/dm/device.h | 11 +++
include/dm/uclass-internal.h | 15 +++
include/dm/uclass.h | 15 +++
5 files changed, 94 insertions(+)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 89ea820d48..54a3a8d870 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -591,6 +591,25 @@ static int device_find_by_ofnode(ofnode node, struct
udevice **devp)
}
#endif
+
+int device_find_by_platdata(void *platdata, struct udevice **devp)
+{
+ struct uclass *uc;
+ struct udevice *dev;
+ int ret;
+
+ list_for_each_entry(uc, &gd->uclass_root, sibling_node) {
+ ret = uclass_find_device_by_platdata(uc->uc_drv->id, platdata,
+ &dev);
+ if (!ret || dev) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
int device_get_child(const struct udevice *parent, int index,
struct udevice **devp)
{
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 58b19a4210..7b0ae5b122 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -271,6 +271,29 @@ int uclass_find_device_by_name(enum uclass_id id, const
char *name,
return -ENODEV;
}
+int uclass_find_device_by_platdata(enum uclass_id id, void * platdata, struct
udevice **devp)
+{
+ struct uclass *uc;
+ struct udevice *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = uclass_get(id, &uc);
+ if (ret)
+ return ret;
+ if (list_empty(&uc->dev_head))
+ return -ENODEV;
+
+ uclass_foreach_dev(dev, uc) {
+ if (dev->platdata == platdata) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
int uclass_find_next_free_req_seq(enum uclass_id id)
{
struct uclass *uc;
@@ -466,6 +489,17 @@ int uclass_get_device_by_name(enum uclass_id id, const
char *name,
return uclass_get_device_tail(dev, ret, devp);
}
+int uclass_get_device_by_platdata(enum uclass_id id, void * platdata,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = uclass_find_device_by_platdata(id, platdata, &dev);
+ return uclass_get_device_tail(dev, ret, devp);
+}
+
int uclass_get_device_by_seq(enum uclass_id id, int seq, struct udevice **devp)
{
struct udevice *dev;
diff --git a/include/dm/device.h b/include/dm/device.h
index ab806d0b7e..6282376789 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -396,6 +396,17 @@ enum uclass_id device_get_uclass_id(const struct udevice
*dev);
*/
const char *dev_get_uclass_name(const struct udevice *dev);
+/**
+ * device_find_by_platdata() - return the device by its platdata
+ *
+ * Returns the device which onws the platdata structure pointed.
+ *
+ * @platdata: Struct platdata to use for search
+ * @devp: Returns pointer to device
+ * @return error code
+ */
+int device_find_by_platdata(void *platdata, struct udevice **devp);
+
/**
* device_get_child() - Get the child of a device by index
*
diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h
index 6e3f15c2b0..aeff1ec127 100644
--- a/include/dm/uclass-internal.h
+++ b/include/dm/uclass-internal.h
@@ -100,6 +100,21 @@ int uclass_find_next_device(struct udevice **devp);
int uclass_find_device_by_name(enum uclass_id id, const char *name,
struct udevice **devp);
+/**
+ * uclass_find_device_by_platdata() - Find uclass device based on ID and
platdata
+ *
+ * This searches for a device with the exactly given platada.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @platdata: pointer to struct platdata of a device to find
+ * @devp: Returns pointer to device
+ * @return 0 if OK, -ve on error
+ */
+int uclass_find_device_by_platdata(enum uclass_id id, void *platdata,
+ struct udevice **devp);
+
/**
* uclass_find_device_by_seq() - Find uclass device based on ID and sequence
*
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 70fca79b44..8429b28289 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -167,6 +167,21 @@ int uclass_get_device(enum uclass_id i
[RFC 0/7] mx6cuboxi: enable OF_PLATDATA with MMC support
The SPL in iMX6 boards is restricted to 68 KB as this is the free available space in OCRAM for most revisions. In this context, adding OF_CONTROL and DM increases the SPL size which could make it difficult to add specific features required for custom scenarios. These patches aim to take advantage of OF_PLATADATA in order to reduce the SPL size in this scenario, by parsing DT data to generate platdata structures, and thus removing the overhead caused by DT and related libraries. This series is focused in MMC driver, which is used for boot in boards such as Cubox-i. Also, in order to support CD, the OF_PLATDATA support is also implemented on GPIO driver. To make possible to link the CD information found in platdata with a GPIO, a new API is suggested, to find/get a device based on its platdata. This new API was discussed in [1] but the lack of context made the discussion not to progress. With this series, the general idea should be clearer, so a better solution could be discussed. Finally, in order to make use of these new features, enable OF_PLATADATA for Cubox-i board, for which OF_CONTROL support is being discussed in [2]. [1] https://patchwork.ozlabs.org/patch/1249198/ [2] https://patchwork.ozlabs.org/project/uboot/list/?series=163738 Walter Lozano (7): mmc: fsl_esdhc_imx: add OF_PLATDATA support mmc: fsl_esdhc_imx: add ofdata_to_platdata support dtoc: update dtb_platdata to support cd-gpio dm: uclass: add functions to get device by platdata gpio: mxc_gpio: add OF_PLATDATA support mmc: fsl_esdhc_imx: add CD support when OF_PLATDATA is enabled mx6cuboxi: enable OF_PLATDATA configs/mx6cuboxi_defconfig | 2 + drivers/core/device.c| 19 +++ drivers/core/uclass.c| 34 drivers/gpio/mxc_gpio.c | 27 - drivers/mmc/fsl_esdhc_imx.c | 105 ++- include/dm/device.h | 11 include/dm/uclass-internal.h | 15 + include/dm/uclass.h | 15 + tools/dtoc/dtb_platdata.py | 9 ++- 9 files changed, 218 insertions(+), 19 deletions(-) -- 2.20.1
[RFC 2/7] mmc: fsl_esdhc_imx: add ofdata_to_platdata support
Signed-off-by: Walter Lozano
---
drivers/mmc/fsl_esdhc_imx.c | 71 ++---
1 file changed, 42 insertions(+), 29 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 761a4b46e9..049a1b6ea8 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1379,41 +1379,20 @@ __weak void init_clk_usdhc(u32 index)
{
}
-static int fsl_esdhc_probe(struct udevice *dev)
-{
- struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
- struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+static int fsl_esdhc_ofdata_to_platdata(struct udevice *dev){
+
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(dev);
- fdt_addr_t addr;
-#else
- struct dtd_fsl_imx6q_usdhc *dtplat = &plat->dtplat;
-#endif
- struct esdhc_soc_data *data =
- (struct esdhc_soc_data *)dev_get_driver_data(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
+ int ret;
#endif
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+
+ fdt_addr_t addr;
unsigned int val;
- struct mmc *mmc;
-#if !CONFIG_IS_ENABLED(BLK)
- struct blk_desc *bdesc;
-#endif
- int ret;
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
- priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
- val = plat->dtplat.bus_width;
- if (val == 8)
- priv->bus_width = 8;
- else if (val == 4)
- priv->bus_width = 4;
- else
- priv->bus_width = 1;
- priv->non_removable = 1;
-#else
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
@@ -1483,8 +1462,40 @@ static int fsl_esdhc_probe(struct udevice *dev)
}
#endif
#endif
+ return 0;
+}
+
+static int fsl_esdhc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct esdhc_soc_data *data =
+ (struct esdhc_soc_data *)dev_get_driver_data(dev);
+ struct mmc *mmc;
+#if !CONFIG_IS_ENABLED(BLK)
+ struct blk_desc *bdesc;
+#endif
+ int ret;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_fsl_imx6q_usdhc *dtplat = &plat->dtplat;
+ unsigned int val;
+
+ priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+ val = plat->dtplat.bus_width;
+ if (val == 8)
+ priv->bus_width = 8;
+ else if (val == 4)
+ priv->bus_width = 4;
+ else
+ priv->bus_width = 1;
+ priv->non_removable = 1;
+#endif
+
if (data)
priv->flags = data->flags;
+
/*
* TODO:
* Because lack of clk driver, if SDHC clk is not enabled,
@@ -1664,6 +1675,7 @@ U_BOOT_DRIVER(fsl_esdhc) = {
.name = "fsl-esdhc-mmc",
.id = UCLASS_MMC,
.of_match = fsl_esdhc_ids,
+ .ofdata_to_platdata = fsl_esdhc_ofdata_to_platdata,
.ops= &fsl_esdhc_ops,
#if CONFIG_IS_ENABLED(BLK)
.bind = fsl_esdhc_bind,
@@ -1677,6 +1689,7 @@ U_BOOT_DRIVER(fsl_esdhc) = {
U_BOOT_DRIVER(fsl_usdhc) = {
.name = "fsl_imx6q_usdhc",
.id = UCLASS_MMC,
+ .ofdata_to_platdata = fsl_esdhc_ofdata_to_platdata,
.ops= &fsl_esdhc_ops,
#if CONFIG_IS_ENABLED(BLK)
.bind = fsl_esdhc_bind,
--
2.20.1
[RFC 1/7] mmc: fsl_esdhc_imx: add OF_PLATDATA support
Signed-off-by: Walter Lozano
---
drivers/mmc/fsl_esdhc_imx.c | 46 +
1 file changed, 42 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 4900498e9b..761a4b46e9 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -29,6 +29,8 @@
#include
#include
#include
+#include
+#include
#if !CONFIG_IS_ENABLED(BLK)
#include "mmc_private.h"
@@ -98,6 +100,11 @@ struct fsl_esdhc {
};
struct fsl_esdhc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_fsl_imx6q_usdhc dtplat;
+#endif
+
struct mmc_config cfg;
struct mmc mmc;
};
@@ -1377,14 +1384,18 @@ static int fsl_esdhc_probe(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
+ fdt_addr_t addr;
+#else
+ struct dtd_fsl_imx6q_usdhc *dtplat = &plat->dtplat;
+#endif
struct esdhc_soc_data *data =
(struct esdhc_soc_data *)dev_get_driver_data(dev);
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
#endif
- fdt_addr_t addr;
unsigned int val;
struct mmc *mmc;
#if !CONFIG_IS_ENABLED(BLK)
@@ -1392,14 +1403,23 @@ static int fsl_esdhc_probe(struct udevice *dev)
#endif
int ret;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+ val = plat->dtplat.bus_width;
+ if (val == 8)
+ priv->bus_width = 8;
+ else if (val == 4)
+ priv->bus_width = 4;
+ else
+ priv->bus_width = 1;
+ priv->non_removable = 1;
+#else
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->esdhc_regs = (struct fsl_esdhc *)addr;
priv->dev = dev;
priv->mode = -1;
- if (data)
- priv->flags = data->flags;
val = dev_read_u32_default(dev, "bus-width", -1);
if (val == 8)
@@ -1462,7 +1482,9 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->vs18_enable = 1;
}
#endif
-
+#endif
+ if (data)
+ priv->flags = data->flags;
/*
* TODO:
* Because lack of clk driver, if SDHC clk is not enabled,
@@ -1513,9 +1535,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
return ret;
}
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
+#endif
mmc = &plat->mmc;
mmc->cfg = &plat->cfg;
@@ -1648,4 +1672,18 @@ U_BOOT_DRIVER(fsl_esdhc) = {
.platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
.priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+U_BOOT_DRIVER(fsl_usdhc) = {
+ .name = "fsl_imx6q_usdhc",
+ .id = UCLASS_MMC,
+ .ops= &fsl_esdhc_ops,
+#if CONFIG_IS_ENABLED(BLK)
+ .bind = fsl_esdhc_bind,
+#endif
+ .probe = fsl_esdhc_probe,
+ .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
+ .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+};
+#endif
#endif
--
2.20.1
[RFC 3/7] dtoc: update dtb_platdata to support cd-gpio
Signed-off-by: Walter Lozano
---
tools/dtoc/dtb_platdata.py | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py
index 037e82c8bb..c52da7925e 100644
--- a/tools/dtoc/dtb_platdata.py
+++ b/tools/dtoc/dtb_platdata.py
@@ -211,7 +211,7 @@ class DtbPlatdata(object):
Return:
Number of argument cells is this is a phandle, else None
"""
-if prop.name in ['clocks']:
+if prop.name in ['clocks', 'cd-gpios']:
if not isinstance(prop.value, list):
prop.value = [prop.value]
val = prop.value
@@ -231,8 +231,11 @@ class DtbPlatdata(object):
if not target:
raise ValueError("Cannot parse '%s' in node '%s'" %
(prop.name, node_name))
-prop_name = '#clock-cells'
-cells = target.props.get(prop_name)
+cells = None
+for prop_name in ['#clock-cells', '#gpio-cells']:
+cells = target.props.get(prop_name)
+if cells:
+break
if not cells:
raise ValueError("Node '%s' has no '%s' property" %
(target.name, prop_name))
--
2.20.1
Re: [PATCH 1/3] riscv: Start using ldflags-y for 32/64bit LDFLAGS
> From: Tom Rini [mailto:tr...@konsulko.com] > Sent: Friday, March 27, 2020 9:52 PM > To: u-boot@lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志) > Subject: [PATCH 1/3] riscv: Start using ldflags-y for 32/64bit LDFLAGS > > To prepare to update our Kbuild logic, start switching some of our cases of > adding different bit/endian linker flags via ldflags-y > > Cc: Rick Chen > Signed-off-by: Tom Rini > --- > arch/riscv/config.mk | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) Reviewed-by: Rick Chen .
Re: [PATCH v3 8/8] mkimage: fit_image: Add option to make fit header align
Hi Tom, On 2020/3/28 上午2:16, Tom Rini wrote: On Thu, Mar 26, 2020 at 06:09:16PM +0800, Kever Yang wrote: The image is usually stored in block device like emmc, SD card, make the offset of image data aligned to block(512 byte) can avoid data copy during boot process. eg. SPL boot from FIT image with external data: - SPL read the first block of FIT image, and then parse the header; - SPL read image data separately; - The first image offset is the base_offset which is the header size; - The second image offset is just after the first image; - If the offset of imge does not aligned, SPL will do memcpy; The header size is a ramdon number, which is very possible not aligned, so add '-B' to specify the align size in hex for better performance. example usage: ./tools/mkimage -E -f u-boot.its -B 200 u-boot.itb OK, so we're taking a hex input, and that's not clear in the documentation. The example should also be 0x200 for clarity. In fact, being user-space, we need to make this user friendly and sanity check the input and if we're going to take hex in, enforce '0x' as a prefix even I think. Thanks! I use hex input because all of other parameters for mkimage tool are using hex format instead of decimal format. I will update ot use 0x200. Thanks, - Kever
RE: [PATCH RESEND] arm: dts: agilex: Enable QSPI
> -Original Message-
> From: Marek Vasut
> Sent: Monday, March 30, 2020 9:47 AM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Ley Foon Tan ; See, Chin Liang
> ; Simon Goldschmidt
>
> Subject: Re: [PATCH RESEND] arm: dts: agilex: Enable QSPI
>
> On 3/30/20 3:34 AM, Tan, Ley Foon wrote:
> >
> >
> >> -Original Message-
> >> From: Marek Vasut
> >> Sent: Monday, March 30, 2020 9:29 AM
> >> To: Tan, Ley Foon ; u-boot@lists.denx.de
> >> Cc: Ley Foon Tan ; See, Chin Liang
> >> ; Simon Goldschmidt
> >>
> >> Subject: Re: [PATCH RESEND] arm: dts: agilex: Enable QSPI
> >>
> >> On 3/30/20 3:21 AM, Tan, Ley Foon wrote:
> >>>
> On 3/27/20 9:24 AM, Ley Foon Tan wrote:
> > Enable QSPI for Agilex SoC devkit.
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> > arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> > index 1908be4b8b27..241c0efab14c 100644
> > --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> > +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> > @@ -37,3 +37,7 @@
> > u-boot,dm-pre-reloc;
> > };
> >
> > +&qspi {
> > + status = "okay";
> > +}
>
> Is this for master or next ?
> >>> Will it be too late for master? If yes, then for next.
> >>
> >> It's late, but if you feel adventurous and think this is gonna work
> >> fine, then I can put it into master. This is isolated to agilex, so I
> >> don't mind
> either way.
> > Tested on Agilex board. Master should be okay.
> > Thanks.
>
> Then master it is.
Thanks!
Regards
Ley Foon
Re: [PATCH RESEND] arm: dts: agilex: Enable QSPI
On 3/30/20 3:34 AM, Tan, Ley Foon wrote:
>
>
>> -Original Message-
>> From: Marek Vasut
>> Sent: Monday, March 30, 2020 9:29 AM
>> To: Tan, Ley Foon ; u-boot@lists.denx.de
>> Cc: Ley Foon Tan ; See, Chin Liang
>> ; Simon Goldschmidt
>>
>> Subject: Re: [PATCH RESEND] arm: dts: agilex: Enable QSPI
>>
>> On 3/30/20 3:21 AM, Tan, Ley Foon wrote:
>>>
On 3/27/20 9:24 AM, Ley Foon Tan wrote:
> Enable QSPI for Agilex SoC devkit.
>
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> index 1908be4b8b27..241c0efab14c 100644
> --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> @@ -37,3 +37,7 @@
> u-boot,dm-pre-reloc;
> };
>
> +&qspi {
> + status = "okay";
> +}
Is this for master or next ?
>>> Will it be too late for master? If yes, then for next.
>>
>> It's late, but if you feel adventurous and think this is gonna work fine,
>> then I
>> can put it into master. This is isolated to agilex, so I don't mind either
>> way.
> Tested on Agilex board. Master should be okay.
> Thanks.
Then master it is.
RE: [PATCH RESEND] arm: dts: agilex: Enable QSPI
> -Original Message-
> From: Marek Vasut
> Sent: Monday, March 30, 2020 9:29 AM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Ley Foon Tan ; See, Chin Liang
> ; Simon Goldschmidt
>
> Subject: Re: [PATCH RESEND] arm: dts: agilex: Enable QSPI
>
> On 3/30/20 3:21 AM, Tan, Ley Foon wrote:
> >
> >> On 3/27/20 9:24 AM, Ley Foon Tan wrote:
> >>> Enable QSPI for Agilex SoC devkit.
> >>>
> >>> Signed-off-by: Ley Foon Tan
> >>> ---
> >>> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
> >>> 1 file changed, 4 insertions(+)
> >>>
> >>> diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> >> b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> >>> index 1908be4b8b27..241c0efab14c 100644
> >>> --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> >>> +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> >>> @@ -37,3 +37,7 @@
> >>> u-boot,dm-pre-reloc;
> >>> };
> >>>
> >>> +&qspi {
> >>> + status = "okay";
> >>> +}
> >>
> >> Is this for master or next ?
> > Will it be too late for master? If yes, then for next.
>
> It's late, but if you feel adventurous and think this is gonna work fine,
> then I
> can put it into master. This is isolated to agilex, so I don't mind either
> way.
Tested on Agilex board. Master should be okay.
Thanks.
Regards
Ley Foon
Re: [PATCH RESEND] arm: dts: agilex: Enable QSPI
On 3/30/20 3:21 AM, Tan, Ley Foon wrote:
>
>> On 3/27/20 9:24 AM, Ley Foon Tan wrote:
>>> Enable QSPI for Agilex SoC devkit.
>>>
>>> Signed-off-by: Ley Foon Tan
>>> ---
>>> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
>>> 1 file changed, 4 insertions(+)
>>>
>>> diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
>> b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
>>> index 1908be4b8b27..241c0efab14c 100644
>>> --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
>>> +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
>>> @@ -37,3 +37,7 @@
>>> u-boot,dm-pre-reloc;
>>> };
>>>
>>> +&qspi {
>>> + status = "okay";
>>> +}
>>
>> Is this for master or next ?
> Will it be too late for master? If yes, then for next.
It's late, but if you feel adventurous and think this is gonna work
fine, then I can put it into master. This is isolated to agilex, so I
don't mind either way.
RE: [PATCH RESEND] arm: dts: agilex: Enable QSPI
> On 3/27/20 9:24 AM, Ley Foon Tan wrote:
> > Enable QSPI for Agilex SoC devkit.
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> > arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> > index 1908be4b8b27..241c0efab14c 100644
> > --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> > +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> > @@ -37,3 +37,7 @@
> > u-boot,dm-pre-reloc;
> > };
> >
> > +&qspi {
> > + status = "okay";
> > +}
>
> Is this for master or next ?
Will it be too late for master? If yes, then for next.
Regards
Ley Foon
Re: [PATCH v1] x86: acpi: Refactor XSDT handling in acpi_add_table()
On Sun, Mar 29, 2020 at 5:13 AM Simon Glass wrote:
> On Thu, 5 Mar 2020 at 05:17, Andy Shevchenko
> wrote:
> > On Tue, Mar 03, 2020 at 07:47:56PM -0700, Simon Glass wrote:
> > > On Tue, 3 Mar 2020 at 02:23, Andy Shevchenko
> > > wrote:
> > > > On Tue, Mar 3, 2020 at 1:36 AM Simon Glass wrote:
...
> > 2/ How this is supposed to be compiled?
> > + table_compute_checksum((xsdt, xsdt->header.length);
> >...means this series should go thru bisectability tests (something like
> >aiaiai https://lwn.net/Articles/488992/ script provides)
>
> I'm not sure what you mean by that?
Isn't above may not be compiled without error?
aiaiai is a script which allows to check bisectability (compile-time)
errors like above.
> > 3/ This one looks not 64-bit compatible.
> > + printf("RSDP %08lx %06x (v%02d %.6s)\n",
> > (ulong)map_to_sysmem(rsdp),
> > + rsdp->length, rsdp->revision, rsdp->oem_id);
> > ...means that types for printing and all explicit casting should be
> > revisited.
>
> I don't want to print 64-bit addresses if I can help it. I don't even
> want to use them as they are a pain to look at! If we start using
> 64-bit U-Boot I still think we will put the ACPI tables below 2GB.
So, it should be documented then.
...
> > Till this one "acpi: Add some tables required by the generation code" looks
> > okay (in terms of approach).
> >
> > This one "acpi: Add generation code for devices" requires quite a good
> > review.
> > So, I would recommend to split the series (and this patch in particular) to
> > smaller chunks. So does this "acpi: Add functions to generate ACPI code".
> > They are unreviewable.
>
> OK I can split that first part off as a series and then split the next
> patches.
Thank you.
...
> > > > I was thinking myself about some U-Boot framework that actually takes
> > > > ACPI _HID from the driver. So, when you define in U-Boot device tree a
> > > > compatible string (for U-Boot use), in the driver it will have in the
> > > > class structure the callback / field / stubstructure to use when ACPI
> > > > generate tables is enabled. It will drop duplication of compatible
> > > > with ACPI _HID in each DTS.
> > >
> > > Why are you so opposed to using device tree for this? The GPIO and
> > > pinctrl drivers are intended to be genericwhat a pain to add all
> > > this stuff into the tables in the driver!
> >
> > So, this is a trade off between C code and DTS. I'm okay to use DTS for
> > the stuff that belongs to it. But then, if we enable DTS for ACPI tables
> > generation, we have to provide a mean to do it without driver involvement.
> >
> > How to generate the table for the device U-Boot has no driver for?
>
> We add a driver. The driver might only generate ACPI tables, but it is
> still a driver.
Hmm... This is interesting concept. So, each time we would like to get
only tables we will need to create a stub driver.
...
> > > > But to the current topic, you put *instance* (not even _HID) to the DT
> > > > with property called "linux,name". It's inappropriate. NAK for that
> > > > for sure.
> > >
> > > OK, so are you saying the property name (linux-name) should change? We
> > > have acpi,name elsewhere but I don't think that is the _HID.
> > >
> > > Or are you saying that the "INT3452:" should be factored out and it
> > > should know the 00/01/0203 by its position in the device tree?
> >
> > It shouldn't be anywhere in the U-Boot, it's complete OS business.
> > What you have in U-Boot is ACPI _HID (_UID, etc.), and device path (e.g.
> > \\_SB_.GPO0), no-one should rely on OS (Linux, Windows, etc) internals.
> > We have already an issue with GPIO pin numbers on Chromebook with Intel
> > Cherryview SoC.
>
> Right but how can ACPI code refer to the GPIO if it cannot reference it?
What do you mean? Any example where you need *instance* over *_HID*?
> > This
> >
> > + linux-name = "INT3452:00";
> >
> > is wrong in both sides -- left, as a property name, and right,
> > as an *instance* in some OS we must not rely on ever.
> >
> > The question is why do you need it?
>
> To generate ACPI code which references that GPIO.
>
> See chromeos_acpi_gpio_generate().
I can't see right now. Do you have web browser thru source code?
GitLab instance doesn't show recent x86 repository.
> Can you suggest a better property name? Maybe acpi,linux-name? But it
> isn't really an ACPI name.
ACPI _HID. No instance, please. If you are using instance outside of
Linux kernel code it points to wrong design and I have strong opinion
not to support this kind of design.
> > > > > > > > On top of that, I think we rather need to have a conversion
> > > > > > > > layer than
> > > > > > > > putting some names inside DT, like \_SB_.GPO0 should be
> > > > > > > > generated
> > > > > > > > automatically from DT node. That said, I don't like DT being
> > > > > > > > polluted
> > > > > > > > with non-DT stuff.
> > > > > > >
> > > > > > > Well DT is the configuration mechan
eMMC: power on protection of boot areas
Currently U-Boot does not protect the boot areas of eMMC devices. This may lead to an unsolicited replacement of the boot loader. In https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/tree/mmc I have added a command 'mmc wp' to enable power on boot protection for the boot areas and enhanced command 'mmc info' to display the protection. I am still contemplating what should be protected on an eMMC device: There is a permanent write protection for boot areas. If this property is set updates are no longer possible. This capability can be permanently disabled (flag B_PERM_WP_DIS in BOOT_WP register of extended CSD [1]). The same exists for the user area. eMMCs can be password protected. This protection might be used as a denial of service vector. The password protection feature can be permanently disabled (flag PERM_PSWD_DIS in USER_WP register of extended CSD). Protecting the boot areas via command 'mmc wp' requires a boot script for automatic execution. Should we enable power on boot area protection inside the boot commands whenever they are called (as a customizable feature)? [1] Embedded Multi-Media Card (e•MMC) Electrical Standard (5.1) JESD84-B51, 2015 Best regards Heinrich
Pull request for UEFI sub-system for efi-2020-04-rc4 (6)
The following changes since commit 350c44dfb99017e9147ee07d37a40626bde62250: Merge branch '2020-03-27-master-imports' (2020-03-27 17:54:38 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2020-04-rc4-6 for you to fetch changes up to d4babee087f24a60d910659cb4367a077bad87a0: vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader. (2020-03-28 11:11:32 +0100) Pull request for UEFI sub-system for efi-2020-04-rc4 (6) This series fixes: * UEFI Python test for helloworld requires CONFIG_OF_CONTROL=y. * int to pointer cast warning for cmd/efidebug.c * memory reservation even if fdt node is disabled Now that the Python test is fixed reintroduce the reverted patch for vexpress_ca9x4 to enable EFI_LOADER and define the dtb file name. Heinrich Schuchardt (3): test/py: UEFI helloworld requires OF_CONTROL cmd: efidebug: fix int to pointer cast efi_loader: only reserve memory if fdt node enabled Kristian Amlie (1): vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader. cmd/bootefi.c | 3 ++- cmd/efidebug.c| 8 +--- configs/vexpress_ca9x4_defconfig | 2 +- include/configs/vexpress_common.h | 3 ++- test/py/tests/test_efi_loader.py | 5 +++-- 5 files changed, 13 insertions(+), 8 deletions(-)
Re: Bug#955310: u-boot-tools: update list of architectures in mkimage
On 2020-03-29, Chris Dumont wrote: >* What led up to the situation? > read the manpage for mkimage and then used 'mkimage -T -h' ... >* What was the outcome of this action? > The output (ellipsized) > > $ mkimage -T -h > > Invalid image type, supported are: > Unknown image type Unknown image type > aisimage Davinci AIS image > atmelimage ATMEL ROM-Boot Image > filesystem Filesystem Image > ... It appears the recommendation from mkimage help output is to use "mkimage -T list" now. It seems like this should be changed to "-T list" in the manpage. There are several other options -A, -O and -C that also should probably be updated, but those options need an updated to the code as well, as they output the usage information in addition to listing the available Architecture/Os/Compression types: $ mkimage -A list Invalid architecture, supported are: Unknown architecture Unknown architecture Unknown architecture Unknown architecture alphaAlpha arc ARC arm ARM arm64AArch64 ... x86_64 AMD x86_64 xtensa Xtensa Error: Invalid architecture Usage: mkimage -l image -l ==> list image header information mkimage [-x] -A arch -O os -T type -C comp -a addr -e ep -n name -d data_file[:data_file...] image -A ==> set architecture to 'arch' ... -i => input filename for ramdisk file Signing / verified boot not supported (CONFIG_FIT_SIGNATURE undefined) mkimage -V ==> print version information and exit Use '-T list' to see a list of available image types Using "mkimage -T list" just displays the list of image types, from what I can tell, which seems more-or-less fine. I haven't tested anything newer than 2020.04~rc2, so there may be newer fixes upstream... live well, vagrant signature.asc Description: PGP signature
[PATCH 1/1] cmd: mmc: fix typo 'a EMMC'
%s/a EMMC/an eMMC/g
Signed-off-by: Heinrich Schuchardt
---
cmd/mmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 80a32d9fa9..cfe813d686 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -288,7 +288,7 @@ static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag,
return CMD_RET_FAILURE;
if (!(mmc->version & MMC_VERSION_MMC)) {
- printf("It is not a EMMC device\n");
+ printf("It is not an eMMC device\n");
return CMD_RET_FAILURE;
}
if (mmc->version < MMC_VERSION_4_41) {
@@ -742,7 +742,7 @@ static int do_mmc_boot_resize(cmd_tbl_t *cmdtp, int flag,
return CMD_RET_FAILURE;
if (IS_SD(mmc)) {
- printf("It is not a EMMC device\n");
+ printf("It is not an eMMC device\n");
return CMD_RET_FAILURE;
}
--
2.20.1
[PATCH] mtd: spi-nor: Enable dual and quad read for s25fl256s0
From: Bacem Daassi
The s25fl256s0 supports dual and quad read like s25fl256s1.
Enable it by adding SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ
flags to the flash_info entry.
Tested on real silicon and confirmed to be working.
Signed-off-by: Bacem Daassi
---
drivers/mtd/spi/spi-nor-ids.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 973b6f86c9..cfc3a41f04 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -191,7 +191,7 @@ const struct flash_info spi_nor_ids[] = {
*/
{ INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
+ { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
--
2.17.1
Re: [PATCH 0/6] rockchip: rk3328: sync dts and add ROC-RK3328-CC board
On Fri, 2020-03-27 at 12:41 +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai
>
> Hi everyone,
>
> This series adds proper support for Firefly / Libre Computer ROC-RK3328-CC
> single board computer.
>
> The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
> card size development board based on the Rockchip RK3328 SoC, with:
>
> - 1/2/4 GB DDR4 DRAM
> - eMMC connector for optional module
> - micro SD card slot
> - 1 x USB 3.0 host port
> - 2 x USB 2.0 host port
> - 1 x USB 2.0 OTG port
> - HDMI video output
> - TRRS connector with audio and composite video output
> - gigabit Ethernet
> - consumer IR receiver
> - debug UART pins
>
> Originally I started with Loic's patches, and syncing the device tree
> files from Linux. That didn't get very far, with SPL failing to detect
> the SD card. Examining the schematics and internal state of GRF and
> GPIOs, I realized that the logic for the SD card power enable switch
> is opposite that of what the SD card controller's SDMMC0_PWREN pin
> would use. Instead, directly using the GPIO is required.
>
> Thus this series creates a special target for this board to handle
> muxing this specific pin to GPIO state. The GPIO is left in input mode,
> letting the external pull-down work its magic.
>
> Along the way, there are some clean-ups of existing dts files, moving
> U-boot only features to -u-boot.dtsi files, and then a wholesale sync
> from Linux. Only boards already existing in U-boot are synced. DT
> binding header files are synced separately as there is already one
> patch floating around. The DT sync also includes clean-up changes only
> recently posted, and likely won't make it in for at least a few weeks.
>
> Please have a look, and test if possible. I cc-ed a couple people that
> showed interest in this board on mailing lists recently.
>
Thank you for updating the dts for rk3328. I have Rock64 v2 and v3
boards and have tested your patchset with OpenBSD-current. The v2 board
is working and I have not noticed any regressions. The v3 board prior
to your patchset was not booting and continues to not boot.
U-Boot TPL 2020.04-rc3-00172-gaf827140e5-dirty (Mar 27 2020 - 09:44:24)
LPDDR3, 800MHz
BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB
Trying to boot from BOOTROM
Returning to boot ROM...
U-Boot SPL 2020.04-rc3-00172-gaf827140e5-dirty (Mar 27 2020 - 09:44:24 -0400)
Trying to boot from MMC1
Card did not respond to voltage select!
spl: mmc init failed with error: -95
Trying to boot from MMC2
Card did not respond to voltage select!
spl: mmc init failed with error: -95
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
The Rock64 v3 board issues are unrelated to your patch set, but I
believe it needs a similar approach as ROC-RK3328-CC. Here is some
info previously posted regarding this:
https://marc.info/?t=15575150651&r=1&w=2
Regards,
-Kurt
> Regards
> ChenYu
>
>
> Chen-Yu Tsai (6):
> rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi
> rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi
> dt-bindings: clock: rk3328: sync from upstream Linux kernel
> dt-bindings: power: rk3328-power: sync from upstream Linux kernel
> rockchip: dts: rk3328: Sync device tree files from Linux
> rockchip: rk3328: Add support for ROC-RK3328-CC board
>
> arch/arm/dts/Makefile |1 +
> arch/arm/dts/rk3328-evb-u-boot.dtsi | 39 +
> arch/arm/dts/rk3328-evb.dts | 220 +--
> arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 17 +
> .../{rk3328-rock64.dts => rk3328-roc-cc.dts} | 135 +-
> arch/arm/dts/rk3328-rock64.dts| 132 +-
> arch/arm/dts/rk3328.dtsi | 1420 +++--
> arch/arm/mach-rockchip/rk3328/Kconfig |8 +
> board/firefly/roc-cc-rk3328/Kconfig | 24 +
> board/firefly/roc-cc-rk3328/MAINTAINERS |7 +
> board/firefly/roc-cc-rk3328/Makefile |1 +
> board/firefly/roc-cc-rk3328/board.c | 38 +
> configs/roc-cc-rk3328_defconfig | 97 ++
> doc/README.rockchip |4 +-
> include/dt-bindings/clock/rk3328-cru.h| 212 +--
> include/dt-bindings/power/rk3328-power.h | 19 +
> 16 files changed, 1622 insertions(+), 752 deletions(-)
> create mode 100644 arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
> copy arch/arm/dts/{rk3328-rock64.dts => rk3328-roc-cc.dts} (68%)
> create mode 100644 board/firefly/roc-cc-rk3328/Kconfig
> create mode 100644 board/firefly/roc-cc-rk3328/MAINTAINERS
> create mode 100644 board/firefly/roc-cc-rk3328/Makefile
> create mode 100644 board/firefly/roc-cc-rk3328/board.c
> create mode 100644 configs/roc-cc-rk3328_defconfig
> create mode 100644 include/dt-bindings/power/rk3328-power.h
>
Re: [PATCH 0/6] rockchip: rk3328: sync dts and add ROC-RK3328-CC board
On Sat, 2020-03-28 at 01:44 +0800, Chen-Yu Tsai wrote: > Hi, > > On Fri, Mar 27, 2020 at 11:07 PM Kurt Miller > wrote: > > > > > > On Fri, 2020-03-27 at 12:41 +0800, Chen-Yu Tsai wrote: > > > > > > From: Chen-Yu Tsai > > > > > > Hi everyone, > > > > > > This series adds proper support for Firefly / Libre Computer ROC-RK3328-CC > > > single board computer. > > > > > > The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit > > > card size development board based on the Rockchip RK3328 SoC, with: > > > > > > - 1/2/4 GB DDR4 DRAM > > > - eMMC connector for optional module > > > - micro SD card slot > > > - 1 x USB 3.0 host port > > > - 2 x USB 2.0 host port > > > - 1 x USB 2.0 OTG port > > > - HDMI video output > > > - TRRS connector with audio and composite video output > > > - gigabit Ethernet > > > - consumer IR receiver > > > - debug UART pins > > > > > > Originally I started with Loic's patches, and syncing the device tree > > > files from Linux. That didn't get very far, with SPL failing to detect > > > the SD card. Examining the schematics and internal state of GRF and > > > GPIOs, I realized that the logic for the SD card power enable switch > > > is opposite that of what the SD card controller's SDMMC0_PWREN pin > > > would use. Instead, directly using the GPIO is required. > > > > > > Thus this series creates a special target for this board to handle > > > muxing this specific pin to GPIO state. The GPIO is left in input mode, > > > letting the external pull-down work its magic. > > > > > > Along the way, there are some clean-ups of existing dts files, moving > > > U-boot only features to -u-boot.dtsi files, and then a wholesale sync > > > from Linux. Only boards already existing in U-boot are synced. DT > > > binding header files are synced separately as there is already one > > > patch floating around. The DT sync also includes clean-up changes only > > > recently posted, and likely won't make it in for at least a few weeks. > > > > > > Please have a look, and test if possible. I cc-ed a couple people that > > > showed interest in this board on mailing lists recently. > > > > > Thank you for updating the dts for rk3328. I have Rock64 v2 and v3 > > boards and have tested your patchset with OpenBSD-current. The v2 board > > is working and I have not noticed any regressions. The v3 board prior > > to your patchset was not booting and continues to not boot. > > > > U-Boot TPL 2020.04-rc3-00172-gaf827140e5-dirty (Mar 27 2020 - 09:44:24) > > LPDDR3, 800MHz > > BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB > > Trying to boot from BOOTROM > > Returning to boot ROM... > > > > U-Boot SPL 2020.04-rc3-00172-gaf827140e5-dirty (Mar 27 2020 - 09:44:24 > > -0400) > > Trying to boot from MMC1 > > Card did not respond to voltage select! > > spl: mmc init failed with error: -95 > > Trying to boot from MMC2 > > Card did not respond to voltage select! > > spl: mmc init failed with error: -95 > > SPL: failed to boot from all boot devices > > ### ERROR ### Please RESET the board ### > > > > The Rock64 v3 board issues are unrelated to your patch set, but I > > believe it needs a similar approach as ROC-RK3328-CC. Here is some > > info previously posted regarding this: > > > > https://marc.info/?t=15575150651&r=1&w=2 > So based on the changes from Pine64, it looks like v3 follows a similar > design as the ROC-RK3328-CC, that is use the SDMMC0_PWREN pin to control > power to the SD card. On the Rock64 v3, there's no external pull-down, > but the internal pull-down might be enough... > > You could try setting the target to ROC-RK3328-CC through menuconfig > after you use the defconfig for rock64 and see if that works for you. > Yes, that works for both the v2 and v3 boards. Thank you. Would you be able to create a patch 7 in your series to apply this approch to the rock64? Regards, -Kurt
[PATCH v2 2/3] arm: asm/cache.c: Introduce arm_reserve_mmu
As a preparation for turning reserve_mmu into an arch-specific variant,
introduce arm_reserve_mmu on ARM. It implements the default routine for
reserving memory for MMU TLB and needs to be weakly defined in order to allow
for machines to override it.
Without this decoupling, after introducing arch_reserve_mmu, there would be two
weak definitions for it, one in common/board_f.c and one in
arch/arm/lib/cache.c.
Signed-off-by: Ovidiu Panait
---
arch/arm/include/asm/cache.h | 11 +++
arch/arm/lib/cache.c | 5 +
arch/arm/mach-versal/cpu.c | 3 ++-
arch/arm/mach-zynqmp/cpu.c | 3 ++-
4 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 950ec1e793..c20e05ec7f 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -49,4 +49,15 @@ void dram_bank_mmu_setup(int bank);
*/
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+/*
+ * arm_reserve_mmu() - Reserve memory for MMU TLB table
+ *
+ * Default implementation for reserving memory for MMU TLB table. It is used
+ * during generic board init sequence in common/board_f.c. Weakly defined, so
+ * that machines can override it if needed.
+ *
+ * Return: 0 if OK
+ */
+int arm_reserve_mmu(void);
+
#endif /* _ASM_CACHE_H */
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index b8e1e340a1..3cbed602eb 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -122,6 +122,11 @@ void invalidate_l2_cache(void)
#endif
__weak int reserve_mmu(void)
+{
+ return arm_reserve_mmu();
+}
+
+__weak int arm_reserve_mmu(void)
{
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/* reserve TLB table */
diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
index 6ee6cd43ec..c14c5bb39c 100644
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -98,7 +99,7 @@ u64 get_page_table_size(void)
}
#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
-int reserve_mmu(void)
+int arm_reserve_mmu(void)
{
tcm_init(TCM_LOCK);
gd->arch.tlb_size = PGTABLE_SIZE;
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 442427bc11..811684a9f8 100644
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#define ZYNQ_SILICON_VER_MASK 0xF000
#define ZYNQ_SILICON_VER_SHIFT 12
@@ -116,7 +117,7 @@ void tcm_init(u8 mode)
#endif
#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
-int reserve_mmu(void)
+int arm_reserve_mmu(void)
{
tcm_init(TCM_LOCK);
gd->arch.tlb_size = PGTABLE_SIZE;
--
2.17.1
[PATCH v2 1/3] common/board_f: Move arm-specific reserve_mmu to arch/arm/lib/cache.c
Move the ARM-specific reserve_mmu definition from common/board_f.c
to arch/arm/lib/cache.c.
Signed-off-by: Ovidiu Panait
---
arch/arm/lib/cache.c | 28
common/board_f.c | 28
2 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 007d4ebc49..b8e1e340a1 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -10,6 +10,8 @@
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Flush range from all levels of d-cache/unified-cache.
* Affects the range [start, start + size - 1].
@@ -118,3 +120,29 @@ void invalidate_l2_cache(void)
isb();
}
#endif
+
+__weak int reserve_mmu(void)
+{
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ /* reserve TLB table */
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ gd->relocaddr -= gd->arch.tlb_size;
+
+ /* round down to next 64 kB limit */
+ gd->relocaddr &= ~(0x1 - 1);
+
+ gd->arch.tlb_addr = gd->relocaddr;
+ debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ /*
+* Record allocated tlb_addr in case gd->tlb_addr to be overwritten
+* with location within secure ram.
+*/
+ gd->arch.tlb_allocated = gd->arch.tlb_addr;
+#endif
+#endif
+
+ return 0;
+}
diff --git a/common/board_f.c b/common/board_f.c
index 82a164752a..a88bd64630 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -385,34 +385,6 @@ static int reserve_round_4k(void)
return 0;
}
-#ifdef CONFIG_ARM
-__weak int reserve_mmu(void)
-{
-#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
- /* reserve TLB table */
- gd->arch.tlb_size = PGTABLE_SIZE;
- gd->relocaddr -= gd->arch.tlb_size;
-
- /* round down to next 64 kB limit */
- gd->relocaddr &= ~(0x1 - 1);
-
- gd->arch.tlb_addr = gd->relocaddr;
- debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
- gd->arch.tlb_addr + gd->arch.tlb_size);
-
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- /*
-* Record allocated tlb_addr in case gd->tlb_addr to be overwritten
-* with location within secure ram.
-*/
- gd->arch.tlb_allocated = gd->arch.tlb_addr;
-#endif
-#endif
-
- return 0;
-}
-#endif
-
static int reserve_video(void)
{
#ifdef CONFIG_DM_VIDEO
--
2.17.1
[PATCH v2 3/3] common/board_f: Make reserve_mmu generic
Introduce arch_reserve_mmu to allow for architecture-specific reserve_mmu
routines. Also, define a weak nop stub for it.
Signed-off-by: Ovidiu Panait
---
arch/arm/lib/cache.c | 2 +-
common/board_f.c | 9 ++---
include/init.h | 13 -
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 3cbed602eb..44dde26065 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -121,7 +121,7 @@ void invalidate_l2_cache(void)
}
#endif
-__weak int reserve_mmu(void)
+int arch_reserve_mmu(void)
{
return arm_reserve_mmu();
}
diff --git a/common/board_f.c b/common/board_f.c
index a88bd64630..52750dd307 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -385,6 +385,11 @@ static int reserve_round_4k(void)
return 0;
}
+__weak int arch_reserve_mmu(void)
+{
+ return 0;
+}
+
static int reserve_video(void)
{
#ifdef CONFIG_DM_VIDEO
@@ -942,9 +947,7 @@ static const init_fnc_t init_sequence_f[] = {
reserve_pram,
#endif
reserve_round_4k,
-#ifdef CONFIG_ARM
- reserve_mmu,
-#endif
+ arch_reserve_mmu,
reserve_video,
reserve_trace,
reserve_uboot,
diff --git a/include/init.h b/include/init.h
index 2a33a3fd1e..9ef88c966b 100644
--- a/include/init.h
+++ b/include/init.h
@@ -129,6 +129,18 @@ int testdram(void);
*/
int arch_reserve_stacks(void);
+/**
+ * arch_reserve_mmu() - Reserve memory for MMU TLB table
+ *
+ * Architecture-specific routine for reserving memory for the MMU TLB table.
+ * This is used in generic board init sequence in common/board_f.c.
+ *
+ * If an implementation is not provided, it will just be a nop stub.
+ *
+ * Return: 0 if OK
+ */
+int arch_reserve_mmu(void);
+
/**
* init_cache_f_r() - Turn on the cache in preparation for relocation
*
@@ -145,7 +157,6 @@ int init_cache_f_r(void);
int print_cpuinfo(void);
#endif
int timer_init(void);
-int reserve_mmu(void);
int misc_init_f(void);
#if defined(CONFIG_DTB_RESELECT)
--
2.17.1
[PATCH v2 0/3] common/board_f: Make reserve_mmu generic
Changes in v2:
- split the original patch in 3 parts
- add function comments
- drop #ifdefs around asm/cache.h includes
- drop reserve_mmu function and leave only arch_reserve_mmu
For the following suggestion:
"Can you please try to use if() instead of #if as much as possible?"
I tried replacing in reserve_mmu
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
with
if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
...
}
but it caused compile issues on different arm platforms such as:
...
arch/arm/lib/cache.c: In function 'arm_reserve_mmu':
arch/arm/lib/cache.c:134:11: error: 'volatile struct arch_global_data' has no
member named 'tlb_size'
gd->arch.tlb_size = PGTABLE_SIZE;
^
arch/arm/lib/cache.c:135:28: error: 'volatile struct arch_global_data' has no
member named 'tlb_size'
gd->relocaddr -= gd->arch.tlb_size;
^
arch/arm/lib/cache.c:140:11: error: 'volatile struct arch_global_data' has no
member named 'tlb_addr'
gd->arch.tlb_addr = gd->relocaddr;
In file included from include/common.h:34:0,
from arch/arm/lib/cache.c:9:
arch/arm/lib/cache.c:141:52: error: 'volatile struct arch_global_data' has no
member named 'tlb_addr'
...
Ovidiu Panait (3):
common/board_f: Move arm-specific reserve_mmu to arch/arm/lib/cache.c
arm: asm/cache.c: Introduce arm_reserve_mmu
common/board_f: Make reserve_mmu generic
arch/arm/include/asm/cache.h | 11 +++
arch/arm/lib/cache.c | 33 +
arch/arm/mach-versal/cpu.c | 3 ++-
arch/arm/mach-zynqmp/cpu.c | 3 ++-
common/board_f.c | 29 ++---
include/init.h | 13 -
6 files changed, 62 insertions(+), 30 deletions(-)
--
2.17.1
[PATCH v6 14/17] sifive: dts: fu540: Enable L2 Cache in U-Boot
Add L2 cache node to enable cache ways from U-Boot
Signed-off-by: Pragnesh Patel
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 56a45371d4..8f6c9f525d 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -73,3 +73,7 @@
&qspi2 {
u-boot,dm-spl;
};
+
+&l2cache {
+ status = "okay";
+};
--
2.17.1
[PATCH v6 17/17] doc: update FU540 RISC-V documentation
Add descriptions about U-Boot SPL feature and how to build and run. Signed-off-by: Pragnesh Patel --- doc/board/sifive/fu540.rst | 409 ++--- 1 file changed, 385 insertions(+), 24 deletions(-) diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst index 3937222c6c..cf76b88ebc 100644 --- a/doc/board/sifive/fu540.rst +++ b/doc/board/sifive/fu540.rst @@ -42,8 +42,60 @@ Building export ARCH=riscv export CROSS_COMPILE= -3. make sifive_fu540_defconfig -4. make +User can use FSBL or u-boot-spl as the 1st stage bootloader. + +1) Use FSBL as the 1st stage bootloader + +.. code-block:: console + + git clone https://github.com/sifive/freedom-u540-c000-bootloader.git + cd freedom-u540-c000-bootloader + make + + cd + make sifive_fu540_defconfig + make + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= + +This will generate a fw_payload.bin (build/platform/sifive/fu540/firmware/fw_payload.bin) + +u-boot-dtb.bin is used as a payload of the OpenSBI FW_PAYLOAD firmware. + +More detailed description of steps required to build FW_PAYLOAD firmware +is beyond the scope of this document. Please refer OpenSBI documenation. +(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git) + +2) Use u-boot-spl as the 1st stage bootloader + +Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be +cloned and built for FU540 as below: + +.. code-block:: console + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=sifive/fu540 + +Copy OpenSBI FW_DYNAMIC image (build/platform/sifive/fu540/firmware/fw_dynamic.bin) +into U-Boot root directory + +.. code-block:: console + + cp build/platform/sifive/fu540/firmware/fw_dynamic.bin + +Now build the u-boot-spl and U-Boot proper + +.. code-block:: console + + cd + make sifive_fu540_defconfig + make + +This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb) + Flashing @@ -53,28 +105,55 @@ The current U-Boot port is supported in S-mode only and loaded from DRAM. A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to boot the u-boot.bin in S-mode and provide M-mode runtime services. -Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD -firmware. We need to compile OpenSBI with below command: +1) Use FSBL as the 1st stage bootloader + +ZSBL loads the FSBL (fsbl.bin) from a partition with GUID type +5B193300-FC78-40CD-8002-E86C45580B47 + +FSBL loads the fw_payload.bin from a partition with GUID type +2E54B353-1271-4842-806F-E436D6AF6985 + +Once the prior stage firmware/bootloader binary is generated, it should be +copied to the first partition of the sdcard. .. code-block:: none -make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= + sudo dd if=fsbl.bin of=/dev/disk2s4 bs=1024 + sudo dd if=fw_payload.bin of=/dev/disk2s1 bs=1024 -More detailed description of steps required to build FW_PAYLOAD firmware -is beyond the scope of this document. Please refer OpenSBI documenation. -(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git) +Assuming that /dev/disk2s4 partition is of GUID type +5B193300-FC78-40CD-8002-E86C45580B47 and /dev/disk2s1 partition +is of GUID type 2E54B353-1271-4842-806F-E436D6AF6985 + +2) Use u-boot-spl as the 1st stage bootloader + +ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type +5B193300-FC78-40CD-8002-E86C45580B47 + +U-boot SPL expects a U-Boot FIT image (u-boot.itb) from 1st partition (/dev/sdc1) +of SD card irrespective of GUID + +FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and +device tree blob (hifive-unleashed-a00.dtb) Once the prior stage firmware/bootloader binary is generated, it should be copied to the first partition of the sdcard. .. code-block:: none -sudo dd if= of=/dev/disk2s1 bs=1024 +sudo dd if=spl/u-boot-spl.bin of=/dev/disk2s4 bs=1024 +sudo dd if=u-boot.itb of=/dev/disk2s1 bs=1024 + +Assuming that /dev/disk2s4 partition is of GUID type +5B193300-FC78-40CD-8002-E86C45580B47 and /dev/disk2s1 is of +any GUID type raw partition. Booting --- Once you plugin the sdcard and power up, you should see the U-Boot prompt. +1) Use FSBL as the 1st stage bootloader + Sample boot log from HiFive Unleashed board --- @@ -145,19 +224,6 @@ load uImage. Filename '/sifive/fu540/Image'. Load address: 0x8400 Loading: # -# -# -# -# -
[PATCH v6 15/17] riscv: sifive: fu540: enable all cache ways from u-boot proper
Enable all cache ways from u-boot proper.
Signed-off-by: Pragnesh Patel
---
arch/riscv/fu540/Makefile | 3 +-
arch/riscv/fu540/cache.c| 58 +
arch/riscv/include/asm/arch-generic/cache.h | 14 +
board/sifive/fu540/fu540.c | 10 +++-
4 files changed, 81 insertions(+), 4 deletions(-)
create mode 100644 arch/riscv/fu540/cache.c
create mode 100644 arch/riscv/include/asm/arch-generic/cache.h
diff --git a/arch/riscv/fu540/Makefile b/arch/riscv/fu540/Makefile
index e3b40ae7d4..3f385e8529 100644
--- a/arch/riscv/fu540/Makefile
+++ b/arch/riscv/fu540/Makefile
@@ -6,6 +6,5 @@
ifeq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_TARGET_SIFIVE_FU540) += spl.o
else
-# necessary to create built-in.o
-obj- += __dummy__.o
+obj-y += cache.o
endif
diff --git a/arch/riscv/fu540/cache.c b/arch/riscv/fu540/cache.c
new file mode 100644
index 00..3eb71a06d4
--- /dev/null
+++ b/arch/riscv/fu540/cache.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#include
+#include
+#include
+
+#ifdef CONFIG_TARGET_SIFIVE_FU540
+/* Register offsets */
+#define CACHE_CONFIG 0x000
+#define CACHE_ENABLE 0x008
+
+#define MASK_NUM_WAYS GENMASK(15, 8)
+#define NUM_WAYS_SHIFT 8
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cache_enable_ways(void)
+{
+ const void *blob = gd->fdt_blob;
+ int node = (-FDT_ERR_NOTFOUND);
+ fdt_addr_t base;
+ u32 config;
+ u32 ways;
+
+ volatile u32 *enable;
+
+#ifdef CONFIG_TARGET_SIFIVE_FU540
+ node = fdt_node_offset_by_compatible(blob, -1,
+"sifive,fu540-c000-ccache");
+
+ if (node < 0)
+ return node;
+
+ base = fdtdec_get_addr(blob, node, "reg");
+ if (base == FDT_ADDR_T_NONE)
+ return FDT_ADDR_T_NONE;
+
+ config = readl((volatile u32 *)base + CACHE_CONFIG);
+ ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+ enable = (volatile u32 *)(base + CACHE_ENABLE);
+
+ /* memory barrier */
+ mb();
+ (*enable) = ways - 1;
+ /* memory barrier */
+ mb();
+#endif /* CONFIG_TARGET_SIFIVE_FU540 */
+
+ return 0;
+}
diff --git a/arch/riscv/include/asm/arch-generic/cache.h
b/arch/riscv/include/asm/arch-generic/cache.h
new file mode 100644
index 00..135a17c679
--- /dev/null
+++ b/arch/riscv/include/asm/arch-generic/cache.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#ifndef _CACHE_SIFIVE_H
+#define _CACHE_SIFIVE_H
+
+int cache_enable_ways(void);
+
+#endif /* _CACHE_SIFIVE_H */
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index d05529a86b..131fee8898 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/*
* This define is a value used for error/unknown serial.
@@ -111,8 +112,13 @@ int misc_init_r(void)
int board_init(void)
{
- /* For now nothing to do here. */
-
+ int ret;
+ /* enable all cache ways */
+ ret = cache_enable_ways();
+ if (ret) {
+ debug("%s: could not enable cache ways\n", __func__);
+ return ret;
+ }
return 0;
}
--
2.17.1
[PATCH v6 12/17] riscv: sifive: fu540: add SPL configuration
Add a support for SPL which will boot from L2 LIM (0x0800_) and
then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware
and U-Boot proper images from 1st partition of MMC boot devices.
SPL related code is leverage from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
arch/riscv/Makefile| 1 +
arch/riscv/fu540/Makefile | 11
arch/riscv/fu540/spl.c | 30 +
arch/riscv/include/asm/arch-generic/gpio.h | 3 +
arch/riscv/include/asm/arch-generic/spl.h | 14 +
board/sifive/fu540/Kconfig | 8 +++
board/sifive/fu540/Makefile| 4 ++
board/sifive/fu540/fu540.c | 24
board/sifive/fu540/spl.c | 72 ++
include/configs/sifive-fu540.h | 18 ++
10 files changed, 185 insertions(+)
create mode 100644 arch/riscv/fu540/Makefile
create mode 100644 arch/riscv/fu540/spl.c
create mode 100644 arch/riscv/include/asm/arch-generic/spl.h
create mode 100644 board/sifive/fu540/spl.c
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 0b80eb8d86..599ae8d77d 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -35,3 +35,4 @@ head-y := arch/riscv/cpu/start.o
libs-y += arch/riscv/cpu/
libs-y += arch/riscv/cpu/$(CPU)/
libs-y += arch/riscv/lib/
+libs-y += arch/riscv/fu540/
diff --git a/arch/riscv/fu540/Makefile b/arch/riscv/fu540/Makefile
new file mode 100644
index 00..e3b40ae7d4
--- /dev/null
+++ b/arch/riscv/fu540/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 SiFive, Inc
+# Pragnesh Patel
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_TARGET_SIFIVE_FU540) += spl.o
+else
+# necessary to create built-in.o
+obj- += __dummy__.o
+endif
diff --git a/arch/riscv/fu540/spl.c b/arch/riscv/fu540/spl.c
new file mode 100644
index 00..3d9dea5e30
--- /dev/null
+++ b/arch/riscv/fu540/spl.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ * Pragnesh Patel
+ */
+
+#include
+#include
+
+int soc_spl_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* PRCI init */
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ debug("Clock init failed: %d\n", ret);
+ return ret;
+ }
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/riscv/include/asm/arch-generic/gpio.h
b/arch/riscv/include/asm/arch-generic/gpio.h
index dfcb753051..0d16c59ca6 100644
--- a/arch/riscv/include/asm/arch-generic/gpio.h
+++ b/arch/riscv/include/asm/arch-generic/gpio.h
@@ -32,4 +32,7 @@ struct sifive_gpio_platdata {
void *base; /* address of registers in physical memory */
};
+#define SIFIVE_GENERIC_GPIO_NR(port, index) \
+ (((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
+
#endif /* _GPIO_SIFIVE_H */
diff --git a/arch/riscv/include/asm/arch-generic/spl.h
b/arch/riscv/include/asm/arch-generic/spl.h
new file mode 100644
index 00..0c188be747
--- /dev/null
+++ b/arch/riscv/include/asm/arch-generic/spl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#ifndef _SPL_SIFIVE_H
+#define _SPL_SIFIVE_H
+
+int soc_spl_init(void);
+
+#endif /* _SPL_SIFIVE_H */
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 900197bbb2..ebe3472f9a 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -13,12 +13,20 @@ config SYS_CONFIG_NAME
default "sifive-fu540"
config SYS_TEXT_BASE
+ default 0x8020 if SPL
default 0x8000 if !RISCV_SMODE
default 0x8020 if RISCV_SMODE
+config SPL_TEXT_BASE
+ default 0x0800
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x8000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+ select SUPPORT_SPL
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
index 6e1862c475..b05e2f5807 100644
--- a/board/sifive/fu540/Makefile
+++ b/board/sifive/fu540/Makefile
@@ -3,3 +3,7 @@
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 540638c919..d05529a86b 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
/*
* This define is a value used for error/unknown serial.
@@ -114,3 +115,26 @@ int board_init(void)
return 0;
}
+
+#ifdef CONFIG_SPL
+voi
[PATCH v6 13/17] configs: fu540: Add config options for U-Boot SPL
With sifive_fu540_defconfig: User can use FSBL or u-boot-spl.bin anyone at a time. For FSBL, fsbl->fw_payload.bin(opensbi+u-boot) For u-boot-spl.bin, u-boot-spl.bin->FIT image(opensbi+u-boot+dtb) U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT image u-boot.itb from 1st partition of SD card (replace fw_payload.bin with u-boot.itb) into RAM. U-Boot SPL expects u-boot.itb FIT image in the 1st partition of SD card irrespective of GUID Signed-off-by: Pragnesh Patel --- configs/sifive_fu540_defconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index 6d61e6c960..4fa4e1520f 100644 --- a/configs/sifive_fu540_defconfig +++ b/configs/sifive_fu540_defconfig @@ -12,3 +12,14 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SPL_CLK=y +CONFIG_SPL_PAYLOAD="u-boot.itb" +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SIFIVE_FU540_DDR=y -- 2.17.1
[PATCH v6 16/17] sifive: fix palmer's email address
Fix Palmer's email address Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng --- board/sifive/fu540/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS index 702d803ad8..5381fc0639 100644 --- a/board/sifive/fu540/MAINTAINERS +++ b/board/sifive/fu540/MAINTAINERS @@ -1,6 +1,6 @@ SiFive FU540 BOARD M: Paul Walmsley -M: Palmer Dabbelt +M: Palmer Dabbelt M: Anup Patel M: Atish Patra S: Maintained -- 2.17.1
[PATCH v6 10/17] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux
This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.
Signed-off-by: Pragnesh Patel
---
arch/riscv/dts/fu540-c000.dtsi | 37 -
arch/riscv/dts/hifive-unleashed-a00.dts | 9 ++
2 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi
index afa43c7ea3..7db8610534 100644
--- a/arch/riscv/dts/fu540-c000.dtsi
+++ b/arch/riscv/dts/fu540-c000.dtsi
@@ -54,6 +54,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -77,6 +78,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -100,6 +102,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -123,6 +126,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -162,6 +166,13 @@
clocks = <&prci PRCI_CLK_TLCLK>;
status = "disabled";
};
+ dma: dma@300 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x300 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <23 24 25 26 27 28 29 30>;
+ #dma-cells = <1>;
+ };
uart1: serial@10011000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
reg = <0x0 0x10011000 0x0 0x1000>;
@@ -246,6 +257,30 @@
#pwm-cells = <3>;
status = "disabled";
};
-
+ l2cache: cache-controller@201 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x201 0x0 0x1000>;
+ };
+ gpio: gpio@1006 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+<14>, <15>, <16>, <17>, <18>, <19>, <20>,
+<21>, <22>;
+ reg = <0x0 0x1006 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts
b/arch/riscv/dts/hifive-unleashed-a00.dts
index 88cfcb96bf..4a2729f5ca 100644
--- a/arch/riscv/dts/hifive-unleashed-a00.dts
+++ b/arch/riscv/dts/hifive-unleashed-a00.dts
@@ -2,6 +2,7 @@
/* Copyright (c) 2018-2019 SiFive, Inc */
#include "fu540-c000.dtsi"
+#include
/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
#define RTCCLK_FREQ100
@@ -41,6 +42,10 @@
clock-frequency = ;
clock-output-names = "rtcclk";
};
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ };
};
&uart0 {
@@ -94,3 +99,7 @@
&pwm1 {
status = "okay";
};
+
+&gpio {
+ status = "okay";
+};
--
2.17.1
[PATCH v6 11/17] sifive: dts: fu540: Enable gpio in U-Boot SPL
Add gpio node for U-Boot SPL
Signed-off-by: Pragnesh Patel
---
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index af8c3e904c..b83f6afe4f 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -21,3 +21,7 @@
u-boot,dm-spl;
};
};
+
+&gpio {
+ u-boot,dm-spl;
+};
--
2.17.1
[PATCH v6 09/17] clk: sifive: fu540-prci: Add clock initialization for SPL
Set corepll, ddrpll and ethernet PLL for u-boot-spl
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 118
1 file changed, 118 insertions(+)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index e6214cd821..3a73c2c8d1 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -41,6 +41,10 @@
#include
#include
+#define DDRCTLPLL_F55
+#define DDRCTLPLL_Q2
+#define MHz100
+
/*
* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
* hfclk and rtcclk
@@ -152,6 +156,27 @@
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
+/* PROCMONCFG */
+#define PRCI_PROCMONCFG_OFFSET 0xF0
+#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
+#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
+ (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
+
+#define PLL_R(x) \
+ ((x) << PRCI_DDRPLLCFG0_DIVR_SHIFT) & PRCI_DDRPLLCFG0_DIVR_MASK
+#define PLL_F(x) \
+ ((x) << PRCI_DDRPLLCFG0_DIVF_SHIFT) & PRCI_DDRPLLCFG0_DIVF_MASK
+#define PLL_Q(x) \
+ ((x) << PRCI_DDRPLLCFG0_DIVQ_SHIFT) & PRCI_DDRPLLCFG0_DIVQ_MASK
+#define PLL_RANGE(x) \
+ ((x) << PRCI_DDRPLLCFG0_RANGE_SHIFT) & PRCI_DDRPLLCFG0_RANGE_MASK
+#define PLL_BYPASS(x) \
+ ((x) << PRCI_DDRPLLCFG0_BYPASS_SHIFT) & PRCI_DDRPLLCFG0_BYPASS_MASK
+#define PLL_FSE(x) \
+ ((x) << PRCI_DDRPLLCFG0_FSE_SHIFT) & PRCI_DDRPLLCFG0_FSE_MASK
+#define PLL_LOCK(x) \
+ ((x) << PRCI_DDRPLLCFG0_LOCK_SHIFT) & PRCI_DDRPLLCFG0_LOCK_MASK
+
/*
* Private structures
*/
@@ -654,6 +679,93 @@ static int sifive_fu540_prci_disable(struct clk *clk)
return pc->ops->enable_clk(pc, 0);
}
+#ifdef CONFIG_SPL_BUILD
+static void corepll_init(struct udevice *dev)
+{
+ u32 v;
+ struct clk clock;
+ struct __prci_data *pd = dev_get_priv(dev);
+
+ v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
+ v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
+
+ clock.id = PRCI_CLK_COREPLL;
+
+ if (v) {
+ /* corepll 500 Mhz */
+ sifive_fu540_prci_set_rate(&clock, 500UL * MHz);
+ } else {
+ /* corepll 1 Ghz */
+ sifive_fu540_prci_set_rate(&clock, 1000UL * MHz);
+ }
+
+ sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
+}
+
+static void ddr_init(struct udevice *dev)
+{
+ u32 v;
+ struct clk clock;
+ struct __prci_data *pd = dev_get_priv(dev);
+
+ //DDR init
+ u32 ddrctlmhz =
+ (PLL_R(0)) |
+ (PLL_F(DDRCTLPLL_F)) |
+ (PLL_Q(DDRCTLPLL_Q)) |
+ (PLL_RANGE(0x4)) |
+ (PLL_BYPASS(0)) |
+ (PLL_FSE(1));
+ __prci_writel(ddrctlmhz, PRCI_DDRPLLCFG0_OFFSET, pd);
+
+ clock.id = PRCI_CLK_DDRPLL;
+ sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
+
+ /* Release DDR reset */
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ // HACK to get the '1 full controller clock cycle'.
+ asm volatile ("fence");
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK);
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+ // HACK to get the '1 full controller clock cycle'.
+ asm volatile ("fence");
+
+ /* These take like 16 cycles to actually propagate. We can't go sending
+* stuff before they come out of reset. So wait. (TODO: Add a register
+* to read the current reset states, or DDR Control device?)
+*/
+ for (int i = 0; i < 256; i++)
+ asm volatile ("nop");
+}
+
+static void ethernet_init(struct udevice *dev)
+{
+ u32 v;
+ struct clk clock;
+ struct __prci_data *pd = dev_get_priv(dev);
+
+ /* GEMGXL init */
+ clock.id = PRCI_CLK_GEMGXLPLL;
+ sifive_fu540_prci_set_rate(&clock, 125UL * MHz);
+ sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
+
+ /* Release GEMGXL reset */
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* Procmon => core clock */
+ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
+ pd);
+}
+#endif
+
static int sifive_fu540_prci_probe(struct udevice *dev)
{
int i, err;
@@ -679,6 +791,12 @@ static int sifive_fu540_prci_probe(struct udevice *dev)
__prci_wrpll_read_cfg0(pd, pc->pwd);
}
+#ifdef CONFIG_
[PATCH v6 06/17] sifive: fu540: add ddr driver
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
drivers/ram/Kconfig | 7 +
drivers/ram/Makefile | 2 +
drivers/ram/sifive/Kconfig | 8 +
drivers/ram/sifive/Makefile | 6 +
drivers/ram/sifive/sdram_fu540.c | 399 +++
5 files changed, 422 insertions(+)
create mode 100644 drivers/ram/sifive/Kconfig
create mode 100644 drivers/ram/sifive/Makefile
create mode 100644 drivers/ram/sifive/sdram_fu540.c
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 56fea7c94c..c60c63204c 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -73,5 +73,12 @@ config IMXRT_SDRAM
to support external memories like sdram, psram & nand.
This driver is for the sdram memory interface with the SEMC.
+config SIFIVE_DDR
+ bool "Enable SiFive DDR support"
+ depends on RAM
+ help
+ Enable support for the internal DDR Memory Controller of SiFive SoCs.
+
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
+source "drivers/ram/sifive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 5c897410c6..12bf61510b 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
+
+obj-$(CONFIG_SIFIVE_DDR) += sifive/
diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
new file mode 100644
index 00..b754700db8
--- /dev/null
+++ b/drivers/ram/sifive/Kconfig
@@ -0,0 +1,8 @@
+config SIFIVE_FU540_DDR
+ bool "SiFive FU540 DDR driver"
+ depends on DM && OF_CONTROL
+ select RAM
+ select SPL_RAM if SPL
+ select SIFIVE_DDR
+ help
+ This enables DDR support for the platforms based on SiFive FU540 SoC.
diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
new file mode 100644
index 00..0187805199
--- /dev/null
+++ b/drivers/ram/sifive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020 SiFive, Inc
+#
+
+obj-$(CONFIG_SIFIVE_FU540_DDR) += sdram_fu540.o
diff --git a/drivers/ram/sifive/sdram_fu540.c b/drivers/ram/sifive/sdram_fu540.c
new file mode 100644
index 00..6e6c551ced
--- /dev/null
+++ b/drivers/ram/sifive/sdram_fu540.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DENALI_CTL_0 0
+#define DENALI_CTL_21 21
+#define DENALI_CTL_120 120
+#define DENALI_CTL_132 132
+#define DENALI_CTL_136 136
+#define DENALI_CTL_170 170
+#define DENALI_CTL_181 181
+#define DENALI_CTL_182 182
+#define DENALI_CTL_184 184
+#define DENALI_CTL_208 208
+#define DENALI_CTL_209 209
+#define DENALI_CTL_210 210
+#define DENALI_CTL_212 212
+#define DENALI_CTL_214 214
+#define DENALI_CTL_216 216
+#define DENALI_CTL_224 224
+#define DENALI_CTL_225 225
+#define DENALI_CTL_260 260
+
+#define DENALI_PHY_11521152
+#define DENALI_PHY_12141214
+
+#define PAYLOAD_DEST 0x8000
+#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL)
+
+#define DRAM_CLASS_OFFSET 8
+#define DRAM_CLASS_DDR40xA
+#define OPTIMAL_RMODW_EN_OFFSET0
+#define DISABLE_RD_INTERLEAVE_OFFSET 16
+#define OUT_OF_RANGE_OFFSET1
+#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
+#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
+#define MC_INIT_COMPLETE_OFFSET8
+#define LEVELING_OPERATION_COMPLETED_OFFSET22
+#define DFI_PHY_WRLELV_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
+#define VREF_EN_OFFSET 24
+#define PORT_ADDR_PROTECTION_EN_OFFSET 0
+#define AXI0_ADDRESS_RANGE_ENABLE 8
+#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
+#define RDLVL_EN_OFFSET16
+#define RDLVL_GATE_EN_OFFSET 24
+#define WRLVL_EN_OFFSET0
+
+#define PHY_RX_CAL_DQ0_0_OFFSET0
+#define PHY_RX_CAL_DQ1_0_OFFSET16
+
+struct fu540_ddrctl {
+ volatile u32 denali_ctl[265];
+};
+
+struct fu540_ddrphy {
+ volatile u32 denali_phy[1215];
+};
+
+/**
+ * struct ddr_info
+ *
+ * @dev : pointer for the device
+ * @info: UCLASS RAM information
+ * @ctl : DDR controller base address
+ * @phy : DDR PHY base address
+ * @ctrl: DDR control base address
+ * @p
[PATCH v6 07/17] sifive: dts: fu540: Add DDR controller and phy register settings
Add DDR controller and phy register settings, taken from fsbl
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
arch/riscv/dts/fu540-c000-u-boot.dtsi |7 +
...fu540-hifive-unleashed-a00-sdram-ddr4.dtsi | 1489 +
.../dts/hifive-unleashed-a00-u-boot.dtsi |1 +
3 files changed, 1497 insertions(+)
create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 387b13bdfb..56a45371d4 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -52,6 +52,13 @@
reg = <0x0 0x200 0x0 0xc>;
u-boot,dm-spl;
};
+ dmc: dmc@100b {
+ compatible = "sifive,fu540-c000-ddr";
+ reg = <0x0 0x100b 0x0 0x0800
+ 0x0 0x100b2000 0x0 0x2000
+ 0x0 0x100b8000 0x0 0x0fff>;
+ u-boot,dm-spl;
+ };
};
};
diff --git a/arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi
b/arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi
new file mode 100644
index 00..370c53800d
--- /dev/null
+++ b/arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 SiFive, Inc
+ */
+
+&dmc {
+ sifive,sdram-params = <
+ 0x0a00 /* DENALI_CTL_00_DATA */
+ 0x /* DENALI_CTL_01_DATA */
+ 0x /* DENALI_CTL_02_DATA */
+ 0x /* DENALI_CTL_03_DATA */
+ 0x /* DENALI_CTL_04_DATA */
+ 0x /* DENALI_CTL_05_DATA */
+ 0x000a /* DENALI_CTL_06_DATA */
+ 0x0002d362 /* DENALI_CTL_07_DATA */
+ 0x00071073 /* DENALI_CTL_08_DATA */
+ 0x0a1c0255 /* DENALI_CTL_09_DATA */
+ 0x1c1c0400 /* DENALI_CTL_10_DATA */
+ 0x0404990b /* DENALI_CTL_11_DATA */
+ 0x2b050405 /* DENALI_CTL_12_DATA */
+ 0x0e0c081e /* DENALI_CTL_13_DATA */
+ 0x08090914 /* DENALI_CTL_14_DATA */
+ 0x00fde718 /* DENALI_CTL_15_DATA */
+ 0x00180a05 /* DENALI_CTL_16_DATA */
+ 0x008b130e /* DENALI_CTL_17_DATA */
+ 0x01000118 /* DENALI_CTL_18_DATA */
+ 0x0e032101 /* DENALI_CTL_19_DATA */
+ 0x /* DENALI_CTL_20_DATA */
+ 0x0101 /* DENALI_CTL_21_DATA */
+ 0x /* DENALI_CTL_22_DATA */
+ 0x0a00 /* DENALI_CTL_23_DATA */
+ 0x /* DENALI_CTL_24_DATA */
+ 0x01450100 /* DENALI_CTL_25_DATA */
+ 0x1c36 /* DENALI_CTL_26_DATA */
+ 0x0005 /* DENALI_CTL_27_DATA */
+ 0x00170006 /* DENALI_CTL_28_DATA */
+ 0x014e0300 /* DENALI_CTL_29_DATA */
+ 0x0301 /* DENALI_CTL_30_DATA */
+ 0x000a0e00 /* DENALI_CTL_31_DATA */
+ 0x04030200 /* DENALI_CTL_32_DATA */
+ 0x031f /* DENALI_CTL_33_DATA */
+ 0x00070004 /* DENALI_CTL_34_DATA */
+ 0x /* DENALI_CTL_35_DATA */
+ 0x /* DENALI_CTL_36_DATA */
+ 0x /* DENALI_CTL_37_DATA */
+ 0x /* DENALI_CTL_38_DATA */
+ 0x /* DENALI_CTL_39_DATA */
+ 0x /* DENALI_CTL_40_DATA */
+ 0x /* DENALI_CTL_41_DATA */
+ 0x /* DENALI_CTL_42_DATA */
+ 0x /* DENALI_CTL_43_DATA */
+ 0x /* DENALI_CTL_44_DATA */
+ 0x /* DENALI_CTL_45_DATA */
+ 0x /* DENALI_CTL_46_DATA */
+ 0x /* DENALI_CTL_47_DATA */
+ 0x /* DENALI_CTL_48_DATA */
+ 0x /* DENALI_CTL_49_DATA */
+ 0x /* DENALI_CTL_50_DATA */
+ 0x /* DENALI_CTL_51_DATA */
+ 0x /* DENALI_CTL_52_DATA */
+ 0x /* DENALI_CTL_53_DATA */
+ 0x /* DENALI_CTL_54_DATA */
+ 0x /* DENALI_CTL_55_DATA */
+ 0x /* DENALI_CTL_56_DATA */
+ 0x /* DENALI_CTL_57_DATA */
+ 0x /* DENALI_CTL_58_DATA */
+ 0x /* DENALI_CTL_59_DATA */
+ 0x0
[PATCH v6 08/17] clk: sifive: fu540-prci: Add clock enable and disable ops
Added clock enable and disable functions in prci ops
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 100
1 file changed, 88 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 8847178001..e6214cd821 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -68,6 +68,11 @@
#define PRCI_COREPLLCFG0_LOCK_SHIFT31
#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
+/* COREPLLCFG1 */
+#define PRCI_COREPLLCFG1_OFFSET0x8
+#define PRCI_COREPLLCFG1_CKE_SHIFT 31
+#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
+
/* DDRPLLCFG0 */
#define PRCI_DDRPLLCFG0_OFFSET 0xc
#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
@@ -87,7 +92,7 @@
/* DDRPLLCFG1 */
#define PRCI_DDRPLLCFG1_OFFSET 0x10
-#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
+#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* GEMGXLPLLCFG0 */
@@ -114,7 +119,7 @@
/* GEMGXLPLLCFG1 */
#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
#define PRCI_GEMGXLPLLCFG1_CKE_MASK(0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
/* CORECLKSEL */
@@ -142,7 +147,7 @@
(0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
/* CLKMUXSTATUSREG */
-#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
+#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
@@ -170,6 +175,7 @@ struct __prci_data {
* @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else
NULL)
* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
+ * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
*
* @enable_bypass and @disable_bypass are used for WRPLL instances
* that contain a separate external glitchless clock mux downstream
@@ -180,6 +186,7 @@ struct __prci_wrpll_data {
void (*enable_bypass)(struct __prci_data *pd);
void (*disable_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
+ u8 cfg1_offs;
};
struct __prci_clock;
@@ -194,6 +201,7 @@ struct __prci_clock_ops {
unsigned long *parent_rate);
unsigned long (*recalc_rate)(struct __prci_clock *pc,
unsigned long parent_rate);
+ int (*enable_clk)(struct __prci_clock *pc, bool enable);
};
/**
@@ -316,7 +324,7 @@ static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
}
/**
- * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
+ * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
* @pd: PRCI context
* @pwd: PRCI WRPLL metadata
*
@@ -327,14 +335,14 @@ static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
* Context: Any context. Caller must prevent the records pointed to by
* @pd and @pwd from changing during execution.
*/
-static void __prci_wrpll_read_cfg(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd)
+static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd)
{
__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
}
/**
- * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
+ * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
* @pd: PRCI context
* @pwd: PRCI WRPLL metadata
* @c: WRPLL configuration record to write
@@ -347,15 +355,29 @@ static void __prci_wrpll_read_cfg(struct __prci_data *pd,
* Context: Any context. Caller must prevent the records pointed to by
* @pd and @pwd from changing during execution.
*/
-static void __prci_wrpll_write_cfg(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd,
- struct wrpll_cfg *c)
+static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ struct wrpll_cfg *c)
{
__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
memcpy(&pwd->c, c, sizeof(*c));
}
+/**
+ * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
+ * into the PRCI
+ * @pd: PRCI context
+ * @pwd: PRCI WRPLL metadata
+ * @enable: Clock enable or disable value
+ */
+static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ u32 enable)
+{
+ __prci_writel(enable,
[PATCH v6 03/17] riscv: Add _image_binary_end for SPL
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
Reviewed-by: Jagan Teki
---
arch/riscv/cpu/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 955dd3106d..d0495ce248 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -72,6 +72,7 @@ SECTIONS
. = ALIGN(4);
_end = .;
+ _image_binary_end = .;
.bss : {
__bss_start = .;
--
2.17.1
[PATCH v6 04/17] lib: Makefile: build crc7.c when CONFIG_MMC_SPI
When build U-Boot SPL, meet an issue of undefined reference to 'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when CONFIG_MMC_SPI selected. Signed-off-by: Pragnesh Patel --- common/spl/Kconfig | 6 ++ drivers/mmc/Kconfig | 1 + lib/Makefile| 1 + 3 files changed, 8 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index b03a476b9f..07eee56219 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -401,6 +401,12 @@ config SPL_CRC32_SUPPORT for detected accidental image corruption. For secure applications you should consider SHA1 or SHA256. +config SPL_CRC7_SUPPORT + bool "Support CRC7" + help + Enable CRC7 hashing for drivers which are using in SPL. + This is a 32-bit checksum value that can be used to verify images. + config SPL_MD5_SUPPORT bool "Support MD5" depends on SPL_FIT diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 2f0eedc22f..f23a3242b3 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -49,6 +49,7 @@ if MMC config MMC_SPI bool "Support for SPI-based MMC controller" depends on DM_MMC && DM_SPI + select SPL_CRC7_SUPPORT if SPL help This selects SPI-based MMC controllers. If you have an MMC controller on a SPI bus, say Y here. diff --git a/lib/Makefile b/lib/Makefile index 15259d0473..7a50aa56ef 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -78,6 +78,7 @@ endif ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o +obj-$(CONFIG_SPL_CRC7_SUPPORT) += crc7.o obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o obj-y += net_utils.o endif -- 2.17.1
[PATCH v6 02/17] riscv: sifive: fu540: Use OTP DM driver for serial environment variable
Use the OTP DM driver to set the serial environment variable.
Signed-off-by: Pragnesh Patel
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 6 +
board/sifive/fu540/Kconfig| 2 +
board/sifive/fu540/fu540.c| 111 ++
4 files changed, 61 insertions(+), 72 deletions(-)
create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
new file mode 100644
index 00..db55773bd2
--- /dev/null
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2019 SiFive, Inc
+ */
+
+/ {
+ soc {
+ otp: otp@1007 {
+ compatible = "sifive,fu540-c000-otp";
+ reg = <0x0 0x1007 0x0 0x0FFF>;
+ fuse-count = <0x1000>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
new file mode 100644
index 00..f1735c1385
--- /dev/null
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 SiFive, Inc
+ */
+
+#include "fu540-c000-u-boot.dtsi"
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 5ca21474de..900197bbb2 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -48,5 +48,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SIFIVE_GPIO
imply CMD_GPIO
imply SMP
+ imply MISC
+ imply SIFIVE_OTP
endif
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 47a2090251..540638c919 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -10,94 +10,61 @@
#include
#include
#include
+#include
+
+/*
+ * This define is a value used for error/unknown serial.
+ * If we really care about distinguishing errors and 0 is
+ * valid, we'll need a different one.
+ */
+#define ERROR_READING_SERIAL_NUMBER 0
#ifdef CONFIG_MISC_INIT_R
-#define FU540_OTP_BASE_ADDR0x1007
-
-struct fu540_otp_regs {
- u32 pa; /* Address input */
- u32 paio; /* Program address input */
- u32 pas;/* Program redundancy cell selection input */
- u32 pce;/* OTP Macro enable input */
- u32 pclk; /* Clock input */
- u32 pdin; /* Write data input */
- u32 pdout; /* Read data output */
- u32 pdstb; /* Deep standby mode enable input (active low) */
- u32 pprog; /* Program mode enable input */
- u32 ptc;/* Test column enable input */
- u32 ptm;/* Test mode enable input */
- u32 ptm_rep;/* Repair function test mode enable input */
- u32 ptr;/* Test row enable input */
- u32 ptrim; /* Repair function enable input */
- u32 pwe;/* Write enable input (defines program cycle) */
-} __packed;
-
-#define BYTES_PER_FUSE 4
-#define NUM_FUSES 0x1000
-
-static int fu540_otp_read(int offset, void *buf, int size)
+#if CONFIG_IS_ENABLED(SIFIVE_OTP)
+static u32 otp_read_serialnum(struct udevice *dev)
{
- struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR;
- unsigned int i;
- int fuseidx = offset / BYTES_PER_FUSE;
- int fusecount = size / BYTES_PER_FUSE;
- u32 fusebuf[fusecount];
-
- /* check bounds */
- if (offset < 0 || size < 0)
- return -EINVAL;
- if (fuseidx >= NUM_FUSES)
- return -EINVAL;
- if ((fuseidx + fusecount) > NUM_FUSES)
- return -EINVAL;
+ int ret;
+ u32 serial[2] = {0};
- /* init OTP */
- writel(0x01, ®s->pdstb); /* wake up from stand-by */
- writel(0x01, ®s->ptrim); /* enable repair function */
- writel(0x01, ®s->pce); /* enable input */
-
- /* read all requested fuses */
- for (i = 0; i < fusecount; i++, fuseidx++) {
- writel(fuseidx, ®s->pa);
-
- /* cycle clock to read */
- writel(0x01, ®s->pclk);
- mdelay(1);
- writel(0x00, ®s->pclk);
- mdelay(1);
-
- /* read the value */
- fusebuf[i] = readl(®s->pdout);
- }
+ for (int i = 0xfe * 4; i > 0; i -= 8) {
+ ret = misc_read(dev, i, serial, sizeof(serial));
- /* shut down */
- writel(0, ®s->pce);
- writel(0, ®s->ptrim);
- writel(0, ®s->pdstb);
+ if (ret != sizeof(serial)) {
+ printf("%s: error reading serial from OTP\n", __func__);
+ break;
+ }
- /* copy out */
- memcpy(buf, fusebu
[PATCH v6 05/17] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 54 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 16 ++
2 files changed, 70 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index db55773bd2..387b13bdfb 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -4,11 +4,65 @@
*/
/ {
+ cpus {
+ u-boot,dm-spl;
+ cpu0: cpu@0 {
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu1: cpu@1 {
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu2: cpu@2 {
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+u-boot,dm-spl;
+ };
+ };
+ cpu3: cpu@3 {
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu4: cpu@4 {
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
soc {
+ u-boot,dm-spl;
otp: otp@1007 {
compatible = "sifive,fu540-c000-otp";
reg = <0x0 0x1007 0x0 0x0FFF>;
fuse-count = <0x1000>;
};
+ clint@200 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
+ reg = <0x0 0x200 0x0 0xc>;
+ u-boot,dm-spl;
+ };
};
};
+
+&prci {
+ u-boot,dm-spl;
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&qspi2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index f1735c1385..efa7cbb75d 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -4,3 +4,19 @@
*/
#include "fu540-c000-u-boot.dtsi"
+
+/ {
+ hfclk {
+ u-boot,dm-spl;
+ };
+
+ rtcclk {
+ u-boot,dm-spl;
+ };
+};
+
+&qspi2 {
+ mmc@0 {
+ u-boot,dm-spl;
+ };
+};
--
2.17.1
[PATCH v6 01/17] misc: add driver for the SiFive otp controller
Added a misc driver to handle OTP memory in SiFive SoCs.
Signed-off-by: Pragnesh Patel
---
drivers/misc/Kconfig | 7 ++
drivers/misc/Makefile | 1 +
drivers/misc/sifive-otp.c | 255 ++
3 files changed, 263 insertions(+)
create mode 100644 drivers/misc/sifive-otp.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f18aa8f7ba..5caf61d077 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -68,6 +68,13 @@ config ROCKCHIP_OTP
addressing and a length or through child-nodes that are generated
based on the e-fuse map retrieved from the DTS.
+config SIFIVE_OTP
+ bool "SiFive eMemory OTP driver"
+ depends on RISCV && MISC
+ help
+ Enable support for reading and writing the eMemory OTP on the
+ SiFive SoCs.
+
config VEXPRESS_CONFIG
bool "Enable support for Arm Versatile Express config bus"
depends on MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 2b843de93c..ee888631b6 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
+obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
diff --git a/drivers/misc/sifive-otp.c b/drivers/misc/sifive-otp.c
new file mode 100644
index 00..c1c2386b97
--- /dev/null
+++ b/drivers/misc/sifive-otp.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
+ * One-Time-Programmable (OTP) memory used within the SiFive FU540.
+ * It is documented in the FU540 manual here:
+ * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
+ *
+ * Copyright (C) 2018 Philipp Hug
+ * Copyright (C) 2018 Joey Hewitt
+ *
+ * Copyright (C) 2020 SiFive, Inc
+ */
+
+/*
+ * The FU540 stores 4096x32 bit (16KiB) values.
+ * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
+ * Right now first 1KiB is used to store only serial number.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define BYTES_PER_FUSE 4
+
+#define PA_RESET_VAL 0x00
+#define PAS_RESET_VAL 0x00
+#define PAIO_RESET_VAL 0x00
+#define PDIN_RESET_VAL 0x00
+#define PTM_RESET_VAL 0x00
+
+#define PCLK_ENABLE_VALBIT(0)
+#define PCLK_DISABLE_VAL 0x00
+
+#define PWE_WRITE_ENABLE BIT(0)
+#define PWE_WRITE_DISABLE 0x00
+
+#define PTM_FUSE_PROGRAM_VAL BIT(1)
+
+#define PCE_ENABLE_INPUT BIT(0)
+#define PCE_DISABLE_INPUT 0x00
+
+#define PPROG_ENABLE_INPUT BIT(0)
+#define PPROG_DISABLE_INPUT0x00
+
+#define PTRIM_ENABLE_INPUT BIT(0)
+#define PTRIM_DISABLE_INPUT0x00
+
+#define PDSTB_DEEP_STANDBY_ENABLE BIT(0)
+#define PDSTB_DEEP_STANDBY_DISABLE 0x00
+
+struct sifive_otp_regs {
+ u32 pa; /* Address input */
+ u32 paio; /* Program address input */
+ u32 pas;/* Program redundancy cell selection input */
+ u32 pce;/* OTP Macro enable input */
+ u32 pclk; /* Clock input */
+ u32 pdin; /* Write data input */
+ u32 pdout; /* Read data output */
+ u32 pdstb; /* Deep standby mode enable input (active low) */
+ u32 pprog; /* Program mode enable input */
+ u32 ptc;/* Test column enable input */
+ u32 ptm;/* Test mode enable input */
+ u32 ptm_rep;/* Repair function test mode enable input */
+ u32 ptr;/* Test row enable input */
+ u32 ptrim; /* Repair function enable input */
+ u32 pwe;/* Write enable input (defines program cycle) */
+};
+
+struct sifive_otp_platdata {
+ struct sifive_otp_regs __iomem *regs;
+ u32 total_fuses;
+};
+
+/*
+ * offset and size are assumed aligned to the size of the fuses (32-bit).
+ */
+static int sifive_otp_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
+
+ /* Check if offset and size are multiple of BYTES_PER_FUSE */
+ if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
+ printf("%s: size and offset must be multiple of 4.\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ int fuseidx = offset / BYTES_PER_FUSE;
+ int fusecount = size / BYTES_PER_FUSE;
+
+ /* check bounds */
+ if (offset < 0 || size < 0)
+ return -EINVAL;
+ if (fuseidx >= plat->total_fuses)
+ return -EINVAL;
+
[PATCH v6 00/17] RISC-V SiFive FU540 support SPL
This series add support for SPL to FU540.U-Boot SPL can boot from L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. How to test this patch: 1) Go to OpenSBI-dir : make PLATFORM=sifive/fu540 O=build_dir I=install_dir FW_DYNAMIC=y install 2) cp install_dir/platform/sifive/fu540/firmware/fw_dynamic.bin / 3) Change to u-boot-dir 4) make sifive_fu540_defconfig 5) make all 6) ZSBL loads the U-boot SPL(u-boot-spl.bin) from a partition with GUID type 5B193300-FC78-40CD-8002-E86C45580B47 sudo dd if=spl/u-boot-spl.bin of=/dev/sdc4 bs=1M 7) U-boot SPL expects a u-boot FIT image(u-boot.itb) from 1st partition(/dev/sdc1) of SD card irrespective of GUID sudo dd if=u-boot.itb of=/dev/sdc1 bs=1M Thanks to Yash Shah for testing the series. Changes in v6: - Typo Correction - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi Dual Licensed - Sync Hifive unleashed dts from Linux - Add arch/riscv/fu540 for FU540 specific code Changes in v5: - Return read/write bytes for sifive_otp_read and sifive_otp_write - Correct Palmer's email address Changes in v4: - Split misc DM driver patch into multiple patches - Added new SPL_CRC7_SUPPORT Kconfig option - Added DM driver for DDR - Added clk_enable and clk_disable ops in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added SPL config options in sifive_fu540_defconfig instead of creatiing a new config file for SPL - Update fu540.rst on how to build and flash U-boot SPL Changes in v3: - Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/ - Split SPL patches into DDR and SPL and spl defconfig - Update fu540/MAINTAINERS file - Update fu540.rst on how to build and flash U-boot SPL Changes in v2: - Add DM driver Sifive OTP - Split SPL patches into multiple patches - Add a seprate patch for _image_binary_end and crc7.c - Add a seprate patch to add board -u-boot.dtsi files - Update FU540 RISC-V documentation Pragnesh Patel (17): misc: add driver for the SiFive otp controller riscv: sifive: fu540: Use OTP DM driver for serial environment variable riscv: Add _image_binary_end for SPL lib: Makefile: build crc7.c when CONFIG_MMC_SPI riscv: sifive: dts: fu540: Add board -u-boot.dtsi files sifive: fu540: add ddr driver sifive: dts: fu540: Add DDR controller and phy register settings clk: sifive: fu540-prci: Add clock enable and disable ops clk: sifive: fu540-prci: Add clock initialization for SPL riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux sifive: dts: fu540: Enable gpio in U-Boot SPL riscv: sifive: fu540: add SPL configuration configs: fu540: Add config options for U-Boot SPL sifive: dts: fu540: Enable L2 Cache in U-Boot riscv: sifive: fu540: enable all cache ways from u-boot proper sifive: fix palmer's email address doc: update FU540 RISC-V documentation arch/riscv/Makefile |1 + arch/riscv/cpu/u-boot-spl.lds |1 + arch/riscv/dts/fu540-c000-u-boot.dtsi | 79 + arch/riscv/dts/fu540-c000.dtsi| 37 +- ...fu540-hifive-unleashed-a00-sdram-ddr4.dtsi | 1489 + .../dts/hifive-unleashed-a00-u-boot.dtsi | 27 + arch/riscv/dts/hifive-unleashed-a00.dts |9 + arch/riscv/fu540/Makefile | 10 + arch/riscv/fu540/cache.c | 58 + arch/riscv/fu540/spl.c| 30 + arch/riscv/include/asm/arch-generic/cache.h | 14 + arch/riscv/include/asm/arch-generic/gpio.h|3 + arch/riscv/include/asm/arch-generic/spl.h | 14 + board/sifive/fu540/Kconfig| 10 + board/sifive/fu540/MAINTAINERS|2 +- board/sifive/fu540/Makefile |4 + board/sifive/fu540/fu540.c| 143 +- board/sifive/fu540/spl.c | 72 + common/spl/Kconfig|6 + configs/sifive_fu540_defconfig| 11 + doc/board/sifive/fu540.rst| 409 - drivers/clk/sifive/fu540-prci.c | 218 ++- drivers/misc/Kconfig |7 + drivers/misc/Makefile |1 + drivers/misc/sifive-otp.c | 255 +++ drivers/mmc/Kconfig |1 + drivers/ram/Kconfig |7 + drivers/ram/Makefile |2 + drivers/ram/sifive/Kconfig|8 + drivers/ram/sifive/Makefile |6 + drivers/ram/sifive/sdram_fu540.c | 399 + include/configs/sifive-fu540.h| 18 + lib/Makefile |1 + 33 files changed, 3241 insertions(+), 111 deletions(-) create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi create mode 100
[PATCH 3/3] dm: core: refactor functions reading an u32 from dt
Now reading a 32 bit value from a device-tree property can be expressed
as reading the first element of an array with a single value.
Signed-off-by: Dario Binacchi
---
drivers/core/of_access.c | 16 +---
drivers/core/ofnode.c| 23 ++-
2 files changed, 3 insertions(+), 36 deletions(-)
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 55e4a38fc5..d116d106d9 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -449,21 +449,7 @@ static void *of_find_property_value_of_size(const struct
device_node *np,
int of_read_u32(const struct device_node *np, const char *propname, u32 *outp)
{
- const __be32 *val;
-
- debug("%s: %s: ", __func__, propname);
- if (!np)
- return -EINVAL;
- val = of_find_property_value_of_size(np, propname, sizeof(*outp));
- if (IS_ERR(val)) {
- debug("(not found)\n");
- return PTR_ERR(val);
- }
-
- *outp = be32_to_cpup(val);
- debug("%#x (%d)\n", *outp, *outp);
-
- return 0;
+ return of_read_u32_index(np, propname, 0, outp);
}
int of_read_u32_array(const struct device_node *np, const char *propname,
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 5bc3b02996..b0be7cbe19 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -18,32 +18,13 @@
int ofnode_read_u32(ofnode node, const char *propname, u32 *outp)
{
- assert(ofnode_valid(node));
- debug("%s: %s: ", __func__, propname);
-
- if (ofnode_is_np(node)) {
- return of_read_u32(ofnode_to_np(node), propname, outp);
- } else {
- const fdt32_t *cell;
- int len;
-
- cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node),
- propname, &len);
- if (!cell || len < sizeof(int)) {
- debug("(not found)\n");
- return -EINVAL;
- }
- *outp = fdt32_to_cpu(cell[0]);
- }
- debug("%#x (%d)\n", *outp, *outp);
-
- return 0;
+ return ofnode_read_u32_index(node, propname, 0, outp);
}
u32 ofnode_read_u32_default(ofnode node, const char *propname, u32 def)
{
assert(ofnode_valid(node));
- ofnode_read_u32(node, propname, &def);
+ ofnode_read_u32_index(node, propname, 0, &def);
return def;
}
--
2.17.1
[PATCH 2/3] dm: core: support reading a single indexed u32 value
The patch adds helper functions to allow reading a single indexed u32
value from a device-tree property containing multiple u32 values, that
is an array of integers.
Signed-off-by: Dario Binacchi
---
arch/sandbox/dts/test.dts | 1 +
drivers/core/of_access.c | 22 +
drivers/core/ofnode.c | 40 +++
drivers/core/read.c | 13 +
include/dm/of_access.h| 19 +++
include/dm/ofnode.h | 25
include/dm/read.h | 40 +++
test/dm/test-fdt.c| 29
8 files changed, 189 insertions(+)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 6664adb385..270eb3d87d 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -94,6 +94,7 @@
int-value = <1234>;
uint-value = <(-1234)>;
int64-value = /bits/ 64 <0x>;
+ int-array = <5678 9123 4567>;
interrupts-extended = <&irq 3 0>;
};
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index acd745c121..55e4a38fc5 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -485,6 +485,28 @@ int of_read_u32_array(const struct device_node *np, const
char *propname,
return 0;
}
+int of_read_u32_index(const struct device_node *np, const char *propname,
+ int index, u32 *outp)
+{
+ const __be32 *val;
+
+ debug("%s: %s: ", __func__, propname);
+ if (!np)
+ return -EINVAL;
+
+ val = of_find_property_value_of_size(np, propname,
+sizeof(*outp) * (index + 1));
+ if (IS_ERR(val)) {
+ debug("(not found)\n");
+ return PTR_ERR(val);
+ }
+
+ *outp = be32_to_cpup(val + index);
+ debug("%#x (%d)\n", *outp, *outp);
+
+ return 0;
+}
+
int of_read_u64(const struct device_node *np, const char *propname, u64 *outp)
{
const __be64 *val;
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 96a5dd20bd..5bc3b02996 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -48,6 +48,46 @@ u32 ofnode_read_u32_default(ofnode node, const char
*propname, u32 def)
return def;
}
+int ofnode_read_u32_index(ofnode node, const char *propname, int index,
+ u32 *outp)
+{
+ const fdt32_t *cell;
+ int len;
+
+ assert(ofnode_valid(node));
+ debug("%s: %s: ", __func__, propname);
+
+ if (ofnode_is_np(node))
+ return of_read_u32_index(ofnode_to_np(node), propname, index,
+outp);
+
+ cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname,
+ &len);
+ if (!cell) {
+ debug("(not found)\n");
+ return -EINVAL;
+ }
+
+ if (len < (sizeof(int) * (index + 1))) {
+ debug("(not large enough)\n");
+ return -EOVERFLOW;
+ }
+
+ *outp = fdt32_to_cpu(cell[index]);
+ debug("%#x (%d)\n", *outp, *outp);
+
+ return 0;
+}
+
+u32 ofnode_read_u32_index_default(ofnode node, const char *propname, int index,
+ u32 def)
+{
+ assert(ofnode_valid(node));
+ ofnode_read_u32_index(node, propname, index, &def);
+
+ return def;
+}
+
int ofnode_read_s32_default(ofnode node, const char *propname, s32 def)
{
assert(ofnode_valid(node));
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 1f999b1b31..ce78f09d28 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -22,6 +22,19 @@ int dev_read_u32_default(const struct udevice *dev, const
char *propname,
return ofnode_read_u32_default(dev_ofnode(dev), propname, def);
}
+int dev_read_u32_index(struct udevice *dev, const char *propname, int index,
+ u32 *outp)
+{
+ return ofnode_read_u32_index(dev_ofnode(dev), propname, index, outp);
+}
+
+u32 dev_read_u32_index_default(struct udevice *dev, const char *propname,
+ int index, u32 def)
+{
+ return ofnode_read_u32_index_default(dev_ofnode(dev), propname, index,
+def);
+}
+
int dev_read_s32(const struct udevice *dev, const char *propname, s32 *outp)
{
return ofnode_read_u32(dev_ofnode(dev), propname, (u32 *)outp);
diff --git a/include/dm/of_access.h b/include/dm/of_access.h
index 13fedb7cf5..92876b3ecb 100644
--- a/include/dm/of_access.h
+++ b/include/dm/of_access.h
@@ -234,6 +234,25 @@ struct device_node *of_find_node_by_phandle(phandle
handle);
*/
int of_read_u32(const struct device_node *np, const char *propname, u32 *outp);
+/**
+ * of_read_u32_index() - Find and read a 32-bit value from a multi-value
+ * property
+ *
[PATCH 0/3] Support reading an u32 from a multi-value property
The main part of the series consists of adding the dev_read_u32_index and dev_read_u32_index_default functions. During implementation and testing I noticed the lack of testing for the 64-bit data access functions. I decided to add the 64-bit test patch to the series to avoid merge conflicts that could have occurred with the submission of a single separated patch. In fact, it also contains changes to the test/dm/test-fdt.c file. If this series is accepted, it will be possible to evaluate the addition of functions for indexed access also for the dev_read_s32 and dev_read_u32u functions. Maybe to add in a second version of this series. Dario Binacchi (3): dm: test: add test case for dev_read_u64 function dm: core: support reading a single indexed u32 value dm: core: refactor functions reading an u32 from dt arch/sandbox/dts/test.dts | 2 ++ drivers/core/of_access.c | 38 ++ drivers/core/ofnode.c | 49 --- drivers/core/read.c | 13 +++ include/dm/of_access.h| 19 +++ include/dm/ofnode.h | 25 include/dm/read.h | 40 include/test/ut.h | 16 + test/dm/test-fdt.c| 39 +++ 9 files changed, 212 insertions(+), 29 deletions(-) -- 2.17.1
[PATCH 1/3] dm: test: add test case for dev_read_u64 function
Add test case to cover dev_read_u64 and dev_read_u64_default functions.
Signed-off-by: Dario Binacchi
---
arch/sandbox/dts/test.dts | 1 +
include/test/ut.h | 16
test/dm/test-fdt.c| 10 ++
3 files changed, 27 insertions(+)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 4a277934a7..6664adb385 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -93,6 +93,7 @@
<&gpio_b 9 0xc 3 2 1>;
int-value = <1234>;
uint-value = <(-1234)>;
+ int64-value = /bits/ 64 <0x>;
interrupts-extended = <&irq 3 0>;
};
diff --git a/include/test/ut.h b/include/test/ut.h
index 04df8ba3af..ab861588a8 100644
--- a/include/test/ut.h
+++ b/include/test/ut.h
@@ -104,6 +104,22 @@ int ut_check_console_dump(struct unit_test_state *uts, int
total_bytes);
} \
}
+/* Assert that two 64 int expressions are equal */
+#define ut_asserteq_64(expr1, expr2) { \
+ u64 _val1 = (expr1), _val2 = (expr2); \
+ \
+ if (_val1 != _val2) { \
+ ut_failf(uts, __FILE__, __LINE__, __func__, \
+#expr1 " == " #expr2, \
+"Expected %#llx (%lld), got %#llx (%lld)", \
+(unsigned long long)_val1, \
+(unsigned long long)_val1, \
+(unsigned long long)_val2, \
+(unsigned long long)_val2);\
+ return CMD_RET_FAILURE; \
+ } \
+}
+
/* Assert that two string expressions are equal */
#define ut_asserteq_str(expr1, expr2) {
\
const char *_val1 = (expr1), *_val2 = (expr2); \
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 75ae08081c..50bff4fdfb 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -867,6 +867,7 @@ static int dm_test_read_int(struct unit_test_state *uts)
u32 val32;
s32 sval;
uint val;
+ u64 val64;
ut_assertok(uclass_first_device_err(UCLASS_TEST_FDT, &dev));
ut_asserteq_str("a-test", dev->name);
@@ -891,6 +892,15 @@ static int dm_test_read_int(struct unit_test_state *uts)
ut_assertok(dev_read_u32u(dev, "uint-value", &val));
ut_asserteq(-1234, val);
+ ut_assertok(dev_read_u64(dev, "int64-value", &val64));
+ ut_asserteq_64(0x, val64);
+
+ ut_asserteq_64(-EINVAL, dev_read_u64(dev, "missing", &val64));
+ ut_asserteq_64(6, dev_read_u64_default(dev, "missing", 6));
+
+ ut_asserteq_64(0x,
+ dev_read_u64_default(dev, "int64-value", 6));
+
return 0;
}
DM_TEST(dm_test_read_int, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
--
2.17.1
Re: [PATCH v2 2/2] rockchip: video: Convert to use APIs which support live DT
Hi Kever,
On Sun, 29 Mar 2020 at 07:27, Kever Yang wrote:
>
> Hi Simon,
>
>
> On 2020/3/29 上午4:05, Simon Glass wrote:
> > Hi Kever,
> >
> > On Thu, 26 Mar 2020 at 07:37, Kever Yang wrote:
> >> Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
> >> driver can support live DT.
> >>
> >> Signed-off-by: Kever Yang
> >> ---
> >>
> >> Changes in v2:
> >> - use dev_read_s32() instead of dev_read_s32_default();
> [...]
> >>
> >> drivers/video/rockchip/rk3288_mipi.c | 1 -
> >> drivers/video/rockchip/rk3399_mipi.c | 1 -
> >> drivers/video/rockchip/rk_edp.c | 2 +-
> >> drivers/video/rockchip/rk_lvds.c | 28 +---
> >> drivers/video/rockchip/rk_mipi.c | 11 +--
> >> 5 files changed, 15 insertions(+), 28 deletions(-)
> >>
> >> diff --git a/drivers/video/rockchip/rk3288_mipi.c
> >> b/drivers/video/rockchip/rk3288_mipi.c
> >> index fb9c34..71d3faf169 100644
> >> --- a/drivers/video/rockchip/rk3288_mipi.c
> >> +++ b/drivers/video/rockchip/rk3288_mipi.c
> >> @@ -8,7 +8,6 @@
> >> #include
> >> #include
> >> #include
> >> -#include
> >> #include
> >> #include
> >> #include "rk_mipi.h"
> >> diff --git a/drivers/video/rockchip/rk3399_mipi.c
> >> b/drivers/video/rockchip/rk3399_mipi.c
> >> index 74ebe770a9..cfaa37797e 100644
> >> --- a/drivers/video/rockchip/rk3399_mipi.c
> >> +++ b/drivers/video/rockchip/rk3399_mipi.c
> >> @@ -8,7 +8,6 @@
> >> #include
> >> #include
> >> #include
> >> -#include
> >> #include
> >> #include
> >> #include "rk_mipi.h"
> >> diff --git a/drivers/video/rockchip/rk_edp.c
> >> b/drivers/video/rockchip/rk_edp.c
> >> index 8703df0ec0..842034c77c 100644
> >> --- a/drivers/video/rockchip/rk_edp.c
> >> +++ b/drivers/video/rockchip/rk_edp.c
> >> @@ -996,7 +996,7 @@ static int rk_edp_ofdata_to_platdata(struct udevice
> >> *dev)
> >> {
> >> struct rk_edp_priv *priv = dev_get_priv(dev);
> >>
> >> - priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev);
> >> + priv->regs = dev_read_addr_ptr(dev);
> >> priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> >>
> >> return 0;
> >> diff --git a/drivers/video/rockchip/rk_lvds.c
> >> b/drivers/video/rockchip/rk_lvds.c
> >> index cae8bada32..a11d793135 100644
> >> --- a/drivers/video/rockchip/rk_lvds.c
> >> +++ b/drivers/video/rockchip/rk_lvds.c
> >> @@ -171,32 +171,22 @@ int rk_lvds_read_timing(struct udevice *dev, struct
> >> display_timing *timing)
> >> static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
> >> {
> >> struct rk_lvds_priv *priv = dev_get_priv(dev);
> >> - const void *blob = gd->fdt_blob;
> >> - int node = dev_of_offset(dev);
> >> int ret;
> >> - priv->regs = (void *)devfdt_get_addr(dev);
> >> +
> >> + priv->regs = dev_read_addr_ptr(dev);
> >> priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> >>
> >> - ret = fdtdec_get_int(blob, node, "rockchip,output", -1);
> >> - if (ret != -1) {
> >> - priv->output = ret;
> >> - debug("LVDS output : %d\n", ret);
> >> - } else {
> >> - /* default set it as output rgb */
> >> + if (!dev_read_s32(dev, "rockchip,output", &priv->output))
> >> + debug("LVDS output : %d\n", priv->output);
> >> + else /* default set it as output rgb */
> >> priv->output = LVDS_OUTPUT_RGB;
> > Can you use dev_read_u32_default() ?
>
>
> Could you share the point about which API should be used? It's both OK
> to me and I think
>
> it's up to user to decide which is more convenient for them.
>
> The main update of this version for this patch is update to use
> dev_read_s32() instead of
>
> dev_read_u32_default() as your request. Maybe you can take V1 patch[0]?
Yes that was better, sorry.
Regards,
Simon
>
>
> Thanks,
>
> - Kever
>
> [0] http://patchwork.ozlabs.org/patch/1240459/
>
> > also below.
> >
> >> - }
> >>
> >> - ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1);
> >> - if (ret != -1) {
> >> - priv->format = ret;
> >> - debug("LVDS data-mapping : %d\n", ret);
> >> - } else {
> >> - /* default set it as format jeida */
> >> + if (!dev_read_s32(dev, "rockchip,data-mapping", &priv->format))
> >> + debug("LVDS data-mapping : %d\n", priv->format);
> >> + else /* default set it as format jeida */
> >> priv->format = LVDS_FORMAT_JEIDA;
> >> - }
> >>
> >> - ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1);
> >> - if (ret != -1) {
> >> + if (!dev_read_s32(dev, "rockchip,data-width", &ret)) {
> >> debug("LVDS data-width : %d\n", ret);
> >> if (ret == 24) {
> >> priv->format |= LVDS_24BIT;
> >> diff --git a/drivers/video/rockchip/rk_mipi.c
> >> b/drivers/video/rockchip/rk_mipi.c
> >> index a7
Re: [PATCH 2/2] rockchip: video: Convert to use APIs which support live DT
On Wed, 19 Feb 2020 at 20:04, Simon Glass wrote:
>
> Hi Kever,
>
> On Tue, 18 Feb 2020 at 18:45, Kever Yang wrote:
> >
> > Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
> > driver can support live DT.
> >
> > Signed-off-by: Kever Yang
> > ---
> >
> > drivers/video/rockchip/rk3288_mipi.c | 1 -
> > drivers/video/rockchip/rk3399_mipi.c | 1 -
> > drivers/video/rockchip/rk_edp.c | 2 +-
> > drivers/video/rockchip/rk_lvds.c | 10 --
> > drivers/video/rockchip/rk_mipi.c | 11 +--
> > 5 files changed, 10 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/video/rockchip/rk3288_mipi.c
> > b/drivers/video/rockchip/rk3288_mipi.c
> > index 65891ce45c..5b2dc2ad02 100644
> > --- a/drivers/video/rockchip/rk3288_mipi.c
> > +++ b/drivers/video/rockchip/rk3288_mipi.c
> > @@ -8,7 +8,6 @@
> > #include
> > #include
> > #include
> > -#include
> > #include
> > #include
> > #include "rk_mipi.h"
> > diff --git a/drivers/video/rockchip/rk3399_mipi.c
> > b/drivers/video/rockchip/rk3399_mipi.c
> > index a5b7ba69a8..03e1349509 100644
> > --- a/drivers/video/rockchip/rk3399_mipi.c
> > +++ b/drivers/video/rockchip/rk3399_mipi.c
> > @@ -8,7 +8,6 @@
> > #include
> > #include
> > #include
> > -#include
> > #include
> > #include
> > #include "rk_mipi.h"
> > diff --git a/drivers/video/rockchip/rk_edp.c
> > b/drivers/video/rockchip/rk_edp.c
> > index 4330725a25..e617a974a5 100644
> > --- a/drivers/video/rockchip/rk_edp.c
> > +++ b/drivers/video/rockchip/rk_edp.c
> > @@ -995,7 +995,7 @@ static int rk_edp_ofdata_to_platdata(struct udevice
> > *dev)
> > {
> > struct rk_edp_priv *priv = dev_get_priv(dev);
> >
> > - priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev);
> > + priv->regs = dev_read_addr_ptr(dev);
> > priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> >
> > return 0;
> > diff --git a/drivers/video/rockchip/rk_lvds.c
> > b/drivers/video/rockchip/rk_lvds.c
> > index cae8bada32..92e70f6317 100644
> > --- a/drivers/video/rockchip/rk_lvds.c
> > +++ b/drivers/video/rockchip/rk_lvds.c
> > @@ -171,13 +171,11 @@ int rk_lvds_read_timing(struct udevice *dev, struct
> > display_timing *timing)
> > static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
> > {
> > struct rk_lvds_priv *priv = dev_get_priv(dev);
> > - const void *blob = gd->fdt_blob;
> > - int node = dev_of_offset(dev);
> > int ret;
> > - priv->regs = (void *)devfdt_get_addr(dev);
> > + priv->regs = dev_read_addr_ptr(dev);
> > priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> >
> > - ret = fdtdec_get_int(blob, node, "rockchip,output", -1);
> > + ret = dev_read_s32_default(dev, "rockchip,output", -1);
>
> if (!dev_read_s32(...) {
>
> > if (ret != -1) {
> > priv->output = ret;
> > debug("LVDS output : %d\n", ret);
> > @@ -186,7 +184,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice
> > *dev)
> > priv->output = LVDS_OUTPUT_RGB;
> > }
> >
> > - ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1);
> > + ret = dev_read_s32_default(dev, "rockchip,data-mapping", -1);
> > if (ret != -1) {
>
> Same here
>
> > priv->format = ret;
> > debug("LVDS data-mapping : %d\n", ret);
> > @@ -195,7 +193,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice
> > *dev)
> > priv->format = LVDS_FORMAT_JEIDA;
> > }
> >
> > - ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1);
> > + ret = dev_read_s32_default(dev, "rockchip,data-width", -1);
>
> and here
>
> > if (ret != -1) {
> > debug("LVDS data-width : %d\n", ret);
> > if (ret == 24) {
> > diff --git a/drivers/video/rockchip/rk_mipi.c
> > b/drivers/video/rockchip/rk_mipi.c
> > index a77bdfd24d..f1c21bb8d7 100644
> > --- a/drivers/video/rockchip/rk_mipi.c
> > +++ b/drivers/video/rockchip/rk_mipi.c
> > @@ -8,7 +8,6 @@
> > #include
> > #include
> > #include
> > -#include
> > #include
> > #include
> > #include "rk_mipi.h"
> > @@ -76,7 +75,7 @@ static void rk_mipi_dsi_write(uintptr_t regs, u32 reg,
> > u32 val)
> > int rk_mipi_dsi_enable(struct udevice *dev,
> >const struct display_timing *timing)
> > {
> > - int node, timing_node;
> > + ofnode node, timing_node;
> > int val;
> > struct rk_mipi_priv *priv = dev_get_priv(dev);
> > uintptr_t regs = priv->regs;
> > @@ -119,10 +118,10 @@ int rk_mipi_dsi_enable(struct udevice *dev,
> > rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
> >
> > /* Set dpi color coding depth 24 bit */
> > - timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
> > -
> > "display-timings");
> > - node = fdt_first_subnode
Re: [PATCH 0/4] Fixes for rv1108 and rv1108-elgin-r1
On 2020/3/26 下午8:20, Otavio Salvador wrote: Hello, On Fri, Mar 13, 2020 at 2:42 PM Otavio Salvador wrote: Those are fixes we've been using and we'd like to upstream. They are fixes and would be great to have them included on 2020.04 release. Otavio Salvador (4): ARM: dts: Activate pullups in the console pins on rv1108-elgin-r1 elgin-rv1108: Use rk_board_late_init() for GPIO settings elgin-rv1108: Avoid adc_channel_single_shot error rv1108: Fix boot regression Applied to u-boot-rockchip master. Thanks, - Kever The patches on this serie are all bug fixes so please make sure they go on 2020.04. Maybe Tom may apply them directly?
Re: [PATCH v2 2/2] rockchip: video: Convert to use APIs which support live DT
Hi Simon,
On 2020/3/29 上午4:05, Simon Glass wrote:
Hi Kever,
On Thu, 26 Mar 2020 at 07:37, Kever Yang wrote:
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: Kever Yang
---
Changes in v2:
- use dev_read_s32() instead of dev_read_s32_default();
[...]
drivers/video/rockchip/rk3288_mipi.c | 1 -
drivers/video/rockchip/rk3399_mipi.c | 1 -
drivers/video/rockchip/rk_edp.c | 2 +-
drivers/video/rockchip/rk_lvds.c | 28 +---
drivers/video/rockchip/rk_mipi.c | 11 +--
5 files changed, 15 insertions(+), 28 deletions(-)
diff --git a/drivers/video/rockchip/rk3288_mipi.c
b/drivers/video/rockchip/rk3288_mipi.c
index fb9c34..71d3faf169 100644
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -8,7 +8,6 @@
#include
#include
#include
-#include
#include
#include
#include "rk_mipi.h"
diff --git a/drivers/video/rockchip/rk3399_mipi.c
b/drivers/video/rockchip/rk3399_mipi.c
index 74ebe770a9..cfaa37797e 100644
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -8,7 +8,6 @@
#include
#include
#include
-#include
#include
#include
#include "rk_mipi.h"
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 8703df0ec0..842034c77c 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -996,7 +996,7 @@ static int rk_edp_ofdata_to_platdata(struct udevice *dev)
{
struct rk_edp_priv *priv = dev_get_priv(dev);
- priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev);
+ priv->regs = dev_read_addr_ptr(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
return 0;
diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c
index cae8bada32..a11d793135 100644
--- a/drivers/video/rockchip/rk_lvds.c
+++ b/drivers/video/rockchip/rk_lvds.c
@@ -171,32 +171,22 @@ int rk_lvds_read_timing(struct udevice *dev, struct
display_timing *timing)
static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
{
struct rk_lvds_priv *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
int ret;
- priv->regs = (void *)devfdt_get_addr(dev);
+
+ priv->regs = dev_read_addr_ptr(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- ret = fdtdec_get_int(blob, node, "rockchip,output", -1);
- if (ret != -1) {
- priv->output = ret;
- debug("LVDS output : %d\n", ret);
- } else {
- /* default set it as output rgb */
+ if (!dev_read_s32(dev, "rockchip,output", &priv->output))
+ debug("LVDS output : %d\n", priv->output);
+ else /* default set it as output rgb */
priv->output = LVDS_OUTPUT_RGB;
Can you use dev_read_u32_default() ?
Could you share the point about which API should be used? It's both OK
to me and I think
it's up to user to decide which is more convenient for them.
The main update of this version for this patch is update to use
dev_read_s32() instead of
dev_read_u32_default() as your request. Maybe you can take V1 patch[0]?
Thanks,
- Kever
[0] http://patchwork.ozlabs.org/patch/1240459/
also below.
- }
- ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1);
- if (ret != -1) {
- priv->format = ret;
- debug("LVDS data-mapping : %d\n", ret);
- } else {
- /* default set it as format jeida */
+ if (!dev_read_s32(dev, "rockchip,data-mapping", &priv->format))
+ debug("LVDS data-mapping : %d\n", priv->format);
+ else /* default set it as format jeida */
priv->format = LVDS_FORMAT_JEIDA;
- }
- ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1);
- if (ret != -1) {
+ if (!dev_read_s32(dev, "rockchip,data-width", &ret)) {
debug("LVDS data-width : %d\n", ret);
if (ret == 24) {
priv->format |= LVDS_24BIT;
diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
index a77bdfd24d..f1c21bb8d7 100644
--- a/drivers/video/rockchip/rk_mipi.c
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -8,7 +8,6 @@
#include
#include
#include
-#include
#include
#include
#include "rk_mipi.h"
@@ -76,7 +75,7 @@ static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32
val)
int rk_mipi_dsi_enable(struct udevice *dev,
const struct display_timing *timing)
{
- int node, timing_node;
+ ofnode node, timing_node;
int val;
struct rk_mipi_priv *priv = dev_get_priv(dev);
uintptr_t regs = priv->regs;
@@ -119,10 +118,10 @@ int rk_mipi_dsi_enable(struct udevice *dev,
rk_mipi_dsi_write(regs, VID
