Re: Please pull u-boot-marvell/master

[Stefan Roese]

On 22.04.20 20:34, Tom Rini wrote:

On Wed, Apr 22, 2020 at 04:48:33PM +0200, Stefan Roese wrote:


Hi Tom,

please pull the 2nd batch of MVEBU related patches in this merge
window. The major changes are:



Applied to u-boot/master, thanks!

But the following checkpatch should be fixed in a follow up sometime:
WARNING: quoted string split across lines
#28: FILE: cmd/mvebu/bubt.c:734:
+   printf("Error: A38x image meant to be "
+  "booted from \"%s\", not
\"%s\"!\n",


(There's another but I think the split is fine for how humans would grep
for it).


Joel, will you please take care of this.

Thanks,
Stefan

Re: [RFC] dm: uclass: add functions to get device by platdata

[Walter Lozano]

Hi Simon,

On 21/4/20 14:36, Simon Glass wrote:

Hi Walter,

On Fri, 17 Apr 2020 at 15:18, Walter Lozano  wrote:

Hi Simon,

On 9/4/20 16:36, Simon Glass wrote:

HI Walter,

On Thu, 9 Apr 2020 at 12:57, Walter Lozano  wrote:

Hi Simon,

On 8/4/20 00:14, Simon Glass wrote:

Hi Walter,

On Tue, 7 Apr 2020 at 14:05, Walter Lozano  wrote:

Hi Simon,

On 6/4/20 00:43, Simon Glass wrote:

Hi Walter,

On Mon, 9 Mar 2020 at 12:27, Walter Lozano   wrote:

Hi Simon

On 6/3/20 17:32, Simon Glass wrote:

Hi Walter,

On Fri, 6 Mar 2020 at 09:10, Walter Lozano   wrote:

Hi Simon,

Thanks again for taking the time to check my comments.

On 6/3/20 10:17, Simon Glass wrote:

Hi Walter,

On Thu, 5 Mar 2020 at 06:54, Walter Lozano   wrote:

Hi Simon,

Thanks for taking the time to check for my comments

On 4/3/20 20:11, Simon Glass wrote:


Hi Walter,

On Wed, 4 Mar 2020 at 12:40, Walter Lozano   wrote:

When OF_PLATDATA is enabled DT information is parsed and platdata
structures are populated. In this context the links between DT nodes are
represented as pointers to platdata structures, and there is no clear way
to access to the device which owns the structure.

This patch implements a set of functions:

- device_find_by_platdata
- uclass_find_device_by_platdata

to access to the device.

Signed-off-by: Walter Lozano
---
drivers/core/device.c| 19 +++
drivers/core/uclass.c| 34 ++
include/dm/device.h  |  2 ++
include/dm/uclass-internal.h |  3 +++
include/dm/uclass.h  |  2 ++
5 files changed, 60 insertions(+)

This is interesting. Could you also add the motivation for this? It's
not clear to me who would call this function.

I have been reviewing the OF_PLATDATA support as an R project, in this 
context, in order to have
a better understanding on the possibilities and limitations I decided to add 
its support to iMX6,
more particularly to the MMC drivers. The link issue arises when I tried to 
setup the GPIO for
Card Detection, which is trivial when DT is available. However, when 
OF_PLATDATA is enabled
this seems, at least for me, not straightforward.

In order to overcome this limitation I think that having a set of functions to 
find/get devices
based on platdata could be useful. Of course, there might be a better 
approach/idea, so that is
the motivation for this RFC.

An example of the usage could be

#if CONFIG_IS_ENABLED(DM_GPIO)

   struct udevice *gpiodev;

   ret = uclass_get_device_by_platdata(UCLASS_GPIO, (void 
*)dtplat->cd_gpios->node, );

   if (ret)
   return ret;

   ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
dtplat->cd_gpios->arg[0], 
GPIOD_IS_IN,
dtplat->cd_gpios->arg[1], 
>cd_gpio);

   if (ret)
   return ret;

#endif

This is part of my current work, a series of patches to add OF_PLATDATA support 
as explained.

Does this make sense to you?

Not yet :-)

What is the context of this call? Typically dtplat is only available
in the driver that includes it.

Sorry for not being clear enough. I'm working in a patchset that needs
some clean up, that is the reason I didn't send it yet. I'll try to
clarify, but if you think it could be useful to share it, please let me
know.


What driver is the above code in? Is it for MMC that needs a GPIO to
function? I'll assume it is for now.

The driver on which I'm working in is drivers/mmc/fsl_esdhc_imx.c, I'm
adding support for OF_PLATDATA to it, and in this sense trying to get
the GPIOs used for CD to be requested.


Then the weird thing is that we are accessing the dtplat of another
device. It's a clever technique but I wonder if we can find another
way.

If you see drivers/mmc/rockchip_sdhci.c it has:

ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, );

So I wonder if we need gpio_dev_request_by_platdata()?

Thanks for pointing to this example, as I saw it before starting to work
on these functions and had some doubts. I'll use it in the next
paragraph to share my thoughts and the motivation of my work.

  From my understanding, clk_get_by_index_platdata in this context can
only get a UCLASS_CLK device with id == 0. Is this correct?

If it is so, this will only allow us to use this function if we know in
advance that the UCLASS_CLK device has index 0.

How can we get the correct UCLASS_CLK device in case of multiple instances?

We actually can't support that at present. I think we would need to
change the property to be an array, like:

clocks = [
[, CLK_ID_SPI],
[, CLK_ID_I2C, 23],
  ]

which would need a fancier dtoc. Perhaps we should start by
upstreaming that tool.

In this case, are you suggesting to replace CLK_ID_SPI and CLK_ID_I2C
with a integer calculated by dtoc based on the 

Re: [PATCH v8 00/21] riscv: Add Sipeed Maix support

[Rick Chen]

Hi Sean

> On 4/22/20 9:51 PM, Rick Chen wrote:
> > Hi Sean
> >
> >> Hi Sean
> >>
> >>> This patch series adds support for Sipeed Maix boards and the Kendryte
> >>> K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
> >>> models are similar.
> >>>
> >>> Known Bugs/Limitations:
> >>> - Accessing the AI ram hangs, limiting available ram to 6M
> >>> - Trying to boot an image with bootm fails with
> >>>   ERROR: Failed to allocate 0x7d60 bytes below 0x8000.
> >>>
> >>> To flash u-boot to a maix bit, run
> >>> kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
> >>>
> >>> Boot output should look like the following:
> >>>
> >>> U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
> >>>
> >>> DRAM:  8 MiB
> >>> In:serial@3800
> >>> Out:   serial@3800
> >>> Err:   serial@3800
> >>> =>
> >>>
> >>> Changes for v8:
> >>> - Removed dependency on the patch "clk: Add functions to register CCF 
> >>> clock
> >>>   structs". Hopefully this will make reviewing easier.
> >>
> >> I have applied this patch series to u-boot-riscv/master except [PATCH
> >> v8 14/21] riscv: Clean up IPI initialization code.
> >> Because it will cause some warnings as below:
> >>
> >> arch/riscv/lib/andes_plic.c: In function 'riscv_init_ipi':
> >> arch/riscv/lib/andes_plic.c:84:12: warning: initialization makes
> >> integer from pointer without a cast [-Wint-conversion]
> >>   int ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
> >> ^~
> >> arch/riscv/lib/andes_plic.c:86:13: warning: passing argument 1 of
> >> 'IS_ERR' makes pointer from integer without a cast [-Wint-conversion]
> >>   if (IS_ERR(ret))
> >>  ^~~
> >> In file included from arch/riscv/lib/andes_plic.c:20:0:
> >> include/linux/err.h:34:20: note: expected 'const void *' but argument
> >> is of type 'int'
> >>  static inline long IS_ERR(const void *ptr)
> >> ^~
> >> arch/riscv/lib/andes_plic.c:87:18: warning: passing argument 1 of
> >> 'PTR_ERR' makes pointer from integer without a cast [-Wint-conversion]
> >>return PTR_ERR(ret);
> >>   ^~~
> >> In file included from arch/riscv/lib/andes_plic.c:20:0:
> >> include/linux/err.h:29:20: note: expected 'const void *' but argument
> >> is of type 'int'
> >>  static inline long PTR_ERR(const void *ptr)
> >> ^~~
> >> arch/riscv/lib/andes_plic.c:88:16: warning: assignment makes pointer
> >> from integer without a cast [-Wint-conversion]
> >>   gd->arch.plic = ret;
> >>
> >
> > after running CI yesterday, it failed in many cases:
> > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678023975
> >
> > and I trace at least two cases belong to your patch
> > 49.59
> > https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024035
> >
> > arning, treated as error:
> > /home/travis/build/rickchen36/u-boot-riscv/doc/board/sipeed/maix.rst:173:Error
> > in "code-block" directive:
> > 1 argument(s) required, 0 supplied.
> > .. code-block::
> >  {
> > assigned-clocks = < K210_CLK_PLL0>;
> > assigned-clock-rates = <8>;
> > };
> > doc/Makefile:69: recipe for target 'htmldocs' failed
> > make[1]: *** [htmldocs] Error 1
>
> I used to have
>
> .. code-block:: dts
>
> but it warned that "dts" was not a valid language, so I dropped it.
>
> > 49.66
> > https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024042
> >
> > ./tools/patman/patman --test && ./tools/buildman/buildman -t &&
> > ./tools/dtoc/dtoc -t && make testconfig; fi; fi
> > cp: cannot create regular file
> > '/home/travis/build/rickchen36/sandbox/': Not a directory
> > cp: cannot create regular file
> > '/home/travis/build/rickchen36/sandbox/': Not a directory
> > WARNING: no status info for 'sipeed_maix_bitm'
> > WARNING: no maintainers for 'sipeed_maix_bitm'
>
> I'm not sure what the issue here is. Which specific files are lacking a
> MAINTAINERS entry?
>
> >
> > So I will drop your patchs and run CI again today.
> > And hope you can fix them in next version and pass CI verification.
>
>
>
> >
> > Thanks,
> > Rick
> >
>
> These "errors" seem rather minor. I will fix the PLIC ones in the next
> revision, but I don't think the sort found in this email are
> particularly erroneous.


Can you run and pass Travis CI after you fix your patchs
It help us to maintain the quality about patch works.

Thanks,
Rick

>
> --Sean
>

[PATCH v9 20/21] doc: riscv: Add documentation for Sipeed Maix Bit

[Sean Anderson]

This patch adds documentation for the Sipeed Maix bit, and more generally
for the Kendryte K210 processor.

Signed-off-by: Sean Anderson 
---

Changes in v9:
- Mark dts code block as "none" explicitly
Changes in v7:
- Split off into its own patch
- Fix size of clint

 doc/board/index.rst|   1 +
 doc/board/sipeed/index.rst |   9 ++
 doc/board/sipeed/maix.rst  | 298 +
 3 files changed, 308 insertions(+)
 create mode 100644 doc/board/sipeed/index.rst
 create mode 100644 doc/board/sipeed/maix.rst

diff --git a/doc/board/index.rst b/doc/board/index.rst
index 51a2ae6f28..dcc47c5a21 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -16,6 +16,7 @@ Board-specific doc
renesas/index
rockchip/index
sifive/index
+   sipeed/index
st/index
toradex/index
xilinx/index
diff --git a/doc/board/sipeed/index.rst b/doc/board/sipeed/index.rst
new file mode 100644
index 00..3518e2d8f4
--- /dev/null
+++ b/doc/board/sipeed/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sipeed
+==
+
+.. toctree::
+   :maxdepth: 2
+
+   maix
diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
new file mode 100644
index 00..06e0008b9f
--- /dev/null
+++ b/doc/board/sipeed/maix.rst
@@ -0,0 +1,298 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Sean Anderson 
+
+Maix Bit
+
+
+Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
+a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
+neural network processing and other "ai" tasks. This includes a "KPU" neural
+network processor, an audio processor supporting beamforming reception, and a
+digital video port supporting capture and output at VGA resolution. Other
+peripherals include 8M of SRAM (accessible with and without caching); 
remappable
+pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
+and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi 
flash;
+on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
+ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but
+the boards are fairly similar.
+
+Documentation for Maix boards is available from
+`Sipeed's website `_.
+Documentation for the Kendryte K210 is available from
+`Kendryte's website `_. However, hardware
+details are rather lacking, so most technical reference has been taken from the
+`standalone sdk `_.
+
+Build and boot steps
+
+
+To build u-boot, run
+
+.. code-block:: none
+
+make sipeed_maix_bitm_defconfig
+make CROSS_COMPILE=
+
+To flash u-boot to a maix bit, run
+
+.. code-block:: none
+
+kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
+
+Boot output should look like the following:
+
+.. code-block:: none
+
+U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
+
+DRAM:  8 MiB
+In:serial@3800
+Out:   serial@3800
+Err:   serial@3800
+=>
+
+Loading Images
+^^
+
+To load a kernel, transfer it over serial.
+
+.. code-block:: none
+
+=> loady 8000 150
+## Switch baudrate to 150 bps and press ENTER ...
+
+*** baud: 150
+
+*** baud: 150 ***
+## Ready for binary (ymodem) download to 0x8000 at 150 bps...
+C
+*** file: loader.bin
+$ sz -vv loader.bin
+Sending: loader.bin
+Bytes Sent:2478208   BPS:72937
+Sending:
+Ymodem sectors/kbytes sent:   0/ 0k
+Transfer complete
+
+*** exit status: 0 ***
+## Total Size  = 0x0025d052 = 2478162 Bytes
+## Switch baudrate to 115200 bps and press ESC ...
+
+*** baud: 115200
+
+*** baud: 115200 ***
+=>
+
+Running Programs
+
+
+Binaries
+
+
+To run a bare binary, use the ``go`` command:
+
+.. code-block:: none
+
+=> loady
+## Ready for binary (ymodem) download to 0x8000 at 115200 bps...
+C
+*** file: ./examples/standalone/hello_world.bin
+$ sz -vv ./examples/standalone/hello_world.bin
+Sending: hello_world.bin
+Bytes Sent:   4864   BPS:649
+Sending:
+Ymodem sectors/kbytes sent:   0/ 0k
+Transfer complete
+
+*** exit status: 0 ***
+(CAN) packets, 5 retries
+## Total Size  = 0x12f8 = 4856 Bytes
+=> go 8000
+## Starting application at 0x8000 ...
+Example expects ABI version 9
+Actual U-Boot ABI version 9
+Hello World
+argc = 1
+argv[0] = "8000"
+argv[1] = ""
+Hit any key to exit ...
+
+Legacy Images
+"
+
+To run legacy images, use the ``bootm`` command:
+
+.. code-block:: none
+
+$ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 8000 -e 
8000 -d examples/standalone/hello_world.bin hello_world.img
+Image Name:
+Created:  Thu 

[PATCH v9 21/21] riscv: Add Sipeed Maix support

[Sean Anderson]

The Sipeed Maix series is a collection of boards built around the RISC-V
Kendryte K210 processor. This processor contains several peripherals to
accelerate neural network processing and other "ai" tasks. This includes a
"KPU" neural network processor, an audio processor supporting beamforming
reception, and a digital video port supporting capture and output at VGA
resolution. Other peripherals include 8M of sram (accessible with and
without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
peripherals vary, but include spi flash; on-board usb-serial bridges; ports
for cameras, displays, and sd cards; and ESP32 chips. Currently, only the
Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly
similar.

Documentation for Maix boards is located at
.  Documentation for the Kendryte K210 is
located at . However, hardware details are
rather lacking, so most technical reference has been taken from the
standalone sdk located at
.

Signed-off-by: Sean Anderson 
---

Changes in v9:
- Update MAINTAINERS to reflect defconfig name change

Changes in v8:
- Remove unnecessary fdt fixup for sipeed maix

Changes in v7:
- Split docs off into their own patch
- Enable ram clocks by name

Changes in v6:
- Remove trailing whitespace from documentation
- Remove configuration for spi/pinmux/gpio features
- Flesh out documentation some more

Changes in v5:
- Configure relocation location with CONFIG_SYS_SDRAM_*
- Enable ram clocks
- Add pinmux/gpio/led support
- Remove (broken) MMC support
- Store the environment in flash
- Add partitions
- Add bootcmd
- Add docs for pinctrl and booting

Changes in v4:
- Rework documentation to be organized by board mfg not cpu mfg
- Update docs to reflect working SPI support
- Add proper spi support
- Don't define unneecessary macros in config.h
- Lower the default stack so it isn't clobbered on relocation
- Update MAINTAINERS
- Update copyright

Changes in v3:
- Reorder to be last in the patch series
- Add documentation for the board
- Generate defconfig with "make savedefconfig"
- Update Kconfig to imply most features we need
- Update MAINTAINERS

Changes in v2:
- Select CONFIG_SYS_RISCV_NOCOUNTER
- Imply CONFIG_CLK_K210
- Remove spurious references to CONFIG_ARCH_K210
- Remove many configs from defconfig where the defaults were fine
- Add a few "not set" lines to suppress unneeded defaults
- Reduce pre-reloc malloc space, now that clocks initialization happens
  later

 arch/riscv/Kconfig |  4 +++
 board/sipeed/maix/Kconfig  | 47 ++
 board/sipeed/maix/MAINTAINERS  | 11 +++
 board/sipeed/maix/Makefile |  5 
 board/sipeed/maix/maix.c   | 41 ++
 configs/sipeed_maix_bitm_defconfig |  8 +
 include/configs/sipeed-maix.h  | 24 +++
 7 files changed, 140 insertions(+)
 create mode 100644 board/sipeed/maix/Kconfig
 create mode 100644 board/sipeed/maix/MAINTAINERS
 create mode 100644 board/sipeed/maix/Makefile
 create mode 100644 board/sipeed/maix/maix.c
 create mode 100644 configs/sipeed_maix_bitm_defconfig
 create mode 100644 include/configs/sipeed-maix.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index cb1ca31b1b..ba171b4918 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
 config TARGET_SIFIVE_FU540
bool "Support SiFive FU540 Board"
 
+config TARGET_SIPEED_MAIX
+   bool "Support Sipeed Maix Board"
+
 endchoice
 
 config SYS_ICACHE_OFF
@@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
+source "board/sipeed/maix/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
new file mode 100644
index 00..0cdcd32adc
--- /dev/null
+++ b/board/sipeed/maix/Kconfig
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019-20 Sean Anderson 
+
+if TARGET_SIPEED_MAIX
+
+config SYS_BOARD
+   default "maix"
+
+config SYS_VENDOR
+   default "sipeed"
+
+config SYS_CPU
+   default "generic"
+
+config SYS_CONFIG_NAME
+   default "sipeed-maix"
+
+config SYS_TEXT_BASE
+   default 0x8000
+
+config DEFAULT_DEVICE_TREE
+   default "k210-maix-bit"
+
+config NR_CPUS
+   default 2
+
+config NR_DRAM_BANKS
+   default 3
+
+config BOARD_SPECIFIC_OPTIONS
+   def_bool y
+   select GENERIC_RISCV
+   select RISCV_PRIV_1_9
+   imply SMP
+   imply DM_SERIAL
+   imply SIFIVE_SERIAL
+   imply SIFIVE_CLINT
+   imply POWER_DOMAIN
+   imply SIMPLE_PM_BUS
+   imply CLK_CCF
+   imply CLK_COMPOSITE_CCF

[PATCH v9 14/21] riscv: Clean up IPI initialization code

[Sean Anderson]

The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. Before this
point, no riscv_*_ipi functions should be called.

Signed-off-by: Sean Anderson 
Reviewed-by: Rick Chen 
---

Changes in v9:
- Fix type of ret variable in riscv_ipi_init
Changes in v7:
- Split IPI clearing off into its own patch

Changes in v6:
- Fix some formatting
- Clear IPIs before enabling interrupts instead of using a ipi_ready flag
- Only print messages on error in smp code

Changes in v5:
- New

 arch/riscv/cpu/cpu.c  |  6 
 arch/riscv/include/asm/smp.h  | 43 +++
 arch/riscv/lib/andes_plic.c   | 34 -
 arch/riscv/lib/sbi_ipi.c  |  5 
 arch/riscv/lib/sifive_clint.c | 33 +++--
 arch/riscv/lib/smp.c  | 56 ---
 6 files changed, 90 insertions(+), 87 deletions(-)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e457f6acbf..f851374255 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -96,6 +96,12 @@ int arch_cpu_init_dm(void)
csr_write(CSR_SATP, 0);
}
 
+#ifdef CONFIG_SMP
+   ret = riscv_init_ipi();
+   if (ret)
+   return ret;
+#endif
+
return 0;
 }
 
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 74de92ed13..1b428856b2 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -51,4 +51,47 @@ void handle_ipi(ulong hart);
  */
 int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
 
+/**
+ * riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
+ *
+ * Platform code must provide this function. This function is called once after
+ * the cpu driver is initialized. No other riscv_*_ipi() calls will be made
+ * before this function is called.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int riscv_init_ipi(void);
+
+/**
+ * riscv_send_ipi() - Send inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of receiving hart
+ * @return 0 if OK, -ve on error
+ */
+int riscv_send_ipi(int hart);
+
+/**
+ * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be cleared
+ * @return 0 if OK, -ve on error
+ */
+int riscv_clear_ipi(int hart);
+
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ *   1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+int riscv_get_ipi(int hart, int *pending);
+
 #endif
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 20529ab3eb..5cf29df670 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -30,20 +30,6 @@
 #define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
 
 DECLARE_GLOBAL_DATA_PTR;
-static int init_plic(void);
-
-#define PLIC_BASE_GET(void)\
-   do {\
-   long *ret;  \
-   \
-   if (!gd->arch.plic) {   \
-   ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
-   if (IS_ERR(ret))\
-   return PTR_ERR(ret);\
-   gd->arch.plic = ret;\
-   init_plic();\
-   }   \
-   } while (0)
 
 static int enable_ipi(int hart)
 {
@@ -93,13 +79,21 @@ static int init_plic(void)
return -ENODEV;
 }
 
+int riscv_init_ipi(void)
+{
+   long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
+
+   if (IS_ERR(ret))
+   return PTR_ERR(ret);
+   gd->arch.plic = ret;
+
+   return init_plic();
+}
+
 int riscv_send_ipi(int hart)
 {
-   unsigned int ipi;
+   unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
 
-   PLIC_BASE_GET();
-
-   ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
 
@@ -110,8 +104,6 @@ int riscv_clear_ipi(int hart)
 {
u32 source_id;
 
-   PLIC_BASE_GET();
-
source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
writel(source_id, (void __iomem 

[PATCH v9 19/21] riscv: Add device tree for K210 and Sipeed Maix BitM

[Sean Anderson]

Where possible, I have tried to find compatible drivers based on the layout
of registers. However, many devices remain untested. All untested devices
have been left disabled, but some tentative properties (such as compatible
strings, and clocks, interrupts, and resets properties) have been added.

Signed-off-by: Sean Anderson 
---

Changes in v7:
- Move clocks node to be just before soc node, matching linux's tree
- Merge memory nodes into one node with different registers
- Add aliases for uclasses which use them
- Fix size of clint

Changes in v6:
- Remove spi, gpio, pinmux, wdt, and led bindings
- Use consistent capitalization for hex digits

Changes in v5:
- Add more compatible strings
- Add cache line size
- Document CPUs as rocket cores
- Flesh out the gpio devices
- Add ports for audio and video devices
- Add fpioa pinctrl support
- Configure pins for MMC on SPI1
- Enable MMC
- Fix a couple uart properties (Thanks laanwj)
- Reorder ram now that relocation is handled with CONFIG_SYS defines
- Enable WDT
- Add pinctrl properties
- Add gpio support
- Add led support
- Add assorted AV bindings
- Add compatible strings for ram
- Use GPIO-based CS for MMC
- Limit SPI flash to 50 MHz

Changes in v4:
- Set regs sizes to full address range
- Remove clock-frequency property from cpus
- Add spi-max-frequency to spi devices from documentation
- Add more compatible strings for each device
- Add AI ram as a separate memory bank. Its clock is disabled on boot, and
  it cannot be accessed
- Reorder memory banks so u-boot relocates higher, leaving more room to
  load boot images
- Add designware ssi CTRL0 field shifts to spi devices
- Don't enable the MMC slot
- Update copyright
- Lint

Changes in v3:
- Move this patch to the end of the series
- Add a max frequency for spi3
- Remov unused compatible strings from spi-flash@0
- Add s and u to isa string
- Fix mmu-type
- Remove cache-line size since it is unused (in u-boot) and undocumented
  (upstream)
- Add timer interrupts to clint0
- Round up various registers
- Add riscv,max-priority to plic
- Add apb* busses, since they have clocks which need to be enabled to
  access their devices
- Change uart compatible strings to "snps,dw-apb-uart", since that appears
  to match their registers
- Add compatible string for wdt*
- Add system reset device under sysctl
- Add reset device under sysctl

Changes in v2:
- Model changed to "Sipeed Maix Bit" to match file name
- Value of stdout-path fixed
- SD card slot compatible changed to "mmc-spi-slot"
- "jedec,spi-nor" added to spi flash compatible list
- Aliases for spi busses added
- timebase-frequency divided by 50 to match timer speed
- cpu-frequency renamed to clock-frequency
- CPUX_intc restyled to cpuX_intc
- "kendryte,k210-soc" added to soc compatible list for future-proofing
- PLIC handle renamed to plic0 from pic0
- K210_RST_SOC removed from sysrst, due to not being located in the reset
  register
- K210_RST_* numbers changed to match their bit offset within the reset
  register
- gpio_controller restyled to gpio-controller
- Added a second clock to the dma binding to match what the driver expects
- Changed "snps,designware-spi" compatible string to "snps,dw-apb-ssi" to
  match the correct driver
- Added a name to the spi clocks
- Added reg-io-width property to spi bindings
- Assigned a default parent to K210_CLK_SPI3
- Removed assigned clocks for ACLK and PLLs
- Removed u-boot,dm-pre-reloc bindings

 arch/riscv/dts/Makefile |   1 +
 arch/riscv/dts/k210-maix-bit.dts|  47 ++
 arch/riscv/dts/k210.dtsi| 594 
 include/dt-bindings/reset/k210-sysctl.h |  38 ++
 4 files changed, 680 insertions(+)
 create mode 100644 arch/riscv/dts/k210-maix-bit.dts
 create mode 100644 arch/riscv/dts/k210.dtsi
 create mode 100644 include/dt-bindings/reset/k210-sysctl.h

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 4f30e6936f..3a6f96c67d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
new file mode 100644
index 00..5b32c5fd5f
--- /dev/null
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson 
+ */
+
+/dts-v1/;
+
+#include "k210.dtsi"
+
+#include 
+
+/ {
+   model = "Sipeed Maix Bit 2.0";
+   compatible = "sipeed,maix-bitm", "sipeed,maix-bit", "kendryte,k210";
+
+   chosen {
+   stdout-path = "serial0:115200";
+   };
+
+   sound {
+   compatible = "simple-audio-card";
+   simple-audio-card,format = "i2s";
+   status = "disabled";
+
+   simple-audio-card,cpu {
+  

[PATCH v9 15/21] riscv: Add option to support RISC-V privileged spec 1.9

[Sean Anderson]

Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs.  Using the new CSR on an old processor causes an illegal
instruction exception.  This patch adds an option to use the old CSRs
instead of the new one.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v6:
- Reformat so chechpatch errors less

Changes in v5:
- Rename to 1.9 to reflect the spec as implemented by the k210

Changes in v4:
- Fixed CSRs not being defined properly (thanks bmeng)
- Added ifdefs for all changed CSRs (e.g. for VM)
- Also properly disable VM on boot

Changes in v3:
- Renamed from "riscv: Add option to disable writes to mcounteren"
- Added original functionality back for older priv specs.

Changes in v2:
- Moved forward in the patch series

 arch/riscv/Kconfig   | 10 +
 arch/riscv/cpu/cpu.c |  9 
 arch/riscv/include/asm/csr.h | 40 
 3 files changed, 59 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3061bf8863..cb1ca31b1b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -238,6 +238,16 @@ config XIP
 config SHOW_REGS
bool "Show registers on unhandled exception"
 
+config RISCV_PRIV_1_9
+   bool "Use version 1.9 of the RISC-V priviledged specification"
+   help
+ Older versions of the RISC-V priviledged specification had
+ separate counter enable CSRs for each privilege mode. Writing
+ to the unified mcounteren CSR on a processor implementing the
+ old specification will result in an illegal instruction
+ exception. In addition to counter CSR changes, the way virtual
+ memory is configured was also changed.
+
 config STACK_SIZE_SHIFT
int
default 14
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index f851374255..3c1836694a 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -89,11 +89,20 @@ int arch_cpu_init_dm(void)
 * Enable perf counters for cycle, time,
 * and instret counters only
 */
+#ifdef CONFIG_RISCV_PRIV_1_9
+   csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+   csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+#else
csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+#endif
 
/* Disable paging */
if (supports_extension('s'))
+#ifdef CONFIG_RISCV_PRIV_1_9
+   csr_read_clear(CSR_MSTATUS, SR_VM);
+#else
csr_write(CSR_SATP, 0);
+#endif
}
 
 #ifdef CONFIG_SMP
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index d1520743a2..1a15089cae 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -15,7 +15,11 @@
 #define SR_SIE _AC(0x0002, UL) /* Supervisor Interrupt Enable */
 #define SR_SPIE_AC(0x0020, UL) /* Previous Supervisor IE */
 #define SR_SPP _AC(0x0100, UL) /* Previously Supervisor */
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_PUM _AC(0x0004, UL) /* Protect User Memory Access */
+#else
 #define SR_SUM _AC(0x0004, UL) /* Supervisor User Memory Access */
+#endif
 
 #define SR_FS  _AC(0x6000, UL) /* Floating-point Status */
 #define SR_FS_OFF  _AC(0x, UL)
@@ -29,6 +33,22 @@
 #define SR_XS_CLEAN_AC(0x0001, UL)
 #define SR_XS_DIRTY_AC(0x00018000, UL)
 
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_VM  _AC(0x1F00, UL) /* Virtualization Management */
+#define SR_VM_MODE_BARE_AC(0x, UL) /* No translation or 
protection */
+#define SR_VM_MODE_BB  _AC(0x0100, UL) /* Single base-and-bound */
+/* Separate instruction and data base-and-bound */
+#define SR_VM_MODE_BBID_AC(0x0200, UL)
+#ifndef CONFIG_64BIT
+#define SR_VM_MODE_32  _AC(0x0800, UL)
+#define SR_VM_MODE SR_VM_MODE_32
+#else
+#define SR_VM_MODE_39  _AC(0x0900, UL)
+#define SR_VM_MODE_48  _AC(0x0A00, UL)
+#define SR_VM_MODE SR_VM_MODE_39
+#endif
+#endif
+
 #ifndef CONFIG_64BIT
 #define SR_SD  _AC(0x8000, UL) /* FS/XS dirty */
 #else
@@ -36,6 +56,7 @@
 #endif
 
 /* SATP flags */
+#ifndef CONFIG_RISCV_PRIV_1_9
 #ifndef CONFIG_64BIT
 #define SATP_PPN   _AC(0x003F, UL)
 #define SATP_MODE_32   _AC(0x8000, UL)
@@ -45,6 +66,7 @@
 #define SATP_MODE_39   _AC(0x8000, UL)
 #define SATP_MODE  SATP_MODE_39
 #endif
+#endif
 
 /* SCAUSE */
 #define SCAUSE_IRQ_FLAG(_AC(1, UL) << (__riscv_xlen - 1))
@@ -88,17 +110,35 @@
 #define CSR_SCAUSE 0x142
 #define CSR_STVAL  0x143
 #define CSR_SIP0x144
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define CSR_SPTBR  0x180
+#else
 #define CSR_SATP   0x180
+#endif
 #define CSR_MSTATUS 

[PATCH v9 17/21] riscv: Try to get cpu frequency from a "clocks" node if it exists

[Sean Anderson]

Instead of always using the "clock-frequency" property to determine cpu
frequency, try using a clock in "clocks" if it exists. This patch also
fixes a bug where there could be spurious higher frequencies if sizeof(u32)
!= sizeof(ulong).

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---
This patch was previously sumbitted on its own as
https://patchwork.ozlabs.org/patch/1232420/

This patch is the combination of the patches
https://patchwork.ozlabs.org/patch/1223933/
https://patchwork.ozlabs.org/patch/1224957/
"riscv: Fix incorrect cpu frequency on RV64"
"riscv: Try to get cpu frequency from device tree"

Changes in v5:
- Include linux/err.h explicitly
- Reword commit message

Changes in v4:
- New

 drivers/cpu/riscv_cpu.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 28ad0aa30f..c6ed060abc 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -3,12 +3,14 @@
  * Copyright (C) 2018, Bin Meng 
  */
 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,9 +29,24 @@ static int riscv_cpu_get_desc(struct udevice *dev, char 
*buf, int size)
 
 static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
 {
+   int ret;
+   struct clk clk;
const char *mmu;
 
-   dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
+   /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */
+   info->cpu_freq = 0;
+
+   /* First try getting the frequency from the assigned clock */
+   ret = clk_get_by_index(dev, 0, );
+   if (!ret) {
+   ret = clk_get_rate();
+   if (!IS_ERR_VALUE(ret))
+   info->cpu_freq = ret;
+   clk_free();
+   }
+
+   if (!info->cpu_freq)
+   dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
 
mmu = dev_read_string(dev, "mmu-type");
if (!mmu)
-- 
2.25.1

[PATCH v9 18/21] riscv: Enable cpu clock if it is present

[Sean Anderson]

The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---
This patch was previously submitted on its own as
https://patchwork.ozlabs.org/patch/1232420/

Changes in v4:
- New

 drivers/cpu/riscv_cpu.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index c6ed060abc..9ce58695aa 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2018, Bin Meng 
+ * Copyright (C) 2020, Sean Anderson 
  */
 
 #include 
@@ -117,6 +118,24 @@ static int riscv_cpu_bind(struct udevice *dev)
return 0;
 }
 
+static int riscv_cpu_probe(struct udevice *dev)
+{
+   int ret = 0;
+   struct clk clk;
+
+   /* Get a clock if it exists */
+   ret = clk_get_by_index(dev, 0, );
+   if (ret)
+   return 0;
+
+   ret = clk_enable();
+   clk_free();
+   if (ret == -ENOSYS || ret == -ENOTSUPP)
+   return 0;
+   else
+   return ret;
+}
+
 static const struct cpu_ops riscv_cpu_ops = {
.get_desc   = riscv_cpu_get_desc,
.get_info   = riscv_cpu_get_info,
@@ -133,6 +152,7 @@ U_BOOT_DRIVER(riscv_cpu) = {
.id = UCLASS_CPU,
.of_match = riscv_cpu_ids,
.bind = riscv_cpu_bind,
+   .probe = riscv_cpu_probe,
.ops = _cpu_ops,
.flags = DM_FLAG_PRE_RELOC,
 };
-- 
2.25.1

[PATCH v9 13/21] riscv: Clear pending interrupts before enabling IPIs

[Sean Anderson]

On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.

Signed-off-by: Sean Anderson 
Reviewed-by: Rick Chen 
---

Changes in v7:
- Split of into its own patch

 arch/riscv/cpu/start.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6b3ff99c38..e8740c8568 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -67,6 +67,8 @@ _start:
 #else
li  t0, SIE_SSIE
 #endif
+   /* Clear any pending IPIs */
+   csrcMODE_PREFIX(ip), t0
csrsMODE_PREFIX(ie), t0
 #endif
 
-- 
2.25.1

[PATCH v9 10/21] reset: Add generic reset driver

[Sean Anderson]

This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
---

Changes in v5:
- Reorder includes
- Include linux/err.h explicitly

Changes in v4:
- Added basic test
- Fix incorrect usage of regmap_update_bits

Changes in v3:
- New

 arch/sandbox/dts/test.dts | 15 
 configs/sandbox_defconfig |  2 +
 .../reset/syscon-reset.txt| 36 +
 drivers/reset/Kconfig |  5 ++
 drivers/reset/Makefile|  1 +
 drivers/reset/reset-syscon.c  | 80 +++
 test/dm/Makefile  |  1 +
 test/dm/syscon-reset.c| 58 ++
 8 files changed, 198 insertions(+)
 create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt
 create mode 100644 drivers/reset/reset-syscon.c
 create mode 100644 test/dm/syscon-reset.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 6567a322dd..52cf7f305c 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1000,6 +1000,21 @@
clocks = <_sandbox 4>;
power-domains = < 1>;
};
+
+   resetc2: syscon-reset {
+   compatible = "syscon-reset";
+   #reset-cells = <1>;
+   regmap = <>;
+   offset = <1>;
+   mask = <0x27FF>;
+   assert-high = <0>;
+   };
+
+   syscon-reset-test {
+   compatible = "sandbox,misc_sandbox";
+   resets = < 15>, < 30>, < 60>;
+   reset-names = "valid", "no_mask", "out_of_range";
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index e09ee209f2..23506850dd 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -194,6 +194,8 @@ CONFIG_REMOTEPROC_SANDBOX=y
 CONFIG_DM_RESET=y
 CONFIG_SANDBOX_RESET=y
 CONFIG_DM_RNG=y
+CONFIG_RNG_SANDBOX=y
+CONFIG_RESET_SYSCON=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RV8803=y
 CONFIG_DEBUG_UART_SANDBOX=y
diff --git a/doc/device-tree-bindings/reset/syscon-reset.txt 
b/doc/device-tree-bindings/reset/syscon-reset.txt
new file mode 100644
index 00..f136b3d225
--- /dev/null
+++ b/doc/device-tree-bindings/reset/syscon-reset.txt
@@ -0,0 +1,36 @@
+Generic SYSCON mapped register reset driver
+
+This is a generic reset driver using syscon to map the reset register.
+The reset is generally performed with a write to the reset register
+defined by the register map pointed by syscon reference plus the offset and
+shifted by the reset specifier/
+
+To assert a reset on some device, the equivalent of the following operation is
+performed, where reset_id is the reset specifier from the device's resets
+property.
+
+   if (BIT(reset_id) & mask)
+   regmap[offset][reset_id] = assert-high;
+
+Required properties:
+- compatible: should contain "syscon-reset"
+- #reset-cells: must be 1
+- regmap: this is phandle to the register map node
+- offset: offset in the register map for the reboot register (in bytes)
+
+Optional properties:
+- mask: accept only the reset specifiers defined by the mask (32 bit)
+- assert-high: Bit to write when asserting a reset. Defaults to 1.
+
+Default will be little endian mode, 32 bit access only.
+
+Example:
+
+   reset-controller {
+   compatible = "syscon-reset";
+   #reset-cells = <1>;
+   regmap = <>;
+   offset = <0x20>;
+   mask = <0x27FF>;
+   assert-high = <0>;
+   };
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 75ccd65799..097bf32b21 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -148,4 +148,9 @@ config RESET_IMX7
help
  Support for reset controller on i.MX7/8 SoCs.
 
+config RESET_SYSCON
+   bool "Enable generic syscon reset driver support"
+   depends on DM_RESET
+   help
+ Support generic syscon mapped register reset devices.
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 0a044d5d8c..433f1eca54 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
diff --git a/drivers/reset/reset-syscon.c b/drivers/reset/reset-syscon.c
new file mode 100644
index 00..34dfe0bab6
--- /dev/null
+++ b/drivers/reset/reset-syscon.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson

[PATCH v9 12/21] riscv: Add headers for asm/global_data.h

[Sean Anderson]

This header depended on bd_t and ulong, but did not include the appropriate
headers.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v4:
- Include compiler.h not linux/compiler.h

 arch/riscv/include/asm/global_data.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index b74bd7e738..7276d9763f 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -11,6 +11,8 @@
 #define __ASM_GBL_DATA_H
 
 #include 
+#include 
+#include 
 
 /* Architecture-specific global data */
 struct arch_global_data {
-- 
2.25.1

[PATCH v9 11/21] lib: Always set errno in hcreate_r

[Sean Anderson]

This could give a confusing error message if it failed and didn't set
errno.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v5:
- New

 lib/hashtable.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/hashtable.c b/lib/hashtable.c
index 907e8a642f..e9ac7e252e 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -109,8 +109,10 @@ int hcreate_r(size_t nel, struct hsearch_data *htab)
}
 
/* There is still another table active. Return with error. */
-   if (htab->table != NULL)
+   if (htab->table != NULL) {
+   __set_errno(EINVAL);
return 0;
+   }
 
/* Change nel to the first prime number not smaller as nel. */
nel |= 1;   /* make odd */
@@ -123,8 +125,10 @@ int hcreate_r(size_t nel, struct hsearch_data *htab)
/* allocate memory and zero out */
htab->table = (struct env_entry_node *)calloc(htab->size + 1,
sizeof(struct env_entry_node));
-   if (htab->table == NULL)
+   if (htab->table == NULL) {
+   __set_errno(ENOMEM);
return 0;
+   }
 
/* everything went alright */
return 1;
-- 
2.25.1

[PATCH v9 09/21] dm: Fix error handling for dev_read_addr_ptr

[Sean Anderson]

dev_read_addr_ptr had different semantics depending on whether OF_LIVE was
enabled. This patch converts both implementations to return NULL on error,
and converts all call sites which check for FDT_ADDR_T_NONE to check for
NULL instead. This patch also removes the call to map_physmem, since we
have dev_remap_addr* for those semantics.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
Reviewed-by: Simon Glass 
---

Changes in v5:
- New

 drivers/clk/imx/clk-imx8mp.c  | 2 +-
 drivers/core/read.c   | 2 +-
 drivers/pinctrl/broadcom/pinctrl-bcm283x.c| 2 +-
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +-
 include/dm/read.h | 4 +++-
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a2693d2f7a..df30f4a087 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -281,7 +281,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", 
"sys_pll2_out", 1, 1));
 
base = dev_read_addr_ptr(dev);
-   if (base == (void *)FDT_ADDR_T_NONE)
+   if (!base)
return -EINVAL;
 
clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 
24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 47b8e03446..d8024e07a7 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -167,7 +167,7 @@ void *dev_read_addr_ptr(const struct udevice *dev)
 {
fdt_addr_t addr = dev_read_addr(dev);
 
-   return (addr == FDT_ADDR_T_NONE) ? NULL : map_sysmem(addr, 0);
+   return (addr == FDT_ADDR_T_NONE) ? NULL : addr;
 }
 
 void *dev_remap_addr(const struct udevice *dev)
diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c 
b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
index eb720f09f8..6961536a4d 100644
--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
@@ -116,7 +116,7 @@ int bcm283x_pinctl_probe(struct udevice *dev)
}
 
priv->base_reg = dev_read_addr_ptr(dev);
-   if (priv->base_reg == (void *)FDT_ADDR_T_NONE) {
+   if (!priv->base_reg) {
debug("%s: Failed to get base address\n", __func__);
return -EINVAL;
}
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c 
b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index c7351f32bb..bd95662ed5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -630,7 +630,7 @@ int mtk_pinctrl_common_probe(struct udevice *dev,
int ret;
 
priv->base = dev_read_addr_ptr(dev);
-   if (priv->base == (void *)FDT_ADDR_T_NONE)
+   if (!priv->base)
return -EINVAL;
 
priv->soc = soc;
diff --git a/include/dm/read.h b/include/dm/read.h
index 03c15b8550..e30bed2ef6 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -791,7 +791,9 @@ static inline fdt_addr_t dev_read_addr(const struct udevice 
*dev)
 
 static inline void *dev_read_addr_ptr(const struct udevice *dev)
 {
-   return devfdt_get_addr_ptr(dev);
+   void *addr = devfdt_get_addr_ptr(dev);
+
+   return ((fdt_addr_t)addr == FDT_ADDR_T_NONE) ? NULL : addr;
 }
 
 static inline fdt_addr_t dev_read_addr_pci(const struct udevice *dev)
-- 
2.25.1

[PATCH v9 16/21] riscv: Allow use of reset drivers

[Sean Anderson]

Currently, one cannot use a reset driver on RISC-V. Follow the MIPS
example, and disable the default reset handler when the sysreset driver is
enabled.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v3:
- New

 arch/riscv/lib/reset.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
index ce3c1cf872..7622e5df43 100644
--- a/arch/riscv/lib/reset.c
+++ b/arch/riscv/lib/reset.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 
+#ifndef CONFIG_SYSRESET
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
printf("resetting ...\n");
@@ -16,3 +17,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 
return 0;
 }
+#endif
-- 
2.25.1

[PATCH v9 06/21] clk: Add a bypass clock for K210

[Sean Anderson]

This is a small driver to do a software bypass of a clock if hardware
bypass is not working. I have tried to write this in a generic fashion, so
that it could be potentially broken out of the kendryte code at some future
date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
so that the CPU keeps on working.

Signed-off-by: Sean Anderson 
---

Changes in v5:
- Add function to register from a struct bypass

Changes in v4:
- New

 drivers/clk/kendryte/Makefile |   2 +-
 drivers/clk/kendryte/bypass.c | 270 ++
 include/kendryte/bypass.h |  31 
 3 files changed, 302 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/kendryte/bypass.c
 create mode 100644 include/kendryte/bypass.h

diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index c56d93ea1c..47f682fce3 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += pll.o
+obj-y += bypass.o pll.o
diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
new file mode 100644
index 00..eb3e27d055
--- /dev/null
+++ b/drivers/clk/kendryte/bypass.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson 
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#define LOG_CATEGORY UCLASS_CLK
+#include 
+
+#define CLK_K210_BYPASS "k210_clk_bypass"
+
+/*
+ * This is a small driver to do a software bypass of a clock if hardware bypass
+ * is not working. I have tried to write this in a generic fashion, so that it
+ * could be potentially broken out of the kendryte code at some future date.
+ *
+ * Say you have the following clock configuration
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ * ^
+ */|
+ *   / |
+ *  /  |
+ * /   |
+ */|
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * But the pll does not have a bypass, so when you configure the pll, the
+ * configuration needs to change to look like
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ *   ^
+ *   |\
+ *   | \
+ *   |  \
+ *   |   \
+ *   |\
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
+ * creating the child clocks, set their parent to the bypass clock. After
+ * creating all the children, call k210_bypass_setchildren().
+ */
+
+static int k210_bypass_dobypass(struct k210_bypass *bypass)
+{
+   int ret, i;
+
+   /*
+* If we already have saved parents, then the children are already
+* bypassed
+*/
+   if (bypass->child_count && bypass->saved_parents[0])
+   return 0;
+
+   for (i = 0; i < bypass->child_count; i++) {
+   struct clk *child = bypass->children[i];
+   struct clk *parent = clk_get_parent(child);
+
+   if (IS_ERR(parent)) {
+   for (; i; i--)
+   bypass->saved_parents[i] = NULL;
+   return PTR_ERR(parent);
+   }
+   bypass->saved_parents[i] = parent;
+   }
+
+   for (i = 0; i < bypass->child_count; i++) {
+   struct clk *child = bypass->children[i];
+
+   ret = clk_set_parent(child, bypass->alt);
+   if (ret) {
+   for (; i; i--)
+   clk_set_parent(bypass->children[i],
+  bypass->saved_parents[i]);
+   for (i = 0; i < bypass->child_count; i++)
+   bypass->saved_parents[i] = NULL;
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
+static int k210_bypass_unbypass(struct k210_bypass *bypass)
+{
+   int err, ret, i;
+
+   if (!bypass->child_count && !bypass->saved_parents[0]) {
+   log_warning("Cannot unbypass children; dobypass not called 
first\n");
+   return 0;
+   }
+
+   ret = 0;
+   for (i = 0; i < bypass->child_count; i++) {
+   err = clk_set_parent(bypass->children[i],
+bypass->saved_parents[i]);
+   if (err)
+   ret = err;
+   bypass->saved_parents[i] = NULL;
+   }
+   return ret;
+}
+
+static ulong k210_bypass_get_rate(struct clk *clk)
+{
+   struct k210_bypass *bypass = to_k210_bypass(clk);
+   const struct clk_ops *ops = bypass->bypassee_ops;
+
+   if (ops->get_rate)
+   return ops->get_rate(bypass->bypassee);
+   else
+   return clk_get_parent_rate(bypass->bypassee);
+}
+
+static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
+{
+   int ret;
+   struct k210_bypass *bypass = to_k210_bypass(clk);
+   const struct clk_ops *ops = bypass->bypassee_ops;
+
+   /* Don't bother bypassing if we aren't going to set the rate */
+   if 

[PATCH v9 05/21] clk: Add K210 pll support

[Sean Anderson]

This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.

Signed-off-by: Sean Anderson 
---

Changes in v8:
- Rename k210_pll_params to k210_pll_config to avoid a name conflict with the
  rest of the clock code
Changes in v6:
- Reformat code to reduce checkpatch errors

Changes in v5:
- Add function to register from a struct

Changes in v4:
- Rename the reference clock to "divider clock", and input clock to "reference
  clock" to match the upstream documentation.
- Add a test for calc_params. This currently resides in test/dm, but perhaps it
  should be moved to its own directory.
- Update MAINTAINERS
- Update copyright
- Lint

Changes in v3:
- Add an option to not include support for setting the pll rate. This saves
  around 1K in the final executable.
- Remove udelays to suppress warnings
- Bypass PLL after enabling, instead of before
- Check if the PLL is enabled already before doing a reset
- Fix bug with locked mask

Changes in v2:
- Rename driver to "k210_clk_pll"
- Add additional in-line documentation on algorithm and PLLs
- Restrict the range of internal VCO and reference frequencies
- Don't load driver before relocation
- Remove spurious references to mach-k210

 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   1 +
 drivers/clk/kendryte/Kconfig  |  12 +
 drivers/clk/kendryte/Makefile |   1 +
 drivers/clk/kendryte/pll.c| 601 ++
 include/kendryte/pll.h|  57 
 include/test/export.h |  16 +
 test/dm/Makefile  |   1 +
 test/dm/k210_pll.c|  96 ++
 9 files changed, 786 insertions(+)
 create mode 100644 drivers/clk/kendryte/Kconfig
 create mode 100644 drivers/clk/kendryte/Makefile
 create mode 100644 drivers/clk/kendryte/pll.c
 create mode 100644 include/kendryte/pll.h
 create mode 100644 include/test/export.h
 create mode 100644 test/dm/k210_pll.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 1992d4a4b4..fb8335267b 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -155,6 +155,7 @@ source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/imx/Kconfig"
+source "drivers/clk/kendryte/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/owl/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e01783391d..d911954581 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
 obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
+obj-$(CONFIG_CLK_K210) += kendryte/
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
 obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
new file mode 100644
index 00..7b69c8afaf
--- /dev/null
+++ b/drivers/clk/kendryte/Kconfig
@@ -0,0 +1,12 @@
+config CLK_K210
+   bool "Clock support for Kendryte K210"
+   depends on CLK && CLK_CCF
+   help
+ This enables support clock driver for Kendryte K210 platforms.
+
+config CLK_K210_SET_RATE
+   bool "Enable setting the Kendryte K210 PLL rate"
+   depends on CLK_K210
+   help
+ Add functionality to calculate new rates for K210 PLLs. Enabling this
+ feature adds around 1K to U-Boot's final size.
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
new file mode 100644
index 00..c56d93ea1c
--- /dev/null
+++ b/drivers/clk/kendryte/Makefile
@@ -0,0 +1 @@
+obj-y += pll.o
diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
new file mode 100644
index 00..2c5d5b8857
--- /dev/null
+++ b/drivers/clk/kendryte/pll.c
@@ -0,0 +1,601 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson 
+ */
+#include 
+
+#define LOG_CATEGORY UCLASS_CLK
+#include 
+/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLK_K210_PLL "k210_clk_pll"
+
+#ifdef CONFIG_CLK_K210_SET_RATE
+static int k210_pll_enable(struct clk *clk);
+static int k210_pll_disable(struct clk *clk);
+
+/*
+ * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
+ * General-Purpose PLL. The logical layout of the PLL with internal feedback is
+ * approximately the following:
+ *
+ *  +---+
+ *  |reference clock|
+ *  +---+
+ *  |
+ *  v
+ *+--+
+ *|/r|
+ *+--+
+ *  |
+ *  v
+ *   +-+
+ *   |divided clock|
+ *   +-+
+ *  |
+ *  v
+ *  

[PATCH v9 08/21] dm: Add support for simple-pm-bus

[Sean Anderson]

This type of bus is used in Linux to designate buses which have power
domains and/or clocks which need to be enabled before their child devices
can be used. Because power domains are automatically enabled before probing
in U-Boot, we just need to enable any clocks present.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
---

Changes in v5:
- Reorder includes (simple pm)

Changes in v4:
- Split the bus off into its own driver
- Add test
- Fix line spacing in Kconfig
- Lint

Changes in v3:
- New

 arch/sandbox/dts/test.dts |  6 ++
 arch/sandbox/include/asm/clk.h|  1 +
 configs/sandbox_defconfig |  1 +
 .../bus/simple-pm-bus.txt | 44 +++
 drivers/core/Kconfig  |  7 +++
 drivers/core/Makefile |  1 +
 drivers/core/simple-pm-bus.c  | 56 +++
 test/dm/Makefile  |  1 +
 test/dm/simple-pm-bus.c   | 45 +++
 9 files changed, 162 insertions(+)
 create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt
 create mode 100644 drivers/core/simple-pm-bus.c
 create mode 100644 test/dm/simple-pm-bus.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index df9f1835c9..6567a322dd 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -994,6 +994,12 @@
mdio: mdio-test {
compatible = "sandbox,mdio";
};
+
+   pm-bus-test {
+   compatible = "simple-pm-bus";
+   clocks = <_sandbox 4>;
+   power-domains = < 1>;
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index 1573e4a134..c184c4bffc 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -21,6 +21,7 @@ enum sandbox_clk_id {
SANDBOX_CLK_ID_I2C,
SANDBOX_CLK_ID_UART1,
SANDBOX_CLK_ID_UART2,
+   SANDBOX_CLK_ID_BUS,
 
SANDBOX_CLK_ID_COUNT,
 };
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index cc38315868..e09ee209f2 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -94,6 +94,7 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
+CONFIG_SIMPLE_PM_BUS=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
 CONFIG_AXI=y
diff --git a/doc/device-tree-bindings/bus/simple-pm-bus.txt 
b/doc/device-tree-bindings/bus/simple-pm-bus.txt
new file mode 100644
index 00..6f15037131
--- /dev/null
+++ b/doc/device-tree-bindings/bus/simple-pm-bus.txt
@@ -0,0 +1,44 @@
+Simple Power-Managed Bus
+
+
+A Simple Power-Managed Bus is a transparent bus that doesn't need a real
+driver, as it's typically initialized by the boot loader.
+
+However, its bus controller is part of a PM domain, or under the control of a
+functional clock.  Hence, the bus controller's PM domain and/or clock must be
+enabled for child devices connected to the bus (either on-SoC or externally)
+to function.
+
+While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
+in the Devicetree Specification, it is not an extension of "simple-bus".
+
+
+Required properties:
+  - compatible: Must contain at least "simple-pm-bus".
+   Must not contain "simple-bus".
+   It's recommended to let this be preceded by one or more
+   vendor-specific compatible values.
+  - #address-cells, #size-cells, ranges: Must describe the mapping between
+   parent address and child address spaces.
+
+Optional platform-specific properties for clock or PM domain control (at least
+one of them is required):
+  - clocks: Must contain a reference to the functional clock(s),
+  - power-domains: Must contain a reference to the PM domain.
+Please refer to the binding documentation for the clock and/or PM domain
+providers for more details.
+
+
+Example:
+
+   bsc: bus@fec1 {
+   compatible = "renesas,bsc-sh73a0", "renesas,bsc",
+"simple-pm-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0 0x2000>;
+   reg = <0xfec1 0x400>;
+   interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <_clk>;
+   power-domains = <_a4s>;
+   };
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index a3b0399342..a594899f37 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -195,6 +195,13 @@ config SPL_SIMPLE_BUS
  Supports the 'simple-bus' driver, which is used on some systems
  in SPL.
 
+config SIMPLE_PM_BUS
+   bool "Support simple-pm-bus driver"
+   depends on DM && OF_CONTROL && CLK && POWER_DOMAIN
+   help
+ Supports the 'simple-pm-bus' driver, which is used for busses that
+ have power domains and/or clocks which need to be 

[PATCH v9 02/21] clk: Check that ops of composite clock components exist before calling

[Sean Anderson]

clk_composite_ops was shared between all devices in the composite clock
driver.  If one clock had a feature (such as supporting set_parent) which
another clock did not, it could call a null pointer dereference.

This patch does three things
1. It adds null-pointer checks to all composite clock functions.
2. It makes clk_composite_ops const and sets its functions at compile-time.
3. It adds some basic sanity checks to num_parents.

The combined effect of these changes is that any of mux, rate, or gate can
be NULL, and composite clocks will still function normally. Previously, at
least mux had to exist, since clk_composite_get_parent was used to
determine the parent for clk_register.

Signed-off-by: Sean Anderson 
Acked-by: Lukasz Majewski 
---

Changes in v4:
- Return ENOTSUPP not ENOSYS with no set_parent

Changes in v3:
- Don't return an error code where a no-op would be fine

 drivers/clk/clk-composite.c | 57 +++--
 1 file changed, 35 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 2ff1d6b47f..819bfca2fc 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -24,7 +24,10 @@ static u8 clk_composite_get_parent(struct clk *clk)
(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
struct clk *mux = composite->mux;
 
-   return clk_mux_get_parent(mux);
+   if (mux)
+   return clk_mux_get_parent(mux);
+   else
+   return 0;
 }
 
 static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
@@ -34,7 +37,10 @@ static int clk_composite_set_parent(struct clk *clk, struct 
clk *parent)
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk *mux = composite->mux;
 
-   return mux_ops->set_parent(mux, parent);
+   if (mux && mux_ops)
+   return mux_ops->set_parent(mux, parent);
+   else
+   return -ENOTSUPP;
 }
 
 static unsigned long clk_composite_recalc_rate(struct clk *clk)
@@ -44,7 +50,10 @@ static unsigned long clk_composite_recalc_rate(struct clk 
*clk)
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *rate = composite->rate;
 
-   return rate_ops->get_rate(rate);
+   if (rate && rate_ops)
+   return rate_ops->get_rate(rate);
+   else
+   return clk_get_parent_rate(clk);
 }
 
 static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
@@ -54,7 +63,10 @@ static ulong clk_composite_set_rate(struct clk *clk, 
unsigned long rate)
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *clk_rate = composite->rate;
 
-   return rate_ops->set_rate(clk_rate, rate);
+   if (rate && rate_ops)
+   return rate_ops->set_rate(clk_rate, rate);
+   else
+   return clk_get_rate(clk);
 }
 
 static int clk_composite_enable(struct clk *clk)
@@ -64,7 +76,10 @@ static int clk_composite_enable(struct clk *clk)
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk *gate = composite->gate;
 
-   return gate_ops->enable(gate);
+   if (gate && gate_ops)
+   return gate_ops->enable(gate);
+   else
+   return 0;
 }
 
 static int clk_composite_disable(struct clk *clk)
@@ -74,15 +89,12 @@ static int clk_composite_disable(struct clk *clk)
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk *gate = composite->gate;
 
-   gate_ops->disable(gate);
-
-   return 0;
+   if (gate && gate_ops)
+   return gate_ops->disable(gate);
+   else
+   return 0;
 }
 
-struct clk_ops clk_composite_ops = {
-   /* This will be set according to clk_register_composite */
-};
-
 struct clk *clk_register_composite(struct device *dev, const char *name,
   const char * const *parent_names,
   int num_parents, struct clk *mux,
@@ -96,7 +108,9 @@ struct clk *clk_register_composite(struct device *dev, const 
char *name,
struct clk *clk;
struct clk_composite *composite;
int ret;
-   struct clk_ops *composite_ops = _composite_ops;
+
+   if (!num_parents || (num_parents != 1 && !mux))
+   return ERR_PTR(-EINVAL);
 
composite = kzalloc(sizeof(*composite), GFP_KERNEL);
if (!composite)
@@ -105,8 +119,6 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
if (mux && mux_ops) {
composite->mux = mux;
composite->mux_ops = mux_ops;
-   if (mux_ops->set_parent)
-   composite_ops->set_parent = clk_composite_set_parent;
mux->data = (ulong)composite;
}
 
@@ -115,11 +127,6 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
clk = ERR_PTR(-EINVAL);
goto err;

[PATCH v9 04/21] clk: Fix clk_get_by_* handling of index

[Sean Anderson]

clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean
predicate instead of the index. Other clk_get_by_* functions got the clock
correctly, but passed a predicate instead of the index to clk_get_by_tail.
This could lead to confusing error messages.

Signed-off-by: Sean Anderson 
---

Changes in v7:
- New

 drivers/clk/clk-uclass.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index aa8dd9d027..c082fe95ff 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -121,7 +121,7 @@ static int clk_get_by_indexed_prop(struct udevice *dev, 
const char *prop_name,
 
 
return clk_get_by_index_tail(ret, dev_ofnode(dev), , "clocks",
-index > 0, clk);
+index, clk);
 }
 
 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
@@ -133,7 +133,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct 
clk *clk)
 index, );
 
return clk_get_by_index_tail(ret, dev_ofnode(dev), , "clocks",
-index > 0, clk);
+index, clk);
 }
 
 int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
@@ -142,10 +142,10 @@ int clk_get_by_index_nodev(ofnode node, int index, struct 
clk *clk)
int ret;
 
ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
-index > 0, );
+index, );
 
return clk_get_by_index_tail(ret, node, , "clocks",
-index > 0, clk);
+index, clk);
 }
 
 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
-- 
2.25.1

[PATCH v9 07/21] clk: Add K210 clock support

[Sean Anderson]

Due to the large number of clocks, I decided to use the CCF. The overall
structure is modeled after the imx code. Clocks parameters are stored in
several arrays, and are then instantiated at run-time. There are some
translation macros (FOOIFY()) which allow for more dense packing.

Signed-off-by: Sean Anderson 
---

Changes in v8:
- Rework code to not need a new CCF api
- Add some documentation

Changes in v7:
- Add numbering to some sysctl registers

Changes in v6:
- Reformat code so checkpatch generates fewer warnings
- Give "fictional" clocks their own ids
- Rename sysctl CLK_FREQ register to UART_BAUD to better reflect its
  semantics

Changes in v5:
- Don't unmap priv->reg
- Remove comment on APB clocks since it has been clarified by Kendryte
- Add i2s mclks
- Reorder clock ids to be continuous
- Rewrite to statically allocate all clocks. This has helped find several
  bugs (since it is easy to see when a clock has the wrong register).
- Fix ACLK sometimes having the wrong parent
- Fix SPI3 having the wrong divider
- Prevent being probed multiple times on failure

Changes in v4:
- Reparent aclk before configuring pll0
- Update copyright
- Lint

Changes in v3:
- Removed sysctl struct, replacing it with defines. This is to have the
  same interface to sysctl from C as from the device tree.
- Fixed clocks having the same id
- Fixed clocks not using the correct register/bits
- Aligned the defines in headers

Changes in v2:
- Add clk.o to obj-y
- Don't probe before relocation

 MAINTAINERS   |   7 +
 .../mfd/kendryte,k210-sysctl.txt  |  33 +
 drivers/clk/kendryte/Kconfig  |   2 +-
 drivers/clk/kendryte/Makefile |   2 +-
 drivers/clk/kendryte/clk.c| 663 ++
 include/dt-bindings/clock/k210-sysctl.h   |  59 ++
 include/dt-bindings/mfd/k210-sysctl.h |  38 +
 include/kendryte/clk.h|  35 +
 8 files changed, 837 insertions(+), 2 deletions(-)
 create mode 100644 doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
 create mode 100644 drivers/clk/kendryte/clk.c
 create mode 100644 include/dt-bindings/clock/k210-sysctl.h
 create mode 100644 include/dt-bindings/mfd/k210-sysctl.h
 create mode 100644 include/kendryte/clk.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 7ac7e21ba1..88443bf82d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -830,6 +830,13 @@ F: arch/riscv/
 F: cmd/riscv/
 F: tools/prelink-riscv.c
 
+RISC-V KENDRYTE
+M: Sean Anderson 
+S: Maintained
+F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
+F: drivers/clk/kendryte/
+F: include/kendryte/
+
 RNG
 M: Sughosh Ganu 
 R: Heinrich Schuchardt 
diff --git a/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt 
b/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
new file mode 100644
index 00..5b24abcb62
--- /dev/null
+++ b/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
@@ -0,0 +1,33 @@
+Kendryte K210 Sysctl
+
+This binding describes the K210 sysctl device, which contains many 
miscellaneous
+registers controlling system functionality. This node is a register map and can
+be reference by other bindings which need a phandle to the K210 sysctl regmap.
+
+Required properties:
+- compatible: should be
+   "kendryte,k210-sysctl", "syscon", "simple-mfd"
+- reg: address and length of the sysctl registers
+- reg-io-width: must be <4>
+
+Clock sub-node
+
+This node is a binding for the clock tree driver
+
+Required properties:
+- compatible: should be "kendryte,k210-clk"
+- clocks: phandle to the "in0" external oscillator
+- #clock-cells: must be <1>
+
+Example:
+sysctl: syscon@5044 {
+   compatible = "kendryte,k210-sysctl", "syscon", "simple-mfd";
+   reg = <0x5044 0x100>;
+   reg-io-width = <4>;
+
+   sysclk: clock-controller {
+   compatible = "kendryte,k210-clk";
+   clocks = <>;
+   #clock-cells = <1>;
+   };
+};
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
index 7b69c8afaf..073fca0781 100644
--- a/drivers/clk/kendryte/Kconfig
+++ b/drivers/clk/kendryte/Kconfig
@@ -1,6 +1,6 @@
 config CLK_K210
bool "Clock support for Kendryte K210"
-   depends on CLK && CLK_CCF
+   depends on CLK && CLK_CCF && CLK_COMPOSITE_CCF
help
  This enables support clock driver for Kendryte K210 platforms.
 
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index 47f682fce3..6fb68253ae 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += bypass.o pll.o
+obj-y += bypass.o clk.o pll.o
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
new file mode 100644
index 00..981b3b7699
--- /dev/null
+++ b/drivers/clk/kendryte/clk.c
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson 
+ */
+#include 
+
+#include 
+#include 

[PATCH v9 00/21] riscv: Add Sipeed Maix support

[Sean Anderson]

This patch series adds support for Sipeed Maix boards and the Kendryte
K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
models are similar.

Known Bugs/Limitations:
- Accessing the AI ram hangs, limiting available ram to 6M
- Trying to boot an image with bootm fails with
  ERROR: Failed to allocate 0x7d60 bytes below 0x8000.

To flash u-boot to a maix bit, run
kflash -tp /dev/ -B bit_mic u-boot-dtb.bin

Boot output should look like the following:

U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)

DRAM:  8 MiB
In:serial@3800
Out:   serial@3800
Err:   serial@3800
=>

Changes for v9:
- Fix error in Andes PLIC
- Update MAINTAINERS
- Mark dts blocks in documentation as "none" highlighting

Changes for v8:
- Removed dependency on the patch "clk: Add functions to register CCF clock
  structs". Hopefully this will make reviewing easier.

Changes for v7:
- Split documentation from other board support
- Split IPI clear from other IPI cleanup
- Rebased onto a clean upstream. Hopefully this fixes any patching
  problems.

Changes for v6:
- Remove spi, pinmux, gpio, led, and wdt support --- to be added in separate
  patches
- Rebase onto master
- Clear IPIs before enabling them
- Reorganize code so checkpatch errors less

Changes for v5:
- Rebase onto master
- Add pinconf support
- Add gpio support
- Store environment in spi flash
- Group patches by prefix
- Add additional documentation
- Add SMP support
- Add WDT support

Changes for v4:
- Linted several patches
- Updated the copyright year for several files
- Added tests for syscon-reset, simple-pm-bus, and the pll calc_rate function
- Added/updated documentation
- Fixed SPI for the nor flash
- Fixed PLLs not enabling/setting rate properly
- RISCV_PRIV_1_9_1 now (un)defines all diferring CSRs, and also disables VM
- More devicetree changes

Changes for v3:
- Remove patch to set RV64I as default
- Remove patch for a separate sysctl driver
- Split off cpu frequency patch into its own series
- Reorder support/devicetree patches to come last
- Add patch for reset driver
- Add simple-pm-bus for busses with their own clocks
- Add additional documentation
- Reword mcounteren patch to refer to the RISC-V priv spec 1.9.1
- Many devicetree changes
- Switch to "make savedefconfig" to generate the config

Changes for v2:
- Many bugfixes for the device tree
- Modify the config to build without errors
- Add support for keeping internal PLL frequencies in-range
- Fix several rebase-induced artifacts

Sean Anderson (21):
  clk: Always use the supplied struct clk
  clk: Check that ops of composite clock components exist before calling
  clk: Unconditionally recursively en-/dis-able clocks
  clk: Fix clk_get_by_* handling of index
  clk: Add K210 pll support
  clk: Add a bypass clock for K210
  clk: Add K210 clock support
  dm: Add support for simple-pm-bus
  dm: Fix error handling for dev_read_addr_ptr
  reset: Add generic reset driver
  lib: Always set errno in hcreate_r
  riscv: Add headers for asm/global_data.h
  riscv: Clear pending interrupts before enabling IPIs
  riscv: Clean up IPI initialization code
  riscv: Add option to support RISC-V privileged spec 1.9
  riscv: Allow use of reset drivers
  riscv: Try to get cpu frequency from a "clocks" node if it exists
  riscv: Enable cpu clock if it is present
  riscv: Add device tree for K210 and Sipeed Maix BitM
  doc: riscv: Add documentation for Sipeed Maix Bit
  riscv: Add Sipeed Maix support

 MAINTAINERS   |   7 +
 arch/riscv/Kconfig|  14 +
 arch/riscv/cpu/cpu.c  |  15 +
 arch/riscv/cpu/start.S|   2 +
 arch/riscv/dts/Makefile   |   1 +
 arch/riscv/dts/k210-maix-bit.dts  |  47 ++
 arch/riscv/dts/k210.dtsi  | 594 
 arch/riscv/include/asm/csr.h  |  40 ++
 arch/riscv/include/asm/global_data.h  |   2 +
 arch/riscv/include/asm/smp.h  |  43 ++
 arch/riscv/lib/andes_plic.c   |  34 +-
 arch/riscv/lib/reset.c|   2 +
 arch/riscv/lib/sbi_ipi.c  |   5 +
 arch/riscv/lib/sifive_clint.c |  33 +-
 arch/riscv/lib/smp.c  |  56 +-
 arch/sandbox/dts/test.dts |  21 +
 arch/sandbox/include/asm/clk.h|   1 +
 board/sipeed/maix/Kconfig |  47 ++
 board/sipeed/maix/MAINTAINERS |  11 +
 board/sipeed/maix/Makefile|   5 +
 board/sipeed/maix/maix.c  |  41 ++
 configs/sandbox_defconfig |   3 +
 configs/sipeed_maix_bitm_defconfig|   8 +
 doc/board/index.rst   |   1 +
 doc/board/sipeed/index.rst|   9 +
 doc/board/sipeed/maix.rst | 298 
 .../bus/simple-pm-bus.txt   

[PATCH v9 03/21] clk: Unconditionally recursively en-/dis-able clocks

[Sean Anderson]

For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
just enable them as normal. The enable count is local to the struct clk,
but this will never result in the actual en-/dis-able op being called
(unless the same struct clk is enabled twice).

For clocks in the CCF, we always traverse up the tree when enabling.
Previously, CCF clocks without id set would be skipped, stopping the
traversal too early.

Signed-off-by: Sean Anderson 
---

Changes in v6:
- Fix disable incorrectly recursing into non-clock devices

Changes in v5:
- Clear enable_count on request

Changes in v4:
- Lint

Changes in v3:
- New

 drivers/clk/clk-uclass.c | 60 ++--
 1 file changed, 27 insertions(+), 33 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 71878474eb..aa8dd9d027 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -410,6 +410,7 @@ int clk_request(struct udevice *dev, struct clk *clk)
ops = clk_dev_ops(dev);
 
clk->dev = dev;
+   clk->enable_count = 0;
 
if (!ops->request)
return 0;
@@ -521,7 +522,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 int clk_enable(struct clk *clk)
 {
const struct clk_ops *ops;
-   struct clk *clkp = NULL;
int ret;
 
debug("%s(clk=%p)\n", __func__, clk);
@@ -530,32 +530,29 @@ int clk_enable(struct clk *clk)
ops = clk_dev_ops(clk->dev);
 
if (CONFIG_IS_ENABLED(CLK_CCF)) {
-   /* Take id 0 as a non-valid clk, such as dummy */
-   if (clk->id && !clk_get_by_id(clk->id, )) {
-   if (clkp->enable_count) {
-   clkp->enable_count++;
-   return 0;
-   }
-   if (clkp->dev->parent &&
-   device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
-   ret = 
clk_enable(dev_get_clk_ptr(clkp->dev->parent));
-   if (ret) {
-   printf("Enable %s failed\n",
-  clkp->dev->parent->name);
-   return ret;
-   }
+   if (clk->enable_count) {
+   clk->enable_count++;
+   return 0;
+   }
+   if (clk->dev->parent &&
+   device_get_uclass_id(clk->dev->parent) == UCLASS_CLK) {
+   ret = clk_enable(dev_get_clk_ptr(clk->dev->parent));
+   if (ret) {
+   printf("Enable %s failed\n",
+  clk->dev->parent->name);
+   return ret;
}
}
 
if (ops->enable) {
ret = ops->enable(clk);
if (ret) {
-   printf("Enable %s failed\n", clk->dev->name);
+   printf("Enable %s failed (error %d)\n",
+  clk->dev->name, ret);
return ret;
}
}
-   if (clkp)
-   clkp->enable_count++;
+   clk->enable_count++;
} else {
if (!ops->enable)
return -ENOSYS;
@@ -581,7 +578,6 @@ int clk_enable_bulk(struct clk_bulk *bulk)
 int clk_disable(struct clk *clk)
 {
const struct clk_ops *ops;
-   struct clk *clkp = NULL;
int ret;
 
debug("%s(clk=%p)\n", __func__, clk);
@@ -590,29 +586,27 @@ int clk_disable(struct clk *clk)
ops = clk_dev_ops(clk->dev);
 
if (CONFIG_IS_ENABLED(CLK_CCF)) {
-   if (clk->id && !clk_get_by_id(clk->id, )) {
-   if (clkp->enable_count == 0) {
-   printf("clk %s already disabled\n",
-  clkp->dev->name);
-   return 0;
-   }
-
-   if (--clkp->enable_count > 0)
-   return 0;
+   if (clk->enable_count == 0) {
+   printf("clk %s already disabled\n",
+  clk->dev->name);
+   return 0;
}
 
+   if (--clk->enable_count > 0)
+   return 0;
+
if (ops->disable) {
ret = ops->disable(clk);
if (ret)
return ret;
}
 
-   if (clkp && clkp->dev->parent &&
-   device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
-   ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
+   if (clk->dev->parent &&
+   

[PATCH v9 01/21] clk: Always use the supplied struct clk

[Sean Anderson]

CCF clocks should always use the struct clock passed to their methods for
extracting the driver-specific clock information struct. Previously, many
functions would use the clk->dev->priv if the device was bound. This could
cause problems with composite clocks. The individual clocks in a composite
clock did not have the ->dev field filled in. This was fine, because the
device-specific clock information would be used. However, since there was
no ->dev, there was no way to get the parent clock. This caused the
recalc_rate method of the CCF divider clock to fail. One option would be to
use the clk->priv field to get the composite clock and from there get the
appropriate parent device. However, this would tie the implementation to
the composite clock. In general, different devices should not rely on the
contents of ->priv from another device.

The simple solution to this problem is to just always use the supplied
struct clock. The composite clock now fills in the ->dev pointer of its
child clocks.  This allows child clocks to make calls like clk_get_parent()
without issue.

imx avoided the above problem by using a custom get_rate function with
composite clocks.

Signed-off-by: Sean Anderson 
Acked-by: Lukasz Majewski 
---

Changes in v4:
- Lint

Changes in v3:
- Documented new assumptions in the CCF
- Wrapped docs to 80 columns

 doc/imx/clk/ccf.txt| 63 +-
 drivers/clk/clk-composite.c|  7 
 drivers/clk/clk-divider.c  |  6 ++--
 drivers/clk/clk-fixed-factor.c |  3 +-
 drivers/clk/clk-gate.c |  6 ++--
 drivers/clk/clk-mux.c  | 12 +++
 drivers/clk/imx/clk-gate2.c|  4 +--
 7 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/doc/imx/clk/ccf.txt b/doc/imx/clk/ccf.txt
index 36b60dc438..e40ac360e8 100644
--- a/doc/imx/clk/ccf.txt
+++ b/doc/imx/clk/ccf.txt
@@ -1,42 +1,37 @@
 Introduction:
 =
 
-This documentation entry describes the Common Clock Framework [CCF]
-port from Linux kernel (v5.1.12) to U-Boot.
+This documentation entry describes the Common Clock Framework [CCF] port from
+Linux kernel (v5.1.12) to U-Boot.
 
-This code is supposed to bring CCF to IMX based devices (imx6q, imx7
-imx8). Moreover, it also provides some common clock code, which would
-allow easy porting of CCF Linux code to other platforms.
+This code is supposed to bring CCF to IMX based devices (imx6q, imx7 imx8).
+Moreover, it also provides some common clock code, which would allow easy
+porting of CCF Linux code to other platforms.
 
 Design decisions:
 =
 
-* U-Boot's driver model [DM] for clk differs from Linux CCF. The most
-  notably difference is the lack of support for hierarchical clocks and
-  "clock as a manager driver" (single clock DTS node acts as a starting
-  point for all other clocks).
+* U-Boot's driver model [DM] for clk differs from Linux CCF. The most notably
+  difference is the lack of support for hierarchical clocks and "clock as a
+  manager driver" (single clock DTS node acts as a starting point for all other
+  clocks).
 
-* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE
-  is not set (no need for recursive access).
+* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE is
+  not set (no need for recursive access).
 
-* On purpose the "manager" clk driver (clk-imx6q.c) is not using large
-  table to store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = 
-  Instead we use udevice's linked list for the same class (UCLASS_CLK).
+* On purpose the "manager" clk driver (clk-imx6q.c) is not using large table to
+  store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] =  Instead we
+  use udevice's linked list for the same class (UCLASS_CLK).
 
   Rationale:
   --
-When porting the code as is from Linux, one would need ~1KiB of RAM to
-store it. This is way too much if we do plan to use this driver in SPL.
+When porting the code as is from Linux, one would need ~1KiB of RAM to 
store
+it. This is way too much if we do plan to use this driver in SPL.
 
 * The "central" structure of this patch series is struct udevice and its
   uclass_priv field contains the struct clk pointer (to the originally created
   one).
 
-* Up till now U-Boot's driver model (DM) CLK operates on udevice (main
-  access to clock is by udevice ops)
-  In the CCF the access to struct clk (embodying pointer to *dev) is
-  possible via dev_get_clk_ptr() (it is a wrapper on dev_get_uclass_priv()).
-
 * To keep things simple the struct udevice's uclass_priv pointer is used to
   store back pointer to corresponding struct clk. However, it is possible to
   modify clk-uclass.c file and add there struct uc_clk_priv, which would have
@@ -45,13 +40,17 @@ Design decisions:
   setting .per_device_auto_alloc_size = sizeof(struct uc_clk_priv)) the
   uclass_priv stores the pointer to struct clk.
 
+* Non-CCF clocks do not have a pointer to a clock in 

Re: [PATCH v8 00/21] riscv: Add Sipeed Maix support

[Sean Anderson]

On 4/22/20 10:12 PM, Sean Anderson wrote:
> On 4/22/20 10:10 PM, Bin Meng wrote:
>> Hi Sean,
>>
>> On Thu, Apr 23, 2020 at 10:03 AM Sean Anderson  wrote:
>>>
>>> On 4/22/20 9:51 PM, Rick Chen wrote:
 Hi Sean

> Hi Sean
>
>> This patch series adds support for Sipeed Maix boards and the Kendryte
>> K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
>> models are similar.
>>
>> Known Bugs/Limitations:
>> - Accessing the AI ram hangs, limiting available ram to 6M
>> - Trying to boot an image with bootm fails with
>>   ERROR: Failed to allocate 0x7d60 bytes below 0x8000.
>>
>> To flash u-boot to a maix bit, run
>> kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
>>
>> Boot output should look like the following:
>>
>> U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
>>
>> DRAM:  8 MiB
>> In:serial@3800
>> Out:   serial@3800
>> Err:   serial@3800
>> =>
>>
>> Changes for v8:
>> - Removed dependency on the patch "clk: Add functions to register CCF 
>> clock
>>   structs". Hopefully this will make reviewing easier.
>
> I have applied this patch series to u-boot-riscv/master except [PATCH
> v8 14/21] riscv: Clean up IPI initialization code.
> Because it will cause some warnings as below:
>
> arch/riscv/lib/andes_plic.c: In function 'riscv_init_ipi':
> arch/riscv/lib/andes_plic.c:84:12: warning: initialization makes
> integer from pointer without a cast [-Wint-conversion]
>   int ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
> ^~
> arch/riscv/lib/andes_plic.c:86:13: warning: passing argument 1 of
> 'IS_ERR' makes pointer from integer without a cast [-Wint-conversion]
>   if (IS_ERR(ret))
>  ^~~
> In file included from arch/riscv/lib/andes_plic.c:20:0:
> include/linux/err.h:34:20: note: expected 'const void *' but argument
> is of type 'int'
>  static inline long IS_ERR(const void *ptr)
> ^~
> arch/riscv/lib/andes_plic.c:87:18: warning: passing argument 1 of
> 'PTR_ERR' makes pointer from integer without a cast [-Wint-conversion]
>return PTR_ERR(ret);
>   ^~~
> In file included from arch/riscv/lib/andes_plic.c:20:0:
> include/linux/err.h:29:20: note: expected 'const void *' but argument
> is of type 'int'
>  static inline long PTR_ERR(const void *ptr)
> ^~~
> arch/riscv/lib/andes_plic.c:88:16: warning: assignment makes pointer
> from integer without a cast [-Wint-conversion]
>   gd->arch.plic = ret;
>

This was caused by the ret variable being the wrong type; should be
fixed.


 after running CI yesterday, it failed in many cases:
 https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678023975

 and I trace at least two cases belong to your patch
 49.59
 https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024035

 arning, treated as error:
 /home/travis/build/rickchen36/u-boot-riscv/doc/board/sipeed/maix.rst:173:Error
 in "code-block" directive:
 1 argument(s) required, 0 supplied.
 .. code-block::
  {
 assigned-clocks = < K210_CLK_PLL0>;
 assigned-clock-rates = <8>;
 };
 doc/Makefile:69: recipe for target 'htmldocs' failed
 make[1]: *** [htmldocs] Error 1
>>>
>>> I used to have
>>>
>>> .. code-block:: dts
>>>
>>> but it warned that "dts" was not a valid language, so I dropped it
>>>

I've marked these blocks as "none" instead.

 49.66
 https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024042

 ./tools/patman/patman --test && ./tools/buildman/buildman -t &&
 ./tools/dtoc/dtoc -t && make testconfig; fi; fi
 cp: cannot create regular file
 '/home/travis/build/rickchen36/sandbox/': Not a directory
 cp: cannot create regular file
 '/home/travis/build/rickchen36/sandbox/': Not a directory
 WARNING: no status info for 'sipeed_maix_bitm'
 WARNING: no maintainers for 'sipeed_maix_bitm'
>>>
>>> I'm not sure what the issue here is. Which specific files are lacking a
>>> MAINTAINERS entry?
>>>
>>
>> You need create a MAINTAINERS file in the board directory.
> 
> It is already created.

Ok, I think this is because the defconfig was renamed at some point but
MAINTAINERS was not update to reflect the change.

> 
>>

 So I will drop your patchs and run CI again today.
 And hope you can fix them in next version and pass CI verification.
>>>
>>
>> Regards,
>> Bin
>>
> 

Re: [PATCH v8 00/21] riscv: Add Sipeed Maix support

[Sean Anderson]

On 4/22/20 10:10 PM, Bin Meng wrote:
> Hi Sean,
> 
> On Thu, Apr 23, 2020 at 10:03 AM Sean Anderson  wrote:
>>
>> On 4/22/20 9:51 PM, Rick Chen wrote:
>>> Hi Sean
>>>
 Hi Sean

> This patch series adds support for Sipeed Maix boards and the Kendryte
> K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
> models are similar.
>
> Known Bugs/Limitations:
> - Accessing the AI ram hangs, limiting available ram to 6M
> - Trying to boot an image with bootm fails with
>   ERROR: Failed to allocate 0x7d60 bytes below 0x8000.
>
> To flash u-boot to a maix bit, run
> kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
>
> Boot output should look like the following:
>
> U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
>
> DRAM:  8 MiB
> In:serial@3800
> Out:   serial@3800
> Err:   serial@3800
> =>
>
> Changes for v8:
> - Removed dependency on the patch "clk: Add functions to register CCF 
> clock
>   structs". Hopefully this will make reviewing easier.

 I have applied this patch series to u-boot-riscv/master except [PATCH
 v8 14/21] riscv: Clean up IPI initialization code.
 Because it will cause some warnings as below:

 arch/riscv/lib/andes_plic.c: In function 'riscv_init_ipi':
 arch/riscv/lib/andes_plic.c:84:12: warning: initialization makes
 integer from pointer without a cast [-Wint-conversion]
   int ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
 ^~
 arch/riscv/lib/andes_plic.c:86:13: warning: passing argument 1 of
 'IS_ERR' makes pointer from integer without a cast [-Wint-conversion]
   if (IS_ERR(ret))
  ^~~
 In file included from arch/riscv/lib/andes_plic.c:20:0:
 include/linux/err.h:34:20: note: expected 'const void *' but argument
 is of type 'int'
  static inline long IS_ERR(const void *ptr)
 ^~
 arch/riscv/lib/andes_plic.c:87:18: warning: passing argument 1 of
 'PTR_ERR' makes pointer from integer without a cast [-Wint-conversion]
return PTR_ERR(ret);
   ^~~
 In file included from arch/riscv/lib/andes_plic.c:20:0:
 include/linux/err.h:29:20: note: expected 'const void *' but argument
 is of type 'int'
  static inline long PTR_ERR(const void *ptr)
 ^~~
 arch/riscv/lib/andes_plic.c:88:16: warning: assignment makes pointer
 from integer without a cast [-Wint-conversion]
   gd->arch.plic = ret;

>>>
>>> after running CI yesterday, it failed in many cases:
>>> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678023975
>>>
>>> and I trace at least two cases belong to your patch
>>> 49.59
>>> https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024035
>>>
>>> arning, treated as error:
>>> /home/travis/build/rickchen36/u-boot-riscv/doc/board/sipeed/maix.rst:173:Error
>>> in "code-block" directive:
>>> 1 argument(s) required, 0 supplied.
>>> .. code-block::
>>>  {
>>> assigned-clocks = < K210_CLK_PLL0>;
>>> assigned-clock-rates = <8>;
>>> };
>>> doc/Makefile:69: recipe for target 'htmldocs' failed
>>> make[1]: *** [htmldocs] Error 1
>>
>> I used to have
>>
>> .. code-block:: dts
>>
>> but it warned that "dts" was not a valid language, so I dropped it.
>>
>>> 49.66
>>> https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024042
>>>
>>> ./tools/patman/patman --test && ./tools/buildman/buildman -t &&
>>> ./tools/dtoc/dtoc -t && make testconfig; fi; fi
>>> cp: cannot create regular file
>>> '/home/travis/build/rickchen36/sandbox/': Not a directory
>>> cp: cannot create regular file
>>> '/home/travis/build/rickchen36/sandbox/': Not a directory
>>> WARNING: no status info for 'sipeed_maix_bitm'
>>> WARNING: no maintainers for 'sipeed_maix_bitm'
>>
>> I'm not sure what the issue here is. Which specific files are lacking a
>> MAINTAINERS entry?
>>
> 
> You need create a MAINTAINERS file in the board directory.

It is already created.

> 
>>>
>>> So I will drop your patchs and run CI again today.
>>> And hope you can fix them in next version and pass CI verification.
>>
> 
> Regards,
> Bin
> 

Re: [PATCH v8 00/21] riscv: Add Sipeed Maix support

[Bin Meng]

Hi Sean,

On Thu, Apr 23, 2020 at 10:03 AM Sean Anderson  wrote:
>
> On 4/22/20 9:51 PM, Rick Chen wrote:
> > Hi Sean
> >
> >> Hi Sean
> >>
> >>> This patch series adds support for Sipeed Maix boards and the Kendryte
> >>> K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
> >>> models are similar.
> >>>
> >>> Known Bugs/Limitations:
> >>> - Accessing the AI ram hangs, limiting available ram to 6M
> >>> - Trying to boot an image with bootm fails with
> >>>   ERROR: Failed to allocate 0x7d60 bytes below 0x8000.
> >>>
> >>> To flash u-boot to a maix bit, run
> >>> kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
> >>>
> >>> Boot output should look like the following:
> >>>
> >>> U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
> >>>
> >>> DRAM:  8 MiB
> >>> In:serial@3800
> >>> Out:   serial@3800
> >>> Err:   serial@3800
> >>> =>
> >>>
> >>> Changes for v8:
> >>> - Removed dependency on the patch "clk: Add functions to register CCF 
> >>> clock
> >>>   structs". Hopefully this will make reviewing easier.
> >>
> >> I have applied this patch series to u-boot-riscv/master except [PATCH
> >> v8 14/21] riscv: Clean up IPI initialization code.
> >> Because it will cause some warnings as below:
> >>
> >> arch/riscv/lib/andes_plic.c: In function 'riscv_init_ipi':
> >> arch/riscv/lib/andes_plic.c:84:12: warning: initialization makes
> >> integer from pointer without a cast [-Wint-conversion]
> >>   int ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
> >> ^~
> >> arch/riscv/lib/andes_plic.c:86:13: warning: passing argument 1 of
> >> 'IS_ERR' makes pointer from integer without a cast [-Wint-conversion]
> >>   if (IS_ERR(ret))
> >>  ^~~
> >> In file included from arch/riscv/lib/andes_plic.c:20:0:
> >> include/linux/err.h:34:20: note: expected 'const void *' but argument
> >> is of type 'int'
> >>  static inline long IS_ERR(const void *ptr)
> >> ^~
> >> arch/riscv/lib/andes_plic.c:87:18: warning: passing argument 1 of
> >> 'PTR_ERR' makes pointer from integer without a cast [-Wint-conversion]
> >>return PTR_ERR(ret);
> >>   ^~~
> >> In file included from arch/riscv/lib/andes_plic.c:20:0:
> >> include/linux/err.h:29:20: note: expected 'const void *' but argument
> >> is of type 'int'
> >>  static inline long PTR_ERR(const void *ptr)
> >> ^~~
> >> arch/riscv/lib/andes_plic.c:88:16: warning: assignment makes pointer
> >> from integer without a cast [-Wint-conversion]
> >>   gd->arch.plic = ret;
> >>
> >
> > after running CI yesterday, it failed in many cases:
> > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678023975
> >
> > and I trace at least two cases belong to your patch
> > 49.59
> > https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024035
> >
> > arning, treated as error:
> > /home/travis/build/rickchen36/u-boot-riscv/doc/board/sipeed/maix.rst:173:Error
> > in "code-block" directive:
> > 1 argument(s) required, 0 supplied.
> > .. code-block::
> >  {
> > assigned-clocks = < K210_CLK_PLL0>;
> > assigned-clock-rates = <8>;
> > };
> > doc/Makefile:69: recipe for target 'htmldocs' failed
> > make[1]: *** [htmldocs] Error 1
>
> I used to have
>
> .. code-block:: dts
>
> but it warned that "dts" was not a valid language, so I dropped it.
>
> > 49.66
> > https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024042
> >
> > ./tools/patman/patman --test && ./tools/buildman/buildman -t &&
> > ./tools/dtoc/dtoc -t && make testconfig; fi; fi
> > cp: cannot create regular file
> > '/home/travis/build/rickchen36/sandbox/': Not a directory
> > cp: cannot create regular file
> > '/home/travis/build/rickchen36/sandbox/': Not a directory
> > WARNING: no status info for 'sipeed_maix_bitm'
> > WARNING: no maintainers for 'sipeed_maix_bitm'
>
> I'm not sure what the issue here is. Which specific files are lacking a
> MAINTAINERS entry?
>

You need create a MAINTAINERS file in the board directory.

> >
> > So I will drop your patchs and run CI again today.
> > And hope you can fix them in next version and pass CI verification.
>

Regards,
Bin

Re: [PATCH v8 00/21] riscv: Add Sipeed Maix support

[Sean Anderson]

On 4/22/20 9:51 PM, Rick Chen wrote:
> Hi Sean
> 
>> Hi Sean
>>
>>> This patch series adds support for Sipeed Maix boards and the Kendryte
>>> K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
>>> models are similar.
>>>
>>> Known Bugs/Limitations:
>>> - Accessing the AI ram hangs, limiting available ram to 6M
>>> - Trying to boot an image with bootm fails with
>>>   ERROR: Failed to allocate 0x7d60 bytes below 0x8000.
>>>
>>> To flash u-boot to a maix bit, run
>>> kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
>>>
>>> Boot output should look like the following:
>>>
>>> U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
>>>
>>> DRAM:  8 MiB
>>> In:serial@3800
>>> Out:   serial@3800
>>> Err:   serial@3800
>>> =>
>>>
>>> Changes for v8:
>>> - Removed dependency on the patch "clk: Add functions to register CCF clock
>>>   structs". Hopefully this will make reviewing easier.
>>
>> I have applied this patch series to u-boot-riscv/master except [PATCH
>> v8 14/21] riscv: Clean up IPI initialization code.
>> Because it will cause some warnings as below:
>>
>> arch/riscv/lib/andes_plic.c: In function 'riscv_init_ipi':
>> arch/riscv/lib/andes_plic.c:84:12: warning: initialization makes
>> integer from pointer without a cast [-Wint-conversion]
>>   int ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
>> ^~
>> arch/riscv/lib/andes_plic.c:86:13: warning: passing argument 1 of
>> 'IS_ERR' makes pointer from integer without a cast [-Wint-conversion]
>>   if (IS_ERR(ret))
>>  ^~~
>> In file included from arch/riscv/lib/andes_plic.c:20:0:
>> include/linux/err.h:34:20: note: expected 'const void *' but argument
>> is of type 'int'
>>  static inline long IS_ERR(const void *ptr)
>> ^~
>> arch/riscv/lib/andes_plic.c:87:18: warning: passing argument 1 of
>> 'PTR_ERR' makes pointer from integer without a cast [-Wint-conversion]
>>return PTR_ERR(ret);
>>   ^~~
>> In file included from arch/riscv/lib/andes_plic.c:20:0:
>> include/linux/err.h:29:20: note: expected 'const void *' but argument
>> is of type 'int'
>>  static inline long PTR_ERR(const void *ptr)
>> ^~~
>> arch/riscv/lib/andes_plic.c:88:16: warning: assignment makes pointer
>> from integer without a cast [-Wint-conversion]
>>   gd->arch.plic = ret;
>>
> 
> after running CI yesterday, it failed in many cases:
> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678023975
> 
> and I trace at least two cases belong to your patch
> 49.59
> https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024035
> 
> arning, treated as error:
> /home/travis/build/rickchen36/u-boot-riscv/doc/board/sipeed/maix.rst:173:Error
> in "code-block" directive:
> 1 argument(s) required, 0 supplied.
> .. code-block::
>  {
> assigned-clocks = < K210_CLK_PLL0>;
> assigned-clock-rates = <8>;
> };
> doc/Makefile:69: recipe for target 'htmldocs' failed
> make[1]: *** [htmldocs] Error 1

I used to have

.. code-block:: dts

but it warned that "dts" was not a valid language, so I dropped it.

> 49.66
> https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024042
> 
> ./tools/patman/patman --test && ./tools/buildman/buildman -t &&
> ./tools/dtoc/dtoc -t && make testconfig; fi; fi
> cp: cannot create regular file
> '/home/travis/build/rickchen36/sandbox/': Not a directory
> cp: cannot create regular file
> '/home/travis/build/rickchen36/sandbox/': Not a directory
> WARNING: no status info for 'sipeed_maix_bitm'
> WARNING: no maintainers for 'sipeed_maix_bitm'

I'm not sure what the issue here is. Which specific files are lacking a
MAINTAINERS entry?

> 
> So I will drop your patchs and run CI again today.
> And hope you can fix them in next version and pass CI verification.



> 
> Thanks,
> Rick
> 

These "errors" seem rather minor. I will fix the PLIC ones in the next
revision, but I don't think the sort found in this email are
particularly erroneous.

--Sean

Re: [PATCH v8 00/21] riscv: Add Sipeed Maix support

[Sean Anderson]

On 4/22/20 9:51 PM, Rick Chen wrote:
> Hi Sean
> 
>> Hi Sean
>>
>>> This patch series adds support for Sipeed Maix boards and the Kendryte
>>> K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
>>> models are similar.
>>>
>>> Known Bugs/Limitations:
>>> - Accessing the AI ram hangs, limiting available ram to 6M
>>> - Trying to boot an image with bootm fails with
>>>   ERROR: Failed to allocate 0x7d60 bytes below 0x8000.
>>>
>>> To flash u-boot to a maix bit, run
>>> kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
>>>
>>> Boot output should look like the following:
>>>
>>> U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
>>>
>>> DRAM:  8 MiB
>>> In:serial@3800
>>> Out:   serial@3800
>>> Err:   serial@3800
>>> =>
>>>
>>> Changes for v8:
>>> - Removed dependency on the patch "clk: Add functions to register CCF clock
>>>   structs". Hopefully this will make reviewing easier.
>>
>> I have applied this patch series to u-boot-riscv/master except [PATCH
>> v8 14/21] riscv: Clean up IPI initialization code.
>> Because it will cause some warnings as below:
>>
>> arch/riscv/lib/andes_plic.c: In function 'riscv_init_ipi':
>> arch/riscv/lib/andes_plic.c:84:12: warning: initialization makes
>> integer from pointer without a cast [-Wint-conversion]
>>   int ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
>> ^~
>> arch/riscv/lib/andes_plic.c:86:13: warning: passing argument 1 of
>> 'IS_ERR' makes pointer from integer without a cast [-Wint-conversion]
>>   if (IS_ERR(ret))
>>  ^~~
>> In file included from arch/riscv/lib/andes_plic.c:20:0:
>> include/linux/err.h:34:20: note: expected 'const void *' but argument
>> is of type 'int'
>>  static inline long IS_ERR(const void *ptr)
>> ^~
>> arch/riscv/lib/andes_plic.c:87:18: warning: passing argument 1 of
>> 'PTR_ERR' makes pointer from integer without a cast [-Wint-conversion]
>>return PTR_ERR(ret);
>>   ^~~
>> In file included from arch/riscv/lib/andes_plic.c:20:0:
>> include/linux/err.h:29:20: note: expected 'const void *' but argument
>> is of type 'int'
>>  static inline long PTR_ERR(const void *ptr)
>> ^~~
>> arch/riscv/lib/andes_plic.c:88:16: warning: assignment makes pointer
>> from integer without a cast [-Wint-conversion]
>>   gd->arch.plic = ret;
>>
> 
> after running CI yesterday, it failed in many cases:
> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678023975
> 
> and I trace at least two cases belong to your patch
> 49.59
> https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024035
> 
> arning, treated as error:
> /home/travis/build/rickchen36/u-boot-riscv/doc/board/sipeed/maix.rst:173:Error
> in "code-block" directive:
> 1 argument(s) required, 0 supplied.
> .. code-block::
>  {
> assigned-clocks = < K210_CLK_PLL0>;
> assigned-clock-rates = <8>;
> };
> doc/Makefile:69: recipe for target 'htmldocs' failed
> make[1]: *** [htmldocs] Error 1

I used to have

.. code-block:: dts

but it warned that "dts" was not a valid language, so I dropped it.

> 49.66
> https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024042
> 
> ./tools/patman/patman --test && ./tools/buildman/buildman -t &&
> ./tools/dtoc/dtoc -t && make testconfig; fi; fi
> cp: cannot create regular file
> '/home/travis/build/rickchen36/sandbox/': Not a directory
> cp: cannot create regular file
> '/home/travis/build/rickchen36/sandbox/': Not a directory
> WARNING: no status info for 'sipeed_maix_bitm'
> WARNING: no maintainers for 'sipeed_maix_bitm'

I'm not sure what the issue here is. Which specific files are lacking a
MAINTAINERS entry?

> 
> So I will drop your patchs and run CI again today.
> And hope you can fix them in next version and pass CI verification.



> 
> Thanks,
> Rick
> 

These "errors" seem rather minor. I will fix the PLIC ones in the next
revision, but I don't think the sort found in this email are
particularly erroneous.

--Sean

Re: [PATCH v8 00/21] riscv: Add Sipeed Maix support

[Rick Chen]

Hi Sean

> Hi Sean
>
> > This patch series adds support for Sipeed Maix boards and the Kendryte
> > K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
> > models are similar.
> >
> > Known Bugs/Limitations:
> > - Accessing the AI ram hangs, limiting available ram to 6M
> > - Trying to boot an image with bootm fails with
> >   ERROR: Failed to allocate 0x7d60 bytes below 0x8000.
> >
> > To flash u-boot to a maix bit, run
> > kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
> >
> > Boot output should look like the following:
> >
> > U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
> >
> > DRAM:  8 MiB
> > In:serial@3800
> > Out:   serial@3800
> > Err:   serial@3800
> > =>
> >
> > Changes for v8:
> > - Removed dependency on the patch "clk: Add functions to register CCF clock
> >   structs". Hopefully this will make reviewing easier.
>
> I have applied this patch series to u-boot-riscv/master except [PATCH
> v8 14/21] riscv: Clean up IPI initialization code.
> Because it will cause some warnings as below:
>
> arch/riscv/lib/andes_plic.c: In function 'riscv_init_ipi':
> arch/riscv/lib/andes_plic.c:84:12: warning: initialization makes
> integer from pointer without a cast [-Wint-conversion]
>   int ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
> ^~
> arch/riscv/lib/andes_plic.c:86:13: warning: passing argument 1 of
> 'IS_ERR' makes pointer from integer without a cast [-Wint-conversion]
>   if (IS_ERR(ret))
>  ^~~
> In file included from arch/riscv/lib/andes_plic.c:20:0:
> include/linux/err.h:34:20: note: expected 'const void *' but argument
> is of type 'int'
>  static inline long IS_ERR(const void *ptr)
> ^~
> arch/riscv/lib/andes_plic.c:87:18: warning: passing argument 1 of
> 'PTR_ERR' makes pointer from integer without a cast [-Wint-conversion]
>return PTR_ERR(ret);
>   ^~~
> In file included from arch/riscv/lib/andes_plic.c:20:0:
> include/linux/err.h:29:20: note: expected 'const void *' but argument
> is of type 'int'
>  static inline long PTR_ERR(const void *ptr)
> ^~~
> arch/riscv/lib/andes_plic.c:88:16: warning: assignment makes pointer
> from integer without a cast [-Wint-conversion]
>   gd->arch.plic = ret;
>

after running CI yesterday, it failed in many cases:
https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678023975

and I trace at least two cases belong to your patch
49.59
https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024035

arning, treated as error:
/home/travis/build/rickchen36/u-boot-riscv/doc/board/sipeed/maix.rst:173:Error
in "code-block" directive:
1 argument(s) required, 0 supplied.
.. code-block::
 {
assigned-clocks = < K210_CLK_PLL0>;
assigned-clock-rates = <8>;
};
doc/Makefile:69: recipe for target 'htmldocs' failed
make[1]: *** [htmldocs] Error 1

49.66
https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/678024042

./tools/patman/patman --test && ./tools/buildman/buildman -t &&
./tools/dtoc/dtoc -t && make testconfig; fi; fi
cp: cannot create regular file
'/home/travis/build/rickchen36/sandbox/': Not a directory
cp: cannot create regular file
'/home/travis/build/rickchen36/sandbox/': Not a directory
WARNING: no status info for 'sipeed_maix_bitm'
WARNING: no maintainers for 'sipeed_maix_bitm'

So I will drop your patchs and run CI again today.
And hope you can fix them in next version and pass CI verification.

Thanks,
Rick

RE: Please pull NXP i.MX nxp-imx-20200422

[Peng Fan]

> Subject: Re: Please pull NXP i.MX nxp-imx-20200422
> 
> Hi Peng,
> 
> On Wed, Apr 22, 2020 at 10:54 AM Peng Fan  wrote:
> >
> > Hi Stefano,
> >
> > Please pull this version nxp-imx-20200422, with patches sent out to ML.
> > Based on yours master branch.
> 
> These 24 patches have just been posted to the list.
> 
> Please allow time for people to review it and only send the pull request after
> review has been done

Code in downstream tree has been reviewed. Ok, let's wait and see comments
from community.

Thanks,
Peng.

RE: [PATCH 07/24] imx: update is_imx6ull to include i.MX6ULZ

[Peng Fan]

> Subject: Re: [PATCH 07/24] imx: update is_imx6ull to include i.MX6ULZ
> 
> Am Mittwoch, 22. April 2020, 15:52:18 CEST schrieb Peng Fan:
> > Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could share
> > same macro, then we no need to add is_imx6ulz in various drivers.
> >
> > Signed-off-by: Peng Fan 
> > ---
> >  arch/arm/include/asm/mach-imx/sys_proto.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
> > b/arch/arm/include/asm/mach-imx/sys_proto.h
> > index a02cd40c7d..2a997f280d 100644
> > --- a/arch/arm/include/asm/mach-imx/sys_proto.h
> > +++ b/arch/arm/include/asm/mach-imx/sys_proto.h
> > @@ -37,7 +37,7 @@
> >  #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))  #define
> is_mx6solo()
> > (is_cpu_type(MXC_CPU_MX6SOLO))  #define is_mx6ul()
> > (is_cpu_type(MXC_CPU_MX6UL)) -#define is_mx6ull()
> > (is_cpu_type(MXC_CPU_MX6ULL))
> > +#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) ||
> > +is_cpu_type(MXC_CPU_MX6ULZ))
> 
> While I probably understand your intentions, I fear that it will lead to
> confusion when the helper's name does not reflect that more than one cpu
> type can match.
> What about introducing is_mx6ulX() to signal that the last letter is "don't
> care"?

Renaming the macro needs to modify drivers using this macro, this is risk
to easy break existing code.
I prefer to keep as is.

Thanks,
Peng.

> 
> Best regards,
> Michael
> 
> >  #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))  #define
> > is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
> >
> >
> 
> 
> 

[PATCH] configs: ls1021a: Append CMA configuration to bootargs

[Alison Wang]

According to commit , this patch appends CMA configuration
to bootargs for LS1021ATWR.

Signed-off-by: Shengzhou Liu 
Signed-off-by: Alison Wang 
---
 include/configs/ls1021atwr.h | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a6289850ca..45ce460dca 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -297,7 +297,8 @@
 
 #ifdef CONFIG_LPUART
 #define CONFIG_EXTRA_ENV_SETTINGS   \
-   "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 $othbootargs\0" \
+   "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
+   "cma=64M@0x0-0xb000\0" \
"initrd_high=0x\0"  \
"fdt_addr=0x64f0\0" \
"kernel_addr=0x6500\0"  \
@@ -353,7 +354,8 @@
"$kernel_size && bootm $load_addr#$board\0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS  \
-   "bootargs=root=/dev/ram0 rw console=ttyS0,115200 $othbootargs\0" \
+   "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "  \
+   "cma=64M@0x0-0xb000\0" \
"initrd_high=0x\0"  \
"fdt_addr=0x64f0\0" \
"kernel_addr=0x6100\0"  \
-- 
2.17.1

Re: [PATCH] lib/crypto, efi_loader: move some headers to include/crypto

[AKASHI Takahiro]

Heinrich,

On Tue, Apr 21, 2020 at 12:26:08PM +0200, Heinrich Schuchardt wrote:
> On 4/21/20 2:38 AM, AKASHI Takahiro wrote:
> > Pkcs7_parse.h and x509_parser.h are used in UEFI subsystem, in particular,
> > secure boot. So move them to include/crypto to avoid relative paths.
> >
> > Signed-off-by: AKASHI Takahiro 
> > Suggested-by: Heinrich Schuchardt 
> > ---
> >  {lib => include}/crypto/pkcs7_parser.h | 0
> >  {lib => include}/crypto/x509_parser.h  | 0
> >  lib/crypto/pkcs7_parser.c  | 4 
> >  lib/crypto/x509_cert_parser.c  | 4 
> >  lib/crypto/x509_public_key.c   | 6 --
> >  lib/efi_loader/efi_image_loader.c  | 4 ++--
> >  lib/efi_loader/efi_signature.c | 4 ++--
> >  lib/efi_loader/efi_variable.c  | 2 +-
> >  test/lib/asn1.c| 4 ++--
> >  9 files changed, 19 insertions(+), 9 deletions(-)
> >  rename {lib => include}/crypto/pkcs7_parser.h (100%)
> >  rename {lib => include}/crypto/x509_parser.h (100%)
> >
> > diff --git a/lib/crypto/pkcs7_parser.h b/include/crypto/pkcs7_parser.h
> > similarity index 100%
> > rename from lib/crypto/pkcs7_parser.h
> > rename to include/crypto/pkcs7_parser.h
> > diff --git a/lib/crypto/x509_parser.h b/include/crypto/x509_parser.h
> > similarity index 100%
> > rename from lib/crypto/x509_parser.h
> > rename to include/crypto/x509_parser.h
> > diff --git a/lib/crypto/pkcs7_parser.c b/lib/crypto/pkcs7_parser.c
> > index f5dda1179f8a..0ee207b6b1c8 100644
> > --- a/lib/crypto/pkcs7_parser.c
> > +++ b/lib/crypto/pkcs7_parser.c
> > @@ -20,7 +20,11 @@
> >  #include 
> >  #include 
> >  #include 
> > +#ifdef __UBOOT__
> > +#include 
> > +#else
> >  #include "pkcs7_parser.h"
> > +#endif
> >  #include "pkcs7.asn1.h"
> >
> >  MODULE_DESCRIPTION("PKCS#7 parser");
> > diff --git a/lib/crypto/x509_cert_parser.c b/lib/crypto/x509_cert_parser.c
> > index 4e41cffd2301..18f5407a076c 100644
> > --- a/lib/crypto/x509_cert_parser.c
> > +++ b/lib/crypto/x509_cert_parser.c
> > @@ -18,7 +18,11 @@
> >  #include 
> >  #endif
> >  #include 
> > +#ifdef __UBOOT__
> > +#include 
> > +#else
> >  #include "x509_parser.h"
> > +#endif
> >  #include "x509.asn1.h"
> >  #include "x509_akid.asn1.h"
> >
> > diff --git a/lib/crypto/x509_public_key.c b/lib/crypto/x509_public_key.c
> > index 676c0df17410..571af9a0adf9 100644
> > --- a/lib/crypto/x509_public_key.c
> > +++ b/lib/crypto/x509_public_key.c
> > @@ -16,15 +16,17 @@
> >  #include 
> >  #endif
> >  #include 
> > -#ifndef __UBOOT__
> > +#ifdef __UBOOT__
> > +#include 
> > +#else
> >  #include 
> >  #include 
> >  #include 
> >  #include 
> >  #include 
> >  #include "asymmetric_keys.h"
> > -#endif
> >  #include "x509_parser.h"
> > +#endif
> >
> >  /*
> >   * Set up the signature parameters in an X.509 certificate.  This involves
> > diff --git a/lib/efi_loader/efi_image_loader.c 
> > b/lib/efi_loader/efi_image_loader.c
> > index 899adf8493d0..f59b9a01140e 100644
> > --- a/lib/efi_loader/efi_image_loader.c
> > +++ b/lib/efi_loader/efi_image_loader.c
> > @@ -13,8 +13,8 @@
> >  #include 
> >  #include 
> >  #include 
> > -#include "../lib/crypto/pkcs7_parser.h"
> > -#include "../lib/crypto/x509_parser.h"
> > +#include "crypto/pkcs7_parser.h"
> > +#include "crypto/x509_parser.h"
> 
> Thanks for fixing this.
> 
> x509_parser.h is included in pkcs7_parser.h. Please, remove the
> superfluous line.

See my comment in [1]

[1] https://lists.denx.de/pipermail/u-boot/2020-April/408160.html

-Takahiro Akashi


> >
> >  const efi_guid_t efi_global_variable_guid = EFI_GLOBAL_VARIABLE_GUID;
> >  const efi_guid_t efi_guid_device_path = EFI_DEVICE_PATH_PROTOCOL_GUID;
> > diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c
> > index 6ad09e4acbd7..0ead10203aeb 100644
> > --- a/lib/efi_loader/efi_signature.c
> > +++ b/lib/efi_loader/efi_signature.c
> > @@ -10,12 +10,12 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> 
> Same here.
> 
> Best regards
> 
> Heinrich
> 
> >  #include 
> >  #include 
> >  #include 
> >  #include 
> > -#include "../lib/crypto/pkcs7_parser.h"
> > -#include "../lib/crypto/x509_parser.h"
> >
> >  const efi_guid_t efi_guid_image_security_database =
> > EFI_IMAGE_SECURITY_DATABASE_GUID;
> > diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> > index 7df881a74b44..0c6d1deb58eb 100644
> > --- a/lib/efi_loader/efi_variable.c
> > +++ b/lib/efi_loader/efi_variable.c
> > @@ -12,9 +12,9 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> > -#include "../lib/crypto/pkcs7_parser.h"
> >
> >  enum efi_secure_mode {
> > EFI_MODE_SETUP,
> > diff --git a/test/lib/asn1.c b/test/lib/asn1.c
> > index d2b3f67e68da..8661fdd30687 100644
> > --- a/test/lib/asn1.c
> > +++ b/test/lib/asn1.c
> > @@ -13,10 +13,10 @@
> >  #include 
> >
> >  #ifdef CONFIG_PKCS7_MESSAGE_PARSER
> > -#include "../../lib/crypto/pkcs7_parser.h"
> > +#include 
> >  #else
> >  #ifdef 

Re: [PATCH] lib/crypto, efi_loader: avoid multiple inclusions of header files

[AKASHI Takahiro]

Heinrich,

On Tue, Apr 21, 2020 at 12:23:13PM +0200, Heinrich Schuchardt wrote:
> On 4/21/20 2:37 AM, AKASHI Takahiro wrote:
> > By adding extra symbols, we can now avoid including x509_parser and
> > pkcs7_parser.h files multiple times.
> >
> > Signed-off-by: AKASHI Takahiro 
> > Suggested-by: Heinrich Schuchardt 
> > ---
> >  lib/crypto/pkcs7_parser.h | 4 
> >  lib/crypto/x509_parser.h  | 4 
> >  lib/efi_loader/efi_image_loader.c | 1 +
> >  lib/efi_loader/efi_signature.c| 1 +
> >  4 files changed, 10 insertions(+)
> >
> > diff --git a/lib/crypto/pkcs7_parser.h b/lib/crypto/pkcs7_parser.h
> > index 6565fdc2d4ca..b8234da45a6a 100644
> > --- a/lib/crypto/pkcs7_parser.h
> > +++ b/lib/crypto/pkcs7_parser.h
> > @@ -5,6 +5,9 @@
> >   * Written by David Howells (dhowe...@redhat.com)
> >   */
> >
> > +#ifndef _PKCS7_PARSER_H
> > +#define _PKCS7_PARSER_H
> > +
> >  #include 
> >  #include 
> >  #include "x509_parser.h"
> > @@ -63,3 +66,4 @@ struct pkcs7_message {
> > size_t  data_hdrlen;/* Length of Data ASN.1 header */
> > const void  *data;  /* Content Data (or 0) */
> >  };
> > +#endif /* _PKCS7_PARSER_H */
> > diff --git a/lib/crypto/x509_parser.h b/lib/crypto/x509_parser.h
> > index c233f136fb35..4cbdc1d6612d 100644
> > --- a/lib/crypto/x509_parser.h
> > +++ b/lib/crypto/x509_parser.h
> > @@ -5,6 +5,9 @@
> >   * Written by David Howells (dhowe...@redhat.com)
> >   */
> >
> > +#ifndef _X509_PARSER_H
> > +#define _X509_PARSER_H
> > +
> >  #include 
> >  #include 
> >  #include 
> > @@ -55,3 +58,4 @@ extern int x509_decode_time(time64_t *_t,  size_t hdrlen,
> >   */
> >  extern int x509_get_sig_params(struct x509_certificate *cert);
> >  extern int x509_check_for_self_signed(struct x509_certificate *cert);
> > +#endif /* _X509_PARSER_H */
> > diff --git a/lib/efi_loader/efi_image_loader.c 
> > b/lib/efi_loader/efi_image_loader.c
> > index 6c270ce94f44..899adf8493d0 100644
> > --- a/lib/efi_loader/efi_image_loader.c
> > +++ b/lib/efi_loader/efi_image_loader.c
> > @@ -14,6 +14,7 @@
> >  #include 
> >  #include 
> >  #include "../lib/crypto/pkcs7_parser.h"
> > +#include "../lib/crypto/x509_parser.h"
> 
> As pkcs7_parser.h includes x509_parser.h there is no reason to include
> it again.

No, I don't think so.

My style of coding is that, if a symbol is used in a C file and it is
defined in a header file, the header file should be *directly* included
in the C file.
I believe that it is the common way so that we can avoid any "implicit"
dependencies among header files.

Thanks,
-Takahiro Akashi


> >
> >  const efi_guid_t efi_global_variable_guid = EFI_GLOBAL_VARIABLE_GUID;
> >  const efi_guid_t efi_guid_device_path = EFI_DEVICE_PATH_PROTOCOL_GUID;
> > diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c
> > index 658e3547da37..6ad09e4acbd7 100644
> > --- a/lib/efi_loader/efi_signature.c
> > +++ b/lib/efi_loader/efi_signature.c
> > @@ -15,6 +15,7 @@
> >  #include 
> >  #include 
> >  #include "../lib/crypto/pkcs7_parser.h"
> > +#include "../lib/crypto/x509_parser.h"
> 
> Same here.
> 
> The rest is correct and should be merged.
> 
> Best regards
> 
> Heinrich
> 
> >
> >  const efi_guid_t efi_guid_image_security_database =
> > EFI_IMAGE_SECURITY_DATABASE_GUID;
> >
> 

Re: [PATCH v3 2/2] efi_loader: identify EFI system partition

[AKASHI Takahiro]

Heinrich,

On Wed, Apr 22, 2020 at 07:51:33PM +0200, Heinrich Schuchardt wrote:
> In subsequent patches UEFI variables shalled be stored on the EFI system
> partition. Hence we need to identify the EFI system partition.
> 
> Signed-off-by: Heinrich Schuchardt 
> ---
> v3:
>   adjust commit message


I said 'no' along with my counter proposals[1], and you haven't
replied yet.

[1] https://lists.denx.de/pipermail/u-boot/2020-April/406678.html

-Takahiro Akashi

> v2:
>   no change
> ---
>  include/efi_loader.h  |  7 +++
>  lib/efi_loader/efi_disk.c | 20 
>  2 files changed, 27 insertions(+)
> 
> diff --git a/include/efi_loader.h b/include/efi_loader.h
> index 0ba9a1f702..b7bccf50b3 100644
> --- a/include/efi_loader.h
> +++ b/include/efi_loader.h
> @@ -47,6 +47,13 @@ static inline void *guidcpy(void *dst, const void *src)
>  /* Root node */
>  extern efi_handle_t efi_root;
> 
> +/* EFI system partition */
> +extern struct efi_system_partition {
> + enum if_type if_type;
> + int devnum;
> + u8 part;
> +} efi_system_partition;
> +
>  int __efi_entry_check(void);
>  int __efi_exit_check(void);
>  const char *__efi_nesting(void);
> diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
> index fd8fe17567..fd3df80b0b 100644
> --- a/lib/efi_loader/efi_disk.c
> +++ b/lib/efi_loader/efi_disk.c
> @@ -13,6 +13,8 @@
>  #include 
>  #include 
> 
> +struct efi_system_partition efi_system_partition;
> +
>  const efi_guid_t efi_block_io_guid = EFI_BLOCK_IO_PROTOCOL_GUID;
> 
>  /**
> @@ -418,6 +420,24 @@ static efi_status_t efi_disk_add_dev(
>   diskobj->ops.media = >media;
>   if (disk)
>   *disk = diskobj;
> +
> + /* Store first EFI system partition */
> + if (part && !efi_system_partition.if_type) {
> + int r;
> + disk_partition_t info;
> +
> + r = part_get_info(desc, part, );
> + if (r)
> + return EFI_DEVICE_ERROR;
> + if (info.bootable & PART_EFI_SYSTEM_PARTITION) {
> + efi_system_partition.if_type = desc->if_type;
> + efi_system_partition.devnum = desc->devnum;
> + efi_system_partition.part = part;
> + EFI_PRINT("EFI system partition: %s %d:%d\n",
> +   blk_get_if_type_name(desc->if_type),
> +   desc->devnum, part);
> + }
> + }
>   return EFI_SUCCESS;
>  }
> 
> --
> 2.26.1
> 

Re: [PATCH 2/2] test/py: fix test_efi_secboot/conftest.py

[AKASHI Takahiro]

Heinrich,

On Wed, Apr 22, 2020 at 05:52:55PM +0200, Heinrich Schuchardt wrote:
> If udisksctl is present
> test/py/tests/test_efi_secboot/conftest.py
> fails because the disk image is never mounted.
> 
> Normal users can only mount fuse file systems. Unfortunately fusefat is
> still in an experimental state and seems not to work here correctly.

I haven't confirmed that fuse/fat is not stable, but

> So as we have to be root or use the sudo command anyway delete all coding
> referring to udisksctl.

I don't mind non-root path being deleted as it was used when Travis CI
didn't work with "sudo".

> --
> 
> We should not use mount point /mnt as this directory or one of its
> sub-directories might already be in use as active mount points. Instead
> create a new directory in the build root as mount point.
> 
> --
> 
> Remove debug print statements that have been commented out. print without
> parentheses is anyway invalid in Python 3. And pytest anyway filters out
> the output if there is no exception reported.

'printing a mount point' was mostly useful for debugging
non-root path.

> Signed-off-by: Heinrich Schuchardt 
> ---
>  test/py/tests/test_efi_secboot/conftest.py | 30 +-
>  1 file changed, 6 insertions(+), 24 deletions(-)
> 
> diff --git a/test/py/tests/test_efi_secboot/conftest.py 
> b/test/py/tests/test_efi_secboot/conftest.py
> index 40cdf15bf2..93d308cf0d 100644
> --- a/test/py/tests/test_efi_secboot/conftest.py
> +++ b/test/py/tests/test_efi_secboot/conftest.py
> @@ -43,7 +43,8 @@ def efi_boot_env(request, u_boot_config):
>  HELLO_PATH = u_boot_config.build_dir + 
> '/lib/efi_loader/helloworld.efi'
> 
>  try:
> -non_root = tool_is_in_path('udisksctl')
> +mnt_point = u_boot_config.persistent_data_dir + '/mnt_efisecure'
> +check_call('mkdir -p {}'.format(mnt_point), shell=True)

For consistency, it would be better to use "%" formatting as elsewhere
in the file.

Thanks,
-Takahiro Akashi

> 
>  # create a disk/partition
>  check_call('dd if=/dev/zero of=%s bs=1MiB count=%d'
> @@ -57,25 +58,11 @@ def efi_boot_env(request, u_boot_config):
>  check_call('dd if=%s.tmp of=%s bs=1MiB seek=1 count=%d conv=notrunc'
>  % (image_path, image_path, 1), shell=True)
>  check_call('rm %s.tmp' % image_path, shell=True)
> -if non_root:
> -out_data = check_output('udisksctl loop-setup -f %s -o %d'
> -% (image_path, 1048576), shell=True).decode()
> -m = re.search('(?<= as )(.*)\.', out_data)
> -loop_dev = m.group(1)
> -# print 'loop device is: %s' % loop_dev
> -out_data = check_output('udisksctl info -b %s'
> -% loop_dev, shell=True).decode()
> -m = re.search('MountPoints:[ \t]+(.*)', out_data)
> -mnt_point = m.group(1)
> -else:
> -loop_dev = check_output('sudo losetup -o 1MiB --sizelimit %dMiB 
> --show -f %s | tr -d "\n"'
> +loop_dev = check_output('sudo losetup -o 1MiB --sizelimit %dMiB 
> --show -f %s | tr -d "\n"'
>  % (part_size, image_path), 
> shell=True).decode()
> -mnt_point = '/mnt'
> -check_output('sudo mount -t %s -o umask=000 %s %s'
> +check_output('sudo mount -t %s -o umask=000 %s %s'
>  % (fs_type, loop_dev, mnt_point), shell=True)
> 
> -# print 'mount point is: %s' % mnt_point
> -
>  # suffix
>  # *.key: RSA private key in PEM
>  # *.crt: X509 certificate (self-signed) in PEM
> @@ -134,13 +121,8 @@ def efi_boot_env(request, u_boot_config):
>  % (mnt_point, EFITOOLS_PATH, EFITOOLS_PATH),
>  shell=True)
> 
> -if non_root:
> -check_call('udisksctl unmount -b %s' % loop_dev, shell=True)
> -# not needed
> -# check_call('udisksctl loop-delete -b %s' % loop_dev, 
> shell=True)
> -else:
> -check_call('sudo umount %s' % loop_dev, shell=True)
> -check_call('sudo losetup -d %s' % loop_dev, shell=True)
> +check_call('sudo umount %s' % loop_dev, shell=True)
> +check_call('sudo losetup -d %s' % loop_dev, shell=True)
> 
>  except CalledProcessError as e:
>  pytest.skip('Setup failed: %s' % e.cmd)
> --
> 2.26.1
> 

Re: [PATCH 1/2] test/py: efi_secboot should not assume sbin is in the path

[AKASHI Takahiro]

Heinrich,

On Wed, Apr 22, 2020 at 05:52:54PM +0200, Heinrich Schuchardt wrote:
> For non-root users /sbin is typically not in the path. So use absolute
> paths to mkfs.vfat and sgdisk.

As Stephen pointed out somewhere else else before, you should
set $PATH properly instead of using an absolute path directly.

Thanks,
-Takahiro Akashi



> Signed-off-by: Heinrich Schuchardt 
> ---
>  test/py/tests/test_efi_secboot/conftest.py | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/test/py/tests/test_efi_secboot/conftest.py 
> b/test/py/tests/test_efi_secboot/conftest.py
> index e542fef6e8..40cdf15bf2 100644
> --- a/test/py/tests/test_efi_secboot/conftest.py
> +++ b/test/py/tests/test_efi_secboot/conftest.py
> @@ -48,12 +48,12 @@ def efi_boot_env(request, u_boot_config):
>  # create a disk/partition
>  check_call('dd if=/dev/zero of=%s bs=1MiB count=%d'
>  % (image_path, image_size), shell=True)
> -check_call('sgdisk %s -n 1:0:+%dMiB'
> +check_call('/sbin/sgdisk %s -n 1:0:+%dMiB'
>  % (image_path, part_size), shell=True)
>  # create a file system
>  check_call('dd if=/dev/zero of=%s.tmp bs=1MiB count=%d'
>  % (image_path, part_size), shell=True)
> -check_call('mkfs -t %s %s.tmp' % (fs_type, image_path), shell=True)
> +check_call('/sbin/mkfs.%s %s.tmp' % (fs_type, image_path), 
> shell=True)
>  check_call('dd if=%s.tmp of=%s bs=1MiB seek=1 count=%d conv=notrunc'
>  % (image_path, image_path, 1), shell=True)
>  check_call('rm %s.tmp' % image_path, shell=True)
> --
> 2.26.1
> 

Re: [PATCH 07/24] imx: update is_imx6ull to include i.MX6ULZ

[Michael Heimpold]

Am Mittwoch, 22. April 2020, 15:52:18 CEST schrieb Peng Fan:
> Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could
> share same macro, then we no need to add is_imx6ulz in various drivers.
> 
> Signed-off-by: Peng Fan 
> ---
>  arch/arm/include/asm/mach-imx/sys_proto.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
> b/arch/arm/include/asm/mach-imx/sys_proto.h
> index a02cd40c7d..2a997f280d 100644
> --- a/arch/arm/include/asm/mach-imx/sys_proto.h
> +++ b/arch/arm/include/asm/mach-imx/sys_proto.h
> @@ -37,7 +37,7 @@
>  #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
>  #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
>  #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
> -#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
> +#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || 
> is_cpu_type(MXC_CPU_MX6ULZ))

While I probably understand your intentions, I fear that it will lead to 
confusion 
when the helper's name does not reflect that more than
one cpu type can match.
What about introducing is_mx6ulX() to signal that the last letter is "don't 
care"?

Best regards,
Michael

>  #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
>  #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
>  
> 

Re: [PATCH v5 3/6] log: output for CONFIG_LOG=n

[Marek Vasut]

On 4/22/20 9:01 PM, Tom Rini wrote:
> On Wed, Apr 22, 2020 at 09:00:02PM +0200, Marek Vasut wrote:
>> On 2/26/20 9:48 PM, Heinrich Schuchardt wrote:
>>> If CONFIG_LOG=n, we should still output errors, warnings, notices, infos,
>>> and for DEBUG=1 also debug messages.
>>>
>>> Signed-off-by: Heinrich Schuchardt 
>>> Reviewed-by: Simon Glass 
>>
>> NAK
>>
>> This patch grows SoCFPGA SPL size by more than 6 bytes, and considering
>> the recent discussion, I believe it was made very clear that any growth
>> in SPL size is not allowed. I am surprised that this was not caught earlier.
>>
>> So, please revert this patch.
>>
>> I see the following with socfpga_cyclone5_defconfig
>>
>>textdata bss dec hex filename
>> - 522351916  16   54167d397 spl/u-boot-spl
>> + 523191916  16   54251d3eb spl/u-boot-spl
> 
> Bugfix of previously important prints being missing.
So, can you please clarify what the rule for acceptable SPL growth is?

Re: [PATCH v5 3/6] log: output for CONFIG_LOG=n

[Tom Rini]

On Wed, Apr 22, 2020 at 09:00:02PM +0200, Marek Vasut wrote:
> On 2/26/20 9:48 PM, Heinrich Schuchardt wrote:
> > If CONFIG_LOG=n, we should still output errors, warnings, notices, infos,
> > and for DEBUG=1 also debug messages.
> > 
> > Signed-off-by: Heinrich Schuchardt 
> > Reviewed-by: Simon Glass 
> 
> NAK
> 
> This patch grows SoCFPGA SPL size by more than 6 bytes, and considering
> the recent discussion, I believe it was made very clear that any growth
> in SPL size is not allowed. I am surprised that this was not caught earlier.
> 
> So, please revert this patch.
> 
> I see the following with socfpga_cyclone5_defconfig
> 
>textdata bss dec hex filename
> - 522351916  16   54167d397 spl/u-boot-spl
> + 523191916  16   54251d3eb spl/u-boot-spl

Bugfix of previously important prints being missing.  Fix your patch and
quit trolling please.

-- 
Tom


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Description: PGP signature

Re: [PATCH v5 3/6] log: output for CONFIG_LOG=n

[Marek Vasut]

On 2/26/20 9:48 PM, Heinrich Schuchardt wrote:
> If CONFIG_LOG=n, we should still output errors, warnings, notices, infos,
> and for DEBUG=1 also debug messages.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Simon Glass 

NAK

This patch grows SoCFPGA SPL size by more than 6 bytes, and considering
the recent discussion, I believe it was made very clear that any growth
in SPL size is not allowed. I am surprised that this was not caught earlier.

So, please revert this patch.

I see the following with socfpga_cyclone5_defconfig

   textdata bss dec hex filename
- 522351916  16   54167d397 spl/u-boot-spl
+ 523191916  16   54251d3eb spl/u-boot-spl

> ---
> v5:
>   no change
> v4:
>   no change
> ---
>  include/log.h | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/include/log.h b/include/log.h
> index 62fb8afbd0..0453876001 100644
> --- a/include/log.h
> +++ b/include/log.h
> @@ -115,11 +115,11 @@ static inline int _log_nop(enum log_category_t cat, 
> enum log_level_t level,
>  #define log_io(_fmt...)  log(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt)
>  #else
>  #define _LOG_MAX_LEVEL LOGL_INFO
> -#define log_err(_fmt...) log_nop(LOG_CATEGORY, LOGL_ERR, ##_fmt)
> -#define log_warning(_fmt...) log_nop(LOG_CATEGORY, LOGL_WARNING, ##_fmt)
> -#define log_notice(_fmt...)  log_nop(LOG_CATEGORY, LOGL_NOTICE, ##_fmt)
> -#define log_info(_fmt...)log_nop(LOG_CATEGORY, LOGL_INFO, ##_fmt)
> -#define log_debug(_fmt...)   log_nop(LOG_CATEGORY, LOGL_DEBUG, ##_fmt)
> +#define log_err(_fmt, ...)   printf(_fmt, ##__VA_ARGS__)
> +#define log_warning(_fmt, ...)   printf(_fmt, ##__VA_ARGS__)
> +#define log_notice(_fmt, ...)printf(_fmt, ##__VA_ARGS__)
> +#define log_info(_fmt, ...)  printf(_fmt, ##__VA_ARGS__)
> +#define log_debug(_fmt, ...) debug(_fmt, ##__VA_ARGS__)
>  #define log_content(_fmt...) log_nop(LOG_CATEGORY, \
>   LOGL_DEBUG_CONTENT, ##_fmt)
>  #define log_io(_fmt...)  log_nop(LOG_CATEGORY, LOGL_DEBUG_IO, 
> ##_fmt)
> --
> 2.25.0
> 

Re: Please pull u-boot-marvell/master

[Tom Rini]

On Wed, Apr 22, 2020 at 04:48:33PM +0200, Stefan Roese wrote:

> Hi Tom,
> 
> please pull the 2nd batch of MVEBU related patches in this merge
> window. The major changes are:
> 

Applied to u-boot/master, thanks!

But the following checkpatch should be fixed in a follow up sometime:
WARNING: quoted string split across lines
#28: FILE: cmd/mvebu/bubt.c:734:
+   printf("Error: A38x image meant to be "
+  "booted from \"%s\", not
\"%s\"!\n",


(There's another but I think the split is fine for how humans would grep
for it).

-- 
Tom


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Description: PGP signature

Re: Please pull mmc-2020-4-22

[Tom Rini]

On Wed, Apr 22, 2020 at 12:29:13PM +, Peng Fan wrote:

> Hi Tom,
> 
> Please pull mmc-2020-4-22.
> 
> I dropped the env patchset from the pull request since delegation change,
> but my CI still have the 3 patches, but without the 3 patches would not
> cause build issue.
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Description: PGP signature

[PATCH v3 1/2] part: detect EFI system partition

[Heinrich Schuchardt]

Up to now for MBR and GPT partitions the info field 'bootable' was set to 1
if either the partition was an EFI system partition or the bootable flag
was set.

Turn info field 'bootable' into a bit mask with separate bits for bootable
and EFI system partition.

This will allow us to identify the EFI system partition in the UEFI
sub-system.

Signed-off-by: Heinrich Schuchardt 
---
v3:
adjust gpt command to use only the boot flag not the EFI system
partition
v2:
used BIT() macro to define bit mask
---
 cmd/gpt.c   |  4 ++--
 disk/part_dos.c | 14 ++
 disk/part_efi.c | 16 ++--
 include/part.h  | 11 ++-
 4 files changed, 32 insertions(+), 13 deletions(-)

diff --git a/cmd/gpt.c b/cmd/gpt.c
index efaf1bcecb..b94f0051cd 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -245,7 +245,7 @@ static void print_gpt_info(void)
printf("Block size %lu, name %s\n", curr->gpt_part_info.blksz,
   curr->gpt_part_info.name);
printf("Type %s, bootable %d\n", curr->gpt_part_info.type,
-  curr->gpt_part_info.bootable);
+  curr->gpt_part_info.bootable & PART_BOOTABLE);
 #ifdef CONFIG_PARTITION_UUIDS
printf("UUID %s\n", curr->gpt_part_info.uuid);
 #endif
@@ -535,7 +535,7 @@ static int set_gpt_info(struct blk_desc *dev_desc,

/* bootable */
if (found_key(tok, "bootable"))
-   parts[i].bootable = 1;
+   parts[i].bootable = PART_BOOTABLE;
}

*parts_count = p_count;
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 83ff40d310..813379f851 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -45,9 +45,15 @@ static inline int is_extended(int part_type)
part_type == 0x85);
 }

-static inline int is_bootable(dos_partition_t *p)
+static int get_bootable(dos_partition_t *p)
 {
-   return (p->sys_ind == 0xef) || (p->boot_ind == 0x80);
+   int ret = 0;
+
+   if (p->sys_ind == 0xef)
+   ret |= PART_EFI_SYSTEM_PARTITION;
+   if (p->boot_ind == 0x80)
+   ret |= PART_BOOTABLE;
+   return ret;
 }

 static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector,
@@ -60,7 +66,7 @@ static void print_one_part(dos_partition_t *p, lbaint_t 
ext_part_sector,
"u\t%08x-%02x\t%02x%s%s\n",
part_num, lba_start, lba_size, disksig, part_num, p->sys_ind,
(is_extended(p->sys_ind) ? " Extd" : ""),
-   (is_bootable(p) ? " Boot" : ""));
+   (get_bootable(p) ? " Boot" : ""));
 }

 static int test_block_type(unsigned char *buffer)
@@ -258,7 +264,7 @@ static int part_get_info_extended(struct blk_desc *dev_desc,
  (char *)info->name);
/* sprintf(info->type, "%d, pt->sys_ind); */
strcpy((char *)info->type, "U-Boot");
-   info->bootable = is_bootable(pt);
+   info->bootable = get_bootable(pt);
 #if CONFIG_IS_ENABLED(PARTITION_UUIDS)
sprintf(info->uuid, "%08x-%02x", disksig, part_num);
 #endif
diff --git a/disk/part_efi.c b/disk/part_efi.c
index b2e157d9c1..83876a7bd9 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -71,11 +71,15 @@ static char *print_efiname(gpt_entry *pte)

 static const efi_guid_t system_guid = PARTITION_SYSTEM_GUID;

-static inline int is_bootable(gpt_entry *p)
+static int get_bootable(gpt_entry *p)
 {
-   return p->attributes.fields.legacy_bios_bootable ||
-   !memcmp(&(p->partition_type_guid), _guid,
-   sizeof(efi_guid_t));
+   int ret = 0;
+
+   if (!memcmp(>partition_type_guid, _guid, sizeof(efi_guid_t)))
+   ret |=  PART_EFI_SYSTEM_PARTITION;
+   if (p->attributes.fields.legacy_bios_bootable)
+   ret |=  PART_BOOTABLE;
+   return ret;
 }

 static int validate_gpt_header(gpt_header *gpt_h, lbaint_t lba,
@@ -286,7 +290,7 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part,
snprintf((char *)info->name, sizeof(info->name), "%s",
 print_efiname(_pte[part - 1]));
strcpy((char *)info->type, "U-Boot");
-   info->bootable = is_bootable(_pte[part - 1]);
+   info->bootable = get_bootable(_pte[part - 1]);
 #if CONFIG_IS_ENABLED(PARTITION_UUIDS)
uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
UUID_STR_FORMAT_GUID);
@@ -501,7 +505,7 @@ int gpt_fill_pte(struct blk_desc *dev_desc,
memset(_e[i].attributes, 0,
   sizeof(gpt_entry_attributes));

-   if (partitions[i].bootable)
+   if (partitions[i].bootable & PART_BOOTABLE)
gpt_e[i].attributes.fields.legacy_bios_bootable = 1;

/* partition name */
diff --git a/include/part.h b/include/part.h
index 

[PATCH v3 2/2] efi_loader: identify EFI system partition

[Heinrich Schuchardt]

In subsequent patches UEFI variables shalled be stored on the EFI system
partition. Hence we need to identify the EFI system partition.

Signed-off-by: Heinrich Schuchardt 
---
v3:
adjust commit message
v2:
no change
---
 include/efi_loader.h  |  7 +++
 lib/efi_loader/efi_disk.c | 20 
 2 files changed, 27 insertions(+)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index 0ba9a1f702..b7bccf50b3 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -47,6 +47,13 @@ static inline void *guidcpy(void *dst, const void *src)
 /* Root node */
 extern efi_handle_t efi_root;

+/* EFI system partition */
+extern struct efi_system_partition {
+   enum if_type if_type;
+   int devnum;
+   u8 part;
+} efi_system_partition;
+
 int __efi_entry_check(void);
 int __efi_exit_check(void);
 const char *__efi_nesting(void);
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index fd8fe17567..fd3df80b0b 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -13,6 +13,8 @@
 #include 
 #include 

+struct efi_system_partition efi_system_partition;
+
 const efi_guid_t efi_block_io_guid = EFI_BLOCK_IO_PROTOCOL_GUID;

 /**
@@ -418,6 +420,24 @@ static efi_status_t efi_disk_add_dev(
diskobj->ops.media = >media;
if (disk)
*disk = diskobj;
+
+   /* Store first EFI system partition */
+   if (part && !efi_system_partition.if_type) {
+   int r;
+   disk_partition_t info;
+
+   r = part_get_info(desc, part, );
+   if (r)
+   return EFI_DEVICE_ERROR;
+   if (info.bootable & PART_EFI_SYSTEM_PARTITION) {
+   efi_system_partition.if_type = desc->if_type;
+   efi_system_partition.devnum = desc->devnum;
+   efi_system_partition.part = part;
+   EFI_PRINT("EFI system partition: %s %d:%d\n",
+ blk_get_if_type_name(desc->if_type),
+ desc->devnum, part);
+   }
+   }
return EFI_SUCCESS;
 }

--
2.26.1

[PATCH v3 0/2] efi_loader: identify EFI system partition

[Heinrich Schuchardt]

For storing UEFI variables we need to know where the EFI system partition
is located.

With the patches the first available EFI system partition is determined
both for MBR and GPT partition tables.

v3:
adjust gpt command
adjust commit message
v2:
BIT() macro to define bit mask

Heinrich Schuchardt (2):
  part: detect EFI system partition
  efi_loader: identify EFI system partition

 cmd/gpt.c |  4 ++--
 disk/part_dos.c   | 14 ++
 disk/part_efi.c   | 16 ++--
 include/efi_loader.h  |  7 +++
 include/part.h| 11 ++-
 lib/efi_loader/efi_disk.c | 20 
 6 files changed, 59 insertions(+), 13 deletions(-)

--
2.26.1

[PATCH 3/3] configs: lx2160a: Enable OPTEE support

[Ruchika Gupta]

Enable support to compile OPTEE driver, access AVB TA
and RPMB API's access via RPC from OPTEE for lx2160

Signed-off-by: Ruchika Gupta 
---
 configs/lx2160ardb_tfa_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index c8582aa40d..930c88221f 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -73,3 +73,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_GIC_V3_ITS=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_TA_AVB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_CMD_OPTEE_RPMB=y
-- 
2.17.1

[PATCH 2/3] arm64: lx2160a: dts: Add OPTEE node

[Ruchika Gupta]

Add OPTEE node in lx2 device tree to enable access of
OPTEE TA's from u-boot.

Signed-off-by: Ruchika Gupta 
---
 arch/arm/dts/fsl-lx2160a.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 42ce4379ec..f0306e9390 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -363,4 +363,11 @@
bus-range = <0x0 0xff>;
ranges = <0x8200 0x0 0x4000 0xa8 0x4000 0x0 
0x4000>;
};
+
+   firmware {
+   optee {
+   compatible = "linaro,optee-tz";
+   method = "smc";
+   };
+   };
 };
-- 
2.17.1

[PATCH 1/3] cmd: optee_rpmb command for read/write of rpmb from optee

[Ruchika Gupta]

Enable "optee_rpmb" command to write/read named persistent values
created on RPMB by opening session with OPTEE AVB TA.
This provides easy test for establishing a session with OPTEE
TA and storage of persistent data in MMC RPMB.

It includes following subcommands:

optee_rpmb read_pvalue - read persistent values on rpmb via OPTEE AVB TA
optee_rpmb write_pvalue - write persistent values on rpmb via OPTEE AVB TA

Signed-off-by: Ruchika Gupta 
---
 cmd/Kconfig  |  16 +++
 cmd/Makefile |   1 +
 cmd/optee_rpmb.c | 269 +++
 3 files changed, 286 insertions(+)
 create mode 100644 cmd/optee_rpmb.c

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 6ce9e5521c..b5dc571e60 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1088,6 +1088,14 @@ config CMD_MMC_SWRITE
 
 endif
 
+config CMD_OPTEE_RPMB
+   bool "Enable read/write support on RPMB via OPTEE"
+   depends on SUPPORT_EMMC_RPMB && OPTEE
+   help
+ Enable the commands for reading, writing persistent named values
+ in the Replay Protection Memory Block partition in eMMC by
+ using Persistent Objects in OPTEE
+
 config CMD_MTD
bool "mtd"
depends on MTD
@@ -1137,6 +1145,14 @@ config CMD_ONENAND
  and erasing blocks. It allso provides a way to show and change
  bad blocks, and test the device.
 
+config CMD_OPTEE_RPMB
+   bool "Enable read/write support on RPMB via OPTEE"
+   depends on SUPPORT_EMMC_RPMB && OPTEE
+   help
+ Enable the commands for reading, writing persistent named values
+ in the Replay Protection Memory Block partition in eMMC by
+ using Persistent Objects in OPTEE
+
 config CMD_OSD
bool "osd"
help
diff --git a/cmd/Makefile b/cmd/Makefile
index 6692ed96c6..0159493a13 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_CMD_MII) += mii.o
 obj-$(CONFIG_CMD_MDIO) += mdio.o
 obj-$(CONFIG_CMD_MISC) += misc.o
 obj-$(CONFIG_CMD_MMC) += mmc.o
+obj-$(CONFIG_CMD_OPTEE_RPMB) += optee_rpmb.o
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_CMD_MTD) += mtd.o
 obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o
diff --git a/cmd/optee_rpmb.c b/cmd/optee_rpmb.c
new file mode 100644
index 00..829d1268f7
--- /dev/null
+++ b/cmd/optee_rpmb.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct udevice *tee;
+u32 session;
+
+static int avb_ta_open_session(void)
+{
+   const struct tee_optee_ta_uuid uuid = TA_AVB_UUID;
+   struct tee_open_session_arg arg;
+   int rc;
+
+   tee = tee_find_device(tee, NULL, NULL, NULL);
+   if (!tee)
+   return -ENODEV;
+
+   memset(, 0, sizeof(arg));
+   tee_optee_ta_uuid_to_octets(arg.uuid, );
+   rc = tee_open_session(tee, , 0, NULL);
+   if (!rc)
+   session = arg.session;
+
+   return 0;
+}
+
+static int invoke_func(u32 func, ulong num_param, struct tee_param *param)
+{
+   struct tee_invoke_arg arg;
+
+   if (!tee)
+   if (avb_ta_open_session())
+   return -ENODEV;
+
+   memset(, 0, sizeof(arg));
+   arg.func = func;
+   arg.session = session;
+
+   if (tee_invoke_func(tee, , num_param, param))
+   return -EFAULT;
+   switch (arg.ret) {
+   case TEE_SUCCESS:
+   return 0;
+   case TEE_ERROR_OUT_OF_MEMORY:
+   case TEE_ERROR_STORAGE_NO_SPACE:
+   return -ENOSPC;
+   case TEE_ERROR_ITEM_NOT_FOUND:
+   return -EIO;
+   case TEE_ERROR_TARGET_DEAD:
+   /*
+* The TA has paniced, close the session to reload the TA
+* for the next request.
+*/
+   tee_close_session(tee, session);
+   tee = NULL;
+   return -EIO;
+   default:
+   return -EIO;
+   }
+}
+
+static int read_persistent_value(const char *name,
+size_t buffer_size,
+u8 *out_buffer,
+size_t *out_num_bytes_read)
+{
+   int rc = 0;
+   struct tee_shm *shm_name;
+   struct tee_shm *shm_buf;
+   struct tee_param param[2];
+   size_t name_size = strlen(name) + 1;
+
+   if (!tee)
+   if (avb_ta_open_session())
+   return -ENODEV;
+
+   rc = tee_shm_alloc(tee, name_size,
+  TEE_SHM_ALLOC, _name);
+   if (rc)
+   return -ENOMEM;
+
+   rc = tee_shm_alloc(tee, buffer_size,
+  TEE_SHM_ALLOC, _buf);
+   if (rc) {
+   rc = -ENOMEM;
+   goto free_name;
+   }
+
+   memcpy(shm_name->addr, name, name_size);
+
+   memset(param, 0, sizeof(param));
+   param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT;
+   param[0].u.memref.shm = shm_name;
+   

Re: [PATCH] dm: pinctrl: Use right device pointer for configuring pinctrl

[Tom Rini]

On Wed, Apr 22, 2020 at 10:55:31PM +0530, Lokesh Vutla wrote:

> commit 719cab6d2e2bf ("dm: pinctrl: convert pinctrl-single to livetree")
> converted pinctrl driver to livetree. In this conversion, the call to
> read pinctrl-single,pins/bits property is provided with pinctrl device
> pointer instead of pinctrl config pointer. Because of this none of the
> pins gets configured. Fix it by passing the right udevice pointer.
> 
> Fixes: 719cab6d2e2bf ("dm: pinctrl: convert pinctrl-single to livetree")
> Reported-by: Tom Rini 
> Signed-off-by: Lokesh Vutla 

Thanks for the quick turn-around!

Tested-by: Tom Rini  [am65x_evm_a53 / am65x_evm_r5]

I'll pick this up soon to give others a chance to comment.

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH v3 01/21] dm: pinctrl: convert pinctrl-single to livetree

[Lokesh Vutla]

On 22/04/20 9:57 PM, Tom Rini wrote:
> On Fri, Apr 17, 2020 at 05:05:48PM -0400, Tom Rini wrote:
>> On Mon, Jan 13, 2020 at 11:34:55AM +0100, Patrick Delaunay wrote:
>>
>>> Convert 'pinctrl-single' using livetree functions
>>> - dev_read_prop
>>> - dev_read_u32_default
>>> - dev_read_u32_array
>>> - dev_read_bool
>>> - dev_read_addr
>>> and get rid of DECLARE_GLOBAL_DATA_PTR.
>>>
>>> Reviewed-by: Simon Glass 
>>> Signed-off-by: Patrick Delaunay 
>>
>> Applied to u-boot/master, thanks!
> 
> Now that I've setup my AM65x board, this commit is breaking boot there
> and I don't have any idea why.  I don't get any sort of output on either
> core (this platform takes am65x_evm_r5 for the SPL and am65x_evm_a53 for
> the main core).
> 

Ahh thanks for the pointer Tom. I have been struggling since yesterday as why my
board is not booting with latest master. Looks like this patch is passing the
wrong device pointer for searching pinctrl-single-pins. Just posted a patch
fixing it[0]. Please have a look and merge it asap.

[0]
https://patchwork.ozlabs.org/project/uboot/patch/20200422172531.29649-1-lokeshvu...@ti.com/

Thanks and regards,
Lokesh

[PATCH] dm: pinctrl: Use right device pointer for configuring pinctrl

[Lokesh Vutla]

commit 719cab6d2e2bf ("dm: pinctrl: convert pinctrl-single to livetree")
converted pinctrl driver to livetree. In this conversion, the call to
read pinctrl-single,pins/bits property is provided with pinctrl device
pointer instead of pinctrl config pointer. Because of this none of the
pins gets configured. Fix it by passing the right udevice pointer.

Fixes: 719cab6d2e2bf ("dm: pinctrl: convert pinctrl-single to livetree")
Reported-by: Tom Rini 
Signed-off-by: Lokesh Vutla 
---
 drivers/pinctrl/pinctrl-single.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index a5d1ff0e97..738f5bd636 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -120,7 +120,7 @@ static int single_set_state(struct udevice *dev,
const struct single_fdt_bits_cfg *prop_bits;
int len;
 
-   prop = dev_read_prop(dev, "pinctrl-single,pins", );
+   prop = dev_read_prop(config, "pinctrl-single,pins", );
 
if (prop) {
dev_dbg(dev, "configuring pins for %s\n", config->name);
@@ -133,7 +133,7 @@ static int single_set_state(struct udevice *dev,
}
 
/* pinctrl-single,pins not found so check for pinctrl-single,bits */
-   prop_bits = dev_read_prop(dev, "pinctrl-single,bits", );
+   prop_bits = dev_read_prop(config, "pinctrl-single,bits", );
if (prop_bits) {
dev_dbg(dev, "configuring pins for %s\n", config->name);
if (len % sizeof(struct single_fdt_bits_cfg)) {
-- 
2.23.0

Serial Console not taking input

[Diez Roggisch]

Hi,

I'm using u-boot v2018.07 within a custom product based on a Raspberry PI 
compute module 3. I have a serial console that works for output in u-boot, and 
out/input in Linux Land. So basic stuff like wiring, bps etc can be assumed 
working.

But I do not get to input any characters, meaning I can't play around with 
commands etc.

I rummaged throug the menuconfig and manual but so far to no avail.

Any pointers what could be at fault here, or how to investigate further?

As a note:a later version of u-boot is difficult to use due to the CM3 custom 
boot-loader. The most current one used in yocto/zeus - 2019/7 - works with the 
standard PI, but *not* with the CM3.

Cheers,

Diez

[PATCH] tools: k3_gen_x509_cert: Allow selecting early JTAG debug value

[Andrew F. Davis]

When authenticating the initial boot binary the ROM will check a debug
type value in the certificate and based on that open JTAG access to that
core.

The default is currently full access, on HS this is useful for early
developers, but should not be the default as to prevent end system
integrators from unintentionally leaving this open.

On non-HS devices JTAG is left open anyway so this does not change
behavior on those devices. Change the default to off and allow it to be
switched back on by command line flag if needed.

Signed-off-by: Andrew F. Davis 
---
 tools/k3_gen_x509_cert.sh | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/tools/k3_gen_x509_cert.sh b/tools/k3_gen_x509_cert.sh
index b6d055f6f5..298cec1313 100755
--- a/tools/k3_gen_x509_cert.sh
+++ b/tools/k3_gen_x509_cert.sh
@@ -12,6 +12,7 @@ RAND_KEY=eckey.pem
 LOADADDR=0x41c0
 BOOTCORE_OPTS=0
 BOOTCORE=16
+DEBUG_TYPE=0
 
 gen_degen_template() {
 cat << 'EOF' > degen-template.txt
@@ -79,7 +80,7 @@ cat << 'EOF' > x509-template.txt
 
  [ debug ]
  debugUID = 
FORMAT:HEX,OCT:
- debugType = INTEGER:4
+ debugType = INTEGER:TEST_DEBUG_TYPE
  coreDbgEn = INTEGER:0
  coreDbgSecEn = INTEGER:0
 EOF
@@ -151,8 +152,9 @@ options_help[k]="key_file:file with key inside it. If not 
provided script genera
 options_help[o]="output_file:Name of the final output file. default to $OUTPUT"
 options_help[c]="core_id:target core id on which the image would be running. 
Default to $BOOTCORE"
 options_help[l]="loadaddr: Target load address of the binary in hex. Default 
to $LOADADDR"
+options_help[d]="debug_type: Debug type, set to 4 to enable early JTAG. 
Default to $DEBUG_TYPE"
 
-while getopts "b:k:o:c:l:h" opt
+while getopts "b:k:o:c:l:d:h" opt
 do
case $opt in
b)
@@ -170,6 +172,9 @@ do
c)
BOOTCORE=$OPTARG
;;
+   d)
+   DEBUG_TYPE=$OPTARG
+   ;;
h)
usage
exit 0
@@ -224,12 +229,15 @@ gen_cert() {
#echo " LOADADDR = 0x$ADDR"
#echo " IMAGE_SIZE = $BIN_SIZE"
#echo " CERT_TYPE = $CERTTYPE"
+   #echo " DEBUG_TYPE = $DEBUG_TYPE"
sed -e "s/TEST_IMAGE_LENGTH/$BIN_SIZE/" \
-e "s/TEST_IMAGE_SHA_VAL/$SHA_VAL/" \
-e "s/TEST_CERT_TYPE/$CERTTYPE/" \
-e "s/TEST_BOOT_CORE_OPTS/$BOOTCORE_OPTS/" \
-e "s/TEST_BOOT_CORE/$BOOTCORE/" \
-   -e "s/TEST_BOOT_ADDR/$ADDR/" x509-template.txt > $TEMP_X509
+   -e "s/TEST_BOOT_ADDR/$ADDR/" \
+   -e "s/TEST_DEBUG_TYPE/$DEBUG_TYPE/" \
+   x509-template.txt > $TEMP_X509
openssl req -new -x509 -key $KEY -nodes -outform DER -out $CERT -config 
$TEMP_X509 -sha512
 }
 
-- 
2.17.1

[PATCH 6/6] configs: lx2160aqds_tfa_defconfig: enable DM_ETH and related

[Ioana Ciornei]

Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LX2160AQDS board.

Signed-off-by: Ioana Ciornei 
---
 configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 8 
 configs/lx2160aqds_tfa_defconfig | 8 
 2 files changed, 16 insertions(+)

diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig 
b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 319f7103829e..ba78f3ba3309 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -20,6 +20,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 
earlycon=pl011,mmio32,0x2
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -30,6 +31,8 @@ CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
+CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x 
fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x  
fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x 
fsl-lx2160a-qds-20-11-x"
+CONFIG_MULTI_DTB_FIT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
@@ -52,7 +55,12 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
 CONFIG_E1000=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 0161dba9a723..fc0d71f0d43e 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -22,6 +22,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 
earlycon=pl011,mmio32,0x2
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -32,6 +33,8 @@ CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
+CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x 
fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x  
fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x 
fsl-lx2160a-qds-20-11-x"
+CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0x2050
@@ -56,7 +59,12 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
 CONFIG_E1000=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
-- 
2.17.1

[PATCH 3/6] arm: dts: lx2160aqds: add nodes describing possible mezzanine cards

[Ioana Ciornei]

Add device trees describing possible uses of mezzanine cards depending
on the SERDES protocol employed.

Each SERDES block has a different device tree file per protocol
supported, where the IO SLOTs used are enabled and PHYs located on the
mezzanine cards are described. Also, dpmac nodes are edited and their
associated phy-connection-type and phy-handle are added.

Top DTS files are also added for each combination of protocol on the 3
SERDES blocks.

Signed-off-by: Ioana Ciornei 
---
 arch/arm/dts/Makefile|  10 +-
 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts |  19 +++
 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts  |  17 +++
 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts |  19 +++
 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts  |  17 +++
 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts  |  19 +++
 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts   |  17 +++
 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts  |  19 +++
 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts   |  17 +++
 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi |  75 ++
 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi |  39 +
 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi  |  55 +++
 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi  | 100 +
 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi |  76 ++
 arch/arm/dts/fsl-lx2160a-qds.dts | 180 +--
 arch/arm/dts/fsl-lx2160a-qds.dtsi| 169 +
 16 files changed, 670 insertions(+), 178 deletions(-)
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6d1e8668e7ee..4fe042dbd7ee 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -377,7 +377,15 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls1028a-rdb.dtb \
fsl-ls1028a-qds.dtb \
fsl-lx2160a-rdb.dtb \
-   fsl-lx2160a-qds.dtb
+   fsl-lx2160a-qds.dtb \
+   fsl-lx2160a-qds-3-x-x.dtb \
+   fsl-lx2160a-qds-3-11-x.dtb \
+   fsl-lx2160a-qds-7-x-x.dtb \
+   fsl-lx2160a-qds-7-11-x.dtb \
+   fsl-lx2160a-qds-19-x-x.dtb \
+   fsl-lx2160a-qds-19-11-x.dtb \
+   fsl-lx2160a-qds-20-x-x.dtb \
+   fsl-lx2160a-qds-20-11-x.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts 
b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
new file mode 100644
index ..585759162f6c
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 19.11.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-19.dtsi"
+
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+
+/ {
+   model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)";
+   compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts 
b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
new file mode 100644
index ..ebe11396a6cb
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 19.x.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-19.dtsi"
+
+/ {
+   model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)";
+   compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts 
b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
new file mode 100644
index ..d9f091896746
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 20.11.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-20.dtsi"
+
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+
+/ {
+   model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)";
+   compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts 
b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
new file mode 100644
index 

[PATCH 4/6] board: lx2160aqds: transition to DM_ETH

[Ioana Ciornei]

In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated.  Also, force the PCI devices to be enumerated at probe
time.

Signed-off-by: Ioana Ciornei 
---
 board/freescale/lx2160a/eth_lx2160aqds.c | 12 +++-
 board/freescale/lx2160a/lx2160a.c|  5 +
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c 
b/board/freescale/lx2160a/eth_lx2160aqds.c
index 0e928ebd8689..3b7830343d1e 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -25,6 +25,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_DM_ETH
 #define EMI_NONE   0
 #define EMI1   1 /* Mdio Bus 1 */
 #define EMI2   2 /* Mdio Bus 2 */
@@ -439,9 +440,11 @@ static inline void do_dpmac_config(int dpmac, const char 
*arg_dpmacid,
 }
 
 #endif
+#endif /* !CONFIG_DM_ETH */
 
 int board_eth_init(bd_t *bis)
 {
+#ifndef CONFIG_DM_ETH
 #if defined(CONFIG_FSL_MC_ENET)
struct memac_mdio_info mdio_info;
struct memac_mdio_controller *regs;
@@ -564,6 +567,7 @@ int board_eth_init(bd_t *bis)
 
cpu_eth_init(bis);
 #endif /* CONFIG_FMAN_ENET */
+#endif /* !CONFIG_DM_ETH */
 
 #ifdef CONFIG_PHY_AQUANTIA
/*
@@ -577,7 +581,12 @@ int board_eth_init(bd_t *bis)
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 #endif
+
+#ifdef CONFIG_DM_ETH
+   return 0;
+#else
return pci_eth_init(bis);
+#endif
 }
 
 #if defined(CONFIG_RESET_PHY_R)
@@ -589,6 +598,7 @@ void reset_phy(void)
 }
 #endif /* CONFIG_RESET_PHY_R */
 
+#ifndef CONFIG_DM_ETH
 #if defined(CONFIG_FSL_MC_ENET)
 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
 {
@@ -837,4 +847,4 @@ int fdt_fixup_board_phy(void *fdt)
return ret;
 }
 #endif // CONFIG_FSL_MC_ENET
-
+#endif
diff --git a/board/freescale/lx2160a/lx2160a.c 
b/board/freescale/lx2160a/lx2160a.c
index 23ea1b6f16aa..abfbc9188392 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -587,6 +587,9 @@ int board_init(void)
sec_init();
 #endif
 
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+   pci_init();
+#endif
return 0;
 }
 
@@ -632,7 +635,9 @@ void fdt_fixup_board_enet(void *fdt)
if (get_mc_boot_status() == 0 &&
(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
fdt_status_okay(fdt, offset);
+#ifndef CONFIG_DM_ETH
fdt_fixup_board_phy(fdt);
+#endif
} else {
fdt_status_fail(fdt, offset);
}
-- 
2.17.1

[PATCH 5/6] board: lx2160aqds: implement board_fit_config_name_match

[Ioana Ciornei]

In case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the
board_fit_config_name_match() function in order to choose the
appropriate DTS for the current SERDES protocol configuration.

Signed-off-by: Ioana Ciornei 
---
 board/freescale/lx2160a/eth_lx2160aqds.c | 109 +++
 1 file changed, 109 insertions(+)

diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c 
b/board/freescale/lx2160a/eth_lx2160aqds.c
index 3b7830343d1e..d90b5c3e3a2f 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -848,3 +848,112 @@ int fdt_fixup_board_phy(void *fdt)
 }
 #endif // CONFIG_FSL_MC_ENET
 #endif
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+   u8 serdes_block;
+   u32 serdes_protocol;
+   bool dts_needed;
+} supported_protocols[] = {
+   /* Serdes block #1 */
+   {1, 3, true},
+   {1, 7, true},
+   {1, 19, true},
+   {1, 20, true},
+
+   /* Serdes block #2 */
+   {2, 2, false},
+   {2, 3, false},
+   {2, 5, false},
+   {2, 11, true},
+
+   /* Serdes block #3 */
+   {3, 2, false},
+   {3, 3, false},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+   struct serdes_configuration serdes_conf;
+   int i;
+
+   for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+   serdes_conf = supported_protocols[i];
+   if (serdes_conf.serdes_block == serdes_block &&
+   serdes_conf.serdes_protocol == protocol)
+   return true;
+   }
+
+   return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+   struct serdes_configuration serdes_conf;
+   int i;
+
+   for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+   serdes_conf = supported_protocols[i];
+   if (serdes_conf.serdes_block == serdes_block &&
+   serdes_conf.serdes_protocol == protocol) {
+   if (serdes_conf.dts_needed == true)
+   sprintf(str, "%u", protocol);
+   else
+   sprintf(str, "x");
+   return;
+   }
+   }
+}
+
+int board_fit_config_name_match(const char *name)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   u32 rcw_status = in_le32(>rcwsr[28]);
+   char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2];
+   u32 srds_s1, srds_s2, srds_s3;
+   char expected_dts[100];
+
+   srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+   srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+   srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+   srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+   srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
+   srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
+
+   /* Check for supported protocols. The default DTS will be used
+* in this case
+*/
+   if (!protocol_supported(1, srds_s1) ||
+   !protocol_supported(2, srds_s2) ||
+   !protocol_supported(3, srds_s3))
+   return -1;
+
+   get_str_protocol(1, srds_s1, srds_s1_str);
+   get_str_protocol(2, srds_s2, srds_s2_str);
+   get_str_protocol(3, srds_s3, srds_s3_str);
+
+   sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s",
+   srds_s1_str, srds_s2_str, srds_s3_str);
+
+   if (!strcmp(name, expected_dts))
+   return 0;
+
+   return -1;
+}
+#endif
-- 
2.17.1

[PATCH 2/6] arm: dts: lx2160aqds: add MDIO slots

[Ioana Ciornei]

The LX2160A processor has two external MDIO interfaces, described in the
DTS as emdio1 and emdio2. EMDIO1 is used with two onboard RGMII PHYs
(Realtek RTL8211FD-CG), as well as eight input/output connectors for
mezzanine cards. Configuration signals from the Qixis FPGA control the
routing of the external MDIOs.

Describe register 0x54 of the Qixis FPGA as a MDIO mux controlled over
i2c and add its child MDIO busses describing the IO SLOTs.

Signed-off-by: Ioana Ciornei 
---
 arch/arm/dts/fsl-lx2160a-qds.dts | 115 ++-
 1 file changed, 114 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts
index 592fd5977e27..4946ce8dfba8 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dts
+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
@@ -2,7 +2,7 @@
 /*
  * NXP LX2160AQDS device tree source
  *
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
  *
  */
 
@@ -18,6 +18,26 @@
};
 };
 
+ {
+   status = "okay";
+   phy-handle = <_phy1>;
+   phy-connection-type = "rgmii-id";
+};
+
+ {
+   status = "okay";
+   phy-handle = <_phy2>;
+   phy-connection-type = "rgmii-id";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
@@ -30,6 +50,99 @@
status = "okay";
u-boot,dm-pre-reloc;
 
+   fpga@66 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "simple-mfd";
+   reg = <0x66>;
+
+   mux-mdio@54 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "mdio-mux-i2creg";
+   reg = <0x54>;
+   #mux-control-cells = <1>;
+   mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
+   mdio-parent-bus = <>;
+
+   mdio@00 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x00>;
+
+   rgmii_phy1: ethernet-phy@1 {
+   reg = <0x1>;
+   };
+   };
+   mdio@08 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x40>;
+
+   rgmii_phy2: ethernet-phy@2 {
+   reg = <0x2>;
+   };
+   };
+
+   emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
+   reg = <0xC0>;
+   device-name = "emdio1_slot1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
+   reg = <0xC8>;
+   device-name = "emdio1_slot2";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
+   reg = <0xD0>;
+   device-name = "emdio1_slot3";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
+   reg = <0xD8>;
+   device-name = "emdio1_slot4";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
+   reg = <0xE0>;
+   device-name = "emdio1_slot5";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
+   reg = <0xE8>;
+   device-name = "emdio1_slot6";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
+   reg = <0xF0>;
+   device-name = "emdio1_slot7";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
+   reg = <0xF8>;
+   device-name = "emdio1_slot8";
+  

[PATCH 0/6] boards: lx2160aqds: transition to CONFIG_DM_ETH

[Ioana Ciornei]

This patch set targets to add support for CONFIG_DM_ETH for the NXP
LX2160AQDS board.

The main focus is on changing the DTS based on the SERDES protocol used.
In order to accomplish this, the MULTI_DTB_FIT feature is employed and
the appropriate DTS is chosed on boot from a list of predefined files.

The possible DTS filenames for the board have a standard format that
describes for which SERDES protocol combinations it can be used.  For
example, the 'fsl-lx2160a-qds-19-11-x.dtb' can be used for a LX2160AQDS
board which is configured as follows:
 * SERDES block #1 - protocol 19
 * SERDES block #2 - protocol 11
 * SERDES block #3 - any protocol

Any unnecessary configurations made for the DPAA2 ethernet devices in
the board files are compiled out when CONFIG_DM_ETH is enabled. This is
because any information necessary is available in its associated DTS
node.

This patch set depends on another series that adds support for DM_ETH in
the ldpaa_eth driver and the RDB boards:
 https://patchwork.ozlabs.org/project/uboot/list/?series=165158

Ioana Ciornei (6):
  arm: dts: lx2160a: add any missing dpmac nodes
  arm: dts: lx2160aqds: add MDIO slots
  arm: dts: lx2160aqds: add nodes describing possible mezzanine cards
  board: lx2160aqds: transition to DM_ETH
  board: lx2160aqds: implement board_fit_config_name_match
  configs: lx2160aqds_tfa_defconfig: enable DM_ETH and related

 arch/arm/dts/Makefile|  10 +-
 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts |  19 +++
 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts  |  17 ++
 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts |  19 +++
 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts  |  17 ++
 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts  |  19 +++
 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts   |  17 ++
 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts  |  19 +++
 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts   |  17 ++
 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi |  75 
 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi |  39 +
 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi  |  55 ++
 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi  | 100 +++
 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi |  76 +
 arch/arm/dts/fsl-lx2160a-qds.dts |  67 +---
 arch/arm/dts/fsl-lx2160a-qds.dtsi| 169 +++
 arch/arm/dts/fsl-lx2160a.dtsi|  86 +-
 board/freescale/lx2160a/eth_lx2160aqds.c | 119 +
 board/freescale/lx2160a/lx2160a.c|   5 +
 configs/lx2160aqds_tfa_SECURE_BOOT_defconfig |   8 +
 configs/lx2160aqds_tfa_defconfig |   8 +
 21 files changed, 895 insertions(+), 66 deletions(-)
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
 create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi

-- 
2.17.1

[PATCH 1/6] arm: dts: lx2160a: add any missing dpmac nodes

[Ioana Ciornei]

Add the remaining DPMAC nodes in the LX2160A base dtsi.
These will be later used on the LX2160AQDS specific DTS.

Signed-off-by: Ioana Ciornei 
---
 arch/arm/dts/fsl-lx2160a.dtsi | 86 ++-
 1 file changed, 85 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 17ecdc569b37..9499fb9a3779 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP lx2160a SOC common device tree source
  *
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
  *
  */
 
@@ -383,6 +383,18 @@
#address-cells = <1>;
#size-cells = <0>;
 
+   dpmac1: dpmac@1 {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0x1>;
+   status = "disabled";
+   };
+
+   dpmac2: dpmac@2 {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0x2>;
+   status = "disabled";
+   };
+
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x3>;
@@ -395,6 +407,78 @@
status = "disabled";
};
 
+   dpmac5: dpmac@5 {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0x5>;
+   status = "disabled";
+   };
+
+   dpmac6: dpmac@6 {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0x6>;
+   status = "disabled";
+   };
+
+   dpmac7: dpmac@7 {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0x7>;
+   status = "disabled";
+   };
+
+   dpmac8: dpmac@8 {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0x8>;
+   status = "disabled";
+   };
+
+   dpmac9: dpmac@9 {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0x9>;
+   status = "disabled";
+   };
+
+   dpmac10: dpmac@a {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0xa>;
+   status = "disabled";
+   };
+
+   dpmac11: dpmac@b {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0xb>;
+   status = "disabled";
+   };
+
+   dpmac12: dpmac@c {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0xc>;
+   status = "disabled";
+   };
+
+   dpmac13: dpmac@d {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0xd>;
+   status = "disabled";
+   };
+
+   dpmac14: dpmac@e {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0xe>;
+   status = "disabled";
+   };
+
+   dpmac15: dpmac@f {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0xf>;
+   status = "disabled";
+   };
+
+   dpmac16: dpmac@10 {
+   compatible = "fsl,qoriq-mc-dpmac";
+   reg = <0x10>;
+   status = "disabled";
+   };
+
dpmac17: dpmac@11 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x11>;
-- 
2.17.1

[PATCH] arm: dts: uDPU: switch default PHY speed to 3.125Gbit

[Jakov Petrina]

This resolves issues with certain SFP modules.

Signed-off-by: Jakov Petrina 
Signed-off-by: Vladimir Vid 
---
 arch/arm/dts/armada-3720-uDPU.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/armada-3720-uDPU.dts 
b/arch/arm/dts/armada-3720-uDPU.dts
index 683dac2a7c..d528f07ec0 100644
--- a/arch/arm/dts/armada-3720-uDPU.dts
+++ b/arch/arm/dts/armada-3720-uDPU.dts
@@ -109,11 +109,11 @@
  {
phy0 {
phy-type = ;
-   phy-speed = ;
+   phy-speed = ;
};
 phy1 {
 phy-type = ;
-phy-speed = ;
+phy-speed = ;
 };
 
 phy2 {
-- 
2.24.1

Re: [PATCH U-BOOT 18/26] fs: btrfs: Implement btrfs_lookup_path()

[Su Yue]

On Wed 22 Apr 2020 at 14:50, Qu Wenruo  wrote:


This is the extent buffer based path lookup routine.

To implement this, btrfs_lookup_dir_item() is cross ported from
btrfs-progs, and implement btrfs_lookup_path() from scratch.

Unlike the existing __btrfs_lookup_path(), since
btrfs_read_fs_root() will check whether a root is orphan at read
time, there is no need to check root backref, this make the code
a little easier to read.

Signed-off-by: Qu Wenruo  ---
 fs/btrfs/ctree.h|   4 + fs/btrfs/dir-item.c | 106
 +++ fs/btrfs/inode.c| 245
  3 files changed,
 355 insertions(+)

diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h index
f702eaff293c..78f7746d1f32 100644 --- a/fs/btrfs/ctree.h +++
b/fs/btrfs/ctree.h @@ -1284,6 +1284,10 @@ struct btrfs_dir_item
*btrfs_lookup_dir_item(struct btrfs_trans_handle *trans,
 struct btrfs_path *path, u64 dir, 
const
 char *name, int name_len, int mod);
+/* inode.c */ +int btrfs_lookup_path(struct btrfs_root *root,
u64 ino, const char *filename, +struct btrfs_root
**root_ret, u64 *ino_ret, + u8 *type_ret, int
symlink_limit);
  /* ctree.c */ int btrfs_comp_cpu_keys(const struct btrfs_key
 *k1, const struct btrfs_key *k2);
diff --git a/fs/btrfs/dir-item.c b/fs/btrfs/dir-item.c index
aea621c72bb3..4bf45c2fa925 100644 --- a/fs/btrfs/dir-item.c +++
b/fs/btrfs/dir-item.c @@ -8,6 +8,112 @@
 #include "btrfs.h" #include "disk-io.h"
+static int verify_dir_item(struct btrfs_root *root, +
struct extent_buffer *leaf, +   struct btrfs_dir_item
*dir_item) +{ + u16 namelen = BTRFS_NAME_LEN; + u8 type =
btrfs_dir_type(leaf, dir_item); + + if (type ==
BTRFS_FT_XATTR) +   namelen = XATTR_NAME_MAX; + +   if
(btrfs_dir_name_len(leaf, dir_item) > namelen) { +
fprintf(stderr, "invalid dir item name len: %u\n", +
(unsigned)btrfs_dir_data_len(leaf, dir_item)); +return 1;
+   } + +   /* BTRFS_MAX_XATTR_SIZE is the same for all dir items
*/ +if ((btrfs_dir_data_len(leaf, dir_item) + +
btrfs_dir_name_len(leaf, dir_item)) > +
BTRFS_MAX_XATTR_SIZE(root->fs_info)) { + fprintf(stderr,
"invalid dir item name + data len: %u + %u\n", +
(unsigned)btrfs_dir_name_len(leaf, dir_item), +
(unsigned)btrfs_dir_data_len(leaf, dir_item)); +return 1;
+   } + +   return 0; +} + +struct btrfs_dir_item
*btrfs_match_dir_item_name(struct btrfs_root *root, +
struct btrfs_path *path, +const char *name,
int name_len) +{ +  struct btrfs_dir_item *dir_item; +
unsigned long name_ptr; +   u32 total_len; +u32 cur = 0; +
u32 this_len; + struct extent_buffer *leaf; + + leaf =
path->nodes[0]; +dir_item = btrfs_item_ptr(leaf,
path->slots[0], struct btrfs_dir_item); +total_len =
btrfs_item_size_nr(leaf, path->slots[0]); +  if
(verify_dir_item(root, leaf, dir_item)) +   return NULL; + +
while(cur < total_len) { +   this_len = sizeof(*dir_item) +
+   btrfs_dir_name_len(leaf, dir_item) + +
btrfs_dir_data_len(leaf, dir_item); +   if (this_len >
(total_len - cur)) { +  fprintf(stderr, "invalid dir
item size\n"); +   return NULL; +  } + +
name_ptr = (unsigned long)(dir_item + 1); + +   if
(btrfs_dir_name_len(leaf, dir_item) == name_len && +
memcmp_extent_buffer(leaf, name, name_ptr, name_len) == 0) +
return dir_item; + +cur += this_len; +  dir_item =
(struct btrfs_dir_item *)((char *)dir_item + +
this_len); +} + return NULL; +} + +struct btrfs_dir_item
*btrfs_lookup_dir_item(struct btrfs_trans_handle *trans, +
struct btrfs_root *root, +   struct
btrfs_path *path, u64 dir, + const char
*name, int name_len, +   int mod) +{ +
int ret; +  struct btrfs_key key; + int ins_len = mod < 0 ? -1
: 0; +  int cow = mod != 0; +   struct btrfs_key found_key; +
struct extent_buffer *leaf; + + key.objectid = dir; +
key.type = BTRFS_DIR_ITEM_KEY; + +  key.offset =
btrfs_name_hash(name, name_len); + +ret =
btrfs_search_slot(trans, root, , path, ins_len, cow); + if
(ret < 0) +  return ERR_PTR(ret); +  if (ret > 0) { +
if (path->slots[0] == 0) +   return NULL; +
path->slots[0]--; +  } + +   leaf = path->nodes[0]; +
btrfs_item_key_to_cpu(leaf, _key, path->slots[0]); + + if
(found_key.objectid != dir || + found_key.type !=
BTRFS_DIR_ITEM_KEY || + found_key.offset != key.offset) +
return NULL; + +return btrfs_match_dir_item_name(root, path,
name, name_len); +} +
 static int __verify_dir_item(struct btrfs_dir_item *item, u32
 start, u32 total) { u16 max_len = BTRFS_NAME_LEN;
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index
df2f6590bb40..af4f30bbd50c 100644 --- a/fs/btrfs/inode.c 

Re: [RFC PATCH 8/9] pci: Add driver for Broadcom STB PCIe controller

[Nicolas Saenz Julienne]

On Wed, 2020-04-22 at 18:42 +0200, Sylwester Nawrocki wrote:
> Hi Nicolas,
> 
> On 22.04.2020 11:16, Nicolas Saenz Julienne wrote:
>  
> > I see that you based your code on the downstream PCIe driver (the one
> > available
> > in the Raspberry Pi foundation kernel repos). There's a real upstream
> > version
> > of it[1], It's properly reviewed and we made a point to remove all non
> > bcm2711
> > specific stuff from it, as support for other platforms (like bcm7445) isn't
> > there yet (it depends on supporting multiple dma-ranges in Linux, which we
> > don't). Also note that the Raspberry Pi foundation is moving towards using
> > this
> > driver, see for example their rpi-5.6.y branch, and I belive Broadcom is
> > doing
> > the same.
> > 
> > So I strongly suggest you base this driver on the upstream version. As I was
> > working towards the same goal as you I already have an implementation for
> > u-boot myself[2]. Feel free to use that if you find it useful. Ultimately,
> > whether you base it on my version or the upstream Linux version it's half
> > the
> > size and easier to follow.
> 
> Thanks, I'm going to reuse you code, it looks much cleaner.
> I started working on this PCIe driver back at end of 2019, then that task was
> postponed for few months. I should have been following better related Linux
> mainline works. Now, when it all more or less works I will try reuse your
> code.

Nice, FYI I replaced the driver as is and it worked out of the box, so it
should be relatively painless.

Regards,
Nicolas



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Re: [RFC PATCH 9/9] config: Enable support for the XHCI controller on RPI4 board

[Sylwester Nawrocki]

On 22.04.2020 14:26, Nicolas Saenz Julienne wrote:
> On Wed, 2020-04-22 at 11:50 +0100, Peter Robinson wrote:

>>> Would you mind enabling USB keyboard support too? It's useful for people
>>> using
>>> u-boot/UEFI.
>>
>> And storage too:
>> CONFIG_USB_STORAGE=y
>> CONFIG_USB_KEYBOARD=y
>>
>> In testing these patches I can see the devices with a "usb tree" but
>> even with the keyboard enabled it doesn't appear to work. AFAICT with
>> it enabled there should be support for usb keyboard via console in
>> include/configs/rpi.h but I couldn't see what else might be missing.
> 
> That's surprising, USB keyboard works fine in my case.

USB keyboard also works well for me (but not the one with a built-in 
touchpad). I could add those 2 additional options to the patch but perhaps 
it's better to leave it as is, i.e. enable PCIe/xHCI in one patch and all 
needed USB devices in another?
  
-- 
Regards,
Sylwester

Re: [RFC PATCH 8/9] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

Hi Nicolas,

On 22.04.2020 11:16, Nicolas Saenz Julienne wrote:
 
> I see that you based your code on the downstream PCIe driver (the one 
> available
> in the Raspberry Pi foundation kernel repos). There's a real upstream version
> of it[1], It's properly reviewed and we made a point to remove all non bcm2711
> specific stuff from it, as support for other platforms (like bcm7445) isn't
> there yet (it depends on supporting multiple dma-ranges in Linux, which we
> don't). Also note that the Raspberry Pi foundation is moving towards using 
> this
> driver, see for example their rpi-5.6.y branch, and I belive Broadcom is doing
> the same.
> 
> So I strongly suggest you base this driver on the upstream version. As I was
> working towards the same goal as you I already have an implementation for
> u-boot myself[2]. Feel free to use that if you find it useful. Ultimately,
> whether you base it on my version or the upstream Linux version it's half the
> size and easier to follow.

Thanks, I'm going to reuse you code, it looks much cleaner.
I started working on this PCIe driver back at end of 2019, then that task was
postponed for few months. I should have been following better related Linux
mainline works. Now, when it all more or less works I will try reuse your code.
> [1] 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-brcmstb.c?h=v5.7-rc2
> [2] 
> https://protect2.fireeye.com/url?k=14361ea6-49a8854c-143795e9-0cc47a6cba04-df90fb3bfec30a2d=1=https%3A%2F%2Fgithub.com%2Fvianpl%2Fu-boot%2Fcommits%2Fbrcm-pcie
> 

-- 
Regards,
Sylwester

Re: [RFC PATCH 1/9] usb: xhci: Add missing cache flush in the scratchpad array initialization

[Simon Glass]

On Wed, 22 Apr 2020 at 06:33, Nicolas Saenz Julienne
 wrote:
>
> On Wed, 2020-04-22 at 14:01 +0200, Sylwester Nawrocki wrote:
> > Hi Nicolas,
> >
> > (fixed Simon's email address, apologies for mistyping it, I will make sure
> > it's correct in next iteration)
> >
> > On 22.04.2020 10:53, Nicolas Saenz Julienne wrote:
> > > I've been trying to get this working on my own and got stuck with this
> > > specific
> > > issue. I'm glad you found a solution, it was driving me crazy.
> > >
> > > Out of curiosity how did you found the solution?
> >
> > It took me many days of debugging...given my nearly non existent previous
> > experience in u-boot development.In short, it started with a suggestion to 
> > map
> > all memory for CPU as uncached.
> > As in such a case booting was failing I checked where the xhci shared buffer
> > allocation fall and created only a small uncached window to cover those
> > allocations. This was first thing that started working, after fixing the
> > 64-bit pointers setup in XHCI registers.
> > Then I discovered "dcache" command and that was also helpful. It was
> > sufficient
> > to run "dcache off; usb start; dcache on". Then USB worked even after "usb
> > reset"
> > IIRC. But that was with my old development branch based on v2019.10-rc4 tag.
> > Marek tried the same with newer tree and dcache_disable() was not helping,
> > but dcache_flush_all() was.
> >
> > By moving dcache_disable(), dcache_enable() around I found out that it was
> > sufficient to disable dcache before xhci_start() call and to enable it right
> > afterwards.
> >
> > Then I just "bisected" the uncached memory region which narrowed it roughly
> > to the scratchpad buffer allocations. By inspecting the code carefully again
> > it turned there is one more cache flush call needed.
>
> Thanks for the in-depth explanation, it's very much appreciated!

Yes indeed, thank you!


- Simon

Re: [PATCH v1 2/2] cmd: bind: allow to bind driver with driver data

[Simon Glass]

Hi Patrice,

On Wed, 22 Apr 2020 at 02:13, Patrice CHOTARD  wrote:
>
>
> On 4/21/20 7:36 PM, Simon Glass wrote:
> > Hi Patrice,
> >
> > On Tue, 21 Apr 2020 at 08:09, Patrice Chotard  
> > wrote:
> >> Initial implementation invokes device_bind_with_driver_data()
> >> with driver_data parameter equal to 0.
> >> For driver with driver data, the bind command can't bind
> >> correctly this driver or even worse causes data abort.
> >>
> >> Add find_udevice_id() to parse the driver's of_match list
> >> and return the entry corresponding to the driver compatible string.
> >> This allows to get access to driver_data and to use it as
> >> parameters of device_bind_with_driver_data().
> >>
> >> Signed-off-by: Patrice Chotard 
> >> Cc: Jean-Jacques Hiblot 
> >>
> >> ---
> >>
> >>  cmd/bind.c | 29 -
> >>  1 file changed, 28 insertions(+), 1 deletion(-)
> >>
> > The thing I don't quite get here is why the driver name needs to be
> > specified. If the device tree node is present, and it has a compatible
>
> Sorry, i didn't get your point when you said "why the driver name needs to be 
> specified"

It's just that I don't understand it at all. If the compatible string
is available, why not use lists_bind_fdt()?

>
> Which part of this patch do you made reference to ?

The whole thing, because I just don't understand the bind command.

>
> > string, can't DM find the driver and bind a device automatically?
> >
> > Also, is there any docs for this command? It would be good to add to
>
> Is what in cmd/bind.c not enough ?

I am just confused here. You obviously have a use case in mind, but
the help below is not sufficient to understand what is going on. As I
said, if you have a device-tree node you can find the driver. I am
just not sure what this is for.

It could really use a short document as I said, to explain the uses of
this command and what it does in a bit more detail.

>
>
> U_BOOT_CMD(
> bind,4,0,do_bind_unbind,
> "Bind a device to a driver",
> " \n"
> "bind   \n"
> );
>
> U_BOOT_CMD(
> unbind,4,0,do_bind_unbind,
> "Unbind a device from a driver",
> "\n"
> "unbind  \n"
> "unbind   \n"
> );
>
>
> > doc/driver-model and also add a simple test.
>
> Ok i will add an additionnal test to test/py/tests/test_bind.py

OK thanks.

Regards,
SImon

Re: [PATCH] net: ethernet: ti: am65-cpsw-nuss: enable 10Mbps link speed in rgmii mode

[Grygorii Strashko]

On 20/04/2020 14:10, Murali Karicheri wrote:

+ Lokesh

On 04/17/2020 11:12 AM, Murali Karicheri wrote:

In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is
configured for External Control ("in band") mode
CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1

Hence update am65_cpsw_update_link() to follow documentation.

Signed-off-by: Murali Karicheri 
---
  drivers/net/ti/am65-cpsw-nuss.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 2b77213001..7531a07203 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -61,6 +61,7 @@
  #define AM65_CPSW_MACSL_CTL_REG    0x0
  #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A    BIT(15)
+#define AM65_CPSW_MACSL_CTL_EXT_EN    BIT(18)
  #define AM65_CPSW_MACSL_CTL_REG_GIG    BIT(7)
  #define AM65_CPSW_MACSL_CTL_REG_GMII_EN    BIT(5)
  #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK    BIT(1)
@@ -187,6 +188,9 @@ static int am65_cpsw_update_link(struct am65_cpsw_priv 
*priv)
    AM65_CPSW_MACSL_CTL_REG_GMII_EN;
  if (phy->speed == 1000)
  mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
+    if (phy->speed == 10 && phy_interface_is_rgmii(phy))
+    /* Can be used with in band mode only */
+    mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN;
  if (phy->duplex == DUPLEX_FULL)
  mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
  if (phy->speed == 100)





Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH v3 01/21] dm: pinctrl: convert pinctrl-single to livetree

[Tom Rini]

On Fri, Apr 17, 2020 at 05:05:48PM -0400, Tom Rini wrote:
> On Mon, Jan 13, 2020 at 11:34:55AM +0100, Patrick Delaunay wrote:
> 
> > Convert 'pinctrl-single' using livetree functions
> > - dev_read_prop
> > - dev_read_u32_default
> > - dev_read_u32_array
> > - dev_read_bool
> > - dev_read_addr
> > and get rid of DECLARE_GLOBAL_DATA_PTR.
> > 
> > Reviewed-by: Simon Glass 
> > Signed-off-by: Patrick Delaunay 
> 
> Applied to u-boot/master, thanks!

Now that I've setup my AM65x board, this commit is breaking boot there
and I don't have any idea why.  I don't get any sort of output on either
core (this platform takes am65x_evm_r5 for the SPL and am65x_evm_a53 for
the main core).

-- 
Tom


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[PATCH 2/2] i2c: designware_i2c: Check if the device is powered

[Simon Glass]

From: Raul E Rangel 

If the device doesn't return a version that means the device is
non-functional.

The dw_i2c_regs had invalid offsets for the version field. I got the
correct value from the DesignWare databook. It also matches what the
Picasso PPR says.

Signed-off-by: Raul E Rangel 
Reviewed-by: Simon Glass 
Reviewed-by: Furquan Shaikh 
Tested on chromebook_coral:
Signed-off-by: Simon Glass 
---

 drivers/i2c/designware_i2c.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index ac170769f4..f7a48f6225 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -16,6 +16,12 @@
 #include 
 #include 
 
+/*
+ * This assigned unique hex value is constant and is derived from the two ASCII
+ * letters 'DW' followed by a 16-bit unsigned number
+ */
+#define DW_I2C_COMP_TYPE   0x44570140
+
 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 {
@@ -764,6 +770,17 @@ int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 int designware_i2c_probe(struct udevice *bus)
 {
struct dw_i2c *priv = dev_get_priv(bus);
+   uint comp_type;
+
+   comp_type = readl(>regs->comp_type);
+   if (comp_type != DW_I2C_COMP_TYPE) {
+   log_err("I2C bus %s has unknown type %#x\n", bus->name,
+   comp_type);
+   return -ENXIO;
+   }
+
+   log_info("I2C bus %s version %#x\n", bus->name,
+readl(>regs->comp_version));
 
return __dw_i2c_init(priv->regs, 0, 0);
 }
-- 
2.26.1.301.g55bc3eb7cb9-goog

Re: [PATCH v3 22/23] i2c: designware_i2c: Separate out the speed calculation

[Simon Glass]

Hi Heinrich,

On Wed, 22 Apr 2020 at 00:43, Heinrich Schuchardt  wrote:
>
> On 1/23/20 7:48 PM, Simon Glass wrote:
> > We want to be able to calculate the speed separately from actually setting
> > the speed, so we can generate the required ACPI tables. Split out the
> > calculation into its own function.
> >
> > Drop the double underscore on __dw_i2c_set_bus_speed while we are here.
> > That is reserved for compiler internals.
> >
> > Signed-off-by: Simon Glass 
> > ---
> >
> > Changes in v3:
> > - Add new patch to separate out the speed calculation
> >
> > Changes in v2: None
> >
> >  drivers/i2c/designware_i2c.c | 78 +---
> >  drivers/i2c/designware_i2c.h |  3 ++
> >  2 files changed, 48 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
> > index 6be98ee43b..39af25af9a 100644
> > --- a/drivers/i2c/designware_i2c.c
> > +++ b/drivers/i2c/designware_i2c.c
> > @@ -194,22 +194,12 @@ static int dw_i2c_calc_timing(struct dw_i2c *priv, 
> > enum i2c_speed_mode mode,
> >   return 0;
> >  }
> >
> > -/*
> > - * i2c_set_bus_speed - Set the i2c speed
> > - * @speed:   required i2c speed
> > - *
> > - * Set the i2c speed.
> > - */
> > -static unsigned int __dw_i2c_set_bus_speed(struct dw_i2c *priv,
> > -struct i2c_regs *i2c_base,
> > -unsigned int speed,
> > -unsigned int bus_clk)
> > +static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
> > +   struct dw_i2c_speed_config *config)
> >  {
> >   const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
> > - struct dw_i2c_speed_config config;
> > + struct i2c_regs *regs = priv->regs;
>
> Later in the code you have 'if (priv)'. Please, do not dereference priv
> before the check.
>
> Overall the code is somehow odd:
>
> _dw_i2c_set_bus_speed() is called in multiple places with priv == NULL
> and then calls calc_bus_speed(priv, ...).
>
> Then in calc_bus_speed() you have:
>
> comp_param1 = readl(>comp_param1);
>
> where regs == NULL->regs.
>
> comp_param1 is used later on in the code to determine i2c_spd which is
> returned in config->speed_mode.

Only for non-DM though I think. Still this is horrible, will send a patch.

What board are you testing with?

>
> Could you, please, have a close look at the driver.
>
> Best regards
>
> Heinrich
>
Regards,
Simon

[PATCH 1/2] i2c: designware_i2c: Tidy up use of NULL priv

[Simon Glass]

At present we still have pre-driver-model code in this driver and it makes
things a bit confusing. In particular calc_bus_speed() is called with priv
as NULL if not using driver model.

This results in spk_cnt and comp_param1 being read from an invalid address
if not using driver model. For comp_param1 this may not cause problems if
reading from addresses close to 0 happens to be allowed, as high speed is
only supported by DM code. But spk_cnt is subsequently used to calculate
the bus periods and so this may cause problems (e.g. on spear600 board
which has not been migrated yet).

Add a new parameter regs parameter to calc_bus_speed() and add more
comments to this function and to _dw_i2c_set_bus_speed(), which calls it.

Signed-off-by: Simon Glass 
Reported-by: Heinrich Schuchardt 
---

 drivers/i2c/designware_i2c.c | 34 +++---
 1 file changed, 23 insertions(+), 11 deletions(-)

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 088a6f3efb..ac170769f4 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -197,18 +197,24 @@ static int dw_i2c_calc_timing(struct dw_i2c *priv, enum 
i2c_speed_mode mode,
return 0;
 }
 
-static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
- struct dw_i2c_speed_config *config)
+/**
+ * calc_bus_speed() - Calculate the config to use for a particular i2c speed
+ *
+ * @priv: Private information for the driver (NULL if not using driver model)
+ * @i2c_base: Registers for the I2C controller
+ * @speed: Required i2c speed in Hz
+ * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
+ * @config: Returns the config to use for this speed
+ * @return 0 if OK, -ve on error
+ */
+static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int 
speed,
+ ulong bus_clk, struct dw_i2c_speed_config *config)
 {
const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
-   struct i2c_regs *regs = priv->regs;
enum i2c_speed_mode i2c_spd;
-   u32 comp_param1;
int spk_cnt;
int ret;
 
-   comp_param1 = readl(>comp_param1);
-
if (priv)
scl_sda_cfg = priv->scl_sda_cfg;
/* Allow high speed if there is no config, or the config allows it */
@@ -223,6 +229,9 @@ static int calc_bus_speed(struct dw_i2c *priv, int speed, 
ulong bus_clk,
 
/* Check is high speed possible and fall back to fast mode if not */
if (i2c_spd == IC_SPEED_MODE_HIGH) {
+   u32 comp_param1;
+
+   comp_param1 = readl(>comp_param1);
if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
i2c_spd = IC_SPEED_MODE_FAST;
@@ -258,11 +267,14 @@ static int calc_bus_speed(struct dw_i2c *priv, int speed, 
ulong bus_clk,
return 0;
 }
 
-/*
- * _dw_i2c_set_bus_speed - Set the i2c speed
- * @speed: required i2c speed
+/**
+ * _dw_i2c_set_bus_speed() - Set the i2c speed
  *
- * Set the i2c speed.
+ * @priv: Private information for the driver (NULL if not using driver model)
+ * @i2c_base: Registers for the I2C controller
+ * @speed: Required i2c speed in Hz
+ * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
+ * @return 0 if OK, -ve on error
  */
 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs 
*i2c_base,
 unsigned int speed, unsigned int bus_clk)
@@ -272,7 +284,7 @@ static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, 
struct i2c_regs *i2c_base,
unsigned int ena;
int ret;
 
-   ret = calc_bus_speed(priv, speed, bus_clk, );
+   ret = calc_bus_speed(priv, i2c_base, speed, bus_clk, );
if (ret)
return ret;
 
-- 
2.26.1.301.g55bc3eb7cb9-goog

[PATCH 3/3] rtc: Add base support for the RK808 PMIC RTC

[sunil]

From: Suniel Mahesh 

Rockchip RK808 PMIC provides an integrated RTC module. It is
commonly used with Rockchip SoCs. Add basic support to access
date and time.

Signed-off-by: Suniel Mahesh 
---
Note:
1. The RK808 PMIC RTC has a hardware bug. It counts 31 days
for november month and the weeks register counts 0 - 7.

2. This driver does a temporary fix, where as in if date is Nov 31,
then it resets the date to Dec 1(this happens only if date cmd is queried
from u-boot command line/script). Similarly for the weeks register, 0(sun)
- 6(sat). If 7 is encountered then it is reset to zero.

3. u-boot generally loads linux/other binary. Linux has a full fledged
driver implemented along with a workaround.
https://lkml.org/lkml/2015/12/2/1202

4. Is this change acceptable ? please comment
---
 configs/roc-pc-rk3399_defconfig |   2 +
 drivers/rtc/Kconfig |   8 ++
 drivers/rtc/Makefile|   1 +
 drivers/rtc/rk808-rtc.c | 165 
 4 files changed, 176 insertions(+)
 create mode 100644 drivers/rtc/rk808-rtc.c

diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index be76524..e98d680 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -20,6 +20,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DATE=y
 CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc"
@@ -39,6 +40,7 @@ CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
+CONFIG_DM_RTC=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM_RK3399_LPDDR4=y
 CONFIG_BAUDRATE=150
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 59e2fc4..6cf1abb 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -75,6 +75,14 @@ config RTC_ISL1208
  This driver supports reading and writing the RTC/calendar and detects
  total power failures.
 
+config RTC_RK808
+   bool "Enable Rockchip RK8XX RTC driver"
+depends on DM_RTC && PMIC_RK8XX
+   default y
+   help
+ Basic support for Rockchip RK808 PMIC Real Time Clock devices for 
+ time and date.
+
 config RTC_RV3029
bool "Enable RV3029 driver"
depends on DM_RTC
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 12eb449..63e2c34 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_RTC_PCF8563) += pcf8563.o
 obj-$(CONFIG_RTC_PCF2127) += pcf2127.o
 obj-$(CONFIG_RTC_PL031) += pl031.o
 obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
+obj-$(CONFIG_RTC_RK808) += rk808-rtc.o
 obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
 obj-$(CONFIG_RTC_RV3029) += rv3029.o
 obj-$(CONFIG_RTC_RV8803) += rv8803.o
diff --git a/drivers/rtc/rk808-rtc.c b/drivers/rtc/rk808-rtc.c
new file mode 100644
index 000..b63cced
--- /dev/null
+++ b/drivers/rtc/rk808-rtc.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RTC driver for Rockchip RK808 PMIC.
+ *
+ * Copyright (C) 2020 Amarula Solutions(India).
+ * Suniel Mahesh 
+ *
+ * Based on code from Linux kernel:
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Chris Zhong 
+ * Author: Zhang Qing 
+ *
+ * Date & Time support (no alarms and interrupts)
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* RTC_CTRL_REG bitfields */
+#define BIT_RTC_CTRL_REG_STOP_RTC_MBIT(0)
+
+/* RK808 has a shadowed register for saving a "frozen" RTC time.
+ * When user setting "GET_TIME" to 1, the time will save in this shadowed
+ * register. If set "READSEL" to 1, user read rtc time register, actually
+ * get the time of that moment. If we need the real time, clr this bit.
+ */
+
+#define BIT_RTC_CTRL_REG_RTC_GET_TIME  BIT(6)
+#define BIT_RTC_CTRL_REG_RTC_READSEL_M BIT(7)
+#define RTC_STATUS_MASK0xFE
+
+#define SECONDS_REG_MSK0x7F
+#define MINUTES_REG_MAK0x7F
+#define HOURS_REG_MSK  0x3F
+#define DAYS_REG_MSK   0x3F
+#define MONTHS_REG_MSK 0x1F
+#define YEARS_REG_MSK  0xFF
+#define WEEKS_REG_MSK  0x7
+
+/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
+
+#define NUM_TIME_REGS  (REG_WEEKS - REG_SECONDS + 1)
+
+static int rk808_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+   u8 rtc_data[NUM_TIME_REGS];
+
+   debug("RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
+   tm->tm_year, tm->tm_mon, tm->tm_mday,
+   tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+   rtc_data[0] = bin2bcd(tm->tm_sec);
+   rtc_data[1] = bin2bcd(tm->tm_min);
+   rtc_data[2] = bin2bcd(tm->tm_hour);
+   rtc_data[3] = bin2bcd(tm->tm_mday);
+   rtc_data[4] = bin2bcd(tm->tm_mon);
+   

[PATCH 0/3] Add support for Rockchip RK808 PMIC RTC device

[sunil]

From: Suniel Mahesh 

This patch series adds support for Rockchip RK808 PMIC RTC device.

Patch #1, adds a child node under RK808 PMIC node. Patch #2 binds
this child device with its parent RK808 PMIC. Patch #3 adds the rtc
driver. 

The RK808 PMIC RTC has a hardware bug. It counts 31 days for november
month and the weeks register counts 0 - 7.

This driver does a temporary fix, where as in if date is Nov 31, then it resets
the date to Dec 1(this happens only if date cmd is queried from u-boot command 
line/script).
Similarly for the weeks register, 0(sun) - 6(sat). If 7 is encountered then it 
is reset to zero.

u-boot generally loads linux/other binary. Linux has a full fledged
driver implemented along with a workaround.
https://lkml.org/lkml/2015/12/2/1202 

Is this changeset acceptable ? please comment.

Suniel Mahesh (3):
  arm: dts: rockchip: rk3399-roc-pc: Add RTC child node for RK808 PMIC
  power: pmic: rk8xx: bind rk808 RTC
  rtc: Add base support for the RK808 PMIC RTC

 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi |   8 ++
 configs/roc-pc-rk3399_defconfig|   2 +
 drivers/power/pmic/rk8xx.c |  19 +++-
 drivers/rtc/Kconfig|   8 ++
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rk808-rtc.c| 169 +
 6 files changed, 206 insertions(+), 1 deletion(-)
 create mode 100644 drivers/rtc/rk808-rtc.c

-- 
2.7.4

[PATCH 2/3] power: pmic: rk8xx: bind rk808 RTC

[sunil]

From: Suniel Mahesh 

RK808 PMIC is a multi functional device with an RTC. In order to access
RTC, bind to its parent device i.e. RK808 PMIC.

Signed-off-by: Suniel Mahesh 
---
 drivers/power/pmic/rk8xx.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 52e6d9d..8d6b64e 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -24,6 +24,11 @@ static const struct pmic_child_info pmic_children_info[] = {
{ },
 };
 
+static const struct pmic_child_info rtc_info[] = {
+   { .prefix = "rk808-rtc", .driver = "rk808_rtc"},
+   { },
+};
+
 static int rk8xx_reg_count(struct udevice *dev)
 {
return RK808_NUM_OF_REGS;
@@ -59,7 +64,7 @@ static int rk8xx_read(struct udevice *dev, uint reg, uint8_t 
*buff, int len)
 #if CONFIG_IS_ENABLED(PMIC_CHILDREN)
 static int rk8xx_bind(struct udevice *dev)
 {
-   ofnode regulators_node;
+   ofnode regulators_node, rtc_node;
int children;
 
regulators_node = dev_read_subnode(dev, "regulators");
@@ -75,6 +80,18 @@ static int rk8xx_bind(struct udevice *dev)
if (!children)
debug("%s: %s - no child found\n", __func__, dev->name);
 
+   rtc_node = dev_read_subnode(dev, "rtc");
+   if (!ofnode_valid(rtc_node)) {
+   debug("%s: %s rtc subnode not found!\n", __func__, dev->name);
+   return -ENXIO;
+   }
+
+   debug("%s: '%s' - found rtc subnode\n", __func__, dev->name);
+
+   children = pmic_bind_children(dev, rtc_node, rtc_info);
+   if (!children)
+   debug("%s: %s - no child found\n", __func__, dev->name);
+
/* Always return success for this device */
return 0;
 }
-- 
2.7.4

[PATCH 1/3] arm: dts: rockchip: rk3399-roc-pc: Add RTC child node for RK808 PMIC

[sunil]

From: Suniel Mahesh 

Rockchip RK808 PMIC is a multi function device which hosts a Real Time
Clock along with other devices. Add a child RTC node so that it can be
bound and probed once the master pmic node completes probe.

Signed-off-by: Suniel Mahesh 
---
 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi 
b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
index 5746442..7d189c8 100644
--- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -20,3 +20,11 @@
regulator-min-microvolt = <43>;
regulator-init-microvolt = <95>;
 };
+
+ {
+   rtc {
+   rkrtc: rk808-rtc {
+   status="okay";
+   };
+   };
+};
-- 
2.7.4

Re: [RFC PATCH 1/3] net: phy: Add a generic phy file for TI generic PHYs

[Grygorii Strashko]

On 21/04/2020 14:48, Dan Murphy wrote:

Michal

On 4/21/20 2:57 AM, Michal Simek wrote:

On 20. 04. 20 20:53, Dan Murphy wrote:

Add a TI Generic init file that will initialize TI PHYs that follow that
not require special handling.  These PHYs can connect with the standard
MII register set.  This generice file will register the PHY IDs and
names of the PHYs so when the command 'mdio list' is executed the PHY
name will display as opposed to 'Generic PHY'.

The DP8382X PHY series is a generic PHY that requires the generic
registration.

The DP83867 driver was updated to rename the init to a more PHY specific
init call.

Signed-off-by: Dan Murphy 

I would personally do it with two patches.


I was going to do 2 patches but I wanted to show the viability of why this 
generic file was needed.  Without the DP8382X PHY added it looks like I was 
just moving things around for the DP83867 and changing names.

I will break it up in v2 (non-RFC if no one has serious objections to this)




---
  configs/am65x_evm_a53_defconfig  |   2 +-
  configs/am65x_hs_evm_a53_defconfig   |   2 +-
  configs/dra7xx_evm_defconfig |   2 +-
  configs/dra7xx_hs_evm_defconfig  |   2 +-
  configs/dra7xx_hs_evm_usb_defconfig  |   2 +-
  configs/j721e_evm_a72_defconfig  |   2 +-
  configs/j721e_hs_evm_a72_defconfig   |   2 +-
  configs/k2g_evm_defconfig    |   2 +-
  configs/xilinx_versal_virt_defconfig |   2 +-
  configs/xilinx_zynqmp_virt_defconfig |   2 +-
  drivers/net/phy/Kconfig  |   8 ++
  drivers/net/phy/Makefile |   3 +-
  drivers/net/phy/dp83867.c    |   3 +-
  drivers/net/phy/ti_phy_init.c    | 106 +++
  drivers/net/phy/ti_phy_init.h    |  16 
  15 files changed, 144 insertions(+), 12 deletions(-)
  create mode 100644 drivers/net/phy/ti_phy_init.c
  create mode 100644 drivers/net/phy/ti_phy_init.h

diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 542bbd992c53..7051d6c40505 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -101,7 +101,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT
  CONFIG_SPI_FLASH_STMICRO=y
  # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_DP83867=y

Don't know why this name was chosen but don't you want to label it with TI?

CONFIG_PHY_TI_DP83867 ?

Kernel is using different symbol anyway.
CONFIG_DP83867_PHY


ACK.  I will make it CONFIG_PHY_TI_DP83867.  That follows the Kconfig uBoot 
standard for PHYs


yep. It definitely has to be split

Cover?

--
Best regards,
grygorii

[PATCH 2/2] test/py: fix test_efi_secboot/conftest.py

[Heinrich Schuchardt]

If udisksctl is present
test/py/tests/test_efi_secboot/conftest.py
fails because the disk image is never mounted.

Normal users can only mount fuse file systems. Unfortunately fusefat is
still in an experimental state and seems not to work here correctly.

So as we have to be root or use the sudo command anyway delete all coding
referring to udisksctl.

--

We should not use mount point /mnt as this directory or one of its
sub-directories might already be in use as active mount points. Instead
create a new directory in the build root as mount point.

--

Remove debug print statements that have been commented out. print without
parentheses is anyway invalid in Python 3. And pytest anyway filters out
the output if there is no exception reported.

Signed-off-by: Heinrich Schuchardt 
---
 test/py/tests/test_efi_secboot/conftest.py | 30 +-
 1 file changed, 6 insertions(+), 24 deletions(-)

diff --git a/test/py/tests/test_efi_secboot/conftest.py 
b/test/py/tests/test_efi_secboot/conftest.py
index 40cdf15bf2..93d308cf0d 100644
--- a/test/py/tests/test_efi_secboot/conftest.py
+++ b/test/py/tests/test_efi_secboot/conftest.py
@@ -43,7 +43,8 @@ def efi_boot_env(request, u_boot_config):
 HELLO_PATH = u_boot_config.build_dir + '/lib/efi_loader/helloworld.efi'

 try:
-non_root = tool_is_in_path('udisksctl')
+mnt_point = u_boot_config.persistent_data_dir + '/mnt_efisecure'
+check_call('mkdir -p {}'.format(mnt_point), shell=True)

 # create a disk/partition
 check_call('dd if=/dev/zero of=%s bs=1MiB count=%d'
@@ -57,25 +58,11 @@ def efi_boot_env(request, u_boot_config):
 check_call('dd if=%s.tmp of=%s bs=1MiB seek=1 count=%d conv=notrunc'
 % (image_path, image_path, 1), shell=True)
 check_call('rm %s.tmp' % image_path, shell=True)
-if non_root:
-out_data = check_output('udisksctl loop-setup -f %s -o %d'
-% (image_path, 1048576), shell=True).decode()
-m = re.search('(?<= as )(.*)\.', out_data)
-loop_dev = m.group(1)
-# print 'loop device is: %s' % loop_dev
-out_data = check_output('udisksctl info -b %s'
-% loop_dev, shell=True).decode()
-m = re.search('MountPoints:[ \t]+(.*)', out_data)
-mnt_point = m.group(1)
-else:
-loop_dev = check_output('sudo losetup -o 1MiB --sizelimit %dMiB 
--show -f %s | tr -d "\n"'
+loop_dev = check_output('sudo losetup -o 1MiB --sizelimit %dMiB --show 
-f %s | tr -d "\n"'
 % (part_size, image_path), shell=True).decode()
-mnt_point = '/mnt'
-check_output('sudo mount -t %s -o umask=000 %s %s'
+check_output('sudo mount -t %s -o umask=000 %s %s'
 % (fs_type, loop_dev, mnt_point), shell=True)

-# print 'mount point is: %s' % mnt_point
-
 # suffix
 # *.key: RSA private key in PEM
 # *.crt: X509 certificate (self-signed) in PEM
@@ -134,13 +121,8 @@ def efi_boot_env(request, u_boot_config):
 % (mnt_point, EFITOOLS_PATH, EFITOOLS_PATH),
 shell=True)

-if non_root:
-check_call('udisksctl unmount -b %s' % loop_dev, shell=True)
-# not needed
-# check_call('udisksctl loop-delete -b %s' % loop_dev, shell=True)
-else:
-check_call('sudo umount %s' % loop_dev, shell=True)
-check_call('sudo losetup -d %s' % loop_dev, shell=True)
+check_call('sudo umount %s' % loop_dev, shell=True)
+check_call('sudo losetup -d %s' % loop_dev, shell=True)

 except CalledProcessError as e:
 pytest.skip('Setup failed: %s' % e.cmd)
--
2.26.1

[PATCH 1/2] test/py: efi_secboot should not assume sbin is in the path

[Heinrich Schuchardt]

For non-root users /sbin is typically not in the path. So use absolute
paths to mkfs.vfat and sgdisk.

Signed-off-by: Heinrich Schuchardt 
---
 test/py/tests/test_efi_secboot/conftest.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/test/py/tests/test_efi_secboot/conftest.py 
b/test/py/tests/test_efi_secboot/conftest.py
index e542fef6e8..40cdf15bf2 100644
--- a/test/py/tests/test_efi_secboot/conftest.py
+++ b/test/py/tests/test_efi_secboot/conftest.py
@@ -48,12 +48,12 @@ def efi_boot_env(request, u_boot_config):
 # create a disk/partition
 check_call('dd if=/dev/zero of=%s bs=1MiB count=%d'
 % (image_path, image_size), shell=True)
-check_call('sgdisk %s -n 1:0:+%dMiB'
+check_call('/sbin/sgdisk %s -n 1:0:+%dMiB'
 % (image_path, part_size), shell=True)
 # create a file system
 check_call('dd if=/dev/zero of=%s.tmp bs=1MiB count=%d'
 % (image_path, part_size), shell=True)
-check_call('mkfs -t %s %s.tmp' % (fs_type, image_path), shell=True)
+check_call('/sbin/mkfs.%s %s.tmp' % (fs_type, image_path), shell=True)
 check_call('dd if=%s.tmp of=%s bs=1MiB seek=1 count=%d conv=notrunc'
 % (image_path, image_path, 1), shell=True)
 check_call('rm %s.tmp' % image_path, shell=True)
--
2.26.1

[PATCH 0/2] test/py: fix test_efi_secboot/conftest.py

[Heinrich Schuchardt]

The Python tests for secure booting have some issues that stop them from
being executed by non-root.

With this patch series a non-root user can execute the tests if he is
member of the sudoers group.

The test preparations relies on mounting a disk image. Non-root users can
only mount fuse file-systems and fusefat is in bad shape. So currently
changing the tests to run as non-sudo user seems infeasible.

Heinrich Schuchardt (2):
  test/py: efi_secboot should not assume sbin is in the path
  test/py: fix test_efi_secboot/conftest.py

 test/py/tests/test_efi_secboot/conftest.py | 34 +-
 1 file changed, 8 insertions(+), 26 deletions(-)

--
2.26.1

RE: [PATCH] configs: add support for stm32mp157c-dk2 board

[Patrick DELAUNAY]

Hi

> From: Arnaud Ferraris 
> Sent: mercredi 22 avril 2020 15:19
> 
> This config is based on stm32mp15_basic_defconfig and adds the necessary
> options to be able to boot a STM32MP157C-DK2 dev board.
> 
> Signed-off-by: Arnaud Ferraris 
> ---
>  configs/stm32mp157c-dk2_defconfig | 131
> ++
>  1 file changed, 131 insertions(+)
>  create mode 100644 configs/stm32mp157c-dk2_defconfig
>

For information, stm32mp157c-dk2 board is already supported by 
stm32mp15_basic_defconfig
without the need of a specific defconfig (I am using it every day).

You just need to specify the used devictree with the generic Makefile parameter
DEVICE_TREE=stm32mp157c-dk2

For support details: ./doc/board/st/stm32mp1.rst
Or https://wiki.st.com/stm32mpu/wiki/STM32MP15_U-Boot

example

  # make stm32mp15_basic_defconfig
  # make DEVICE_TREE=stm32mp157c-dk2 all

Or

  # export KBUILD_OUTPUT=../build/stm32mp15_basic
  # export DEVICE_TREE= stm32mp157c-dk2
  # make stm32mp15_basic_defconfig
  # make all

CONFIG_DEFAULT_DEVICE_TREE only provide the default device tree used
when DEVICE_TREE is absent.

What it is the need to this new defconfig ?
U-Boot size optimization for DK2 only ?

PS: If something is missing in 
stm32mp15_basic_defconfig/stm32mp15_trusted_defconfig
   it should be added in this generic target common for all ST supported 
boards.

Regards

Patrick

Re: [PATCH V3 3/6] ARM: stm32: Implement board coding on AV96

[Marek Vasut]

On 4/22/20 5:04 PM, Patrick DELAUNAY wrote:
> Hi Marek,

Hi,

>> From: Marek Vasut 
>> Sent: mercredi 22 avril 2020 13:18
>>
>> The AV96 board does exist in multiple variants. To cater for all of them, 
>> implement
>> board code handling. There are two GPIOs which code the type of the board, 
>> read
>> them out and use the value to pick the correct device tree from an fitImage.
>>
>> Reviewed-by: Patrick Delaunay 
>> Signed-off-by: Marek Vasut 
>> Cc: Manivannan Sadhasivam 
>> Cc: Patrick Delaunay 
>> Cc: Patrice Chotard 
>> ---
>> V2: No change
>> V3: Drop dm-pre-reloc and gpio-cells from config node
>> ---
>>  arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi|  1 +
>>  .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi   |  1 +
>>  arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi|  7 +++
>>  board/dhelectronics/dh_stm32mp1/Kconfig   |  2 +-
>>  board/dhelectronics/dh_stm32mp1/board.c   | 61 +++
>>  .../dh_stm32mp1/u-boot-dhcom.its  | 39 
>>  .../dh_stm32mp1/u-boot-dhcor.its  | 39 
>>  configs/stm32mp15_dhcom_basic_defconfig   |  3 +
>>  configs/stm32mp15_dhcor_basic_defconfig   |  3 +
>>  include/configs/dh_stm32mp1.h | 15 +
>>  10 files changed, 170 insertions(+), 1 deletion(-)  create mode 100644
>> board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
>>  create mode 100644 board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
>>  create mode 100644 include/configs/dh_stm32mp1.h
>>
> 
> I have 2 compilation issue on this patch with buildman
> 
> tools/buildman/buildman -v -V stm32mp15_dhcom_basic stm32mp15_dhcor_basic
> 
> Building current source for 2 boards (2 threads, 6 jobs per thread)
>arm:  +   stm32mp15_dhcor_basic
> +FATAL ERROR: Couldn't open 
> "board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its": No such file or directory
> +./tools/mkimage: Can't open u-boot.itb.tmp: No such file or directory
> +/local/home/frq07632/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ld.bfd:
>  common/built-in.o: in function `fit_find_config_node':
> +common/common_fit.c:66: undefined reference to `board_fit_config_name_match'
> +make[2]: *** [spl/u-boot-spl] Error 1
> +make[1]: *** [spl/u-boot-spl] Error 2
> +make: *** [sub-make] Error 2
>arm:  +   stm32mp15_dhcom_basic   
> +FATAL ERROR: Couldn't open 
> "board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its": No such file or directory
> +./tools/mkimage: Can't open u-boot.itb.tmp: No such file or directory
> +/local/home/frq07632/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ld.bfd:
>  common/built-in.o: in function `fit_find_config_node':
> +common/common_fit.c:66: undefined reference to `board_fit_config_name_match'
> +make[2]: *** [spl/u-boot-spl] Error 1
> +make[1]: *** [spl/u-boot-spl] Error 2
> +make: *** [sub-make] Error 2
> 002 /2  stm32mp15_dhcom_basic
>  
> 
> The 'board_fit_config_name_match'  error 
> is just because CONFIG_BOARD_EARLY_INIT_F=y is missing in the 2 defconfig 
> (added in PATH 6/6 but needed in patch 3)

Ha, OK, I'll move that in V4.

> But I reproduce of other buildman just with out of dir compilation
> KBUILD_OUTPUT=../build
> 
> I think that Makefile  serach 
> CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its" 
> in the builddir but it is present in the srcdir.
> 
> And you are the first user of CONFIG_SPL_FIT_SOURCE...

Most certainly not the first, this was used before.

> I want to propose to copy the file with:
> 
> --- Makefile 
> ---
> index 26307fd4a6..2dbf96a073 100644
> @@ -1320,7 +1320,12 @@ endif
>  # Boards with more complex image requirements can provide an .its source file
>  # or a generator script
>  ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
> -U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
> +
> +U_BOOT_ITS := u-boot.its
> +
> +$(U_BOOT_ITS): $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
> + $(call if_changed,copy)
> +
>  else
>  ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
>  U_BOOT_ITS := u-boot.its
> 
> 
> But then you need to update the patch in .its files
> 
> => remove no more necessary "../../../"

Cam you send this patch, so I can rebase on top of it ?

RE: [PATCH V3 3/6] ARM: stm32: Implement board coding on AV96

[Patrick DELAUNAY]

Hi Marek,

> From: Marek Vasut 
> Sent: mercredi 22 avril 2020 13:18
> 
> The AV96 board does exist in multiple variants. To cater for all of them, 
> implement
> board code handling. There are two GPIOs which code the type of the board, 
> read
> them out and use the value to pick the correct device tree from an fitImage.
> 
> Reviewed-by: Patrick Delaunay 
> Signed-off-by: Marek Vasut 
> Cc: Manivannan Sadhasivam 
> Cc: Patrick Delaunay 
> Cc: Patrice Chotard 
> ---
> V2: No change
> V3: Drop dm-pre-reloc and gpio-cells from config node
> ---
>  arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi|  1 +
>  .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi   |  1 +
>  arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi|  7 +++
>  board/dhelectronics/dh_stm32mp1/Kconfig   |  2 +-
>  board/dhelectronics/dh_stm32mp1/board.c   | 61 +++
>  .../dh_stm32mp1/u-boot-dhcom.its  | 39 
>  .../dh_stm32mp1/u-boot-dhcor.its  | 39 
>  configs/stm32mp15_dhcom_basic_defconfig   |  3 +
>  configs/stm32mp15_dhcor_basic_defconfig   |  3 +
>  include/configs/dh_stm32mp1.h | 15 +
>  10 files changed, 170 insertions(+), 1 deletion(-)  create mode 100644
> board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
>  create mode 100644 board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
>  create mode 100644 include/configs/dh_stm32mp1.h
> 

I have 2 compilation issue on this patch with buildman

tools/buildman/buildman -v -V stm32mp15_dhcom_basic stm32mp15_dhcor_basic

Building current source for 2 boards (2 threads, 6 jobs per thread)
   arm:  +   stm32mp15_dhcor_basic
+FATAL ERROR: Couldn't open "board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its": 
No such file or directory
+./tools/mkimage: Can't open u-boot.itb.tmp: No such file or directory
+/local/home/frq07632/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ld.bfd:
 common/built-in.o: in function `fit_find_config_node':
+common/common_fit.c:66: undefined reference to `board_fit_config_name_match'
+make[2]: *** [spl/u-boot-spl] Error 1
+make[1]: *** [spl/u-boot-spl] Error 2
+make: *** [sub-make] Error 2
   arm:  +   stm32mp15_dhcom_basic   
+FATAL ERROR: Couldn't open "board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its": 
No such file or directory
+./tools/mkimage: Can't open u-boot.itb.tmp: No such file or directory
+/local/home/frq07632/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ld.bfd:
 common/built-in.o: in function `fit_find_config_node':
+common/common_fit.c:66: undefined reference to `board_fit_config_name_match'
+make[2]: *** [spl/u-boot-spl] Error 1
+make[1]: *** [spl/u-boot-spl] Error 2
+make: *** [sub-make] Error 2
002 /2  stm32mp15_dhcom_basic
 

The 'board_fit_config_name_match'  error 
is just because CONFIG_BOARD_EARLY_INIT_F=y is missing in the 2 defconfig 
(added in PATH 6/6 but needed in patch 3)


But I reproduce of other buildman just with out of dir compilation
KBUILD_OUTPUT=../build

I think that Makefile  serach 
CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its" 
in the builddir but it is present in the srcdir.

And you are the first user of CONFIG_SPL_FIT_SOURCE...

I want to propose to copy the file with:

--- Makefile ---
index 26307fd4a6..2dbf96a073 100644
@@ -1320,7 +1320,12 @@ endif
 # Boards with more complex image requirements can provide an .its source file
 # or a generator script
 ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
-U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
+
+U_BOOT_ITS := u-boot.its
+
+$(U_BOOT_ITS): $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
+   $(call if_changed,copy)
+
 else
 ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
 U_BOOT_ITS := u-boot.its


But then you need to update the patch in .its files

=> remove no more necessary "../../../"

Regards

Patrick

Re: Please pull NXP i.MX nxp-imx-20200422

[Fabio Estevam]

Hi Peng,

On Wed, Apr 22, 2020 at 10:54 AM Peng Fan  wrote:
>
> Hi Stefano,
>
> Please pull this version nxp-imx-20200422, with patches sent out to ML.
> Based on yours master branch.

These 24 patches have just been posted to the list.

Please allow time for people to review it and only send the pull
request after review has been done.

Re: [PATCH U-BOOT 18/26] fs: btrfs: Implement btrfs_lookup_path()

[Marek Behun]

On Wed, 22 Apr 2020 22:44:43 +0800
Su Yue  wrote:

> Looked through older codes, should be "symlink_limit - 1"?

OMG yes :) without this it can break :)

Please pull u-boot-marvell/master

[Stefan Roese]

Hi Tom,

please pull the 2nd batch of MVEBU related patches in this merge
window. The major changes are:


- mvebu bubt cmd: Add A38x support (Joel)
- Clearfog: Fix SCSI boot duplication (Joel)
- Armada-37xx: Fix DDR PHY clock divider values (Marek)


Here the Azure build, without any issues:

https://dev.azure.com/sr0718/u-boot/_build/results?buildId=5=results

Thanks,
Stefan


The following changes since commit bdcb29960e3a9558803632783b922f26993d219e:

  Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq 
(2020-04-21 15:20:42 -0400)


are available in the Git repository at:

  g...@gitlab.denx.de:u-boot/custodians/u-boot-marvell.git

for you to fetch changes up to f60a66ef5d7da1980f180cd1cbfd2ce01157e522:

  cmd: mvebu: bubt: show image boot device (2020-04-22 14:28:15 +0200)


Joel Johnson (7):
  arm: mvebu: clearfog: adjust SCSI boot duplication
  arm: mvebu: correct SPL boot configs for SPI/MMC
  cmd: mvebu: bubt: add A38x support
  cmd: mvebu: bubt: correct U-Boot spelling
  cmd: mvebu: bubt: verify A38x target device type
  arm: mvebu: clearfog: enable bubt command
  cmd: mvebu: bubt: show image boot device

Marek Behún (1):
  clk: armada-37xx-periph: fix DDR PHY clock divider values

 arch/arm/mach-mvebu/Kconfig|  12 +++
 cmd/mvebu/bubt.c   | 133 
+++--

 configs/clearfog_defconfig |   4 +-
 configs/controlcenterdc_defconfig  |   4 -
 configs/db-88f6720_defconfig   |   4 -
 configs/db-88f6820-amc_defconfig   |   4 -
 configs/db-88f6820-gp_defconfig|   4 -
 configs/db-mv784mp-gp_defconfig|   3 -
 configs/ds414_defconfig|   3 -
 configs/helios4_defconfig  |   1 -
 configs/maxbcm_defconfig   |   3 -
 configs/theadorable_debug_defconfig|   3 -
 configs/turris_omnia_defconfig |   4 -
 configs/x530_defconfig |   4 -
 drivers/clk/mvebu/armada-37xx-periph.c |   4 +-
 include/configs/clearfog.h |   7 --
 include/configs/helios4.h  |   5 --
 17 files changed, 142 insertions(+), 60 deletions(-)

AW: latest u-boot branch for Marvell Armada 88F3720

[Moritz Berghof]

On Wed, 22 Apr 2020 09:03:58 +
Moritz Berghof  wrote:

>> Hi Marek,
>> 
>> do you have an espressobin? If not, please give me an answer, I can send you 
>> one board for development / testing if you like. Unfortunately ssh access is 
>> not possible. 
>> 
>> Greetings,

>No, I do not. That's why I wanted to test u-boot via ssh :)
>Marek

Ok. So i can send you one espressobin via packet to your place. Do you like for 
development / testing? So we would have the same platforms. 

--
Moritz Berghof
Software Engineer
Tel. +49 30 921028-209 
Fax +49 30 921028-020
mberg...@phoenixcontact.com
www.phoenixcontact.com
 
PHOENIX CONTACT Cyber Security GmbH
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-Ursprüngliche Nachricht-
Von: Marek Behun  
Gesendet: Dienstag, 21. April 2020 13:12
An: Moritz Berghof 
Cc: u-boot mailing list ; stefan roese 
Betreff: Re: latest u-boot branch for Marvell Armada 88F3720

***External email! Do not click links or open attachments unless you recognize 
the sender and know the content is safe.***

Moritz,
is it possible for you to give me ssh access to a computer connected to the 
espressobin? Are you open to that? I could give you information about how to do 
it.
Marek

On Tue, 21 Apr 2020 10:25:22 +
Moritz Berghof  wrote:

> Hi Marek,
>
> sorry i'm not that fast. Different things around.
>
> I tested the u-boot master with your patches. But it crashed on my 
> espressobin, unfortunately.
>
> Log:
>
> DLL 0xc0001050[29:24]: [5,32,1b]
>DLL 0xc0001054[21:16]: [4,2b,17]
>DLL 0xc0001054[29:24]: [a,35,1f]
>DLL 0xc0001074[21:16]: [0,3f,1f]
>DLL 0xc0001074NOTICE:  Booting Trusted Firmware
> NOTICE:  BL1: v1.3(release):armada-17.10.8:34247e02
> NOTICE:  BL1: Built : 10:52:47, Mar 31 2NOTICE:  BL2: 
> v1.3(release):armada-17.10.8:34247e02
> NOTICE:  BL2: Built : 10:52:48, Mar 31 2020
> NNOTICE:  BL31: v1.3(release):armada-17.10.8:34247e02
> NOTICE:  BL31:
>
> U-Boot 2020.04-00490-ge4837da782 (Apr 21 2020 - 12:06:24 +0200)
>
> DRAM:  1 GiB
> Comphy-0: UNCONNECTED   2.5 Gbps
> Comphy-1: UNCONNECTED   5 Gbps
> Comphy-2: SATA0 5 Gbps
> SATA link 0 timeout.
> AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
> flags: ncq led only pmp fbss pio slum part sxs "Synchronous Abort" 
> handler, esr 0x96000210
> elr: 00028afc lr : 00028acc (reloc)
> elr: 3ff6aafc lr : 3ff6aacc
> x0 : d0074000 x1 : 
> x2 : 0008 x3 : 
> x4 : 0018 x5 : 
> x6 : 3fb2f440 x7 : ffe0
> x8 : 3fb2f640 x9 : 0008
> x10: 0abc x11: 3fb2f23c
> x12: 0a2b x13: 0a20
> x14:  x15: 3fb2f640
> x16: 3ffc7f41 x17: 3ffc7f41
> x18: 3fb31de0 x19: 3fb33aa0
> x20: 3fb33880 x21: 3ffd2800
> x22:  x23: 
> x24:  x25: 
> x26:  x27: 
> x28:  x29: 3fb2f540
>
> Code: 91406000 b901 f9400260 91401000 (b9480001) Resetting CPU ...
>
> resetting ...
>
>
>
>
>
> Even when I disable the sata device at the espressobin .dts, the actuall 
> master crashs.
>
> Log:
>
> DLL 0xc0001050[29:24]: [5,32,1b]
>DLL 0xc0001054[21:16]: [4,2b,17]
>DLL 0xc0001054[29:24]: [a,35,1f]
>DLL 0xc0001074[21:16]: [0,3f,1f]
>DLL 0xc0001074NOTICE:  Booting Trusted Firmware
> NOTICE:  BL1: v1.3(release):armada-17.10.8:34247e02
> NOTICE:  BL1: Built : 10:52:47, Mar 31 2NOTICE:  BL2: 
> v1.3(release):armada-17.10.8:34247e02
> NOTICE:  BL2: Built : 10:52:48, Mar 31 2020
> NNOTICE:  BL31: v1.3(release):armada-17.10.8:34247e02
> NOTICE:  BL31:
>
> U-Boot 2020.04-00490-ge4837da782 (Apr 21 2020 - 12:06:24 +0200)
>
> DRAM:  1 GiB
> Comphy-0: UNCONNECTED   2.5 Gbps
> Comphy-1: UNCONNECTED   5 Gbps
> Comphy-2: SATA0 5 Gbps
> "Synchronous Abort" handler, esr 0x96000210
> elr: 00028afc lr : 00028acc (reloc)
> elr: 3ff6aafc lr : 3ff6aacc
> x0 : d0074000 x1 : 
> x2 : 0008 x3 : 
> x4 : 0018 x5 : 
> x6 : 3fb2f440 x7 : ffe0
> x8 : 3fb2f640 x9 : 0008
> x10: 0abc x11: 3fb2f23c
> x12: 0a2b x13: 0a20
> x14:  x15: 3fb2f640
> x16: 3ffc7f41 x17: 3ffc7f41
> x18: 3fb31de0 x19: 3fb33aa0
> x20: 3fb33880 x21: 3ffd2800
> x22:  x23: 
> x24:  x25: 
> x26:  x27: 
> x28:  x29: 3fb2f540
>
> Code: 91406000 b901 f9400260 91401000 (b9480001) Resetting CPU ...
>
> resetting ...
>
>
>
> To disable Sata 

Re: [PATCH 5/5] Add initial support for the Pinebook Pro laptop from Pine64.

[Rtp]

Hi,

> diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi 
> b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
> new file mode 100644
> index 00..1a2e24d3ef
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Peter Robinson 
> + */
> +
> +#include "rk3399-u-boot.dtsi"
> +#include "rk3399-sdram-lpddr4-100.dtsi"
> +
> +/ {
> +   aliases {
> +   spi0 = 
> +   };
> +
> +   chosen {
> +   u-boot,spl-boot-order = "same-as-spl", , 
> +   };
> +};
> +
> + {
> +   u-boot,dm-pre-reloc;
> +};
> +
> + {
> +   u-boot,dm-pre-reloc;
> +};

This one makes the SPL rather unhappy on my system:

U-Boot TPL 2020.04-00522-g1bf65142b3-dirty (Apr 22 2020 - 15:22:59)
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
256B stride
lpddr4_set_rate: change freq to 4 mhz 0, 1
lpddr4_set_rate: change freq to 8 mhz 1, 0
Trying to boot from BOOTROM
Returning to boot ROM...
spl_early_init() failed: -6
### ERROR ### Please RESET the board ###

Any idea ? Configuration issue ?

Arnaud

Re: [PATCH U-BOOT 18/26] fs: btrfs: Implement btrfs_lookup_path()

[Su Yue]

On Wed 22 Apr 2020 at 18:04, Marek Behun 
wrote:


On Wed, 22 Apr 2020 17:46:25 +0800 Su Yue 
wrote:


> +  while (*cur != '\0') { + +  cur =
> skip_current_directories(cur); +   len =
> next_length(cur); +if (len > BTRFS_NAME_LEN) {
 next_length() promises @len <= BTRFS_NAME_LEN, so the check is
trivial.




Okay.

Hmm. This is a bug in next_length. I meant for next_length to
return len > BTRFS_NAME_LEN in case of too long name. Thanks for
noticing.


> +  ret = btrfs_readlink(root, ino, target); +
> if (ret < 0) { +free(target); +
> return ret; +  } + target[ret] = '\0';
 It was done in btrfs_readlink() already.


It is in old btrfs_readlink, but is it even after this patches?
I don't see it in the new implementation.



You are right. The thing changed in the 17th patch.
btrfs_readlink()
doesn't set the null byte now.

--
Su

> +
> +  ret = btrfs_lookup_path(root, ino, target, _root,
> +  _ino, _type,
> +  symlink_limit);

Just notify gentlely this is a recursive call here. I don't know
whether uboot cares about stack things. But, recursion makes coding simpler :).


It is limited by symlink_limit. Until somebody complains about stack
issues I would like to keep it simple.

Re: [PATCH 3/5] dt-bindings: leds: adopt Linux leds common binding constants

[Rtp]

Fwiw, it looks like that this file is already in uboot:

https://gitlab.denx.de/u-boot/u-boot/-/blob/master/include/dt-bindings/leds/common.h

commit 423aabc43613b58d7b91a28a94791ab937afcd90
Author: Jerome Brunet 
Date:   Thu Mar 5 12:12:35 2020 +0100

dt-bindings: leds: import common led bindings from linux v5.5

Import the common leds bindings definition from linux
d5226fa6dbae ("Linux 5.5")

Reviewed-by: Neil Armstrong 
Signed-off-by: Jerome Brunet 
Signed-off-by: Neil Armstrong 

Arnaud

RE: [PATCH V3 4/6] ram: stm32mp1: Add support for multiple configs

[Patrick DELAUNAY]

Hi,

> From: Marek Vasut 
> Sent: mercredi 22 avril 2020 13:18
> 
> Add support for multiple DRAM configuration subnodes, while retaining the
> support for a single flat DRAM configuration node. This is useful on systems
> which can be manufactured in multiple configurations and where the DRAM
> configuration can be determined at runtime.
> 
> The code is augmented by a function which can be overridden on board level,
> allowing a match on the configuration node name, very much like the fitImage
> configuration node name matching works. The default match is on the single 
> top-
> level DRAM configuration, if matching on subnodes is required, then this
> board_stm32mp1_ddr_config_name_match() must be overridden.
> 
> Signed-off-by: Marek Vasut 
> Cc: Manivannan Sadhasivam 
> Cc: Patrick Delaunay 
> Cc: Patrice Chotard 
> ---
> V2: Match on compatible string
> V3: Rework the stm32mp1_ddr_get_ofnode() function
> ---
>  drivers/ram/stm32mp1/stm32mp1_ram.c | 33 -
>  1 file changed, 28 insertions(+), 5 deletions(-)
> 

Reviewed-by: Patrick Delaunay 

Thanks

Patrick

Please pull NXP i.MX nxp-imx-20200422

[Peng Fan]

Hi Stefano,

Please pull this version nxp-imx-20200422, with patches sent out to ML.
Based on yours master branch.

CI: https://travis-ci.org/github/MrVan/u-boot/builds/678170004

Sorry for this late pull request.

---
SCFW API update, including seco/snvs
SNVS support for i.MX8
A53 clk fixes for i.MX8MQ
Speed grade updating
i.MX8M variants support
misc clk update
acquire ATF build info
---

Thanks,
Peng.

The following changes since commit d1bbf833aa7b45c00a42227b9563134643e44237:

  Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx 
(2020-04-20 08:45:27 -0400)

are available in the Git repository at:

  https://github.com/MrVan/u-boot.git tags/nxp-imx-20200422

for you to fetch changes up to 6734e085ed3b733d37a00b22b1e9bd2ec299cc45:

  imx8: Configure SNVS (2020-04-22 21:50:43 +0800)


Breno Lima (2):
  doc: ahab: Add encrypted boot documentation for i.MX8/8x devices
  imx8: scu api: Add support for SECO manufacturing protection APIs

Franck LENORMAND (1):
  imx8: Configure SNVS

Peng Fan (13):
  imx: fix cpu_type helper
  imx8mn: Update speed grade
  imx: cpu: support speed grade for i.MX8MP
  imx: imx8m: add i.MX8MQ Dual and QuadLite support
  imx: imx8m: add i.MX8MN variants support
  imx: update is_imx6ull to include i.MX6ULZ
  imx8: move SIP macro to common header
  imx8m: acquire ATF commit hash
  imx8m: update clock root and fix core_sel
  imx8mq: Set ARM core clock directly from ARM PLL
  imx8: parser: fix 'end address' parameter of rm_find_memreg
  imx8: ahab: fix 'end address' parameter of rm_find_memreg
  imx8: parser: fix some bad debug message formating

Seb Fagard (1):
  imx8: ahab: fix some bad debug message formating

Ye Li (7):
  imx8mm: Update CPU speed grading
  imx8mq: Enable eMMC HS400 and SD UHS mode on EVK
  imx8m: Dump DRAM PLL rate by clocks command
  imx8: Change to use new SECO API commands
  imx8mm: clock: fix fracpll decode issue
  imx8m: Enable WDOG_B for timeout
  imx8: Update SCFW API to version 1.5

 arch/arm/include/asm/arch-imx/cpu.h   |   7 +
 arch/arm/include/asm/arch-imx8/sci/rpc.h  |  86 +---
 arch/arm/include/asm/arch-imx8/sci/sci.h  |  10 ++
 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h  |   3 +
 arch/arm/include/asm/arch-imx8/sci/types.h|   6 +
 arch/arm/include/asm/arch-imx8/snvs_security_sc.h |  11 ++
 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h|   5 +-
 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h|   3 +-
 arch/arm/include/asm/mach-imx/sys_proto.h |  17 ++-
 arch/arm/mach-imx/cpu.c   |  38 -
 arch/arm/mach-imx/imx8/Kconfig|  13 ++
 arch/arm/mach-imx/imx8/Makefile   |   1 +
 arch/arm/mach-imx/imx8/ahab.c |  15 +-
 arch/arm/mach-imx/imx8/misc.c |   8 +-
 arch/arm/mach-imx/imx8/parse-container.c  |  18 +--
 arch/arm/mach-imx/imx8/snvs_security_sc.c | 923 
+
 arch/arm/mach-imx/imx8m/clock_imx8mm.c|  24 ++--
 arch/arm/mach-imx/imx8m/clock_imx8mq.c|  57 +---
 arch/arm/mach-imx/imx8m/clock_slice.c | 824 
+---
 arch/arm/mach-imx/imx8m/soc.c |  73 --
 board/freescale/imx8qxp_mek/imx8qxp_mek.c |  10 ++
 doc/imx/ahab/csf_examples/csf_enc_boot_image.txt  |  27 
 doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt   | 293 
+++
 drivers/misc/imx8/scu_api.c   | 194 
++
 include/imx_sip.h |   5 +-
 25 files changed, 2553 insertions(+), 118 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-imx8/snvs_security_sc.h
 create mode 100644 arch/arm/mach-imx/imx8/snvs_security_sc.c
 create mode 100644 doc/imx/ahab/csf_examples/csf_enc_boot_image.txt
 create mode 100644 doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt

Re: [PATCH] imx8: Run SPL with caches enabled

[Oliver Graute]

On 21/04/20, Fabio Estevam wrote:
> It is safe to run SPL with caches enabled on i.MX8, so
> remove such restriction.
> 
> Signed-off-by: Fabio Estevam 

Acked-by: Oliver Graute 

Re: [RFC PATCH 7/9] pci: Add some PCI Express capability register offset definitions

[Sylwester Nawrocki]

On 22.04.2020 08:16, Bin Meng wrote:
> On Wed, Apr 22, 2020 at 12:51 AM Sylwester Nawrocki
>  wrote:

>>  #define PCI_EXP_LNKCAP 12  /* Link Capabilities */
>> +#define  PCI_EXP_LNKCAP_SLS0x000f /* Supported Link Speeds */
>> +#define  PCI_EXP_LNKCAP_MLW0x03f0 /* Maximum Link Width */
>>  #define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
>> Active Reporting Capable */
>>
>>  #define PCI_EXP_LNKSTA 18  /* Link Status */
>> +#define  PCI_EXP_LNKSTA_CLS0x000f  /* Current Link Speed */
>> +#define  PCI_EXP_LNKSTA_NLW0x03f0  /* Negotiated Link Width */
>> +#define  PCI_EXP_LNKSTA_NLW_SHIFT 4/* start of NLW mask in link status 
>> */
>> +
>>  #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
>> +#define PCI_EXP_LNKCTL248  /* Link Control 2 */
> 
> Please put PCI_EXP_LNKCTL2 after PCI_EXP_SLTCAP (sorted in order)

Thanks for pointing this out, will be corrected in next iteration.

>>  #define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
>>  #define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */

--
Regards, 
Sylwester

Re: [RFC PATCH 6/9] usb: xhci: Allow accessing 64-bit registers with DWORD accesses only

[Sylwester Nawrocki]

Hi Bin,

On 22.04.2020 08:00, Bin Meng wrote:
> On Wed, Apr 22, 2020 at 12:51 AM Sylwester Nawrocki
>  wrote:
[...]
>> So far I couldn't come up with anything better to make the xHCI host
>> controller working on the rpi4 board. For some reason dereferencing
>> a 64-bit pointer to access 64-bit registers doesn't work there,
>> might be a limitation of the PCIe bridge behind the SCB. In Linux
>> always 2 double word accesses are used.
> 
> If Linux always uses 2 double word accesses, let's simply do the same
> in U-Boot by removing the readq/writeq.

Thanks for your review. That sounds good to me, I will do it that way
in next iteration.

--
Regards, 
Sylwester

[PATCH 24/24] imx8: Configure SNVS

[Peng Fan]

From: Franck LENORMAND 

Add a module to configure the tamper and secure violation of
the SNVS using the SCU API.

The module also adds some commands:
 - snvs_cfg: Configure the SNVS HP and LP registers
 - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP)
 - tamper_pin_cfg: Change the configuration of the tamper pins
 - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear
   status bits

Signed-off-by: Franck LENORMAND 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/arch-imx8/sci/sci.h  |   4 +
 arch/arm/include/asm/arch-imx8/snvs_security_sc.h |  11 +
 arch/arm/mach-imx/imx8/Kconfig|  13 +
 arch/arm/mach-imx/imx8/Makefile   |   1 +
 arch/arm/mach-imx/imx8/snvs_security_sc.c | 923 ++
 board/freescale/imx8qxp_mek/imx8qxp_mek.c |  10 +
 drivers/misc/imx8/scu_api.c   |  72 +-
 7 files changed, 1030 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-imx8/snvs_security_sc.h
 create mode 100644 arch/arm/mach-imx/imx8/snvs_security_sc.c

diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h 
b/arch/arm/include/asm/arch-imx8/sci/sci.h
index 179037ae17..05f736f14f 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -109,6 +109,7 @@ int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t 
resource,
 
 /* PAD API */
 int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
+int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
 
 /* SMMU API */
 int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
@@ -128,5 +129,8 @@ int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 
size, u8 lock);
 int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
 int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
+int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
+ u32 *data0, u32 *data1, u32 *data2, u32 *data3,
+ u32 *data4, u8 size);
 
 #endif
diff --git a/arch/arm/include/asm/arch-imx8/snvs_security_sc.h 
b/arch/arm/include/asm/arch-imx8/snvs_security_sc.h
new file mode 100644
index 00..0b7ded7ba6
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/snvs_security_sc.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _SNVS_SECURITY_SC_H
+#define _SNVS_SECURITY_SC_H
+
+int snvs_security_sc_init(void);
+
+#endif /* _SNVS_SECURITY_SC_H */
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 5827ab334f..1f8add015f 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -90,4 +90,17 @@ source "board/toradex/apalis-imx8/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
 source "board/siemens/capricorn/Kconfig"
 
+config IMX_SNVS_SEC_SC
+   bool "Support SNVS configuration"
+   help
+ Allow to configure the SNVS via SCU API to configure tampers and 
secure
+ violation.
+
+config IMX_SNVS_SEC_SC_AUTO
+   bool "Support SNVS configuration command"
+   depends on IMX_SNVS_SEC_SC
+   help
+ This configuration will apply the selected configurations 
automatically
+ at boot.
+
 endif
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
index 7ffb7e95b2..bbb41adbe4 100644
--- a/arch/arm/mach-imx/imx8/Makefile
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_AHAB_BOOT) += ahab.o
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o
 endif
+obj-$(CONFIG_IMX_SNVS_SEC_SC) += snvs_security_sc.o
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c 
b/arch/arm/mach-imx/imx8/snvs_security_sc.c
new file mode 100644
index 00..73f5651161
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c
@@ -0,0 +1,923 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2020 NXP.
+ */
+
+/*
+ * Configuration of the Tamper pins in different mode:
+ *  - default (no tamper pins): _default_
+ *  - passive mode expecting VCC on the line: "_passive_vcc_"
+ *  - passive mode expecting VCC on the line: "_passive_gnd_"
+ *  - active mode: "_active_"
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Access to gd */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SC_WRITE_CONF 1
+
+#define PGD_HEX_VALUE 0x41736166
+#define SRTC_EN 0x1
+#define DP_EN BIT(5)
+
+struct snvs_security_sc_conf {
+   struct snvs_hp_conf {
+   u32 lock;   /* HPLR - HP Lock */
+   u32 __cmd;  /* HPCOMR - HP Command */
+   u32 __ctl;  /* HPCR - HP Control */
+   u32 secvio_intcfg;  /* HPSICR - Security Violation Int
+* Config
+*/
+ 

[PATCH 22/24] imx8: scu api: Add support for SECO manufacturing protection APIs

[Peng Fan]

From: Breno Lima 

SECO provides APIs to support CAAM manufacturing protection:

- sc_seco_get_mp_key()
- sc_seco_get_mp_sign()
- sc_seco_update_mpmr()

Add SCFW APIs support.

Signed-off-by: Breno Lima 
Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/arch-imx8/sci/sci.h |  4 ++
 drivers/misc/imx8/scu_api.c  | 80 
 2 files changed, 84 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h 
b/arch/arm/include/asm/arch-imx8/sci/sci.h
index 14ee6f999b..ac65f199b8 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -122,5 +122,9 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 
*commit);
 int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
 int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
 sc_faddr_t export_addr, u16 max_size);
+int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
+int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
+int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
+   u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
 
 #endif
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index 3ad21c1ea0..c1e54fc4bc 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -948,3 +948,83 @@ int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t 
load_addr,
 
return ret;
 }
+
+int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr,
+   u16 dst_size)
+{
+   struct udevice *dev = gd->arch.scu_dev;
+   struct sc_rpc_msg_s msg;
+   int size = sizeof(struct sc_rpc_msg_s);
+   int ret;
+
+   RPC_VER() = SC_RPC_VERSION;
+   RPC_SIZE() = 4U;
+   RPC_SVC() = (u8)(SC_RPC_SVC_SECO);
+   RPC_FUNC() = (u8)(SECO_FUNC_GET_MP_KEY);
+
+   RPC_U32(, 0U) = (u32)(dst_addr >> 32ULL);
+   RPC_U32(, 4U) = (u32)(dst_addr);
+   RPC_U16(, 8U) = (u16)(dst_size);
+
+   ret = misc_call(dev, SC_FALSE, , size, , size);
+   if (ret)
+   printf("%s, dst_addr:0x%llx, res:%d\n",
+  __func__, dst_addr, RPC_R8());
+
+   return ret;
+}
+
+int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, uint8_t size_m,
+   uint8_t lock)
+{
+   struct udevice *dev = gd->arch.scu_dev;
+   struct sc_rpc_msg_s msg;
+   int size = sizeof(struct sc_rpc_msg_s);
+   int ret;
+
+   RPC_VER() = SC_RPC_VERSION;
+   RPC_SIZE() = 4U;
+   RPC_SVC() = (u8)(SC_RPC_SVC_SECO);
+   RPC_FUNC() = (u8)(SECO_FUNC_UPDATE_MPMR);
+
+   RPC_U32(, 0U) = (u32)(addr >> 32ULL);
+   RPC_U32(, 4U) = (u32)(addr);
+   RPC_U8(, 8U) = (u8)(size_m);
+   RPC_U8(, 9U) = (u8)(lock);
+
+   ret = misc_call(dev, SC_FALSE, , size, , size);
+   if (ret)
+   printf("%s, addr:0x%llx, size_m:%x, lock:0x%x, res:%d\n",
+  __func__, addr, size_m, lock, RPC_R8());
+   return ret;
+}
+
+int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
+   u16 msg_size, sc_faddr_t dst_addr,
+   u16 dst_size)
+{
+   struct udevice *dev = gd->arch.scu_dev;
+   struct sc_rpc_msg_s msg;
+   int size = sizeof(struct sc_rpc_msg_s);
+   int ret;
+
+   RPC_VER() = SC_RPC_VERSION;
+   RPC_SIZE() = 6U;
+   RPC_SVC() = (u8)(SC_RPC_SVC_SECO);
+   RPC_FUNC() = (u8)(SECO_FUNC_GET_MP_SIGN);
+
+   RPC_U32(, 0U) = (u32)(msg_addr >> 32ULL);
+   RPC_U32(, 4U) = (u32)(msg_addr);
+   RPC_U32(, 8U) = (u32)(dst_addr >> 32ULL);
+   RPC_U32(, 12U) = (u32)(dst_addr);
+   RPC_U16(, 16U) = (u16)(msg_size);
+   RPC_U16(, 18U) = (u16)(dst_size);
+
+   ret = misc_call(dev, SC_FALSE, , size, , size);
+   if (ret)
+   printf("%s, msg_addr:0x%llx, msg_size:%x, dst_addr:0x%llx,"
+  "dst_size:%x, res:%d\n", __func__, msg_addr, msg_size,
+  dst_addr, dst_size, RPC_R8());
+
+   return ret;
+}
-- 
2.16.4