Re: [PATCH] spi: renesas: Make driver available on R-Car Gen4

[Geert Uytterhoeven]

On Tue, Feb 28, 2023 at 10:28 PM Marek Vasut
 wrote:
> Use CONFIG_RCAR_64 to make the driver available on both
> R-Car Gen3 and R-Car Gen4.
>
> Signed-off-by: Marek Vasut 

LGTM, so
Reviewed-by: Geert Uytterhoeven 

> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -381,7 +381,7 @@ config SPI_QUP
>
>  config RENESAS_RPC_SPI
> bool "Renesas RPC SPI driver"
> -   depends on RCAR_GEN3 || RZA1
> +   depends on RCAR_64 || RZA1

Note that the RPC-IF is also present on the RZ/G2L SoC family
(RZ/G2L{,}, RZ/G2UL, RZ/Five), which does not seem to have upstream
U-Boot support yet.

> imply SPI_FLASH_BAR
> help
>   Enable the Renesas RPC SPI driver, used to access SPI NOR flash

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 1/2] spi: spi-mem: s/dummy/data buswidth check in dtr_supports_op()

[Nikhil M Jain]

From: Dhruva Gole 

This should have been op->data.buswidth instead as we check for octal
bus width for the data related ops
Also add explanation for why there is checks for 8D even data bytes

Cc: Pratyush Yadav 
Reviewed-by: Pratyush Yadav 
Tested-by: Nikhil M Jain 
Signed-off-by: Dhruva Gole 
---

This patch has no changes wrt previously sent patch:
https://lore.kernel.org/u-boot/20230220054231.74367-1-d-g...@ti.com/

 drivers/spi/spi-mem.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 8e8995fc53..57a36f31a5 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -181,8 +181,12 @@ bool spi_mem_dtr_supports_op(struct spi_slave *slave,
if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2)
return false;
 
+   /*
+* Transactions of odd length do not make sense for 8D-8D-8D mode
+* because a byte is transferred in just half a cycle.
+*/
if (op->data.dir != SPI_MEM_NO_DATA &&
-   op->dummy.buswidth == 8 && op->data.nbytes % 2)
+   op->data.buswidth == 8 && op->data.nbytes % 2)
return false;
 
return spi_mem_check_buswidth(slave, op);
-- 
2.34.1

[PATCH 2/2] spi: spi-mem: perform odd len check only while writing data

[Nikhil M Jain]

From: Dhruva Gole 

in spi_mem_dtr_supports_op we have a check for allowing only even number
of bytes to be r/w. Odd bytes writing can be a concern while writing
data to a flash for example because 8 DTR mode doesn't support it.
However, reading ODD Bytes even  though may not be physically possible
we can still allow for it because it will not have serious implications
on any critical registers being overwritten since they are just reads.

Cc: Vaishnav Achath 
Cc: Pratyush Yadav 
Cc: Vignesh Raghavendra 
Tested-by: Nikhil M Jain 
Signed-off-by: Dhruva Gole 
---
 drivers/spi/spi-mem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 57a36f31a5..b7eca58359 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -185,7 +185,7 @@ bool spi_mem_dtr_supports_op(struct spi_slave *slave,
 * Transactions of odd length do not make sense for 8D-8D-8D mode
 * because a byte is transferred in just half a cycle.
 */
-   if (op->data.dir != SPI_MEM_NO_DATA &&
+   if (op->data.dir != SPI_MEM_NO_DATA && op->data.dir != SPI_MEM_DATA_IN 
&&
op->data.buswidth == 8 && op->data.nbytes % 2)
return false;
 
-- 
2.34.1

[PATCH 0/2] spi: spi-mem: odd byte condition changes in dtr_supports_op

[Nikhil M Jain]

From: Dhruva Gole 

Currently if one tries to read an odd filesize from a flash in OSPI DTR
Mode then the transaction just straightaway returns failure without even
attempting a read.

Base on comments from a series a while back:
https://lore.kernel.org/u-boot/20221025062036.383460-1-d-g...@ti.com/

where Pratyush highlights the risk of on writes an extra byte goes to the
flash. Hence this series makes sure that we perform this ODD Byte check
only if the transactions are "non-read" related ie. only write related.

An alternative solution was suggested here:
https://patchwork.ozlabs.org/project/linux-mtd/patch/20210531181757.19458-6-p.ya...@ti.com/

However the code is in linux kernel where it's a full fledge OS running
with presumambly enough DDR RAM and we dont really have memory
contraints as tight as in a bootloader. The part where the above
solution does

...
tmp_buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
...

This is something we do not have the luxury of doing at bootloader stage
where the RAM is very limited. In TI K3 AM625 SOC's case we have the
same code running on R5 SPL Stage where memory is extremely limited and
we can't really afford to allocate some at runtime as and when we want.

These patches have been tested on AM625 SK EVM platform and check for
odd and even byte reads, updates and also full bootup from OSPI Flash
till U-Boot prompt:

...
U-Boot SPL 2023.04-rc2-00040-gbe9fd01af6 (Mar 01 2023 - 11:30:52 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.5.3--v08.05.03 (Chill Capybar')
Trying to boot from SPI
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.7(release):v2.7.0-359-g1309c6c805-dirty
NOTICE:  BL31: Built : 11:48:12, Dec 14 2022
I/TC:
I/TC: OP-TEE version: 3.19.0-15-gd6c5d0037 (gcc version 9.2.1 20191025 (GNU 
Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Wed Dec 14 
11:52:03 UTC 2022 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check 
https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.5.3--v08.05.03 (Chill Capybar')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2023.04-rc2-00040-gbe9fd01af6 (Mar 01 2023 - 11:31:30 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.5.3--v08.05.03 (Chill Capybar')
Trying to boot from SPI


U-Boot 2023.04-rc2-00040-gbe9fd01af6 (Mar 01 2023 - 11:31:30 +0530)

SoC:   AM62X SR1.0 GP
Model: Texas Instruments AM625 SK
DRAM:  2 GiB
Core:  50 devices, 20 uclasses, devicetree: separate
MMC:   mmc@fa1: 0, mmc@fa0: 1, mmc@fa2: 2
Loading Environment from nowhere... OK
In:serial@280
Out:   serial@280
Err:   serial@280
Net:   eth0: ethernet@800port@1
Hit any key to stop autoboot:  0
=>
...

Odd length reads:
...
=> sf probe
SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 
MiB
=> fatload mmc 1 $loadaddr ti.gz
12285 bytes read in 8 ms (1.5 MiB/s)
=> sf update $loadaddr 0x70 $filesize
device 0 offset 0x70, size 0x2ffd
12285 bytes written, 0 bytes skipped in 1.478s, speed 8494 B/s
sf read 0x9000 0x70 $filesize
device 0 offset 0x70, size 0x2ffd
SF: 12285 bytes @ 0x70 Read: OK
=> cmp.b $loadaddr 0x9000 $filesize
# all bytes were same #
...

Cc: Vignesh Raghavendra 
Cc: Pratyush Yadav 
Cc: Vaishnav Achath 
Cc: Nikhil M Jain 

Dhruva Gole (2):
  spi: spi-mem: s/dummy/data buswidth check in dtr_supports_op()
  spi: spi-mem: perform odd len check only while writing data

 drivers/spi/spi-mem.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

-- 
2.39.2

Re: [PATCH RFC u-boot-mvebu 00/59] arm: mvebu: Various fixes

[Stefan Roese]

Hi Pali,

On 2/28/23 23:41, Pali Rohár wrote:




So my question is, why are less patches in your github branch? Or did
you try to re-send with this smaller amount of patches and this did not
work because of the crashing mail server?


I cannot understand how it is possible. There should be 59 patches. I
have not created / sent more patches. If there is missing some patch on
Github I can double check it...


Most likely I have fat-fingered myself something here. Please forget
about this. My fault.


Ok. So do you have all patches in the correct form?


Yes. All fine.

Thanks,
Stefan


Thanks,
Stefan




Thanks,
Stefan




Thanks,
Stefan



> Thanks,
> Stefan
>
> >
> > >
> > > Pali Rohár (59):
> > >    tools: kwbimage: Fix generating, verifying and extracting SDIO
> > >      kwbimage
> > >    tools: kwboot: Fix parsing SDIO kwbimage
> > >    arm: mvebu: spl: Fix parsing SDIO kwbimage
> > >    cmd: mvebu/bubt: Fix parsing SDIO kwbimage
> > >    tools: kwbimage: Fix generating, verifying and extracting SATA
> > >      kwbimage
> > >    tools: kwboot: Fix parsing SATA kwbimage
> > >    arm: mvebu: spl: Fix parsing SATA kwbimage
> > >    cmd: mvebu/bubt: Fix parsing SATA kwbimage
> > >    arm: mvebu: spl: Remove checks for BOOT_DEVICE_MMC2 and
> > >      BOOT_DEVICE_MMC2_2
> > >    arm: mvebu: spl: Load proper U-Boot from selected eMMC
   boot partition
> > >    spl: mmc: Allow to disable SYS_MMCSD_FS_BOOT_PARTITION
> > >    arm: mvebu: spl: Fix support for loading U-Boot proper
   from SD card
> > >    tools: kwboot: Add more documentation references
> > >    tools: kwboot: Add image type documentation
> > >    tools: kwboot: Fix parsing UART image without data checksum
> > >    tools: kwboot: Validate optional kwbimage v1 headers
> > >    tools: kwboot: Add check that kwbimage contains DDR init code
> > >    tools: kwboot: Fix patching of SPI/NOR XIP images
> > >    tools: kwboot: Show image type and error parsing reasons
> > >    cmd: mvebu/bubt: Add support for selecting eMMC HW partition
> > >    cmd: mvebu/bubt: Add support for writing image to SATA disk
> > >    cmd: mvebu/bubt: Add support for reading image from the
   SATA disk
> > >      partition
> > >    cmd: mvebu/bubt: Rename variable image_size to hdr_size
> > >    cmd: mvebu/bubt: Mark all local symbols as static
> > >    cmd: mvebu/bubt: Do not modify image in A8K
   check_image_header()
> > >    cmd: mvebu/bubt: Check also A8K boot image checksum
> > >    cmd: mvebu/bubt: Set correct default image name for 32-bit
   Armada SoCs
> > >    cmd: mvebu/bubt: Better guess default MVEBU_*_BOOT option
> > >    cmd: mvebu/bubt: Fix warnings: unused variable
   'secure_mode' and
> > >      'fuse_read_u64' defined but not used
> > >    cmd: mvebu/bubt: Enable command by default
> > >    tools: kwbimage: Fix dumping register set / DATA commands
> > >    tools: kwbimage: Fix endianity when dumping NAND_PAGE_SIZE
> > >    tools: kwbimage: Fix dumping NAND_BADBLK_LOCATION
> > >    tools: kwbimage: Fix dumping NAND_BLKSZ
> > >    tools: kwbimage: Fix generating of kwbimage v0 header checksum
> > >    tools: kwbimage: Fix endianity when printing kwbimage header
> > >    tools: kwbimage: Reject mkimage -F option
> > >    tools: kwbimage: Add support for dumping NAND_BLKSZ for v0
   images
> > >    tools: kwbimage: Print binary image offset as size
> > >    tools: kwbimage: Print image data offset when printing
   kwbimage header
> > >    tools: kwbimage: Simplify add_secure_header_v1()
> > >    tools: kwbimage: Rename imagesz to dataoff
> > >    tools: kwbimage: Fix generating secure boot data image
   signature
> > >    tools: kwbimage: Fix invalid secure boot header signature
> > >    tools: mkimage: Do not fill legacy_img_hdr for non-legacy
   XIP images
> > >    tools: kwbimage: Add support for XIP SPI/NOR images
> > >    tools: mkimage: Print human readable error when -d is not
   specified
> > >    tools: mkimage: Do not try to open datafile when it is skipped
> > >    tools: kwbimage: Add support for creating an image with no
   data
> > >    arm: mvebu: Add support for generating NAND kwbimage
> > >    arm: mvebu: Add support for generating PEX kwbimage
> > >    arm: mvebu: Fix description of
   MVEBU_SPL_BOOT_DEVICE_(SPI|MMC) options
> > >    arm: mvebu: db-88f6820-amc: Add defconfig for NAND booting
> > >    arm: mvebu: clearfog: Add defconfig for SATA booting
> > >    arm: mvebu: 

Re: [PATCH] i2c: rcar_i2c: Add R-Car Gen4 support

[Heiko Schocher]

Hello Marek,

On 28.02.23 22:25, Marek Vasut wrote:
> From: Hai Pham 
> 
> Add support for R-Car Gen4 SoCs into the driver.
> 
> While I2C on R-Car Gen4 does support some extra features (Slave Clock
> Stretch Select), for now it is treated the same as I2C on R-Car Gen3,
> which let us share the same driver.
> 
> Reviewed-by: Marek Vasut 
> Signed-off-by: Hai Pham 
> Signed-off-by: Marek Vasut  # Use RCAR_64 
> Kconfig
> ---
> Cc: Heiko Schocher 
> ---
>  drivers/i2c/Kconfig| 2 +-
>  drivers/i2c/rcar_i2c.c | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Heiko Schocher 

bye,
Heiko
-- 
DENX Software Engineering GmbH,  Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH 2/2] i2c: rcar_i2c: Sort Kconfig depends list ascending

[Heiko Schocher]

Hello Marek,

On 28.02.23 00:03, Marek Vasut wrote:
> Sort the list of "depends" symbols in ascending order.
> No functional change.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Heiko Schocher 
> ---
>  drivers/i2c/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Heiko Schocher 

bye,
Heiko
-- 
DENX Software Engineering GmbH,  Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

Re: [PATCH 1/2] i2c: rcar_iic: Sort Kconfig depends list ascending

[Heiko Schocher]

Hello Marek,

On 28.02.23 00:03, Marek Vasut wrote:
> Sort the list of "depends" symbols in ascending order.
> No functional change.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Heiko Schocher 
> ---
>  drivers/i2c/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Heiko Schocher 

bye,
Heiko
-- 
DENX Software Engineering GmbH,  Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

[PATCH] usb: dwc3: core: improve reset sequence

[Venkatesh Yadav Abbarapu]

[ Felipe: Ported from Linux kernel commit
  f59dcab17629 ("usb: dwc3: core: improve reset sequence") ]

According to Synopsys Databook, we shouldn't be
relying on GCTL.CORESOFTRESET bit as that's only for
debugging purposes. Instead, let's use DCTL.CSFTRST
if we're OTG or PERIPHERAL mode.

Host side block will be reset by XHCI driver if
necessary. Note that this reduces amount of time
spent on dwc3_probe() by a long margin.

We're still gonna wait for reset to finish for a
long time (default to 1ms max), but tests show that
the reset polling loop executed at most 19 times
(modprobe dwc3 && modprobe -r dwc3 executed 1000
times in a row).

Without proper core reset, observing random issues like when the USB(DWC3)
is in device mode, the host device is not able to detect the USB device.

Signed-off-by: Venkatesh Yadav Abbarapu 
---
 drivers/usb/dwc3/core.c | 49 +++--
 1 file changed, 18 insertions(+), 31 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 49f6a1900b..6cd0ad4746 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -60,42 +60,29 @@ static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 {
u32 reg;
+   int retries = 1000;
 
-   /* Before Resetting PHY, put Core in Reset */
-   reg = dwc3_readl(dwc->regs, DWC3_GCTL);
-   reg |= DWC3_GCTL_CORESOFTRESET;
-   dwc3_writel(dwc->regs, DWC3_GCTL, reg);
-
-   /* Assert USB3 PHY reset */
-   reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
-   reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
-   dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
-
-   /* Assert USB2 PHY reset */
-   reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-   reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
-   dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
-
-   mdelay(100);
-
-   /* Clear USB3 PHY reset */
-   reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
-   reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
-   dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+   /*
+* We're resetting only the device side because, if we're in host mode,
+* XHCI driver will reset the host block. If dwc3 was configured for
+* host-only mode, then we can return early.
+*/
+   if (dwc->dr_mode == USB_DR_MODE_HOST)
+   return 0;
 
-   /* Clear USB2 PHY reset */
-   reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-   reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
-   dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+   reg = dwc3_readl(dwc->regs, DWC3_DCTL);
+   reg |= DWC3_DCTL_CSFTRST;
+   dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 
-   mdelay(100);
+   do {
+   reg = dwc3_readl(dwc->regs, DWC3_DCTL);
+   if (!(reg & DWC3_DCTL_CSFTRST))
+   return 0;
 
-   /* After PHYs are stable we can take Core out of reset state */
-   reg = dwc3_readl(dwc->regs, DWC3_GCTL);
-   reg &= ~DWC3_GCTL_CORESOFTRESET;
-   dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+   udelay(1);
+   } while (--retries);
 
-   return 0;
+   return -ETIMEDOUT;
 }
 
 /*
-- 
2.17.1

[PATCH 3/3] test: Run the VPL tests with 'make check'

[Simon Glass]

Update the script to run VPL tests as well as the others.

Signed-off-by: Simon Glass 
---

 test/run | 5 +
 1 file changed, 5 insertions(+)

diff --git a/test/run b/test/run
index c4ab046ce8f..9e94ae23fb7 100755
--- a/test/run
+++ b/test/run
@@ -56,6 +56,11 @@ echo "${prompt}"
 run_test "sandbox_noinst" ./test/py/test.py --bd sandbox_noinst --build 
${para} \
-k 'test_ofplatdata or test_handoff or test_spl'
 
+# Run tests which require sandbox_vpl
+echo "${prompt}"
+run_test "sandbox_vpl" ./test/py/test.py --bd sandbox_vpl --build ${para} \
+   -k 'vpl or test_spl'
+
 if [ -z "$tools_only" ]; then
# Run tests for the flat-device-tree version of sandbox. This is a 
special
# build which does not enable CONFIG_OF_LIVE for the live device tree, 
so we can
-- 
2.39.2.722.g9855ee24e9-goog

[PATCH 2/3] CI: Ensure that vpl test is run

[Simon Glass]

This is actually skipped at present due to the condition in the file.
Fix this by running all vpl tests.

Signed-off-by: Simon Glass 
---

 .azure-pipelines.yml | 2 +-
 .gitlab-ci.yml   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 30025ff7517..3e213de4f41 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -253,7 +253,7 @@ stages:
   TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
 sandbox_vpl:
   TEST_PY_BD: "sandbox_vpl"
-  TEST_PY_TEST_SPEC: "test_vpl_help or test_spl"
+  TEST_PY_TEST_SPEC: "vpl or test_spl"
 sandbox_noinst:
   TEST_PY_BD: "sandbox_noinst"
   TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e320a24ef31..6eccff86b09 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -284,7 +284,7 @@ sandbox_noinst_test.py:
 sandbox_vpl test.py:
   variables:
 TEST_PY_BD: "sandbox_vpl"
-TEST_PY_TEST_SPEC: "test_vpl_help or test_spl"
+TEST_PY_TEST_SPEC: "vpl or test_spl"
   <<: *buildman_and_testpy_dfn
 
 # Enable tracing and disable LTO, to ensure functions are not elided
-- 
2.39.2.722.g9855ee24e9-goog

[PATCH 1/3] vbe: Use the correct image filename in the test

[Simon Glass]

At present this inadvertently relies on having a symlink to the correct
file from the current directory. Use the correct path to fix this.

Signed-off-by: Simon Glass 
---

 test/py/tests/test_vbe_vpl.py | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/test/py/tests/test_vbe_vpl.py b/test/py/tests/test_vbe_vpl.py
index d1c9d0548ae..ed12d3a4618 100644
--- a/test/py/tests/test_vbe_vpl.py
+++ b/test/py/tests/test_vbe_vpl.py
@@ -15,6 +15,7 @@ def test_vbe_vpl(u_boot_console):
 #cmd = [cons.config.build_dir + fname, '-v']
 ram = os.path.join(cons.config.build_dir, 'ram.bin')
 fdt = os.path.join(cons.config.build_dir, 'arch/sandbox/dts/test.dtb')
+image_fname = os.path.join(cons.config.build_dir, 'image.bin')
 
 # Enable firmware1 and the mmc that it uses. These are needed for the full
 # VBE flow.
@@ -24,12 +25,13 @@ def test_vbe_vpl(u_boot_console):
 cons, f'fdtput -t s {fdt} /bootstd/firmware1 status okay')
 u_boot_utils.run_and_log(
 cons, f'fdtput -t s {fdt} /mmc3 status okay')
+u_boot_utils.run_and_log(
+cons, f'fdtput -t s {fdt} /mmc3 filename {image_fname}')
 
 # Remove any existing RAM file, so we don't have old data present
 if os.path.exists(ram):
 os.remove(ram)
-flags = ['-p', os.path.join(cons.config.build_dir, 'image.bin'), '-w',
- '-s', 'state.dtb']
+flags = ['-p', image_fname, '-w', '-s', 'state.dtb']
 cons.restart_uboot_with_flags(flags)
 
 # Make sure that VBE was used in both VPL (to load SPL) and SPL (to load
-- 
2.39.2.722.g9855ee24e9-goog

[PATCH 0/3] vpl: Correct some tests

[Simon Glass]

It was reported that one of the VPL tests does not work. The problem
turned out to be a leftover symlink that I had which made things work
locally. This was not noticed in CI since the tests did not run there
either.

This little series fixes these problems.


Simon Glass (3):
  vbe: Use the correct image filename in the test
  CI: Ensure that vpl test is run
  test: Run the VPL tests with 'make check'

 .azure-pipelines.yml  | 2 +-
 .gitlab-ci.yml| 2 +-
 test/py/tests/test_vbe_vpl.py | 6 --
 test/run  | 5 +
 4 files changed, 11 insertions(+), 4 deletions(-)

-- 
2.39.2.722.g9855ee24e9-goog

Re: [PATCH 2/2] arm: mvebu: clearfog: Add defconfig for SPI booting

[Tony Dinh]

Hi Pali,

On Tue, Feb 28, 2023 at 2:19 PM Pali Rohár  wrote:
>
> On Tuesday 28 February 2023 13:51:24 Tony Dinh wrote:
> > Hi Pali,
> >
> > On Tue, Feb 28, 2023 at 10:52 AM Pali Rohár  wrote:
> > >
> > > On Tuesday 28 February 2023 10:48:24 Pali Rohár wrote:
> > > > On Monday 27 February 2023 17:17:31 Tony Dinh wrote:
> > > > > Hi Pali,
> > > > >
> > > > > On Mon, Feb 27, 2023 at 4:42 PM Tony Dinh  wrote:
> > > > > >
> > > > > > Hi Pali,
> > > > > >
> > > > > > On Mon, Feb 27, 2023 at 3:41 PM Tony Dinh  wrote:
> > > > > > >
> > > > > > > Hi Pali,
> > > > > > > It is not related to this patch series (I also tested without the
> > > > > > > patch series to confirm). But it is strange that I can no longer 
> > > > > > > get
> > > > > > > the configuration to boot from SPI. The 1st device in the boot 
> > > > > > > order
> > > > > > > is alway BOOTROM. The spl_boot_list is printed out below.
> > > > > > >
> > > > > > > 
> > > > > > > High speed PHY - Ended Successfully
> > > > > > > mv_ddr: 14.0.0
> > > > > > > DDR4 Training Sequence - Switching XBAR Window to FastPath Window
> > > > > > > mv_ddr: completed successfully
> > > > > > > board_boot_order spl_boot_list[0] = 15
> > > > > > > Trying to boot from BOOTROM
> > > > > > > Returning to BootROM (return address 0x05c4)...
> > > > > > > BootROM: Image checksum verification PASSED
> > > > > > > 
> > > > > > >
> > > > > > > The SPL SPI configs (board Thecus N2350) are:
> > > > > > > # grep SPL .config| grep SPI
> > > > > > >
> > > > > > > CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI=y
> > > > > > > CONFIG_SPL_DM_SPI=y
> > > > > > > CONFIG_SPL_SPI_FLASH_SUPPORT=y
> > > > > > > CONFIG_SPL_SPI=y
> > > > > > > CONFIG_SPL_DM_SPI_FLASH=y
> > > > > > > CONFIG_SPL_SPI_FLASH_TINY=y
> > > > > > > # CONFIG_SPL_SPI_FLASH_MTD is not set
> > > > > > > CONFIG_SPL_SPI_LOAD=y
> > > > > > >
> > > > > > > Did I miss something new lately?
> > > > > > >
> > > > > > > Thanks,
> > > > > > > Tony
> > > > > > >
> > > > > > > Trying to boot from BOOTROM
> > > > > > > Returning to BootROM (return address 0x05c4)...
> > > > > > > BootROM: Image checksum verification PASSED
> > > > > >
> > > > > > It turns out that the board strapping register itself is the 
> > > > > > problem.
> > > > > > boot_device=0x9 was printed out in arch/arm/mach-mvebu/cpu.c. It
> > > > > > surely does not match what we expected for A38x  (#define
> > > > > > BOOT_FROM_SPI 0x32). Actually 0x9 is not defined in cpu.c at all. So
> > > > > > it fell to the default case, which is BOOTROM.
> > > > > >
> > > > > > 
> > > > > > U-Boot SPL 2023.04-rc2-tld-1-00089-g3fe03f96fc-dirty (Feb 27 2023 -
> > > > > > 16:24:01 -0800)
> > > > > > High speed PHY - Version: 2.0
> > > > > > Detected Device ID 6820
> > > > > > board SerDes lanes topology details:
> > > > > >  | Lane # | Speed |  Type   |
> > > > > >  
> > > > > >  |   0|   0   | SGMII0 |
> > > > > >  |   1|   3   | SATA0 |
> > > > > >  |   2|   3   | SATA1 |
> > > > > >  |   4|   5   | USB3 HOST0 |
> > > > > >  |   5|   5   | USB3 HOST1 |
> > > > > >  
> > > > > > High speed PHY - Ended Successfully
> > > > > > mv_ddr: 14.0.0
> > > > > > DDR4 Training Sequence - Switching XBAR Window to FastPath Window
> > > > > > mv_ddr: completed successfully
> > > > > > BOOTROM_REG=0x97001000 boot_device=0x9
> > >
> > > Wait...
> > >
> > > Stop here. BOOTROM_REG is the value of BOOTROM_ERR_REG register which is
> > > mvebu register 0x182d0.
> > >
> > > Boot strapping pins are available in the SAR_REG register which is mvebu
> > > register 0x18600 and SPL prints it under name SAR_REG.
> >
> > Ah, I see. Thanks Pali. I've jumped the gun too soon after seeing the
> > 1st boot_device debug statement! Please see below.
>
> Perfect!
>
> > >
> > > So above boot_device=9 is not strapping pin configuration but something
> > > parsed from BOOTROM_ERR_REG.
> > >
> > > So above 0x9 signal some A385 bootrom error and SPL in case case of any
> > > error (value different from zero) always use bootrom for loading proper
> > > u-boot. As it thinks that bootrom loaded u-boot via uart. Seems that
> > > this assumption is incorrect.
> > >
> > > Unfortunately upper four bits which above code parses from mvebu
> > > register 0x182d0 are marked as reserved in functional specification.
> > >
> > > So it is needed to inspect bootrom binary when it sets these bits...
> >
> > I think I understand the problem now. The strapping is for Spi 1,
> > which is 0x34, but it has not been defined in u-boot yet. We have only
> > Spi 0 defined in the code, which is 0x32.
> >
> > A38x Hardware Specs
> > 0x34
> > BootROM Enabled, Boot from SPI: Controller #1, 24 address bits, NOR
> > Flash type, using MPP multiplexing option of SPI on MPP[59:56]
> >
> > /arch/arm/mach-mvebu/include/mach/soc.h
> > #define BOOT_FROM_SPI 0x32
> >
> > Here is the boot log. This time I have the SAR_REG printed out.
>
> Ok, this looks correct. BootROM prints that 

RE: [PATCH] README.mpc85xx-sd-spi-boot: Suggest the NXP boot format github repo

[Leo Li]

> -Original Message-
> From: Pali Rohár 
> Sent: Tuesday, February 28, 2023 9:32 AM
> To: Leo Li 
> Cc: Fabio Estevam ; Priyanka Jain
> ; Fabio Estevam ;
> ka...@kernel.org; u-boot@lists.denx.de
> Subject: Re: [PATCH] README.mpc85xx-sd-spi-boot: Suggest the NXP boot
> format github repo
> 
> On Friday 13 January 2023 09:10:18 Fabio Estevam wrote:
> > On Fri, Jan 13, 2023 at 4:53 AM Pali Rohár  wrote:
> >
> > > >  you can browse it online at:
> > > > -https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2
> > > > Fsource.codeaurora.org%2Fexternal%2Fqoriq%2Fqoriq-yocto-
> sdk%2Fboot
> > > > -
> format=05%7C01%7Cleoyang.li%40nxp.com%7C664a99443c3b4bc3f80d
> > > >
> 08db19a0febf%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638131
> 95
> > > >
> 1494370943%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIj
> oiV2l
> > > >
> uMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C=0Pcm
> Yxsc
> > > > yUY%2FuvgaxrchWlBlaVezU8nwO1C7%2FFYQr9U%3D=0
> > > > +https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2
> > > > +Fgithub.com%2Fnxp-qoriq-yocto-sdk%2Fboot-
> format=05%7C01%7Cle
> > > >
> +oyang.li%40nxp.com%7C664a99443c3b4bc3f80d08db19a0febf%7C686ea1d3
> b
> > > >
> +c2b4c6fa92cd99c5c301635%7C0%7C0%7C638131951494527177%7CUnknown
> %7C
> > > >
> +TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> L
> > > >
> +CJXVCI6Mn0%3D%7C3000%7C%7C%7C=tM%2BXzNN03DeMVcQL8jc
> 2a1nBvsz
> > > > +31bHC%2FrKGV7rKGaY%3D=0
> > >
> > > This "new" repo contains old broken version of boot-format which is
> > > missing important commits and fixes.
> >
> > Priyanka, can anyone at NXP fix this?
> 
> Leo Li, could you look at NXP boot-format github repository and import latest
> version from codeaurora? I see that github repository is missing more
> commits which are on codeaurora.

Looks like the master branch on codeaurora was not migrated to github.  Let me 
talk with the related people on this.

Regards,
Leo

Re: [PATCH 5/7] imx8image: Remove unused cont_img_count variable

[Peng Fan]

On 2/28/2023 6:08 AM, Tom Rini wrote:

With clang-15, it is now reported that cont_img_count is unused. This is
true as the code will increment / reset this counter, but never
functionally use it. Remove it.

Signed-off-by: Tom Rini 


Reviewed-by: Peng Fan 


---
Cc: Peng Fan 
Cc: Mikhail Ilin 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: "NXP i.MX U-Boot Team" 
---
  tools/imx8image.c | 5 -
  1 file changed, 5 deletions(-)

diff --git a/tools/imx8image.c b/tools/imx8image.c
index 395d5c64bdf0..c25ea84e25c5 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -829,7 +829,6 @@ static int build_container(soc_type_t soc, uint32_t 
sector_size,
int ret;
  
  	int container = -1;

-   int cont_img_count = 0; /* indexes to arrange the container */
  
  	memset((char *)_header, 0, sizeof(imx_header_v3_t));
  
@@ -879,7 +878,6 @@ static int build_container(soc_type_t soc, uint32_t sector_size,

img_sp->src = file_off;
  
  			file_off += ALIGN(sbuf.st_size, sector_size);

-   cont_img_count++;
break;
  
  		case SECO:

@@ -899,7 +897,6 @@ static int build_container(soc_type_t soc, uint32_t 
sector_size,
img_sp->src = file_off;
  
  			file_off += sbuf.st_size;

-   cont_img_count++;
break;
  
  		case NEW_CONTAINER:

@@ -908,8 +905,6 @@ static int build_container(soc_type_t soc, uint32_t 
sector_size,
  CONTAINER_ALIGNMENT,
  CONTAINER_FLAGS_DEFAULT,
  fuse_version);
-   /* reset img count when moving to new container */
-   cont_img_count = 0;
scfw_flags = 0;
break;
  

Re: [PATCH 0/5] Convert the LS208xA RDB/QDS boards to DM_SERIAL

[Peng Fan]

Hi Ioana,

Thanks for working on this.

On 3/1/2023 12:32 AM, Ioana Ciornei wrote:

This patch set converts the LS208xA based boards to DM_SERIAL.

Since we don't want to introduce even more differences between the
U-Boot's and Linux's device trees the first 4 patches make the necessary
updates so that the serial nodes are synced with their counterpart.

The last patch just enables DM_SERIAL in the associated configs.


LGTM: Reviewed-by: Peng Fan 

Thanks,
Peng.



Ioana Ciornei (5):
   arch: arm: dst: fsl-ls2080a.dtsi: add an 'soc' node
   arch: arm: dst: fsl-ls2080a.dtsi: move the serial nodes under soc
   arch: arm: dst: fsl-ls2080a.dts: sync serial nodes with Linux
   arch: arm: dst: fsl-ls2080a.dts: tag serial nodes with bootph-all
   configs: ls208x: enable DM_SERIAL

  arch/arm/dts/fsl-ls2080a.dtsi| 57 +++-
  configs/ls2088aqds_tfa_defconfig |  5 +-
  configs/ls2088ardb_tfa_SECURE_BOOT_defconfig |  4 +-
  configs/ls2088ardb_tfa_defconfig |  4 +-
  4 files changed, 53 insertions(+), 17 deletions(-)

Re: [PATCH v3 0/3] imx93: add ADC support

[Peng Fan]

+ Haibo

On 2/27/2023 8:55 PM, Luca Ellero wrote:

Add ADC support for NXP iMX93

Changes for v2:
- add "static" to functions
- enable ADC in iMX93 EVK

Changes for v3:
- split in 3 commits
- keep dts file in sync with Linux devicetree
- add comments to commits

Luca Ellero (3):
   dm: adc: add iMX93 ADC support
   imx93_evk: add adc node to dts file
   imx93_evk: defconfig: add adc support

  arch/arm/dts/imx93-11x11-evk.dts  |   4 +
  configs/imx93_11x11_evk_defconfig |   1 +
  drivers/adc/Kconfig   |   8 +
  drivers/adc/Makefile  |   1 +
  drivers/adc/imx93-adc.c   | 284 ++
  5 files changed, 298 insertions(+)
  create mode 100644 drivers/adc/imx93-adc.c

Pull request: u-boot-rockchip-20230228

[Kever Yang]

Hi Tom,

Please pull the updates for rockchip platform:
- Add support for rk3588 soc;
- Add rk3588 Edgeble Neu6 board and Radxa ROCK5B board;
- Add rk3308 Radxa ROCK Pi S board;
- Add rk3568 Radxa ROCK 3 board,
- Add rk3566 Radxa Compute Module 3 board;
- Add support for sdram reg info version 3
- Refactor rockchip OTP/eFuse driver and add more soc support;
- Add external TPL support for binman;

binman support for mkimage ignore missing entry is based on [1];

CI:
https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/15403

Thanks,
- Kever

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20230219220158.4160763-7-jo...@kwiboo.se/


The following changes since commit e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8:

  Prepare v2023.04-rc3 (2023-02-27 17:18:36 -0500)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-rockchip.git 
tags/u-boot-rockchip-20230228

for you to fetch changes up to a6e85a35b50ade7df5f32092c1cc05ade303a22a:

  board: rock5b-rk3588: add memory gaps into kernel's DTB (2023-02-28 18:07:29 
+0800)


Akash Gajjar (2):
  arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support
  arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S support

Chris Morgan (7):
  gpio: gpio-rockchip: parse gpio-ranges for bank id
  dts: rockchip: px30: add gpio-ranges property to gpio nodes
  arm64: dts: rockchip: Sync rk356x from Linux main
  rockchip: rk3568: add boot device detection
  rockchip: rk3568: enable automatic power savings
  arm64: dts: rockchip: add gpio-ranges property to gpio nodes
  evb-rk3568: Update MAINTAINERS and documentation

Christian Kohlschütter (1):
  arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfo

Christopher Obbard (1):
  include: rk3328: Add default env for compressed kernel images

Eugen Hristev (2):
  board: rockchip: add Radxa ROCK5B Rk3588 board
  board: rock5b-rk3588: add memory gaps into kernel's DTB

Jagan Teki (27):
  board: edgeble: Fix neural-compute-module-2 board name
  rockchip: rk3568: Move DM_RESET in arch kconfig
  dt-bindings: rockchip: Sync rockchip, vop2.h from Linux
  arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3
  arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 IO
  board: rockchip: Add Radxa Compute Module 3 IO Board
  phy: rockchip: inno-usb2: Add support #address_cells = 2
  drivers: phy: add naneng combphy for rk3568
  arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates
  rockchip: rk3568: add rk3568 pinctrl driver
  rockchip: mkimage: Add rk3588 support
  arm: rockchip: Add cru header for rk3588
  arm: rockchip: Add grf header for rk3588
  dt-bindings: clk: Add dt-binding header for RK3588
  clk: rockchip: Add rk3588 clk support
  clk: rockchip: pll: Add pll_rk3588 type for rk3588
  ram: rockchip: Add rk3588 ddr driver support
  dt-bindings: power: Add power-domain header for rk3588
  dt-bindings: reset: add rk3588 reset definitions
  arm: rockchip: Add ioc header for rk3588
  arm64: dts: rockchip: Add base DT for rk3588 SoC
  arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM
  arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO
  arm: rockchip: Add RK3588 arch core support
  ARM: dts: rockchip: Add rk3588-u-boot.dtsi
  ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node
  board: rockchip: Add Edgeble Neural Compute Module 6

John Keeping (1):
  mmc: rockchip_dw_mmc: fix DDR52 8-bit mode handling

Jonas Karlman (21):
  rockchip: sdram: add basic support for sdram reg info version 3
  rockchip: sdram: add dram bank with usable memory beyond 4GB
  rockchip: dts: rk3328: fix sdram params
  binman: Add support for a rockchip-tpl entry
  rockchip: Use an external TPL binary on RK3568
  Revert "board: rockchip: Fix binman_init failure on EVB-RK3568"
  rockchip: mkimage: Update init size limit for RK3328
  rockchip: mkimage: Update init size limit for RK3568
  binman: Mark mkimage entry missing when its subnodes is missing
  rockchip: otp: Refactor to use driver data and ops
  rockchip: otp: Add support for RK3568
  rockchip: otp: Add support for RK3588
  rockchip: otp: Add dump_otp debug command
  rockchip: efuse: Refactor to use driver data and ops
  rockchip: efuse: Add support for RK3288 and more
  rockchip: efuse: Add support for RK3328
  rockchip: efuse: Add support for RK3128
  rockchip: efuse: Add support for RK3036
  rockchip: misc: Set eth1addr mac address
  rockchip: rk3568: Read cpuid from otp
  rockchip: rk3588: Read cpuid from otp

Manoj Sai (3):
  phy: rockchip-inno-usb2: Add USB2 PHY for rk3568
  rockchip: rk3568: Select DM_REGULATOR_FIXED
  rk3566: radxa-cm3: Enable USB2.0, USB3.0 suppor

Re: [PATCH RFC u-boot-mvebu 00/59] arm: mvebu: Various fixes

[Pali Rohár]

On Tuesday 28 February 2023 11:16:03 Stefan Roese wrote:
> Hi Pali,
> 
> On 2/28/23 11:10, Pali Rohár wrote:
> > On Tuesday 28 February 2023 11:01:55 Stefan Roese wrote:
> > > Hi Pali,
> > > 
> > > On 2/28/23 10:54, Pali Rohár wrote:
> > > > On Tuesday 28 February 2023 08:03:47 Stefan Roese wrote:
> > > > > Hi Martin,
> > > > > Hi Pali,
> > > > > 
> > > > > On 2/27/23 12:29, Martin Rowe wrote:
> > > > > > On Mon, 27 Feb 2023 at 08:04, Pali Rohár  > > > > > > wrote:
> > > > > > 
> > > > > >   On Monday 27 February 2023 08:44:30 Stefan Roese wrote:
> > > > > >> Hi Pali,
> > > > > >>
> > > > > >> On 2/25/23 23:00, Pali Rohár wrote:
> > > > > >> > On Tuesday 21 February 2023 21:18:26 Pali Rohár wrote:
> > > > > >> > > This patch series contains various improvements and 
> > > > > > fixes for
> > > > > >   existing
> > > > > >> > > logical errors. Boot phase was adjusted to match 
> > > > > > behavior of
> > > > > >   Armada 385
> > > > > >> > > BootROM by inspecting and disassembling of BootROM 
> > > > > > binary
> > > > > >   dump itself.
> > > > > >> > > Important information are included in documentation 
> > > > > > patch for
> > > > > >   kwboot.
> > > > > >> > > Most of the changes are untested, hence this patch 
> > > > > > series is
> > > > > >   just RFC.
> > > > > >> > > So please test changes before applying, idealy on SPI, 
> > > > > > SATA
> > > > > >   and SD/MMC.
> > > > > >> > > Nevertheless all patches on github passed CI testing 
> > > > > > in this PR:
> > > > > >> > > https://github.com/u-boot/u-boot/pull/275
> > > > > >   
> > > > > >> >
> > > > > >> > Patches were tested on more boards and seems there is no
> > > > > >   reported issue,
> > > > > >> > but other improvements.
> > > > > >> >
> > > > > >> > So do you need something to modify in this relatively 
> > > > > > big patch
> > > > > >   series?
> > > > > >> > If it is not really needed I would like to not send it 
> > > > > > again
> > > > > >   because
> > > > > >> > denx servers are not able to handle it. And it take me 
> > > > > > lot of
> > > > > >   time to
> > > > > >> > send patches over emails to denx servers.
> > > > > >>
> > > > > >> I'm fine with applying the series as-is. I'm a bit hesitant
> > > > > >   though, if
> > > > > >> it should be applied to master or to next. As Tom clearly
> > > > > >   noticed, that
> > > > > >> only fixes should be added after rc2 this time.
> > > > > >>
> > > > > >> What is your thinking on this?
> > > > > > 
> > > > > >   Well, I do not know. AFAIK more patches here are fixing 
> > > > > > broken mvebu
> > > > > >   boards (e.g. eMMC or SATA parts). Maybe Martin or Josua could 
> > > > > > comment?
> > > > > > 
> > > > > > 
> > > > > > A388 Clearfog was definitely broken prior to this patchset. There is
> > > > > > quite a bit of churn that this has caused for some OpenWRT users 
> > > > > > [1] as
> > > > > > well as for me. It would be nice to have a stable build for these
> > > > > > boards.
> > > > > > 
> > > > > > [1] https://github.com/openwrt/openwrt/issues/11661
> > > > > > 
> > > > > 
> > > > > Okay. Thanks for the explanation. So it makes sense to pull this
> > > > > patchset at this stage IMHO.
> > > > > 
> > > > > BUT: While trying to apply the patches sent to me directly this fails 
> > > > > at
> > > > > this patch:
> > > > > 
> > > > > tools: kwbimage: Add support for XIP SPI/NOR images
> > > > > 
> > > > > I tried to fix this merge problem manually, but this looks a bit 
> > > > > bogus.
> > > > > That's why I followed your instruction to pull the patches directly 
> > > > > from
> > > > > github:
> > > > > 
> > > > > git fetch https://github.com/u-boot/u-boot.git 
> > > > > refs/pull/275/merge:mvebu
> > > > > 
> > > > > This works and all patches apply clean. But looking into the patches I
> > > > > noticed, that these patches from github do not include all patches
> > > > > sent to the list. refs/pull/275/merge:mvebu stops after
> > > > > 
> > > > > tools: mkimage: Do not fill legacy_img_hdr for non-legacy XIP images
> > > > > 
> > > > > This is the patch directly before the failing patch mentioned above.
> > > > > 
> > > > > Pali, could you please explain what went wrong here? Maybe I'm missing
> > > > > something?
> > > > 
> > > > Yes, denx mail server is broken and randomly crashes when receiving /
> > > > processing email. It just bounce back with server stacktrace or what.
> > > > I tried to resend patches to ML which did not appeared on patchwork.
> > > > But I cannot do more. So you can try to download patches from patchwork
> > > > or from github.
> > > 
> > > Okay, I understood 

Re: [PATCH 2/2] arm: mvebu: clearfog: Add defconfig for SPI booting

[Pali Rohár]

On Tuesday 28 February 2023 13:51:24 Tony Dinh wrote:
> Hi Pali,
> 
> On Tue, Feb 28, 2023 at 10:52 AM Pali Rohár  wrote:
> >
> > On Tuesday 28 February 2023 10:48:24 Pali Rohár wrote:
> > > On Monday 27 February 2023 17:17:31 Tony Dinh wrote:
> > > > Hi Pali,
> > > >
> > > > On Mon, Feb 27, 2023 at 4:42 PM Tony Dinh  wrote:
> > > > >
> > > > > Hi Pali,
> > > > >
> > > > > On Mon, Feb 27, 2023 at 3:41 PM Tony Dinh  wrote:
> > > > > >
> > > > > > Hi Pali,
> > > > > > It is not related to this patch series (I also tested without the
> > > > > > patch series to confirm). But it is strange that I can no longer get
> > > > > > the configuration to boot from SPI. The 1st device in the boot order
> > > > > > is alway BOOTROM. The spl_boot_list is printed out below.
> > > > > >
> > > > > > 
> > > > > > High speed PHY - Ended Successfully
> > > > > > mv_ddr: 14.0.0
> > > > > > DDR4 Training Sequence - Switching XBAR Window to FastPath Window
> > > > > > mv_ddr: completed successfully
> > > > > > board_boot_order spl_boot_list[0] = 15
> > > > > > Trying to boot from BOOTROM
> > > > > > Returning to BootROM (return address 0x05c4)...
> > > > > > BootROM: Image checksum verification PASSED
> > > > > > 
> > > > > >
> > > > > > The SPL SPI configs (board Thecus N2350) are:
> > > > > > # grep SPL .config| grep SPI
> > > > > >
> > > > > > CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI=y
> > > > > > CONFIG_SPL_DM_SPI=y
> > > > > > CONFIG_SPL_SPI_FLASH_SUPPORT=y
> > > > > > CONFIG_SPL_SPI=y
> > > > > > CONFIG_SPL_DM_SPI_FLASH=y
> > > > > > CONFIG_SPL_SPI_FLASH_TINY=y
> > > > > > # CONFIG_SPL_SPI_FLASH_MTD is not set
> > > > > > CONFIG_SPL_SPI_LOAD=y
> > > > > >
> > > > > > Did I miss something new lately?
> > > > > >
> > > > > > Thanks,
> > > > > > Tony
> > > > > >
> > > > > > Trying to boot from BOOTROM
> > > > > > Returning to BootROM (return address 0x05c4)...
> > > > > > BootROM: Image checksum verification PASSED
> > > > >
> > > > > It turns out that the board strapping register itself is the problem.
> > > > > boot_device=0x9 was printed out in arch/arm/mach-mvebu/cpu.c. It
> > > > > surely does not match what we expected for A38x  (#define
> > > > > BOOT_FROM_SPI 0x32). Actually 0x9 is not defined in cpu.c at all. So
> > > > > it fell to the default case, which is BOOTROM.
> > > > >
> > > > > 
> > > > > U-Boot SPL 2023.04-rc2-tld-1-00089-g3fe03f96fc-dirty (Feb 27 2023 -
> > > > > 16:24:01 -0800)
> > > > > High speed PHY - Version: 2.0
> > > > > Detected Device ID 6820
> > > > > board SerDes lanes topology details:
> > > > >  | Lane # | Speed |  Type   |
> > > > >  
> > > > >  |   0|   0   | SGMII0 |
> > > > >  |   1|   3   | SATA0 |
> > > > >  |   2|   3   | SATA1 |
> > > > >  |   4|   5   | USB3 HOST0 |
> > > > >  |   5|   5   | USB3 HOST1 |
> > > > >  
> > > > > High speed PHY - Ended Successfully
> > > > > mv_ddr: 14.0.0
> > > > > DDR4 Training Sequence - Switching XBAR Window to FastPath Window
> > > > > mv_ddr: completed successfully
> > > > > BOOTROM_REG=0x97001000 boot_device=0x9
> >
> > Wait...
> >
> > Stop here. BOOTROM_REG is the value of BOOTROM_ERR_REG register which is
> > mvebu register 0x182d0.
> >
> > Boot strapping pins are available in the SAR_REG register which is mvebu
> > register 0x18600 and SPL prints it under name SAR_REG.
> 
> Ah, I see. Thanks Pali. I've jumped the gun too soon after seeing the
> 1st boot_device debug statement! Please see below.

Perfect!

> >
> > So above boot_device=9 is not strapping pin configuration but something
> > parsed from BOOTROM_ERR_REG.
> >
> > So above 0x9 signal some A385 bootrom error and SPL in case case of any
> > error (value different from zero) always use bootrom for loading proper
> > u-boot. As it thinks that bootrom loaded u-boot via uart. Seems that
> > this assumption is incorrect.
> >
> > Unfortunately upper four bits which above code parses from mvebu
> > register 0x182d0 are marked as reserved in functional specification.
> >
> > So it is needed to inspect bootrom binary when it sets these bits...
> 
> I think I understand the problem now. The strapping is for Spi 1,
> which is 0x34, but it has not been defined in u-boot yet. We have only
> Spi 0 defined in the code, which is 0x32.
> 
> A38x Hardware Specs
> 0x34
> BootROM Enabled, Boot from SPI: Controller #1, 24 address bits, NOR
> Flash type, using MPP multiplexing option of SPI on MPP[59:56]
> 
> /arch/arm/mach-mvebu/include/mach/soc.h
> #define BOOT_FROM_SPI 0x32
> 
> Here is the boot log. This time I have the SAR_REG printed out.

Ok, this looks correct. BootROM prints that boots from SPI and SPL just
needs correct bootstrap detection.

I would propose to rather define some macro e.g.
BOOT_FROM_IS_SPI(boot_device)
which returns true if boot_device is any SPI option as defined in HW
spec. And not just two options.

> 
> BootROM - 1.73
> Booting from SPI flash
> 
> U-Boot SPL 

Re: [PULL] Please pull u-boot-coldfire/master

[Tom Rini]

On Tue, Feb 28, 2023 at 10:01:46PM +0100, Angelo Dureghello wrote:
> Hi Tom,
> 
> On 28/02/23 9:34 PM, Tom Rini wrote:
> > On Tue, Feb 28, 2023 at 09:21:23PM +0100, Angelo Dureghello wrote:
> > 
> > > The following changes since commit 
> > > e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8:
> > > 
> > >Prepare v2023.04-rc3 (2023-02-27 17:18:36 -0500)
> > > 
> > > are available in the Git repository at:
> > > 
> > >git://git.denx.de/u-boot-coldfire.git master
> > > 
> > > for you to fetch changes up to 4c885f9f64cd85471614c75027620e3bcf3046bd:
> > > 
> > >m68k: dts: stmark2: set correct compatible field for spi nor 
> > > (2023-02-28
> > > 21:19:47 +0100)
> > > 
> > > 
> > > Angelo Dureghello (6):
> > >board: amcore: fix u-boot mtd partition
> > >m68k: use longword-based jumps
> > >m68k: add global variable sdhc_per_clk for m68k
> > >board: stmark2: fix clock value
> > >arch: enable private libgcc for m68k
> > >m68k: dts: stmark2: set correct compatible field for spi nor
> > > 
> > >   arch/Kconfig|  1 +
> > >   arch/m68k/cpu/mcf530x/start.S   | 18 --
> > >   arch/m68k/dts/stmark2.dts   |  2 +-
> > >   arch/m68k/include/asm/global_data.h |  3 +++
> > >   board/sysam/stmark2/Kconfig |  2 +-
> > >   include/configs/amcore.h| 20 +++-
> > >   6 files changed, 33 insertions(+), 13 deletions(-)
> > 
> > OK, you need to re-work a few of the changes:
> > https://source.denx.de/u-boot/u-boot/-/jobs/586499
> > 
> > Things are either in a Kconfig (and the defconfig), or now "CFG_..."
> > instead of "CONFIG_...".
> > 
> 
> i received the automated email. Fixes are in progress, but
> not ready still, there are several CFG to be fixed.
> Could i ask another pull request later, for next release ?

Yes, that's fine.

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH 2/2] arm: mvebu: clearfog: Add defconfig for SPI booting

[Tony Dinh]

Hi Pali,

On Tue, Feb 28, 2023 at 10:52 AM Pali Rohár  wrote:
>
> On Tuesday 28 February 2023 10:48:24 Pali Rohár wrote:
> > On Monday 27 February 2023 17:17:31 Tony Dinh wrote:
> > > Hi Pali,
> > >
> > > On Mon, Feb 27, 2023 at 4:42 PM Tony Dinh  wrote:
> > > >
> > > > Hi Pali,
> > > >
> > > > On Mon, Feb 27, 2023 at 3:41 PM Tony Dinh  wrote:
> > > > >
> > > > > Hi Pali,
> > > > > It is not related to this patch series (I also tested without the
> > > > > patch series to confirm). But it is strange that I can no longer get
> > > > > the configuration to boot from SPI. The 1st device in the boot order
> > > > > is alway BOOTROM. The spl_boot_list is printed out below.
> > > > >
> > > > > 
> > > > > High speed PHY - Ended Successfully
> > > > > mv_ddr: 14.0.0
> > > > > DDR4 Training Sequence - Switching XBAR Window to FastPath Window
> > > > > mv_ddr: completed successfully
> > > > > board_boot_order spl_boot_list[0] = 15
> > > > > Trying to boot from BOOTROM
> > > > > Returning to BootROM (return address 0x05c4)...
> > > > > BootROM: Image checksum verification PASSED
> > > > > 
> > > > >
> > > > > The SPL SPI configs (board Thecus N2350) are:
> > > > > # grep SPL .config| grep SPI
> > > > >
> > > > > CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI=y
> > > > > CONFIG_SPL_DM_SPI=y
> > > > > CONFIG_SPL_SPI_FLASH_SUPPORT=y
> > > > > CONFIG_SPL_SPI=y
> > > > > CONFIG_SPL_DM_SPI_FLASH=y
> > > > > CONFIG_SPL_SPI_FLASH_TINY=y
> > > > > # CONFIG_SPL_SPI_FLASH_MTD is not set
> > > > > CONFIG_SPL_SPI_LOAD=y
> > > > >
> > > > > Did I miss something new lately?
> > > > >
> > > > > Thanks,
> > > > > Tony
> > > > >
> > > > > Trying to boot from BOOTROM
> > > > > Returning to BootROM (return address 0x05c4)...
> > > > > BootROM: Image checksum verification PASSED
> > > >
> > > > It turns out that the board strapping register itself is the problem.
> > > > boot_device=0x9 was printed out in arch/arm/mach-mvebu/cpu.c. It
> > > > surely does not match what we expected for A38x  (#define
> > > > BOOT_FROM_SPI 0x32). Actually 0x9 is not defined in cpu.c at all. So
> > > > it fell to the default case, which is BOOTROM.
> > > >
> > > > 
> > > > U-Boot SPL 2023.04-rc2-tld-1-00089-g3fe03f96fc-dirty (Feb 27 2023 -
> > > > 16:24:01 -0800)
> > > > High speed PHY - Version: 2.0
> > > > Detected Device ID 6820
> > > > board SerDes lanes topology details:
> > > >  | Lane # | Speed |  Type   |
> > > >  
> > > >  |   0|   0   | SGMII0 |
> > > >  |   1|   3   | SATA0 |
> > > >  |   2|   3   | SATA1 |
> > > >  |   4|   5   | USB3 HOST0 |
> > > >  |   5|   5   | USB3 HOST1 |
> > > >  
> > > > High speed PHY - Ended Successfully
> > > > mv_ddr: 14.0.0
> > > > DDR4 Training Sequence - Switching XBAR Window to FastPath Window
> > > > mv_ddr: completed successfully
> > > > BOOTROM_REG=0x97001000 boot_device=0x9
>
> Wait...
>
> Stop here. BOOTROM_REG is the value of BOOTROM_ERR_REG register which is
> mvebu register 0x182d0.
>
> Boot strapping pins are available in the SAR_REG register which is mvebu
> register 0x18600 and SPL prints it under name SAR_REG.

Ah, I see. Thanks Pali. I've jumped the gun too soon after seeing the
1st boot_device debug statement! Please see below.

>
> So above boot_device=9 is not strapping pin configuration but something
> parsed from BOOTROM_ERR_REG.
>
> So above 0x9 signal some A385 bootrom error and SPL in case case of any
> error (value different from zero) always use bootrom for loading proper
> u-boot. As it thinks that bootrom loaded u-boot via uart. Seems that
> this assumption is incorrect.
>
> Unfortunately upper four bits which above code parses from mvebu
> register 0x182d0 are marked as reserved in functional specification.
>
> So it is needed to inspect bootrom binary when it sets these bits...

I think I understand the problem now. The strapping is for Spi 1,
which is 0x34, but it has not been defined in u-boot yet. We have only
Spi 0 defined in the code, which is 0x32.

A38x Hardware Specs
0x34
BootROM Enabled, Boot from SPI: Controller #1, 24 address bits, NOR
Flash type, using MPP multiplexing option of SPI on MPP[59:56]

/arch/arm/mach-mvebu/include/mach/soc.h
#define BOOT_FROM_SPI 0x32

Here is the boot log. This time I have the SAR_REG printed out.


BootROM - 1.73
Booting from SPI flash

U-Boot SPL 2023.04-rc2-tld-1-00089-g3fe03f96fc-dirty (Feb 28 2023 -
13:13:39 -0800)
High speed PHY - Version: 2.0
Detected Device ID 6820
board SerDes lanes topology details:
 | Lane # | Speed |  Type   |
 
 |   0|   0   | SGMII0 |
 |   1|   3   | SATA0 |
 |   2|   3   | SATA1 |
 |   4|   5   | USB3 HOST0 |
 |   5|   5   | USB3 HOST1 |
 
High speed PHY - Ended Successfully
mv_ddr: 14.0.0
DDR4 Training Sequence - Switching XBAR Window to FastPath Window
mv_ddr: completed successfully
BOOTROM_REG=0x97001000 boot_device=0x9
get_boot_device 

[PATCH] rockchip: Use an external TPL binary on RK3588

[Jonas Karlman]

There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL
and instead an external TPL binary must be used to generate a bootable
u-boot-rockchip.bin image.

Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for
RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.

Signed-off-by: Jonas Karlman 
---
 arch/arm/mach-rockchip/Kconfig| 2 +-
 configs/neu6a-io-rk3588_defconfig | 1 -
 configs/rock-3a-rk3568_defconfig  | 1 -
 configs/rock5b-rk3588_defconfig   | 1 -
 doc/board/rockchip/rockchip.rst   | 9 +
 5 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 0390431601f9..e5ac58ae60b5 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -428,7 +428,7 @@ config TPL_ROCKCHIP_COMMON_BOARD
 
 config ROCKCHIP_EXTERNAL_TPL
bool "Use external TPL binary"
-   default y if ROCKCHIP_RK3568
+   default y if ROCKCHIP_RK3568 || ROCKCHIP_RK3588
help
  Some Rockchip SoCs require an external TPL to initialize DRAM.
  Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
diff --git a/configs/neu6a-io-rk3588_defconfig 
b/configs/neu6a-io-rk3588_defconfig
index fb5a2b7dbceb..33c03b58a16c 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -63,5 +63,4 @@ CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
-# CONFIG_BINMAN_FDT is not set
 CONFIG_ERRNO_STR=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 1686c8c1aa5a..e16d98b07af9 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -70,5 +70,4 @@ CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
-# CONFIG_BINMAN_FDT is not set
 CONFIG_ERRNO_STR=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index f3026c7ea166..66199387195a 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -68,5 +68,4 @@ CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_SYSRESET=y
-# CONFIG_BINMAN_FDT is not set
 CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index b5563b8f7f9e..1f88d15aad2a 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -185,6 +185,15 @@ To build rk3568 boards:
 make evb-rk3568_defconfig
 make CROSS_COMPILE=aarch64-linux-gnu-
 
+To build rk3588 boards:
+
+.. code-block:: bash
+
+export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.27.elf
+export 
ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin
+make rock5b-rk3588_defconfig
+make CROSS_COMPILE=aarch64-linux-gnu-
+
 Flashing
 
 
-- 
2.39.2

[PATCH 9/9] ARM: renesas: Add R8A779G0 V4H White Hawk board code

[Marek Vasut]

From: Hai Pham 

Add board code for R8A779G0 V4H White Hawk board.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Synchronize configuration symbols which are now switched to Kconfig
Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
Sort headers, use clrbits_le32(), use BIT macros where appropriate
Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
---
 arch/arm/dts/Makefile   |  3 +-
 arch/arm/dts/r8a779g0-white-hawk-u-boot.dts | 42 
 arch/arm/mach-rmobile/Kconfig.rcar4 |  7 ++
 board/renesas/whitehawk/Kconfig | 15 +
 board/renesas/whitehawk/Makefile|  9 +++
 board/renesas/whitehawk/whitehawk.c | 72 
 configs/r8a779g0_whitehawk_defconfig| 74 +
 include/configs/whitehawk.h | 14 
 8 files changed, 235 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
 create mode 100644 board/renesas/whitehawk/Kconfig
 create mode 100644 board/renesas/whitehawk/Makefile
 create mode 100644 board/renesas/whitehawk/whitehawk.c
 create mode 100644 configs/r8a779g0_whitehawk_defconfig
 create mode 100644 include/configs/whitehawk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2a4af697716..390fb72fd43 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1039,7 +1039,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 
 dtb-$(CONFIG_RCAR_GEN4) += \
r8a779a0-falcon-u-boot.dtb \
-   r8a779f0-spider-u-boot.dtb
+   r8a779f0-spider-u-boot.dtb \
+   r8a779g0-white-hawk-u-boot.dtb
 
 ifdef CONFIG_RCAR_64
 DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts 
b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
new file mode 100644
index 000..efc1b9519ef
--- /dev/null
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the White Hawk board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779g0-white-hawk.dts"
+#include "r8a779g0-u-boot.dtsi"
+
+/ {
+   aliases {
+   spi0 = 
+   };
+};
+
+ {
+   qspi0_pins: qspi0 {
+   groups = "qspi0_ctrl", "qspi0_data4";
+   function = "qspi0";
+   };
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+   spi-max-frequency = <4000>;
+   status = "okay";
+
+   spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "s25fs512s", "jedec,spi-nor";
+   reg = <0>;
+   spi-tx-bus-width = <1>;
+   spi-rx-bus-width = <1>;
+   spi-max-frequency = <4000>;
+   };
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
b/arch/arm/mach-rmobile/Kconfig.rcar4
index 2dc9f00b5d6..d4f93c89cac 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar4
+++ b/arch/arm/mach-rmobile/Kconfig.rcar4
@@ -38,9 +38,16 @@ config TARGET_SPIDER
help
  Support for Renesas R-Car Gen4 Spider platform
 
+config TARGET_WHITEHAWK
+   bool "White Hawk board"
+   imply R8A779G0
+   help
+ Support for Renesas R-Car Gen4 White Hawk platform
+
 endchoice
 
 source "board/renesas/falcon/Kconfig"
 source "board/renesas/spider/Kconfig"
+source "board/renesas/whitehawk/Kconfig"
 
 endif
diff --git a/board/renesas/whitehawk/Kconfig b/board/renesas/whitehawk/Kconfig
new file mode 100644
index 000..05a87894fac
--- /dev/null
+++ b/board/renesas/whitehawk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_WHITEHAWK
+
+config SYS_SOC
+   default "rmobile"
+
+config SYS_BOARD
+   default "whitehawk"
+
+config SYS_VENDOR
+   default "renesas"
+
+config SYS_CONFIG_NAME
+   default "whitehawk"
+
+endif
diff --git a/board/renesas/whitehawk/Makefile b/board/renesas/whitehawk/Makefile
new file mode 100644
index 000..ed5bdc04e01
--- /dev/null
+++ b/board/renesas/whitehawk/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/whitehawk/Makefile
+#
+# Copyright (C) 2021 Renesas Electronics Corp.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := whitehawk.o ../rcar-common/common.o
diff --git a/board/renesas/whitehawk/whitehawk.c 
b/board/renesas/whitehawk/whitehawk.c
new file mode 100644
index 000..19f09e009b5
--- /dev/null
+++ b/board/renesas/whitehawk/whitehawk.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/whitehawk/whitehawk.c
+ * This file is White Hawk board support.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void init_generic_timer(void)
+{
+   const u32 freq = CONFIG_SYS_CLK_FREQ;
+
+   /* 

[PATCH 5/9] ARM: dts: renesas: Add R8A779G0 V4H DT

[Marek Vasut]

From: Phong Hoang 

Add initial DT support for R8A779G0 (R-Car V4H). Based on Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: Phong Hoang 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Sync with Linux next 20230228, update commit message]
---
 arch/arm/dts/r8a779g0.dtsi | 1355 
 1 file changed, 1355 insertions(+)
 create mode 100644 arch/arm/dts/r8a779g0.dtsi

diff --git a/arch/arm/dts/r8a779g0.dtsi b/arch/arm/dts/r8a779g0.dtsi
new file mode 100644
index 000..7a87a5dc1b6
--- /dev/null
+++ b/arch/arm/dts/r8a779g0.dtsi
@@ -0,0 +1,1355 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H (R8A779G0) SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a779g0";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cluster0_opp: opp-table-0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp-5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <825000>;
+   clock-latency-ns = <50>;
+   };
+   opp-10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <825000>;
+   clock-latency-ns = <50>;
+   };
+   opp-15 {
+   opp-hz = /bits/ 64 <15>;
+   opp-microvolt = <825000>;
+   clock-latency-ns = <50>;
+   };
+   opp-17 {
+   opp-hz = /bits/ 64 <17>;
+   opp-microvolt = <825000>;
+   clock-latency-ns = <50>;
+   opp-suspend;
+   };
+   opp-18 {
+   opp-hz = /bits/ 64 <18>;
+   opp-microvolt = <88>;
+   clock-latency-ns = <50>;
+   turbo-mode;
+   };
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <_0>;
+   };
+   core1 {
+   cpu = <_1>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <_2>;
+   };
+   core1 {
+   cpu = <_3>;
+   };
+   };
+   };
+
+   a76_0: cpu@0 {
+   compatible = "arm,cortex-a76";
+   reg = <0>;
+   device_type = "cpu";
+   power-domains = < R8A779G0_PD_A1E0D0C0>;
+   next-level-cache = <_CA76_0>;
+   enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
+   clocks = < CPG_CORE R8A779G0_CLK_Z0>;
+   operating-points-v2 = <_opp>;
+   };
+
+   a76_1: cpu@100 {
+   compatible = "arm,cortex-a76";
+   reg = <0x100>;
+   device_type = "cpu";
+   power-domains = < R8A779G0_PD_A1E0D0C1>;
+   next-level-cache = <_CA76_0>;
+   enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
+   clocks = < CPG_CORE R8A779G0_CLK_Z0>;
+   operating-points-v2 = <_opp>;
+   };
+
+   a76_2: cpu@1 {
+   compatible = "arm,cortex-a76";
+   reg = <0x1>;
+   device_type = "cpu";
+   power-domains = < R8A779G0_PD_A1E0D1C0>;
+   next-level-cache = <_CA76_1>;
+   enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
+   clocks = < CPG_CORE R8A779G0_CLK_Z0>;
+   operating-points-v2 = <_opp>;
+   };
+
+   

[PATCH 8/9] ARM: renesas: Add R8A779G0 V4H Kconfig entry and PRR ID

[Marek Vasut]

From: Hai Pham 

Add Kconfig entry and PRR ID to support R8A779G0 V4H SoC.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Update commit message]
---
 arch/arm/mach-rmobile/Kconfig.rcar4  | 6 ++
 arch/arm/mach-rmobile/cpu_info.c | 1 +
 arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
b/arch/arm/mach-rmobile/Kconfig.rcar4
index 262791635e5..2dc9f00b5d6 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar4
+++ b/arch/arm/mach-rmobile/Kconfig.rcar4
@@ -14,6 +14,12 @@ config R8A779F0
imply CLK_R8A779F0
imply PINCTRL_PFC_R8A779F0
 
+config R8A779G0
+   bool "Renesas SoC R8A779G0"
+   select GICV3
+   imply CLK_R8A779G0
+   imply PINCTRL_PFC_R8A779G0
+
 endmenu
 
 choice
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 02477c2cc7c..7e7465a2c8b 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -77,6 +77,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
{ RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
+   { RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
{ 0x0, "CPU" },
 };
 
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h 
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index 75838441471..a14c2aad0a6 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -40,6 +40,7 @@
 #define RMOBILE_CPU_TYPE_R8A77995  0x58
 #define RMOBILE_CPU_TYPE_R8A779A0  0x59
 #define RMOBILE_CPU_TYPE_R8A779F0  0x5A
+#define RMOBILE_CPU_TYPE_R8A779G0  0x5C
 
 #ifndef __ASSEMBLY__
 const u8 *rzg_get_cpu_name(void);
-- 
2.39.2

[PATCH 7/9] ARM: dts: renesas: Add R8A779G0 V4H White Hawk DTs

[Marek Vasut]

From: Tho Vu 

Add DTs for R8A779G0 V4H White Hawk CPU and BreakOut boards.

Based on Linux next 20230228 DTs up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: Tho Vu 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Sync with Linux next 20230228, update commit message
Rename DTs to match Linux, which has dash between white-hawk]
---
 arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi | 375 ++
 arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi |  15 +
 .../arm/dts/r8a779g0-white-hawk-ethernet.dtsi |  16 +
 arch/arm/dts/r8a779g0-white-hawk.dts  |  25 ++
 4 files changed, 431 insertions(+)
 create mode 100644 arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi
 create mode 100644 arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
 create mode 100644 arch/arm/dts/r8a779g0-white-hawk-ethernet.dtsi
 create mode 100644 arch/arm/dts/r8a779g0-white-hawk.dts

diff --git a/arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi 
b/arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi
new file mode 100644
index 000..bb4a5270f71
--- /dev/null
+++ b/arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the White Hawk CPU board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include "r8a779g0.dtsi"
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "Renesas White Hawk CPU board";
+   compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
+
+   aliases {
+   ethernet0 = 
+   serial0 = 
+   };
+
+   chosen {
+   bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+   stdout-path = "serial0:921600n8";
+   };
+
+   keys {
+   compatible = "gpio-keys";
+
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   key-1 {
+   gpios = < 0 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "SW47";
+   wakeup-source;
+   debounce-interval = <20>;
+   };
+
+   key-2 {
+   gpios = < 1 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "SW48";
+   wakeup-source;
+   debounce-interval = <20>;
+   };
+
+   key-3 {
+   gpios = < 2 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "SW49";
+   wakeup-source;
+   debounce-interval = <20>;
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   led-1 {
+   gpios = < 0 GPIO_ACTIVE_HIGH>;
+   color = ;
+   function = LED_FUNCTION_INDICATOR;
+   function-enumerator = <1>;
+   };
+
+   led-2 {
+   gpios = < 1 GPIO_ACTIVE_HIGH>;
+   color = ;
+   function = LED_FUNCTION_INDICATOR;
+   function-enumerator = <2>;
+   };
+
+   led-3 {
+   gpios = < 2 GPIO_ACTIVE_HIGH>;
+   color = ;
+   function = LED_FUNCTION_INDICATOR;
+   function-enumerator = <3>;
+   };
+   };
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@48000 {
+   device_type = "memory";
+   reg = <0x4 0x8000 0x0 0x8000>;
+   };
+
+   memory@6 {
+   device_type = "memory";
+   reg = <0x6 0x 0x1 0x>;
+   };
+
+   mini-dp-con {
+   compatible = "dp-connector";
+   label = "CN5";
+   type = "mini";
+
+   port {
+   mini_dp_con_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+   };
+
+   reg_1p2v: regulator-1p2v {
+   compatible = "regulator-fixed";
+   regulator-name = "fixed-1.2V";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   reg_1p8v: regulator-1

[PATCH 6/9] ARM: dts: renesas: Add R8A779G0 V4H DT extras

[Marek Vasut]

From: Hai Pham 

Add R8A779G0 V4H DT extras for U-Boot.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Update compatible string to match latest upstream]
---
 arch/arm/dts/r8a779g0-u-boot.dtsi | 28 
 1 file changed, 28 insertions(+)
 create mode 100644 arch/arm/dts/r8a779g0-u-boot.dtsi

diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi 
b/arch/arm/dts/r8a779g0-u-boot.dtsi
new file mode 100644
index 000..450220ec1ac
--- /dev/null
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on R-Car R8A779G0 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+/ {
+   soc {
+   rpc: spi@ee20 {
+   compatible = "renesas,r8a779g0-rpc-if", 
"renesas,rcar-gen4-rpc-if";
+   reg = <0 0xee20 0 0x200>, <0 0x0800 0 
0x0400>;
+   interrupts = ;
+   clocks = < CPG_MOD 629>;
+   power-domains = < R8A779G0_PD_ALWAYS_ON>;
+   resets = < 629>;
+   bank-width = <2>;
+   num-cs = <1>;
+   status = "disabled";
+   };
+   };
+};
+
+_clk {
+   u-boot,dm-pre-reloc;
+};
-- 
2.39.2

[PATCH 3/9] clk: renesas: Add R8A779G0 V4H clock tables

[Marek Vasut]

From: Hai Pham 

Add clock tables for R8A779G0 V4H SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

There is an adjustment to the clock tables to make them easier suitable
for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a
plain PLL2. This should be sufficient until PLL2_VAR is implemented in
the clock core.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver
Treat PLL2 as non-PLL2_VAR for now]
---
 drivers/clk/renesas/Kconfig |   6 +
 drivers/clk/renesas/Makefile|   1 +
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 312 
 3 files changed, 319 insertions(+)
 create mode 100644 drivers/clk/renesas/r8a779g0-cpg-mssr.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index cf28aed7c4b..45671c69251 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -137,3 +137,9 @@ config CLK_R8A779F0
depends on CLK_RCAR_GEN3
help
  Enable this to support the clocks on Renesas R8A779F0 SoC.
+
+config CLK_R8A779G0
+   bool "Renesas R8A779G0 clock driver"
+   depends on CLK_RCAR_GEN3
+   help
+ Enable this to support the clocks on Renesas R8A779G0 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 6cd8157cf3a..fe0391e520c 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c 
b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
new file mode 100644
index 000..8625e8a2d36
--- /dev/null
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ * Based on r8a779f0-cpg-mssr.c
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A779G0_CLK_R,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+   CLK_EXTALR,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL1,
+   CLK_PLL2,
+   CLK_PLL3,
+   CLK_PLL4,
+   CLK_PLL5,
+   CLK_PLL6,
+   CLK_PLL1_DIV2,
+   CLK_PLL2_DIV2,
+   CLK_PLL3_DIV2,
+   CLK_PLL4_DIV2,
+   CLK_PLL5_DIV2,
+   CLK_PLL5_DIV4,
+   CLK_PLL6_DIV2,
+   CLK_S0,
+   CLK_S0_VIO,
+   CLK_S0_VC,
+   CLK_S0_HSC,
+   CLK_SASYNCPER,
+   CLK_SV_VIP,
+   CLK_SV_IR,
+   CLK_SDSRC,
+   CLK_RPCSRC,
+   CLK_VIO,
+   CLK_VC,
+   CLK_OCO,
+
+   /* Module Clocks */
+   MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779g0_core_clks[] = {
+   /* External Clock Inputs */
+   DEF_INPUT("extal",  CLK_EXTAL),
+   DEF_INPUT("extalr", CLK_EXTALR),
+
+   /* Internal Core Clocks */
+   DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+   DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+   DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
+   DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
+   DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
+   DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
+   DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
+
+   DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,   2, 1),
+   DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2,  CLK_PLL2,   2, 1),
+   DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2,  CLK_PLL3,   2, 1),
+   DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2,  CLK_PLL4,   2, 1),
+   DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2,  CLK_PLL5,   2, 1),
+   DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4,  CLK_PLL5_DIV2,  2, 1),
+   DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2,  CLK_PLL6,   2, 1),
+   DEF_FIXED(".s0",CLK_S0, CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s0_vio",CLK_S0_VIO, CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s0_vc", CLK_S0_VC,  CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s0_hsc",CLK_S0_HSC, CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".sasyncper", CLK_SASYNCPER,  CLK_PLL5_DIV4,  3

[PATCH 2/9] dt-bindings: clock: Add R8A779G0 V4H CPG Core Clock Definitions

[Marek Vasut]

From: Tho Vu 

Add all Clock Pulse Generator Core Clock Outputs for the
Renesas R-Car V4H (R8A779G0) SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: Tho Vu 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Update to linux next 20230228 state]
---
 include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 90 +++
 1 file changed, 90 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h 
b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
new file mode 100644
index 000..754c54a6eb0
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+
+#include 
+
+/* r8a779g0 CPG Core Clocks */
+
+#define R8A779G0_CLK_ZX0
+#define R8A779G0_CLK_ZS1
+#define R8A779G0_CLK_ZT2
+#define R8A779G0_CLK_ZTR   3
+#define R8A779G0_CLK_S0D2  4
+#define R8A779G0_CLK_S0D3  5
+#define R8A779G0_CLK_S0D4  6
+#define R8A779G0_CLK_S0D1_VIO  7
+#define R8A779G0_CLK_S0D2_VIO  8
+#define R8A779G0_CLK_S0D4_VIO  9
+#define R8A779G0_CLK_S0D8_VIO  10
+#define R8A779G0_CLK_S0D1_VC   11
+#define R8A779G0_CLK_S0D2_VC   12
+#define R8A779G0_CLK_S0D4_VC   13
+#define R8A779G0_CLK_S0D2_MM   14
+#define R8A779G0_CLK_S0D4_MM   15
+#define R8A779G0_CLK_S0D2_U3DG 16
+#define R8A779G0_CLK_S0D4_U3DG 17
+#define R8A779G0_CLK_S0D2_RT   18
+#define R8A779G0_CLK_S0D3_RT   19
+#define R8A779G0_CLK_S0D4_RT   20
+#define R8A779G0_CLK_S0D6_RT   21
+#define R8A779G0_CLK_S0D24_RT  22
+#define R8A779G0_CLK_S0D2_PER  23
+#define R8A779G0_CLK_S0D3_PER  24
+#define R8A779G0_CLK_S0D4_PER  25
+#define R8A779G0_CLK_S0D6_PER  26
+#define R8A779G0_CLK_S0D12_PER 27
+#define R8A779G0_CLK_S0D24_PER 28
+#define R8A779G0_CLK_S0D1_HSC  29
+#define R8A779G0_CLK_S0D2_HSC  30
+#define R8A779G0_CLK_S0D4_HSC  31
+#define R8A779G0_CLK_S0D2_CC   32
+#define R8A779G0_CLK_SVD1_IR   33
+#define R8A779G0_CLK_SVD2_IR   34
+#define R8A779G0_CLK_SVD1_VIP  35
+#define R8A779G0_CLK_SVD2_VIP  36
+#define R8A779G0_CLK_CL37
+#define R8A779G0_CLK_CL16M 38
+#define R8A779G0_CLK_CL16M_MM  39
+#define R8A779G0_CLK_CL16M_RT  40
+#define R8A779G0_CLK_CL16M_PER 41
+#define R8A779G0_CLK_CL16M_HSC 42
+#define R8A779G0_CLK_Z043
+#define R8A779G0_CLK_ZB3   44
+#define R8A779G0_CLK_ZB3D2 45
+#define R8A779G0_CLK_ZB3D4 46
+#define R8A779G0_CLK_ZG47
+#define R8A779G0_CLK_SD0H  48
+#define R8A779G0_CLK_SD0   49
+#define R8A779G0_CLK_RPC   50
+#define R8A779G0_CLK_RPCD2 51
+#define R8A779G0_CLK_MSO   52
+#define R8A779G0_CLK_CANFD 53
+#define R8A779G0_CLK_CSI   54
+#define R8A779G0_CLK_FRAY  55
+#define R8A779G0_CLK_IPC   56
+#define R8A779G0_CLK_SASYNCRT  57
+#define R8A779G0_CLK_SASYNCPERD1   58
+#define R8A779G0_CLK_SASYNCPERD2   59
+#define R8A779G0_CLK_SASYNCPERD4   60
+#define R8A779G0_CLK_VIOBUS61
+#define R8A779G0_CLK_VIOBUSD2  62
+#define R8A779G0_CLK_VCBUS 63
+#define R8A779G0_CLK_VCBUSD2   64
+#define R8A779G0_CLK_DSIEXT65
+#define R8A779G0_CLK_DSIREF66
+#define R8A779G0_CLK_ADGH  67
+#define R8A779G0_CLK_OSC   68
+#define R8A779G0_CLK_ZR0   69
+#define R8A779G0_CLK_ZR1   70
+#define R8A779G0_CLK_ZR2   71
+#define R8A779G0_CLK_IMPA  72
+#define R8A779G0_CLK_IMPAD473
+#define R8A779G0_CLK_CPEX  74
+#define R8A779G0_CLK_CBFUSA75
+#define R8A779G0_CLK_R 76
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
-- 
2.39.2

[PATCH 1/9] dt-bindings: power: Add R8A779G0 V4H SYSC power domain definitions

[Marek Vasut]

From: Tho Vu 

Add power domain indices for R-Car V4H (R8A779G0) from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: Tho Vu 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Update to linux next 20230228 state]
---
 include/dt-bindings/power/r8a779g0-sysc.h | 46 +++
 1 file changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a779g0-sysc.h

diff --git a/include/dt-bindings/power/r8a779g0-sysc.h 
b/include/dt-bindings/power/r8a779g0-sysc.h
new file mode 100644
index 000..c7b139fb075
--- /dev/null
+++ b/include/dt-bindings/power/r8a779g0-sysc.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779G0_PD_A1E0D0C0   0
+#define R8A779G0_PD_A1E0D0C1   1
+#define R8A779G0_PD_A1E0D1C0   2
+#define R8A779G0_PD_A1E0D1C1   3
+#define R8A779G0_PD_A2E0D0 16
+#define R8A779G0_PD_A2E0D1 17
+#define R8A779G0_PD_A3E0   20
+#define R8A779G0_PD_A33DGA 24
+#define R8A779G0_PD_A23DGB 25
+#define R8A779G0_PD_A1DSP0 33
+#define R8A779G0_PD_A2IMP0134
+#define R8A779G0_PD_A2PSC  35
+#define R8A779G0_PD_A2CV0  36
+#define R8A779G0_PD_A2CV1  37
+#define R8A779G0_PD_A1CNN0 41
+#define R8A779G0_PD_A2CN0  42
+#define R8A779G0_PD_A3IR   43
+#define R8A779G0_PD_A1DSP1 45
+#define R8A779G0_PD_A2IMP2346
+#define R8A779G0_PD_A2DMA  47
+#define R8A779G0_PD_A2CV2  48
+#define R8A779G0_PD_A2CV3  49
+#define R8A779G0_PD_A1DSP2 53
+#define R8A779G0_PD_A1DSP3 54
+#define R8A779G0_PD_A3VIP0 56
+#define R8A779G0_PD_A3VIP1 57
+#define R8A779G0_PD_A3VIP2 58
+#define R8A779G0_PD_A3ISP0 60
+#define R8A779G0_PD_A3ISP1 61
+#define R8A779G0_PD_A3DUL  62
+
+/* Always-on power area */
+#define R8A779G0_PD_ALWAYS_ON  64
+
+#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/
-- 
2.39.2

[PATCH 05/11] pinctrl: renesas: Add R8A779F0 S4 PFC tables

[Marek Vasut]

From: LUU HOAI 

Add pinctrl tables for R8A779F0 S4 SoC.

Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: LUU HOAI 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Use RCAR_64 Kconfig, sync with Linux next 20230228]
---
 drivers/gpio/sh_pfc.c  |2 +-
 drivers/pinctrl/renesas/Kconfig|6 +
 drivers/pinctrl/renesas/Makefile   |1 +
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 2106 
 drivers/pinctrl/renesas/pfc.c  |   11 +
 drivers/pinctrl/renesas/sh_pfc.h   |1 +
 6 files changed, 2126 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pinctrl/renesas/pfc-r8a779f0.c

diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c
index 92522b63bbe..2495d6c1c15 100644
--- a/drivers/gpio/sh_pfc.c
+++ b/drivers/gpio/sh_pfc.c
@@ -569,7 +569,7 @@ static int sh_gpio_get_value(struct pinmux_info *gpioc, 
unsigned gpio)
if (!gpioc || get_data_reg(gpioc, gpio, , ) != 0)
return -1;
 
-   if (IS_ENABLED(CONFIG_RCAR_GEN3) &&
+   if (IS_ENABLED(CONFIG_RCAR_64) &&
((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == 
PINMUX_TYPE_INPUT))
offset += 4;
 
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 8f994d8d769..5b82d965b20 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -119,6 +119,12 @@ config PINCTRL_PFC_R8A779A0
help
  Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs.
 
+config PINCTRL_PFC_R8A779F0
+   bool "Renesas RCar Gen4 R8A779F0 pin control driver"
+   depends on PINCTRL_PFC
+   help
+ Support pin multiplexing control on Renesas RCar Gen4 R8A779F0 SoCs.
+
 config PINCTRL_PFC_R7S72100
bool "Renesas RZ/A1 R7S72100 pin control driver"
depends on CPU_RZA1
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1198c868557..d3e62011973 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
 obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
+obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
 obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c 
b/drivers/pinctrl/renesas/pfc-r8a779f0.c
new file mode 100644
index 000..e2ac9d1efde
--- /dev/null
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -0,0 +1,2106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A779F0 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "sh_pfc.h"
+
+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
+#define CPU_ALL_GP(fn, sfx)\
+   PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | 
SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),\
+   PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | 
SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),\
+   PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS),  \
+   PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
+
+#define CPU_ALL_NOGP(fn)   
\
+   PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, 
SH_PFC_PIN_CFG_PULL_DOWN),\
+   PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_20   F_(IRQ3,IP2SR0_19_16)
+#define GPSR0_19   F_(IRQ2,IP2SR0_15_12)
+#define GPSR0_18   F_(IRQ1,IP2SR0_11_8)
+#define GPSR0_17   F_(IRQ0,IP2SR0_7_4)
+#define GPSR0_16   F_(MSIOF0_SS2,  IP2SR0_3_0)
+#define GPSR0_15   F_(MSIOF0_SS1,  IP1SR0_31_28)
+#define GPSR0_14   F_(MSIOF0_SCK,  IP1SR0_27_24)
+#define GPSR0_13   F_(MSIOF0_TXD,  IP1SR0_23_20)
+#define GPSR0_12   F_(MSIOF0_RXD,  IP1SR0_19_16)
+#define GPSR0_11   F_(MSIOF0_SYNC, IP1SR0_15_12)
+#define GPSR0_10   F_(CTS0_N,  IP1SR0_11_8)
+#define GPSR0_9F_(RTS0_N,  IP1SR0_7_4)
+#define GPSR0_8F_(SCK0,IP1SR0_3_0)
+#define GPSR0_7F_(TX0, IP0SR0_31_28)
+#define GPSR0_6F_(RX0, IP0SR0_27_24)
+#define GPSR0_5F_(HRTS0_N, IP0SR0_23_20)
+#define GPSR0_4F_(HCTS0_N, IP0SR0_19_16)
+#define GPSR0_3F_(HTX0,IP0SR0_15_12)
+#define GPSR0_2F_(HRX0,IP0SR0

[PATCH 11/11] ARM: renesas: Add R8A779F0 S4 Spider board code

[Marek Vasut]

From: Hai Pham 

Add board code for R8A779F0 S4 Spider board.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Synchronize configuration symbols which are now switched to Kconfig
Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
Sort headers, use clrbits_le32(), use BIT macros where appropriate
Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
---
 arch/arm/dts/Makefile   |  3 +-
 arch/arm/dts/r8a779f0-spider-u-boot.dts | 42 +++
 arch/arm/mach-rmobile/Kconfig.rcar4 |  7 +++
 board/renesas/spider/Kconfig| 15 ++
 board/renesas/spider/Makefile   |  9 
 board/renesas/spider/spider.c   | 72 +
 configs/r8a779f0_spider_defconfig   | 69 
 include/configs/spider.h| 14 +
 8 files changed, 230 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/r8a779f0-spider-u-boot.dts
 create mode 100644 board/renesas/spider/Kconfig
 create mode 100644 board/renesas/spider/Makefile
 create mode 100644 board/renesas/spider/spider.c
 create mode 100644 configs/r8a779f0_spider_defconfig
 create mode 100644 include/configs/spider.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 379deffa88e..2a4af697716 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1038,7 +1038,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77995-draak-u-boot.dtb
 
 dtb-$(CONFIG_RCAR_GEN4) += \
-   r8a779a0-falcon-u-boot.dtb
+   r8a779a0-falcon-u-boot.dtb \
+   r8a779f0-spider-u-boot.dtb
 
 ifdef CONFIG_RCAR_64
 DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/r8a779f0-spider-u-boot.dts 
b/arch/arm/dts/r8a779f0-spider-u-boot.dts
new file mode 100644
index 000..26fc8bcf440
--- /dev/null
+++ b/arch/arm/dts/r8a779f0-spider-u-boot.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Spider board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779f0-spider.dts"
+#include "r8a779f0-u-boot.dtsi"
+
+/ {
+   aliases {
+   spi0 = 
+   };
+};
+
+ {
+   qspi0_pins: qspi0 {
+   groups = "qspi0_ctrl", "qspi0_data4";
+   function = "qspi0";
+   };
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+   spi-max-frequency = <4000>;
+   status = "okay";
+
+   spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "s25fs512s", "jedec,spi-nor";
+   reg = <0>;
+   spi-tx-bus-width = <1>;
+   spi-rx-bus-width = <1>;
+   spi-max-frequency = <4000>;
+   };
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
b/arch/arm/mach-rmobile/Kconfig.rcar4
index ad9fc3a4bd5..262791635e5 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar4
+++ b/arch/arm/mach-rmobile/Kconfig.rcar4
@@ -26,8 +26,15 @@ config TARGET_FALCON
help
   Support for Renesas R-Car Gen3 Falcon platform
 
+config TARGET_SPIDER
+   bool "Spider board"
+   imply R8A779F0
+   help
+ Support for Renesas R-Car Gen4 Spider platform
+
 endchoice
 
 source "board/renesas/falcon/Kconfig"
+source "board/renesas/spider/Kconfig"
 
 endif
diff --git a/board/renesas/spider/Kconfig b/board/renesas/spider/Kconfig
new file mode 100644
index 000..8df2e85fc9c
--- /dev/null
+++ b/board/renesas/spider/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPIDER
+
+config SYS_SOC
+   default "rmobile"
+
+config SYS_BOARD
+   default "spider"
+
+config SYS_VENDOR
+   default "renesas"
+
+config SYS_CONFIG_NAME
+   default "spider"
+
+endif
diff --git a/board/renesas/spider/Makefile b/board/renesas/spider/Makefile
new file mode 100644
index 000..545cb58a98f
--- /dev/null
+++ b/board/renesas/spider/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/spider/Makefile
+#
+# Copyright (C) 2020 Renesas Electronics Corp.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := spider.o ../rcar-common/common.o
diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c
new file mode 100644
index 000..caf88dcc323
--- /dev/null
+++ b/board/renesas/spider/spider.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/spider/spider.c
+ * This file is Spider board support.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void init_generic_timer(void)
+{
+   const u32 freq = CONFIG_SYS_CLK_FREQ;
+
+   /* Update memory mapped and register based freqency */
+   asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
+   writel(freq, CNTFID0);
+
+   /* Enable counter */
+   

[PATCH 10/11] ARM: renesas: Add R8A779F0 S4 Kconfig entry and PRR ID

[Marek Vasut]

From: Hai Pham 

Add Kconfig entry and PRR ID to support R8A779F0 S4 SoC.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Update commit message]
---
 arch/arm/mach-rmobile/Kconfig.rcar4  | 6 ++
 arch/arm/mach-rmobile/cpu_info.c | 1 +
 arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
b/arch/arm/mach-rmobile/Kconfig.rcar4
index 104672f938e..ad9fc3a4bd5 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar4
+++ b/arch/arm/mach-rmobile/Kconfig.rcar4
@@ -8,6 +8,12 @@ config R8A779A0
imply CLK_R8A779A0
imply PINCTRL_PFC_R8A779A0
 
+config R8A779F0
+   bool "Renesas SoC R8A779F0"
+   select GICV3
+   imply CLK_R8A779F0
+   imply PINCTRL_PFC_R8A779F0
+
 endmenu
 
 choice
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 07f7c2286a4..02477c2cc7c 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -76,6 +76,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
+   { RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
{ 0x0, "CPU" },
 };
 
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h 
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index af5db5c3fd3..75838441471 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -39,6 +39,7 @@
 #define RMOBILE_CPU_TYPE_R8A77990  0x57
 #define RMOBILE_CPU_TYPE_R8A77995  0x58
 #define RMOBILE_CPU_TYPE_R8A779A0  0x59
+#define RMOBILE_CPU_TYPE_R8A779F0  0x5A
 
 #ifndef __ASSEMBLY__
 const u8 *rzg_get_cpu_name(void);
-- 
2.39.2

[PATCH 09/11] ARM: dts: renesas: Add R8A779F0 S4 Spider DTs

[Marek Vasut]

From: Hai Pham 

Add DTs for R8A779F0 S4 Spider CPU boards and Breakout boards.

Based on Linux next 20230228 DTs up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Sync with Linux next 20230228, update commit message]
---
 arch/arm/dts/r8a779f0-spider-cpu.dtsi  | 190 +
 arch/arm/dts/r8a779f0-spider-ethernet.dtsi | 105 
 arch/arm/dts/r8a779f0-spider.dts   |  24 +++
 3 files changed, 319 insertions(+)
 create mode 100644 arch/arm/dts/r8a779f0-spider-cpu.dtsi
 create mode 100644 arch/arm/dts/r8a779f0-spider-ethernet.dtsi
 create mode 100644 arch/arm/dts/r8a779f0-spider.dts

diff --git a/arch/arm/dts/r8a779f0-spider-cpu.dtsi 
b/arch/arm/dts/r8a779f0-spider-cpu.dtsi
new file mode 100644
index 000..dd8e0e15952
--- /dev/null
+++ b/arch/arm/dts/r8a779f0-spider-cpu.dtsi
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the Spider CPU board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include 
+#include "r8a779f0.dtsi"
+
+/ {
+   model = "Renesas Spider CPU board";
+   compatible = "renesas,spider-cpu", "renesas,r8a779f0";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   };
+
+   chosen {
+   bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+   stdout-path = "serial0:1843200n8";
+   };
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@48000 {
+   device_type = "memory";
+   reg = <0x4 0x8000 0x0 0x8000>;
+   };
+
+   rc21012_ufs: clk-rc21012-ufs {
+   compatible = "fixed-clock";
+   clock-frequency = <3840>;
+   #clock-cells = <0>;
+   };
+
+   reg_1p8v: regulator-1p8v {
+   compatible = "regulator-fixed";
+   regulator-name = "fixed-1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   reg_3p3v: regulator-3p3v {
+   compatible = "regulator-fixed";
+   regulator-name = "fixed-3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+};
+
+_clk {
+   clock-frequency = <2000>;
+};
+
+_clk {
+   clock-frequency = <32768>;
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   uart-has-rtscts;
+   status = "okay";
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+   clock-frequency = <40>;
+
+   gpio_exp_20: gpio@20 {
+   compatible = "ti,tca9554";
+   reg = <0x20>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+   clock-frequency = <40>;
+
+   eeprom@50 {
+   compatible = "rohm,br24g01", "atmel,24c01";
+   label = "cpu-board";
+   reg = <0x50>;
+   pagesize = <8>;
+   };
+};
+
+/*
+ * This board also has a microSD slot which we will not support upstream
+ * because we cannot directly switch voltages in software.
+ */
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-1 = <_pins>;
+   pinctrl-names = "default", "state_uhs";
+
+   vmmc-supply = <_3p3v>;
+   vqmmc-supply = <_1p8v>;
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   bus-width = <8>;
+   no-sd;
+   no-sdio;
+   non-removable;
+   full-pwr-cycle-in-suspend;
+   status = "okay";
+};
+
+ {
+   pinctrl-0 = <_clk_pins>;
+   pinctrl-names = "default";
+
+   hscif0_pins: hscif0 {
+   groups = "hscif0_data", "hscif0_ctrl";
+   function = "hscif0";
+   };
+
+   i2c0_pins: i2c0 {
+   groups = "i2c0";
+   function = "i2c0";
+   };
+
+   i2c4_pins: i2c4 {
+   groups = "i2c4";
+   function = "i2c4";
+   };
+
+   mmc_pins: mm

[PATCH 07/11] ARM: dts: renesas: Add R8A779F0 S4 DT

[Marek Vasut]

From: Hai Pham 

Add initial DT for R8A779F0 S4 SoC. Based on Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Sync with Linux next 20230228, update commit message]
---
 arch/arm/dts/r8a779f0.dtsi | 1179 
 1 file changed, 1179 insertions(+)
 create mode 100644 arch/arm/dts/r8a779f0.dtsi

diff --git a/arch/arm/dts/r8a779f0.dtsi b/arch/arm/dts/r8a779f0.dtsi
new file mode 100644
index 000..f20b612b2b9
--- /dev/null
+++ b/arch/arm/dts/r8a779f0.dtsi
@@ -0,0 +1,1179 @@
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a779f0";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cluster01_opp: opp-table-0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp-5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <88>;
+   clock-latency-ns = <50>;
+   };
+   opp-8 {
+   opp-hz = /bits/ 64 <8>;
+   opp-microvolt = <88>;
+   clock-latency-ns = <50>;
+   };
+   opp-10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <88>;
+   clock-latency-ns = <50>;
+   };
+   opp-12 {
+   opp-hz = /bits/ 64 <12>;
+   opp-microvolt = <88>;
+   clock-latency-ns = <50>;
+   opp-suspend;
+   };
+   };
+
+   cluster23_opp: opp-table-1 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp-5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <88>;
+   clock-latency-ns = <50>;
+   };
+   opp-8 {
+   opp-hz = /bits/ 64 <8>;
+   opp-microvolt = <88>;
+   clock-latency-ns = <50>;
+   };
+   opp-10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <88>;
+   clock-latency-ns = <50>;
+   };
+   opp-12 {
+   opp-hz = /bits/ 64 <12>;
+   opp-microvolt = <88>;
+   clock-latency-ns = <50>;
+   opp-suspend;
+   };
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <_0>;
+   };
+   core1 {
+   cpu = <_1>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <_2>;
+   };
+   core1 {
+   cpu = <_3>;
+   };
+   };
+
+   cluster2 {
+   core0 {
+   cpu = <_4>;
+   };
+   core1 {
+   cpu = <_5>;
+   };
+   };
+
+   cluster3 {
+   core0 {
+   cpu = <_6>;
+   };
+   core1 {
+   cpu = <_7>;
+   };
+   };
+   };
+
+   a55_0: cpu@0 {
+   compatible = "arm,cortex-a55";
+   reg = <0>;
+   device_type = "cpu";
+   power-domains = < R8A779F0_PD_A1E0D0C0>;
+   next-level-cache = <_CA55_0>;
+   enable

[PATCH 08/11] ARM: dts: renesas: Add R8A779F0 S4 DT extras

[Marek Vasut]

From: Hai Pham 

Add R8A779F0 S4 DT extras for U-Boot.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Update compatible string to match latest upstream]
---
 arch/arm/dts/r8a779f0-u-boot.dtsi | 28 
 1 file changed, 28 insertions(+)
 create mode 100644 arch/arm/dts/r8a779f0-u-boot.dtsi

diff --git a/arch/arm/dts/r8a779f0-u-boot.dtsi 
b/arch/arm/dts/r8a779f0-u-boot.dtsi
new file mode 100644
index 000..24b67248c09
--- /dev/null
+++ b/arch/arm/dts/r8a779f0-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on R-Car R8A779F0 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+/ {
+   soc {
+   rpc: spi@ee20 {
+   compatible = "renesas,r8a779f0-rpc-if", 
"renesas,rcar-gen4-rpc-if";
+   reg = <0 0xee20 0 0x200>, <0 0x0800 0 
0x0400>;
+   interrupts = ;
+   clocks = < CPG_MOD 629>;
+   power-domains = < R8A779F0_PD_ALWAYS_ON>;
+   resets = < 629>;
+   bank-width = <2>;
+   num-cs = <1>;
+   status = "disabled";
+   };
+   };
+};
+
+_clk {
+   u-boot,dm-pre-reloc;
+};
-- 
2.39.2

[PATCH 06/11] ARM: rmobile: Turn R-Car V3U into R-Car Gen4

[Marek Vasut]

From: Hai Pham 

Despite the name, R-Car V3U is the first member of the R-Car Gen4
family [1]. Hence reflect this in related files, select appropriate
configuration options and split DT build into its own GEN4 entry.

[1] 
https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Deduplicate DTC_FLAGS addition using RCAR_64 symbol
Update commit message]
---
 arch/arm/dts/Makefile   |  6 --
 arch/arm/mach-rmobile/Kconfig.rcar3 | 13 -
 arch/arm/mach-rmobile/Kconfig.rcar4 | 19 +++
 configs/r8a779a0_falcon_defconfig   |  2 +-
 include/configs/falcon.h| 12 +---
 5 files changed, 25 insertions(+), 27 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7a577deb502..379deffa88e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1035,10 +1035,12 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77970-eagle-u-boot.dtb \
r8a77980-condor-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
-   r8a77995-draak-u-boot.dtb \
+   r8a77995-draak-u-boot.dtb
+
+dtb-$(CONFIG_RCAR_GEN4) += \
r8a779a0-falcon-u-boot.dtb
 
-ifdef CONFIG_RCAR_GEN3
+ifdef CONFIG_RCAR_64
 DTC_FLAGS += -R 4 -p 0x1000
 endif
 
diff --git a/arch/arm/mach-rmobile/Kconfig.rcar3 
b/arch/arm/mach-rmobile/Kconfig.rcar3
index 680aa455160..5f338219b45 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar3
+++ b/arch/arm/mach-rmobile/Kconfig.rcar3
@@ -70,12 +70,6 @@ config R8A77995
imply CLK_R8A77995
imply PINCTRL_PFC_R8A77995
 
-config R8A779A0
-   bool "Renesas SoC R8A779A0"
-   select GICV3
-   imply CLK_R8A779A0
-   imply PINCTRL_PFC_R8A779A0
-
 config RZ_G2
bool "Renesas ARM SoCs RZ/G2 (64bit)"
 
@@ -123,12 +117,6 @@ config TARGET_EBISU
help
   Support for Renesas R-Car Gen3 Ebisu platform
 
-config TARGET_FALCON
-   bool "Falcon board"
-   imply R8A779A0
-   help
-  Support for Renesas R-Car Gen3 Falcon platform
-
 config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply MULTI_DTB_FIT
@@ -176,7 +164,6 @@ source "board/renesas/condor/Kconfig"
 source "board/renesas/draak/Kconfig"
 source "board/renesas/eagle/Kconfig"
 source "board/renesas/ebisu/Kconfig"
-source "board/renesas/falcon/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
 source "board/beacon/beacon-rzg2m/Kconfig"
diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
b/arch/arm/mach-rmobile/Kconfig.rcar4
index 6d9e16586d9..104672f938e 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar4
+++ b/arch/arm/mach-rmobile/Kconfig.rcar4
@@ -1,8 +1,27 @@
 if RCAR_GEN4
 
+menu "Select Target SoC"
+
+config R8A779A0
+   bool "Renesas SoC R8A779A0"
+   select GICV3
+   imply CLK_R8A779A0
+   imply PINCTRL_PFC_R8A779A0
+
+endmenu
+
 choice
prompt "Renesas ARM64 SoCs board select"
optional
+
+config TARGET_FALCON
+   bool "Falcon board"
+   imply R8A779A0
+   help
+  Support for Renesas R-Car Gen3 Falcon platform
+
 endchoice
 
+source "board/renesas/falcon/Kconfig"
+
 endif
diff --git a/configs/r8a779a0_falcon_defconfig 
b/configs/r8a779a0_falcon_defconfig
index 083055a1dfa..14feaf13d6e 100644
--- a/configs/r8a779a0_falcon_defconfig
+++ b/configs/r8a779a0_falcon_defconfig
@@ -10,7 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x4
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot"
 CONFIG_SPL_TEXT_BASE=0xe6338000
-CONFIG_RCAR_GEN3=y
+CONFIG_RCAR_GEN4=y
 CONFIG_TARGET_FALCON=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SYS_CLK_FREQ=1666
diff --git a/include/configs/falcon.h b/include/configs/falcon.h
index 446261cedc7..0b62ff9fbe1 100644
--- a/include/configs/falcon.h
+++ b/include/configs/falcon.h
@@ -9,17 +9,7 @@
 #ifndef __FALCON_H
 #define __FALCON_H
 
-#include "rcar-gen3-common.h"
-
-/*
- * Generic Interrupt Controller Definitions.  Undefine v2 locations and define
- * v3 locations.
- */
-#undef GICD_BASE
-#undef GICC_BASE
-#undef GICR_BASE
-#define GICD_BASE  0xF100
-#define GICR_BASE  0xF106
+#include "rcar-gen4-common.h"
 
 /* Board Clock */
 /* XTAL_CLK : 16.66MHz */
-- 
2.39.2

[PATCH 03/11] clk: renesas: Update R-Car Gen3 driver Gen4 support

[Marek Vasut]

Update R-Car Gen4 support in Gen3 clock driver. This patch renames the
V3U clock parts to Gen4 and extends them by new PLL2, PLL3, PLL4, PLL6
as well as SDSRC clock which use undocumented bits so far, and RPCSRC
clock which uses its own more capable divider table. The Gen4 module
standby and reset tables are also updated.

This patch makes use of union to alias Gen3 and more extensive Gen4
PLL tables, as the driver cannot ever be instantiated on hardware
that would identify itself as both Gen3 and Gen4.

The V3U clock driver is updated to match Gen4 clock driver behavior,
it is augmented with a more extensive PLL table and a valid MODEMR
register offset.

This supersedes "clk: renesas: Introduce R-Car Gen4 CPG driver"
from Hai Pham as the R-Car Gen3 and Gen4 clock core drivers are
extremely similar. That implementation was in turn based on Linux
commit 470e3f0d0b15 ("clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver")
by Yoshihiro Shimoda .

Signed-off-by: Marek Vasut 
---
 drivers/clk/renesas/Kconfig |   6 +-
 drivers/clk/renesas/clk-rcar-gen3.c | 109 ++--
 drivers/clk/renesas/r8a779a0-cpg-mssr.c |  20 ++---
 drivers/clk/renesas/rcar-gen3-cpg.h |  28 +-
 drivers/clk/renesas/renesas-cpg-mssr.c  |   2 +-
 drivers/clk/renesas/renesas-cpg-mssr.h  |  28 +++---
 6 files changed, 138 insertions(+), 55 deletions(-)

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index d58e897ca1b..b51837a8e70 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -45,13 +45,13 @@ config CLK_R8A7794
  Enable this to support the clocks on Renesas R8A7794 SoC.
 
 config CLK_RCAR_GEN3
-   bool "Renesas RCar Gen3 clock driver"
-   def_bool y if RCAR_GEN3
+   bool "Renesas RCar Gen3 and Gen4 clock driver"
+   def_bool y if RCAR_64
depends on CLK_RENESAS
select CLK_RCAR_CPG_LIB
select DM_RESET
help
- Enable this to support the clocks on Renesas RCar Gen3 SoC.
+ Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs.
 
 config CLK_R8A774A1
 bool "Renesas R8A774A1 clock driver"
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c 
b/drivers/clk/renesas/clk-rcar-gen3.c
index 9545e0a1435..01c18ab24e1 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -35,10 +35,16 @@
 #define CPG_PLL2CR 0x002c
 #define CPG_PLL4CR 0x01f4
 
-static const struct clk_div_table cpg_rpcsrc_div_table[] = {
+#define SD0CKCR1   0x08a4
+
+static const struct clk_div_table gen3_cpg_rpcsrc_div_table[] = {
{ 2, 5 }, { 3, 6 }, { 0, 0 },
 };
 
+static const struct clk_div_table gen4_cpg_rpcsrc_div_table[] = {
+   { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
+};
+
 static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
{  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
{  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
@@ -181,8 +187,10 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
struct cpg_mssr_info *info = priv->info;
struct clk parent;
const struct cpg_core_clk *core;
-   const struct rcar_gen3_cpg_pll_config *pll_config =
-   priv->cpg_pll_config;
+   const struct rcar_gen3_cpg_pll_config *gen3_pll_config =
+   priv->gen3_cpg_pll_config;
+   const struct rcar_gen4_cpg_pll_config *gen4_pll_config =
+   priv->gen4_cpg_pll_config;
u32 value, div;
u64 rate = 0;
u8 shift;
@@ -227,7 +235,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
case CLK_TYPE_GEN3_MAIN:
return gen3_clk_get_rate64_pll_mul_reg(priv, ,
-   0, 1, pll_config->extal_div,
+   0, 1, 
gen3_pll_config->extal_div,
"MAIN");
 
case CLK_TYPE_GEN3_PLL0:
@@ -236,8 +244,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
case CLK_TYPE_GEN3_PLL1:
return gen3_clk_get_rate64_pll_mul_reg(priv, ,
-   0, pll_config->pll1_mult,
-   pll_config->pll1_div, "PLL1");
+   0, gen3_pll_config->pll1_mult,
+   gen3_pll_config->pll1_div,
+   "PLL1");
 
case CLK_TYPE_GEN3_PLL2:
return gen3_clk_get_rate64_pll_mul_reg(priv, ,
@@ -245,8 +254,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
case CLK_TYPE_GEN3_PLL3:
return gen3_clk_get_rate64_pll_mul_reg(priv, ,
-   0, pll_config->pll3_mult,
-   

[PATCH 04/11] clk: renesas: Add R8A779F0 S4 clock tables

[Marek Vasut]

From: Hai Pham 

Add clock tables for R8A779F0 S4 SoC

Based on Linux commit 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support
for R-Car S4-8") by Yoshihiro Shimoda and sync the tables up to Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver]
---
 drivers/clk/renesas/Kconfig |   6 +
 drivers/clk/renesas/Makefile|   1 +
 drivers/clk/renesas/r8a779f0-cpg-mssr.c | 250 
 3 files changed, 257 insertions(+)
 create mode 100644 drivers/clk/renesas/r8a779f0-cpg-mssr.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index b51837a8e70..cf28aed7c4b 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -131,3 +131,9 @@ config CLK_R8A779A0
depends on CLK_RCAR_GEN3
help
  Enable this to support the clocks on Renesas R8A779A0 SoC.
+
+config CLK_R8A779F0
+   bool "Renesas R8A779F0 clock driver"
+   depends on CLK_RCAR_GEN3
+   help
+ Enable this to support the clocks on Renesas R8A779F0 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 8f82a7aa3e0..6cd8157cf3a 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c 
b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
new file mode 100644
index 000..7aac28ed496
--- /dev/null
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ *
+ * Based on r8a779a0-cpg-mssr.c
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A779F0_CLK_R,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+   CLK_EXTALR,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL1,
+   CLK_PLL2,
+   CLK_PLL3,
+   CLK_PLL5,
+   CLK_PLL6,
+   CLK_PLL1_DIV2,
+   CLK_PLL2_DIV2,
+   CLK_PLL3_DIV2,
+   CLK_PLL5_DIV2,
+   CLK_PLL5_DIV4,
+   CLK_PLL6_DIV2,
+   CLK_S0,
+   CLK_SASYNCPER,
+   CLK_SDSRC,
+   CLK_RPCSRC,
+   CLK_OCO,
+
+   /* Module Clocks */
+   MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779f0_core_clks[] = {
+   /* External Clock Inputs */
+   DEF_INPUT("extal",  CLK_EXTAL),
+   DEF_INPUT("extalr", CLK_EXTALR),
+
+   /* Internal Core Clocks */
+   DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+   DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+   DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
+   DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
+   DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
+   DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
+
+   DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,   2, 1),
+   DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2,  CLK_PLL2,   2, 1),
+   DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2,  CLK_PLL3,   2, 1),
+   DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2,  CLK_PLL5,   2, 1),
+   DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4,  CLK_PLL5_DIV2,  2, 1),
+   DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2,  CLK_PLL6,   2, 1),
+   DEF_FIXED(".s0",CLK_S0, CLK_PLL1_DIV2,  2, 1),
+
+   DEF_FIXED(".sasyncper", CLK_SASYNCPER,  CLK_PLL5_DIV4,  3, 1),
+   DEF_BASE(".sdsrc",  CLK_SDSRC,  CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
+   DEF_RATE(".oco",CLK_OCO,32768),
+
+   DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
+
+   /* Core Clock Outputs */
+   DEF_GEN4_Z("z0",R8A779F0_CLK_Z0,CLK_TYPE_GEN4_Z,
CLK_PLL2,   2, 0),
+   DEF_GEN4_Z("z1",R8A779F0_CLK_Z1,CLK_TYPE_GEN4_Z,
CLK_PLL2,   2, 8),
+   DEF_FIXED("s0d2",   R8A779F0_CLK_S0D2,  CLK_S0, 2, 1),
+   DEF_FIXED("s0d3",   R8A779F0_CLK_S0D3,  CLK_S0, 3, 1),
+   DEF_FIXED("s0d4"

[PATCH 01/11] dt-bindings: power: Add R8A779F0 S4 SYSC power domain definitions

[Marek Vasut]

From: Tho Vu 

Add power domain indices for R-Car S4 (R8A779F0) from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: Tho Vu 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Update to linux next 20230228 state]
---
 include/dt-bindings/power/r8a779f0-sysc.h | 30 +++
 1 file changed, 30 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a779f0-sysc.h

diff --git a/include/dt-bindings/power/r8a779f0-sysc.h 
b/include/dt-bindings/power/r8a779f0-sysc.h
new file mode 100644
index 000..0ec8ad727ed
--- /dev/null
+++ b/include/dt-bindings/power/r8a779f0-sysc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779F0_PD_A1E0D0C0   0
+#define R8A779F0_PD_A1E0D0C1   1
+#define R8A779F0_PD_A1E0D1C0   2
+#define R8A779F0_PD_A1E0D1C1   3
+#define R8A779F0_PD_A1E1D0C0   4
+#define R8A779F0_PD_A1E1D0C1   5
+#define R8A779F0_PD_A1E1D1C0   6
+#define R8A779F0_PD_A1E1D1C1   7
+#define R8A779F0_PD_A2E0D0 16
+#define R8A779F0_PD_A2E0D1 17
+#define R8A779F0_PD_A2E1D0 18
+#define R8A779F0_PD_A2E1D1 19
+#define R8A779F0_PD_A3E0   20
+#define R8A779F0_PD_A3E1   21
+
+/* Always-on power area */
+#define R8A779F0_PD_ALWAYS_ON  64
+
+#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/
-- 
2.39.2

[PATCH 02/11] dt-bindings: clock: Add R8A779F0 S4 CPG Core Clock headers

[Marek Vasut]

From: Tho Vu 

Add definitions for R8A779F0 S4 CPG Core Clock headers from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut 
Signed-off-by: Tho Vu 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Update to linux next 20230228 state]
---
 include/dt-bindings/clock/r8a779f0-cpg-mssr.h | 64 +++
 1 file changed, 64 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a779f0-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h 
b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
new file mode 100644
index 000..f2ae1c6a82d
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
+
+#include 
+
+/* r8a779f0 CPG Core Clocks */
+
+#define R8A779F0_CLK_ZX0
+#define R8A779F0_CLK_ZS1
+#define R8A779F0_CLK_ZT2
+#define R8A779F0_CLK_ZTR   3
+#define R8A779F0_CLK_S0D2  4
+#define R8A779F0_CLK_S0D3  5
+#define R8A779F0_CLK_S0D4  6
+#define R8A779F0_CLK_S0D2_MM   7
+#define R8A779F0_CLK_S0D3_MM   8
+#define R8A779F0_CLK_S0D4_MM   9
+#define R8A779F0_CLK_S0D2_RT   10
+#define R8A779F0_CLK_S0D3_RT   11
+#define R8A779F0_CLK_S0D4_RT   12
+#define R8A779F0_CLK_S0D6_RT   13
+#define R8A779F0_CLK_S0D3_PER  14
+#define R8A779F0_CLK_S0D6_PER  15
+#define R8A779F0_CLK_S0D12_PER 16
+#define R8A779F0_CLK_S0D24_PER 17
+#define R8A779F0_CLK_S0D2_HSC  18
+#define R8A779F0_CLK_S0D3_HSC  19
+#define R8A779F0_CLK_S0D4_HSC  20
+#define R8A779F0_CLK_S0D6_HSC  21
+#define R8A779F0_CLK_S0D12_HSC 22
+#define R8A779F0_CLK_S0D2_CC   23
+#define R8A779F0_CLK_CL24
+#define R8A779F0_CLK_CL16M 25
+#define R8A779F0_CLK_CL16M_MM  26
+#define R8A779F0_CLK_CL16M_RT  27
+#define R8A779F0_CLK_CL16M_PER 28
+#define R8A779F0_CLK_CL16M_HSC 29
+#define R8A779F0_CLK_Z030
+#define R8A779F0_CLK_Z131
+#define R8A779F0_CLK_ZB3   32
+#define R8A779F0_CLK_ZB3D2 33
+#define R8A779F0_CLK_ZB3D4 34
+#define R8A779F0_CLK_SD0H  35
+#define R8A779F0_CLK_SD0   36
+#define R8A779F0_CLK_RPC   37
+#define R8A779F0_CLK_RPCD2 38
+#define R8A779F0_CLK_MSO   39
+#define R8A779F0_CLK_SASYNCRT  40
+#define R8A779F0_CLK_SASYNCPERD1   41
+#define R8A779F0_CLK_SASYNCPERD2   42
+#define R8A779F0_CLK_SASYNCPERD4   43
+#define R8A779F0_CLK_DBGSOC_HSC44
+#define R8A779F0_CLK_RSW2  45
+#define R8A779F0_CLK_OSC   46
+#define R8A779F0_CLK_ZR47
+#define R8A779F0_CLK_CPEX  48
+#define R8A779F0_CLK_CBFUSA49
+#define R8A779F0_CLK_R 50
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */
-- 
2.39.2

[PATCH 2/2] serial: sh: Add HSCIF support for R-Car SoC

[Marek Vasut]

From: Hai Pham 

Provide the basic HSCIF support for R-Car SoC.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Fill in HSSRR offset for Gen2 and SCBRR calculation for Gen2 and Gen3]
---
Cc: Simon Glass 
---
 doc/device-tree-bindings/serial/sh.txt |  2 +-
 drivers/serial/serial_sh.c |  6 ++
 drivers/serial/serial_sh.h | 26 ++
 include/dm/platform_data/serial_sh.h   |  1 +
 4 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/doc/device-tree-bindings/serial/sh.txt 
b/doc/device-tree-bindings/serial/sh.txt
index 99634a5e70c..7707a9cbe38 100644
--- a/doc/device-tree-bindings/serial/sh.txt
+++ b/doc/device-tree-bindings/serial/sh.txt
@@ -1,6 +1,6 @@
 * Renesas SCI serial interface
 
 Required properties:
-- compatible: must be "renesas,scif", "renesas,scifa" or "renesas,sci"
+- compatible: must be "renesas,scif", "renesas,hscif", "renesas,scifa" or 
"renesas,sci"
 - reg: exactly one register range with length
 - clock: input clock frequency for the SCI unit
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index e08bdcadc9c..20cda5dbe27 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -57,6 +57,9 @@ static void sh_serial_init_generic(struct uart_port *port)
 #if defined(CONFIG_RZA1)
sci_out(port, SCSPTR, 0x0003);
 #endif
+
+   if (port->type == PORT_HSCIF)
+   sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8);
 }
 
 static void
@@ -205,6 +208,7 @@ static const struct udevice_id sh_serial_id[] ={
{.compatible = "renesas,sci", .data = PORT_SCI},
{.compatible = "renesas,scif", .data = PORT_SCIF},
{.compatible = "renesas,scifa", .data = PORT_SCIFA},
+   {.compatible = "renesas,hscif", .data = PORT_HSCIF},
{}
 };
 
@@ -257,6 +261,8 @@ U_BOOT_DRIVER(serial_sh) = {
#define SCIF_BASE_PORT  PORT_SCIFA
 #elif defined(CFG_SCI)
#define SCIF_BASE_PORT  PORT_SCI
+#elif defined(CFG_HSCIF)
+   #define SCIF_BASE_PORT  PORT_HSCIF
 #else
#define SCIF_BASE_PORT  PORT_SCIF
 #endif
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 128b0776dac..149ec1fe739 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -213,6 +213,10 @@ struct uart_port {
 #define SCFCR_TCRST 0x4000
 #define SCFCR_MCE   0x0008
 
+/* HSSRR */
+#define HSSRR_SRE  BIT(15)
+#define HSSRR_SRCYC8   0x0007
+
 #define SCI_MAJOR  204
 #define SCI_MINOR_START8
 
@@ -242,7 +246,8 @@ struct uart_port {
 
 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
-   if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
+   if (port->type == PORT_SCIF || port->type == PORT_SCIFB ||\
+   port->type == PORT_HSCIF) {\
SCI_IN(scif_size, scif_offset)\
} else { /* PORT_SCI or PORT_SCIFA */\
SCI_IN(sci_size, sci_offset);\
@@ -250,7 +255,8 @@ struct uart_port {
}\
 static inline void sci_##name##_out(struct uart_port *port,\
unsigned int value) {\
-   if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
+   if (port->type == PORT_SCIF || port->type == PORT_SCIFB ||\
+   port->type == PORT_HSCIF) {\
SCI_OUT(scif_size, scif_offset, value)\
} else {/* PORT_SCI or PORT_SCIFA */\
SCI_OUT(sci_size, sci_offset, value);\
@@ -375,6 +381,7 @@ SCIF_FNS(SCFDR,  0,  0, 0x1C, 16)
 SCIF_FNS(SCSPTR, 0,  0, 0x20, 16)
 SCIF_FNS(DL, 0,  0, 0x30, 16)
 SCIF_FNS(CKS,0,  0, 0x34, 16)
+SCIF_FNS(HSSRR,  0,  0, 0x40, 16) /* HSCIF only */
 #if defined(CFG_SCIF_A)
 SCIF_FNS(SCLSR,  0,  0, 0x14, 16)
 #else
@@ -414,7 +421,9 @@ SCIF_FNS(SCSPTR,0,  0, 0x20, 16)
 #endif
 SCIF_FNS(SCLSR,0,  0, 0x24, 16)
 #endif
-SCIF_FNS(DL,   0,  0, 0x0,  0) /* dummy */
+SCIF_FNS(DL,   0,  0, 0x30, 16)
+SCIF_FNS(CKS,  0,  0, 0x34, 16)
+SCIF_FNS(HSSRR,0,  0, 0x40, 16) /* HSCIF only 
*/
 #endif
 #define sci_in(port, reg) sci_##reg##_in(port)
 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
@@ -485,11 +494,20 @@ static inline int scbrr_calc(struct uart_port *port, int 
bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 #elif defined(CONFIG_RCAR_GEN2)
 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
- #if defined(CFG_SCIF_A)
+ #if defined(CFG_SCIF_A) || defined(CFG_HSCIF)
   #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
  #else
   #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
  #endif
+#elif defined(CONFIG_RCAR_64)
+static inline int scbrr_calc(struct 

[PATCH 1/2] serial: sh: Add R-Car Gen4 support

[Marek Vasut]

From: Hai Pham 

Add R-Car Gen4 family support. The basic function is as same as previous
R-Car Generation.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Swap RZ/A1 and Gen4 to keep the GenN sequence, use RCAR_64]
---
Cc: Simon Glass 
---
 drivers/serial/serial_sh.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index eb8523dde55..128b0776dac 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -89,7 +89,7 @@ struct uart_port {
 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
 # define SCSCR_INIT(port)  0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 # define SCIF_ORER 0x0001  /* overrun error bit */
-#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_64) || \
   defined(CONFIG_R7S72100)
 # if defined(CFG_SCIF_A)
 #  define SCIF_ORER0x0200
-- 
2.39.2

[PATCH] spi: renesas: Make driver available on R-Car Gen4

[Marek Vasut]

Use CONFIG_RCAR_64 to make the driver available on both
R-Car Gen3 and R-Car Gen4.

Signed-off-by: Marek Vasut 
---
Cc: Geert Uytterhoeven 
Cc: Jagan Teki 
Cc: Simon Glass 
Cc: Tom Rini 
---
 drivers/spi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index cdd2304aeb1..b1d4b6c5f89 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -381,7 +381,7 @@ config SPI_QUP
 
 config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver"
-   depends on RCAR_GEN3 || RZA1
+   depends on RCAR_64 || RZA1
imply SPI_FLASH_BAR
help
  Enable the Renesas RPC SPI driver, used to access SPI NOR flash
-- 
2.39.2

[PATCH] i2c: rcar_i2c: Add R-Car Gen4 support

[Marek Vasut]

From: Hai Pham 

Add support for R-Car Gen4 SoCs into the driver.

While I2C on R-Car Gen4 does support some extra features (Slave Clock
Stretch Select), for now it is treated the same as I2C on R-Car Gen3,
which let us share the same driver.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut  # Use RCAR_64 
Kconfig
---
Cc: Heiko Schocher 
---
 drivers/i2c/Kconfig| 2 +-
 drivers/i2c/rcar_i2c.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 1d998d14732..c32659b55a9 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -486,7 +486,7 @@ config SYS_I2C_OMAP24XX
 
 config SYS_I2C_RCAR_I2C
bool "Renesas RCar I2C driver"
-   depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C
+   depends on (RCAR_GEN2 || RCAR_64) && DM_I2C
help
  Support for Renesas RCar I2C controller.
 
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index d9ece5e3a80..ff9a2d80dda 100644
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -369,6 +369,7 @@ static const struct dm_i2c_ops rcar_i2c_ops = {
 static const struct udevice_id rcar_i2c_ids[] = {
{ .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
{ .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
+   { .compatible = "renesas,rcar-gen4-i2c", .data = RCAR_I2C_TYPE_GEN3 },
{ }
 };
 
-- 
2.39.2

[PATCH] mmc: renesas-sdhi: Add R-Car Gen4 support

[Marek Vasut]

From: Hai Pham 

Support R-Car Gen4 family. The default quirk is similar to previous
generation.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut  # Use RCAR_64 
Kconfig
---
 drivers/mmc/renesas-sdhi.c | 1 +
 drivers/mmc/tmio-common.c  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 34119f949aa..280d96dbc2d 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -843,6 +843,7 @@ static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
+   { .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
{ /* sentinel */ }
 };
 
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index d8b6a4a8821..8d7ee481d64 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -369,7 +369,7 @@ static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
return false;
 
-   if (IS_ENABLED(CONFIG_RCAR_GEN3)) {
+   if (IS_ENABLED(CONFIG_RCAR_64)) {
if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
return false;
/* Gen3 DMA has 32bit limit */
-- 
2.39.2

[PATCH] gpio: renesas: Add R-Car Gen4 support

[Marek Vasut]

From: Hai Pham 

Add support for the GPIO controller block in the R-Car Gen4 family.

It has a General Input Enable Register (INEN), whose reset state is to
have all inputs disabled.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
---
 drivers/gpio/gpio-rcar.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 138801850d3..9ffb4a56258 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -195,6 +195,7 @@ static const struct udevice_id rcar_gpio_ids[] = {
{ .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN },
{ .compatible = "renesas,rcar-gen2-gpio" },
{ .compatible = "renesas,rcar-gen3-gpio" },
+   { .compatible = "renesas,rcar-gen4-gpio", .data = RCAR_GPIO_HAS_INEN },
{ /* sentinel */ }
 };
 
-- 
2.39.2

[PATCH v5 21/21] include: fdtdec: decouple fdt_addr_t and phys_addr_t size

[Johan Jonker]

The DT specification supports CPUs with both 32-bit and 64-bit addressing
capabilities. In U-boot the fdt_addr_t and phys_addr_t size are coupled
by a typedef. The MTD NAND drivers for 32-bit CPU's can describe partitions
with a 64-bit reg property. These partitions synced from Linux end up with
the wrong offset and sizes when only the lower 32-bit is passed.
Decouple the fdt_addr_t and phys_addr_t size as they don't necessary
match.

Signed-off-by: Johan Jonker 
Reviewed-by: Simon Glass 
Reviewed-by: Kever Yang 
---

Note:
  Due to the large number of references to fdt_addr_t
  this patch serie fixes only some bugs, but not all.
  Apply only when all remaining errors and warnings
  due to this patch are fixed.
  Help with testing/debug appreciated.
---
 Kconfig  |  8 
 include/fdtdec.h | 13 +
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/Kconfig b/Kconfig
index a75cce7e..7697dade 100644
--- a/Kconfig
+++ b/Kconfig
@@ -422,11 +422,19 @@ endif # EXPERT

 config PHYS_64BIT
bool "64bit physical address support"
+   select FDT_64BIT
help
  Say Y here to support 64bit physical memory address.
  This can be used not only for 64bit SoCs, but also for
  large physical address extension on 32bit SoCs.

+config FDT_64BIT
+   bool "64bit fdt address support"
+   help
+ Say Y here to support 64bit fdt addresses.
+ This can be used not only for 64bit SoCs, but also
+ for large address extensions on 32bit SoCs.
+
 config HAS_ROM
bool
select BINMAN
diff --git a/include/fdtdec.h b/include/fdtdec.h
index aa61a0fc..6b768ed5 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -18,15 +18,18 @@
 #include 

 /*
- * A typedef for a physical address. Note that fdt data is always big
+ * Support for 64bit fdt addresses.
+ * This can be used not only for 64bit SoCs, but also
+ * for large address extensions on 32bit SoCs.
+ * Note that fdt data is always big
  * endian even on a litle endian machine.
  */
-typedef phys_addr_t fdt_addr_t;
-typedef phys_size_t fdt_size_t;

 #define FDT_SIZE_T_NONE (-1U)

-#ifdef CONFIG_PHYS_64BIT
+#ifdef CONFIG_FDT_64BIT
+typedef u64 fdt_addr_t;
+typedef u64 fdt_size_t;
 #define FDT_ADDR_T_NONE ((ulong)(-1))

 #define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
@@ -35,6 +38,8 @@ typedef phys_size_t fdt_size_t;
 #define cpu_to_fdt_size(reg) cpu_to_be64(reg)
 typedef fdt64_t fdt_val_t;
 #else
+typedef u32 fdt_addr_t;
+typedef u32 fdt_size_t;
 #define FDT_ADDR_T_NONE (-1U)

 #define fdt_addr_to_cpu(reg) be32_to_cpu(reg)
--
2.20.1

[PATCH v5 20/21] arm: stm32mp: spl: fix function with fdt_addr_t input

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so fix ofnode_get_addr_size function with fdt_addr_t input to
be able to handle both sizes for stm32mp SoC in spl.c file.

Signed-off-by: Johan Jonker 
---
 arch/arm/mach-stm32mp/spl.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index 19d9fe04..6b26641b 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -112,7 +112,7 @@ uint32_t stm32mp_get_dram_size(void)

 static int optee_get_reserved_memory(uint32_t *start, uint32_t *size)
 {
-   phys_size_t fdt_mem_size;
+   fdt_addr_t fdt_mem_size;
fdt_addr_t fdt_start;
ofnode node;

@@ -121,8 +121,8 @@ static int optee_get_reserved_memory(uint32_t *start, 
uint32_t *size)
return 0;

fdt_start = ofnode_get_addr_size(node, "reg", _mem_size);
-   *start = fdt_start;
-   *size = fdt_mem_size;
+   *start = (uint32_t)fdt_start;
+   *size = (uint32_t)fdt_mem_size;
return (fdt_start < 0) ? fdt_start : 0;
 }

--
2.20.1

[PATCH] ARM: rmobile: Add R-Car Generation 4 support

[Marek Vasut]

From: Hai Pham 

This adds R-Car Generation 4 (Gen4) support as Renesas ARM64 SoC.

In this version, reusing R-Car Gen3 lowlevel initialize routine [1]
and R-Car Gen3 memory map tables [2] .

[1] arch/arm/mach-rmobile/lowlevel_init_gen3.S
[2] arch/arm/mach-rmobile/memmap-gen3.c

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: - Enable DTO support by default
- Sort the Kconfig lists
- Select RCAR_64 Kconfig option to pull in all the shared
  Kconfig options with Gen3, and use where applicable to
  deduplicate entries.
- Fix reference [2] typo in commit message
- Drop config options moved to Kconfig, rename rest to CFG_
  accordingly to synchronize with upstream changes. Drop
  removed CONFIG_VERY_BIG_RAM.
- Move board size limit to arch/Kconfig
- Move GICR_BASE to headers instead of common config]
---
 Kconfig   |  6 +-
 arch/arm/mach-rmobile/Kconfig |  4 +
 arch/arm/mach-rmobile/Kconfig.64  |  1 +
 arch/arm/mach-rmobile/Kconfig.rcar4   |  8 ++
 arch/arm/mach-rmobile/Makefile|  2 +-
 arch/arm/mach-rmobile/cpu_info-rcar.c |  2 +-
 arch/arm/mach-rmobile/cpu_info.c  |  4 +-
 .../include/mach/rcar-gen4-base.h | 75 +++
 arch/arm/mach-rmobile/include/mach/rmobile.h  |  2 +
 board/renesas/rcar-common/common.c|  2 +-
 common/Kconfig|  2 +-
 include/configs/rcar-gen4-common.h| 30 
 12 files changed, 129 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/mach-rmobile/Kconfig.rcar4
 create mode 100644 arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h
 create mode 100644 include/configs/rcar-gen4-common.h

diff --git a/Kconfig b/Kconfig
index 6dd524b0acb..eac480c956e 100644
--- a/Kconfig
+++ b/Kconfig
@@ -454,7 +454,7 @@ config REMAKE_ELF
 
 config BUILD_TARGET
string "Build target special images"
-   default "u-boot-elf.srec" if RCAR_GEN3
+   default "u-boot-elf.srec" if RCAR_64
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 
&& SPL
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
@@ -473,14 +473,14 @@ config BUILD_TARGET
 
 config HAS_BOARD_SIZE_LIMIT
bool "Define a maximum size for the U-Boot image"
-   default y if RCAR_GEN3
+   default y if RCAR_64
help
  In some cases, we need to enforce a hard limit on how big the U-Boot
  image itself can be.
 
 config BOARD_SIZE_LIMIT
int "Maximum size of the U-Boot image in bytes"
-   default 1048576 if RCAR_GEN3
+   default 1048576 if RCAR_64
depends on HAS_BOARD_SIZE_LIMIT
help
  Maximum size of the U-Boot image. When defined, the build system
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 921153a8d9e..1ef7d68bdf3 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -40,6 +40,10 @@ config RCAR_GEN3
imply SPL_USE_TINY_PRINTF
imply SPL_YMODEM_SUPPORT
 
+config RCAR_GEN4
+   bool "Renesas ARM SoCs R-Car Gen4 (64bit)"
+   select RCAR_64
+
 config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
select CPU_V7A
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 3b14721dab5..57ed1d6c50d 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -7,5 +7,6 @@ config OF_LIBFDT_OVERLAY
default y if RCAR_64
 
 source "arch/arm/mach-rmobile/Kconfig.rcar3"
+source "arch/arm/mach-rmobile/Kconfig.rcar4"
 
 endif
diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
b/arch/arm/mach-rmobile/Kconfig.rcar4
new file mode 100644
index 000..6d9e16586d9
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.rcar4
@@ -0,0 +1,8 @@
+if RCAR_GEN4
+
+choice
+   prompt "Renesas ARM64 SoCs board select"
+   optional
+endchoice
+
+endif
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 5b86221bc25..fadb6eb0ab6 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
 obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
 
 ifneq ($(CONFIG_R8A779A0),)
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c 
b/arch/arm/mach-rmobile/cpu_info-rcar.c
index ac9c623eda7..62017f52c3b 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c

[PATCH v5 19/21] drivers: fix debug string with fdt_addr_t input

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.

Signed-off-by: Johan Jonker 
---

Changed V5:
  new patch
---
 arch/arm/mach-mvebu/cpu.c   | 2 +-
 drivers/clk/ti/clk-ctrl.c   | 9 +
 drivers/phy/phy-stm32-usbphyc.c | 4 ++--
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 329d1369..f58689e1 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -631,7 +631,7 @@ int board_xhci_enable(fdt_addr_t base)
 {
const struct mbus_dram_target_info *dram;

-   printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
+   printf("MVEBU XHCI INIT controller @ 0x%llx\n", (fdt64_t)base);

dram = mvebu_mbus_dram_info();
xhci_mvebu_mbus_config((void __iomem *)base, dram);
diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c
index 6cc02d2e..8926e57e 100644
--- a/drivers/clk/ti/clk-ctrl.c
+++ b/drivers/clk/ti/clk-ctrl.c
@@ -44,7 +44,7 @@ static int clk_ti_ctrl_disable(struct clk *clk)
offs = priv->offs[0].start + clk->id;
err = clk_ti_ctrl_check_offs(clk, offs);
if (err) {
-   dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+   dev_err(clk->dev, "invalid offset: 0x%llx\n", (fdt64_t)offs);
return err;
}

@@ -64,7 +64,7 @@ static int clk_ti_ctrl_enable(struct clk *clk)
offs = priv->offs[0].start + clk->id;
err = clk_ti_ctrl_check_offs(clk, offs);
if (err) {
-   dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+   dev_err(clk->dev, "invalid offset: 0x%llx\n", (fdt64_t)offs);
return err;
}

@@ -125,8 +125,9 @@ static int clk_ti_ctrl_of_to_plat(struct udevice *dev)
}

priv->offs[i].end = priv->offs[i].start + fdt_size;
-   dev_dbg(dev, "start=0x%08lx, end=0x%08lx\n",
-   priv->offs[i].start, priv->offs[i].end);
+   dev_dbg(dev, "start=0x%016llx, end=0x%016llx\n",
+   (fdt64_t)priv->offs[i].start,
+   (fdt64_t)priv->offs[i].end);
}

return 0;
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index dcf2194e..15bd60ca 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -583,8 +583,8 @@ static int stm32_usbphyc_probe(struct udevice *dev)

phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
if (phy_id >= MAX_PHYS) {
-   dev_err(dev, "invalid reg value %lx for %s\n",
-   phy_id, ofnode_get_name(node));
+   dev_err(dev, "invalid reg value %llx for %s\n",
+   (fdt64_t)phy_id, ofnode_get_name(node));
return -ENOENT;
}

--
2.20.1

[PATCH v5 18/21] drivers: use devfdt_get_addr_ptr when cast to pointer

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_ptr instead of the devfdt_get_addr function in
the various files in the drivers directory that cast to a pointer.

Signed-off-by: Johan Jonker 
---

Changed V5:
  new patch
---
 doc/develop/driver-model/livetree.rst | 2 +-
 drivers/clk/at91/sama7g5.c| 2 +-
 drivers/clk/at91/sckc.c   | 2 +-
 drivers/spi/mtk_snor.c| 2 +-
 drivers/spi/mtk_spim.c| 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/doc/develop/driver-model/livetree.rst 
b/doc/develop/driver-model/livetree.rst
index e9149d73..07264660 100644
--- a/doc/develop/driver-model/livetree.rst
+++ b/doc/develop/driver-model/livetree.rst
@@ -94,7 +94,7 @@ For example, the old code may be like this:
 const void *blob = gd->fdt_blob;
 int node = dev_of_offset(bus);

-i2c_bus->regs = (struct i2c_ctlr *)devfdt_get_addr(dev);
+i2c_bus->regs = (struct i2c_ctlr *)devfdt_get_addr_ptr(dev);
 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 50);

 The new code is:
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index d1ec3c82..d00016b3 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -1114,7 +1114,7 @@ static const struct pmc_clk_setup {

 static int sama7g5_clk_probe(struct udevice *dev)
 {
-   void __iomem *base = (void *)devfdt_get_addr(dev);
+   void __iomem *base = (void __iomem *)devfdt_get_addr_ptr(dev);
unsigned int *clkmuxallocs[SAMA7G5_MAX_MUX_ALLOCS];
unsigned int *muxallocs[SAMA7G5_MAX_MUX_ALLOCS];
const char *p[10];
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 34ce611a..4a0ae983 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -123,7 +123,7 @@ U_BOOT_DRIVER(at91_sam9x60_td_slck) = {
 static int at91_sam9x60_sckc_probe(struct udevice *dev)
 {
struct sam9x60_sckc *sckc = dev_get_priv(dev);
-   void __iomem *base = (void *)devfdt_get_addr(dev);
+   void __iomem *base = (void __iomem *)devfdt_get_addr_ptr(dev);
const char *slow_rc_osc, *slow_osc;
const char *parents[2];
struct clk *clk, c;
diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c
index 04f588a7..1dc55052 100644
--- a/drivers/spi/mtk_snor.c
+++ b/drivers/spi/mtk_snor.c
@@ -470,7 +470,7 @@ static int mtk_snor_probe(struct udevice *bus)
int ret;
u32 reg;

-   priv->base = (void __iomem *)devfdt_get_addr(bus);
+   priv->base = (void __iomem *)devfdt_get_addr_ptr(bus);
if (!priv->base)
return -EINVAL;

diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c
index a7c0fc59..03275346 100644
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -641,7 +641,7 @@ static int mtk_spim_probe(struct udevice *dev)
struct mtk_spim_priv *priv = dev_get_priv(dev);
int ret;

-   priv->base = (void __iomem *)devfdt_get_addr(dev);
+   priv->base = (void __iomem *)devfdt_get_addr_ptr(dev);
if (!priv->base)
return -EINVAL;

--
2.20.1

[PATCH v5 17/21] drivers: use devfdt_get_addr_index_ptr when cast to pointer

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.

Signed-off-by: Johan Jonker 
---
 drivers/clk/clk-hsdk-cgu.c|  4 ++--
 drivers/ddr/altera/sdram_gen5.c   |  2 +-
 drivers/mmc/xenon_sdhci.c |  2 +-
 drivers/net/mvpp2.c   | 24 
 drivers/pci/pcie_dw_mvebu.c   |  4 ++--
 drivers/pci/pcie_imx.c|  4 ++--
 drivers/pci/pcie_layerscape_ep.c  |  4 ++--
 drivers/phy/marvell/comphy_core.c | 12 ++--
 drivers/spi/cadence_qspi.c|  2 +-
 drivers/usb/musb-new/ti-musb.c|  2 +-
 10 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 26b0aa9a..cf3d0fd3 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -753,11 +753,11 @@ static int hsdk_cgu_clk_probe(struct udevice *dev)
else
hsdk_clk->map = hsdk_4xd_clk_map;

-   hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
+   hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index_ptr(dev, 0);
if (!hsdk_clk->cgu_regs)
return -EINVAL;

-   hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
+   hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index_ptr(dev, 1);
if (!hsdk_clk->creg_regs)
return -EINVAL;

diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 8d3ce495..2cdfdd42 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -567,7 +567,7 @@ static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
 {
struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);

-   plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
+   plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index_ptr(dev, 0);
if (!plat->sdr)
return -ENODEV;

diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 2f880509..16ac84a2 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -537,7 +537,7 @@ static int xenon_sdhci_of_to_plat(struct udevice *dev)
host->ioaddr = dev_read_addr_ptr(dev);

if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
-   priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
+   priv->pad_ctrl_reg = devfdt_get_addr_index_ptr(dev, 1);

name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
   NULL);
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 1bad50d3..76471901 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5349,18 +5349,18 @@ static int mvpp2_base_probe(struct udevice *dev)
}

/* Save base addresses for later use */
-   priv->base = (void *)devfdt_get_addr_index(dev, 0);
-   if (IS_ERR(priv->base))
-   return PTR_ERR(priv->base);
+   priv->base = devfdt_get_addr_index_ptr(dev, 0);
+   if (!priv->base)
+   return -EINVAL;

if (priv->hw_version == MVPP21) {
-   priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
-   if (IS_ERR(priv->lms_base))
-   return PTR_ERR(priv->lms_base);
+   priv->lms_base = devfdt_get_addr_index_ptr(dev, 1);
+   if (!priv->lms_base)
+   return -EINVAL;
} else {
-   priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
-   if (IS_ERR(priv->iface_base))
-   return PTR_ERR(priv->iface_base);
+   priv->iface_base = devfdt_get_addr_index_ptr(dev, 1);
+   if (!priv->iface_base)
+   return -EINVAL;

/* Store common base addresses for all ports */
priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
@@ -5399,10 +5399,10 @@ static int mvpp2_probe(struct udevice *dev)
if (priv->hw_version == MVPP21) {
int priv_common_regs_num = 2;

-   port->base = (void __iomem *)devfdt_get_addr_index(
+   port->base = (void __iomem *)devfdt_get_addr_index_ptr(
dev->parent, priv_common_regs_num + port->id);
-   if (IS_ERR(port->base))
-   return PTR_ERR(port->base);
+   if (!port->base)
+   return -EINVAL;
} else {
port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  "gop-port-id", -1);
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 3b2ada54..c41f3f15 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -564,8 +564,8 @@ static int 

[PATCH v5 16/21] drivers: use devfdt_get_addr_size_index_ptr when cast to pointer

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index
function in the various files in the drivers directory that cast to
a pointer.

Signed-off-by: Johan Jonker 
Reviewed-by: Michael Trimarchi 
---
 drivers/pci/pcie_dw_mvebu.c | 6 +++---
 drivers/spi/cadence_qspi.c  | 3 +--
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index a0b82c78..3b2ada54 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -569,9 +569,9 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
return -EINVAL;

/* Get the config space base address and size */
-   pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
->cfg_size);
-   if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
+   pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1,
+   >cfg_size);
+   if (!pcie->cfg_base)
return -EINVAL;

return 0;
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index c7f10c50..6a52676a 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -384,8 +384,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus)
ofnode subnode;

plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
-   plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
-   >ahbsize);
+   plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, >ahbsize);
plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
--
2.20.1

[PATCH v5 15/21] drivers: use dev_read_addr_ptr when cast to pointer

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.

Signed-off-by: Johan Jonker 
---

Changed V2:
  rebase
  fix typo
  fix more files
---
 arch/arm/mach-mvebu/system-controller.c| 4 ++--
 doc/develop/driver-model/livetree.rst  | 2 +-
 drivers/ata/dwc_ahsata.c   | 2 +-
 drivers/cache/cache-l2x0.c | 2 +-
 drivers/cache/cache-v5l2.c | 2 +-
 drivers/gpio/mscc_sgpio.c  | 2 +-
 drivers/gpio/tegra_gpio.c  | 4 ++--
 drivers/gpio/xilinx_gpio.c | 2 +-
 drivers/i2c/i2c-cdns.c | 2 +-
 drivers/i2c/tegra_i2c.c| 4 ++--
 drivers/mmc/am654_sdhci.c  | 2 +-
 drivers/mmc/davinci_mmc.c  | 2 +-
 drivers/mmc/piton_mmc.c| 2 +-
 drivers/mmc/tegra_mmc.c| 2 +-
 drivers/mmc/zynq_sdhci.c   | 6 +++---
 drivers/mtd/nand/raw/arasan_nfc.c  | 2 +-
 drivers/mtd/nand/raw/cortina_nand.c| 2 +-
 drivers/mtd/nand/raw/mxic_nand.c   | 2 +-
 drivers/mtd/nand/raw/tegra_nand.c  | 2 +-
 drivers/mtd/nand/raw/zynq_nand.c   | 2 +-
 drivers/net/mvmdio.c   | 2 +-
 drivers/net/qe/dm_qe_uec_phy.c | 2 +-
 drivers/pci/pci-aardvark.c | 4 ++--
 drivers/phy/allwinner/phy-sun50i-usb3.c| 6 +++---
 drivers/phy/qcom/phy-qcom-usb-hs-28nm.c| 4 ++--
 drivers/phy/qcom/phy-qcom-usb-ss.c | 4 ++--
 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 4 ++--
 drivers/phy/rockchip/phy-rockchip-typec.c  | 6 +++---
 drivers/pwm/tegra_pwm.c| 2 +-
 drivers/serial/serial_zynq.c   | 6 +++---
 drivers/spi/mpc8xxx_spi.c  | 2 +-
 drivers/spi/mscc_bb_spi.c  | 2 +-
 drivers/spi/sh_qspi.c  | 2 +-
 drivers/spi/spi-mxic.c | 2 +-
 drivers/spi/xilinx_spi.c   | 2 +-
 drivers/ufs/ufs.c  | 2 +-
 drivers/usb/host/ehci-tegra.c  | 2 +-
 drivers/video/dw_mipi_dsi.c| 4 ++--
 drivers/video/rockchip/rk_vop.c| 2 +-
 drivers/video/stm32/stm32_dsi.c| 4 ++--
 drivers/video/stm32/stm32_ltdc.c   | 4 ++--
 drivers/video/tegra124/display.c   | 2 +-
 drivers/video/tegra124/sor.c   | 6 +++---
 drivers/video/ti/tilcdc.c  | 4 ++--
 drivers/watchdog/cdns_wdt.c| 6 +++---
 drivers/watchdog/sp805_wdt.c   | 6 +++---
 drivers/watchdog/xilinx_tb_wdt.c   | 6 +++---
 47 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/arch/arm/mach-mvebu/system-controller.c 
b/arch/arm/mach-mvebu/system-controller.c
index e90aff0c..7cdde11c 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -71,8 +71,8 @@ static int mvebu_reset_of_to_plat(struct udevice *dev)
 {
struct mvebu_reset_data *data = dev_get_priv(dev);

-   data->base = (void *)dev_read_addr(dev);
-   if ((fdt_addr_t)data->base == FDT_ADDR_T_NONE)
+   data->base = dev_read_addr_ptr(dev);
+   if (!data->base)
return -EINVAL;

return 0;
diff --git a/doc/develop/driver-model/livetree.rst 
b/doc/develop/driver-model/livetree.rst
index 579eef5c..e9149d73 100644
--- a/doc/develop/driver-model/livetree.rst
+++ b/doc/develop/driver-model/livetree.rst
@@ -103,7 +103,7 @@ The new code is:

 struct udevice *bus;

-i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
+i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr_ptr(dev);
 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 50);

 The dev_read\_...() interface is more convenient and works with both the
diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index 167b5a39..9ed7348b 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -912,7 +912,7 @@ int dwc_ahsata_probe(struct udevice *dev)
 #endif
uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
-   uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
+   uc_priv->mmio_base = (void __iomem *)dev_read_addr_ptr(dev);

/* initialize adapter */
ret = ahci_host_init(uc_priv);
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
index a1556fbf..70b31899 100644
--- a/drivers/cache/cache-l2x0.c
+++ b/drivers/cache/cache-l2x0.c
@@ -13,7 +13,7 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
 {
 

[PATCH v5 14/21] drivers: use dev_read_addr_index_ptr when cast to pointer

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_index_ptr instead of the dev_read_addr_index function
in the various files in the drivers directory that cast to a pointer.

Signed-off-by: Johan Jonker 
Reviewed-by: Michael Trimarchi 
---
 drivers/mtd/nand/raw/cortina_nand.c |  4 ++--
 drivers/net/dm9000x.c   |  2 +-
 drivers/net/dwmac_meson8b.c |  4 ++--
 drivers/pci/pcie_dw_meson.c |  4 ++--
 drivers/pci/pcie_dw_rockchip.c  |  4 ++--
 drivers/watchdog/sbsa_gwdt.c| 12 ++--
 6 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/mtd/nand/raw/cortina_nand.c 
b/drivers/mtd/nand/raw/cortina_nand.c
index 88798f23..b03f3821 100644
--- a/drivers/mtd/nand/raw/cortina_nand.c
+++ b/drivers/mtd/nand/raw/cortina_nand.c
@@ -1175,8 +1175,8 @@ static int fdt_decode_nand(struct udevice *dev, struct 
nand_drv *info)
int ecc_strength;

info->reg = (struct nand_ctlr *)dev_read_addr(dev);
-   info->dma_glb = (struct dma_global *)dev_read_addr_index(dev, 1);
-   info->dma_nand = (struct dma_ssp *)dev_read_addr_index(dev, 2);
+   info->dma_glb = (struct dma_global *)dev_read_addr_index_ptr(dev, 1);
+   info->dma_nand = (struct dma_ssp *)dev_read_addr_index_ptr(dev, 2);
info->config.enabled = dev_read_enabled(dev);
ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 16);
info->flash_base =
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index b46bdeb2..5855f16b 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -651,7 +651,7 @@ static int dm9000_of_to_plat(struct udevice *dev)

pdata->iobase = dev_read_addr_index(dev, 0);
db->base_io = (void __iomem *)pdata->iobase;
-   db->base_data = (void __iomem *)dev_read_addr_index(dev, 1);
+   db->base_data = (void __iomem *)dev_read_addr_index_ptr(dev, 1);

return 0;
 }
diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c
index ddbaa87d..871171e1 100644
--- a/drivers/net/dwmac_meson8b.c
+++ b/drivers/net/dwmac_meson8b.c
@@ -41,8 +41,8 @@ static int dwmac_meson8b_of_to_plat(struct udevice *dev)
 {
struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);

-   pdata->regs = (void *)dev_read_addr_index(dev, 1);
-   if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE)
+   pdata->regs = dev_read_addr_index_ptr(dev, 1);
+   if (!pdata->regs)
return -EINVAL;

pdata->dwmac_setup = (void *)dev_get_driver_data(dev);
diff --git a/drivers/pci/pcie_dw_meson.c b/drivers/pci/pcie_dw_meson.c
index 07da9fa5..59567883 100644
--- a/drivers/pci/pcie_dw_meson.c
+++ b/drivers/pci/pcie_dw_meson.c
@@ -337,13 +337,13 @@ static int meson_pcie_parse_dt(struct udevice *dev)
struct meson_pcie *priv = dev_get_priv(dev);
int ret;

-   priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
+   priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0);
if (!priv->dw.dbi_base)
return -ENODEV;

dev_dbg(dev, "ELBI address is 0x%p\n", priv->dw.dbi_base);

-   priv->meson_cfg_base = (void *)dev_read_addr_index(dev, 1);
+   priv->meson_cfg_base = dev_read_addr_index_ptr(dev, 1);
if (!priv->meson_cfg_base)
return -ENODEV;

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 9322e735..2608106b 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -353,13 +353,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
struct rk_pcie *priv = dev_get_priv(dev);
int ret;

-   priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
+   priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0);
if (!priv->dw.dbi_base)
return -ENODEV;

dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);

-   priv->apb_base = (void *)dev_read_addr_index(dev, 1);
+   priv->apb_base = dev_read_addr_index_ptr(dev, 1);
if (!priv->apb_base)
return -ENODEV;

diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
index f43cd3fd..ef402898 100644
--- a/drivers/watchdog/sbsa_gwdt.c
+++ b/drivers/watchdog/sbsa_gwdt.c
@@ -98,13 +98,13 @@ static int sbsa_gwdt_of_to_plat(struct udevice *dev)
 {
struct sbsa_gwdt_priv *priv = dev_get_priv(dev);

-   priv->reg_control = (void __iomem *)dev_read_addr_index(dev, 0);
-   if (IS_ERR(priv->reg_control))
-   return PTR_ERR(priv->reg_control);
+   priv->reg_control = (void __iomem *)dev_read_addr_index_ptr(dev, 0);
+   if (!priv->reg_control)
+   return -EINVAL;

-   priv->reg_refresh = (void __iomem *)dev_read_addr_index(dev, 1);
-   if (IS_ERR(priv->reg_refresh))
-   return PTR_ERR(priv->reg_refresh);
+   priv->reg_refresh = (void __iomem *)dev_read_addr_index_ptr(dev, 

[PATCH v5 13/21] spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr
function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able
to handle both sizes.

Signed-off-by: Johan Jonker 
Reviewed-by: Michael Trimarchi 
---
 drivers/spi/spi-aspeed-smc.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 4b6ea9f8..2be9280a 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -1125,15 +1125,14 @@ static int apseed_spi_of_to_plat(struct udevice *bus)
int ret;
struct clk hclk;

-   priv->regs = (void __iomem *)devfdt_get_addr_index(bus, 0);
-   if ((u32)priv->regs == FDT_ADDR_T_NONE) {
+   priv->regs = devfdt_get_addr_index_ptr(bus, 0);
+   if (!priv->regs) {
dev_err(bus, "wrong ctrl base\n");
return -ENODEV;
}

-   plat->ahb_base =
-   (void __iomem *)devfdt_get_addr_size_index(bus, 1, 
>ahb_sz);
-   if ((u32)plat->ahb_base == FDT_ADDR_T_NONE) {
+   plat->ahb_base = devfdt_get_addr_size_index_ptr(bus, 1, >ahb_sz);
+   if (!plat->ahb_base) {
dev_err(bus, "wrong AHB base\n");
return -ENODEV;
}
@@ -1151,8 +1150,8 @@ static int apseed_spi_of_to_plat(struct udevice *bus)
plat->hclk_rate = clk_get_rate();
clk_free();

-   dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%lx\n",
-   (u32)priv->regs, plat->ahb_base, plat->ahb_sz);
+   dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n",
+   (u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz);
dev_dbg(bus, "hclk = %dMHz, max_cs = %d\n",
plat->hclk_rate / 100, plat->max_cs);

--
2.20.1

[PATCH v5 12/21] core: read: add dev_read_addr_index_ptr function

[Johan Jonker]

Add dev_read_addr_index_ptr function with the same
functionality as dev_read_addr_index, but instead
a return pointer is given.

Signed-off-by: Johan Jonker 
---

Changed V5:
  new patch
---
 drivers/core/read.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/core/read.c b/drivers/core/read.c
index e0543bba..85c46913 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -131,6 +131,13 @@ fdt_addr_t dev_read_addr_index(const struct udevice *dev, 
int index)
return devfdt_get_addr_index(dev, index);
 }

+void *dev_read_addr_index_ptr(const struct udevice *dev, int index)
+{
+   fdt_addr_t addr = dev_read_addr_index(dev, index);
+
+   return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+}
+
 fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size)
 {
--
2.20.1

[PATCH v5 11/21] core: fdtaddr: add devfdt_get_addr_size_index_ptr function

[Johan Jonker]

Add devfdt_get_addr_size_index_ptr function with the same
functionality as devfdt_get_addr_size_index, but instead
a return pointer is given.

Suggested-by: Michael Nazzareno Trimarchi 
Signed-off-by: Johan Jonker 
Reviewed-by: Michael Trimarchi 
---

Changed V5:
  fix spelling
  use tabs
---
 drivers/core/fdtaddr.c |  8 
 include/dm/fdtaddr.h   | 17 -
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 91bcd1a2..f5906ff9 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -122,6 +122,14 @@ fdt_addr_t devfdt_get_addr_size_index(const struct udevice 
*dev, int index,
 #endif
 }

+void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index,
+fdt_size_t *size)
+{
+   fdt_addr_t addr = devfdt_get_addr_size_index(dev, index, size);
+
+   return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+}
+
 fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)
diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h
index c9d2b27b..dcdc1913 100644
--- a/include/dm/fdtaddr.h
+++ b/include/dm/fdtaddr.h
@@ -111,7 +111,7 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev, 
int index);
  * @dev: Pointer to a device
  * @index: the 'reg' property can hold a list of  pairs
  *and @index is used to select which one is required
- * @size: Pointer to size varible - this function returns the size
+ * @size: Pointer to size variable - this function returns the size
  *specified in the 'reg' property here
  *
  * Return: addr
@@ -119,6 +119,21 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev, 
int index);
 fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
  fdt_size_t *size);

+/**
+ * devfdt_get_addr_size_index_ptr() - Return indexed pointer to the address of 
the
+ *reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of  pairs
+ *and @index is used to select which one is required
+ * @size: Pointer to size variable - this function returns the size
+ *specified in the 'reg' property here
+ *
+ * Return: Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index,
+fdt_size_t *size);
+
 /**
  * devfdt_get_addr_name() - Get the reg property of a device, indexed by name
  *
--
2.20.1

[PATCH] serial: sh: Make indent consistent

[Marek Vasut]

Make the indent of these macro elements consistent with the
rest of this table. No functional change.

Signed-off-by: Marek Vasut 
---
 drivers/serial/serial_sh.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 660aaab6638..eb8523dde55 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -406,13 +406,13 @@ SCIF_FNS(SCSPTR,  0,  0, 0x24, 16)
 SCIF_FNS(SCLSR,0,  0, 0x28, 16)
 #else
 
-SCIF_FNS(SCFDR,  0x0e, 16, 0x1C, 16)
+SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
 #if defined(CONFIG_CPU_SH7722)
-SCIF_FNS(SCSPTR,0,  0, 0, 0)
+SCIF_FNS(SCSPTR,   0,  0, 0, 0)
 #else
-SCIF_FNS(SCSPTR,0,  0, 0x20, 16)
+SCIF_FNS(SCSPTR,   0,  0, 0x20, 16)
 #endif
-SCIF_FNS(SCLSR, 0,  0, 0x24, 16)
+SCIF_FNS(SCLSR,0,  0, 0x24, 16)
 #endif
 SCIF_FNS(DL,   0,  0, 0x0,  0) /* dummy */
 #endif
-- 
2.39.2

[PATCH v5 10/21] core: remap: convert regmap_init_mem_plat() input to phys_addr_t

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to phys_addr_t in files
that use this function. Also correct struct syscon_base_plat
depending on CONFIG_PHYS_64BIT setting and fix ARRAY_SIZE
divider.

Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang 
---
 drivers/core/regmap.c   |  2 +-
 drivers/core/syscon-uclass.c|  4 ++--
 drivers/ram/rockchip/sdram_rk3066.c |  2 +-
 drivers/ram/rockchip/sdram_rk3188.c |  2 +-
 drivers/ram/rockchip/sdram_rk322x.c |  2 +-
 drivers/ram/rockchip/sdram_rk3288.c |  2 +-
 drivers/ram/rockchip/sdram_rk3328.c |  2 +-
 drivers/ram/rockchip/sdram_rk3399.c |  2 +-
 include/regmap.h|  2 +-
 include/syscon.h| 13 +++--
 10 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index e33bb9d7..37da64b2 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -79,7 +79,7 @@ static struct regmap *regmap_alloc(int count)
 }

 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count,
+int regmap_init_mem_plat(struct udevice *dev, phys_addr_t *reg, int count,
 struct regmap **mapp)
 {
struct regmap_range *range;
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 25fdb66e..b557a24f 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -58,8 +58,8 @@ static int syscon_pre_probe(struct udevice *dev)
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
struct syscon_base_plat *plat = dev_get_plat(dev);

-   return regmap_init_mem_plat(dev, plat->reg, ARRAY_SIZE(plat->reg),
-   >regmap);
+   return regmap_init_mem_plat(dev, (phys_addr_t *)plat->reg,
+   ARRAY_SIZE(plat->reg) / 2, >regmap);
 #else
return regmap_init_mem(dev_ofnode(dev), >regmap);
 #endif
diff --git a/drivers/ram/rockchip/sdram_rk3066.c 
b/drivers/ram/rockchip/sdram_rk3066.c
index a2425f22..9bb26b64 100644
--- a/drivers/ram/rockchip/sdram_rk3066.c
+++ b/drivers/ram/rockchip/sdram_rk3066.c
@@ -801,7 +801,7 @@ static int rk3066_dmc_conv_of_plat(struct udevice *dev)
memcpy(>base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* RK3066 supports dual-channel, set default channel num to 2. */
plat->num_channels = 1;
-   ret = regmap_init_mem_plat(dev, of_plat->reg,
+   ret = regmap_init_mem_plat(dev, (phys_addr_t *)of_plat->reg,
   ARRAY_SIZE(of_plat->reg) / 2, >map);
if (ret)
return ret;
diff --git a/drivers/ram/rockchip/sdram_rk3188.c 
b/drivers/ram/rockchip/sdram_rk3188.c
index 272b1b2d..1838985c 100644
--- a/drivers/ram/rockchip/sdram_rk3188.c
+++ b/drivers/ram/rockchip/sdram_rk3188.c
@@ -867,7 +867,7 @@ static int conv_of_plat(struct udevice *dev)
memcpy(>base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* rk3188 supports dual-channel, set default channel num to 2 */
plat->num_channels = 1;
-   ret = regmap_init_mem_plat(dev, of_plat->reg,
+   ret = regmap_init_mem_plat(dev, (phys_addr_t *)of_plat->reg,
   ARRAY_SIZE(of_plat->reg) / 2, >map);
if (ret)
return ret;
diff --git a/drivers/ram/rockchip/sdram_rk322x.c 
b/drivers/ram/rockchip/sdram_rk322x.c
index 1b204fb5..33599dc5 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -769,7 +769,7 @@ static int conv_of_plat(struct udevice *dev)
memcpy(>base, of_plat->rockchip_sdram_params, sizeof(plat->base));

plat->num_channels = 1;
-   ret = regmap_init_mem_plat(dev, of_plat->reg,
+   ret = regmap_init_mem_plat(dev, (phys_addr_t *)of_plat->reg,
   ARRAY_SIZE(of_plat->reg) / 2, >map);
if (ret)
return ret;
diff --git a/drivers/ram/rockchip/sdram_rk3288.c 
b/drivers/ram/rockchip/sdram_rk3288.c
index 83778ad1..1a548da5 100644
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c
@@ -1029,7 +1029,7 @@ static int conv_of_plat(struct udevice *dev)
memcpy(>base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* Rk3288 supports dual-channel, set default channel num to 2 */
plat->num_channels = 2;
-   ret = regmap_init_mem_plat(dev, of_plat->reg,
+   ret = regmap_init_mem_plat(dev, (phys_addr_t *)of_plat->reg,
   ARRAY_SIZE(of_plat->reg) / 2, >map);
if (ret)
return ret;
diff --git a/drivers/ram/rockchip/sdram_rk3328.c 
b/drivers/ram/rockchip/sdram_rk3328.c
index 184c93f7..41da7ca2 100644
--- a/drivers/ram/rockchip/sdram_rk3328.c
+++ b/drivers/ram/rockchip/sdram_rk3328.c
@@ -54,7 +54,7 @@ static int 

[PATCH v2 1/2] mmc: tmio: Check 'addr' width before checking for 64bit limitation

[Marek Vasut]

The 64bit limitation check is compiled and optimized out on 32bit
platforms, but generates a type width warning:

drivers/mmc/tmio-common.c: In function ‘tmio_sd_addr_is_dmaable’:
drivers/mmc/tmio-common.c:376:26: warning: right shift count >= width of type 
[-Wshift-count-overflow]
  376 | if (addr >> 32)
  |  ^~

Fix the warning by checking the addr type width to see whether the
shift even makes sense in the first place. The width check is also
optimized out at compile time.

Signed-off-by: Marek Vasut 
---
Cc: Jaehoon Chung 
Cc: Peng Fan 
---
V2: New patch
---
 drivers/mmc/tmio-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index e9c7d3a2e00..0b24a5a7bdb 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -373,7 +373,7 @@ static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
return false;
/* Gen3 DMA has 32bit limit */
-   if (addr >> 32)
+   if (sizeof(addr) > 4 && addr >> 32)
return false;
 #endif
 
-- 
2.39.2

[PATCH v5 09/21] include: dm: ofnode: fix headers

[Johan Jonker]

When fdt_addr_t and phys_addr_t are split it turns out that
the header don't match the functions, so fix the headers.

Signed-off-by: Johan Jonker 
Reviewed-by: Simon Glass 
Reviewed-by: Kever Yang 
---
 include/dm/ofnode.h | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 3f6b0843..cd966f6a 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -678,8 +678,8 @@ int ofnode_read_size(ofnode node, const char *propname);
  * @size: Pointer to size of the address
  * Return: address, or FDT_ADDR_T_NONE if not present or invalid
  */
-phys_addr_t ofnode_get_addr_size_index(ofnode node, int index,
-  fdt_size_t *size);
+fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index,
+ fdt_size_t *size);

 /**
  * ofnode_get_addr_size_index_notrans() - get an address/size from a node
@@ -695,8 +695,8 @@ phys_addr_t ofnode_get_addr_size_index(ofnode node, int 
index,
  * @size: Pointer to size of the address
  * Return: address, or FDT_ADDR_T_NONE if not present or invalid
  */
-phys_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index,
-  fdt_size_t *size);
+fdt_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index,
+ fdt_size_t *size);

 /**
  * ofnode_get_addr_index() - get an address from a node
@@ -707,7 +707,7 @@ phys_addr_t ofnode_get_addr_size_index_notrans(ofnode node, 
int index,
  * @index: Index of address to read (0 for first)
  * Return: address, or FDT_ADDR_T_NONE if not present or invalid
  */
-phys_addr_t ofnode_get_addr_index(ofnode node, int index);
+fdt_addr_t ofnode_get_addr_index(ofnode node, int index);

 /**
  * ofnode_get_addr() - get an address from a node
@@ -717,7 +717,7 @@ phys_addr_t ofnode_get_addr_index(ofnode node, int index);
  * @node: node to read from
  * Return: address, or FDT_ADDR_T_NONE if not present or invalid
  */
-phys_addr_t ofnode_get_addr(ofnode node);
+fdt_addr_t ofnode_get_addr(ofnode node);

 /**
  * ofnode_get_size() - get size from a node
@@ -1067,8 +1067,8 @@ const void *ofprop_get_property(const struct ofprop *prop,
  * @sizep: place to put size value (on success)
  * Return: address value, or FDT_ADDR_T_NONE on error
  */
-phys_addr_t ofnode_get_addr_size(ofnode node, const char *propname,
-phys_size_t *sizep);
+fdt_addr_t ofnode_get_addr_size(ofnode node, const char *propname,
+   fdt_size_t *sizep);

 /**
  * ofnode_read_u8_array_ptr() - find an 8-bit array
--
2.20.1

[PATCH v2 2/2] mmc: tmio: Replace ifdeffery with IS_ENABLED/CONFIG_IS_ENABLED macros

[Marek Vasut]

Instead of #if and #ifdef, use IS_ENABLED and CONFIG_IS_ENABLED macros.
This improves build test coverage. The CONFIG_SPL_BUILD must remain an
ifdef, as CONFIG_SPL_STACK may not always be defined, e.g. in U-Boot
proper build. No functional change.

Signed-off-by: Marek Vasut 
---
Cc: Jaehoon Chung 
Cc: Peng Fan 
---
V2: - Rebase on 1/2
- Drop DM_REGULATOR check from struct tmio_sd_priv in tmio-common.h
---
 drivers/mmc/tmio-common.c | 59 +++
 drivers/mmc/tmio-common.h |  2 --
 2 files changed, 29 insertions(+), 32 deletions(-)

diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 0b24a5a7bdb..d8b6a4a8821 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -369,22 +369,23 @@ static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
return false;
 
-#if defined(CONFIG_RCAR_GEN3)
-   if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
-   return false;
-   /* Gen3 DMA has 32bit limit */
-   if (sizeof(addr) > 4 && addr >> 32)
-   return false;
-#endif
+   if (IS_ENABLED(CONFIG_RCAR_GEN3)) {
+   if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
+   return false;
+   /* Gen3 DMA has 32bit limit */
+   if (sizeof(addr) > 4 && addr >> 32)
+   return false;
+   }
 
-#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
-   defined(CONFIG_SPL_BUILD)
-   /*
-* For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
-* of L2, which is unreachable from the DMA engine.
-*/
-   if (addr < CONFIG_SPL_STACK)
-   return false;
+#ifdef CONFIG_SPL_BUILD
+   if (IS_ENABLED(CONFIG_ARCH_UNIPHIER) && 
!CONFIG_IS_ENABLED(CONFIG_ARM64)) {
+   /*
+* For UniPhier ARMv7 SoCs, the stack is allocated in locked
+* ways of L2, which is unreachable from the DMA engine.
+*/
+   if (addr < CONFIG_SPL_STACK)
+   return false;
+   }
 #endif
 
return true;
@@ -622,25 +623,22 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv 
*priv, struct mmc *mmc)
 static void tmio_sd_set_pins(struct udevice *dev)
 {
__maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
-
-#ifdef CONFIG_DM_REGULATOR
struct tmio_sd_priv *priv = dev_get_priv(dev);
 
-   if (priv->vqmmc_dev) {
+   if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->vqmmc_dev) {
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
regulator_set_value(priv->vqmmc_dev, 180);
else
regulator_set_value(priv->vqmmc_dev, 330);
regulator_set_enable(priv->vqmmc_dev, true);
}
-#endif
 
-#ifdef CONFIG_PINCTRL
-   if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
-   pinctrl_select_state(dev, "state_uhs");
-   else
-   pinctrl_select_state(dev, "default");
-#endif
+   if (CONFIG_IS_ENABLED(PINCTRL)) {
+   if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+   pinctrl_select_state(dev, "state_uhs");
+   else
+   pinctrl_select_state(dev, "default");
+   }
 }
 
 int tmio_sd_set_ios(struct udevice *dev)
@@ -734,11 +732,12 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
if (!priv->regbase)
return -ENOMEM;
 
-#ifdef CONFIG_DM_REGULATOR
-   device_get_supply_regulator(dev, "vqmmc-supply", >vqmmc_dev);
-   if (priv->vqmmc_dev)
-   regulator_set_value(priv->vqmmc_dev, 330);
-#endif
+   if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+   device_get_supply_regulator(dev, "vqmmc-supply",
+   >vqmmc_dev);
+   if (priv->vqmmc_dev)
+   regulator_set_value(priv->vqmmc_dev, 330);
+   }
 
ret = mmc_of_parse(dev, >cfg);
if (ret < 0) {
diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h
index 4d717d85dec..f489fb70766 100644
--- a/drivers/mmc/tmio-common.h
+++ b/drivers/mmc/tmio-common.h
@@ -133,9 +133,7 @@ struct tmio_sd_priv {
 #define TMIO_SD_CAP_RCAR_UHS   BIT(7)  /* Renesas RCar UHS/SDR modes */
 #define TMIO_SD_CAP_RCAR   \
(TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3)
-#ifdef CONFIG_DM_REGULATOR
struct udevice *vqmmc_dev;
-#endif
 #if CONFIG_IS_ENABLED(CLK)
struct clk  clk;
struct clk  clkh;
-- 
2.39.2

[PATCH v5 08/21] rockchip: timer: dw-apb-timer: convert dev_read_addr output to phys_addr_t

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert dev_read_addr output to phys_addr_t in the
dw-apb-timer.c file.

Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang 
---
 drivers/timer/dw-apb-timer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 10f0a9f6..f55a3c54 100644
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -23,7 +23,7 @@
 #define DW_APB_CTRL0x8

 struct dw_apb_timer_priv {
-   fdt_addr_t regs;
+   phys_addr_t regs;
struct reset_ctl_bulk resets;
 };

@@ -92,7 +92,7 @@ static int dw_apb_timer_of_to_plat(struct udevice *dev)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct dw_apb_timer_priv *priv = dev_get_priv(dev);

-   priv->regs = dev_read_addr(dev);
+   priv->regs = (phys_addr_t)dev_read_addr(dev);
}

return 0;
--
2.20.1

[PATCH v5 07/21] rockchip: adc: rockchip-saradc: use dev_read_addr_ptr

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip-saradc.c file.

Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang 
---
 drivers/adc/rockchip-saradc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index 760f8fe6..de9298a2 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -145,8 +145,8 @@ int rockchip_saradc_of_to_plat(struct udevice *dev)
struct rockchip_saradc_data *data;

data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
-   priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev);
-   if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) {
+   priv->regs = (struct rockchip_saradc_regs *)dev_read_addr_ptr(dev);
+   if (!priv->regs) {
pr_err("Dev: %s - can't get address!", dev->name);
return -ENODATA;
}
--
2.20.1

[PATCH 2/2] serial: sh: Add DEBUG_UART support

[Marek Vasut]

Add support for debug output very early during boot using the DEBUG_UART
mechanism. This uses a static fixed UART port configuration selected via
Kconfig options and dedicated print functions from debug_uart.h. This is
useful e.g. when debugging problems so early during boot, that not even
the DM is initialized at that point, and thus DM_SERIAL is not available
either.

This functionality is disabled by default. To activate it, define the
following Kconfig options and select SCIF type using CFG_SCI/CFG_SCIF_A/
CFG_HSCIF/:

CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_SCIF=y
CONFIG_DEBUG_UART_BASE=0xe654
CONFIG_DEBUG_UART_CLOCK=2400

The later two options define the SCIF physical base address and SCIF
input clock in Hz. Optionally, to validate DEBUG_UART works, enable
the following as well to get early serial output message by default:

CONFIG_DEBUG_UART_ANNOUNCE=y

Signed-off-by: Marek Vasut 
---
Cc: Samuel Holland 
Cc: Sean Anderson 
Cc: Simon Glass 
---
 drivers/serial/Kconfig |  8 
 drivers/serial/serial_sh.c | 85 +++---
 2 files changed, 68 insertions(+), 25 deletions(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index bb5083201b3..10d07daf277 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -415,6 +415,14 @@ config DEBUG_UART_SEMIHOSTING
  start up driver model. The driver will be available until the real
  driver model serial is running.
 
+config DEBUG_UART_SCIF
+   bool "Renesas SCIF UART"
+   depends on SH || ARCH_RMOBILE
+   help
+ Select this to enable a debug UART using the serial_sh driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
 config DEBUG_UART_SIFIVE
bool "SiFive UART"
depends on SIFIVE_SERIAL
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index c3e3f257c65..e08bdcadc9c 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -249,9 +249,40 @@ U_BOOT_DRIVER(serial_sh) = {
 #endif
.priv_auto  = sizeof(struct uart_port),
 };
+#endif
+
+#if !CONFIG_IS_ENABLED(DM_SERIAL) || IS_ENABLED(CONFIG_DEBUG_UART_SCIF)
 
-#else /* CONFIG_DM_SERIAL */
+#if defined(CFG_SCIF_A)
+   #define SCIF_BASE_PORT  PORT_SCIFA
+#elif defined(CFG_SCI)
+   #define SCIF_BASE_PORT  PORT_SCI
+#else
+   #define SCIF_BASE_PORT  PORT_SCIF
+#endif
+
+static void sh_serial_init_nodm(struct uart_port *port)
+{
+   sh_serial_init_generic(port);
+   serial_setbrg();
+}
+
+static void sh_serial_putc_nondm(struct uart_port *port, const char c)
+{
+   if (c == '\n') {
+   while (1) {
+   if  (serial_raw_putc(port, '\r') != -EAGAIN)
+   break;
+   }
+   }
+   while (1) {
+   if  (serial_raw_putc(port, c) != -EAGAIN)
+   break;
+   }
+}
+#endif
 
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #if defined(CONFIG_CONS_SCIF0)
 # define SCIF_BASE SCIF0_BASE
 #elif defined(CONFIG_CONS_SCIF1)
@@ -274,14 +305,6 @@ U_BOOT_DRIVER(serial_sh) = {
 # error "Default SCIF doesn't set."
 #endif
 
-#if defined(CFG_SCIF_A)
-   #define SCIF_BASE_PORT  PORT_SCIFA
-#elif defined(CFG_SCI)
-   #define SCIF_BASE_PORT  PORT_SCI
-#else
-   #define SCIF_BASE_PORT  PORT_SCIF
-#endif
-
 static struct uart_port sh_sci = {
.membase= (unsigned char *)SCIF_BASE,
.mapbase= SCIF_BASE,
@@ -301,28 +324,14 @@ static void sh_serial_setbrg(void)
 
 static int sh_serial_init(void)
 {
-   struct uart_port *port = _sci;
-
-   sh_serial_init_generic(port);
-   serial_setbrg();
+   sh_serial_init_nodm(_sci);
 
return 0;
 }
 
 static void sh_serial_putc(const char c)
 {
-   struct uart_port *port = _sci;
-
-   if (c == '\n') {
-   while (1) {
-   if  (serial_raw_putc(port, '\r') != -EAGAIN)
-   break;
-   }
-   }
-   while (1) {
-   if  (serial_raw_putc(port, c) != -EAGAIN)
-   break;
-   }
+   sh_serial_putc_nondm(_sci, c);
 }
 
 static int sh_serial_tstc(void)
@@ -367,3 +376,29 @@ __weak struct serial_device *default_serial_console(void)
return _serial_drv;
 }
 #endif /* CONFIG_DM_SERIAL */
+
+#ifdef CONFIG_DEBUG_UART_SCIF
+#include 
+
+static struct uart_port debug_uart_sci = {
+   .membase= (unsigned char *)CONFIG_DEBUG_UART_BASE,
+   .mapbase= CONFIG_DEBUG_UART_BASE,
+   .type   = SCIF_BASE_PORT,
+#ifdef CFG_SCIF_USE_EXT_CLK
+   .clk_mode = EXT_CLK,
+#endif
+};
+
+static inline void _debug_uart_init(void)
+{
+   sh_serial_init_nodm(_uart_sci);
+}
+
+static inline void _debug_uart_putc(int c)
+{
+   sh_serial_putc_nondm(_uart_sci, c);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
-- 
2.39.2

[PATCH 1/2] serial: sh: Rename CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK to CFG_ variants

[Marek Vasut]

Both CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK options do not have a
matching Kconfig entry because they are internal to the SCIF driver.
Change their prefix to CFG_, i.e. CFG_SCIF_USE_EXT_CLK and CFG_SCI,
to reflect that and avoid interferring with Kconfig symbols. Since
neither of those options are defined elsewhere, no functional change.

Signed-off-by: Marek Vasut 
---
Cc: Samuel Holland 
Cc: Sean Anderson 
Cc: Simon Glass 
---
 drivers/serial/serial_sh.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 4671217b59a..c3e3f257c65 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -276,7 +276,7 @@ U_BOOT_DRIVER(serial_sh) = {
 
 #if defined(CFG_SCIF_A)
#define SCIF_BASE_PORT  PORT_SCIFA
-#elif defined(CONFIG_SCI)
+#elif defined(CFG_SCI)
#define SCIF_BASE_PORT  PORT_SCI
 #else
#define SCIF_BASE_PORT  PORT_SCIF
@@ -286,7 +286,7 @@ static struct uart_port sh_sci = {
.membase= (unsigned char *)SCIF_BASE,
.mapbase= SCIF_BASE,
.type   = SCIF_BASE_PORT,
-#ifdef CONFIG_SCIF_USE_EXT_CLK
+#ifdef CFG_SCIF_USE_EXT_CLK
.clk_mode = EXT_CLK,
 #endif
 };
-- 
2.39.2

[PATCH v5 06/21] mtd: nand: add support for the Sandisk SDTNQGAMA chip

[Johan Jonker]

Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size,
1KB write size and 40 bit ecc support

Signed-off-by: Paweł Jarosz 
Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang 
---
 drivers/mtd/nand/raw/nand_ids.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
index d0cfacc6..22ea5e2f 100644
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -48,6 +48,9 @@ struct nand_flash_dev nand_flash_ids[] = {
{"TC58NVG6D2 64G 3.3V 8-bit",
{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
  SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
+   {"SDTNQGAMA 64G 3.3V 8-bit",
+   { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x57} },
+ SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
{"SDTNRGAMA 64G 3.3V 8-bit",
{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
--
2.20.1

[PATCH v5 05/21] mtd: nand: raw: rockchip_nfc: fix oobfree offset and description

[Johan Jonker]

The MTD framework reserves 1 or 2 bytes for the bad block marker
depending on the bus size. The rockchip_nfc driver currently only
supports a 8 bit bus, but reserves standard 2 bytes for the BBM.
The first free OOB byte is therefore OOB2 at offset 2.
Page address(PA) bytes are moved to the last 4 positions before
ECC. Update the description for U-boot.

Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang 
---
 drivers/mtd/nand/raw/rockchip_nfc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c 
b/drivers/mtd/nand/raw/rockchip_nfc.c
index ca5e7313..5ca7eeb8 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -487,10 +487,10 @@ static int rk_nfc_write_page_raw(struct mtd_info *mtd,
 *
 *BBM  OOB1 OOB2 OOB3 |..|  PA0  PA1  PA2  PA3
 *
-* The rk_nfc_ooblayout_free() function already has reserved
-* these 4 bytes with:
+* The oobfree structure already has reserved these 4 bytes
+* together with 2 bytes for BBM by reducing it's length:
 *
-* oob_region->offset = NFC_SYS_DATA_SIZE + 2;
+* oobfree[0].length = rknand->metadata_size - 
NFC_SYS_DATA_SIZE - 2;
 */
if (!i)
memcpy(rk_nfc_oob_ptr(chip, i),
@@ -867,7 +867,7 @@ static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct 
nand_chip *chip)
ecc->layout->eccpos[i] = rknand->metadata_size + i;

ecc->layout->oobfree[0].length = rknand->metadata_size - 
NFC_SYS_DATA_SIZE - 2;
-   ecc->layout->oobfree[0].offset = NFC_SYS_DATA_SIZE + 2;
+   ecc->layout->oobfree[0].offset = 2;

return 0;
 }
--
2.20.1

[PATCH v5 04/21] mtd: nand: raw: rockchip_nfc: add flash_node to chip structure

[Johan Jonker]

Add flash_node to the rockchip_nfc driver chip structure in order
to find the partitions in the add_mtd_partitions_of() function.

Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang 
Reviewed-by: Michael Trimarchi 
---
 drivers/mtd/nand/raw/rockchip_nfc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c 
b/drivers/mtd/nand/raw/rockchip_nfc.c
index ab13e52c..ca5e7313 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -934,6 +934,7 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc 
*nfc, int devnum)

nand_set_controller_data(chip, nfc);

+   chip->flash_node = node;
chip->chip_delay = NFC_RB_DELAY_US;
chip->select_chip = rk_nfc_select_chip;
chip->cmd_ctrl = rk_nfc_cmd;
--
2.20.1

[PATCH] clk: renesas: Always select DM_RESET to prevent inobvious failure of rst_gen3 subdriver

[Marek Vasut]

The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3.
The former depends on the clock framework, which is always enabled
in this context of clock framework driver, while the later depends
on reset framework which may not always be enabled.

Ensure the reset framework is also always enabled to prevent inobvious
early boot time bind failure of the CPG driver, which leads to system
showing no activity and is difficult to debug.

Note that one possible approach to debug this is to use CONFIG_DEBUG_UART
and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c .

Signed-off-by: Marek Vasut 
---
 drivers/clk/renesas/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 1686410d6d3..d58e897ca1b 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -49,6 +49,7 @@ config CLK_RCAR_GEN3
def_bool y if RCAR_GEN3
depends on CLK_RENESAS
select CLK_RCAR_CPG_LIB
+   select DM_RESET
help
  Enable this to support the clocks on Renesas RCar Gen3 SoC.
 
-- 
2.39.2

[PATCH v5 03/21] mtd: nand: raw: rockchip_nfc: add layout structure

[Johan Jonker]

The MTD framework in U-boot is not identical for drivers ported
from Linux. The rockchip_nfc driver was ported with OOB ops functions
while the framework expects a layout structure per chip.
Fix by adding a structure with OOB data and remove unused functions.

Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang 
Reviewed-by: Michael Trimarchi 
---
 drivers/mtd/nand/raw/rockchip_nfc.c | 61 ++---
 1 file changed, 20 insertions(+), 41 deletions(-)

diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c 
b/drivers/mtd/nand/raw/rockchip_nfc.c
index a8ec6bfc..ab13e52c 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -814,47 +814,9 @@ static void rk_nfc_disable_clks(struct rk_nfc *nfc)
clk_disable_unprepare(nfc->ahb_clk);
 }

-static int rk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
-struct mtd_oob_region *oob_region)
-{
-   struct nand_chip *chip = mtd_to_nand(mtd);
-   struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
-
-   if (section)
-   return -ERANGE;
-
-   /*
-* The beginning of the OOB area stores the reserved data for the NFC,
-* the size of the reserved data is NFC_SYS_DATA_SIZE bytes.
-*/
-   oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
-   oob_region->offset = NFC_SYS_DATA_SIZE + 2;
-
-   return 0;
-}
-
-static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
-   struct mtd_oob_region *oob_region)
-{
-   struct nand_chip *chip = mtd_to_nand(mtd);
-   struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
-
-   if (section)
-   return -ERANGE;
-
-   oob_region->length = mtd->oobsize - rknand->metadata_size;
-   oob_region->offset = rknand->metadata_size;
-
-   return 0;
-}
-
-static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = {
-   .rfree = rk_nfc_ooblayout_free,
-   .ecc = rk_nfc_ooblayout_ecc,
-};
-
 static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip)
 {
+   struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
const u8 *strengths = nfc->cfg->ecc_strengths;
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_ecc_ctrl *ecc = >ecc;
@@ -892,6 +854,21 @@ static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct 
nand_chip *chip)
ecc->steps = mtd->writesize / ecc->size;
ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8);

+   if (ecc->bytes * ecc->steps > mtd->oobsize - rknand->metadata_size)
+   return -EINVAL;
+
+   ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
+   if (!ecc->layout)
+   return -ENOMEM;
+
+   ecc->layout->eccbytes = ecc->bytes * ecc->steps;
+
+   for (i = 0; i < ecc->layout->eccbytes; i++)
+   ecc->layout->eccpos[i] = rknand->metadata_size + i;
+
+   ecc->layout->oobfree[0].length = rknand->metadata_size - 
NFC_SYS_DATA_SIZE - 2;
+   ecc->layout->oobfree[0].offset = NFC_SYS_DATA_SIZE + 2;
+
return 0;
 }

@@ -969,7 +946,6 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc 
*nfc, int devnum)
chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;

-   mtd_set_ooblayout(mtd, _nfc_ooblayout_ops);
rk_nfc_hw_init(nfc);
ret = nand_scan_ident(mtd, nsels, NULL);
if (ret)
@@ -998,13 +974,16 @@ static int rk_nfc_nand_chip_init(ofnode node, struct 
rk_nfc *nfc, int devnum)

if (!nfc->page_buf) {
nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL);
-   if (!nfc->page_buf)
+   if (!nfc->page_buf) {
+   kfree(ecc->layout);
return -ENOMEM;
+   }
}

if (!nfc->oob_buf) {
nfc->oob_buf = kzalloc(NFC_MAX_OOB_SIZE, GFP_KERNEL);
if (!nfc->oob_buf) {
+   kfree(ecc->layout);
kfree(nfc->page_buf);
nfc->page_buf = NULL;
return -ENOMEM;
--
2.20.1

[PATCH v5 02/21] mtd: nand: raw: rockchip_nfc: remove the compatible string "rockchip,rk3308-nfc"

[Johan Jonker]

The compatible string for rk3308 has as fallback string
"rockchip,rv1108-nfc". As there is no logic in probe priority between
the SoC orientated string and the fall back, so remove the compatible
string "rockchip,rk3308-nfc" from the driver.

Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang 
Reviewed-by: Michael Trimarchi 
---
 drivers/mtd/nand/raw/rockchip_nfc.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c 
b/drivers/mtd/nand/raw/rockchip_nfc.c
index 5d444133..a8ec6bfc 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -1165,10 +1165,6 @@ static const struct udevice_id rk_nfc_id_table[] = {
.compatible = "rockchip,rv1108-nfc",
.data = (unsigned long)_v8_cfg
},
-   {
-   .compatible = "rockchip,rk3308-nfc",
-   .data = (unsigned long)_v8_cfg
-   },
{ /* sentinel */ }
 };

--
2.20.1

[PATCH v5 01/21] mtd: nand: raw: rockchip_nfc: use dev_read_addr_ptr

[Johan Jonker]

The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip_nfc.c file.

Signed-off-by: Johan Jonker 
Reviewed-by: Michael Trimarchi 
---
 drivers/mtd/nand/raw/rockchip_nfc.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c 
b/drivers/mtd/nand/raw/rockchip_nfc.c
index d016d255..5d444133 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -1180,9 +1180,9 @@ static int rk_nfc_probe(struct udevice *dev)
nfc->cfg = (void *)dev_get_driver_data(dev);
nfc->dev = dev;

-   nfc->regs = (void *)dev_read_addr(dev);
-   if (IS_ERR(nfc->regs)) {
-   ret = PTR_ERR(nfc->regs);
+   nfc->regs = dev_read_addr_ptr(dev);
+   if (!nfc->regs) {
+   ret = -ENODATA;
goto release_nfc;
}

--
2.20.1

[PATCH v5 00/21] Fixes for Rockchip NFC driver part 1

[Johan Jonker]

This serie contains fixes for the Rockchip NFC driver,
which was ported to U-boot and merged with little review
and testing it seems.
Part 1 aims at passing the probe function without errors.
Extended with tree wide function cleanup needed for 64bit DT parsing.

Fixed are:
  64bit FDT parsing
  compatible string removal
  add missing layout structure
  add missing flash_node pointer
  add missing chip ID

Changed V5:
  sort patch order
  add more fixes with pointer functions
  add debug text fixes
  test with binman for ARM only due to limited resources

Changed V4:
  fix cast and divider in syscon-uclass.c

Changed V3:
  use dev_read_addr_ptr
  fix oobfree

TODO:
  Time consuming binman test for other SoC types then ARM.
  Help with testing appreciated.

Johan Jonker (20):
  mtd: nand: raw: rockchip_nfc: use dev_read_addr_ptr
  mtd: nand: raw: rockchip_nfc: remove the compatible string
"rockchip,rk3308-nfc"
  mtd: nand: raw: rockchip_nfc: add layout structure
  mtd: nand: raw: rockchip_nfc: add flash_node to chip structure
  mtd: nand: raw: rockchip_nfc: fix oobfree offset and description
  rockchip: adc: rockchip-saradc: use dev_read_addr_ptr
  rockchip: timer: dw-apb-timer: convert dev_read_addr output to
phys_addr_t
  include: dm: ofnode: fix headers
  core: remap: convert regmap_init_mem_plat() input to phys_addr_t
  core: fdtaddr: add devfdt_get_addr_size_index_ptr function
  core: read: add dev_read_addr_index_ptr function
  spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr
  drivers: use dev_read_addr_index_ptr when cast to pointer
  drivers: use dev_read_addr_ptr when cast to pointer
  drivers: use devfdt_get_addr_size_index_ptr when cast to pointer
  drivers: use devfdt_get_addr_index_ptr when cast to pointer
  drivers: use devfdt_get_addr_ptr when cast to pointer
  drivers: fix debug string with fdt_addr_t input
  arm: stm32mp: spl: fix function with fdt_addr_t input
  include: fdtdec: decouple fdt_addr_t and phys_addr_t size

Paweł Jarosz (1):
  mtd: nand: add support for the Sandisk SDTNQGAMA chip

 Kconfig   |  8 ++
 arch/arm/mach-mvebu/cpu.c |  2 +-
 arch/arm/mach-mvebu/system-controller.c   |  4 +-
 arch/arm/mach-stm32mp/spl.c   |  6 +-
 doc/develop/driver-model/livetree.rst |  4 +-
 drivers/adc/rockchip-saradc.c |  4 +-
 drivers/ata/dwc_ahsata.c  |  2 +-
 drivers/cache/cache-l2x0.c|  2 +-
 drivers/cache/cache-v5l2.c|  2 +-
 drivers/clk/at91/sama7g5.c|  2 +-
 drivers/clk/at91/sckc.c   |  2 +-
 drivers/clk/clk-hsdk-cgu.c|  4 +-
 drivers/clk/ti/clk-ctrl.c |  9 ++-
 drivers/core/fdtaddr.c|  8 ++
 drivers/core/read.c   |  7 ++
 drivers/core/regmap.c |  2 +-
 drivers/core/syscon-uclass.c  |  4 +-
 drivers/ddr/altera/sdram_gen5.c   |  2 +-
 drivers/gpio/mscc_sgpio.c |  2 +-
 drivers/gpio/tegra_gpio.c |  4 +-
 drivers/gpio/xilinx_gpio.c|  2 +-
 drivers/i2c/i2c-cdns.c|  2 +-
 drivers/i2c/tegra_i2c.c   |  4 +-
 drivers/mmc/am654_sdhci.c |  2 +-
 drivers/mmc/davinci_mmc.c |  2 +-
 drivers/mmc/piton_mmc.c   |  2 +-
 drivers/mmc/tegra_mmc.c   |  2 +-
 drivers/mmc/xenon_sdhci.c |  2 +-
 drivers/mmc/zynq_sdhci.c  |  6 +-
 drivers/mtd/nand/raw/arasan_nfc.c |  2 +-
 drivers/mtd/nand/raw/cortina_nand.c   |  6 +-
 drivers/mtd/nand/raw/mxic_nand.c  |  2 +-
 drivers/mtd/nand/raw/nand_ids.c   |  3 +
 drivers/mtd/nand/raw/rockchip_nfc.c   | 78 +++
 drivers/mtd/nand/raw/tegra_nand.c |  2 +-
 drivers/mtd/nand/raw/zynq_nand.c  |  2 +-
 drivers/net/dm9000x.c |  2 +-
 drivers/net/dwmac_meson8b.c   |  4 +-
 drivers/net/mvmdio.c  |  2 +-
 drivers/net/mvpp2.c   | 24 +++---
 drivers/net/qe/dm_qe_uec_phy.c|  2 +-
 drivers/pci/pci-aardvark.c|  4 +-
 drivers/pci/pcie_dw_meson.c   |  4 +-
 drivers/pci/pcie_dw_mvebu.c   | 10 +--
 drivers/pci/pcie_dw_rockchip.c|  4 +-
 drivers/pci/pcie_imx.c|  4 +-
 drivers/pci/pcie_layerscape_ep.c  |  4 +-
 drivers/phy/allwinner/phy-sun50i-usb3.c   |  6 +-
 drivers/phy/marvell/comphy_core.c | 12 +--
 drivers/phy/phy-stm32-usbphyc.c   |  4 +-
 drivers/phy/qcom/phy-qcom-usb-hs-28nm.c   |  4 +-
 drivers/phy/qcom/phy-qcom-usb-ss.c|  4 +-
 .../phy/rockchip/phy-rockchip-snps-pcie3.c|  4 +-
 

Re: [PULL] Please pull u-boot-coldfire/master

[Angelo Dureghello]

Hi Tom,

On 28/02/23 9:34 PM, Tom Rini wrote:

On Tue, Feb 28, 2023 at 09:21:23PM +0100, Angelo Dureghello wrote:


The following changes since commit e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8:

   Prepare v2023.04-rc3 (2023-02-27 17:18:36 -0500)

are available in the Git repository at:

   git://git.denx.de/u-boot-coldfire.git master

for you to fetch changes up to 4c885f9f64cd85471614c75027620e3bcf3046bd:

   m68k: dts: stmark2: set correct compatible field for spi nor (2023-02-28
21:19:47 +0100)


Angelo Dureghello (6):
   board: amcore: fix u-boot mtd partition
   m68k: use longword-based jumps
   m68k: add global variable sdhc_per_clk for m68k
   board: stmark2: fix clock value
   arch: enable private libgcc for m68k
   m68k: dts: stmark2: set correct compatible field for spi nor

  arch/Kconfig|  1 +
  arch/m68k/cpu/mcf530x/start.S   | 18 --
  arch/m68k/dts/stmark2.dts   |  2 +-
  arch/m68k/include/asm/global_data.h |  3 +++
  board/sysam/stmark2/Kconfig |  2 +-
  include/configs/amcore.h| 20 +++-
  6 files changed, 33 insertions(+), 13 deletions(-)


OK, you need to re-work a few of the changes:
https://source.denx.de/u-boot/u-boot/-/jobs/586499

Things are either in a Kconfig (and the defconfig), or now "CFG_..."
instead of "CONFIG_...".



i received the automated email. Fixes are in progress, but
not ready still, there are several CFG to be fixed.
Could i ask another pull request later, for next release ?

Regards,
--
Angelo Dureghello

Re: [PATCH v5 2/6] rockchip: Use an external TPL binary on RK3568

[Jonas Karlman]

On 2023-02-28 10:19, Jagan Teki wrote:
> On Sun, 26 Feb 2023 at 00:31, Jonas Karlman  wrote:
>>
>> Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps
>> back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then
>> jumps to U-Boot SPL to continue the normal boot flow.
>>
>> However, there is no support to initialize DRAM on RK35xx SoCs using
>> U-Boot TPL and instead an external TPL binary must be used to generate a
>> bootable u-boot-rockchip.bin image.
>>
>> Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should
>> be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a
>> bootable u-boot-rockchip.bin image for RK3568.
>>
>> Signed-off-by: Jonas Karlman 
>> Reviewed-by: Simon Glass 
>> Reviewed-by: Kever Yang 
>> Tested-by: Eugen Hristev 
>> ---
>> v5:
>> - No change
>>
>> v4:
>> - No change
>>
>> v3:
>> - Add help text to Kconfig option
>> - Add build step for rk3568 to documentation
>> - Collect r-b and t-b tags
>>
>> v2:
>> - Rename external-tpl-path to rockchip-tpl-path
>> - Rename EXTERNAL_TPL to ROCKCHIP_TPL
>> - Add CONFIG_ROCKCHIP_EXTERNAL_TPL option
>>
>>  Makefile  |  1 +
>>  arch/arm/dts/rockchip-u-boot.dtsi | 10 --
>>  arch/arm/mach-rockchip/Kconfig|  8 
>>  doc/board/rockchip/rockchip.rst   | 11 +++
>>  4 files changed, 28 insertions(+), 2 deletions(-)
>>
>> diff --git a/Makefile b/Makefile
>> index bc1ee94fb74e..67701f20eb6d 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -1336,6 +1336,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if 
>> $(BINMAN_DEBUG),-D) \
>> -a opensbi-path=${OPENSBI} \
>> -a default-dt=$(default_dt) \
>> -a scp-path=$(SCP) \
>> +   -a rockchip-tpl-path=$(ROCKCHIP_TPL) \
>> -a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
>> -a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \
>> -a spl-dtb=$(CONFIG_SPL_OF_REAL) \
>> diff --git a/arch/arm/dts/rockchip-u-boot.dtsi 
>> b/arch/arm/dts/rockchip-u-boot.dtsi
>> index 6c662a72d4f9..2878b80926c4 100644
>> --- a/arch/arm/dts/rockchip-u-boot.dtsi
>> +++ b/arch/arm/dts/rockchip-u-boot.dtsi
>> @@ -20,9 +20,12 @@
>> mkimage {
>> filename = "idbloader.img";
>> args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
>> -#ifdef CONFIG_TPL
>> multiple-data-files;
>>
>> +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
>> +   rockchip-tpl {
>> +   };
>> +#elif defined(CONFIG_TPL)
>> u-boot-tpl {
>> };
>>  #endif
>> @@ -134,9 +137,12 @@
>> mkimage {
>> filename = "idbloader-spi.img";
>> args = "-n", CONFIG_SYS_SOC, "-T", "rkspi";
>> -#ifdef CONFIG_TPL
>> multiple-data-files;
>>
>> +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
>> +   rockchip-tpl {
>> +   };
>> +#elif defined(CONFIG_TPL)
>> u-boot-tpl {
>> };
>>  #endif
>> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
>> index b678ec41318e..0b191b364264 100644
>> --- a/arch/arm/mach-rockchip/Kconfig
>> +++ b/arch/arm/mach-rockchip/Kconfig
>> @@ -401,6 +401,14 @@ config TPL_ROCKCHIP_COMMON_BOARD
>>   common board is a basic TPL board init which can be shared for most
>>   of SoCs to avoid copy-paste for different SoCs.
>>
>> +config ROCKCHIP_EXTERNAL_TPL
>> +   bool "Use external TPL binary"
>> +   default y if ROCKCHIP_RK3568
> 
> Can you add RK3588 as well.

I will send a separate patch to enable this for RK3588.

Regards,
Jonas

> 
> With that,
> 
> Reviewed-by: Jagan Teki 

Re: [PULL] Please pull u-boot-coldfire/master

[Tom Rini]

On Tue, Feb 28, 2023 at 09:21:23PM +0100, Angelo Dureghello wrote:

> The following changes since commit e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8:
> 
>   Prepare v2023.04-rc3 (2023-02-27 17:18:36 -0500)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-coldfire.git master
> 
> for you to fetch changes up to 4c885f9f64cd85471614c75027620e3bcf3046bd:
> 
>   m68k: dts: stmark2: set correct compatible field for spi nor (2023-02-28
> 21:19:47 +0100)
> 
> 
> Angelo Dureghello (6):
>   board: amcore: fix u-boot mtd partition
>   m68k: use longword-based jumps
>   m68k: add global variable sdhc_per_clk for m68k
>   board: stmark2: fix clock value
>   arch: enable private libgcc for m68k
>   m68k: dts: stmark2: set correct compatible field for spi nor
> 
>  arch/Kconfig|  1 +
>  arch/m68k/cpu/mcf530x/start.S   | 18 --
>  arch/m68k/dts/stmark2.dts   |  2 +-
>  arch/m68k/include/asm/global_data.h |  3 +++
>  board/sysam/stmark2/Kconfig |  2 +-
>  include/configs/amcore.h| 20 +++-
>  6 files changed, 33 insertions(+), 13 deletions(-)

OK, you need to re-work a few of the changes:
https://source.denx.de/u-boot/u-boot/-/jobs/586499

Things are either in a Kconfig (and the defconfig), or now "CFG_..."
instead of "CONFIG_...".

-- 
Tom


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[PATCH 1/2] Azure CI: Save pytest output automatically

[Tom Rini]

Enable use of the python-azurepipelines package which provides automatic
formatting and uploading of the pytest output.

Signed-off-by: Tom Rini 
---
 .azure-pipelines.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index f6609bbd6bd1..609020fa5498 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -194,10 +194,11 @@ stages:
   virtualenv -p /usr/bin/python3 /tmp/venv
   . /tmp/venv/bin/activate
   pip install -r test/py/requirements.txt
+  pip install pytest-azurepipelines
   export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
   export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
   # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if 
not
-  ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} 
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir 
"$UBOOT_TRAVIS_BUILD_DIR";
+  ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} 
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir 
"$UBOOT_TRAVIS_BUILD_DIR" --report-dir "$UBOOT_TRAVIS_BUILD_DIR";
   # the below corresponds to .gitlab-ci.yml "after_script"
   rm -rf /tmp/uboot-test-hooks /tmp/venv
   EOF
-- 
2.34.1

[PATCH 2/2] Azure CI: Be explicit about pytest cache directory

[Tom Rini]

The default pytest cache directory is in a read-only directory in Azure,
which results in a warning on the build page. Use the pytest command
line option to set the cache dir to somewhere writable.

Signed-off-by: Tom Rini 
---
 .azure-pipelines.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 609020fa5498..e0c499f8a407 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -198,7 +198,7 @@ stages:
   export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
   export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
   # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if 
not
-  ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} 
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir 
"$UBOOT_TRAVIS_BUILD_DIR" --report-dir "$UBOOT_TRAVIS_BUILD_DIR";
+  ./test/py/test.py -ra -o 
cache_dir="$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd ${TEST_PY_BD} 
${TEST_PY_ID} ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir 
"$UBOOT_TRAVIS_BUILD_DIR" --report-dir "$UBOOT_TRAVIS_BUILD_DIR";
   # the below corresponds to .gitlab-ci.yml "after_script"
   rm -rf /tmp/uboot-test-hooks /tmp/venv
   EOF
-- 
2.34.1

[PULL] Please pull u-boot-coldfire/master

[Angelo Dureghello]

The following changes since commit e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8:

  Prepare v2023.04-rc3 (2023-02-27 17:18:36 -0500)

are available in the Git repository at:

  git://git.denx.de/u-boot-coldfire.git master

for you to fetch changes up to 4c885f9f64cd85471614c75027620e3bcf3046bd:

  m68k: dts: stmark2: set correct compatible field for spi nor 
(2023-02-28 21:19:47 +0100)



Angelo Dureghello (6):
  board: amcore: fix u-boot mtd partition
  m68k: use longword-based jumps
  m68k: add global variable sdhc_per_clk for m68k
  board: stmark2: fix clock value
  arch: enable private libgcc for m68k
  m68k: dts: stmark2: set correct compatible field for spi nor

 arch/Kconfig|  1 +
 arch/m68k/cpu/mcf530x/start.S   | 18 --
 arch/m68k/dts/stmark2.dts   |  2 +-
 arch/m68k/include/asm/global_data.h |  3 +++
 board/sysam/stmark2/Kconfig |  2 +-
 include/configs/amcore.h| 20 +++-
 6 files changed, 33 insertions(+), 13 deletions(-)

Re: [PATCH 2/2] arm: mvebu: clearfog: Add defconfig for SPI booting

[Pali Rohár]

On Tuesday 28 February 2023 10:48:24 Pali Rohár wrote:
> On Monday 27 February 2023 17:17:31 Tony Dinh wrote:
> > Hi Pali,
> > 
> > On Mon, Feb 27, 2023 at 4:42 PM Tony Dinh  wrote:
> > >
> > > Hi Pali,
> > >
> > > On Mon, Feb 27, 2023 at 3:41 PM Tony Dinh  wrote:
> > > >
> > > > Hi Pali,
> > > > It is not related to this patch series (I also tested without the
> > > > patch series to confirm). But it is strange that I can no longer get
> > > > the configuration to boot from SPI. The 1st device in the boot order
> > > > is alway BOOTROM. The spl_boot_list is printed out below.
> > > >
> > > > 
> > > > High speed PHY - Ended Successfully
> > > > mv_ddr: 14.0.0
> > > > DDR4 Training Sequence - Switching XBAR Window to FastPath Window
> > > > mv_ddr: completed successfully
> > > > board_boot_order spl_boot_list[0] = 15
> > > > Trying to boot from BOOTROM
> > > > Returning to BootROM (return address 0x05c4)...
> > > > BootROM: Image checksum verification PASSED
> > > > 
> > > >
> > > > The SPL SPI configs (board Thecus N2350) are:
> > > > # grep SPL .config| grep SPI
> > > >
> > > > CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI=y
> > > > CONFIG_SPL_DM_SPI=y
> > > > CONFIG_SPL_SPI_FLASH_SUPPORT=y
> > > > CONFIG_SPL_SPI=y
> > > > CONFIG_SPL_DM_SPI_FLASH=y
> > > > CONFIG_SPL_SPI_FLASH_TINY=y
> > > > # CONFIG_SPL_SPI_FLASH_MTD is not set
> > > > CONFIG_SPL_SPI_LOAD=y
> > > >
> > > > Did I miss something new lately?
> > > >
> > > > Thanks,
> > > > Tony
> > > >
> > > > Trying to boot from BOOTROM
> > > > Returning to BootROM (return address 0x05c4)...
> > > > BootROM: Image checksum verification PASSED
> > >
> > > It turns out that the board strapping register itself is the problem.
> > > boot_device=0x9 was printed out in arch/arm/mach-mvebu/cpu.c. It
> > > surely does not match what we expected for A38x  (#define
> > > BOOT_FROM_SPI 0x32). Actually 0x9 is not defined in cpu.c at all. So
> > > it fell to the default case, which is BOOTROM.
> > >
> > > 
> > > U-Boot SPL 2023.04-rc2-tld-1-00089-g3fe03f96fc-dirty (Feb 27 2023 -
> > > 16:24:01 -0800)
> > > High speed PHY - Version: 2.0
> > > Detected Device ID 6820
> > > board SerDes lanes topology details:
> > >  | Lane # | Speed |  Type   |
> > >  
> > >  |   0|   0   | SGMII0 |
> > >  |   1|   3   | SATA0 |
> > >  |   2|   3   | SATA1 |
> > >  |   4|   5   | USB3 HOST0 |
> > >  |   5|   5   | USB3 HOST1 |
> > >  
> > > High speed PHY - Ended Successfully
> > > mv_ddr: 14.0.0
> > > DDR4 Training Sequence - Switching XBAR Window to FastPath Window
> > > mv_ddr: completed successfully
> > > BOOTROM_REG=0x97001000 boot_device=0x9

Wait...

Stop here. BOOTROM_REG is the value of BOOTROM_ERR_REG register which is
mvebu register 0x182d0.

Boot strapping pins are available in the SAR_REG register which is mvebu
register 0x18600 and SPL prints it under name SAR_REG.

So above boot_device=9 is not strapping pin configuration but something
parsed from BOOTROM_ERR_REG.

So above 0x9 signal some A385 bootrom error and SPL in case case of any
error (value different from zero) always use bootrom for loading proper
u-boot. As it thinks that bootrom loaded u-boot via uart. Seems that
this assumption is incorrect.

Unfortunately upper four bits which above code parses from mvebu
register 0x182d0 are marked as reserved in functional specification.

So it is needed to inspect bootrom binary when it sets these bits...

> > > spl_boot_device boot_device = 15
> > > board_boot_order spl_boot_list[0] = 15
> > > Trying to boot from BOOTROM
> > > Returning to BootROM (return address 0x05c4)...
> > > BootROM: Image checksum verification PASSED
> > > 
> > >
> > > Is there a chance this value 0x9 means something that we have not come 
> > > across?
> > 
> > Found the answer in the A38x Hardware Specs. I've never noticed this
> > before. This board has the Sample at Reset set to boot from NAND!
> > 
> > "Table 48: Boot Device Mode Options
> > 0x9
> > BootROM Enabled, Boot from NAND: 8 bits width, with page size of 512B,
> > 4 Address cycles support per page, using MPP multiplexing option of
> > NAND 8 bits
> > 0x32
> > BootROM Enabled, Boot from SPI: Controller #0, 24 address bits, NOR
> > Flash type, using MPP multiplexing option of SPI on MPP[25:22]"
> > 
> > So what we actually see here is the fall back to BootROM. And BootROM
> > still loads the image from SPI, ignoring that strapping. Am I confused
> > or correct? :)
> > 
> > Thanks,
> > Tony
> 
> I already wrote in some thread that in Hardware Specifications are
> documented all strapping pins options and u-boot has defined just few of
> them in header files. Beware that strapping pins are SoC specific and so
> you always need to look at the correct document.
> 
> About parallel-NAND vs SPI-NOR, could you send the whole bootlog on uart
> from bootrom to main u-boot and type of the SoC?

Re: Pull request for tpm-next-28022023

[Tom Rini]

On Tue, Feb 28, 2023 at 11:28:24AM +0200, Ilias Apalodimas wrote:

> Hi Tom,
> 
> The following changes since commit 5b197eee334bdf75cc9e9148161299679a5251ea:
> 
>   Merge tag 'v2023.04-rc3' into next (2023-02-27 17:28:21 -0500)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-tpm/ tags/tpm-next-28022023
> 
> for you to fetch changes up to a11be4c303eabb142e074c7ca14b6ae0d293f0cb:
> 
>   tpm: Implement tpm_auto_start() for TPMv1.2 (2023-02-28 09:44:33 +0200)
> 
> The CI showed no issues:
> https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/15398
> 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: Pull request for u-boot-nand-20230227

[Tom Rini]

On Mon, Feb 27, 2023 at 05:52:29PM +0100, Dario Binacchi wrote:

> Hi Tom,
> 
> The following changes since commit 0024e7f72b689f8c2df731a69e20f47b6f8dc5a7:
> 
>   Merge branch 'master' of
> https://source.denx.de/u-boot/custodians/u-boot-tegra (2023-02-23
> 17:40:18 -0500)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
> tags/u-boot-nand-20230227
> 
> for you to fetch changes up to d9fa61f54e7f9ac3e31c362cddda834675200a23:
> 
>   mtd: nand: Show reserved block in chip.erase (2023-02-27 16:30:13 +0100)
> 
> Gitlab CI showed no issues:
> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/15388

Applied to u-boot/next, thanks!

-- 
Tom


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[PATCH V7 14/15] arm: dts: iot2050: Add support for M.2 variant

[Jan Kiszka]

From: chao zeng 

Add support for the M.2 board based on the iot2050 advanced board.
The board has two m.2 connectors, one is B-keyed, the other E-keyed.
The B-key slot can connect 5G/SSD devices, and E-key can be used for
WIFI/BT devices.

This variant is covered by PG2 firmware image.

Signed-off-by: chao zeng 
[Jan: align DT to kernel, polish wording]
Signed-off-by: Jan Kiszka 
---
 arch/arm/dts/Makefile |   3 +-
 .../arm/dts/k3-am6548-iot2050-advanced-m2.dts | 121 ++
 configs/iot2050_pg2_defconfig |   2 +-
 doc/board/siemens/iot2050.rst |   6 +-
 4 files changed, 128 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7a577deb502..8e9e2bf9a42 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1253,7 +1253,8 @@ dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am6528-iot2050-basic.dtb \
k3-am6528-iot2050-basic-pg2.dtb \
k3-am6548-iot2050-advanced.dtb \
-   k3-am6548-iot2050-advanced-pg2.dtb
+   k3-am6548-iot2050-advanced-pg2.dtb \
+   k3-am6548-iot2050-advanced-m2.dtb
 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
  k3-j721e-r5-common-proc-board.dtb \
  k3-j7200-common-proc-board.dtb \
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts 
b/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
new file mode 100644
index 000..9400e35882a
--- /dev/null
+++ b/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2023
+ *
+ * Authors:
+ *   Chao Zeng 
+ *   Jan Kiszka 
+ *
+ * AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product
+ * Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
+ *
+ * Product homepage:
+ * 
https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+ */
+
+#include "k3-am6548-iot2050-advanced-common.dtsi"
+#include "k3-am65-iot2050-common-pg2.dtsi"
+
+/ {
+   compatible = "siemens,iot2050-advanced-m2", "ti,am654";
+   model = "SIMATIC IOT2050 Advanced M2";
+};
+
+_r5fss0 {
+   /* lock-step mode not supported on this board */
+   ti,cluster-mode = <0>;
+};
+
+_pmx0 {
+   main_m2_enable_pins_default: main-m2-enable-pins-default {
+   pinctrl-single,pins = <
+   AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7)  /* (AH13) 
GPIO1_17 */
+   >;
+   };
+
+   main_bkey_pcie_reset: main-bkey-pcie-reset {
+   pinctrl-single,pins = <
+   AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7)  /* (AG13) 
GPIO1_15 */
+   >;
+   };
+
+   main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default {
+   pinctrl-single,pins = <
+   AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7)  /* (AE13) 
GPIO1_18 */
+   AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7)  /* (AD13) 
GPIO1_19 */
+   >;
+   };
+
+   main_m2_pcie_mux_control: main-m2-pcie-mux-control {
+   pinctrl-single,pins = <
+   AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7)  /* (AG22) 
GPIO0_82 */
+   AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7)  /* (AE20) 
GPIO0_88 */
+   AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7)  /* (AF19) 
GPIO0_89 */
+   >;
+   };
+};
+
+_pmx1 {
+   main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default {
+   pinctrl-single,pins = <
+   AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7)  /* (B22) 
GPIO1_88 */
+   AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7)  /* (C23) 
GPIO1_89 */
+   >;
+   };
+};
+
+_gpio0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <
+   _m2_pcie_mux_control
+   _io_d4_to_d9_pins_default
+   >;
+};
+
+_gpio1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <
+   _m2_enable_pins_default
+   _pmx0_m2_config_pins_default
+   _pmx1_m2_config_pins_default
+   _reset_pin_default
+   >;
+};
+
+/*
+ * Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only.
+ * Firmware switches to other modes via device tree overlays.
+ */
+
+ {
+   assigned-clocks = <_clks 153 4>, < AM654_SERDES_CMU_REFCLK>;
+   assigned-clock-parents = <_clks 153 8>, <_clks 153 4>;
+};
+
+_rc {
+   pinctrl-names = "default";
+   pinctrl-0 = <_bkey_pcie_reset>;
+
+   num-lanes = <2>;
+   phys = < PHY_TYPE_PCIE 1>, < PHY_TYPE_PCIE 1>;
+   phy-names = "pcie-phy0","pcie-phy1";
+   reset-gpios = <_gpio1 15 GPIO_ACTIVE_HIGH>;
+   status = "okay";
+};
+
+_rc {
+   status = "disabled";
+};
+
+_0 {
+   assigned-clock-parents = 

[PATCH V7 15/15] iot2050: Add support for configuring M.2 connector

[Jan Kiszka]

From: Jan Kiszka 

The M.2 slots of the related IOT2050 variant need to be configured
according to the plugged cards. This tries to detect the card using the
M.2 configuration pins of the B-key slot. If that fails, a U-Boot
environment variable can be set to configure manually. This variable is
write-permitted also in secure boot mode as it is not able to undermine
the integrity of the booted system.

The configuration is then applied to mux the serdes and to fix up the
device tree passed to or loaded by the bootloader. The fix-ups are
coming from device tree overlays that are embedded into the firmware
image and there also integrity protected. The OS remains free to load
a device tree to which they do not apply: U-Boot will not fail to boot
in that case.

Based on original patch by Chao Zeng.

Signed-off-by: Jan Kiszka 
---
 arch/arm/dts/Makefile |   4 +-
 arch/arm/dts/k3-am65-iot2050-boot-image.dtsi  |  38 ++-
 ...050-advanced-m2-bkey-ekey-pcie-overlay.dts |  27 ++
 ...-iot2050-advanced-m2-bkey-usb3-overlay.dts |  47 
 board/siemens/iot2050/board.c | 259 +-
 doc/board/siemens/iot2050.rst |  18 ++
 include/configs/iot2050.h |   1 +
 7 files changed, 391 insertions(+), 3 deletions(-)
 create mode 100644 
arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts
 create mode 100644 
arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8e9e2bf9a42..0bfc69ecc86 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1254,7 +1254,9 @@ dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am6528-iot2050-basic-pg2.dtb \
k3-am6548-iot2050-advanced.dtb \
k3-am6548-iot2050-advanced-pg2.dtb \
-   k3-am6548-iot2050-advanced-m2.dtb
+   k3-am6548-iot2050-advanced-m2.dtb \
+   k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo \
+   k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo
 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
  k3-j721e-r5-common-proc-board.dtb \
  k3-j7200-common-proc-board.dtb \
diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi 
b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
index a2fc8bbc123..03ccc543293 100644
--- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
@@ -61,6 +61,36 @@
};
};
 
+#ifdef CONFIG_TARGET_IOT2050_A53_PG2
+   bkey-usb3-overlay {
+   description = "M.2-bkey-usb3-overlay";
+   type = "blob";
+   load = <0x8210>;
+   arch = "arm64";
+   compression = "none";
+   blob-ext {
+   filename = 
"k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo";
+   };
+   hash {
+   algo = "sha256";
+   };
+   };
+
+   bkey-ekey-pcie-overlay {
+   description = 
"M.2-bkey-ekey-pcie-overlay";
+   type = "blob";
+   load = <0x8211>;
+   arch = "arm64";
+   compression = "none";
+   blob-ext {
+   filename = 
"k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo";
+   };
+   hash {
+   algo = "sha256";
+   };
+   };
+#endif
+
 #ifdef CONFIG_WDT_K3_RTI_FW_FILE
k3-rti-wdt-firmware {
type = "firmware";
@@ -84,9 +114,15 @@
description = "NAME";
firmware = "u-boot";
fdt = "fdt-SEQ";
+   loadables =
+#ifdef CONFIG_TARGET_IOT2050_A53_PG2
+   "bkey-usb3-overlay",
+   "bkey-ekey-pcie-overlay",
+#endif
 #ifdef CONFIG_WDT_K3_RTI_FW_FILE
-   loadables = "k3-rti-wdt-firmware";
+   "k3-rti-wdt-firmware",
 #endif
+   <>;
  

[PATCH V7 13/15] iot2050: Refresh defconfigs and activate CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN

[Jan Kiszka]

From: Jan Kiszka 

This feature is desired on the platform.

Signed-off-by: Jan Kiszka 
---
 configs/iot2050_pg1_defconfig | 1 +
 configs/iot2050_pg2_defconfig | 5 +
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/configs/iot2050_pg1_defconfig b/configs/iot2050_pg1_defconfig
index 258ad4c87e5..45c88fc134e 100644
--- a/configs/iot2050_pg1_defconfig
+++ b/configs/iot2050_pg1_defconfig
@@ -146,3 +146,4 @@ CONFIG_WDT=y
 CONFIG_WDT_K3_RTI=y
 CONFIG_WDT_K3_RTI_LOAD_FW=y
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN=y
diff --git a/configs/iot2050_pg2_defconfig b/configs/iot2050_pg2_defconfig
index 2ff360b0623..d2bdeab593b 100644
--- a/configs/iot2050_pg2_defconfig
+++ b/configs/iot2050_pg2_defconfig
@@ -25,11 +25,8 @@ CONFIG_ENV_OFFSET_REDUND=0x6a
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8010
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
-# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SHOW_BOOT_PROGRESS=y
@@ -78,7 +75,6 @@ CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl"
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_REGMAP=y
@@ -150,3 +146,4 @@ CONFIG_WDT=y
 CONFIG_WDT_K3_RTI=y
 CONFIG_WDT_K3_RTI_LOAD_FW=y
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN=y
-- 
2.35.3

[PATCH V7 11/15] doc: iot2050: Add a note about the watchdog firmware

[Jan Kiszka]

From: Jan Kiszka 

This is enabled by default, thus should be described as well.

Signed-off-by: Jan Kiszka 
---
 doc/board/siemens/iot2050.rst | 4 
 1 file changed, 4 insertions(+)

diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst
index cb49a0e36bf..efe94a448a9 100644
--- a/doc/board/siemens/iot2050.rst
+++ b/doc/board/siemens/iot2050.rst
@@ -27,6 +27,10 @@ The following binaries from that source need to be present 
in the build folder:
  - seboot_pg1.bin
  - seboot_pg2.bin
 
+When using the watchdog, a related firmware for the R5 core(s) is needed, e.g.
+https://github.com/siemens/k3-rti-wdt. The name and location of the image is
+configured via CONFIG_WDT_K3_RTI_FW_FILE.
+
 For building an image containing the OTP key provisioning data, below binary
 needs to be present in the build folder:
 
-- 
2.35.3

[PATCH V7 10/15] arm: dts: iot2050: Optionally embed OTP programming data into image

[Jan Kiszka]

From: Jan Kiszka 

Use external blob otpcmd.bin to replace the 0xff filled OTP programming
command block to create a firmware image that provisions the OTP on
first boot. This otpcmd.bin is generated from the customer keys using
steps described in the meta-iot2050 integration layer for the device.

Based on original patch by Baocheng Su.

Signed-off-by: Jan Kiszka 
---
 arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 9 +
 board/siemens/iot2050/Kconfig| 7 +++
 doc/board/siemens/iot2050.rst| 8 
 tools/binman/missing-blob-help   | 8 
 4 files changed, 32 insertions(+)

diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi 
b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
index 9082a79a034..a2fc8bbc123 100644
--- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
@@ -111,10 +111,19 @@
};
 
/* OTP update command block */
+#if CONFIG_IOT2050_EMBED_OTPCMD
+   blob-ext@0x6c {
+   offset = <0x6c>;
+   size   = <0x01>;
+   filename = "otpcmd.bin";
+   missing-msg = "iot2050-otpcmd";
+   };
+#else
fill@0x6c {
offset = <0x6c>;
size   = <0x01>;
fill-byte = [ff];
};
+#endif
};
 };
diff --git a/board/siemens/iot2050/Kconfig b/board/siemens/iot2050/Kconfig
index a2b40881d11..e66b2427d95 100644
--- a/board/siemens/iot2050/Kconfig
+++ b/board/siemens/iot2050/Kconfig
@@ -49,4 +49,11 @@ config IOT2050_BOOT_SWITCH
bool "Disable eMMC boot via USER button (Advanced version only)"
default y
 
+config IOT2050_EMBED_OTPCMD
+   bool "Embed OTP programming data"
+   help
+ Embed signed OTP programming data 'otpcmd.bin' into the firmware
+ image. This data will be evaluated and executed on first boot of the
+ device.
+
 endif
diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst
index 4e0925c72c9..cb49a0e36bf 100644
--- a/doc/board/siemens/iot2050.rst
+++ b/doc/board/siemens/iot2050.rst
@@ -27,6 +27,14 @@ The following binaries from that source need to be present 
in the build folder:
  - seboot_pg1.bin
  - seboot_pg2.bin
 
+For building an image containing the OTP key provisioning data, below binary
+needs to be present in the build folder:
+
+ - otpcmd.bin
+
+Regarding how to generating this otpcmd.bin, please refer to:
+https://github.com/siemens/meta-iot2050/tree/master/recipes-bsp/secure-boot-otp-provisioning/files/make-otpcmd.sh
+
 Building
 
 
diff --git a/tools/binman/missing-blob-help b/tools/binman/missing-blob-help
index 1a30da7b5aa..db16229f9f2 100644
--- a/tools/binman/missing-blob-help
+++ b/tools/binman/missing-blob-help
@@ -23,6 +23,14 @@ See the documentation for IOT2050 board. Your image is 
missing SEBoot
 which is mandatory for board startup. Prebuilt SEBoot located at
 meta-iot2050/tree/master/recipes-bsp/u-boot/files/prebuild/seboot_pg*.bin.
 
+iot2050-otpcmd:
+See the documentation for IOT2050 board. Your image is missing OTP command data
+block which is used for provisioning the customer keys to the board.
+Please refer to
+meta-iot2050/tree/master/recipes-bsp/secure-boot-otp-provisioning/files/make-otpcmd.sh
+for how to generate this binary. If you are not using secure boot or do not
+intend to provision the keys, disable CONFIG_IOT2050_EMBED_OTPCMD.
+
 k3-rti-wdt-firmware:
 If CONFIG_WDT_K3_RTI_LOAD_FW is enabled, a firmware image is needed for
 the R5F core(s) to trigger the system reset. One possible source is
-- 
2.35.3

[PATCH V7 08/15] tools: Add script for converting public key into device tree include

[Jan Kiszka]

From: Jan Kiszka 

Allows to create a public key device tree dtsi for inclusion into U-Boot
SPL and proper during first build already. This can be achieved via
CONFIG_DEVICE_TREE_INCLUDES.

Signed-off-by: Jan Kiszka 
---
 tools/key2dtsi.py | 64 +++
 1 file changed, 64 insertions(+)
 create mode 100755 tools/key2dtsi.py

diff --git a/tools/key2dtsi.py b/tools/key2dtsi.py
new file mode 100755
index 000..1dbb2cc94bf
--- /dev/null
+++ b/tools/key2dtsi.py
@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Public key to dtsi converter.
+#
+# Copyright (c) Siemens AG, 2022
+#
+
+from argparse import ArgumentParser, FileType
+from os.path import basename, splitext
+from Cryptodome.PublicKey import RSA
+from Cryptodome.Util.number import inverse
+
+def int_to_bytestr(n, length=None):
+if not length:
+length = (n.bit_length() + 7) // 8
+byte_array = n.to_bytes(length, 'big')
+return ' '.join(['{:02x}'.format(byte) for byte in byte_array])
+
+ap = ArgumentParser(description='Public key to dtsi converter')
+
+ap.add_argument('--hash', '-H', default='sha256',
+help='hash to be used with key (default: sha256)')
+ap.add_argument('--required-conf', '-c', action='store_true',
+help='mark key required for configuration')
+ap.add_argument('--required-image', '-i', action='store_true',
+help='mark key required for image')
+ap.add_argument('--spl', '-s', action='store_true',
+help='mark key for usage in SPL')
+ap.add_argument('key_file', metavar='KEY_FILE', type=FileType('r'),
+help='key file (formats: X.509, PKCS#1, OpenSSH)')
+ap.add_argument('dtsi_file', metavar='DTSI_FILE', type=FileType('w'),
+help='dtsi output file')
+
+args = ap.parse_args()
+
+key_name, _ = splitext(basename(args.key_file.name))
+
+key_data = args.key_file.read()
+key = RSA.importKey(key_data)
+
+r_squared = (2**key.size_in_bits())**2 % key.n
+n0_inverse = 2**32 - inverse(key.n, 2**32)
+
+out = args.dtsi_file
+out.write('/ {\n')
+out.write('\tsignature {\n')
+out.write('\t\tkey-{} {{\n'.format(key_name))
+out.write('\t\t\tkey-name-hint = "{}";\n'.format(key_name))
+out.write('\t\t\talgo = "{},rsa{}";\n'.format(args.hash, key.size_in_bits()))
+out.write('\t\t\trsa,num-bits = <{}>;\n'.format(key.size_in_bits()))
+out.write('\t\t\trsa,modulus = [{}];\n'.format(int_to_bytestr(key.n)))
+out.write('\t\t\trsa,exponent = [{}];\n'.format(int_to_bytestr(key.e, 8)))
+out.write('\t\t\trsa,r-squared = [{}];\n'.format(int_to_bytestr(r_squared)))
+out.write('\t\t\trsa,n0-inverse = <0x{:x}>;\n'.format(n0_inverse))
+if args.required_conf:
+out.write('\t\t\trequired = "conf";\n')
+elif args.required_image:
+out.write('\t\t\trequired = "image";\n')
+if args.spl:
+out.write('\t\t\tu-boot,dm-spl;\n')
+out.write('\t\t};\n')
+out.write('\t};\n')
+out.write('};\n')
-- 
2.35.3

[PATCH V7 09/15] iot2050: Add script for signing artifacts

[Jan Kiszka]

From: Jan Kiszka 

There are many ways to get a signed firmware for the IOT2050 devices,
namely for the parts under user-control. This script documents one way
of doing it, given a signing key. Augment the board documentation with
the required procedure around it.

Signed-off-by: Jan Kiszka 
---
 doc/board/siemens/iot2050.rst | 52 +++
 tools/iot2050-sign-fw.sh  | 51 ++
 2 files changed, 103 insertions(+)
 create mode 100755 tools/iot2050-sign-fw.sh

diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst
index 26972e20ae9..4e0925c72c9 100644
--- a/doc/board/siemens/iot2050.rst
+++ b/doc/board/siemens/iot2050.rst
@@ -79,3 +79,55 @@ Via external programmer Dediprog SF100 or SF600:
 .. code-block:: text
 
  $ dpcmd --vcc 2 -v -u flash.bin
+
+Signing (optional)
+--
+
+To enable verified boot for the firmware artifacts after the Siemens-managed
+first-stage loader (seboot_pg*.bin), the following steps need to be taken
+before and after the build:
+
+Generate dtsi holding the public key
+
+
+.. code-block:: text
+
+ tools/key2dtsi.py -c -s key.pem public-key.dtsi
+
+This will be used to embed the public key into U-Boot SPL and main so that each
+step can validate signatures of the succeeding one.
+
+Adjust U-Boot configuration
+^^^
+
+Enabled at least the following options in U-Boot:
+
+.. code-block:: text
+
+ CONFIG_SPL_FIT_SIGNATURE=y
+ CONFIG_DEVICE_TREE_INCLUDES="/path/to/public-key.dtsi"
+ CONFIG_RSA=y
+
+Note that there are more configuration changes needed in order to lock-down
+the command line and the boot process of U-Boot for secure scenarios. These are
+not in scope here.
+
+Build U-Boot
+
+
+See related section above.
+
+Sign flash.bin
+^^
+
+In the build folder still containing artifacts from step 3, invoke:
+
+.. code-block:: text
+
+ tools/iot2050-sign-fw.sh /path/to/key.pem
+
+Flash signed flash.bin
+^^
+
+The signing has happen in-place in flash.bin, thus the flashing procedure
+described above.
diff --git a/tools/iot2050-sign-fw.sh b/tools/iot2050-sign-fw.sh
new file mode 100755
index 000..4d1d79498c2
--- /dev/null
+++ b/tools/iot2050-sign-fw.sh
@@ -0,0 +1,51 @@
+#!/bin/sh
+
+if [ -z "$1" ]; then
+   echo "Usage: $0 KEY"
+   exit 1
+fi
+
+TEMP_X509=$(mktemp .temp)
+
+REVISION=${2:-0}
+SHA_VAL=$(openssl dgst -sha512 -hex tispl.bin | sed -e "s/^.*= //g")
+BIN_SIZE=$(stat -c %s tispl.bin)
+
+cat <$TEMP_X509
+[ req ]
+distinguished_name = req_distinguished_name
+x509_extensions= v3_ca
+prompt = no
+dirstring_type = nobmp
+
+[ req_distinguished_name ]
+CN = IOT2050 Firmware Signature
+
+[ v3_ca ]
+basicConstraints   = CA:true
+1.3.6.1.4.1.294.1.3= ASN1:SEQUENCE:swrv
+1.3.6.1.4.1.294.1.34   = ASN1:SEQUENCE:sysfw_image_integrity
+
+[ swrv ]
+swrv = INTEGER:$REVISION
+
+[ sysfw_image_integrity ]
+shaType= OID:2.16.840.1.101.3.4.2.3
+shaValue   = FORMAT:HEX,OCT:$SHA_VAL
+imageSize  = INTEGER:$BIN_SIZE
+EOF
+
+CERT_X509=$(mktemp .crt)
+
+openssl req -new -x509 -key $1 -nodes -outform DER -out $CERT_X509 -config 
$TEMP_X509 -sha512
+cat $CERT_X509 tispl.bin > tispl.bin_signed
+# currently broken in upstream
+#source/tools/binman/binman replace -i flash.bin -f tispl.bin_signed 
blob@0x18
+dd if=tispl.bin_signed of=flash.bin bs=$((0x1000)) seek=$((0x18/0x1000)) 
conv=notrunc
+
+rm $TEMP_X509 $CERT_X509
+
+tools/mkimage -G $1 -r -o sha256,rsa4096 -F f...@0x38.fit
+# currently broken in upstream
+#source/tools/binman/binman replace -i flash.bin -f f...@0x38.fit 
fit@0x38
+dd if=f...@0x38.fit of=flash.bin bs=$((0x1000)) seek=$((0x38/0x1000)) 
conv=notrunc
-- 
2.35.3

[PATCH V7 12/15] board: siemens: iot2050: use the named gpio to control the user-button

[Jan Kiszka]

From: chao zeng 

User-button is controlled by the mcu domain gpio number 25.
But main0 main1 mcu domain all have gpio number 25.

To identify where the gpio is from, Using gpio controll base as the prefix
to indicate the gpio resource.

Signed-off-by: chao zeng 
---
 board/siemens/iot2050/board.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index 57d7009e8c7..2735ae3fb74 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -183,7 +183,7 @@ static bool user_button_pressed(void)
 
memset(, 0, sizeof(gpio));
 
-   if (dm_gpio_lookup_name("25", ) < 0 ||
+   if (dm_gpio_lookup_name("gpio@4211_25", ) < 0 ||
dm_gpio_request(, "USER button") < 0 ||
dm_gpio_set_dir_flags(, GPIOD_IS_IN) < 0)
return false;
-- 
2.35.3

[PATCH V7 00/15] IOT2050-related enhancements

[Jan Kiszka]

Flushing our upstream queue for the IOT2050 device, this mostly
brings board-specific changes such as:

 - updated build process and firmware layout for PG1 vs. PG2 devices
 - more watchdog preparations
 - preparations for verified boot on IOT2050 Advanced devices
 - support for M.2 variant

Changes in v7:
 - rebased over master
 - included M.2 support patches, now that the DT is merged into the kernel

Changes in v6:
 - fixed CFG_ENV_FLAGS_LIST_STATIC setup
 - migrated to board env file
 - cleaned up #ifdef in "Optionally embed OTP programming data into image"
 - rebased over latest master

Changes in v5:
 - factored out two patches

Changes in v4:
 - rebased over latest master
 - make use of new CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN

Changes in v3:
 - further reworked patch 1 to load default env directly, leaving driver
   ordering alone

Changes in v2:
 - rebased over latest master
 - reworked patch 1 to be less invasive to the code
 - added "iot2050: use the named gpio to control the user-button"

Jan


CC: chao zeng 
CC: Su Baocheng 

Jan Kiszka (11):
  iot2050: Update firmware layout
  iot2050: Migrate settings into board env file
  iot2050: Add watchdog start to bootcmd
  iot2050: Add CFG_ENV_FLAGS_LIST_STATIC
  arm: dts: iot2050: Allow verifying U-Boot proper by SPL
  tools: Add script for converting public key into device tree include
  iot2050: Add script for signing artifacts
  arm: dts: iot2050: Optionally embed OTP programming data into image
  doc: iot2050: Add a note about the watchdog firmware
  iot2050: Refresh defconfigs and activate
CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN
  iot2050: Add support for configuring M.2 connector

Su Baocheng (2):
  board: siemens: iot2050: Split the build for PG1 and PG2
  arm: dts: iot2050: Use the auto generator nodes for fdt

chao zeng (2):
  board: siemens: iot2050: use the named gpio to control the user-button
  arm: dts: iot2050: Add support for M.2 variant

 arch/arm/dts/Makefile |   5 +-
 arch/arm/dts/k3-am65-iot2050-boot-image.dtsi  | 149 +-
 ...050-advanced-m2-bkey-ekey-pcie-overlay.dts |  27 ++
 ...-iot2050-advanced-m2-bkey-usb3-overlay.dts |  47 +++
 .../arm/dts/k3-am6548-iot2050-advanced-m2.dts | 121 
 board/siemens/iot2050/Kconfig |  35 ++-
 board/siemens/iot2050/board.c | 270 +-
 board/siemens/iot2050/iot2050.env |  17 ++
 ...ot2050_defconfig => iot2050_pg1_defconfig} |   8 +-
 ...ot2050_defconfig => iot2050_pg2_defconfig} |  12 +-
 doc/board/siemens/iot2050.rst | 101 ++-
 include/configs/iot2050.h |  19 +-
 tools/binman/missing-blob-help|  16 +-
 tools/iot2050-sign-fw.sh  |  51 
 tools/key2dtsi.py |  64 +
 15 files changed, 818 insertions(+), 124 deletions(-)
 create mode 100644 
arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts
 create mode 100644 
arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts
 create mode 100644 arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
 create mode 100644 board/siemens/iot2050/iot2050.env
 copy configs/{iot2050_defconfig => iot2050_pg1_defconfig} (93%)
 rename configs/{iot2050_defconfig => iot2050_pg2_defconfig} (90%)
 create mode 100755 tools/iot2050-sign-fw.sh
 create mode 100755 tools/key2dtsi.py

-- 
2.35.3

[PATCH V7 06/15] iot2050: Add CFG_ENV_FLAGS_LIST_STATIC

[Jan Kiszka]

From: Jan Kiszka 

Will be needed when CONFIG_ENV_WRITEABLE_LIST is enabled. The listed
variables shall remain writable, for informational purposes - they have
to be considered untrusted because the persistent U-Boot env is not
protected.

Signed-off-by: Jan Kiszka 
---
 include/configs/iot2050.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h
index 8dfeaddf541..217719472e5 100644
--- a/include/configs/iot2050.h
+++ b/include/configs/iot2050.h
@@ -40,4 +40,11 @@
 
 #include 
 
+#ifdef CONFIG_ENV_WRITEABLE_LIST
+#define CFG_ENV_FLAGS_LIST_STATIC  \
+   "board_uuid:sw,board_name:sw,board_serial:sw,board_a5e:sw," \
+   "mlfb:sw,fw_version:sw,seboot_version:sw,"  \
+   "eth1addr:mw,eth2addr:mw,watchdog_timeout_ms:dw,boot_targets:sw"
+#endif
+
 #endif /* __CONFIG_IOT2050_H */
-- 
2.35.3

[PATCH V7 02/15] arm: dts: iot2050: Use the auto generator nodes for fdt

[Jan Kiszka]

From: Su Baocheng 

Refactor according to the entry `fit: Entry containing a FIT` of
document tools/binman/README.entries.

As the generator uses the device tree name for the config description,
board_fit_config_name_match requires a small adjustment as well.

Signed-off-by: Su Baocheng 
[Jan: re-add now required CONFIG_OF_LIST, update config matching]
Signed-off-by: Jan Kiszka 
---
 arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 44 
 board/siemens/iot2050/board.c|  3 ++
 configs/iot2050_pg1_defconfig|  1 +
 configs/iot2050_pg2_defconfig|  1 +
 4 files changed, 12 insertions(+), 37 deletions(-)

diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi 
b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
index 3135ad04715..46669576864 100644
--- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
@@ -32,6 +32,7 @@
 
fit@0x28 {
description = "U-Boot for IOT2050";
+   fit,fdt-list = "of-list";
offset = <0x28>;
images {
u-boot {
@@ -46,32 +47,11 @@
};
};
 
-   fdt-iot2050-basic {
-   description = 
"k3-am6528-iot2050-basic*.dtb";
+   @fdt-SEQ {
+   description = "fdt-NAME";
type = "flat_dt";
arch = "arm64";
compression = "none";
-   blob {
-#ifdef CONFIG_TARGET_IOT2050_A53_PG1
-   filename = 
"arch/arm/dts/k3-am6528-iot2050-basic.dtb";
-#else
-   filename = 
"arch/arm/dts/k3-am6528-iot2050-basic-pg2.dtb";
-#endif
-   };
-   };
-
-   fdt-iot2050-advanced {
-   description = 
"k3-am6548-iot2050-advanced*.dtb";
-   type = "flat_dt";
-   arch = "arm64";
-   compression = "none";
-   blob {
-#ifdef CONFIG_TARGET_IOT2050_A53_PG1
-   filename = 
"arch/arm/dts/k3-am6548-iot2050-advanced.dtb";
-#else
-   filename = 
"arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dtb";
-#endif
-   };
};
 
 #ifdef CONFIG_WDT_K3_RTI_FW_FILE
@@ -89,21 +69,11 @@
};
 
configurations {
-   default = "conf-iot2050-basic";
-
-   conf-iot2050-basic {
-   description = "iot2050-basic";
-   firmware = "u-boot";
-   fdt = "fdt-iot2050-basic";
-#ifdef CONFIG_WDT_K3_RTI_FW_FILE
-   loadables = "k3-rti-wdt-firmware";
-#endif
-   };
-
-   conf-iot2050-advanced {
-   description = "iot2050-advanced";
+   default = "@config-DEFAULT-SEQ";
+   @config-SEQ {
+   description = "NAME";
firmware = "u-boot";
-   fdt = "fdt-iot2050-advanced";
+   fdt = "fdt-SEQ";
 #ifdef CONFIG_WDT_K3_RTI_FW_FILE
loadables = "k3-rti-wdt-firmware";
 #endif
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index dbf893000a7..57d7009e8c7 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -154,6 +154,9 @@ int board_fit_config_name_match(const char *name)
struct iot2050_info *info = IOT2050_INFO_DATA;
char upper_name[32];
 
+   /* skip the prefix "k3-am65x8-" */
+   name += 10;
+
if (info->magic != IOT2050_INFO_MAGIC ||
strlen(name) >= sizeof(upper_name))
return -1;
diff --git a/configs/iot2050_pg1_defconfig b/configs/iot2050_pg1_defconfig
index d9580309664..a13fd9ff68d 100644
--- a/configs/iot2050_pg1_defconfig
+++ b/configs/iot2050_pg1_defconfig
@@ -69,6 +69,7 @@ CONFIG_CMD_TIME=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="k3-am6528-iot2050-basic k3-am6548-iot2050-advanced"
 CONFIG_SPL_MULTI_DTB_FIT=y
 

[PATCH V7 01/15] board: siemens: iot2050: Split the build for PG1 and PG2

[Jan Kiszka]

From: Su Baocheng 

Due to different signature keys, the PG1 and the PG2 boards can no
longer use the same FSBL (tiboot3). This makes it impossible anyway to
maintaine a single flash.bin for both variants, so we can also split the
build.

A new target is added to indicates the build is for PG1 vs. PG2 boards.
Hence now the variants have separated defconfig files.

The runtime board_is_sr1() check does make no sense anymore, so remove
it and replace with build time check.

Documentation is updated accordingly. New binary artifacts are already
available via meta-iot2050.

Signed-off-by: Su Baocheng 
[Jan: refactor config option into targets, tweak some wordings]
Signed-off-by: Jan Kiszka 
---
 arch/arm/dts/k3-am65-iot2050-boot-image.dtsi  | 80 ++-
 board/siemens/iot2050/Kconfig | 28 ++-
 board/siemens/iot2050/board.c | 12 +--
 ...ot2050_defconfig => iot2050_pg1_defconfig} |  2 +-
 ...ot2050_defconfig => iot2050_pg2_defconfig} | 10 ++-
 doc/board/siemens/iot2050.rst | 15 +++-
 6 files changed, 70 insertions(+), 77 deletions(-)
 copy configs/{iot2050_defconfig => iot2050_pg1_defconfig} (99%)
 rename configs/{iot2050_defconfig => iot2050_pg2_defconfig} (94%)

diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi 
b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
index 27058370ccc..3135ad04715 100644
--- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) Siemens AG, 2020-2021
+ * Copyright (c) Siemens AG, 2020-2022
  *
  * Authors:
  *   Jan Kiszka 
@@ -17,7 +17,11 @@
 
blob-ext@0x00 {
offset = <0x00>;
-   filename = "tiboot3.bin";
+#ifdef CONFIG_TARGET_IOT2050_A53_PG1
+   filename = "seboot_pg1.bin";
+#else
+   filename = "seboot_pg2.bin";
+#endif
missing-msg = "iot2050-seboot";
};
 
@@ -43,42 +47,30 @@
};
 
fdt-iot2050-basic {
-   description = 
"k3-am6528-iot2050-basic.dtb";
+   description = 
"k3-am6528-iot2050-basic*.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
+#ifdef CONFIG_TARGET_IOT2050_A53_PG1
filename = 
"arch/arm/dts/k3-am6528-iot2050-basic.dtb";
-   };
-   };
-
-   fdt-iot2050-basic-pg2 {
-   description = 
"k3-am6528-iot2050-basic-pg2.dtb";
-   type = "flat_dt";
-   arch = "arm64";
-   compression = "none";
-   blob {
+#else
filename = 
"arch/arm/dts/k3-am6528-iot2050-basic-pg2.dtb";
+#endif
};
};
 
fdt-iot2050-advanced {
-   description = 
"k3-am6548-iot2050-advanced.dtb";
+   description = 
"k3-am6548-iot2050-advanced*.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
+#ifdef CONFIG_TARGET_IOT2050_A53_PG1
filename = 
"arch/arm/dts/k3-am6548-iot2050-advanced.dtb";
-   };
-   };
-
-   fdt-iot2050-advanced-pg2 {
-   description = 
"k3-am6548-iot2050-advanced-pg2.dtb";
-   type = "flat_dt";
-   arch = "arm64";
-   compression = "none";
-   blob {
+#else
filename = 
"arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dtb";
+#endif
};
};
 
@@ -108,30 +100,12 @@
 #endif
};
 
-   conf-iot2050-basic-pg2 {
-   description = "iot2050-basic-pg2";
-   firmware = "u-boot";
-   fdt = "fdt-iot2050-basic-pg2";
-#ifdef CONFIG_WDT_K3_RTI_FW_FILE
-

[PATCH V7 03/15] iot2050: Update firmware layout

[Jan Kiszka]

From: Jan Kiszka 

The latest version of the binary-only firmware parts come in a combined
form of FSBL and sysfw containers. This implies some layout changes to
the generated firmware image but also makes handling of artifacts much
simpler (4 files less). The env locations will not change, just the
space reserved for U-Boot will shrink from 4 to 3 MB - still plenty of
space left in practice.

Adjust configuration and documentation accordingly.

Along this change, add a new reservation for update commands of the
user-controlled OTP part. A specific userspace tool will fill it, and
the FSBL will evaluate it during boot. This reservation will use 64K of
the former sysfw section.

Signed-off-by: Jan Kiszka 
---
 arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 30 ++--
 configs/iot2050_pg1_defconfig|  2 +-
 configs/iot2050_pg2_defconfig|  2 +-
 doc/board/siemens/iot2050.rst|  4 ---
 tools/binman/missing-blob-help   |  8 +-
 5 files changed, 11 insertions(+), 35 deletions(-)

diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi 
b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
index 46669576864..3ee0842e993 100644
--- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
@@ -25,15 +25,15 @@
missing-msg = "iot2050-seboot";
};
 
-   blob@0x08 {
-   offset = <0x08>;
+   blob@0x18 {
+   offset = <0x18>;
filename = "tispl.bin";
};
 
-   fit@0x28 {
+   fit@0x38 {
description = "U-Boot for IOT2050";
fit,fdt-list = "of-list";
-   offset = <0x28>;
+   offset = <0x38>;
images {
u-boot {
description = "U-Boot";
@@ -94,25 +94,11 @@
fill-byte = [00];
};
 
-   /* sysfw, basic variant */
-   blob-ext@0x6c {
+   /* OTP update command block */
+   fill@0x6c {
offset = <0x6c>;
-#ifdef CONFIG_TARGET_IOT2050_A53_PG1
-   filename = "sysfw_sr1.itb";
-#else
-   filename = "sysfw_sr2.itb";
-#endif
-   missing-msg = "iot2050-sysfw";
-   };
-   /* sysfw, advanced variant */
-   blob-ext@0x74 {
-   offset = <0x74>;
-#ifdef CONFIG_TARGET_IOT2050_A53_PG1
-   filename = "sysfw_sr1.itb_HS";
-#else
-   filename = "sysfw_sr2.itb_HS";
-#endif
-   missing-msg = "iot2050-sysfw";
+   size   = <0x01>;
+   fill-byte = [ff];
};
};
 };
diff --git a/configs/iot2050_pg1_defconfig b/configs/iot2050_pg1_defconfig
index a13fd9ff68d..2f7a9d86794 100644
--- a/configs/iot2050_pg1_defconfig
+++ b/configs/iot2050_pg1_defconfig
@@ -52,7 +52,7 @@ CONFIG_SPL_POWER_DOMAIN=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x38
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_PBSIZE=1050
 CONFIG_CMD_ASKENV=y
diff --git a/configs/iot2050_pg2_defconfig b/configs/iot2050_pg2_defconfig
index 65400b4696a..e3f82ad3065 100644
--- a/configs/iot2050_pg2_defconfig
+++ b/configs/iot2050_pg2_defconfig
@@ -54,7 +54,7 @@ CONFIG_SPL_POWER_DOMAIN=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x38
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_PBSIZE=1050
 CONFIG_CMD_ASKENV=y
diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst
index fd3431fa3f8..26972e20ae9 100644
--- a/doc/board/siemens/iot2050.rst
+++ b/doc/board/siemens/iot2050.rst
@@ -25,11 +25,7 @@ 
https://github.com/siemens/meta-iot2050/tree/master/recipes-bsp/u-boot/files/pre
 The following binaries from that source need to be present in the build folder:
 
  - seboot_pg1.bin
- - sysfw_sr1.itb
- - sysfw_sr1.itb_HS
  - seboot_pg2.bin
- - sysfw_sr2.itb
- - sysfw_sr2.itb_HS
 
 Building
 
diff --git a/tools/binman/missing-blob-help b/tools/binman/missing-blob-help
index 4448ac93112..1a30da7b5aa 100644
--- a/tools/binman/missing-blob-help
+++ b/tools/binman/missing-blob-help
@@ -21,13 +21,7 @@ Please read the section on SCP firmware in 
board/sunxi/README.sunxi64
 iot2050-seboot:
 See the documentation for IOT2050 board. Your image is missing SEBoot
 which is mandatory for board startup. Prebuilt SEBoot located at
-meta-iot2050/tree/master/recipes-bsp/u-boot/files/prebuild/tiboot3.bin.
-
-iot2050-sysfw:
-See the