date:20230517




On 2023/5/18 06:53, Jonas Karlman wrote:

Use a similar pattern and delay values as the linux mainline driver to
speed up failing when nothing is connected.

Reduce fail speed from around 5+ seconds down to around one second on a
Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot.

Signed-off-by: Jonas Karlman 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
v2:
- No change

  drivers/pci/pcie_dw_rockchip.c | 68 ++
  1 file changed, 37 insertions(+), 31 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 1b8a1409f6df..82a8b9c96e2b 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -61,9 +61,6 @@ struct rk_pcie {
  #define PCIE_CLIENT_DBG_TRANSITION_DATA   0x
  #define PCIE_CLIENT_DBF_EN0x0003
  
-/* Parameters for the waiting for #perst signal */

-#define MACRO_US   1000
-
  static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
  {
if ((uintptr_t)addr & (size - 1)) {
@@ -242,43 +239,46 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
cap_speed)
/* DW pre link configurations */
rk_pcie_configure(priv, cap_speed);
  
-	/* Rest the device */

-   if (dm_gpio_is_valid(>rst_gpio)) {
-   dm_gpio_set_value(>rst_gpio, 0);
-   /*
-* Minimal is 100ms from spec but we see
-* some wired devices need much more, such as 600ms.
-* Add a enough delay to cover all cases.
-*/
-   udelay(MACRO_US * 1000);
-   dm_gpio_set_value(>rst_gpio, 1);
-   }
-
rk_pcie_disable_ltssm(priv);
rk_pcie_link_status_clear(priv);
rk_pcie_enable_debug(priv);
  
+	/* Reset the device */

+   if (dm_gpio_is_valid(>rst_gpio))
+   dm_gpio_set_value(>rst_gpio, 0);
+
/* Enable LTSSM */
rk_pcie_enable_ltssm(priv);
  
-	for (retries = 0; retries < 5; retries++) {

-   if (is_link_up(priv)) {
-   dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
-rk_pcie_readl_apb(priv, 
PCIE_CLIENT_LTSSM_STATUS));
-   rk_pcie_debug_dump(priv);
-   return 0;
-   }
-
-   dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
-rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
-   rk_pcie_debug_dump(priv);
-   udelay(MACRO_US * 1000);
+   /*
+* PCIe requires the refclk to be stable for 100ms prior to releasing
+* PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
+* Express Card Electromechanical Specification, 1.1. However, we don't
+* know if the refclk is coming from RC's PHY or external OSC. If it's
+* from RC, so enabling LTSSM is the just right place to release #PERST.
+*/
+   mdelay(100);
+   if (dm_gpio_is_valid(>rst_gpio))
+   dm_gpio_set_value(>rst_gpio, 1);
+
+   /* Check if the link is up or not */
+   for (retries = 0; retries < 10; retries++) {
+   if (is_link_up(priv))
+   break;
+
+   mdelay(100);
+   }
+
+   if (retries >= 10) {
+   dev_err(priv->dw.dev, "PCIe-%d Link Fail\n",
+   dev_seq(priv->dw.dev));
+   return -EIO;
}
  
-	dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));

-   /* Link maybe in Gen switch recovery but we need to wait more 1s */
-   udelay(MACRO_US * 1000);
-   return -EIO;
+   dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
+rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
+   rk_pcie_debug_dump(priv);
+   return 0;
  }
  
  static int rockchip_pcie_init_port(struct udevice *dev)

@@ -287,6 +287,12 @@ static int rockchip_pcie_init_port(struct udevice *dev)
u32 val;
struct rk_pcie *priv = dev_get_priv(dev);
  
+	ret = reset_assert_bulk(>rsts);

+   if (ret) {
+   dev_err(dev, "failed to assert resets (ret=%d)\n", ret);
+   return ret;
+   }
+
/* Set power and maybe external ref clk input */
ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
if (ret && ret != -ENOSYS) {

Re: [PATCH v2 3/9] pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed


Hi Jonas,

On 2023/5/18 06:53, Jonas Karlman wrote:

The vpcie3v3 regulator is typically a fixed regulator controlled using
gpio. Change to use enable and disable calls on the regulator instead
of trying to set a voltage value.

Also remove the delay to match linux driver, for a fixed regulator the
startup-delay-us prop can be used in case a startup delay is needed.
Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that
this delay was not needed.

Signed-off-by: Jonas Karlman 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
v2:
- Update commit message

  drivers/pci/pcie_dw_rockchip.c | 17 +++--
  1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 83737e62bc6a..1b8a1409f6df 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -288,21 +288,16 @@ static int rockchip_pcie_init_port(struct udevice *dev)
struct rk_pcie *priv = dev_get_priv(dev);
  
  	/* Set power and maybe external ref clk input */

-   if (priv->vpcie3v3) {
-   ret = regulator_set_value(priv->vpcie3v3, 330);
-   if (ret) {
-   dev_err(priv->dw.dev, "failed to enable vpcie3v3 
(ret=%d)\n",
-   ret);
-   return ret;
-   }
+   ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
+   if (ret && ret != -ENOSYS) {
+   dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
+   return ret;
}
  
-	udelay(MACRO_US * 1000);

-
ret = generic_phy_init(>phy);
if (ret) {
dev_err(dev, "failed to init phy (ret=%d)\n", ret);
-   return ret;
+   goto err_disable_regulator;
}
  
  	ret = generic_phy_power_on(>phy);

@@ -345,6 +340,8 @@ err_power_off_phy:
generic_phy_power_off(>phy);
  err_exit_phy:
generic_phy_exit(>phy);
+err_disable_regulator:
+   regulator_set_enable_if_allowed(priv->vpcie3v3, false);
  
  	return ret;

  }

Re: [PATCH v2 1/9] core: read: add dev_read_addr_size_index_ptr function




On 2023/5/18 06:53, Jonas Karlman wrote:

Add dev_read_addr_size_index_ptr function with the same functionality as
dev_read_addr_size_index, but instead a return pointer is given.
Use map_sysmem() function as cast for the return.

Signed-off-by: Jonas Karlman 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
v2:
- New patch

  drivers/core/read.c | 11 +++
  include/dm/read.h   | 21 +
  2 files changed, 32 insertions(+)

diff --git a/drivers/core/read.c b/drivers/core/read.c
index 0289a2edb6a4..d3c939530aa5 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -150,6 +150,17 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice 
*dev, int index,
return devfdt_get_addr_size_index(dev, index, size);
  }
  
+void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index,

+  fdt_size_t *size)
+{
+   fdt_addr_t addr = dev_read_addr_size_index(dev, index, size);
+
+   if (addr == FDT_ADDR_T_NONE)
+   return NULL;
+
+   return map_sysmem(addr, 0);
+}
+
  void *dev_remap_addr_index(const struct udevice *dev, int index)
  {
fdt_addr_t addr = dev_read_addr_index(dev, index);
diff --git a/include/dm/read.h b/include/dm/read.h
index 56ac076c9f13..7dd43d61a665 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -246,6 +246,20 @@ void *dev_read_addr_index_ptr(const struct udevice *dev, 
int index);
  fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size);
  
+/**

+ * dev_read_addr_size_index_ptr() - Get the indexed reg property of a device
+ *  as a pointer
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of  pairs
+ *and @index is used to select which one is required
+ * @size: place to put size value (on success)
+ *
+ * Return: pointer or NULL if not found
+ */
+void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index,
+  fdt_size_t *size);
+
  /**
   * dev_remap_addr_index() - Get the indexed reg property of a device
   *   as a memory-mapped I/O pointer
@@ -957,6 +971,13 @@ static inline fdt_addr_t dev_read_addr_size_index(const 
struct udevice *dev,
return devfdt_get_addr_size_index(dev, index, size);
  }
  
+static inline void *dev_read_addr_size_index_ptr(const struct udevice *dev,

+int index,
+fdt_size_t *size)
+{
+   return devfdt_get_addr_size_index_ptr(dev, index, size);
+}
+
  static inline fdt_addr_t dev_read_addr_name(const struct udevice *dev,
const char *name)
  {

[PATCH] [u-boot, v2023.05-aspeed-openbmc] ARM: dts: aspeed: add Meta greatlakes board (AST2600)

2023-05-17 Thread Delphine CC Chiu

Add initial version of device tree for Meta Greatlakes BMC which is
equipped with Aspeed AST2600 BMC SoC.

Signed-off-by: Delphine CC Chiu 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/ast2600-greatlakes.dts   | 205 ++
 configs/ast2600_openbmc_spl_defconfig |   1 +
 3 files changed, 207 insertions(+)
 create mode 100644 arch/arm/dts/ast2600-greatlakes.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6c34b83336..c9cb54cddd 100755
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -686,6 +686,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
ast2600-evb.dtb \
ast2600-dcscm.dtb \
ast2600-fpga.dtb \
+   ast2600-greatlakes.dtb \
ast2600-intel.dtb \
ast2600-ncsi.dtb \
ast2600-p10bmc.dtb \
diff --git a/arch/arm/dts/ast2600-greatlakes.dts 
b/arch/arm/dts/ast2600-greatlakes.dts
new file mode 100644
index 00..59d6c7a087
--- /dev/null
+++ b/arch/arm/dts/ast2600-greatlakes.dts
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2022 Meta Platforms Inc.
+/dts-v1/;
+
+#include "ast2600-u-boot.dtsi"
+
+/ {
+   model = "Facebook Greatlakes BMC";
+   compatible = "facebook,greatlakes-bmc", "aspeed,ast2600";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x4000>;
+   };
+
+   chosen {
+   stdout-path = 
+   };
+
+   aliases {
+   spi0 = 
+   ethernet3 = 
+   };
+
+   cpus {
+   cpu@0 {
+   clock-frequency = <8>;
+   };
+   cpu@1 {
+   clock-frequency = <8>;
+   };
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+ {
+   clock-frequency = <4>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_mdio4_default>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   ethphy3: ethernet-phy@3 {
+   reg = <0>;
+   };
+};
+
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+   phy-handle = <>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_rgmii4_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_fmcquad_default>;
+
+   flash@0 {
+   status = "okay";
+   spi-max-frequency = <5000>;
+   spi-tx-bus-width = <4>;
+   spi-rx-bus-width = <4>;
+   };
+
+   flash@1 {
+   status = "okay";
+   spi-max-frequency = <5000>;
+   spi-tx-bus-width = <4>;
+   spi-rx-bus-width = <4>;
+   };
+};
+
+ {
+   status = "okay";
+   line_148 {
+   gpio-hog;
+   gpios = <148 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "bmc-slot1-isolated-enabled";
+   };
+   line_149 {
+   gpio-hog;
+   gpios = <149 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "bmc-slot2-isolated-enabled";
+   };
+   line_150 {
+   gpio-hog;
+   gpios = <150 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "bmc-slot3-isolated-enabled";
+   };
+   line_151 {
+   gpio-hog;
+   gpios = <151 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "bmc-slot4-isolated-enabled";
+   };
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c1_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c2_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c3_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c4_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c5_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c6_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c7_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c8_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c9_default>;
+};
+
+ {
+   mac0-clk-delay = <0x10 0x0a
+ 0x10 0x10
+ 0x10 0x10>;
+   mac1-clk-delay = <0x10 0x0a
+ 0x10 0x10
+ 0x10 0x10>;
+   mac2-clk-delay = <0x08 0x04
+ 0x08 0x04
+ 0x08 0x04>;
+   mac3-clk-delay

[PATCH] ARM: dts: aspeed: add Meta greatlakes board (AST2600)

2023-05-17 Thread Delphine CC Chiu

From: Delphine CC Chiu 

Add initial version of device tree for Meta Greatlakes BMC which is
equipped with Aspeed AST2600 BMC SoC.

Signed-off-by: Delphine CC Chiu 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/ast2600-greatlakes.dts   | 191 ++
 configs/ast2600_openbmc_spl_defconfig |   1 +
 3 files changed, 193 insertions(+)
 create mode 100644 arch/arm/dts/ast2600-greatlakes.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6c34b83336..c9cb54cddd 100755
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -686,6 +686,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
ast2600-evb.dtb \
ast2600-dcscm.dtb \
ast2600-fpga.dtb \
+   ast2600-greatlakes.dtb \
ast2600-intel.dtb \
ast2600-ncsi.dtb \
ast2600-p10bmc.dtb \
diff --git a/arch/arm/dts/ast2600-greatlakes.dts 
b/arch/arm/dts/ast2600-greatlakes.dts
new file mode 100644
index 00..94caf295da
--- /dev/null
+++ b/arch/arm/dts/ast2600-greatlakes.dts
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2022 Meta Platforms Inc.
+/dts-v1/;
+
+#include "ast2600-u-boot.dtsi"
+
+/ {
+   model = "Facebook Greatlakes BMC";
+   compatible = "facebook,greatlakes-bmc", "aspeed,ast2600";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x4000>;
+   };
+
+   chosen {
+   stdout-path = 
+   };
+
+   aliases {
+   spi0 = 
+   ethernet3 = 
+   };
+
+   cpus {
+   cpu@0 {
+   clock-frequency = <8>;
+   };
+   cpu@1 {
+   clock-frequency = <8>;
+   };
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+ {
+   clock-frequency = <4>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_mdio4_default>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   ethphy3: ethernet-phy@3 {
+   reg = <0>;
+   };
+};
+
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+   phy-handle = <>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_rgmii4_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_fmcquad_default>;
+};
+
+ {
+   status = "okay";
+   line_148 {
+   gpio-hog;
+   gpios = <148 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "bmc-slot1-isolated-enabled";
+   };
+   line_149 {
+   gpio-hog;
+   gpios = <149 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "bmc-slot2-isolated-enabled";
+   };
+   line_150 {
+   gpio-hog;
+   gpios = <150 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "bmc-slot3-isolated-enabled";
+   };
+   line_151 {
+   gpio-hog;
+   gpios = <151 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "bmc-slot4-isolated-enabled";
+   };
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c1_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c2_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c3_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c4_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c5_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c6_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c7_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c8_default>;
+};
+
+ {
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c9_default>;
+};
+
+ {
+   mac0-clk-delay = <0x10 0x0a
+ 0x10 0x10
+ 0x10 0x10>;
+   mac1-clk-delay = <0x10 0x0a
+ 0x10 0x10
+ 0x10 0x10>;
+   mac2-clk-delay = <0x08 0x04
+ 0x08 0x04
+ 0x08 0x04>;
+   mac3-clk-delay = <0x08 0x04
+ 0x08 0x04
+ 0x08 0x04>;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
diff --git a/configs/ast2600_openbmc_spl_defconfig 
b/configs/ast2600_openbmc_spl_defconfig
index 95d7651b8e..efd683570f 100644
--- a/configs/ast2600_openbmc_spl_defconfig
+++

Re: [PATCH 2/2] configs: rock5b-rk3588: add rtl8169 driver




On 2023/4/25 21:06, Eugen Hristev wrote:

Add the rtl8169 driver, which supports the rtl8125b device, which is
connected on the pciE bus on this board.
Enable also CONFIG_SYS_HAS_NONCACHED_MEMORY to have the descriptors stored.

Signed-off-by: Eugen Hristev 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  configs/rock5b-rk3588_defconfig | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index a14fcd2ee924..bfa48227aee2 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -1,5 +1,6 @@
  CONFIG_ARM=y
  CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
  CONFIG_COUNTER_FREQUENCY=2400
  CONFIG_ARCH_ROCKCHIP=y
  CONFIG_TEXT_BASE=0x00a0
@@ -71,6 +72,7 @@ CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
  CONFIG_SPI_FLASH_MACRONIX=y
  CONFIG_ETH_DESIGNWARE=y
+CONFIG_RTL8169=y
  CONFIG_GMAC_ROCKCHIP=y
  CONFIG_PCI=y
  CONFIG_PCIE_DW_ROCKCHIP=y

Re: [PATCH] rockchip: Pinebook Pro: Fix emmc default configuration




On 2023/5/1 15:43, Wolfgang Zarre wrote:

If u-boot is installed on the internal emmc, then this will
allow to boot without failure.

Signed-off-by: Wolfgang Zarre 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---

  configs/pinebook-pro-rk3399_defconfig | 12 ++--
  1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/configs/pinebook-pro-rk3399_defconfig 
b/configs/pinebook-pro-rk3399_defconfig
index dff4695e37..58a8b91aa6 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -6,6 +6,7 @@ CONFIG_TEXT_BASE=0x0020
  CONFIG_NR_DRAM_BANKS=1
  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30
+CONFIG_SF_DEFAULT_SPEED=2000
  CONFIG_ENV_SIZE=0x8000
  CONFIG_ENV_OFFSET=0x3F8000
  CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
@@ -18,6 +19,7 @@ CONFIG_DEBUG_UART_CLOCK=2400
  CONFIG_SPL_SPI_FLASH_SUPPORT=y
  CONFIG_SPL_SPI=y
  CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
  CONFIG_DEBUG_UART=y
  CONFIG_BOOTDELAY=3
  CONFIG_USE_PREBOOT=y
@@ -57,17 +59,23 @@ CONFIG_LED=y
  CONFIG_LED_GPIO=y
  CONFIG_MISC=y
  CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
  CONFIG_MMC_DW=y
  CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
  CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=2000
  CONFIG_SPI_FLASH_GIGADEVICE=y
  CONFIG_SPI_FLASH_WINBOND=y
  CONFIG_NVME_PCI=y
-CONFIG_PCI=y
  CONFIG_PHY_ROCKCHIP_INNO_USB2=y
  CONFIG_PHY_ROCKCHIP_TYPEC=y
  CONFIG_DM_PMIC_FAN53555=y

Re: [PATCH v2 13/13] rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash


Hi Jonas,


On 2023/5/18 02:26, Jonas Karlman wrote:

Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Add and use BROM_BOOTSOURCE_SPINOR_RK3588 enum value
- Rebased to resolve conflicts
- Collect r-b tag

  arch/arm/dts/rk3588-rock-5b-u-boot.dtsi  | 24 
  arch/arm/dts/rk3588s-u-boot.dtsi | 20 
  arch/arm/include/asm/arch-rockchip/bootrom.h |  1 +
  arch/arm/mach-rockchip/rk3588/rk3588.c   |  1 +
  configs/rock5b-rk3588_defconfig  | 10 
  5 files changed, 56 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index db342e6a9391..1cd8a57a6fa6 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -11,6 +11,7 @@
  / {
aliases {
mmc1 = 
+   spi0 = 
};
  
  	chosen {

@@ -54,6 +55,10 @@
bootph-all;
  };
  
+_pins {

+   bootph-all;
+};
+
   {
pinctrl-names = "default";
pinctrl-0 = <_pins _reset_h>;
@@ -123,6 +128,25 @@
pinctrl-0 = <_bus8 _clk _cmd _data_strobe 
_rstnout>;
  };
  
+ {

+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
  _xfer {
bootph-all;
  };
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 2c4cad82b38f..64c309046587 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -165,6 +165,15 @@
};
};
  
+	sfc: spi@fe2b {

+   compatible = "rockchip,sfc";
+   reg = <0x0 0xfe2b 0x0 0x4000>;
+   interrupts = ;
+   clocks = < SCLK_SFC>, < HCLK_SFC>;
+   clock-names = "clk_sfc", "hclk_sfc";
+   status = "disabled";
+   };
+
otp: nvmem@fecc {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc 0x0 0x400>;
@@ -241,3 +250,14 @@
   {
bootph-pre-ram;
  };
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+ {
+   simple-bin-spi {
+   mkimage {
+   args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+   offset = <0x8000>;
+   };
+   };
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h 
b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 4276a0f6811a..7dab18fbc3fb 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -48,6 +48,7 @@ enum {
BROM_BOOTSOURCE_SPINOR = 3,
BROM_BOOTSOURCE_SPINAND = 4,
BROM_BOOTSOURCE_SD = 5,
+   BROM_BOOTSOURCE_SPINOR_RK3588 = 6,


Why we need a new type of SPINOR_RK3588?

And this patch not able to apply due to conflict at rk3588s-u-boot.dtsi.


BROM_BOOTSOURCE_USB = 10,
BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
  };
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c 
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 18e67b5ca9b2..b1f535fad505 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e",
[BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe2c",
+   [BROM_BOOTSOURCE_SPINOR_RK3588] = "/spi@fe2b/flash@0",


BROM_BOOTSOURCE_SPINOR is already there, why add BROM_BOOTSOURCE_SPINOR_RK3588 ?




Thanks,

- Kever

  };
  
  static struct mm_region rk3588_mem_map[] = {

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 5fe3a3542e11..9d0b55c01ac9 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
  CONFIG_NR_DRAM_BANKS=2
  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
  CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
  CONFIG_ROCKCHIP_RK3588=y
  CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
  CONFIG_SPL_SERIAL=y
  CONFIG_SPL_STACK_R_ADDR=0x60
  CONFIG_TARGET_ROCK5B_RK3588=y
  CONFIG_SPL_STACK=0x40
  CONFIG_DEBUG_UART_BASE=0xFEB5
  CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
  CONFIG_SYS_LOAD_ADDR=0xc00800
  CONFIG_PCI=y
  CONFIG_DEBUG_UART=y
@@ -36,6 +41,8 @@

Re: [PATCH v6] configs: rockchip: rock5b-rk3588: enable USB and regulators

Hi Eugen,

On 2023-05-17 12:34, Eugen Hristev wrote:
> On 5/17/23 12:38, Kever Yang wrote:
>> Hi Eugen,
>>
>> Applied, thanks.
>>
>>
>> - Kever
>>
> 
> Hi Kever,
> 
> Any other patches that you wish me to resend ?
> 
> Also, Jonas,
> 
> I have one thing in my tree that may be already sent by you, but let's 
> double check: adding gpio command to rock5b config, have you sent that 
> already ?

Yes, was included as part of my defconfig sync series.
See 
https://patchwork.ozlabs.org/project/uboot/patch/20230517182624.1765359-12-jo...@kwiboo.se/

Regards,
Jonas

> 
> Thanks,
> Eugen
> 
>

[PATCH v2 9/9] rockchip: rk356x: Update PCIe config, IO and memory regions

Update config, IO and memory regions used based on [1] with pcie3x2
config reg address and reg size corrected.

Before this change:

  PCI Autoconfig: Bus Memory region: [0-3eef],
  PCI Autoconfig: Bus I/O region: [3ef0-3eff],

After this change:

  PCI Autoconfig: Bus Memory region: [4000-7fff],
  PCI Autoconfig: Bus I/O region: [f010-f01f],

[1] https://lore.kernel.org/lkml/20221112114125.1637543-2-ahol...@omnom.net/

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Update commit message
- Collect r-b tag

 arch/arm/dts/rk3568.dtsi | 14 --
 arch/arm/dts/rk356x.dtsi |  7 ---
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index ba67b58f05b7..f1be76a54ceb 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -94,9 +94,10 @@
power-domains = < RK3568_PD_PIPE>;
reg = <0x3 0xc040 0x0 0x0040>,
  <0x0 0xfe27 0x0 0x0001>,
- <0x3 0x7f00 0x0 0x0100>;
-   ranges = <0x0100 0x0 0x3ef0 0x3 0x7ef0 0x0 
0x0010>,
-<0x0200 0x0 0x 0x3 0x4000 0x0 
0x3ef0>;
+ <0x0 0xf200 0x0 0x0010>;
+   ranges = <0x0100 0x0 0xf210 0x0 0xf210 0x0 
0x0010>,
+<0x0200 0x0 0xf220 0x0 0xf220 0x0 
0x01e0>,
+<0x0300 0x0 0x4000 0x3 0x4000 0x0 
0x4000>;
reg-names = "dbi", "apb", "config";
resets = < SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
@@ -146,9 +147,10 @@
power-domains = < RK3568_PD_PIPE>;
reg = <0x3 0xc080 0x0 0x0040>,
  <0x0 0xfe28 0x0 0x0001>,
- <0x3 0xbf00 0x0 0x0100>;
-   ranges = <0x0100 0x0 0x3ef0 0x3 0xbef0 0x0 
0x0010>,
-<0x0200 0x0 0x 0x3 0x8000 0x0 
0x3ef0>;
+ <0x0 0xf000 0x0 0x0010>;
+   ranges = <0x0100 0x0 0xf010 0x0 0xf010 0x0 
0x0010>,
+<0x0200 0x0 0xf020 0x0 0xf020 0x0 
0x01e0>,
+<0x0300 0x0 0x4000 0x3 0x8000 0x0 
0x4000>;
reg-names = "dbi", "apb", "config";
resets = < SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 6492ace0de6b..e0591c194bec 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -951,7 +951,7 @@
compatible = "rockchip,rk3568-pcie";
reg = <0x3 0xc000 0x0 0x0040>,
  <0x0 0xfe26 0x0 0x0001>,
- <0x3 0x3f00 0x0 0x0100>;
+ <0x0 0xf400 0x0 0x0010>;
reg-names = "dbi", "apb", "config";
interrupts = ,
 ,
@@ -980,8 +980,9 @@
phys = < PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = < RK3568_PD_PIPE>;
-   ranges = <0x0100 0x0 0x3ef0 0x3 0x3ef0 0x0 
0x0010
- 0x0200 0x0 0x 0x3 0x 0x0 
0x3ef0>;
+   ranges = <0x0100 0x0 0xf410 0x0 0xf410 0x0 
0x0010>,
+<0x0200 0x0 0xf420 0x0 0xf420 0x0 
0x01e0>,
+<0x0300 0x0 0x4000 0x3 0x 0x0 
0x4000>;
resets = < SRST_PCIE20_POWERUP>;
reset-names = "pipe";
#address-cells = <3>;
-- 
2.40.1

[PATCH v2 8/9] rockchip: rk3568-rock-3a: Enable PCIe and NVMe support

Add missing pinctrl and defconfig options to enable PCIe and NVMe
support on Radxa ROCK 3 Model A.

Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1.
The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is
restored to the perstn pin, a workaround to avoid having to define
a new rockchip,pins.

Signed-off-by: Jonas Karlman 
---
v2:
- Update commit message
- Disable pcie2x1 to work around a possible sys freeze issue

 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 16 
 configs/rock-3a-rk3568_defconfig|  4 
 2 files changed, 20 insertions(+)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index bbf54f888fa0..bbfce7f4c247 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -36,8 +36,24 @@
bootph-all;
 };
 
+ {
+   pinctrl-0 = <_pins _reset_h>;
+   /* Shared vpcie3v3-supply may cause a sys freeze, disable for now */
+   status = "disabled";
+};
+
+ {
+   pinctrl-0 = <_pins _reset_h>;
+};
+
  {
bootph-all;
+
+   pcie {
+   pcie3x2_reset_h: pcie3x2-reset-h {
+   rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO _pull_none>;
+   };
+   };
 };
 
 _pull_none {
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 64864a300153..16775015afa2 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -23,6 +23,7 @@ CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -46,6 +47,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
@@ -70,6 +72,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_SPL_PINCTRL=y
-- 
2.40.1

[PATCH v2 7/9] rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support

Add dummy support for the CLK_PCIEPHY2_REF clock.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Collect r-b tag

 drivers/clk/rockchip/clk_rk3568.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index 6bdd96f35b5c..0df82f597152 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong 
rate)
break;
case CLK_PCIEPHY0_REF:
case CLK_PCIEPHY1_REF:
+   case CLK_PCIEPHY2_REF:
return 0;
default:
return -ENOENT;
-- 
2.40.1

[PATCH v2 5/9] pci: pcie_dw_rockchip: Hide BARs of the root complex

PCI Autoconfig read the Root Complex BARs and try to claim the entire
1 GiB memory region on RK3568, leaving no space for any attached device.

With a memory region less than 1 GiB this was not a real issue:

  PCI Autoconfig: Bus Memory region: [0-3eef],
  PCI Autoconfig: Bus I/O region: [3ef0-3eff],
  PCI Autoconfig: Found P2P bridge, device 0
  PCI Autoconfig: BAR 0, Mem, size=0x4000, No room in resource, avail 
start=1000 / size=3ef0, need=4000
  PCI: Failed autoconfig bar 10
  PCI Autoconfig: BAR 1, Mem, size=0x4000, No room in resource, avail 
start=1000 / size=3ef0, need=4000
  PCI: Failed autoconfig bar 14
  PCI Autoconfig: ROM, size=0x1, address=0x1 bus_lower=0x2

  PCI Autoconfig: BAR 0, Mem64, size=0x4000, address=0x10 bus_lower=0x104000

With a memory region of the entire 1 GiB this leads to:

  PCI Autoconfig: Bus Memory region: [4000-7fff],
  PCI Autoconfig: Bus I/O region: [f010-f01f],
  PCI Autoconfig: Found P2P bridge, device 0
  PCI Autoconfig: BAR 0, Mem, size=0x4000, address=0x4000 
bus_lower=0x8000
  PCI Autoconfig: BAR 1, Mem, size=0x4000, No room in resource, avail 
start=8000 / size=4000, need=4000
  PCI: Failed autoconfig bar 14
  PCI Autoconfig: ROM, size=0x1, No room in resource, avail start=8000 
/ size=4000, need=1

  PCI Autoconfig: BAR 0, Mem64, size=0x4000, No room in resource, avail 
start=8000 / size=4000, need=4000
  PCI: Failed autoconfig bar 10

After this change with a memory region of the entire 1 GiB:

  PCI Autoconfig: Bus Memory region: [4000-7fff],
  PCI Autoconfig: Bus I/O region: [f010-f01f],
  PCI Autoconfig: Found P2P bridge, device 0
  PCI Autoconfig: ROM, size=0x1, address=0x4000 bus_lower=0x4001

  PCI Autoconfig: BAR 0, Mem64, size=0x4000, address=0x4010 
bus_lower=0x40104000

Return an invalid value during config read of Root Complex BARs during
autoconfig to work around such issue.

Signed-off-by: Jonas Karlman 
---
v2:
- Update commit message

 drivers/pci/pcie_dw_rockchip.c | 28 +++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 82a8b9c96e2b..f56773c2e58c 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -146,6 +146,32 @@ static inline void rk_pcie_writel_apb(struct rk_pcie 
*rk_pcie, u32 reg,
__rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
 }
 
+/**
+ * The BARs of bridge should be hidden during enumeration to avoid
+ * allocation of the entire memory region by PCIe core on RK3568.
+ */
+static bool rk_pcie_hide_rc_bar(struct pcie_dw *pcie, pci_dev_t bdf,
+   uint offset)
+{
+   int bus = PCI_BUS(bdf) - pcie->first_busno;
+
+   return bus == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+  offset >= PCI_BASE_ADDRESS_0 && offset <= PCI_BASE_ADDRESS_1;
+}
+
+static int rk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
+  uint offset, ulong *valuep,
+  enum pci_size_t size)
+{
+   struct pcie_dw *pcie = dev_get_priv(bus);
+   int ret = pcie_dw_read_config(bus, bdf, offset, valuep, size);
+
+   if (!ret && rk_pcie_hide_rc_bar(pcie, bdf, offset))
+   *valuep = pci_get_ff(size);
+
+   return ret;
+}
+
 /**
  * rk_pcie_configure() - Configure link capabilities and speed
  *
@@ -476,7 +502,7 @@ rockchip_pcie_probe_err_init_port:
 }
 
 static const struct dm_pci_ops rockchip_pcie_ops = {
-   .read_config= pcie_dw_read_config,
+   .read_config= rk_pcie_read_config,
.write_config   = pcie_dw_write_config,
 };
 
-- 
2.40.1

[PATCH v2 6/9] regulator: fixed: Add support for gpios prop

The commit 12df2c182ccb ("regulator: dt-bindings: fixed-regulator: allow
gpios property") in linux v6.3-rc1 added support for use of either a
gpios or gpio prop with a fixed-regulator.

This adds support for the new gpios prop to the fixed-regulator driver.
gpios prop is used by vcc3v3-pcie-regulator on Radxa ROCK 3 Model A.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Update commit message
- Collect r-b tag

 drivers/power/regulator/fixed.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c
index 90004d1601a9..e921a5984ef7 100644
--- a/drivers/power/regulator/fixed.c
+++ b/drivers/power/regulator/fixed.c
@@ -25,6 +25,7 @@ static int fixed_regulator_of_to_plat(struct udevice *dev)
 {
struct dm_regulator_uclass_plat *uc_pdata;
struct regulator_common_plat *dev_pdata;
+   bool gpios;
 
dev_pdata = dev_get_plat(dev);
uc_pdata = dev_get_uclass_plat(dev);
@@ -33,7 +34,9 @@ static int fixed_regulator_of_to_plat(struct udevice *dev)
 
uc_pdata->type = REGULATOR_TYPE_FIXED;
 
-   return regulator_common_of_to_plat(dev, dev_pdata, "gpio");
+   gpios = dev_read_bool(dev, "gpios");
+   return regulator_common_of_to_plat(dev, dev_pdata,
+  gpios ? "gpios" : "gpio");
 }
 
 static int fixed_regulator_get_value(struct udevice *dev)
-- 
2.40.1

[PATCH v2 4/9] pci: pcie_dw_rockchip: Speed up link probe

Use a similar pattern and delay values as the linux mainline driver to
speed up failing when nothing is connected.

Reduce fail speed from around 5+ seconds down to around one second on a
Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot.

Signed-off-by: Jonas Karlman 
---
v2:
- No change

 drivers/pci/pcie_dw_rockchip.c | 68 ++
 1 file changed, 37 insertions(+), 31 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 1b8a1409f6df..82a8b9c96e2b 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -61,9 +61,6 @@ struct rk_pcie {
 #define PCIE_CLIENT_DBG_TRANSITION_DATA0x
 #define PCIE_CLIENT_DBF_EN 0x0003
 
-/* Parameters for the waiting for #perst signal */
-#define MACRO_US   1000
-
 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 {
if ((uintptr_t)addr & (size - 1)) {
@@ -242,43 +239,46 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
cap_speed)
/* DW pre link configurations */
rk_pcie_configure(priv, cap_speed);
 
-   /* Rest the device */
-   if (dm_gpio_is_valid(>rst_gpio)) {
-   dm_gpio_set_value(>rst_gpio, 0);
-   /*
-* Minimal is 100ms from spec but we see
-* some wired devices need much more, such as 600ms.
-* Add a enough delay to cover all cases.
-*/
-   udelay(MACRO_US * 1000);
-   dm_gpio_set_value(>rst_gpio, 1);
-   }
-
rk_pcie_disable_ltssm(priv);
rk_pcie_link_status_clear(priv);
rk_pcie_enable_debug(priv);
 
+   /* Reset the device */
+   if (dm_gpio_is_valid(>rst_gpio))
+   dm_gpio_set_value(>rst_gpio, 0);
+
/* Enable LTSSM */
rk_pcie_enable_ltssm(priv);
 
-   for (retries = 0; retries < 5; retries++) {
-   if (is_link_up(priv)) {
-   dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
-rk_pcie_readl_apb(priv, 
PCIE_CLIENT_LTSSM_STATUS));
-   rk_pcie_debug_dump(priv);
-   return 0;
-   }
-
-   dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
-rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
-   rk_pcie_debug_dump(priv);
-   udelay(MACRO_US * 1000);
+   /*
+* PCIe requires the refclk to be stable for 100ms prior to releasing
+* PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
+* Express Card Electromechanical Specification, 1.1. However, we don't
+* know if the refclk is coming from RC's PHY or external OSC. If it's
+* from RC, so enabling LTSSM is the just right place to release #PERST.
+*/
+   mdelay(100);
+   if (dm_gpio_is_valid(>rst_gpio))
+   dm_gpio_set_value(>rst_gpio, 1);
+
+   /* Check if the link is up or not */
+   for (retries = 0; retries < 10; retries++) {
+   if (is_link_up(priv))
+   break;
+
+   mdelay(100);
+   }
+
+   if (retries >= 10) {
+   dev_err(priv->dw.dev, "PCIe-%d Link Fail\n",
+   dev_seq(priv->dw.dev));
+   return -EIO;
}
 
-   dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
-   /* Link maybe in Gen switch recovery but we need to wait more 1s */
-   udelay(MACRO_US * 1000);
-   return -EIO;
+   dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
+rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
+   rk_pcie_debug_dump(priv);
+   return 0;
 }
 
 static int rockchip_pcie_init_port(struct udevice *dev)
@@ -287,6 +287,12 @@ static int rockchip_pcie_init_port(struct udevice *dev)
u32 val;
struct rk_pcie *priv = dev_get_priv(dev);
 
+   ret = reset_assert_bulk(>rsts);
+   if (ret) {
+   dev_err(dev, "failed to assert resets (ret=%d)\n", ret);
+   return ret;
+   }
+
/* Set power and maybe external ref clk input */
ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
if (ret && ret != -ENOSYS) {
-- 
2.40.1

[PATCH v2 2/9] pci: pcie_dw_rockchip: Get config region from reg prop

Get the config region to use from the reg prop. Also update the
referenced region index used in comment.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Use dev_read_addr_size_index_ptr
- Collect r-b tag

 drivers/pci/pcie_dw_common.c   | 10 ++
 drivers/pci/pcie_dw_rockchip.c |  7 +++
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
index 9f8b016d1149..74fb6df412c7 100644
--- a/drivers/pci/pcie_dw_common.c
+++ b/drivers/pci/pcie_dw_common.c
@@ -141,9 +141,9 @@ static uintptr_t set_cfg_address(struct pcie_dw *pcie,
 
/*
 * Not accessing root port configuration space?
-* Region #0 is used for Outbound CFG space access.
+* Region #1 is used for Outbound CFG space access.
 * Direction = Outbound
-* Region Index = 0
+* Region Index = 1
 */
d = PCI_MASK_BUS(d);
d = PCI_ADD_BUS(bus, d);
@@ -328,8 +328,10 @@ void pcie_dw_setup_host(struct pcie_dw *pci)
pci->prefetch.bus_start = hose->regions[ret].bus_start; 
 /* PREFETCH_bus_addr */
pci->prefetch.size = hose->regions[ret].size;   /* 
PREFETCH size */
} else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) {
-   pci->cfg_base = (void *)(pci->io.phys_start - 
pci->io.size);
-   pci->cfg_size = pci->io.size;
+   if (!pci->cfg_base) {
+   pci->cfg_base = (void *)(pci->io.phys_start - 
pci->io.size);
+   pci->cfg_size = pci->io.size;
+   }
} else {
dev_err(pci->dev, "invalid flags type!\n");
}
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 6da618055cbe..83737e62bc6a 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -366,6 +366,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
 
dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
 
+   priv->dw.cfg_base = dev_read_addr_size_index_ptr(dev, 2,
+>dw.cfg_size);
+   if (!priv->dw.cfg_base)
+   return -EINVAL;
+
+   dev_dbg(dev, "CFG address is 0x%p\n", priv->dw.cfg_base);
+
ret = gpio_request_by_name(dev, "reset-gpios", 0,
   >rst_gpio, GPIOD_IS_OUT);
if (ret) {
-- 
2.40.1

[PATCH v2 3/9] pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed

The vpcie3v3 regulator is typically a fixed regulator controlled using
gpio. Change to use enable and disable calls on the regulator instead
of trying to set a voltage value.

Also remove the delay to match linux driver, for a fixed regulator the
startup-delay-us prop can be used in case a startup delay is needed.
Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that
this delay was not needed.

Signed-off-by: Jonas Karlman 
---
v2:
- Update commit message

 drivers/pci/pcie_dw_rockchip.c | 17 +++--
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 83737e62bc6a..1b8a1409f6df 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -288,21 +288,16 @@ static int rockchip_pcie_init_port(struct udevice *dev)
struct rk_pcie *priv = dev_get_priv(dev);
 
/* Set power and maybe external ref clk input */
-   if (priv->vpcie3v3) {
-   ret = regulator_set_value(priv->vpcie3v3, 330);
-   if (ret) {
-   dev_err(priv->dw.dev, "failed to enable vpcie3v3 
(ret=%d)\n",
-   ret);
-   return ret;
-   }
+   ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
+   if (ret && ret != -ENOSYS) {
+   dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
+   return ret;
}
 
-   udelay(MACRO_US * 1000);
-
ret = generic_phy_init(>phy);
if (ret) {
dev_err(dev, "failed to init phy (ret=%d)\n", ret);
-   return ret;
+   goto err_disable_regulator;
}
 
ret = generic_phy_power_on(>phy);
@@ -345,6 +340,8 @@ err_power_off_phy:
generic_phy_power_off(>phy);
 err_exit_phy:
generic_phy_exit(>phy);
+err_disable_regulator:
+   regulator_set_enable_if_allowed(priv->vpcie3v3, false);
 
return ret;
 }
-- 
2.40.1

[PATCH v2 1/9] core: read: add dev_read_addr_size_index_ptr function

Add dev_read_addr_size_index_ptr function with the same functionality as
dev_read_addr_size_index, but instead a return pointer is given.
Use map_sysmem() function as cast for the return.

Signed-off-by: Jonas Karlman 
---
v2:
- New patch

 drivers/core/read.c | 11 +++
 include/dm/read.h   | 21 +
 2 files changed, 32 insertions(+)

diff --git a/drivers/core/read.c b/drivers/core/read.c
index 0289a2edb6a4..d3c939530aa5 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -150,6 +150,17 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice 
*dev, int index,
return devfdt_get_addr_size_index(dev, index, size);
 }
 
+void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index,
+  fdt_size_t *size)
+{
+   fdt_addr_t addr = dev_read_addr_size_index(dev, index, size);
+
+   if (addr == FDT_ADDR_T_NONE)
+   return NULL;
+
+   return map_sysmem(addr, 0);
+}
+
 void *dev_remap_addr_index(const struct udevice *dev, int index)
 {
fdt_addr_t addr = dev_read_addr_index(dev, index);
diff --git a/include/dm/read.h b/include/dm/read.h
index 56ac076c9f13..7dd43d61a665 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -246,6 +246,20 @@ void *dev_read_addr_index_ptr(const struct udevice *dev, 
int index);
 fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size);
 
+/**
+ * dev_read_addr_size_index_ptr() - Get the indexed reg property of a device
+ *  as a pointer
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of  pairs
+ *and @index is used to select which one is required
+ * @size: place to put size value (on success)
+ *
+ * Return: pointer or NULL if not found
+ */
+void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index,
+  fdt_size_t *size);
+
 /**
  * dev_remap_addr_index() - Get the indexed reg property of a device
  *   as a memory-mapped I/O pointer
@@ -957,6 +971,13 @@ static inline fdt_addr_t dev_read_addr_size_index(const 
struct udevice *dev,
return devfdt_get_addr_size_index(dev, index, size);
 }
 
+static inline void *dev_read_addr_size_index_ptr(const struct udevice *dev,
+int index,
+fdt_size_t *size)
+{
+   return devfdt_get_addr_size_index_ptr(dev, index, size);
+}
+
 static inline fdt_addr_t dev_read_addr_name(const struct udevice *dev,
const char *name)
 {
-- 
2.40.1

[PATCH v2 0/9] rockchip: Fix PCIe and NVMe support on RK3568

This series fixes and enables PCIe and NVMe support on RK3568.

Patch 1 adds a dev_read_addr_size_index_ptr function.
Patch 2-3 fixes main issue in the driver to be usable on RK3568.
Patch 4 fixes a long wait time during probe when no device is attached.
Patch 5 hides BARs of the root complex that could claim the entire
memory region during PCI autoconfig.
Patch 6 adds support for the gpios prop to the fixed regulators driver.
Patch 7 adds a missing clock to the clock driver.
Patch 8 enables PCIe and NVMe support on rk3568-rock-3a.
Patch 9 updates the device tree with new reg and ranges values.

For a clean apply of patch 8, the series at [1] may be needed.

I have tested that a Samsung 970 EVO NVMe is detected on a ROCK 3A,

BusDevFun VendorId DeviceId Device Class Sub-Class
00.00.00 0x1d87 0x3566 Bridge device 0x04
01.00.00 0x144d 0xa808 Mass storage controller 0x08

and I have also verified that the network controller continues to be
detected on a ROCK 5B.

BusDevFun VendorId DeviceId Device Class Sub-Class
00.00.00 0x1d87 0x3588 Bridge device 0x04
01.00.00 0x10ec 0x8125 Network controller 0x00

Changes in v2:
- Rebased on custodians/u-boot-rockchip master branch and the defconfig
and spi v2 series at [1].
- Drop dependency on basic reference counting of gpio regulators series,
pcie2x1 is disabled for rk3568-rock-3a to avoid a system freeze due to
disable of a shared vpcie3v3-supply regulator while in use by pcie3x2.
- Add and use dev_read_addr_size_index_ptr function.
- Update commit messages.
- Collect r-b tags.

This series can also be found at [2].

[1]
https://patchwork.ozlabs.org/project/uboot/cover/20230517182624.1765359-1-jo...@kwiboo.se/
[2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-pcie-v2

Jonas Karlman (9):
core: read: add dev_read_addr_size_index_ptr function
pci: pcie_dw_rockchip: Get config region from reg prop
pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed
pci: pcie_dw_rockchip: Speed up link probe
pci: pcie_dw_rockchip: Hide BARs of the root complex
regulator: fixed: Add support for gpios prop
rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support
rockchip: rk3568-rock-3a: Enable PCIe and NVMe support
rockchip: rk356x: Update PCIe config, IO and memory regions

--
2.40.1

[PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-05-17 Thread Marek Vasut

In case the DHSOM is in suspend state and either reset button is pushed
or IWDG2 triggers a watchdog reset, then DRAM initialization could fail
as follows:

  "
  RAM: DDR3L 32bits 2x4Gb 533MHz
  DDR invalid size : 0x4, expected 0x4000
  DRAM init failed: -22
  ### ERROR ### Please RESET the board ###
  "

Avoid this failure by not keeping any Buck regulators enabled during reset,
let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3
VDD enabled during reset is ST specific, move this addition to ST specific
SPL board initialization so that it wouldn't affect the DHSOM .

Signed-off-by: Marek Vasut 
---
NOTE: This is 2023.07 material
NOTE: d1a4b09de64 ("board: st: stpmic1: add function stpmic1_init")
  mentions 'keep vdd on during the reset cycle (to avoid issue
  when backup battery is absent)', but there is no further
  description of the 'issue'. Can you please elaborate ?
---
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: uboot-st...@st-md-mailman.stormreply.com
---
 board/st/common/stpmic1.c | 10 +++---
 board/st/common/stpmic1.h |  2 +-
 board/st/stm32mp1/spl.c   | 13 +++--
 3 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index d52dce4f657..969ad484864 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -185,21 +185,17 @@ static int stmpic_buck1_set(struct udevice *dev, u32 
voltage_mv)
 }
 
 /* early init of PMIC */
-void stpmic1_init(u32 voltage_mv)
+struct udevice *stpmic1_init(u32 voltage_mv)
 {
struct udevice *dev;
 
if (uclass_get_device_by_driver(UCLASS_PMIC,
DM_DRIVER_GET(pmic_stpmic1), ))
-   return;
+   return NULL;
 
/* update VDDCORE = BUCK1 */
if (voltage_mv)
stmpic_buck1_set(dev, voltage_mv);
 
-   /* Keep vdd on during the reset cycle */
-   pmic_clrsetbits(dev,
-   STPMIC1_BUCKS_MRST_CR,
-   STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
-   STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+   return dev;
 }
diff --git a/board/st/common/stpmic1.h b/board/st/common/stpmic1.h
index b17d6f16338..7a7169d7cea 100644
--- a/board/st/common/stpmic1.h
+++ b/board/st/common/stpmic1.h
@@ -3,4 +3,4 @@
  * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
  */
 
-void stpmic1_init(u32 voltage_mv);
+struct udevice *stpmic1_init(u32 voltage_mv);
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
index 747ec7e445a..8b4a529f759 100644
--- a/board/st/stm32mp1/spl.c
+++ b/board/st/stm32mp1/spl.c
@@ -5,6 +5,8 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include "../common/stpmic1.h"
 
@@ -19,8 +21,15 @@ void board_vddcore_init(u32 voltage_mv)
 
 int board_early_init_f(void)
 {
-   if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER))
-   stpmic1_init(opp_voltage_mv);
+   if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) {
+   struct udevice *dev = stpmic1_init(opp_voltage_mv);
+
+   /* Keep vdd on during the reset cycle */
+   pmic_clrsetbits(dev,
+   STPMIC1_BUCKS_MRST_CR,
+   STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
+   STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+   }
 
return 0;
 }
-- 
2.39.2

Re: U-Boot OMAP GPMC ECC change

2023-05-17 Thread Colin Foster

Hi Roger,

Thanks for the tests. I attached the files and commented in line... but
at the bottom of this email I have some findings...

On Wed, May 17, 2023 at 04:30:55PM +0300, Roger Quadros wrote:
> Hi Colin,
> 
> I just tested this on AM335x EVM which uses BCH8_CODE_HW but 8-bit NAND part.
> I see that you are using 16-bit NAND.
> 
> One more difference in u-boot configuration. For me:
> CONFIG_NAND_OMAP_GPMC_PREFETCH=y
> 
> Not sure if that matters but let's keep it set for now.
> 
> For debug can you please apply the patch (at end) to u-boot at commit 
> a95410696d21
> (before breakage) and run the test.
> 
> Test procedure:
> 
> > nand dump 0

=> nand dump 0
Page  dump:
40 00 00 00 0c 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 43 48 53 45  54 54 49 4e 47 53 00 00
ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff
c1 c0 c0 c0 00 01 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
dc 99 00 00 00 00 30 40  ff ff ff ea 1a 06 00 ea
00 00 0f e1 1f 10 00 e2  1a 00 31 e3 1f 00 c0 13
13 00 80 13 c0 00 80 e3  00 f0 29 e1 06 00 00 eb
1d 00 00 eb 8a 06 00 eb  15 0f 07 ee 9a 0f 07 ee
95 0f 07 ee 1e ff 2f e1  f0 ff ff ea 00 00 a0 e3
17 0f 08 ee 15 0f 07 ee  d5 0f 07 ee 9a 0f 07 ee
95 0f 07 ee 10 0f 11 ee  02 0a c0 e3 07 00 c0 e3
02 00 80 e3 02 0b 80 e3  01 0a 80 e3 10 0f 01 ee
0e 50 a0 e1 10 1f 10 ee  21 3a a0 e1 0f 30 03 e2
0f 40 01 e2 03 22 a0 e1  02 20 84 e1 0c 00 9f e5
07 00 c0 e3 00 d0 a0 e1  05 f0 a0 e1 64 06 00 ea
00 df 30 40 06 4b 1b 68  1b 68 1b 68 1b 68 bf f3
5f 8f 04 4a 03 f0 1f 03  52 f8 23 00 70 47 00 bf
90 92 30 40 68 6f 30 40  01 4b 03 60 70 47 00 bf
28 86 30 40 00 20 70 47  30 b5 47 4b 19 68 03 f1
80 63 a3 f5 3b 43 99 42  79 d0 44 4a 91 42 0c bf
4f f0 9e 32 4f f0 7c 32  bf f3 5f 8f 40 4b 18 68
00 68 d0 f8 e4 00 02 60  bf f3 5f 8f 18 68 22 f4
c0 24 00 68 d0 f8 e8 00  02 60 bf f3 5f 8f 18 68
00 68 d0 f8 ec 00 04 60  bf f3 5f 8f 18 68 00 68
d0 f8 f0 50 33 48 28 60  bf f3 5f 8f 1d 68 2d 68
d5 f8 f4 50 2a 60 bf f3  5f 8f 1d 68 2d 68 d5 f8
f8 50 2a 60 bf f3 5f 8f  1a 68 12 68 d2 f8 fc 20
14 60 bf f3 5f 8f 1a 68  12 68 d2 f8 00 21 10 60
1a 68 12 68 92 6c 12 68  bf f3 5f 8f 92 b2 92 b9
bf f3 5f 8f 1a 68 12 68  d0 6c 1f 4a 02 60 bf f3
5f 8f 18 68 00 68 00 6d  02 60 bf f3 5f 8f 18 68
00 68 40 6d 02 60 1a 68  12 68 d2 f8 84 21 12 68
bf f3 5f 8f 3a b9 bf f3  5f 8f 1a 68 13 48 12 68
d2 f8 84 21 10 60 12 4a  91 42 0b d8 bf f3 5f 8f
1b 68 10 4a 1b 68 d3 f8  88 31 1a 60 30 bd 4f f0
1c 32 89 e7 1a 68 12 68  d2 f8 88 21 12 68 bf f3
5f 8f 00 2a ea d0 f1 e7  00 bc 30 40 00 02 30 44
90 92 30 40 0f 8c 88 a0  0f 04 01 04 10 01 4d 1c
ff 00 60 44 00 40 08 99  08 b5 00 f0 50 fa 1f 4b
98 42 a3 f5 6f 03 a3 f2  93 43 31 d0 0a d8 1c 4a
90 42 19 d0 02 f5 80 12  01 32 90 42 17 d0 4f f0
ff 32 12 e0 17 4a 90 42  f9 d1 17 4a 12 68 bf f3
5f 8f 16 49 8a 42 1d d0  01 f1 00 51 a1 f5 1c 31
8a 42 19 d0 12 4a 00 e0  12 4a 1a 60 08 bd 0e 4a
12 68 bf f3 5f 8f 10 49  8a 42 05 d0 01 f1 80 51
8a 42 03 d0 0d 4a f0 e7  0d 4a ee e7 0d 4a ec e7
0d 4a ea e7 0d 4a e8 e7  0d 4a e6 e7 93 c0 1f 41
91 c0 0f 41 9a c0 2f

Re: [PATCH v2 5/5] rockchip: rockpro64: Build u-boot-rockchip-spi.bin

Hi Peter,

On 2023-05-17 21:14, Peter Robinson wrote:
> On Wed, May 17, 2023 at 7:41 PM Jonas Karlman  wrote:
>>
>> Enable CONFIG_ROCKCHIP_SPI_IMAGE to build u-boot-rockchip-spi.bin.
>> Define CONFIG_SYS_SPI_U_BOOT_OFFS to write u-boot.itb at the expected
> 
> None of the other rk33* devices enable this offset yet my Pinebook Pro
> works fine booting from SPI flash, what does this fix/enable/change
> over the defaults?

Most other RK3399 devices define the offset in the device tree, even for
the rockpro64. However, the CONFIG_SYS_SPI_U_BOOT_OFFS is used as the
fallback when device tree value is missing, and also as the offset used
when generating the u-boot-rockchip-spi.bin using binman.

puma-rk3399_defconfig is the only other RK3399 board that also generates
a u-boot-rockchip-spi.bin, has CONFIG_ROCKCHIP_SPI_IMAGE=y. That board
override the simple-bin-spi fit offset in rk3399-puma-haikou-u-boot.dtsi
instead of using the Kconfig option.

> 
>> offset. Enable CONFIG_LTO to reduce size of SPL so that the mkimage
>> output fit before the 0x6 offset in u-boot-rockchip-spi.bin.
> 
> The enabling of LTO seems like a separate change TBH, the changes seem
> to be independent and there's no mention of it in the subject.

Without LTO enabled the idbloader.img grows too large that it does not
fit before the u-boot.itb payload at 0x6 and bulding of
u-boot-rockchip-spi.bin fails the u-boot build.

In order to generate a valid u-boot-rockchip-spi.bin, LTO was required
to be enabled, there is also a short mention of it in the commit message.
The alternative would be to move the payload offset to e.g. 0x8 but
that felt like a too big and risky change.

Regards,
Jonas

> 
>>   => sf probe
>>   SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 
>> MiB
>>   => load mmc 1:1 1000 u-boot-rockchip-spi.bin
>>   1442304 bytes read in 27 ms (50.9 MiB/s)
>>   => sf update $fileaddr 0 $filesize
>>   device 0 offset 0x0, size 0x160200
>>   1421824 bytes written, 20480 bytes skipped in 9.501s, speed 155432 B/s
>>
>> Signed-off-by: Jonas Karlman 
>> Reviewed-by: Kever Yang 
>> ---
>> v2:
>> - Collect r-b tag
>>
>>  configs/rockpro64-rk3399_defconfig | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/configs/rockpro64-rk3399_defconfig 
>> b/configs/rockpro64-rk3399_defconfig
>> index 0ca2cecade25..f41c03067903 100644
>> --- a/configs/rockpro64-rk3399_defconfig
>> +++ b/configs/rockpro64-rk3399_defconfig
>> @@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3F8000
>>  CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
>>  CONFIG_DM_RESET=y
>>  CONFIG_ROCKCHIP_RK3399=y
>> +CONFIG_ROCKCHIP_SPI_IMAGE=y
>>  CONFIG_TARGET_ROCKPRO64_RK3399=y
>>  CONFIG_SPL_STACK=0x40
>>  CONFIG_DEBUG_UART_BASE=0xFF1A
>> @@ -20,6 +21,7 @@ CONFIG_SPL_SPI=y
>>  CONFIG_SYS_LOAD_ADDR=0x800800
>>  CONFIG_PCI=y
>>  CONFIG_DEBUG_UART=y
>> +CONFIG_LTO=y
>>  CONFIG_SPL_FIT_SIGNATURE=y
>>  CONFIG_BOOTSTAGE=y
>>  CONFIG_BOOTSTAGE_REPORT=y
>> @@ -37,6 +39,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
>>  CONFIG_SPL_STACK_R=y
>>  CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
>>  CONFIG_SPL_SPI_LOAD=y
>> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
>>  CONFIG_TPL=y
>>  CONFIG_CMD_BOOTZ=y
>>  CONFIG_CMD_GPT=y
>> --
>> 2.40.1
>>

Re: [PATCH v2 3/5] rockchip: rockpro64: Use SDMA to boost eMMC performance

Hi Peter,

On 2023-05-17 21:07, Peter Robinson wrote:
> On Wed, May 17, 2023 at 7:41 PM Jonas Karlman  wrote:
>>
>> Enable the use of SDMA mode to boost eMMC performance on RockPro64.
>> Also add missing flags to indicate the supported MMC modes.
>>
>> Using mmc read command to read 32 MiB data shows following improvement:
>>
>>   => time mmc read 1000 2000 1
>>
>> Before: time: 3.178 seconds
>> After: time: 0.402 seconds
>>
>> This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
>> any possible future issue with loading TF-A into DRAM/SRAM.
>>
>> Signed-off-by: Jonas Karlman 
>> Reviewed-by: Kever Yang 
>> ---
>> v2:
>> - Collect r-b tag
>>
>>  arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 5 +
>>  configs/rockpro64-rk3399_defconfig| 2 ++
>>  2 files changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi 
>> b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
>> index 32a83b2855ac..bd864d067018 100644
>> --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
>> +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
>> @@ -15,6 +15,11 @@
>> };
>>  };
>>
>> + {
>> +   cap-mmc-highspeed;
>> +   mmc-ddr-1_8v;
>> +};
> 
> Has this been submitted for the upstream Linux kernel DT? The
> u-boot.dtsi isn't meant to be a general dumping ground for things that
> should be going upstream. Does it work with the Linux kernel as well
> as those people that boot using firmware provided DT will get this as
> well.

It has not been submitted for upstream linux device tree yet. I have
patches pending for rk3399-rockpro64 and some rk35xx devices in my local
tree, hoping to have them submitted any day now.

This should work with linux, however linux should pick the hs200 mode
over ddr52 mode.

With hs200 mode Kconfig enabled in u-boot the above test cmd result
in ~0.2 seconds.

Regards,
Jonas

> 
> Peter
> 
>>   {
>> spi_flash: flash@0 {
>> bootph-all;
>> diff --git a/configs/rockpro64-rk3399_defconfig 
>> b/configs/rockpro64-rk3399_defconfig
>> index 2b89b1baba51..0ca2cecade25 100644
>> --- a/configs/rockpro64-rk3399_defconfig
>> +++ b/configs/rockpro64-rk3399_defconfig
>> @@ -20,6 +20,7 @@ CONFIG_SPL_SPI=y
>>  CONFIG_SYS_LOAD_ADDR=0x800800
>>  CONFIG_PCI=y
>>  CONFIG_DEBUG_UART=y
>> +CONFIG_SPL_FIT_SIGNATURE=y
>>  CONFIG_BOOTSTAGE=y
>>  CONFIG_BOOTSTAGE_REPORT=y
>>  CONFIG_USE_PREBOOT=y
>> @@ -63,6 +64,7 @@ CONFIG_ROCKCHIP_EFUSE=y
>>  CONFIG_MMC_DW=y
>>  CONFIG_MMC_DW_ROCKCHIP=y
>>  CONFIG_MMC_SDHCI=y
>> +CONFIG_MMC_SDHCI_SDMA=y
>>  CONFIG_MMC_SDHCI_ROCKCHIP=y
>>  CONFIG_SF_DEFAULT_BUS=1
>>  CONFIG_SPI_FLASH_GIGADEVICE=y
>> --
>> 2.40.1
>>

Re: [PATCH v2 0/5] rockchip: Fix eMMC performance regression

Hi Peter,
On 2023-05-17 21:05, Peter Robinson wrote:
> On Wed, May 17, 2023 at 7:40 PM Jonas Karlman  wrote:
>>
>> The eMMC performance on RK3399 was reduced sigificant by the
>> commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read
>> in a single command").
>>
>> That workaround should only have been applied to RK3568 and RK3588.
>> This series fixes that and also help boost eMMC performance on two
>> RK3399 boards even more by enabling use of SDMA.
> 
> Is there a reason to do this on just two devices?

DMA use can and should probably be enabled on other RK3399 devices,
these two where the only ones I could runtime test on.

Regards,
Jonas

> 
>> There is also an extra commit to help build a u-boot-rockchip-spi.bin
>> image that can be used for SPI flash boot on RockPro64.
>>
>> Changes in v2:
>> - Rebase on top of defconfig and spi v2 series
>> - Collect r-b and t-b tags
>>
>> Jonas Karlman (5):
>>   mmc: rockchip_sdhci: Skip blocks read workaround on RK3399
>>   mmc: rockchip_sdhci: Disable DMA mode using a device tree property
>>   rockchip: rockpro64: Use SDMA to boost eMMC performance
>>   rockchip: rock-pi-4: Use SDMA to boost eMMC performance
>>   rockchip: rockpro64: Build u-boot-rockchip-spi.bin
>>
>>  arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi |  6 ++
>>  arch/arm/dts/rk3399-rockpro64-u-boot.dtsi |  5 +
>>  arch/arm/dts/rk3399-u-boot.dtsi   |  1 +
>>  arch/arm/dts/rk3588s-u-boot.dtsi  |  1 +
>>  configs/rock-pi-4-rk3399_defconfig|  2 ++
>>  configs/rock5b-rk3588_defconfig   |  1 -
>>  configs/rockpro64-rk3399_defconfig|  5 +
>>  drivers/mmc/rockchip_sdhci.c  | 12 +++-
>>  8 files changed, 31 insertions(+), 2 deletions(-)
>>
>> --
>> 2.40.1
>>

Re: [PATCH v2 5/5] rockchip: rockpro64: Build u-boot-rockchip-spi.bin

2023-05-17 Thread Peter Robinson

On Wed, May 17, 2023 at 7:41 PM Jonas Karlman  wrote:
>
> Enable CONFIG_ROCKCHIP_SPI_IMAGE to build u-boot-rockchip-spi.bin.
> Define CONFIG_SYS_SPI_U_BOOT_OFFS to write u-boot.itb at the expected

None of the other rk33* devices enable this offset yet my Pinebook Pro
works fine booting from SPI flash, what does this fix/enable/change
over the defaults?

> offset. Enable CONFIG_LTO to reduce size of SPL so that the mkimage
> output fit before the 0x6 offset in u-boot-rockchip-spi.bin.

The enabling of LTO seems like a separate change TBH, the changes seem
to be independent and there's no mention of it in the subject.

>   => sf probe
>   SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 
> MiB
>   => load mmc 1:1 1000 u-boot-rockchip-spi.bin
>   1442304 bytes read in 27 ms (50.9 MiB/s)
>   => sf update $fileaddr 0 $filesize
>   device 0 offset 0x0, size 0x160200
>   1421824 bytes written, 20480 bytes skipped in 9.501s, speed 155432 B/s
>
> Signed-off-by: Jonas Karlman 
> Reviewed-by: Kever Yang 
> ---
> v2:
> - Collect r-b tag
>
>  configs/rockpro64-rk3399_defconfig | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/configs/rockpro64-rk3399_defconfig 
> b/configs/rockpro64-rk3399_defconfig
> index 0ca2cecade25..f41c03067903 100644
> --- a/configs/rockpro64-rk3399_defconfig
> +++ b/configs/rockpro64-rk3399_defconfig
> @@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3F8000
>  CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
>  CONFIG_DM_RESET=y
>  CONFIG_ROCKCHIP_RK3399=y
> +CONFIG_ROCKCHIP_SPI_IMAGE=y
>  CONFIG_TARGET_ROCKPRO64_RK3399=y
>  CONFIG_SPL_STACK=0x40
>  CONFIG_DEBUG_UART_BASE=0xFF1A
> @@ -20,6 +21,7 @@ CONFIG_SPL_SPI=y
>  CONFIG_SYS_LOAD_ADDR=0x800800
>  CONFIG_PCI=y
>  CONFIG_DEBUG_UART=y
> +CONFIG_LTO=y
>  CONFIG_SPL_FIT_SIGNATURE=y
>  CONFIG_BOOTSTAGE=y
>  CONFIG_BOOTSTAGE_REPORT=y
> @@ -37,6 +39,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
>  CONFIG_SPL_STACK_R=y
>  CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
>  CONFIG_SPL_SPI_LOAD=y
> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
>  CONFIG_TPL=y
>  CONFIG_CMD_BOOTZ=y
>  CONFIG_CMD_GPT=y
> --
> 2.40.1
>

Re: [PATCH v2 3/5] rockchip: rockpro64: Use SDMA to boost eMMC performance

2023-05-17 Thread Peter Robinson

On Wed, May 17, 2023 at 7:41 PM Jonas Karlman  wrote:
>
> Enable the use of SDMA mode to boost eMMC performance on RockPro64.
> Also add missing flags to indicate the supported MMC modes.
>
> Using mmc read command to read 32 MiB data shows following improvement:
>
>   => time mmc read 1000 2000 1
>
> Before: time: 3.178 seconds
> After: time: 0.402 seconds
>
> This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
> any possible future issue with loading TF-A into DRAM/SRAM.
>
> Signed-off-by: Jonas Karlman 
> Reviewed-by: Kever Yang 
> ---
> v2:
> - Collect r-b tag
>
>  arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 5 +
>  configs/rockpro64-rk3399_defconfig| 2 ++
>  2 files changed, 7 insertions(+)
>
> diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi 
> b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
> index 32a83b2855ac..bd864d067018 100644
> --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
> @@ -15,6 +15,11 @@
> };
>  };
>
> + {
> +   cap-mmc-highspeed;
> +   mmc-ddr-1_8v;
> +};

Has this been submitted for the upstream Linux kernel DT? The
u-boot.dtsi isn't meant to be a general dumping ground for things that
should be going upstream. Does it work with the Linux kernel as well
as those people that boot using firmware provided DT will get this as
well.

Peter

>   {
> spi_flash: flash@0 {
> bootph-all;
> diff --git a/configs/rockpro64-rk3399_defconfig 
> b/configs/rockpro64-rk3399_defconfig
> index 2b89b1baba51..0ca2cecade25 100644
> --- a/configs/rockpro64-rk3399_defconfig
> +++ b/configs/rockpro64-rk3399_defconfig
> @@ -20,6 +20,7 @@ CONFIG_SPL_SPI=y
>  CONFIG_SYS_LOAD_ADDR=0x800800
>  CONFIG_PCI=y
>  CONFIG_DEBUG_UART=y
> +CONFIG_SPL_FIT_SIGNATURE=y
>  CONFIG_BOOTSTAGE=y
>  CONFIG_BOOTSTAGE_REPORT=y
>  CONFIG_USE_PREBOOT=y
> @@ -63,6 +64,7 @@ CONFIG_ROCKCHIP_EFUSE=y
>  CONFIG_MMC_DW=y
>  CONFIG_MMC_DW_ROCKCHIP=y
>  CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y
>  CONFIG_MMC_SDHCI_ROCKCHIP=y
>  CONFIG_SF_DEFAULT_BUS=1
>  CONFIG_SPI_FLASH_GIGADEVICE=y
> --
> 2.40.1
>

Re: [PATCH v2 0/5] rockchip: Fix eMMC performance regression

2023-05-17 Thread Peter Robinson

On Wed, May 17, 2023 at 7:40 PM Jonas Karlman  wrote:
>
> The eMMC performance on RK3399 was reduced sigificant by the
> commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read
> in a single command").
>
> That workaround should only have been applied to RK3568 and RK3588.
> This series fixes that and also help boost eMMC performance on two
> RK3399 boards even more by enabling use of SDMA.

Is there a reason to do this on just two devices?

> There is also an extra commit to help build a u-boot-rockchip-spi.bin
> image that can be used for SPI flash boot on RockPro64.
>
> Changes in v2:
> - Rebase on top of defconfig and spi v2 series
> - Collect r-b and t-b tags
>
> Jonas Karlman (5):
>   mmc: rockchip_sdhci: Skip blocks read workaround on RK3399
>   mmc: rockchip_sdhci: Disable DMA mode using a device tree property
>   rockchip: rockpro64: Use SDMA to boost eMMC performance
>   rockchip: rock-pi-4: Use SDMA to boost eMMC performance
>   rockchip: rockpro64: Build u-boot-rockchip-spi.bin
>
>  arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi |  6 ++
>  arch/arm/dts/rk3399-rockpro64-u-boot.dtsi |  5 +
>  arch/arm/dts/rk3399-u-boot.dtsi   |  1 +
>  arch/arm/dts/rk3588s-u-boot.dtsi  |  1 +
>  configs/rock-pi-4-rk3399_defconfig|  2 ++
>  configs/rock5b-rk3588_defconfig   |  1 -
>  configs/rockpro64-rk3399_defconfig|  5 +
>  drivers/mmc/rockchip_sdhci.c  | 12 +++-
>  8 files changed, 31 insertions(+), 2 deletions(-)
>
> --
> 2.40.1
>

Re: Pull Request / Patch: Enable Usage of ECC with DDR on AM654x

2023-05-17 Thread Roytburd, Benjamin

Enabling ECC has not given me any problems in running my applications, I have 
even performed poison tests with SECDED that have been effective. No problems 
besides the increased boot time due to priming are occurring.

But agreed, for a patch we should definitely use DMA as opposed to a for loop. 
I have not implemented DMA yet, but when I do I wil formally submit a patch 
with it.

From: Nishanth Menon 
Sent: Wednesday, May 17, 2023 11:30 AM
To: Roytburd, Benjamin 
Cc: Tom Rini ; u-boot@lists.denx.de 
Subject: Re: Pull Request / Patch: Enable Usage of ECC with DDR on AM654x

On 14:23-20230505, Roytburd, Benjamin wrote:
> Nishanth,
>

Gentle reminder: Please do not top post  - email etiquette in upstream mailing
as well as please do not use flowed formatting. See [1] (I use neomutt
personally with 70 char line break)

> Agreed, this is very expensive for boot time, I could probably add a comment
> to address this. But I believe it is better to have this option than not, as
> I struggled to figure out that I even needed to prime ECC when I enabled it.
>
> What is the strategy for TODOs with U-boot? DMA would probably be the best
> option here instead of memset / for loop, but I do not have that implemented
> yet. I could submit it in a future patch.

Remember what I mentioned in my response: there are quite a few other
folks also using the SoC support and evm. They would rather not want
to see the increase in boot time if we merge such a change. I don't see
a reasonable alternative without using DMA to prime effectively.

Also, is blindly enabling ECC across the DDR effective or creating
other problems? Access latencies are increased (since incoming and
outgoing bursts need to be checked against checksum) or should we
scheme something with a range?

[...]

[1] 
https://urldefense.com/v3/__https://www.kernel.org/doc/html/v6.3/process/email-clients.html__;!!HXCxUKc!wabHWUgkSClHiAAP16BJSW3kCDVa_Vt0h8v97UjrkTHHYEiIMNsggLpyACyvo0XtCa-GuQ$
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 
849D 1736 249D

[PATCH v2 4/5] rockchip: rock-pi-4: Use SDMA to boost eMMC performance

Enable the use of SDMA mode to boost eMMC performance on ROCK Pi 4.
Also add missing flags to indicate the supported MMC modes.

Using mmc read command to read 32 MiB data shows following improvement:

  => time mmc read 1000 2000 1

Before: time: 3.178 seconds
After: time: 0.402 seconds

This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Rebase to fix conflict with CONFIG_DEFAULT_FDT_FILE
- Collect r-b tag

 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 ++
 configs/rock-pi-4-rk3399_defconfig| 2 ++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index c17e769f649f..60122f3bcd6c 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -12,6 +12,12 @@
};
 };
 
+ {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+};
+
 _log {
regulator-init-microvolt = <95>;
 };
diff --git a/configs/rock-pi-4-rk3399_defconfig 
b/configs/rock-pi-4-rk3399_defconfig
index cd93093cd2d3..4b984adc6ef8 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -19,6 +19,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
@@ -56,6 +57,7 @@ CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
-- 
2.40.1

[PATCH v2 5/5] rockchip: rockpro64: Build u-boot-rockchip-spi.bin

Enable CONFIG_ROCKCHIP_SPI_IMAGE to build u-boot-rockchip-spi.bin.
Define CONFIG_SYS_SPI_U_BOOT_OFFS to write u-boot.itb at the expected
offset. Enable CONFIG_LTO to reduce size of SPL so that the mkimage
output fit before the 0x6 offset in u-boot-rockchip-spi.bin.

  => sf probe
  SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
  => load mmc 1:1 1000 u-boot-rockchip-spi.bin
  1442304 bytes read in 27 ms (50.9 MiB/s)
  => sf update $fileaddr 0 $filesize
  device 0 offset 0x0, size 0x160200
  1421824 bytes written, 20480 bytes skipped in 9.501s, speed 155432 B/s

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Collect r-b tag

 configs/rockpro64-rk3399_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/rockpro64-rk3399_defconfig 
b/configs/rockpro64-rk3399_defconfig
index 0ca2cecade25..f41c03067903 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_TARGET_ROCKPRO64_RK3399=y
 CONFIG_SPL_STACK=0x40
 CONFIG_DEBUG_UART_BASE=0xFF1A
@@ -20,6 +21,7 @@ CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
+CONFIG_LTO=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
@@ -37,6 +39,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
-- 
2.40.1

[PATCH v2 3/5] rockchip: rockpro64: Use SDMA to boost eMMC performance

Enable the use of SDMA mode to boost eMMC performance on RockPro64.
Also add missing flags to indicate the supported MMC modes.

Using mmc read command to read 32 MiB data shows following improvement:

  => time mmc read 1000 2000 1

Before: time: 3.178 seconds
After: time: 0.402 seconds

This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Collect r-b tag

 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 5 +
 configs/rockpro64-rk3399_defconfig| 2 ++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi 
b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
index 32a83b2855ac..bd864d067018 100644
--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -15,6 +15,11 @@
};
 };
 
+ {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+};
+
  {
spi_flash: flash@0 {
bootph-all;
diff --git a/configs/rockpro64-rk3399_defconfig 
b/configs/rockpro64-rk3399_defconfig
index 2b89b1baba51..0ca2cecade25 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -20,6 +20,7 @@ CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_USE_PREBOOT=y
@@ -63,6 +64,7 @@ CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_SPI_FLASH_GIGADEVICE=y
-- 
2.40.1

[PATCH v2 2/5] mmc: rockchip_sdhci: Disable DMA mode using a device tree property

Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:

  ## Checking hash(es) for Image atf-2 ... sha256 error!
  Bad hash value for 'hash' hash node in 'atf-2' image node
  spl_load_simple_fit: can't load image loadables index 1 (ret = -1)
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

Add a device tree property, u-boot,spl-fifo-mode, to control when the
rockchip_sdhci driver should disable the use of DMA and fallback on PIO
mode. Same device tree property is used by the rockchip_dw_mmc driver.

In commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") the DMA mode was disabled using a CONFIG
option on RK3588. Revert that and instead disable DMA using the device
tree property for all RK3588 boards, also apply similar workaround for
all RK3399 boards.

Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a 
single command")
Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
Tested-by: Quentin Schulz  # RK3399 Puma, RK3588 Tiger
---
v2:
- Rebase on top of defconfig and spi v2 series
- Collect r-b and t-b tags

 arch/arm/dts/rk3399-u-boot.dtsi  | 1 +
 arch/arm/dts/rk3588s-u-boot.dtsi | 1 +
 configs/rock5b-rk3588_defconfig  | 1 -
 drivers/mmc/rockchip_sdhci.c | 8 
 4 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index e677ae678dab..3423b882c437 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -120,6 +120,7 @@
  {
max-frequency = <2>;
bootph-all;
+   u-boot,spl-fifo-mode;
 };
 
  {
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 64c309046587..c703e41802b6 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -239,6 +239,7 @@
 
  {
bootph-pre-ram;
+   u-boot,spl-fifo-mode;
 };
 
  {
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 9d0b55c01ac9..c1155c20efa8 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -66,7 +66,6 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
-# CONFIG_SPL_MMC_SDHCI_SDMA is not set
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_XTX=y
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 8e4a158049a9..285332d9f4fd 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -589,6 +589,14 @@ static int rockchip_sdhci_probe(struct udevice *dev)
if (ret)
return ret;
 
+   /*
+* Disable use of DMA and force use of PIO mode in SPL to fix an issue
+* where loading part of TF-A into SRAM using DMA silently fails.
+*/
+   if (IS_ENABLED(CONFIG_SPL_BUILD) &&
+   dev_read_bool(dev, "u-boot,spl-fifo-mode"))
+   host->flags &= ~USE_DMA;
+
/*
 * Reading more than 4 blocks with a single CMD18 command in PIO mode
 * triggers Data End Bit Error on RK3568 and RK3588. Limit to reading
-- 
2.40.1

[PATCH v2 1/5] mmc: rockchip_sdhci: Skip blocks read workaround on RK3399

The workaround to limit number of blocks to read in a single command
should only be applied to RK3568 and RK3588. Change to be more strict
when to apply the workaround.

Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a 
single command")
Suggested-by: Simon Glass 
Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
Tested-by: Quentin Schulz  # RK3399 Puma, RK3588 Tiger
---
v2:
- Collect r-b and t-b tags

 drivers/mmc/rockchip_sdhci.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 4f110976f4e8..8e4a158049a9 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -594,7 +594,9 @@ static int rockchip_sdhci_probe(struct udevice *dev)
 * triggers Data End Bit Error on RK3568 and RK3588. Limit to reading
 * max 4 blocks in one command when using PIO mode.
 */
-   if (!(host->flags & USE_DMA))
+   if (!(host->flags & USE_DMA) &&
+   (device_is_compatible(dev, "rockchip,rk3568-dwcmshc") ||
+device_is_compatible(dev, "rockchip,rk3588-dwcmshc")))
cfg->b_max = 4;
 
return sdhci_probe(dev);
-- 
2.40.1

[PATCH v2 0/5] rockchip: Fix eMMC performance regression

The eMMC performance on RK3399 was reduced sigificant by the
commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read
in a single command").

That workaround should only have been applied to RK3568 and RK3588.
This series fixes that and also help boost eMMC performance on two
RK3399 boards even more by enabling use of SDMA.

There is also an extra commit to help build a u-boot-rockchip-spi.bin
image that can be used for SPI flash boot on RockPro64.

Changes in v2:
- Rebase on top of defconfig and spi v2 series
- Collect r-b and t-b tags

Jonas Karlman (5):
  mmc: rockchip_sdhci: Skip blocks read workaround on RK3399
  mmc: rockchip_sdhci: Disable DMA mode using a device tree property
  rockchip: rockpro64: Use SDMA to boost eMMC performance
  rockchip: rock-pi-4: Use SDMA to boost eMMC performance
  rockchip: rockpro64: Build u-boot-rockchip-spi.bin

 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi |  6 ++
 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi |  5 +
 arch/arm/dts/rk3399-u-boot.dtsi   |  1 +
 arch/arm/dts/rk3588s-u-boot.dtsi  |  1 +
 configs/rock-pi-4-rk3399_defconfig|  2 ++
 configs/rock5b-rk3588_defconfig   |  1 -
 configs/rockpro64-rk3399_defconfig|  5 +
 drivers/mmc/rockchip_sdhci.c  | 12 +++-
 8 files changed, 31 insertions(+), 2 deletions(-)

-- 
2.40.1

Re: Pull Request / Patch: Enable Usage of ECC with DDR on AM654x

2023-05-17 Thread Nishanth Menon

On 14:23-20230505, Roytburd, Benjamin wrote:
> Nishanth,
> 

Gentle reminder: Please do not top post  - email etiquette in upstream mailing
as well as please do not use flowed formatting. See [1] (I use neomutt
personally with 70 char line break)

> Agreed, this is very expensive for boot time, I could probably add a comment
> to address this. But I believe it is better to have this option than not, as
> I struggled to figure out that I even needed to prime ECC when I enabled it.
> 
> What is the strategy for TODOs with U-boot? DMA would probably be the best
> option here instead of memset / for loop, but I do not have that implemented
> yet. I could submit it in a future patch.

Remember what I mentioned in my response: there are quite a few other
folks also using the SoC support and evm. They would rather not want
to see the increase in boot time if we merge such a change. I don't see
a reasonable alternative without using DMA to prime effectively.

Also, is blindly enabling ECC across the DDR effective or creating
other problems? Access latencies are increased (since incoming and
outgoing bursts need to be checked against checksum) or should we
scheme something with a range?

[...]

[1] https://www.kernel.org/doc/html/v6.3/process/email-clients.html
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 
849D 1736 249D

[PATCH v2 13/13] rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash

Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Add and use BROM_BOOTSOURCE_SPINOR_RK3588 enum value
- Rebased to resolve conflicts
- Collect r-b tag

 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi  | 24 
 arch/arm/dts/rk3588s-u-boot.dtsi | 20 
 arch/arm/include/asm/arch-rockchip/bootrom.h |  1 +
 arch/arm/mach-rockchip/rk3588/rk3588.c   |  1 +
 configs/rock5b-rk3588_defconfig  | 10 
 5 files changed, 56 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index db342e6a9391..1cd8a57a6fa6 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -11,6 +11,7 @@
 / {
aliases {
mmc1 = 
+   spi0 = 
};
 
chosen {
@@ -54,6 +55,10 @@
bootph-all;
 };
 
+_pins {
+   bootph-all;
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins _reset_h>;
@@ -123,6 +128,25 @@
pinctrl-0 = <_bus8 _clk _cmd _data_strobe 
_rstnout>;
 };
 
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
 _xfer {
bootph-all;
 };
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 2c4cad82b38f..64c309046587 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -165,6 +165,15 @@
};
};
 
+   sfc: spi@fe2b {
+   compatible = "rockchip,sfc";
+   reg = <0x0 0xfe2b 0x0 0x4000>;
+   interrupts = ;
+   clocks = < SCLK_SFC>, < HCLK_SFC>;
+   clock-names = "clk_sfc", "hclk_sfc";
+   status = "disabled";
+   };
+
otp: nvmem@fecc {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc 0x0 0x400>;
@@ -241,3 +250,14 @@
  {
bootph-pre-ram;
 };
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+ {
+   simple-bin-spi {
+   mkimage {
+   args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+   offset = <0x8000>;
+   };
+   };
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h 
b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 4276a0f6811a..7dab18fbc3fb 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -48,6 +48,7 @@ enum {
BROM_BOOTSOURCE_SPINOR = 3,
BROM_BOOTSOURCE_SPINAND = 4,
BROM_BOOTSOURCE_SD = 5,
+   BROM_BOOTSOURCE_SPINOR_RK3588 = 6,
BROM_BOOTSOURCE_USB = 10,
BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
 };
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c 
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 18e67b5ca9b2..b1f535fad505 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e",
[BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe2c",
+   [BROM_BOOTSOURCE_SPINOR_RK3588] = "/spi@fe2b/flash@0",
 };
 
 static struct mm_region rk3588_mem_map[] = {
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 5fe3a3542e11..9d0b55c01ac9 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_ROCK5B_RK3588=y
 CONFIG_SPL_STACK=0x40
 CONFIG_DEBUG_UART_BASE=0xFEB5
 CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
@@ -36,6 +41,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -61,6 +68,8 @@ CONFIG_MMC_SDHCI=y

[PATCH v2 12/13] rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and sdhci

Enable pinctrl for sdhci in SPL to support loading of FIT image from SD
and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Reorder nodes alphabetically
- Rebased to resolve conflicts
- Collect r-b tag

 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 28 +
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 406303920d95..db342e6a9391 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -34,6 +34,26 @@
status = "okay";
 };
 
+_bus8 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_data_strobe {
+   bootph-all;
+};
+
+_rstnout {
+   bootph-all;
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins _reset_h>;
@@ -62,6 +82,10 @@
};
 };
 
+_pull_none {
+   bootph-all;
+};
+
 _pull_up_drv_level_2 {
bootph-all;
 };
@@ -99,6 +123,10 @@
pinctrl-0 = <_bus8 _clk _cmd _data_strobe 
_rstnout>;
 };
 
+_xfer {
+   bootph-all;
+};
+
 _host0_ehci {
companion = <_host0_ohci>;
phys = <_host>;
-- 
2.40.1

[PATCH v2 10/13] rockchip: rk3588-evb: Update defconfig

Update defconfig for rk3588-evb with new defaults.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config options to include useful gpio and regulator cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Remove CONFIG_DEBUG_UART_ANNOUNCE=y to remove debug messages.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Drop change to disable CONFIG_SPL_MMC_SDHCI_SDMA,
  fixed in "rockchip: Fix eMMC performance regression" series
- Collect r-b tag

 configs/evb-rk3588_defconfig | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 8760671a1772..d5f1c4b9ebc7 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -21,12 +21,13 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -35,14 +36,15 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -62,6 +64,6 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_ERRNO_STR=y
-- 
2.40.1

[PATCH v2 11/13] rockchip: rk3588-rock-5b: Update defconfig

Update defconfig for rk3588-rock-5b with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Rebased to resolve conflicts
- Collect r-b tag

 configs/rock5b-rk3588_defconfig | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 6cfd161b64f4..5fe3a3542e11 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
 CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_ROCK5B_RK3588=y
@@ -30,7 +28,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -39,6 +37,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
@@ -49,7 +48,6 @@ CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -74,6 +72,7 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
-- 
2.40.1

[PATCH v2 09/13] rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch Kconfig

Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful
across RK3588 platform. Select them from arch Kconfig.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Rsync using moveconfig.py
- Rebased to resolve conflicts
- Collect r-b tag

 arch/arm/mach-rockchip/Kconfig| 2 ++
 configs/evb-rk3588_defconfig  | 1 -
 configs/neu6a-io-rk3588_defconfig | 1 -
 configs/rock5b-rk3588_defconfig   | 4 +---
 4 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 327779a79818..9d6d20bf8ed6 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -311,6 +311,8 @@ config ROCKCHIP_RK3588
select REGMAP
select SYSCON
select BOARD_LATE_INIT
+   select DM_REGULATOR_FIXED
+   select DM_RESET
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
imply ROCKCHIP_COMMON_BOARD
imply OF_LIBFDT_OVERLAY
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 7911cc7c0b77..8760671a1772 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -9,7 +9,6 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
-CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/neu6a-io-rk3588_defconfig 
b/configs/neu6a-io-rk3588_defconfig
index fb1ce4c1746f..09729a0ea429 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -9,7 +9,6 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
-CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index c35dd451032e..6cfd161b64f4 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -9,7 +9,6 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
-CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
@@ -21,6 +20,7 @@ CONFIG_SPL_STACK=0x40
 CONFIG_DEBUG_UART_BASE=0xFEB5
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -65,13 +65,11 @@ CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
-- 
2.40.1

[PATCH v2 07/13] rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPL

Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Use bootph-all in pinctrl nodes
- Reorder nodes alphabetically
- Collect r-b tag

 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 52 +
 configs/rock-3a-rk3568_defconfig|  3 +-
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index c7855135906f..8cccd7e22659 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -12,6 +12,54 @@
};
 };
 
+_bus8 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_datastrobe {
+   bootph-all;
+};
+
+ {
+   bootph-all;
+};
+
+_pull_none {
+   bootph-all;
+};
+
+_pull_up_drv_level_2 {
+   bootph-all;
+};
+
+_pull_up {
+   bootph-all;
+};
+
+_bus4 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_det {
+   bootph-all;
+};
+
  {
cap-mmc-highspeed;
mmc-ddr-1_8v;
@@ -28,6 +76,10 @@
status = "disabled";
 };
 
+_xfer {
+   bootph-all;
+};
+
  {
clock-frequency = <2400>;
bootph-all;
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 5126feb6b11d..2e556dc2c1a2 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -63,6 +63,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
-- 
2.40.1

[PATCH v2 08/13] rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash

Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 3 Model A.

Unlike prior generation SoCs the BootRom in RK3568 can read all data and
look for idbloader at 0x8000, same as on SD and eMMC.

Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x6.

  => sf probe
  SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 
MiB

  => load mmc 1:1 1000 u-boot-rockchip-spi.bin
  1384448 bytes read in 119 ms (11.1 MiB/s)

  => sf update $fileaddr 0 $filesize
  device 0 offset 0x0, size 0x152000
  1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Reorder nodes alphabetically
- Collect r-b tag

 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 25 +
 arch/arm/dts/rk356x-u-boot.dtsi | 11 +++
 configs/rock-3a-rk3568_defconfig| 10 ++
 3 files changed, 46 insertions(+)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 8cccd7e22659..bbf54f888fa0 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -7,6 +7,10 @@
 #include "rk356x-u-boot.dtsi"
 
 / {
+   aliases {
+   spi0 = 
+   };
+
chosen {
stdout-path = 
};
@@ -28,6 +32,10 @@
bootph-all;
 };
 
+_pins {
+   bootph-all;
+};
+
  {
bootph-all;
 };
@@ -68,6 +76,23 @@
mmc-hs400-enhanced-strobe;
 };
 
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
  {
status = "disabled";
 };
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index a1c2d03c52f0..c340c2bba6ff 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -68,3 +68,14 @@
bootph-pre-ram;
status = "okay";
 };
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+ {
+   simple-bin-spi {
+   mkimage {
+   args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+   offset = <0x8000>;
+   };
+   };
+};
+#endif
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 2e556dc2c1a2..64864a300153 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_EVB_RK3568=y
 CONFIG_SPL_STACK=0x40
 CONFIG_DEBUG_UART_BASE=0xFE66
 CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
@@ -34,6 +39,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -59,6 +66,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -72,6 +81,7 @@ CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.40.1

[PATCH v2 06/13] rockchip: rk3568-rock-3a: Update defconfig

Update defconfig for rk3568-rock-3a with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Remove the CONFIG_SPL_PMIC_RK8XX=y option, the pmic is not used in SPL.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Collect r-b tag

 configs/rock-3a-rk3568_defconfig | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index f0db15baa30e..5126feb6b11d 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
 CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_EVB_RK3568=y
@@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -36,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -65,7 +65,6 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
-- 
2.40.1

[PATCH v2 05/13] rockchip: rk3568-evb: Update defconfig

Update defconfig for rk3568-evb with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config options to include useful gpio, i2c, pmic and regulator cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Add config options to enable support for the RK809 PMIC.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Collect r-b tag

 configs/evb-rk3568_defconfig | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index c929bac509c0..0b4fc52e263d 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
 CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_EVB_RK3568=y
@@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -36,13 +35,17 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -57,7 +60,9 @@ CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
-- 
2.40.1

[PATCH v2 04/13] rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL

Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Use bootph-all in pinctrl nodes
- Reorder nodes alphabetically
- Collect r-b tag

 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 56 
 configs/radxa-cm3-io-rk3566_defconfig|  3 +-
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index a8c31fecafd8..f91740c1c0c8 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -11,11 +11,67 @@
};
 };
 
+_bus8 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_datastrobe {
+   bootph-all;
+};
+
+ {
+   bootph-all;
+};
+
+_pull_none {
+   bootph-all;
+};
+
+_pull_up_drv_level_2 {
+   bootph-all;
+};
+
+_pull_up {
+   bootph-all;
+};
+
+_bus4 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_det {
+   bootph-all;
+};
+
+_pwren {
+   bootph-all;
+};
+
  {
cap-mmc-highspeed;
mmc-ddr-1_8v;
 };
 
+_xfer {
+   bootph-all;
+};
+
  {
clock-frequency = <2400>;
bootph-all;
diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index dfaacbc8839e..dd1dd36a59b7 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -63,6 +63,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
-- 
2.40.1

[PATCH v2 03/13] rockchip: rk3566-radxa-cm3-io: Update defconfig

Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
missing supported mmc modes to sdhci node.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Collect r-b tag

 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 5 +
 configs/radxa-cm3-io-rk3566_defconfig| 9 +
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index d183e935754d..a8c31fecafd8 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -11,6 +11,11 @@
};
 };
 
+ {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+};
+
  {
clock-frequency = <2400>;
bootph-all;
diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index 1df9cab79d51..dfaacbc8839e 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io"
 CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_EVB_RK3568=y
@@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -36,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -70,6 +70,7 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.40.1

[PATCH v2 01/13] spi: rockchip_sfc: Use linux rockchip,sfc-no-dma prop

Use the same prop as linux to control the use of fifo or dma mode. Also
add a u-boot,spl-sfc-no-dma prop to control the same in SPL.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Use IS_ENABLED(CONFIG_SPL_BUILD) instead of ifdef
- Collect r-b tag

 drivers/spi/rockchip_sfc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 851a6482985b..596c22aa0108 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -227,10 +227,10 @@ static int rockchip_sfc_ofdata_to_platdata(struct udevice 
*bus)
struct rockchip_sfc *sfc = dev_get_plat(bus);
 
sfc->regbase = dev_read_addr_ptr(bus);
-   if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
-   sfc->use_dma = false;
-   else
-   sfc->use_dma = true;
+   sfc->use_dma = !dev_read_bool(bus, "rockchip,sfc-no-dma");
+
+   if (IS_ENABLED(CONFIG_SPL_BUILD) && sfc->use_dma)
+   sfc->use_dma = !dev_read_bool(bus, "u-boot,spl-sfc-no-dma");
 
 #if CONFIG_IS_ENABLED(CLK)
int ret;
-- 
2.40.1

[PATCH v2 00/13] rockchip: rk35xx: Update defconfigs and enable boot from SPI NOR flash

This series sync some defconfig options across the different rk35xx
boards and enables boot from SPI NOR flash on rk3568-rock-3a and
rk3588-rock-5b.

Patch 1 fixes use of sfc-no-dma prop in rockchip sfc driver.
Patch 2-7 updates defconfig for rk356x boards.
Patch 8 enables boot from SPI NOR flash on rk3568-rock-3a.
Patch 9-12 updates defconfig for rk3588 boards.
Patch 13 enables boot from SPI NOR flash on rk3588-rock-5b.

Changes in v2:
- Use IS_ENABLED(CONFIG_SPL_BUILD) instead of ifdef
- Use bootph-all in pinctrl nodes
- Reorder nodes alphabetically
- Rsync rock5b-rk3588_defconfig using moveconfig.py
- Drop change to disable CONFIG_SPL_MMC_SDHCI_SDMA,
  fixed in "rockchip: Fix eMMC performance regression" series
- Add and use BROM_BOOTSOURCE_SPINOR_RK3588 enum value
- Rebased on custodians/u-boot-rockchip master branch,
  excluding patches picked from this series
- Drop patch that reverts addition of regulator-boot-on props
- Collect r-b tags

This series can also be found at [1].

[1] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-defconfig-spi-v2


Jonas Karlman (13):
  spi: rockchip_sfc: Use linux rockchip,sfc-no-dma prop
  rockchip: rk356x-u-boot: Add xin24m clock node to SPL
  rockchip: rk3566-radxa-cm3-io: Update defconfig
  rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL
  rockchip: rk3568-evb: Update defconfig
  rockchip: rk3568-rock-3a: Update defconfig
  rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPL
  rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash
  rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch
Kconfig
  rockchip: rk3588-evb: Update defconfig
  rockchip: rk3588-rock-5b: Update defconfig
  rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and
sdhci
  rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash

 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 61 
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi  | 77 
 arch/arm/dts/rk356x-u-boot.dtsi  | 16 
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi  | 52 +
 arch/arm/dts/rk3588s-u-boot.dtsi | 20 +
 arch/arm/mach-rockchip/Kconfig   |  2 +
 arch/arm/mach-rockchip/rk3588/rk3588.c   |  1 +
 configs/evb-rk3568_defconfig | 15 ++--
 configs/evb-rk3588_defconfig |  9 ++-
 configs/neu6a-io-rk3588_defconfig|  1 -
 configs/radxa-cm3-io-rk3566_defconfig| 10 ++-
 configs/rock-3a-rk3568_defconfig | 20 +++--
 configs/rock5b-rk3588_defconfig  | 19 +++--
 drivers/spi/rockchip_sfc.c   | 10 ++-
 14 files changed, 284 insertions(+), 29 deletions(-)

-- 
2.40.1

[PATCH v2 02/13] rockchip: rk356x-u-boot: Add xin24m clock node to SPL

Add bootph-all prop to xin24m clock node, it is referenced by cru node.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 
---
v2:
- Collect r-b tag

 arch/arm/dts/rk356x-u-boot.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 0a764ce5119c..a1c2d03c52f0 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -34,6 +34,11 @@
};
 };
 
+ {
+   bootph-all;
+   status = "okay";
+};
+
  {
bootph-all;
status = "okay";
-- 
2.40.1

Re: [External] : Re: [PATCH] usb: kbd: dwc2: Increase wait for dwc2 controller reset by 125us

2023-05-17 Thread Filip Žaludek





Hi Marek,

On 5/15/23 20:56, Filip Žaludek wrote:



Hi Marek,


On 5/15/23 20:09, Marek Vasut wrote:

On 5/15/23 16:53, Filip Zaludek wrote:

Two following performance patches applied together occasionally harm usb 
keyboard on RPi3.

'dwc2: use the nonblock argument in submit_int_msg'
commit 9dcab2c4d2cb50ab1864c818b82a72393c160236

'console: usb: kbd: Limit poll frequency to improve performance'
commit 96991e652f541323a03c5b7e075d54a117091618

This empirically increased by sub-millisecond wait for dwc2 controller reset 
makes
keyboard reliable.

Signed-off-by: Filip Zaludek 
---
  drivers/usb/host/dwc2.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 23060fc369..71b66a52ed 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -764,7 +764,7 @@ static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
  DWC2_HPRT0_PRTENCHNG |
  DWC2_HPRT0_PRTOVRCURRCHNG,
  DWC2_HPRT0_PRTRST);
-    mdelay(50);
+    udelay(50125);


Why not just use 'mdelay(51);' ?

If you can tell me how to reproduce this , I could try and use USB bus analyzer (Beagle 5000) to look at his. I have 
RPi3 somewhere I think. Then we would know what's up.


But that might take a while, since I am a bit busy these days.



  Unfortunately mdelay(51) does not work, what is actually strange.
Be aware 'usb reset' might require 50 repetitions to reproduce,
but usually it is reproduced under 20 cycles.


Prerequisities:
* RPi3B or RPi3B+
* unplugged all usb devices except keyboard, (both usb 1.1 and 2.0 tested)
* RPi3 connected to console and HDMI monitor, (monitor is not requirement)
* u-boot from master compiled without debugging as it works as workaround 
(reproducible with current JeOS-20230110)

Refined reproducer:
* Enter 'U-Boot>' shell using usb keyboard, (always works)
* repeat 'usb reset' until usb keyboard responds, (press ENTER, or ARROW UP 
followed by ENTER [to see responsiveness])
* keyboard can be usually resurrected by subsequent 'usb reset' from console





 Marek Vasut suggested CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y is another way
how to deal with it, I can confirm. Thanks!

Not proposing changes to configs/rpi_3_* defaults, hopefully distributors are 
listening..

Regards,
Filip

Re: [PATCH v3 4/5] spl: Support loading a FIT from ext FS

2023-05-17 Thread Heinrich Schuchardt




Am 17. Mai 2023 16:41:47 MESZ schrieb Tom Rini :
>On Thu, May 04, 2023 at 03:23:26PM +0530, Mayuresh Chitale wrote:
>
>> Detect a FIT when loading from an ext File system and handle it using
>> the FIT SPL support.
>> 
>> Signed-off-by: Mayuresh Chitale 
>> ---
>>  common/spl/spl_ext.c | 33 +
>>  1 file changed, 33 insertions(+)
>> 
>> diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
>> index f117c630bf..7b771c41e9 100644
>> --- a/common/spl/spl_ext.c
>> +++ b/common/spl/spl_ext.c
>> @@ -8,6 +8,26 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>> +
>> +static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
>> +  ulong size, void *buf)
>> +{
>> +loff_t filelen = (loff_t)load->priv, actlen;

The comma seems to be incorrect.

>> +char *filename = (char *)load->filename;
>
>Please build on 32bit platforms such as j721e_evm_r5 as well:
>+common/spl/spl_ext.c:16:26: error: cast from pointer to integer of different 
>size [-Werror=pointer-to-int-cast]
>+   16 | loff_t filelen = (loff_t)load->priv, actlen;
>

Re: [UBOOT PATCH 0/3] Port the usb reset patches from linux

2023-05-17 Thread Marek Vasut


On 5/17/23 08:37, Michal Simek wrote:

Hi,


Hi,


On 5/8/23 13:56, Marek Vasut wrote:

On 5/8/23 05:00, Venkatesh Yadav Abbarapu wrote:

Port the usb reset patches from linux kernel.


What kind of patches are these ?
What sort of problem are those patches attempting to address ?


Venkatesh Yadav Abbarapu (3):
   usb: dwc3: core: improve reset sequence
   usb: dwc3: gadget: Don't send unintended link state change
   usb: dwc3: core: Only handle soft-reset in DCTL


These seem to be randomly picked patches from Linux 4.7, 5.5 ... but 
there seem to be a huge amount of backports missing inbetween, which 
would create a tremendous maintenance burden of the DWC3 driver.


Can you please instead pick ALL the missing patches from Linux, so 
that the DWC3 driver is instead synchronized with Linux, rather than 
diverging and growing partial backports ?


It shouldn't be difficult, one approach I can think of is roughly this:
- figure out the original merge base from which the DWC3 driver was 
imported to U-Boot

- in U-Boot, revert all dwc3 patches on top of that import patch
- pick all Linux kernel dwc3 patches from that merge base and apply on 
top of this U-Boot with reverts

- Run rebase and drop the reverts, let git drop duplicate patches


Based on internal discussion decision was made to keep these patches 
only in soc vendor tree. We are not happy with it but we are not going 
to invest our time and take responsibility for the driver 
synchronization work at this point.


That's unfortunate, as I spent considerable amount of time explaining 
and re-explaining how to perform this synchronization in very much 
automated manner. It would be nice to know whether AMD attempted this 
approach and get a report back regarding any difficulties with that 
approach.


That's why if you insist on full synchronization with Linux version 
please ignore this patchset and also serarate dwc3 clock patch.


I already tried to explain this multiple times before, picking random 
patches into the DWC3 driver would make the full synchronization more 
difficult later, and it would make maintaining the driver harder too.

Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model

2023-05-17 Thread Maxim Kiselev

Hi Sam,

> I might have to start pushing for room for SPI drivers
> in the SPL soon. :)

As Andre already pointed out, I have a patch which adds boot support
from SPI-NOR for D1/T113 SoCs.
Maybe I can share it somewhere to avoid double work?

[PATCH v2] atmel_sdhci: Force card-detect if MMC_CAP_NONREMOVABLE.

2023-05-17 Thread Zixun LI

If the device attached to the MMC bus is not removable, set force card-detect
bit to bypass card detection procedure, so card detection pin can be used for
other purposes.

It's also a workaround for SAMA5D2 who doesn't drive CMD if using GPIO for card
detection.

Signed-off-by: Zixun LI 
---
 drivers/mmc/atmel_sdhci.c | 40 +--
 1 file changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index 37b0beeed4..ae56266f57 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -15,6 +15,9 @@
 #define ATMEL_SDHC_MIN_FREQ40
 #define ATMEL_SDHC_GCK_RATE24000
 
+#define ATMEL_SDHC_MC1R 0x204
+#define ATMEL_SDHC_MC1R_FCD0x80
+
 #ifndef CONFIG_DM_MMC
 int atmel_sdhci_init(void *regbase, u32 id)
 {
@@ -52,11 +55,38 @@ struct atmel_sdhci_plat {
struct mmc mmc;
 };
 
+static void atmel_sdhci_config_fcd(struct sdhci_host *host)
+{
+   u8 mc1r;
+
+   /* If nonremovable, assume that the card is always present.
+*
+* WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
+*/
+   if ((host->mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
+#if CONFIG_IS_ENABLED(DM_GPIO)
+   || dm_gpio_get_value(>cd_gpio) >= 0
+#endif
+  )
+   {
+   sdhci_readb(host, ATMEL_SDHC_MC1R);
+   mc1r |= ATMEL_SDHC_MC1R_FCD;
+   sdhci_writeb(host, mc1r, ATMEL_SDHC_MC1R);
+   }
+}
+
 static int atmel_sdhci_deferred_probe(struct sdhci_host *host)
 {
struct udevice *dev = host->mmc->dev;
+   int ret;
 
-   return sdhci_probe(dev);
+   ret = sdhci_probe(dev);
+   if (ret)
+   return ret;
+
+   atmel_sdhci_config_fcd(host);
+
+   return 0;
 }
 
 static const struct sdhci_ops atmel_sdhci_ops = {
@@ -120,7 +150,13 @@ static int atmel_sdhci_probe(struct udevice *dev)
 
clk_free();
 
-   return sdhci_probe(dev);
+   ret = sdhci_probe(dev);
+   if (ret)
+   return ret;
+
+   atmel_sdhci_config_fcd(host);
+
+   return 0;
 }
 
 static int atmel_sdhci_bind(struct udevice *dev)
-- 
2.40.1

Re: [PATCH v3 4/5] spl: Support loading a FIT from ext FS

2023-05-17 Thread Tom Rini

On Thu, May 04, 2023 at 03:23:26PM +0530, Mayuresh Chitale wrote:

> Detect a FIT when loading from an ext File system and handle it using
> the FIT SPL support.
> 
> Signed-off-by: Mayuresh Chitale 
> ---
>  common/spl/spl_ext.c | 33 +
>  1 file changed, 33 insertions(+)
> 
> diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
> index f117c630bf..7b771c41e9 100644
> --- a/common/spl/spl_ext.c
> +++ b/common/spl/spl_ext.c
> @@ -8,6 +8,26 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +
> +static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
> +   ulong size, void *buf)
> +{
> + loff_t filelen = (loff_t)load->priv, actlen;
> + char *filename = (char *)load->filename;

Please build on 32bit platforms such as j721e_evm_r5 as well:
+common/spl/spl_ext.c:16:26: error: cast from pointer to integer of different 
size [-Werror=pointer-to-int-cast]
+   16 | loff_t filelen = (loff_t)load->priv, actlen;

-- 
Tom


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Re: [PATCH v3 2/2] firmware: zynqmp: Move permission to change config object message

2023-05-17 Thread Stefan Herbrechtsmeier


Am 17.05.2023 um 14:12 schrieb Michal Simek:

On 5/16/23 16:05, Stefan Herbrechtsmeier wrote:

From: Stefan Herbrechtsmeier 

Move the permission to change a config object message from
zynqmp_pmufw_load_config_object function to zynqmp_pmufw_node function
to simplify the code and check the permission only if required.

Signed-off-by: Stefan Herbrechtsmeier 



---

Changes in v4:
- Reword
- Move the check back to zynqmp_pmufw_node because the check need to be
   run after the config object load.
- Return error in zynqmp_pmufw_config_close and zynqmp_pmufw_node

Changes in v3:
- Added

  drivers/firmware/firmware-zynqmp.c | 36 ++
  1 file changed, 17 insertions(+), 19 deletions(-)

diff --git a/drivers/firmware/firmware-zynqmp.c 
b/drivers/firmware/firmware-zynqmp.c

index 2b1ad5d2c3..6dc745bd14 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -63,29 +63,32 @@ static unsigned int xpm_configobject_close[] = {
    int zynqmp_pmufw_config_close(void)
  {
-    zynqmp_pmufw_load_config_object(xpm_configobject_close,
-    sizeof(xpm_configobject_close));
-    return 0;
+    return zynqmp_pmufw_load_config_object(xpm_configobject_close,
+   sizeof(xpm_configobject_close));
  }
    int zynqmp_pmufw_node(u32 id)
  {
-    static bool skip_config;
-    int ret;
+    static bool checked;
+    static bool skip;


I see interesting behavior in connection to these variables.
I did this change and keep test variable to see behavior.


diff --git a/drivers/firmware/firmware-zynqmp.c 
b/drivers/firmware/firmware-zynqmp.c

index 6dc745bd1424..becbea7b64ea 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -67,10 +67,14 @@ int zynqmp_pmufw_config_close(void)
sizeof(xpm_configobject_close));
 }

+static bool checked;
+static bool skip;
+
 int zynqmp_pmufw_node(u32 id)
 {
-   static bool checked;
-   static bool skip;
+   static bool test;
+
+   printf("%s, id %d, ch %d, skp %d - test %d\n", 
__func__, id, checked, skip, test);


    if (!checked) {
    checked = true;
@@ -379,6 +391,9 @@ static int zynqmp_firmware_bind(struct udevice *dev)
    int ret;
    struct udevice *child;

+   checked = 0;
+   skip = 0;
+
    if ((IS_ENABLED(CONFIG_SPL_BUILD) &&
 IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) &&
 IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) ||



zynqmp_power_domain zynqmp_power_domain: Request for id: 34
zynqmp_pmufw_node, id 34, ch 0, skp 0 - test 255/815a2fa
zynqmp_pmufw_node, id 11, ch 1, skp 0 - test 255/815a2fa
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
zynqmp_power_domain zynqmp_power_domain: Domain ON for id: 34
zynq_serial_setbrg: CLK 


U-Boot 2023.07-rc2-00053-gaf7817988644-dirty (May 17 2023 - 14:03:37 
+0200)


CPU:   ZynqMP
Silicon: v3
Chip:  xck26
zynqmp_power_domain zynqmp_power_domain: Request for id: 38
zynqmp_pmufw_node, id 38, ch 1, skp 0 - test 1/815a2fa
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
zynqmp_power_domain zynqmp_power_domain: Domain ON for id: 38
Detected name: zynqmp-smk-k26-xcl2g-revA-sck-kv-g-revB
Model: ZynqMP KV260 revB
Board: Xilinx ZynqMP
DRAM:  2 GiB (effective 4 GiB)
zynqmp_power_domain zynqmp_power_domain: Request for id: 46
zynqmp_pmufw_node, id 46, ch 0, skp 0 - test 0/7ffd42fa
zynqmp_pmufw_node, id 11, ch 1, skp 0 - test 0/7ffd42fa
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
zynqmp_power_domain zynqmp_power_domain: Domain ON for id: 46
PMUFW:    v1.1
zynqmp_power_domain zynqmp_power_domain: Request for id: 38
zynqmp_pmufw_node, id 38, ch 1, skp 0 - test 1/7ffd42fa
---zynqmp_pmufw_node ACCESS OK


As you see test variable is in BSS section but it is not initialized 
at this stage. If you look at arch/arm/lib/crt0_64.S debug uart is 
called before calling board_init_f and bss is cleared before 
board_init_r is called.


What does "but BSS and  initialized non-const data are still not 
available" mean? Could we use variables from the data section like 
"static bool check = true"?


It means variables should be placed to different section or 
initialized them directly from the code.


I think the zynqmp_power variable could have the same problem.

The initialization from the code doesn't work because the class is 
dynamic probed.

zynqmp_pmufw_node -->

Re: U-Boot OMAP GPMC ECC change

2023-05-17 Thread Roger Quadros

Hi Colin,

On 12/05/2023 19:05, Colin Foster wrote:
> Hi Roger,
> 
> On Fri, May 12, 2023 at 02:53:07PM +0300, Roger Quadros wrote:
>>
>>
>> On 10/05/2023 18:38, Colin Foster wrote:
>>>
>>> This is still out-of-U-Boot. I have an include/configs/our_product.h
>>> file with this:
>>>
>>> """
>>> #define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 
>>> 12, \
>>>  13, 14, 15, 16, 17, 18, 19, 20, 
>>> 21, 22, \
>>>  23, 24, 25, 26, 27, 28, 29, 30, 
>>> 31, 32, \
>>>  33, 34, 35, 36, 37, 38, 39, 40, 
>>> 41, \
>>>  42, 43, 44, 45, 46, 47, 48, 49, 
>>> 50, 51, \
>>>  52, 53, 54, 55, 56, 57}
>>>
>>> #define CFG_SYS_NAND_ECCBYTES   14
>>> #define CFG_SYS_NAND_MAX_ECCPOS 57
>>
>> This should be 56 i.e. (57 - 2 + 1)
>> But it won't fix the issue you are facing. :P
> 
> Oh, good catch. I know when I was trying to get this working I had to
> play with these values quite a bit. I must have missed changing this at
> one point.
> 
>>
>>> #define CFG_SYS_NAND_ECCSIZE512
>>> #define CFG_SYS_NAND_MAX_OOBFREE2
>>> """
>>>
>>>
 Can you please point me to the Linux device tree file if it exists?
>>>
>>> This is the latest submission. Still not accepted - I need to find time
>>> to button everything up and resubmit. My plan of attack was Kernel
>>> Acceptance, then U-Boot. Unfortunately my company lets the pesky
>>> "Shipping products" step get in the way :-)
>>>
>>> https://lkml.org/lkml/2023/2/22/939
>>>
>>> Or if you just want the ECC part:
>>>
>>> +   nandflash: nand@0,0 {
>>> +   compatible = "ti,omap2-nand";
>>> +   reg = <0 0 4>;
>>> +   interrupt-parent = <>;
>>> +
>>> +   nand-bus-width = <16>;
>>> +   ti,nand-ecc-opt = "bch8";
>>> +   ti,elm-id=<>;
>>> +   linux,mtd-name = "micron,nand";
>>>
>>>
>>> I think that's all the info you're looking for. Let me know if I missed
>>> something.
>>
>> Yes this is all I was looking for.
>>
>> Is CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW set in your u-boot config?
> 
> Yes, it is set. I've attached our .config file. I just made a change to
> CONFIG_NAND_OMAP_GPMC_PREFETCH as a test, which didn't fix the issue.
> 
> And as another sanity check, I reverted the patch and have functionality
> again:
> 

I just tested this on AM335x EVM which uses BCH8_CODE_HW but 8-bit NAND part.
I see that you are using 16-bit NAND.

One more difference in u-boot configuration. For me:
CONFIG_NAND_OMAP_GPMC_PREFETCH=y

Not sure if that matters but let's keep it set for now.

For debug can you please apply the patch (at end) to u-boot at commit 
a95410696d21
(before breakage) and run the test.

Test procedure:

> nand dump 0

> mmc dev 0 
#replace 0 with whatever points to SD-card
> nand read $loadaddr 0 800
#loadaddr is any address in RAM which is free for use.
> fatwrite mmc 0:1 $loadaddr nand.org 800


- restore NAND page 0

> fatload mmc 0:1 $loadaddr nand.org
> nand write $loadaddr 0 800


Now please run the below test on the offending commit 04fcd25873 after applying
the patch (at end).

> nand dump 0
> mmc dev 0
#replace 0 with whatever points to SD-card
> fatload mmc 0:1 $loadaddr nand.org
> nand write $loadaddr 0 800


Please send me the logs of both tests and the nand.org file so I can try it out 
here. Thanks!


--- patch starts---
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index be3cb3c601..ac06d5f019 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -300,6 +300,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const 
uint8_t *dat,
ecc_code[i++] = (val >>  0) & 0xFF;
ptr--;
}
+   printf("ecc: %x\n", val);
break;
case OMAP_ECC_BCH16_CODE_HW:
val = readl(_cfg->bch_result_4_6[0].bch_result_x[2]);

Re: [PATCH v2] atmel_sdhci: Force card-detect if MMC_CAP_NONREMOVABLE.




Hi Zixun,

On 5/15/23 15:07, Zixun LI wrote:

Signed-off-by:  Zixun LI 


Can you provide a small explanation about what is the commit doing and why ?
It will be recorded in the commit message for future reference.


Can you also fix this warning:


WARNING: Use a single space after Signed-off-by:
#124:
Signed-off-by:  Zixun LI 



---
  drivers/mmc/atmel_sdhci.c | 40 +--
  1 file changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index 37b0beeed4..ae56266f57 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -15,6 +15,9 @@
  #define ATMEL_SDHC_MIN_FREQ   40
  #define ATMEL_SDHC_GCK_RATE   24000
  
+#define ATMEL_SDHC_MC1R 0x204

+#define ATMEL_SDHC_MC1R_FCD0x80
+
  #ifndef CONFIG_DM_MMC
  int atmel_sdhci_init(void *regbase, u32 id)
  {
@@ -52,11 +55,38 @@ struct atmel_sdhci_plat {
struct mmc mmc;
  };
  
+static void atmel_sdhci_config_fcd(struct sdhci_host *host)

+{
+   u8 mc1r;
+
+   /* If nonremovable, assume that the card is always present.
+*
+* WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
+*/
+   if ((host->mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
+#if CONFIG_IS_ENABLED(DM_GPIO)


Can
(CONFIG_IS_ENABLED(DM_REGULATOR)) be used here directly (without the #if 
... #else ) ?


Have you tried it ?

I am not sure whether it works or not, but if it does, it will remove 
the preprocessor directives and it will be more readable



+   || dm_gpio_get_value(>cd_gpio) >= 0
+#endif
+  )
+   {


ERROR: that open brace { should be on the previous line

Fix this as well please



+   sdhci_readb(host, ATMEL_SDHC_MC1R);
+   mc1r |= ATMEL_SDHC_MC1R_FCD;
+   sdhci_writeb(host, mc1r, ATMEL_SDHC_MC1R);
+   }
+}
+
  static int atmel_sdhci_deferred_probe(struct sdhci_host *host)
  {
struct udevice *dev = host->mmc->dev;
+   int ret;
  
-	return sdhci_probe(dev);

+   ret = sdhci_probe(dev);
+   if (ret)
+   return ret;
+
+   atmel_sdhci_config_fcd(host);
+
+   return 0;
  }
  
  static const struct sdhci_ops atmel_sdhci_ops = {

@@ -120,7 +150,13 @@ static int atmel_sdhci_probe(struct udevice *dev)
  
  	clk_free();
  
-	return sdhci_probe(dev);

+   ret = sdhci_probe(dev);
+   if (ret)
+   return ret;
+
+   atmel_sdhci_config_fcd(host);
+
+   return 0;
  }
  
  static int atmel_sdhci_bind(struct udevice *dev)



The patch looks good, however, any changes in the at91 tree at the 
moment are difficult to do because some of the boards get an overflow on 
the SPL memory size. So your patch has to go after that is fixed 
(pending...)


Eugen

Re: [PATCH v3 2/2] firmware: zynqmp: Move permission to change config object message





On 5/16/23 16:05, Stefan Herbrechtsmeier wrote:

From: Stefan Herbrechtsmeier 

Move the permission to change a config object message from
zynqmp_pmufw_load_config_object function to zynqmp_pmufw_node function
to simplify the code and check the permission only if required.

Signed-off-by: Stefan Herbrechtsmeier 

---

Changes in v4:
- Reword
- Move the check back to zynqmp_pmufw_node because the check need to be
   run after the config object load.
- Return error in zynqmp_pmufw_config_close and zynqmp_pmufw_node

Changes in v3:
- Added

  drivers/firmware/firmware-zynqmp.c | 36 ++
  1 file changed, 17 insertions(+), 19 deletions(-)

diff --git a/drivers/firmware/firmware-zynqmp.c 
b/drivers/firmware/firmware-zynqmp.c
index 2b1ad5d2c3..6dc745bd14 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -63,29 +63,32 @@ static unsigned int xpm_configobject_close[] = {
  
  int zynqmp_pmufw_config_close(void)

  {
-   zynqmp_pmufw_load_config_object(xpm_configobject_close,
-   sizeof(xpm_configobject_close));
-   return 0;
+   return zynqmp_pmufw_load_config_object(xpm_configobject_close,
+  sizeof(xpm_configobject_close));
  }
  
  int zynqmp_pmufw_node(u32 id)

  {
-   static bool skip_config;
-   int ret;
+   static bool checked;
+   static bool skip;


I see interesting behavior in connection to these variables.
I did this change and keep test variable to see behavior.


diff --git a/drivers/firmware/firmware-zynqmp.c 
b/drivers/firmware/firmware-zynqmp.c
index 6dc745bd1424..becbea7b64ea 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -67,10 +67,14 @@ int zynqmp_pmufw_config_close(void)
   sizeof(xpm_configobject_close));
 }

+static bool checked;
+static bool skip;
+
 int zynqmp_pmufw_node(u32 id)
 {
-   static bool checked;
-   static bool skip;
+   static bool test;
+
+   printf("%s, id %d, ch %d, skp %d - test %d\n", __func__, 
id, checked, skip, test);


if (!checked) {
checked = true;
@@ -379,6 +391,9 @@ static int zynqmp_firmware_bind(struct udevice *dev)
int ret;
struct udevice *child;

+   checked = 0;
+   skip = 0;
+
if ((IS_ENABLED(CONFIG_SPL_BUILD) &&
 IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) &&
 IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) ||



zynqmp_power_domain zynqmp_power_domain: Request for id: 34
zynqmp_pmufw_node, id 34, ch 0, skp 0 - test 255/815a2fa
zynqmp_pmufw_node, id 11, ch 1, skp 0 - test 255/815a2fa
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
zynqmp_power_domain zynqmp_power_domain: Domain ON for id: 34
zynq_serial_setbrg: CLK 


U-Boot 2023.07-rc2-00053-gaf7817988644-dirty (May 17 2023 - 14:03:37 +0200)

CPU:   ZynqMP
Silicon: v3
Chip:  xck26
zynqmp_power_domain zynqmp_power_domain: Request for id: 38
zynqmp_pmufw_node, id 38, ch 1, skp 0 - test 1/815a2fa
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
zynqmp_power_domain zynqmp_power_domain: Domain ON for id: 38
Detected name: zynqmp-smk-k26-xcl2g-revA-sck-kv-g-revB
Model: ZynqMP KV260 revB
Board: Xilinx ZynqMP
DRAM:  2 GiB (effective 4 GiB)
zynqmp_power_domain zynqmp_power_domain: Request for id: 46
zynqmp_pmufw_node, id 46, ch 0, skp 0 - test 0/7ffd42fa
zynqmp_pmufw_node, id 11, ch 1, skp 0 - test 0/7ffd42fa
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
---zynqmp_pmufw_node ACCESS OK
zynqmp_pmufw_load_config_object
zynqmp_pmufw_load_config_object44
zynqmp_power_domain zynqmp_power_domain: Domain ON for id: 46
PMUFW:  v1.1
zynqmp_power_domain zynqmp_power_domain: Request for id: 38
zynqmp_pmufw_node, id 38, ch 1, skp 0 - test 1/7ffd42fa
---zynqmp_pmufw_node ACCESS OK


As you see test variable is in BSS section but it is not initialized at this 
stage. If you look at arch/arm/lib/crt0_64.S debug uart is called before calling 
board_init_f and bss is cleared before board_init_r is called.


It means variables should be placed to different section or initialized them 
directly from the code.


  
-	if (skip_config)

-   return 0;
+   if (!checked) {
+   checked = true;
  
-	/* Record power domain id */

-   xpm_configobject[NODE_ID_LOCATION] = id;
+   if (zynqmp_pmufw_node(NODE_OCM_BANK_0) == -EACCES) {
+

Re: [PATCH] global: Use proper project name U-Boot

2023-05-17 Thread Ilias Apalodimas

On Wed, 17 May 2023 at 10:18, Michal Simek  wrote:
>
> Use proper project name in comments, Kconfig, readmes.
>
> Signed-off-by: Michal Simek 
> ---
>
> I am ignoring these for now because they can break automated scripts or
> user setting that's why they should be fixed separately.
>
> arch/arm/dts/am335x-igep0033.dtsi:178:  label = "U-boot";
> arch/arm/dts/armada-3720-db.dts:183:label = 
> "U-boot Env";
> board/armadeus/opos6uldev/opos6uldev.env:45:echo Flashing 
> of U-boot SPL succeed;
> board/armadeus/opos6uldev/opos6uldev.env:46:else echo Flashing of 
> U-boot SPL failed;
> board/armadeus/opos6uldev/opos6uldev.env:55:echo Flashing 
> of U-boot image succeed;
> board/armadeus/opos6uldev/opos6uldev.env:56:else echo Flashing of 
> U-boot image failed;
> board/freescale/common/fsl_chain_of_trust.c:130:printf("SPL: 
> Validation of U-boot successful\n");
> board/freescale/ls1012afrdm/README:55:U-boot| 1MB   | 0x4010_
> board/freescale/ls1012afrdm/README:56:U-boot Env| 1MB   | 0x4020_
> board/freescale/ls1012aqds/README:56:U-boot | 1MB   | 0x4010_
> board/freescale/ls1012aqds/README:57:U-boot Env | 1MB   | 0x4020_
> board/freescale/ls1012ardb/README:51:U-boot | 1MB   | 0x4010_
> board/freescale/ls1012ardb/README:52:U-boot Env | 1MB   | 0x4020_
> board/freescale/ls1012ardb/README:93:U-boot | 1MB   | 0x4010_
> board/freescale/ls1012ardb/README:94:U-boot Env | 1MB   | 0x4030_
> board/imgtec/boston/checkboard.c:19:lowlevel_display("U-boot  ");
> doc/board/amlogic/pre-generated-fip.rst:77:- bl33.bin: U-boot binary image
> include/dt-bindings/memory/bcm-ns3-mc.h:31:/* ATF/U-boot/Linux error logs */
> net/dhcpv6.h:41:#define DHCP6_VCI_STRING"U-boot"
>
> ---
>  arch/Kconfig.nxp   |  2 +-
>  arch/arc/include/asm/io.h  |  2 +-
>  arch/arm/cpu/armv7/Kconfig |  2 +-
>  arch/arm/cpu/armv8/Kconfig |  2 +-
>  .../cpu/armv8/fsl-layerscape/doc/README.lsch3  |  2 +-
>  arch/arm/dts/fsl-ls1028a.dtsi  |  2 +-
>  arch/arm/dts/meson-g12-common-u-boot.dtsi  |  2 +-
>  arch/arm/dts/meson-gx-u-boot.dtsi  |  2 +-
>  arch/arm/dts/rk3328-evb-u-boot.dtsi|  2 +-
>  arch/arm/dts/rk3328.dtsi   |  2 +-
>  .../asm/arch-fsl-layerscape/stream_id_lsch2.h  |  2 +-
>  .../asm/arch-fsl-layerscape/stream_id_lsch3.h  |  2 +-
>  board/bosch/acc/acc.c  |  2 +-
>  board/bosch/shc/README |  2 +-
>  board/compulab/cl-som-imx7/cl-som-imx7.c   |  2 +-
>  board/hisilicon/poplar/README  |  2 +-
>  board/isee/igep003x/board.c|  2 +-
>  board/isee/igep00x0/igep00x0.c |  2 +-
>  board/keymile/Kconfig  |  8 
>  board/keymile/README   |  2 +-
>  board/kontron/sl-mx6ul/spl.c   |  2 +-
>  board/phytec/pcm058/README | 18 +-
>  board/synopsys/hsdk/hsdk.c | 14 +++---
>  boot/boot_fit.c|  2 +-
>  cmd/ufs.c  |  2 +-
>  common/spl/spl.c   |  2 +-
>  common/spl/spl_mmc.c   |  2 +-
>  doc/README.pcap|  2 +-
>  doc/README.s5p4418 |  2 +-
>  doc/SPL/README.spl-secure-boot |  4 ++--
>  doc/board/amlogic/p201.rst |  2 +-
>  doc/board/amlogic/p212.rst |  2 +-
>  doc/board/amlogic/s400.rst |  2 +-
>  doc/board/emulation/qemu-arm.rst   |  2 +-
>  doc/board/nxp/ls1046ardb.rst   |  2 +-
>  doc/board/nxp/mx6sabresd.rst   |  2 +-
>  doc/board/rockchip/rockchip.rst|  6 +++---
>  doc/board/sifive/unmatched.rst |  2 +-
>  doc/board/st/stm32mp1.rst  |  2 +-
>  doc/board/xen/xenguest_arm64.rst   | 10 +-
>  doc/develop/driver-model/bind.rst  |  2 +-
>  .../driver-model/fs_firmware_loader.rst|  6 +++---
>  doc/develop/uefi/uefi.rst  |  2 +-
>  doc/usage/cmd/source.rst   |  2 +-
>  doc/usage/dfu.rst  |  2 +-
>  drivers/clk/clk-mux.c  |  2 +-
>  drivers/gpio/gpio-fxl6408.c|  2 +-
>  drivers/mtd/nand/raw/Kconfig   |  6 +++---
>  drivers/mtd/nand/raw/fsl_ifc_spl.c |  4 ++--
>  drivers/net/pfe_eth/pfe_hw.c   |  2 +-
>  drivers/phy/marvell/comphy_cp110.c |  2 +-
>  drivers/spi/spi-qup.c  |  2 +-
>  dts/Kconfig

Re: [PATCH] global: Use proper project name U-Boot

2023-05-17 Thread Stefan Roese


On 5/17/23 09:17, Michal Simek wrote:

Use proper project name in comments, Kconfig, readmes.

Signed-off-by: Michal Simek 


Reviewed-by: Stefan Roese 

Thanks,
Stefan


---

I am ignoring these for now because they can break automated scripts or
user setting that's why they should be fixed separately.

arch/arm/dts/am335x-igep0033.dtsi:178:  label = "U-boot";
arch/arm/dts/armada-3720-db.dts:183:label = "U-boot 
Env";
board/armadeus/opos6uldev/opos6uldev.env:45:echo Flashing 
of U-boot SPL succeed;
board/armadeus/opos6uldev/opos6uldev.env:46:else echo Flashing of 
U-boot SPL failed;
board/armadeus/opos6uldev/opos6uldev.env:55:echo Flashing 
of U-boot image succeed;
board/armadeus/opos6uldev/opos6uldev.env:56:else echo Flashing of 
U-boot image failed;
board/freescale/common/fsl_chain_of_trust.c:130:printf("SPL: 
Validation of U-boot successful\n");
board/freescale/ls1012afrdm/README:55:U-boot| 1MB   | 0x4010_
board/freescale/ls1012afrdm/README:56:U-boot Env| 1MB   | 0x4020_
board/freescale/ls1012aqds/README:56:U-boot | 1MB   | 0x4010_
board/freescale/ls1012aqds/README:57:U-boot Env | 1MB   | 0x4020_
board/freescale/ls1012ardb/README:51:U-boot | 1MB   | 0x4010_
board/freescale/ls1012ardb/README:52:U-boot Env | 1MB   | 0x4020_
board/freescale/ls1012ardb/README:93:U-boot | 1MB   | 0x4010_
board/freescale/ls1012ardb/README:94:U-boot Env | 1MB   | 0x4030_
board/imgtec/boston/checkboard.c:19:lowlevel_display("U-boot  ");
doc/board/amlogic/pre-generated-fip.rst:77:- bl33.bin: U-boot binary image
include/dt-bindings/memory/bcm-ns3-mc.h:31:/* ATF/U-boot/Linux error logs */
net/dhcpv6.h:41:#define DHCP6_VCI_STRING"U-boot"

---
  arch/Kconfig.nxp   |  2 +-
  arch/arc/include/asm/io.h  |  2 +-
  arch/arm/cpu/armv7/Kconfig |  2 +-
  arch/arm/cpu/armv8/Kconfig |  2 +-
  .../cpu/armv8/fsl-layerscape/doc/README.lsch3  |  2 +-
  arch/arm/dts/fsl-ls1028a.dtsi  |  2 +-
  arch/arm/dts/meson-g12-common-u-boot.dtsi  |  2 +-
  arch/arm/dts/meson-gx-u-boot.dtsi  |  2 +-
  arch/arm/dts/rk3328-evb-u-boot.dtsi|  2 +-
  arch/arm/dts/rk3328.dtsi   |  2 +-
  .../asm/arch-fsl-layerscape/stream_id_lsch2.h  |  2 +-
  .../asm/arch-fsl-layerscape/stream_id_lsch3.h  |  2 +-
  board/bosch/acc/acc.c  |  2 +-
  board/bosch/shc/README |  2 +-
  board/compulab/cl-som-imx7/cl-som-imx7.c   |  2 +-
  board/hisilicon/poplar/README  |  2 +-
  board/isee/igep003x/board.c|  2 +-
  board/isee/igep00x0/igep00x0.c |  2 +-
  board/keymile/Kconfig  |  8 
  board/keymile/README   |  2 +-
  board/kontron/sl-mx6ul/spl.c   |  2 +-
  board/phytec/pcm058/README | 18 +-
  board/synopsys/hsdk/hsdk.c | 14 +++---
  boot/boot_fit.c|  2 +-
  cmd/ufs.c  |  2 +-
  common/spl/spl.c   |  2 +-
  common/spl/spl_mmc.c   |  2 +-
  doc/README.pcap|  2 +-
  doc/README.s5p4418 |  2 +-
  doc/SPL/README.spl-secure-boot |  4 ++--
  doc/board/amlogic/p201.rst |  2 +-
  doc/board/amlogic/p212.rst |  2 +-
  doc/board/amlogic/s400.rst |  2 +-
  doc/board/emulation/qemu-arm.rst   |  2 +-
  doc/board/nxp/ls1046ardb.rst   |  2 +-
  doc/board/nxp/mx6sabresd.rst   |  2 +-
  doc/board/rockchip/rockchip.rst|  6 +++---
  doc/board/sifive/unmatched.rst |  2 +-
  doc/board/st/stm32mp1.rst  |  2 +-
  doc/board/xen/xenguest_arm64.rst   | 10 +-
  doc/develop/driver-model/bind.rst  |  2 +-
  .../driver-model/fs_firmware_loader.rst|  6 +++---
  doc/develop/uefi/uefi.rst  |  2 +-
  doc/usage/cmd/source.rst   |  2 +-
  doc/usage/dfu.rst  |  2 +-
  drivers/clk/clk-mux.c  |  2 +-
  drivers/gpio/gpio-fxl6408.c|  2 +-
  drivers/mtd/nand/raw/Kconfig   |  6 +++---
  drivers/mtd/nand/raw/fsl_ifc_spl.c |  4 ++--
  drivers/net/pfe_eth/pfe_hw.c   |  2 +-
  drivers/phy/marvell/comphy_cp110.c |  2 +-
  drivers/spi/spi-qup.c  |  2 +-
  dts/Kconfig|  4 ++--
  fs/btrfs/compat.h

[PATCH] global: Use proper project name U-Boot

Use proper project name in comments, Kconfig, readmes.

Signed-off-by: Michal Simek 
---

I am ignoring these for now because they can break automated scripts or
user setting that's why they should be fixed separately.

arch/arm/dts/am335x-igep0033.dtsi:178:  label = "U-boot";
arch/arm/dts/armada-3720-db.dts:183:label = "U-boot 
Env";
board/armadeus/opos6uldev/opos6uldev.env:45:echo Flashing 
of U-boot SPL succeed;
board/armadeus/opos6uldev/opos6uldev.env:46:else echo Flashing of 
U-boot SPL failed;
board/armadeus/opos6uldev/opos6uldev.env:55:echo Flashing 
of U-boot image succeed;
board/armadeus/opos6uldev/opos6uldev.env:56:else echo Flashing of 
U-boot image failed;
board/freescale/common/fsl_chain_of_trust.c:130:printf("SPL: 
Validation of U-boot successful\n");
board/freescale/ls1012afrdm/README:55:U-boot| 1MB   | 0x4010_
board/freescale/ls1012afrdm/README:56:U-boot Env| 1MB   | 0x4020_
board/freescale/ls1012aqds/README:56:U-boot | 1MB   | 0x4010_
board/freescale/ls1012aqds/README:57:U-boot Env | 1MB   | 0x4020_
board/freescale/ls1012ardb/README:51:U-boot | 1MB   | 0x4010_
board/freescale/ls1012ardb/README:52:U-boot Env | 1MB   | 0x4020_
board/freescale/ls1012ardb/README:93:U-boot | 1MB   | 0x4010_
board/freescale/ls1012ardb/README:94:U-boot Env | 1MB   | 0x4030_
board/imgtec/boston/checkboard.c:19:lowlevel_display("U-boot  ");
doc/board/amlogic/pre-generated-fip.rst:77:- bl33.bin: U-boot binary image
include/dt-bindings/memory/bcm-ns3-mc.h:31:/* ATF/U-boot/Linux error logs */
net/dhcpv6.h:41:#define DHCP6_VCI_STRING"U-boot"

---
 arch/Kconfig.nxp   |  2 +-
 arch/arc/include/asm/io.h  |  2 +-
 arch/arm/cpu/armv7/Kconfig |  2 +-
 arch/arm/cpu/armv8/Kconfig |  2 +-
 .../cpu/armv8/fsl-layerscape/doc/README.lsch3  |  2 +-
 arch/arm/dts/fsl-ls1028a.dtsi  |  2 +-
 arch/arm/dts/meson-g12-common-u-boot.dtsi  |  2 +-
 arch/arm/dts/meson-gx-u-boot.dtsi  |  2 +-
 arch/arm/dts/rk3328-evb-u-boot.dtsi|  2 +-
 arch/arm/dts/rk3328.dtsi   |  2 +-
 .../asm/arch-fsl-layerscape/stream_id_lsch2.h  |  2 +-
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h  |  2 +-
 board/bosch/acc/acc.c  |  2 +-
 board/bosch/shc/README |  2 +-
 board/compulab/cl-som-imx7/cl-som-imx7.c   |  2 +-
 board/hisilicon/poplar/README  |  2 +-
 board/isee/igep003x/board.c|  2 +-
 board/isee/igep00x0/igep00x0.c |  2 +-
 board/keymile/Kconfig  |  8 
 board/keymile/README   |  2 +-
 board/kontron/sl-mx6ul/spl.c   |  2 +-
 board/phytec/pcm058/README | 18 +-
 board/synopsys/hsdk/hsdk.c | 14 +++---
 boot/boot_fit.c|  2 +-
 cmd/ufs.c  |  2 +-
 common/spl/spl.c   |  2 +-
 common/spl/spl_mmc.c   |  2 +-
 doc/README.pcap|  2 +-
 doc/README.s5p4418 |  2 +-
 doc/SPL/README.spl-secure-boot |  4 ++--
 doc/board/amlogic/p201.rst |  2 +-
 doc/board/amlogic/p212.rst |  2 +-
 doc/board/amlogic/s400.rst |  2 +-
 doc/board/emulation/qemu-arm.rst   |  2 +-
 doc/board/nxp/ls1046ardb.rst   |  2 +-
 doc/board/nxp/mx6sabresd.rst   |  2 +-
 doc/board/rockchip/rockchip.rst|  6 +++---
 doc/board/sifive/unmatched.rst |  2 +-
 doc/board/st/stm32mp1.rst  |  2 +-
 doc/board/xen/xenguest_arm64.rst   | 10 +-
 doc/develop/driver-model/bind.rst  |  2 +-
 .../driver-model/fs_firmware_loader.rst|  6 +++---
 doc/develop/uefi/uefi.rst  |  2 +-
 doc/usage/cmd/source.rst   |  2 +-
 doc/usage/dfu.rst  |  2 +-
 drivers/clk/clk-mux.c  |  2 +-
 drivers/gpio/gpio-fxl6408.c|  2 +-
 drivers/mtd/nand/raw/Kconfig   |  6 +++---
 drivers/mtd/nand/raw/fsl_ifc_spl.c |  4 ++--
 drivers/net/pfe_eth/pfe_hw.c   |  2 +-
 drivers/phy/marvell/comphy_cp110.c |  2 +-
 drivers/spi/spi-qup.c  |  2 +-
 dts/Kconfig|  4 ++--
 fs/btrfs/compat.h  |  2 +-
 fs/btrfs/extent-io.h   |  2 +-
 include/fsl_validate.h |  4 ++--

Re: [PATCH 1/2] net: rtl8169: add minimal support for 8125B variant


On 4/30/23 22:44, Ramon Fried wrote:

On Tue, Apr 25, 2023 at 10:47 PM Eugen Hristev
 wrote:


On 4/25/23 22:22, Ramon Fried wrote:

On Tue, Apr 25, 2023 at 4:17 PM Eugen Hristev
 wrote:


On 4/25/23 16:06, Eugen Hristev wrote:

Add minimal support for 8125B version.
Changes are based on the Linux driver.
Tested on Radxa Rock 5B Rk3588 board.

Connection to a laptop worked fine in 100 Mbps mode.
1000 Mbps mode is not working at the moment.

Signed-off-by: Eugen Hristev 
---


The one thing that impacts all the rtl chips is the way the pci BAR is
now mapped.
I could not test this on another platform so help on this matter is
appreciated.

Thanks!
Eugen

Let's wait a bit to see if someone can test it. why did you change the
mapping of the BAR ?


It did not work with the old code. It provided a bad address, to some
area which did not have the right registers.
I looked into similar drivers and they were using this call, which works
perfectly for 8125b device

Eugen

Ok.
Hopefully nothing breaks.
Reviewed-by: Ramon Fried 



Hello Ramon,

I have a question if you don't mind, maybe you are better suited to 
answer this :


In the case of rtl8169 which is a pci express device, the probing is 
done on demand (pci enum) or with MISC_INIT_R, anyway, the probing is 
done *after* the board init is done, and in case of rockchip, the board 
init will check if there is any 'ethaddr' set, and if not, set the 
ethaddr by generating an unique cpuid-based MAC. This happens, no 
ethaddr is set, and the MAC is generated.
However, when the rtl8169 probes, it has ofcourse a different hardware 
written MAC, but the uboot subsystem will deny it, and claim ethaddr is 
already set, and it will call the 8169 driver to rewrite its MAC.
This then happens, and Uboot will use the initial ethaddr (the one 
generated) for any kind of packets.
While this is not a problem at first glance, when Linux boots, it will 
read the MAC from rtl8169 ROM (even if uboot attempted to rewrite its 
MAC, being a ROM, it will not be written), and Linux will use a 
different MAC now.
Do you have any idea on how to solve this problem ? I would like that 
once rtl8169 driver probes, the initial ethaddr would be overwritten.


Thanks !

Re: [PATCH 2/2] configs: rock5b-rk3588: add rtl8169 driver


On 5/15/23 16:16, Tom Rini wrote:

On Mon, May 15, 2023 at 03:57:14PM +0300, Eugen Hristev wrote:

On 5/15/23 15:52, Tom Rini wrote:

On Mon, May 15, 2023 at 03:36:24PM +0300, Eugen Hristev wrote:

On 5/6/23 01:03, Tom Rini wrote:

On Tue, Apr 25, 2023 at 04:06:59PM +0300, Eugen Hristev wrote:

Add the rtl8169 driver, which supports the rtl8125b device, which is
connected on the pciE bus on this board.
Enable also CONFIG_SYS_HAS_NONCACHED_MEMORY to have the descriptors stored.

Signed-off-by: Eugen Hristev 
---
configs/rock5b-rk3588_defconfig | 2 ++
1 file changed, 2 insertions(+)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index a14fcd2ee924..bfa48227aee2 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a0
@@ -71,6 +72,7 @@ CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_RTL8169=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y


Does this depend on some series I missed where PCI is enabled on this
config?



Hi Tom,

the network device is connected on PCI express, that is right. I have a
separate series for that.
However, the network driver itself and the enabling of the network driver is
somewhat independent, so I sent it as a separate series (this one )
I think the config patch can go through rockchip custodian tree.


With 1/2 now applied this results in failure to build due to DM_PCI not
being enabled.



This is most strange. 1/2 are just changes in the driver. How does that
cause a build failure ?
The driver is not even selected for this config in 2/2, before the actual
patch.
Do you have the log of the failure so I can have a look ?


I don't have the log handy right now, please re-test the config changes
on top of master and repost.




Hi Tom,

I figured out the issue.
My patch is indeed based on another patch that selects CONFIG_PCI.

However, the rtl8169 driver depends on PCI, even if it does not have 
'depends on PCI' in the Kconfig.

So selecting it without PCI, well, the error.

So I sent another patch :

https://patchwork.ozlabs.org/project/uboot/patch/20230517104124.111075-1-eugen.hris...@collabora.com/

... that should have the rtl8169 depend on PCI now.

That being said, this current patch can be applied on kever's rockchip 
master branch on top of PCI series, but if it's to be applied on master, 
it should work on top of the 'rtl8169 depends on PCI' patch now.


I hope it makes sense.
Thanks

[PATCH] net: rtl8169: add depends on PCI

The rtl8169 driver uses calls to dm_pci_bus_to_phys,
which are compiled under CONFIG_PCI.

Without CONFIG_PCI, this happens:

drivers/net/rtl8169.o: in function `rtl_recv_common':
drivers/net/rtl8169.c:555: undefined reference to `dm_pci_bus_to_phys'

It is only natural that this driver depends on CONFIG_PCI then.
The device does not work connected in another way anyway, and the driver
does not assume anything else at this moment.

Signed-off-by: Eugen Hristev 
---
 drivers/net/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09039a283eb5..39eee98ca79f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -633,6 +633,7 @@ config RTL8139
 
 config RTL8169
bool "Realtek 8169 series Ethernet controller driver"
+   depends on PCI
help
  This driver supports Realtek 8169 series gigabit ethernet family of
  PCI/PCIe chipsets/adapters.
-- 
2.34.1

Re: [PATCH v6] configs: rockchip: rock5b-rk3588: enable USB and regulators


On 5/17/23 12:38, Kever Yang wrote:

Hi Eugen,

Applied, thanks.


- Kever



Hi Kever,

Any other patches that you wish me to resend ?

Also, Jonas,

I have one thing in my tree that may be already sent by you, but let's 
double check: adding gpio command to rock5b config, have you sent that 
already ?


Thanks,
Eugen

[PATCH 1/1] fs: fix smh_fs_read_at()

2023-05-17 Thread Heinrich Schuchardt

The return value of smh_flen() is written to size and not to ret. But ret
is checked. We can avoid calling smh_flen() by setting maxsize to LONG_MAX
if it is not set yet.

Check input parameters.

Fixes: f676b45151c3 ("fs: Add semihosting filesystem")
Signed-off-by: Heinrich Schuchardt 
---
 fs/semihostingfs.c | 14 +-
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/fs/semihostingfs.c b/fs/semihostingfs.c
index 96eb3349a2..8a7d4da884 100644
--- a/fs/semihostingfs.c
+++ b/fs/semihostingfs.c
@@ -25,6 +25,9 @@ static int smh_fs_read_at(const char *filename, loff_t pos, 
void *buffer,
 {
long fd, size, ret;
 
+   if (pos > LONG_MAX || maxsize > LONG_MAX)
+   return -EINVAL;
+
fd = smh_open(filename, MODE_READ | MODE_BINARY);
if (fd < 0)
return fd;
@@ -33,15 +36,8 @@ static int smh_fs_read_at(const char *filename, loff_t pos, 
void *buffer,
smh_close(fd);
return ret;
}
-   if (!maxsize) {
-   size = smh_flen(fd);
-   if (ret < 0) {
-   smh_close(fd);
-   return size;
-   }
-
-   maxsize = size;
-   }
+   if (!maxsize)
+   maxsize = LONG_MAX;
 
size = smh_read(fd, buffer, maxsize);
smh_close(fd);
-- 
2.39.2

Re: [PATCH resend v3 3/3] configs: rock5b-rk3588: add PCI drivers and command




On 2023/5/17 18:01, Eugen Hristev wrote:

Add drivers for PCIe , phy, and command.

Signed-off-by: Eugen Hristev 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  configs/rock5b-rk3588_defconfig | 4 
  1 file changed, 4 insertions(+)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index fc76d9347db1..f8a9c783764b 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -41,6 +41,7 @@ CONFIG_SPL_STACK_R=y
  CONFIG_SPL_ATF=y
  CONFIG_CMD_GPT=y
  CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
  CONFIG_CMD_USB=y
  # CONFIG_CMD_SETEXPR is not set
  CONFIG_CMD_REGULATOR=y
@@ -63,7 +64,10 @@ CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
  CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
  CONFIG_SPL_PINCTRL=y
  CONFIG_REGULATOR_PWM=y
  CONFIG_DM_REGULATOR_FIXED=y

Re: [PATCH resend v3 2/3] ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphy




On 2023/5/17 18:01, Eugen Hristev wrote:

From: Christopher Obbard 

Enable the PCIe 2x1l 2 device and associated combphy.
On this bus, the Rock5B has an Ethernet transceiver connected.

Signed-off-by: Christopher Obbard 
[eugen.hris...@collabora.com: minor tweaks]
Signed-off-by: Eugen Hristev 
[jo...@kwiboo.se: add PCIe pins]
Signed-off-by: Jonas Karlman 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 22 ++
  1 file changed, 22 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index e9fcb7b92eb3..406303920d95 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -30,9 +30,31 @@
};
  };
  
+_ps {

+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins _reset_h>;
+   reset-gpios = < RK_PB0 GPIO_ACTIVE_HIGH>;
+   status = "okay";
+};
+
   {
bootph-all;
  
+	pcie {

+   pcie_reset_h: pcie-reset-h {
+   rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO _pull_none>;
+   };
+
+   pcie2x1l2_pins: pcie2x1l2-pins {
+   rockchip,pins = <3 RK_PC7 4 _pull_none>,
+   <3 RK_PD0 4 _pull_none>;
+   };
+   };
+
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO _pull_none>;

Re: [PATCH resend v3 1/3] ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY




On 2023/5/17 18:01, Eugen Hristev wrote:

From: Joseph Chen 

Add the node for PCIe 2x1l 2 device together with the corresponding
combphy.

Signed-off-by: Joseph Chen 
[eugen.hris...@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev 
[jo...@kwiboo.se: adapt to kernel node]
Signed-off-by: Jonas Karlman 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  arch/arm/dts/rk3588s-u-boot.dtsi | 77 
  1 file changed, 77 insertions(+)

diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 922cae3f0921..4fdf97ccac44 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -4,6 +4,7 @@
   */
  
  #include "rockchip-u-boot.dtsi"

+#include 
  
  / {

dmc {
@@ -58,6 +59,11 @@
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
  
+	pipe_phy0_grf: syscon@fd5bc000 {

+   compatible = "rockchip,pipe-phy-grf", "syscon";
+   reg = <0x0 0xfd5bc000 0x0 0x100>;
+   };
+
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
 "simple-mfd";
@@ -104,6 +110,61 @@
};
};
  
+	pcie2x1l2: pcie@fe19 {

+   compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x40 0x4f>;
+   clocks = < ACLK_PCIE_1L2_MSTR>, < ACLK_PCIE_1L2_SLV>,
+< ACLK_PCIE_1L2_DBI>, < PCLK_PCIE_1L2>,
+< CLK_PCIE_AUX4>, < CLK_PCIE1L2_PIPE>;
+   clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+   device_type = "pci";
+   interrupts = ,
+,
+,
+,
+;
+   interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 _intc 0>,
+   <0 0 0 2 _intc 1>,
+   <0 0 0 3 _intc 2>,
+   <0 0 0 4 _intc 3>;
+   linux,pci-domain = <4>;
+   num-ib-windows = <8>;
+   num-ob-windows = <8>;
+   num-viewport = <4>;
+   max-link-speed = <2>;
+   msi-map = <0x4000  0x4000 0x1000>;
+   num-lanes = <1>;
+   phys = <_ps PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy";
+   power-domains = < RK3588_PD_PCIE>;
+   ranges = <0x0100 0x0 0xf410 0x0 0xf410 0x0 
0x0010>,
+<0x0200 0x0 0xf420 0x0 0xf420 0x0 
0x00e0>,
+<0x0300 0x0 0x4000 0xa 0x 0x0 
0x4000>;
+   reg = <0xa 0x4100 0x0 0x0040>,
+ <0x0 0xfe19 0x0 0x0001>,
+ <0x0 0xf400 0x0 0x0010>;
+   reg-names = "dbi", "apb", "config";
+   resets = < SRST_PCIE4_POWER_UP>, < SRST_P_PCIE4>;
+   reset-names = "pcie", "periph";
+   rockchip,pipe-grf = <_grf>;
+   status = "disabled";
+
+   pcie2x1l2_intc: legacy-interrupt-controller {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-parent = <>;
+   interrupts = ;
+   };
+   };
+
otp: nvmem@fecc {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc 0x0 0x400>;
@@ -121,6 +182,22 @@
reg = <0x0 0xfe378000 0x0 0x200>;
status = "disabled";
};
+
+   combphy0_ps: phy@fee0 {
+   compatible = "rockchip,rk3588-naneng-combphy";
+   reg = <0x0 0xfee0 0x0 0x100>;
+   #phy-cells = <1>;
+   clocks = < CLK_REF_PIPE_PHY0>, < 
PCLK_PCIE_COMBO_PIPE_PHY0>,
+< PCLK_PHP_ROOT>;
+   clock-names = "refclk", "apbclk", "phpclk";
+   assigned-clocks = < CLK_REF_PIPE_PHY0>;
+   assigned-clock-rates = <1>;
+   resets = < SRST_P_PCIE2_PHY0>, < SRST_REF_PIPE_PHY0>;
+   reset-names = "combphy-apb", "combphy";
+   rockchip,pipe-grf = <_grf>;
+   rockchip,pipe-phy-grf = <_phy0_grf>;
+   status = "disabled";
+   };
  };
  
   {

[PATCH resend v3 3/3] configs: rock5b-rk3588: add PCI drivers and command

Add drivers for PCIe , phy, and command.

Signed-off-by: Eugen Hristev 
---
 configs/rock5b-rk3588_defconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index fc76d9347db1..f8a9c783764b 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -41,6 +41,7 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_REGULATOR=y
@@ -63,7 +64,10 @@ CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_DM_REGULATOR_FIXED=y
-- 
2.34.1

[PATCH resend v3 2/3] ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphy

From: Christopher Obbard 

Enable the PCIe 2x1l 2 device and associated combphy.
On this bus, the Rock5B has an Ethernet transceiver connected.

Signed-off-by: Christopher Obbard 
[eugen.hris...@collabora.com: minor tweaks]
Signed-off-by: Eugen Hristev 
[jo...@kwiboo.se: add PCIe pins]
Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index e9fcb7b92eb3..406303920d95 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -30,9 +30,31 @@
};
 };
 
+_ps {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins _reset_h>;
+   reset-gpios = < RK_PB0 GPIO_ACTIVE_HIGH>;
+   status = "okay";
+};
+
  {
bootph-all;
 
+   pcie {
+   pcie_reset_h: pcie-reset-h {
+   rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO _pull_none>;
+   };
+
+   pcie2x1l2_pins: pcie2x1l2-pins {
+   rockchip,pins = <3 RK_PC7 4 _pull_none>,
+   <3 RK_PD0 4 _pull_none>;
+   };
+   };
+
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO _pull_none>;
-- 
2.34.1

[PATCH resend v3 1/3] ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY

From: Joseph Chen 

Add the node for PCIe 2x1l 2 device together with the corresponding
combphy.

Signed-off-by: Joseph Chen 
[eugen.hris...@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev 
[jo...@kwiboo.se: adapt to kernel node]
Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3588s-u-boot.dtsi | 77 
 1 file changed, 77 insertions(+)

diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 922cae3f0921..4fdf97ccac44 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "rockchip-u-boot.dtsi"
+#include 
 
 / {
dmc {
@@ -58,6 +59,11 @@
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
 
+   pipe_phy0_grf: syscon@fd5bc000 {
+   compatible = "rockchip,pipe-phy-grf", "syscon";
+   reg = <0x0 0xfd5bc000 0x0 0x100>;
+   };
+
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
 "simple-mfd";
@@ -104,6 +110,61 @@
};
};
 
+   pcie2x1l2: pcie@fe19 {
+   compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x40 0x4f>;
+   clocks = < ACLK_PCIE_1L2_MSTR>, < ACLK_PCIE_1L2_SLV>,
+< ACLK_PCIE_1L2_DBI>, < PCLK_PCIE_1L2>,
+< CLK_PCIE_AUX4>, < CLK_PCIE1L2_PIPE>;
+   clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+   device_type = "pci";
+   interrupts = ,
+,
+,
+,
+;
+   interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 _intc 0>,
+   <0 0 0 2 _intc 1>,
+   <0 0 0 3 _intc 2>,
+   <0 0 0 4 _intc 3>;
+   linux,pci-domain = <4>;
+   num-ib-windows = <8>;
+   num-ob-windows = <8>;
+   num-viewport = <4>;
+   max-link-speed = <2>;
+   msi-map = <0x4000  0x4000 0x1000>;
+   num-lanes = <1>;
+   phys = <_ps PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy";
+   power-domains = < RK3588_PD_PCIE>;
+   ranges = <0x0100 0x0 0xf410 0x0 0xf410 0x0 
0x0010>,
+<0x0200 0x0 0xf420 0x0 0xf420 0x0 
0x00e0>,
+<0x0300 0x0 0x4000 0xa 0x 0x0 
0x4000>;
+   reg = <0xa 0x4100 0x0 0x0040>,
+ <0x0 0xfe19 0x0 0x0001>,
+ <0x0 0xf400 0x0 0x0010>;
+   reg-names = "dbi", "apb", "config";
+   resets = < SRST_PCIE4_POWER_UP>, < SRST_P_PCIE4>;
+   reset-names = "pcie", "periph";
+   rockchip,pipe-grf = <_grf>;
+   status = "disabled";
+
+   pcie2x1l2_intc: legacy-interrupt-controller {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-parent = <>;
+   interrupts = ;
+   };
+   };
+
otp: nvmem@fecc {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc 0x0 0x400>;
@@ -121,6 +182,22 @@
reg = <0x0 0xfe378000 0x0 0x200>;
status = "disabled";
};
+
+   combphy0_ps: phy@fee0 {
+   compatible = "rockchip,rk3588-naneng-combphy";
+   reg = <0x0 0xfee0 0x0 0x100>;
+   #phy-cells = <1>;
+   clocks = < CLK_REF_PIPE_PHY0>, < 
PCLK_PCIE_COMBO_PIPE_PHY0>,
+< PCLK_PHP_ROOT>;
+   clock-names = "refclk", "apbclk", "phpclk";
+   assigned-clocks = < CLK_REF_PIPE_PHY0>;
+   assigned-clock-rates = <1>;
+   resets = < SRST_P_PCIE2_PHY0>, < SRST_REF_PIPE_PHY0>;
+   reset-names = "combphy-apb", "combphy";
+   rockchip,pipe-grf = <_grf>;
+   rockchip,pipe-phy-grf = <_phy0_grf>;
+   status = "disabled";
+   };
 };
 
  {
-- 
2.34.1

Re: [PATCH v6] configs: rockchip: rock5b-rk3588: enable USB and regulators


Hi Eugen,

Applied, thanks.


- Kever

On 2023/5/17 17:21, Eugen Hristev wrote:

Enable USB command, USB drivers, PHY and regulators, for USB host
operations.

Reviewed-by: Kever Yang 
Signed-off-by: Eugen Hristev 
---
Changes in v6:
- removed accidentaly added line '+# CONFIG_BINMAN_FDT is not set'


  configs/rock5b-rk3588_defconfig | 17 +
  1 file changed, 17 insertions(+)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index d3136ac850fe..19b5e9e4d44d 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -41,7 +41,9 @@ CONFIG_SPL_STACK_R=y
  CONFIG_SPL_ATF=y
  CONFIG_CMD_GPT=y
  CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
  # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
  # CONFIG_SPL_DOS_PARTITION is not set
  CONFIG_SPL_OF_CONTROL=y
  CONFIG_OF_LIVE=y
@@ -62,10 +64,25 @@ CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
  CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
  CONFIG_PWM_ROCKCHIP=y
  CONFIG_SPL_RAM=y
  CONFIG_BAUDRATE=150
  CONFIG_DEBUG_UART_SHIFT=2
  CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
  CONFIG_ERRNO_STR=y

Re: [PATCH 00/14] rockchip: rk35xx: Update defconfigs and enable boot from SPI NOR flash


On 5/17/23 05:20, Kever Yang wrote:

Hi Jonas,

On 2023/5/10 14:48, Jonas Karlman wrote:

Looks like the following two commits in your enablement efforts tree may
be a source of some of these dependency conflicts.

- rockchip: rk3588-rock-5b: Add spi nor flash node
- ARM: dts: rockchip: rk3588-rock-5b-u-boot: enable SPI flash in SPL

Those commits should come after all your pending series, same/similar
commits are included in this defconfig/spinor series, series that I have
tried to base on top of your series 

I will rebase my series on top of rockchip U-Boot Custodian Tree master
and Eugen's series.

I had some time over and prepared a rebase branch with the following
series from Eugen:

[2/2] reset: rockchip: implement rk3588 lookup table
https://patchwork.ozlabs.org/project/uboot/patch/20230413113646.261415-2-eugen.hris...@collabora.com/

[v5,1/6] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host
https://patchwork.ozlabs.org/project/uboot/list/?series=351534

[v3,1/2] ARM: dts: rk3588-rock-5b-u-boot: add bootph-all to pinctrl 
for sdmmc

https://patchwork.ozlabs.org/project/uboot/list/?series=351078

[v3,1/7] pci: pcie_dw_rockchip: Add rk3588 compatible
https://patchwork.ozlabs.org/project/uboot/list/?series=352596

This patch set will need a rebase due to conflict since 0005.


And on top of those my series:

rockchip: rk35xx: Update defconfigs and enable boot from SPI NOR flash
https://patchwork.ozlabs.org/project/uboot/list/?series=351973
Conflict since 0008 rockchip: rk3568-rock-3a: Enable boot from SPI NOR 
flash


rockchip: Fix eMMC performance regression
https://patchwork.ozlabs.org/project/uboot/list/?series=353826


Conflict for configs/rock-pi-4-rk3399_defconfig in 0004 rockchip: 
rock-pi-4: Use SDMA to boost eMMC performance



Please send the update, maybe after new version "pci: pcie_dw_rockchip: 
Add rk3588 compatible" from Eugen.


I have apply part of these patches for the driver is fine and conflict 
only happen in dts level. Will apply new version


if available.


Hi Kever,

I looked in your branch, and have a few updates:

Can you replace patch ` configs: rockchip: rock5b-rk3588: enable USB and 
regulators` with this new patch I sent (v6), because Jonas pointed out a 
line that was added wrongly. Patch available here:


https://patchwork.ozlabs.org/project/uboot/patch/20230517092126.101245-1-eugen.hris...@collabora.com/

I am also rebasing the pci express patches on top of your branch and 
resending .


Thanks !




Thanks,

- Kever



I think that should be the correct apply order.

The rebase branch can be found at:
https://github.com/Kwiboo/u-boot-rockchip/commits/rebase-20230510a

I will hold off on sending out my v2 series until Eugen have had a
chance to finalize and send out his series 

[PATCH v6] configs: rockchip: rock5b-rk3588: enable USB and regulators

Enable USB command, USB drivers, PHY and regulators, for USB host
operations.

Reviewed-by: Kever Yang 
Signed-off-by: Eugen Hristev 
---
Changes in v6:
- removed accidentaly added line '+# CONFIG_BINMAN_FDT is not set'


 configs/rock5b-rk3588_defconfig | 17 +
 1 file changed, 17 insertions(+)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index d3136ac850fe..19b5e9e4d44d 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -41,7 +41,9 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
@@ -62,10 +64,25 @@ CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_ERRNO_STR=y
-- 
2.34.1

Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model

2023-05-17 Thread Andre Przywara

On Wed, 17 May 2023 01:43:12 +0100
Andre Przywara  wrote:

+Maksim, as he was interested in the U-Boot series as well and had some
plans for SPI-NOR booting, IIUC.

Cheers,
Andre

> On Tue, 16 May 2023 17:53:38 -0600
> Sam Edwards  wrote:
> 
> Hi Sam,
> 
> > On 5/16/23 15:08, Andre Przywara wrote:  
> > > This whole memory map is somewhat of a legacy. Apart from a few
> > > addresses for the SPL needs we shouldn't have those defines at all.
> > > Some symbols are needed because there are other macros using them,
> > > although these then are eventually unused.
> > > I have some patches to remove most of the symbols, and patch 14/17
> > > demonstrates some idea how to pin this down to what's really needed.
> > > 
> > > For this particular case: this was copied from the H6 memory map, some
> > > addresses are just plain wrong for the D1 family. I will try to remove
> > > them as much as possible, leaving only the ones needed in.
> > 
> > I see - the only "tangible" concern I had was the access to 
> > prcm->res_cal_ctrl done in
> > arch/arm/mach-sunxi/clock_sun50i_h6.c:clock_init_safe
> > 
> > This doesn't appear to upset the silicon but also doesn't seem necessary 
> > either -- and with how tight of a memory footprint SPL has to fit into,  
> 
> What's the particular concern here? Compared to the A64 we are pretty
> cool: it's Thumb2 code and we are at around 27KB, at least with my
> toolchain. And I haven't tried, but I am pretty sure the BROM
> loads more than 32K, as it does on the H6 and H616 already. The U-Boot
> build system and the code already supports this - we rely on this for
> the H616 - so we can lift the limit anytime, if really needed.
> 
> > I wanted to check whether this was just something undocumented or dead 
> > code that needed to be removed. It sounds like it's mostly the latter.  
> 
> I haven't checked if the vendor boot0 does this. I am pretty sure there
> is a PRCM block, it's just regularly not mentioned in the manuals.
> 
> > > So where did you see problems? If you would (wrongly) reference
> > > PortL somewhere in SPL GPIO code, it would use a wrong pointer, but at
> > > least the code would still compile fine, wouldn't it?
> > 
> > The specific patch I had to apply (to arch/arm/mach-sunxi/board.c) was:
> >  /* Update PIO power bias configuration by copy hardware 
> > detected value */
> >  val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> >  writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> > -   val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> > -   writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> > +   if (SUNXI_R_PIO_BASE) {
> > +   val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> > +   writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> > +   }  
> 
> Ah, I see, I indeed missed that. We seem to define all symbols anyway,
> so we can even lose the #ifdef and use proper if's here.
> Will incorporate that in the next drop.
> 
> > With SUNXI_R_PIO_BASE being 0, this was actually attempting to write to 
> > BROM. This might also be something that doesn't really upset the 
> > silicon, though: my debug environment is a concolic emulator I quickly 
> > hacked up to trace MMIO accesses, and it flagged the write to BROM as an 
> > error. It was easier to patch the SPL than to have the emulator ignore 
> > the error (and verify that the T113 was cool with it).  
> 
> Ah yeah, the Allwinner interconnect is pretty relaxed about those
> things: accesses to addresses with no device behind them are usually
> ignored (RAZ/WI), where other platform might throw an external abort.
> Writes to ROM areas are ignored as well.
> 
> > Since this kind of extraneous/erroneous init code tends to remain 
> > undetected when the symbols they need are dummied-out like this, I 
> > figured I'd give a nudge in the direction of instead *removing* the 
> > symbols where appropriate and fixing whatever breaks -- especially since 
> > we really need to be thrifty about SPL size. But that might also be 
> > something that happens in a later cleanup pass when the patchset is 
> > being prepared for upstream inclusion. :)
> >   
> > > P.S. Could you try the github post? Then compiled and booted fine for
> > > me, and includes the DRAM code as well now:
> > > https://github.com/apritzel/u-boot/commits/t113s-mq-r-WIP
> > 
> > Ooh, more up-to-date code, thanks for the link! I'll switch to using 
> > this instead going forward. My pulls from that branch might be 
> > relatively infrequent  
> 
> Don't worry, I won't push to this anymore.
> 
> > since I'm also working on some patches for better 
> > Clang compatibility concurrent with the efforts here. Is this email 
> > thread a good venue for feedback against that branch or would you prefer 
> > that I use GitHub issues instead?  
> 
> Please use this thread here, if you find something still wrong in the
> branch. I just

[PATCH 4/6] video: zynqmp: Driver for Xilinx ZynqMP DisplayPort Subsystem

From: Venkatesh Yadav Abbarapu 

The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort
Subsystem. It includes a buffer manager, blender, an audio mixer and a
DisplayPort source controller (transmitter). The DisplayPort controller can
source data from memory (non-live input) or the stream (live input). The
DisplayPort controller is responsible for managing the link and physical
layer functionality. The controller packs audio/video data into transfer
units and sends them over the main link. The link rate and lane counts can
be selected based on the application bandwidth requirements. The
DisplayPort pipeline consists of the DisplayPort direct memory access (DMA)
for fetching data from memory. The DisplayPort DMA controller (DPDMA)
supports up to six input channels as non-live input.

This driver supports the DisplayPort Subsystem and implements
1)640x480 resolution
2)RGBA 32bpp format
3)DPDMA channel 3 for Graphics
4)Non-live input
5)Fixed 5.4G link rate
6)Tested on ZCU102 board

There will be additional work to configure GT lines based on DT, higher
resolutions, support for more compressed video formats, spliting code to
more files, add support for EDID, audio support, using clock framework for
all clocks and in general code clean up.

Codevelop-by: Michal Simek 
Signed-off-by: Michal Simek 
Signed-off-by: Venkatesh Yadav Abbarapu 
---

 MAINTAINERS |1 +
 drivers/video/zynqmp/zynqmp_dpsub.c | 2197 ++-
 drivers/video/zynqmp/zynqmp_dpsub.h |  676 +
 3 files changed, 2855 insertions(+), 19 deletions(-)
 create mode 100644 drivers/video/zynqmp/zynqmp_dpsub.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c8f72e9ec6a2..b0f0390a68c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -755,6 +755,7 @@ F:  drivers/spi/zynq_qspi.c
 F: drivers/spi/zynq_spi.c
 F: drivers/timer/cadence-ttc.c
 F: drivers/video/seps525.c
+F: drivers/video/zynqmp/
 F: drivers/watchdog/cdns_wdt.c
 F: include/zynqmppl.h
 F: include/zynqmp_firmware.h
diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c 
b/drivers/video/zynqmp/zynqmp_dpsub.c
index 4ead663cd59f..c287b475a8d7 100644
--- a/drivers/video/zynqmp/zynqmp_dpsub.c
+++ b/drivers/video/zynqmp/zynqmp_dpsub.c
@@ -1,53 +1,2212 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2021 Xilinx Inc.
+ * Copyright (C) 2021 - 2022, Xilinx Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Xilinx displayport(DP) Tx Subsytem driver
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
+#include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "zynqmp_dpsub.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Maximum supported resolution */
+#define WIDTH  640
+#define HEIGHT 480
+
+static struct dp_dma dp_dma;
+static struct dp_dma_descriptor cur_desc __aligned(256);
+
+static void dma_init_video_descriptor(struct udevice *dev)
+{
+   struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+   struct dp_dma_frame_buffer *frame_buffer = _sub->frame_buffer;
+
+   cur_desc.control = DPDMA_DESC_PREAMBLE | DPDMA_DESC_IGNR_DONE |
+  DPDMA_DESC_LAST_FRAME;
+   cur_desc.dscr_id = 0;
+   cur_desc.xfer_size = frame_buffer->size;
+   cur_desc.line_size_stride = ((frame_buffer->stride >> 4) <<
+DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT) |
+(frame_buffer->line_size);
+   cur_desc.addr_ext = (((u32)(frame_buffer->address >>
+DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) <<
+DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
+(upper_32_bits((u64)_desc)));
+   cur_desc.next_desr = lower_32_bits((u64)_desc);
+   cur_desc.src_addr = lower_32_bits((u64)gd->fb_base);
+}
+
+static void dma_set_descriptor_address(struct udevice *dev)
+{
+   struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+   flush_dcache_range((u64)_desc,
+  ALIGN(((u64)_desc + sizeof(cur_desc)),
+CONFIG_SYS_CACHELINE_SIZE));
+   writel(upper_32_bits((u64)_desc), dp_sub->dp_dma->base_addr +
+  DPDMA_CH3_DSCR_STRT_ADDRE);
+   writel(lower_32_bits((u64)_desc), dp_sub->dp_dma->base_addr +
+  DPDMA_CH3_DSCR_STRT_ADDR);
+}
+
+static void dma_setup_channel(struct udevice *dev)
+{
+   dma_init_video_descriptor(dev);
+   dma_set_descriptor_address(dev);
+}
 
-#define WIDTH  640
-#define HEIGHT 480
+static void dma_set_channel_state(struct udevice *dev)
+{
+   u32 mask = 0, regval = 0;
+   struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+   mask = DPDMA_CH_CNTL_EN_MASK | DPDMA_CH_CNTL_PAUSE_MASK;
+   regval = DPDMA_CH_CNTL_EN_MASK;
+
+   clrsetbits_le32(dp_sub->dp_dma->base_addr + DPDMA_CH3_CNTL,
+

[PATCH 6/6] video: zynqmp: Enable 1024x768 resolution

Add support for 1024x768 60p resolution and set it up this resolution by
default. This resolution is still able to use only one GT line. But for
example 800x600 60p has some issues with settings. That's why extend this
table by tested resolutions.

Signed-off-by: Michal Simek 
---

 drivers/video/zynqmp/zynqmp_dpsub.c | 6 +++---
 drivers/video/zynqmp/zynqmp_dpsub.h | 6 +-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c 
b/drivers/video/zynqmp/zynqmp_dpsub.c
index c287b475a8d7..def4dcf6261a 100644
--- a/drivers/video/zynqmp/zynqmp_dpsub.c
+++ b/drivers/video/zynqmp/zynqmp_dpsub.c
@@ -27,8 +27,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Maximum supported resolution */
-#define WIDTH  640
-#define HEIGHT 480
+#define WIDTH  1024
+#define HEIGHT 768
 
 static struct dp_dma dp_dma;
 static struct dp_dma_descriptor cur_desc __aligned(256);
@@ -1995,7 +1995,7 @@ static void init_run_config(struct udevice *dev)
struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
 
dp_sub->dp_dma   = _dma;
-   dp_sub->video_mode   = VIDC_VM_640x480_60_P;
+   dp_sub->video_mode   = VIDC_VM_1024x768_60_P;
dp_sub->bpc  = VIDC_BPC_8;
dp_sub->color_encode = DP_CENC_RGB;
dp_sub->use_max_cfg_caps = 1;
diff --git a/drivers/video/zynqmp/zynqmp_dpsub.h 
b/drivers/video/zynqmp/zynqmp_dpsub.h
index d2a6f1f4c7c8..7d2737e31aac 100644
--- a/drivers/video/zynqmp/zynqmp_dpsub.h
+++ b/drivers/video/zynqmp/zynqmp_dpsub.h
@@ -9,6 +9,7 @@
 
 enum video_mode {
VIDC_VM_640x480_60_P = 0,
+   VIDC_VM_1024x768_60_P = 1,
 };
 
 enum {
@@ -644,7 +645,7 @@ struct zynqmp_dpsub_priv {
 #define VIDEO_REF_CTRL_DIVISOR0_SHIFT  8
 #define PSS_REF_CLK0
 #define FPD_CTRL_OFFSET
12
-#define VIDC_VM_NUM_SUPPORTED  1
+#define VIDC_VM_NUM_SUPPORTED  2
 
 static const u32 vs[4][4] = {
{ 0x2a, 0x27, 0x24, 0x20 },
@@ -664,6 +665,9 @@ const struct video_timing_mode 
vidc_video_timing_modes[VIDC_VM_NUM_SUPPORTED] =
{ VIDC_VM_640x480_60_P, "640x480@60Hz", VIDC_FR_60HZ,
{640, 16, 96, 48, 800, 0,
 480, 10, 2, 33, 525, 0, 0, 0, 0, 0} },
+   { VIDC_VM_1024x768_60_P, "1024x768@60Hz", VIDC_FR_60HZ,
+   {1024, 24, 136, 160, 1344, 0,
+768, 3, 6, 29, 806, 0, 0, 0, 0, 0} },
 };
 
 const struct av_buf_vid_attribute avbuf_supported_formats[] = {
-- 
2.36.1

[PATCH 5/6] xilinx: zynqmp: Enable the vidconsole by default

From: Venkatesh Yadav Abbarapu 

Add the vidconsole flags for video serial console.

Signed-off-by: Venkatesh Yadav Abbarapu 
Signed-off-by: Michal Simek 
---

 include/configs/xilinx_zynqmp.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 011f0034c509..995427db63c8 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -60,6 +60,9 @@
"scriptaddr=0x2000\0" \
"ramdisk_addr_r=0x0210\0" \
"script_size_f=0x8\0" \
+   "stdin=serial\0" \
+   "stdout=serial,vidconsole\0" \
+   "stderr=serial,vidconsole\0" \
 
 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
 # define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
-- 
2.36.1

[PATCH 3/6] video: move zynqmp files to subdirectory

From: Venkatesh Yadav Abbarapu 

Place zynqmp files and headers in custom driver subdirectory.

Signed-off-by: Venkatesh Yadav Abbarapu 
Signed-off-by: Michal Simek 
---

 drivers/video/Kconfig | 9 +
 drivers/video/Makefile| 2 +-
 drivers/video/zynqmp/Kconfig  | 8 
 drivers/video/zynqmp/Makefile | 5 +
 drivers/video/{ => zynqmp}/zynqmp_dpsub.c | 0
 5 files changed, 15 insertions(+), 9 deletions(-)
 create mode 100644 drivers/video/zynqmp/Kconfig
 create mode 100644 drivers/video/zynqmp/Makefile
 rename drivers/video/{ => zynqmp}/zynqmp_dpsub.c (100%)

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1e2f4e6de4a5..49762950719e 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -740,14 +740,7 @@ config VIDEO_SEPS525
  Enable support for the Syncoam PM-OLED display driver (RGB 160x128).
  Currently driver is supporting only SPI interface.
 
-config VIDEO_ZYNQMP_DPSUB
-   bool "Enable video support for ZynqMP Display Port"
-   depends on ZYNQMP_POWER_DOMAIN
-   help
- Enable support for Xilinx ZynqMP Display Port. Currently this file
- is used as placeholder for driver. The main reason is to record
- compatible string and calling power domain driver.
-
+source "drivers/video/zynqmp/Kconfig"
 source "drivers/video/nexell/Kconfig"
 
 config CONSOLE_SCROLL_LINES
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9a53cd141875..f99d7e3c3d90 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -73,7 +73,7 @@ obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
 obj-$(CONFIG_VIDEO_SEPS525) += seps525.o
-obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp_dpsub.o
+obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp/
 
 obj-y += bridge/
 obj-y += sunxi/
diff --git a/drivers/video/zynqmp/Kconfig b/drivers/video/zynqmp/Kconfig
new file mode 100644
index ..b35cd1fb3429
--- /dev/null
+++ b/drivers/video/zynqmp/Kconfig
@@ -0,0 +1,8 @@
+
+config VIDEO_ZYNQMP_DPSUB
+   bool "Enable video support for ZynqMP Display Port"
+   depends on ZYNQMP_POWER_DOMAIN
+   help
+   Enable support for Xilinx ZynqMP Display Port. Currently this file
+   is used as placeholder for driver. The main reason is to record
+   compatible string and calling power domain driver.
diff --git a/drivers/video/zynqmp/Makefile b/drivers/video/zynqmp/Makefile
new file mode 100644
index ..cc057f53560d
--- /dev/null
+++ b/drivers/video/zynqmp/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2023, Advanced Micro Devices, Inc.
+
+obj-y += zynqmp_dpsub.o
diff --git a/drivers/video/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c
similarity index 100%
rename from drivers/video/zynqmp_dpsub.c
rename to drivers/video/zynqmp/zynqmp_dpsub.c
-- 
2.36.1

[PATCH 2/6] video: bmp: Support rgba8888 pixel format

Adding the support for RGBA format for BMP decoding.

Signed-off-by: Michal Simek 
Signed-off-by: Venkatesh Yadav Abbarapu 
---

 drivers/video/video_bmp.c | 36 
 1 file changed, 36 insertions(+)

diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index 47e52c4f69c9..45f003c8251a 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -42,6 +42,18 @@ static u32 get_bmp_col_x2r10g10b10(struct 
bmp_color_table_entry *cte)
(cte->blue << 2U));
 }
 
+/**
+ * get_bmp_col_rgba() - Convert a colour-table entry into a rgba pixel 
value
+ *
+ * Return: value to write to the rgba frame buffer for this palette entry
+ */
+static u32 get_bmp_col_rgba(struct bmp_color_table_entry *cte)
+{
+   return ((cte->red) |
+   (cte->green << 8U) |
+   (cte->blue << 16U) | 0xff << 24U);
+}
+
 /**
  * write_pix8() - Write a pixel from a BMP image into the framebuffer
  *
@@ -71,6 +83,8 @@ static void write_pix8(u8 *fb, uint bpix, enum video_format 
eformat,
*fb++ = cte->blue;
} else if (eformat == VIDEO_X2R10G10B10) {
*(u32 *)fb = get_bmp_col_x2r10g10b10(cte);
+   } else if (eformat == VIDEO_RGBA) {
+   *(u32 *)fb = get_bmp_col_rgba(cte);
} else {
*fb++ = cte->blue;
*fb++ = cte->green;
@@ -382,6 +396,17 @@ int video_bmp_display(struct udevice *dev, ulong 
bmp_image, int x, int y,
*fb++ = (pix >> 8) & 0xff;
*fb++ = (pix >> 16) & 0xff;
*fb++ = pix >> 24;
+   } else if (eformat == VIDEO_RGBA) {
+   u32 pix;
+
+   pix = *bmap++ << 8U; /* blue */
+   pix |= *bmap++ << 16U; /* green 
*/
+   pix |= *bmap++ << 24U; /* red */
+
+   *fb++ = (pix >> 24) & 0xff;
+   *fb++ = (pix >> 16) & 0xff;
+   *fb++ = (pix >> 8) & 0xff;
+   *fb++ = 0xff;
} else {
*fb++ = *bmap++;
*fb++ = *bmap++;
@@ -409,6 +434,17 @@ int video_bmp_display(struct udevice *dev, ulong 
bmp_image, int x, int y,
*fb++ = (pix >> 8) & 0xff;
*fb++ = (pix >> 16) & 0xff;
*fb++ = pix >> 24;
+   } else if (eformat == VIDEO_RGBA) {
+   u32 pix;
+
+   pix = *bmap++ << 8U; /* blue */
+   pix |= *bmap++ << 16U; /* green 
*/
+   pix |= *bmap++ << 24U; /* red */
+   bmap++;
+   *fb++ = (pix >> 24) & 0xff;
+   *fb++ = (pix >> 16) & 0xff;
+   *fb++ = (pix >> 8) & 0xff;
+   *fb++ = 0xff; /* opacity */
} else {
*fb++ = *bmap++;
*fb++ = *bmap++;
-- 
2.36.1

[PATCH 1/6] video: Add support for RGBA8888 format

Add support for RGBA 32bpp format where pixels are picked in
32-bit integers, where the colors are stored in memory such that
R is at lowest address, G after that, B after that, and A last.

Signed-off-by: Michal Simek 
Signed-off-by: Venkatesh Yadav Abbarapu 
---

 drivers/video/video-uclass.c | 10 --
 include/video.h  |  1 +
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 8396bdfb11e1..1b66a8061a74 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -220,14 +220,20 @@ u32 video_index_to_colour(struct video_priv *priv, 
unsigned int idx)
break;
case VIDEO_BPP32:
if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
-   if (priv->format == VIDEO_X2R10G10B10)
+   switch (priv->format) {
+   case VIDEO_X2R10G10B10:
return (colours[idx].r << 22) |
   (colours[idx].g << 12) |
   (colours[idx].b <<  2);
-   else
+   case VIDEO_RGBA:
+   return (colours[idx].r << 24) |
+  (colours[idx].g << 16) |
+  (colours[idx].b << 8) | 0xff;
+   default:
return (colours[idx].r << 16) |
   (colours[idx].g <<  8) |
   (colours[idx].b <<  0);
+   }
}
break;
default:
diff --git a/include/video.h b/include/video.h
index 29c4f51efb08..03434a81234f 100644
--- a/include/video.h
+++ b/include/video.h
@@ -64,6 +64,7 @@ enum video_log2_bpp {
 
 enum video_format {
VIDEO_UNKNOWN,
+   VIDEO_RGBA,
VIDEO_X8B8G8R8,
VIDEO_X8R8G8B8,
VIDEO_X2R10G10B10,
-- 
2.36.1

[PATCH 0/6] video: zynqmp: Add support for ZynqMP DP

Hi,

this series is adding initial support for Diplay port. As of today
it is working on fixed configuration but working on making it more flexible
to be able to fully configure it via DT only.

Thanks,
Michal


Michal Simek (3):
  video: Add support for RGBA format
  video: bmp: Support rgba pixel format
  video: zynqmp: Enable 1024x768 resolution

Venkatesh Yadav Abbarapu (3):
  video: move zynqmp files to subdirectory
  video: zynqmp: Driver for Xilinx ZynqMP DisplayPort Subsystem
  xilinx: zynqmp: Enable the vidconsole by default

 MAINTAINERS |1 +
 drivers/video/Kconfig   |9 +-
 drivers/video/Makefile  |2 +-
 drivers/video/video-uclass.c|   10 +-
 drivers/video/video_bmp.c   |   36 +
 drivers/video/zynqmp/Kconfig|8 +
 drivers/video/zynqmp/Makefile   |5 +
 drivers/video/zynqmp/zynqmp_dpsub.c | 2225 +++
 drivers/video/zynqmp/zynqmp_dpsub.h |  680 
 drivers/video/zynqmp_dpsub.c|   66 -
 include/configs/xilinx_zynqmp.h |3 +
 include/video.h |1 +
 12 files changed, 2969 insertions(+), 77 deletions(-)
 create mode 100644 drivers/video/zynqmp/Kconfig
 create mode 100644 drivers/video/zynqmp/Makefile
 create mode 100644 drivers/video/zynqmp/zynqmp_dpsub.c
 create mode 100644 drivers/video/zynqmp/zynqmp_dpsub.h
 delete mode 100644 drivers/video/zynqmp_dpsub.c

-- 
2.36.1

Re: mmc: Read eMMC partition access bits before card reset

2023-05-17 Thread Stefan Roese


Hi Pali,

On 5/17/23 00:30, Pali Rohár wrote:

On Tuesday 16 May 2023 14:56:46 Tom Rini wrote:

On Tue, May 16, 2023 at 08:52:23PM +0200, Pali Rohár wrote:

On Tuesday 16 May 2023 11:36:20 Tom Rini wrote:

On Tue, May 16, 2023 at 09:04:27AM +0200, Pali Rohár wrote:

On Sunday 07 May 2023 22:36:16 Pali Rohár wrote:

On Sunday 07 May 2023 12:45:11 Tom Rini wrote:

On Sun, May 07, 2023 at 04:56:04PM +0200, Pali Rohár wrote:

On Sunday 07 May 2023 10:40:44 Tom Rini wrote:

On Sun, May 07, 2023 at 04:01:04PM +0200, Pali Rohár wrote:

On Sunday 07 May 2023 09:54:52 Tom Rini wrote:

On Fri, May 05, 2023 at 09:37:10PM +0200, Pali Rohár wrote:

On Wednesday 03 May 2023 13:14:56 Tom Rini wrote:

On Wed, May 03, 2023 at 11:18:39AM +0200, Stefan Roese wrote:


Hi Tom,

please pull this next batch of mostly Marvell related patches:


NAK.  With commit:
commit 461fa17970de418a93832f734a595031c0b72128
Author: Pali Rohár 
Date:   Thu Apr 13 22:57:48 2023 +0200

 mmc: Read eMMC partition access bits before card reset
 
 eMMC specification in section "Access partitions" says that all reset

 events will restore the access bits in PARTITION_CONFIG CSD register to
 default User Data Area value (0b000).
 
 So read partition access bits from PARTITION_CONFIG CSD register before

 issuing card reset. This allows SPL/U-Boot to get information which eMMC
 partition was in use before SPL/U-Boot was booted. For some platforms this
 is the way how to determinate boot partition from which BootROM loaded SPL.
 
 Signed-off-by: Pali Rohár 


My am335x_evm now fails to boot with:

U-Boot SPL 2023.07-rc1-00021-g461fa17970de (May 03 2023 - 13:10:10 -0400)
Trying to boot from MMC1
omap_hsmmc_send_cmd: timedout waiting on cmd inhibit to clear
spl: mmc init failed with error: -110
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

I can provide more details / test patches as needed.

--
Tom


I do not know what to do with this... The only idea is to hide this code
behind CONFIG symbol and enable it only for mvebu. For example by this:


Well, maybe the problem is we're trying this on uSD cards? The failure I
reported was uSD and not eMMC.


Maybe it is that reason. Problem is that at this stage we do not know if
card is SD or MMC.

Martin, can you check if booting from SD card is working fine on mvebu
clearfog?


I see a failure with this commit on
rpi_3_32b, also from uSD boot.  This time it's:
Loading Environment from FAT... fsm 0, hsts 
fsm 0, hsts 
...

once in U-Boot itself.  Going to the commit prior to the above one and
the board is fine again.

--
Tom


Immediately after that "problematic code" is card reset function. So
another reason for failure is that card reset functionality does not
work correctly on your board / platform.


Well, we're at two different platforms and controllers that this change
breaks things on, so I'm not sure where the fault is exactly.  My
mx6cuboxi is still fine booting from uSD.  Another TI platform from the
same general era as am335x fails the same way (not a surprise), amlogic
libretech-cc is fine, pine64_plus is fine, and my newer TI platforms are
also fine with this.  So maybe the Kconfig is fine, but we just want
default y, default n if ARCH_OMAP2PLUS || ARCH_BCM283X (the TI platforms
that work are not ARCH_OMAP2PLUS).

--
Tom


And do you see this problem in SPL or in proper U-Boot?

If omap2plus is problematic then I can do tests on Nokia N900 or at its
qemu emulated version (to which can be attached gdb). But Nokia N900 is
without SPL.



OK, so on am335x_evm mine is setup so I can X/Y modem boot it before it
tries uSD.  In this case, full U-Boot also fails:
Loading Environment from FAT... omap_hsmmc_send_cmd: timedout waiting on
cmd inhibit to clear
** Bad device specification mmc 0 **

Note that N900 in QEMU passes, but I suspect that's a matter of the
emulator not being faithful to some undocumented bug/feature of the
chipset and that it would also fail like this on real HW or that we
aren't relying on MMC in such a way that the QEMU tests actually report
failure.  When I booted the above, it was not a lock-up since we can
continue on in this case, rather than failure to load U-Boot itself.


--
Tom


Ok, I have tested it on Nokia N900 HW and interesting is that SD card is
also working fine. But its initialization is slower and prints warning:

  omap_hsmmc_send_cmd: timeout waiting on cmd inhibit to clear


Ok, so what with it?


Seems like this change is a real bad idea to introduce on ARCH_OMAP2PLUS
platforms, and probably ARCH_BCM283X too, so rework with a Kconfig
option that defaults to on except for the above as I suggested?

--
Tom


Ok, patch is on the list... I'm curious if patch stay here on the list
more than one year like some other...


I mean, since I asked you to spin a new patch and you posted a patch on
top of the previously rejected one, someone will need to pick it up and
fold it

[PATCH] mmc: zynq: Sync with upstream DT binding

Versal NET is not in production yet that's why no need to keep backward
compatible with previously used compatible string.

Signed-off-by: Michal Simek 
Link: 
https://lore.kernel.org/r/20230403102551.3763054-2-sai.krishna.potth...@amd.com
---

 drivers/mmc/zynq_sdhci.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index e44868aaec51..e779251ce34f 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -873,7 +873,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host 
*host)
if (ret)
return ret;
} else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
-  device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
+  device_is_compatible(dev, "xlnx,versal-net-emmc")) {
if (mmc->clock >= MIN_PHY_CLK_HZ)
if (iclk_phase == 
VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
iclk_phase = 
VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL;
@@ -948,7 +948,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev)
}
 
if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
-   device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
+   device_is_compatible(dev, "xlnx,versal-net-emmc")) {
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
clk_data->clk_phase_in[i] = 
versal_net_emmc_iclk_phases[i];
clk_data->clk_phase_out[i] = 
versal_net_emmc_oclk_phases[i];
@@ -1102,7 +1102,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
}
}
 #endif
-   if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
+   if (device_is_compatible(dev, "xlnx,versal-net-emmc"))
priv->internal_phy_reg = true;
 
ret = clk_get_by_index(dev, 0, );
@@ -1136,7 +1136,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
host->quirks |= SDHCI_QUIRK_NO_1_8_V;
 
if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) &&
-   device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
+   device_is_compatible(dev, "xlnx,versal-net-emmc"))
host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400;
 
plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
@@ -1219,7 +1219,7 @@ static int arasan_sdhci_bind(struct udevice *dev)
 
 static const struct udevice_id arasan_sdhci_ids[] = {
{ .compatible = "arasan,sdhci-8.9a" },
-   { .compatible = "xlnx,versal-net-5.1-emmc" },
+   { .compatible = "xlnx,versal-net-emmc" },
{ }
 };
 
-- 
2.36.1

[PATCH] arm64: versal-net: Add support for SPP production version

Production version restarting platform version field from 0 that's why add
new calculation to be able to use different DT for these platforms.
Requested DT names for production silicons for IPP/SPP and EMU platform are
versal-net-ipp-rev2.0.dts and versal-net-emu-rev2.0.dts.
If platform version increase numbers revision can be even higher.
As of today platform version is 2 that's why expected is rev2.2.

Signed-off-by: Michal Simek 
---

 .../mach-versal-net/include/mach/hardware.h   |  1 +
 board/xilinx/versal-net/board.c   | 35 +--
 2 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h 
b/arch/arm/mach-versal-net/include/mach/hardware.h
index c5e4e22040e2..3de9d439bc5c 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -44,6 +44,7 @@ struct iou_scntrs_regs {
 #define PMC_TAP_VERSION(PMC_TAP + 0x4)
 # define PMC_VERSION_MASK  GENMASK(7, 0)
 # define PS_VERSION_MASK   GENMASK(15, 8)
+# define PS_VERSION_PRODUCTION 0x20
 # define RTL_VERSION_MASK  GENMASK(23, 16)
 # define PLATFORM_MASK GENMASK(27, 24)
 # define PLATFORM_VERSION_MASK GENMASK(31, 28)
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 6724c7290f8e..0e1321734f32 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -74,32 +74,45 @@ char *soc_name_decode(void)
 
 bool soc_detection(void)
 {
-   u32 version;
+   u32 version, ps_version;
 
version = readl(PMC_TAP_VERSION);
platform_id = FIELD_GET(PLATFORM_MASK, version);
+   ps_version = FIELD_GET(PS_VERSION_MASK, version);
 
debug("idcode %x, version %x, usercode %x\n",
  readl(PMC_TAP_IDCODE), version,
  readl(PMC_TAP_USERCODE));
 
-   debug("pmc_ver %lx, ps version %lx, rtl version %lx\n",
+   debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
  FIELD_GET(PMC_VERSION_MASK, version),
- FIELD_GET(PS_VERSION_MASK, version),
+ ps_version,
  FIELD_GET(RTL_VERSION_MASK, version));
 
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
 
if (platform_id == VERSAL_NET_SPP ||
platform_id == VERSAL_NET_EMU) {
-   /*
-* 9 is diff for
-* 0 means 0.9 version
-* 1 means 1.0 version
-* 2 means 1.1 version
-* etc,
-*/
-   platform_version += 9;
+   if (ps_version == PS_VERSION_PRODUCTION) {
+   /*
+* ES1 version ends at 1.9 version where there was +9
+* used because of IPP/SPP conversion. Production
+* version have platform_version started from 0 again
+* that's why adding +20 to continue with the same line.
+* It means the last ES1 version ends at 1.9 version and
+* new PRODUCTION line starts at 2.0.
+*/
+   platform_version += 20;
+   } else {
+   /*
+* 9 is diff for
+* 0 means 0.9 version
+* 1 means 1.0 version
+* 2 means 1.1 version
+* etc,
+*/
+   platform_version += 9;
+   }
}
 
debug("Platform id: %d version: %d.%d\n", platform_id,
-- 
2.36.1

Re: [PATCH 1/5] mtd/spinand: rework detect procedure for different READ_ID operation

2023-05-17 Thread Frieder Schrempf

Hi Michael, hi Dario,

On 15.05.23 23:33, Michael Nazzareno Trimarchi wrote:
> Hi
> 
> Il lun 15 mag 2023, 23:12 Tom Rini  > ha scritto:
> 
> On Tue, May 09, 2023 at 09:09:28AM +0200, Frieder Schrempf wrote:
> > Hi Michael, hi Dario,
> >
> > On 18.04.23 15:46, Frieder Schrempf wrote:
> > > Hi Michael, Dario,
> > >
> > > On 28.03.23 09:57, Frieder Schrempf wrote:
> > >> Hi Michael,
> > >>
> > >> On 10.02.23 12:57, Michael Nazzareno Trimarchi wrote:
> > >>> Hi
> > >>>
> > >>> I will review
> > >>>
> > >>> On Thu, Feb 9, 2023 at 5:52 PM Tom Rini  > wrote:
> > 
> >  On Thu, Feb 09, 2023 at 10:24:47AM +0100, Frieder Schrempf wrote:
> > > Hi,
> > >
> > > On 10.01.23 12:58, Frieder Schrempf wrote:
> > >> From: Mikhail Kshevetskiy  >
> > >>
> > >> Currently there are 3 different variants of read_id
> implementation:
> > >> 1. opcode only. Found in GD5FxGQ4xF.
> > >> 2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
> > >> 3. opcode + 1 dummy byte. Found in other currently
> supported chips.
> > >>
> > >> Original implementation was for variant 1 and let detect
> function
> > >> of chips with variant 2 and 3 to ignore the first byte.
> This isn't
> > >> robust:
> > >>
> > >> 1. For chips of variant 2, if SPI master doesn't keep MOSI low
> > >> during read, chip will get a random id offset, and the
> entire id
> > >> buffer will shift by that offset, causing detect failure.
> > >>
> > >> 2. For chips of variant 1, if it happens to get a devid
> that equals
> > >> to manufacture id of variant 2 or 3 chips, it'll get
> incorrectly
> > >> detected.
> > >>
> > >> This patch reworks detect procedure to address problems
> above. New
> > >> logic do detection for all variants separatedly, in 1-2-3
> order.
> > >> Since all current detect methods do exactly the same id
> matching
> > >> procedure, unify them into core.c and remove detect method from
> > >> manufacture_ops.
> > >>
> > >> This is a rework of Chuanhong Guo  > patch
> > >> submitted to linux kernel
> > >>
> > >> Signed-off-by: Mikhail Kshevetskiy
> mailto:mikhail.kshevets...@iopsys.eu>>
> > >> Signed-off-by: Frieder Schrempf
> mailto:frieder.schre...@kontron.de>>
> > >
> > > +Cc: Jagan, Tom
> > >
> > > Who is supposed to pick up these patches? Some of them have
> been around
> > > for some months (before I resent them).
> > >
> > > There is no maintainer for drivers/mtd/spinand/ and no
> maintainer for
> > > drivers/mtd/ in general.
> > >
> > > In Patchwork Jagan got assigned, but the get_maintainer.pl
>  script didn't
> > > even add him to Cc, of course.
> > >
> > > Any ideas how to proceed?
> > 
> >  We don't have anyone dedicated to that area, yes, sadly. I've
> added
> >  Michael and Dario as they've also been doing mtd-but-not-spi
> work of
> >  late to see if they're interested. Or since you've long been
> working
> >  here, would you like to more formally maintain the area? Thanks!
> > >>>
> > >>> They can come from our tree. I will try to sort out all my
> duties weeked
> > >>
> > >> Any news regarding reviewing/picking these patches?
> > >
> > > Ping!
> > >
> > > Can you please apply these patches, that have been waiting for
> so long?
> >
> > I still can't see this applied anywhere. You already told me to take
> > care of it multiple times. Can you please get it done?
> 
> Yes, I'd really like to see a PR at least vs -next at this point so
> things aren't lost, thanks!
> 
> 
> I think that we pick already it so it will happen.

I can see patch 1/5 of this series in the nand-next tree. What about the
other four patches of this series? Please pick them up, too!

Thanks
Frieder

Re: [PATCH 1/1] config: CONFIG_SPL_SIZE_LIMIT for VisionFive 2

2023-05-17 Thread Heinrich Schuchardt





On 5/17/23 02:17, Bo Gan wrote:
@Heinrich Some background information I discovered by experimenting with 
my vf2 board:


The only reasonable place to load SPL is the L2 LIM, which is 2M in size 
mapped at
0x800. This region consists of 16 0x2 sized regions, each one 
can be used as
either L2 cache way or SRAM (not both). From top to bottom, you have way 
0-15. When
ways are enabled, they can't be disabled without reset. Effectively, as 
you enabling
more and more L2 cache, this SRAM region shrinks. The way 0 is always 
enabled, so SPL

can only use at most 0x1e bytes of memory.

On 5/16/23 12:56 PM, Heinrich Schuchardt wrote:


https://github.com/starfive-tech/Tools/commit/8c5acc4e5eb7e4ad012463b05a5e3dbbfed1c38d

seems to have changed the limit in the tooling.


I don't know how they derive the number 180048, but my guess is they 
just pick some
number that fits their u-boot build. For correctness, it really depends 
on how ROM is
loading SPL, and where does ROM allocate its data/stack during loading, 
so it won't
collide with the SPL being loaded. It might also be that ROM uses S7 
DTIM to load SPL,
and doesn't touch L2 LIM at all. The ROM is close-sourced, thus, not 
very easy to know

without reverse-engineering it. The defconfig already defines


https://github.com/u-boot/u-boot/blob/6e1852c/configs/starfive_visionfive2_defconfig#L37
CONFIG_SPL_MAX_SIZE=0x4
CONFIG_SPL_BSS_START_ADDR=0x804


256KiB of SPL sounds like a reasonable number to me. 128KiB might be a 
little bit small
when you have max loglevels enabled, and -DDEBUG. I think we can 
probably just change

CONFIG_SPL_MAX_SIZE to CONFIG_SPL_SIZE_LIMIT, and be done with it.


128 KiB is exceeded when adding the not yet merged patch series for 
updating the DTB based on EEPROM data. This is why I hit the old limit 
in spl_tool.


I would prefer if we could add the functionality of spl_tool into 
U-Boot's mkimage and let binman handle invoking it.


CONFIG_SPL_SIZE_LIMIT would be without the 1 KiB header added by 
spl_tool. So should CONFIG_SPL_MAX_SIZE and CONFIG_SPL_SIZE_LIMIT be set 
to 0x3FC00?


Best regards

Heinrich

Re: [UBOOT PATCH 0/3] Port the usb reset patches from linux