Re: [PATCH 7/7] verdin-imx8mp_defconfig: Enable PCIe/NVMe support
Hello Sumit, On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote: > Also, enable reset driver which is a prerequisite for PCIe support. > > Signed-off-by: Sumit Garg > --- > configs/verdin-imx8mp_defconfig | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig > index 22b8a334dfa..d8bd644322b 100644 > --- a/configs/verdin-imx8mp_defconfig > +++ b/configs/verdin-imx8mp_defconfig > @@ -185,3 +185,12 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 > CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 > CONFIG_IMX_WATCHDOG=y > CONFIG_HEXDUMP=y > +CONFIG_DM_RESET=y > +CONFIG_RESET_IMX=y > +CONFIG_PCI=y > +CONFIG_PCIE_DW_IMX8=y > +CONFIG_PHY_IMX8M_PCIE=y > +CONFIG_CMD_PCI=y > +CONFIG_NVME=y > +CONFIG_NVME_PCI=y > +CONFIG_CMD_NVME=y This will increase the u-boot proper size and marginally increase the boot time (because of a bigger binary to be read from the eMMC). Apart of that do you expect any other impact on those changes? SPL binary size should not be affected, correct? Asking this out loudly to confirm that nothing unexpected is going to happen because of these changes. For my curiosity, care to share what's the use case? Do you plan to have the OS stored into an NVME device? Francesco
Re: [PATCH v2 5/6] efi_selftest: Add box drawing character selftest
Hej,
On Mon, Feb 12, 2024, at 17:07, Heinrich Schuchardt wrote:
> On 10.02.24 13:46, Janne Grunau via B4 Relay wrote:
>> From: Andre Przywara
>>
>> UEFI applications rely on Unicode output capability, and might use that
>> for drawing pseudo-graphical interfaces using Unicode defined box
>> drawing characters.
>>
>> Add a simple test to display the most basic box characters, which would
>> need to be checked manually on the screen for correctness.
>> To facilitate this, add a three second delay after the output at this
>> point.
>>
>> Signed-off-by: Andre Przywara
>> Suggested-by: Heinrich Schuchardt
>> Signed-off-by: Janne Grunau
>> ---
>> lib/efi_selftest/efi_selftest_textoutput.c | 20
>> 1 file changed, 20 insertions(+)
>>
>> diff --git a/lib/efi_selftest/efi_selftest_textoutput.c
>> b/lib/efi_selftest/efi_selftest_textoutput.c
>> index 2aa81b0a80..cc11a22eee 100644
>> --- a/lib/efi_selftest/efi_selftest_textoutput.c
>> +++ b/lib/efi_selftest/efi_selftest_textoutput.c
>> @@ -33,6 +33,19 @@ static int execute(void)
>> const u16 text[] =
>> u"\u00d6sterreich Edelwei\u00df Sm\u00f8rrebr\u00f8d Sm\u00f6rg"
>> u"\u00e5s Ni\u00f1o Ren\u00e9 >\u1f19\u03bb\u03bb\u03ac\u03c2<\n";
>> +const u16 boxes[] =
>> +u"This should render as four boxes with text\n"
>> +u"\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
>> +u"\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
>> +u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\n\u2502"
>> +u" left top\u2502 right top \u2502\n\u251c\u2500"
>> +u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
>> +u"\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
>> +u"\u2500\u2500\u2500\u2500\u2500\u2500\u2524\n\u2502 "
>> +u"left bottom \u2502 right bottom \u2502\n\u2514\u2500\u2500\u2500"
>> +u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2534"
>> +u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
>> +u"\u2500\u2500\u2500\u2500\u2518\n";
>>
>> /* SetAttribute */
>> efi_st_printf("\nColor palette\n");
>> @@ -126,6 +139,13 @@ u"\u00e5s Ni\u00f1o Ren\u00e9
>> >\u1f19\u03bb\u03bb\u03ac\u03c2<\n";
>> efi_st_error("OutputString failed for international chars\n");
>> return EFI_ST_FAILURE;
>> }
>> +ret = con_out->output_string(con_out, boxes);
>> +if (ret != EFI_ST_SUCCESS) {
>> +efi_st_error("OutputString failed for box drawing chars\n");
>> +return EFI_ST_FAILURE;
>> +}
>> +con_out->output_string(con_out, u"waiting for admiration...\n");
>> +EFI_CALL(systab.boottime->stall(300));
>
> We don't want to add any unnecessary waiting times in the unit tests. If
> somebody wants to see the output, he can scroll up.
I'll remove this but this series is adding UTF-8 support to the video consoles
which do not have scrollback. This is also the reason for the terse test lines.
best regards
Janne
[PATCH] dma: ti: k3-udma: Fix ring_idx to pair k3 nav rings"
ring_idx was not correctly assigned in case of tflow_id is zero.
Which leads to wrong pairing of DMA for drivers like OSPI.
Fixes: 4312a1dfca26 ("dma: ti: k3-udma: Use ring_idx to pair k3 nav rings")
Signed-off-by: Udit Kumar
---
drivers/dma/ti/k3-udma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index eea9ec9659..398668 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -884,10 +884,10 @@ static int udma_alloc_tx_resources(struct udma_chan *uc)
return ret;
tchan = uc->tchan;
- if (tchan->tflow_id >= 0)
+ if (tchan->tflow_id > 0)
ring_idx = tchan->tflow_id;
else
- ring_idx = ud->bchan_cnt + tchan->id;
+ ring_idx = tchan->id;
ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
>tchan->t_ring,
--
2.34.1
[PATCH 2/6] usb: xhci: Set up endpoints for the first 2 interfaces
From: Janne Grunau
Apple USB keyboards carry the HID keyboard boot protocol on the second
interface. Using the second interface in the USB keyboard driver does
not work since the xhci has not allocated a transfer ring.
---
drivers/usb/host/xhci.c | 31 +++
include/usb.h | 6 ++
2 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 534c4b973f..741e186ee0 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -606,24 +606,28 @@ static int xhci_set_configuration(struct usb_device *udev)
int slot_id = udev->slot_id;
struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
struct usb_interface *ifdesc;
+ unsigned int ifnum;
+ unsigned int max_ifnum = min((unsigned int)USB_MAX_ACTIVE_INTERFACES,
+(unsigned int)udev->config.no_of_if);
out_ctx = virt_dev->out_ctx;
in_ctx = virt_dev->in_ctx;
- num_of_ep = udev->config.if_desc[0].no_of_ep;
- ifdesc = >config.if_desc[0];
-
ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
/* Initialize the input context control */
ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
ctrl_ctx->drop_flags = 0;
- /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
- for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
- ep_flag = xhci_get_ep_index(>ep_desc[cur_ep]);
- ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
- if (max_ep_flag < ep_flag)
- max_ep_flag = ep_flag;
+ for (ifnum = 0; ifnum < max_ifnum; ifnum++) {
+ ifdesc = >config.if_desc[ifnum];
+ num_of_ep = ifdesc->no_of_ep;
+ /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
+ for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
+ ep_flag = xhci_get_ep_index(>ep_desc[cur_ep]);
+ ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
+ if (max_ep_flag < ep_flag)
+ max_ep_flag = ep_flag;
+ }
}
xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
@@ -637,9 +641,12 @@ static int xhci_set_configuration(struct usb_device *udev)
xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
/* filling up ep contexts */
- err = xhci_init_ep_contexts_if(udev, ctrl, virt_dev, ifdesc);
- if (err < 0)
- return err;
+ for (ifnum = 0; ifnum < max_ifnum; ifnum++) {
+ ifdesc = >config.if_desc[ifnum];
+ err = xhci_init_ep_contexts_if(udev, ctrl, virt_dev, ifdesc);
+ if (err < 0)
+ return err;
+ }
return xhci_configure_endpoints(udev, false);
}
diff --git a/include/usb.h b/include/usb.h
index 09e3f0cb30..3aafdc8bfd 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -49,6 +49,12 @@ extern bool usb_started; /* flag for the started/stopped USB
status */
*/
#define USB_TIMEOUT_MS(pipe) (usb_pipebulk(pipe) ? 5000 : 1000)
+/*
+ * The xhcd hcd driver prepares only a limited number interfaces / endpoints.
+ * Define this limit so that drivers do not exceed it.
+ */
+#define USB_MAX_ACTIVE_INTERFACES 2
+
/* device request (setup) */
struct devrequest {
__u8requesttype;
--
2.43.2
[PATCH 6/6] usb: kbd: Add probe quirk for Apple and Keychron keyboards
From: Janne Grunau
Those keyboards do not return the current device state. Polling will
timeout unless there are key presses. This is not a problem during
operation but the inital device state query during probing will fail.
Skip this step in usb_kbd_probe_dev() to make these devices useable.
Not all Apple keyboards behave like this. A keyboard with USB
vendor/product ID 05ac:0221 is reported to work with the current code.
Unfortunately some Keychron keyboards "re-use" Apple's vendor ID and
show the same behavior (Keychron C2, 05ac:024f for example).
Signed-off-by: Janne Grunau
---
common/usb_kbd.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 7aa803eb4e..b0012ce7ad 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -31,6 +31,10 @@
#define USB_DEVICE_ID_APPLE_MAGIC_KEYBOARD_FINGERPRINT_20210x029a
#define USB_DEVICE_ID_APPLE_MAGIC_KEYBOARD_NUMPAD_2021 0x029f
+#define USB_VENDOR_ID_KEYCHRON 0x3434
+
+#define USB_HID_QUIRK_POLL_NO_REPORT_IDLE (1 << 0)
+
/*
* If overwrite_console returns 1, the stdin, stderr and stdout
* are switched to the serial port, else the settings in the
@@ -483,6 +487,7 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
unsigned int ifnum)
struct usb_interface *iface;
struct usb_endpoint_descriptor *ep;
struct usb_kbd_pdata *data;
+ unsigned int quirks = 0;
int epNum;
int i;
@@ -525,6 +530,15 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
unsigned int ifnum)
debug("USB KBD: found interrupt EP: 0x%x\n", ep->bEndpointAddress);
+ switch (dev->descriptor.idVendor) {
+ case USB_VENDOR_ID_APPLE:
+ case USB_VENDOR_ID_KEYCHRON:
+ quirks |= USB_HID_QUIRK_POLL_NO_REPORT_IDLE;
+ break;
+ default:
+ break;
+ }
+
data = malloc(sizeof(struct usb_kbd_pdata));
if (!data) {
printf("USB KBD: Error allocating private data\n");
@@ -565,6 +579,14 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
unsigned int ifnum)
usb_set_idle(dev, iface->desc.bInterfaceNumber, 0, 0);
#endif
+ /*
+* Apple and Keychron keyboards do not report the device state. Reports
+* are only returned during key presses.
+*/
+ if (quirks & USB_HID_QUIRK_POLL_NO_REPORT_IDLE) {
+ debug("USB KBD: quirk: skip testing device state\n");
+ return 1;
+ }
debug("USB KBD: enable interrupt pipe...\n");
#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
data->intq = create_int_queue(dev, data->intpipe, 1,
--
2.43.2
[PATCH 3/6] usb: xhci: Abort transfers with unallocated rings
From: Janne Grunau Discovered while trying to use the second interface in the USB keyboard driver necessary on Apple USB keyboards. Signed-off-by: Janne Grunau --- drivers/usb/host/xhci-ring.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index b60661fe05..4446f5f098 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -685,6 +685,9 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, reset_ep(udev, ep_index); ring = virt_dev->eps[ep_index].ring; + if (!ring) + return -1; + /* * How much data is (potentially) left before the 64KB boundary? * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec) @@ -871,6 +874,8 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, ep_index = usb_pipe_ep_index(pipe); ep_ring = virt_dev->eps[ep_index].ring; + if (!ep_ring) + return -1; /* * Check to see if the max packet size for the default control -- 2.43.2
[PATCH 4/6] usb: kbd: Ignore Yubikeys
From: Hector Martin
We currently only support one USB keyboard device, but some devices
emulate keyboards for other purposes. Most commonly, people run into
this with Yubikeys, so let's ignore those.
Even if we end up supporting multiple keyboards in the future, it's
safer to ignore known non-keyboard devices.
Signed-off-by: Hector Martin
---
common/usb_kbd.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 4cbc9acb73..774d3555d9 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -120,6 +120,15 @@ struct usb_kbd_pdata {
extern int __maybe_unused net_busy_flag;
+/*
+ * Since we only support one usbkbd device in the iomux,
+ * ignore common keyboard-emulating devices that aren't
+ * real keyboards.
+ */
+const uint16_t vid_blocklist[] = {
+ 0x1050, /* Yubico */
+};
+
/* The period of time between two calls of usb_kbd_testc(). */
static unsigned long kbd_testc_tms;
@@ -465,6 +474,7 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
unsigned int ifnum)
struct usb_endpoint_descriptor *ep;
struct usb_kbd_pdata *data;
int epNum;
+ int i;
if (dev->descriptor.bNumConfigurations != 1)
return 0;
@@ -480,6 +490,15 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
unsigned int ifnum)
if (iface->desc.bInterfaceProtocol != USB_PROT_HID_KEYBOARD)
return 0;
+ for (i = 0; i < ARRAY_SIZE(vid_blocklist); i++) {
+ if (dev->descriptor.idVendor == vid_blocklist[i]) {
+ printf("Ignoring keyboard device 0x%x:0x%x\n",
+ dev->descriptor.idVendor,
+ dev->descriptor.idProduct);
+ return 0;
+ }
+ }
+
for (epNum = 0; epNum < iface->desc.bNumEndpoints; epNum++) {
ep = >ep_desc[epNum];
--
2.43.2
[PATCH 1/6] usb: xhci: refactor xhci_set_configuration
From: Janne Grunau
In the next step endpoints for multiple interfaces are set up. Move most
of the per endpoint initialization to separate function to avoid another
identation level.
Signed-off-by: Janne Grunau
---
drivers/usb/host/xhci.c | 119 +---
1 file changed, 73 insertions(+), 46 deletions(-)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index d13cbff9b3..534c4b973f 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -475,67 +475,34 @@ static int xhci_configure_endpoints(struct usb_device
*udev, bool ctx_change)
}
/**
- * Configure the endpoint, programming the device contexts.
+ * Fill endpoint contexts for interface descriptor ifdesc.
*
- * @param udev pointer to the USB device structure
- * Return: returns the status of the xhci_configure_endpoints
+ * @param udev pointer to the USB device structure
+ * @param ctrl pointer to the xhci pravte device structure
+ * @param virt_dev pointer to the xhci virtual device structure
+ * @param ifdesc pointer to the USB interface config descriptor
+ * Return: returns the status of xhci_init_ep_contexts_if
*/
-static int xhci_set_configuration(struct usb_device *udev)
+static int xhci_init_ep_contexts_if(struct usb_device *udev,
+ struct xhci_ctrl *ctrl,
+ struct xhci_virt_device *virt_dev,
+ struct usb_interface *ifdesc
+ )
{
- struct xhci_container_ctx *in_ctx;
- struct xhci_container_ctx *out_ctx;
- struct xhci_input_control_ctx *ctrl_ctx;
- struct xhci_slot_ctx *slot_ctx;
struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
int cur_ep;
- int max_ep_flag = 0;
int ep_index;
unsigned int dir;
unsigned int ep_type;
- struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
- int num_of_ep;
- int ep_flag = 0;
u64 trb_64 = 0;
- int slot_id = udev->slot_id;
- struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
- struct usb_interface *ifdesc;
u32 max_esit_payload;
unsigned int interval;
unsigned int mult;
unsigned int max_burst;
unsigned int avg_trb_len;
unsigned int err_count = 0;
+ int num_of_ep = ifdesc->no_of_ep;
- out_ctx = virt_dev->out_ctx;
- in_ctx = virt_dev->in_ctx;
-
- num_of_ep = udev->config.if_desc[0].no_of_ep;
- ifdesc = >config.if_desc[0];
-
- ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
- /* Initialize the input context control */
- ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
- ctrl_ctx->drop_flags = 0;
-
- /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
- for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
- ep_flag = xhci_get_ep_index(>ep_desc[cur_ep]);
- ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
- if (max_ep_flag < ep_flag)
- max_ep_flag = ep_flag;
- }
-
- xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
-
- /* slot context */
- xhci_slot_copy(ctrl, in_ctx, out_ctx);
- slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
- slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK));
- slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
-
- xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
-
- /* filling up ep contexts */
for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
struct usb_endpoint_descriptor *endpt_desc = NULL;
struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
@@ -561,7 +528,8 @@ static int xhci_set_configuration(struct usb_device *udev)
avg_trb_len = max_esit_payload;
ep_index = xhci_get_ep_index(endpt_desc);
- ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
+ ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx,
+ ep_index);
/* Allocate the ep rings */
virt_dev->eps[ep_index].ring = xhci_ring_alloc(ctrl, 1, true);
@@ -614,6 +582,65 @@ static int xhci_set_configuration(struct usb_device *udev)
}
}
+ return 0;
+}
+
+/**
+ * Configure the endpoint, programming the device contexts.
+ *
+ * @param udev pointer to the USB device structure
+ * Return: returns the status of the xhci_configure_endpoints
+ */
+static int xhci_set_configuration(struct usb_device *udev)
+{
+ struct xhci_container_ctx *out_ctx;
+ struct xhci_container_ctx *in_ctx;
+ struct xhci_input_control_ctx *ctrl_ctx;
+ struct xhci_slot_ctx *slot_ctx;
+ int err;
+ int cur_ep;
+ int max_ep_flag = 0;
+ struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
+ int num_of_ep;
+ int ep_flag = 0;
+ int slot_id =
[PATCH 5/6] usb: kbd: support Apple Magic Keyboards (2021)
From: Janne Grunau
Apple USB keyboards (Magic Keyboard from 2021 (product id 0x029c)) carry
the HID keyboard boot protocol on the second interface descriptor.
Probe via vendor and product IDs since the class/subclass/protocol match
uses the first interface descriptor.
Probe the two first interface descriptors for the HID keyboard boot
protocol.
USB configuration descriptor for reference:
| Bus 003 Device 002: ID 05ac:029c Apple, Inc. Magic Keyboard
| Device Descriptor:
| bLength18
| bDescriptorType 1
| bcdUSB 2.00
| bDeviceClass0 [unknown]
| bDeviceSubClass 0 [unknown]
| bDeviceProtocol 0
| bMaxPacketSize064
| idVendor 0x05ac Apple, Inc.
| idProduct 0x029c Magic Keyboard
| bcdDevice3.90
| iManufacturer 1 Apple Inc.
| iProduct2 Magic Keyboard
| iSerial 3 ...
| bNumConfigurations 1
| Configuration Descriptor:
| bLength 9
| bDescriptorType 2
| wTotalLength 0x003b
| bNumInterfaces 2
| bConfigurationValue 1
| iConfiguration 4 Keyboard
| bmAttributes 0xa0
| (Bus Powered)
| Remote Wakeup
| MaxPower 500mA
| Interface Descriptor:
| bLength 9
| bDescriptorType 4
| bInterfaceNumber0
| bAlternateSetting 0
| bNumEndpoints 1
| bInterfaceClass 3 Human Interface Device
| bInterfaceSubClass 0 [unknown]
| bInterfaceProtocol 0
| iInterface 5 Device Management
| HID Device Descriptor:
| bLength 9
| bDescriptorType33
| bcdHID 1.10
| bCountryCode0 Not supported
| bNumDescriptors 1
| bDescriptorType34 Report
| wDescriptorLength 83
| Report Descriptors:
| ** UNAVAILABLE **
| Endpoint Descriptor:
| bLength 7
| bDescriptorType 5
| bEndpointAddress 0x81 EP 1 IN
| bmAttributes3
| Transfer TypeInterrupt
| Synch Type None
| Usage Type Data
| wMaxPacketSize 0x0010 1x 16 bytes
| bInterval 8
| Interface Descriptor:
| bLength 9
| bDescriptorType 4
| bInterfaceNumber1
| bAlternateSetting 0
| bNumEndpoints 1
| bInterfaceClass 3 Human Interface Device
| bInterfaceSubClass 1 Boot Interface Subclass
| bInterfaceProtocol 1 Keyboard
| iInterface 6 Keyboard / Boot
| HID Device Descriptor:
| bLength 9
| bDescriptorType33
| bcdHID 1.10
| bCountryCode 13 International (ISO)
| bNumDescriptors 1
| bDescriptorType34 Report
| wDescriptorLength 207
| Report Descriptors:
| ** UNAVAILABLE **
| Endpoint Descriptor:
| bLength 7
| bDescriptorType 5
| bEndpointAddress 0x82 EP 2 IN
| bmAttributes3
| Transfer TypeInterrupt
| Synch Type None
| Usage Type Data
| wMaxPacketSize 0x0010 1x 16 bytes
| bInterval 8
Signed-off-by: Janne Grunau
---
common/usb_kbd.c | 39 +++
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 774d3555d9..7aa803eb4e 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -23,6 +23,14 @@
#include
+/*
+ * USB vendor and product IDs used for quirks.
+ */
+#define USB_VENDOR_ID_APPLE0x05ac
+#define USB_DEVICE_ID_APPLE_MAGIC_KEYBOARD_20210x029c
+#define USB_DEVICE_ID_APPLE_MAGIC_KEYBOARD_FINGERPRINT_20210x029a
+#define USB_DEVICE_ID_APPLE_MAGIC_KEYBOARD_NUMPAD_2021 0x029f
+
/*
* If overwrite_console returns 1, the stdin, stderr and stdout
* are switched to the serial port, else the settings in the
@@ -106,6 +114,8 @@ struct usb_kbd_pdata {
unsigned long last_report;
struct int_queue *intq;
+ uint32_tifnum;
+
uint32_trepeat_delay;
uint32_tusb_in_pointer;
@@ -159,8 +169,8 @@ static void usb_kbd_put_queue(struct usb_kbd_pdata *data,
u8 c)
*/
static void usb_kbd_setled(struct usb_device *dev)
{
- struct usb_interface *iface = >config.if_desc[0];
struct usb_kbd_pdata *data = dev->privptr;
+ struct usb_interface *iface = >config.if_desc[data->ifnum];
[PATCH 0/6] USB keyboard improvements for asahi / desktop systems
Apple USB Keyboards from 2021 need quirks to be useable. The boot HID keyboard protocol is unfortunately not described in the first interface descriptor but the second. This needs several changes. The USB keyboard driver has to look at all (2) interface descriptors during probing. Since I didn't want to rebuild the USB driver probe code the Apple keyboards are bound to the keyboard driver via USB vendor and product IDs. To make the keyboards useable on Apple silicon devices the xhci driver needs to initializes rings for the endpoints of the first two interface descriptors. If this is causes concerns regarding regressions or memory use the USB_MAX_ACTIVE_INTERFACES define could be turned into a CONFIG option. Even after this changes the keyboards still do not probe successfully since they apparently do not behave HID standard compliant. They only generate reports on key events. This leads the final check whether the keyboard is operational to fail unless the user presses keys during the probe. Skip this check for known keyboards. Keychron seems to emulate Apple keyboards (some models even "re-use" Apple's USB vendor ID) so apply this quirk as well. Some devices like Yubikeys emulate a keyboard. since u-boot only binds a single keyboard block this kind of devices from the USB keyboard driver. Signed-off-by: Janne Grunau --- Hector Martin (1): usb: kbd: Ignore Yubikeys Janne Grunau (5): usb: xhci: refactor xhci_set_configuration usb: xhci: Set up endpoints for the first 2 interfaces usb: xhci: Abort transfers with unallocated rings usb: kbd: support Apple Magic Keyboards (2021) usb: kbd: Add probe quirk for Apple and Keychron keyboards common/usb_kbd.c | 80 +-- drivers/usb/host/xhci-ring.c | 5 ++ drivers/usb/host/xhci.c | 126 +++ include/usb.h| 6 +++ 4 files changed, 167 insertions(+), 50 deletions(-) --- base-commit: 37345abb97ef0dd9c50a03b2a72617612dcae585 change-id: 20240218-asahi-keyboards-f2ddaf0022b2 Best regards, -- Janne Grunau
Re: [PATCH 7/7] verdin-imx8mp_defconfig: Enable PCIe/NVMe support
On Tue, 20 Feb 2024 at 21:34, Fabio Estevam wrote: > > On Tue, Feb 20, 2024 at 10:51 AM Sumit Garg wrote: > > > > Also, enable reset driver which is a prerequisite for PCIe support. > > > > Signed-off-by: Sumit Garg > > --- > > configs/verdin-imx8mp_defconfig | 9 + > > 1 file changed, 9 insertions(+) > > > > diff --git a/configs/verdin-imx8mp_defconfig > > b/configs/verdin-imx8mp_defconfig > > index 22b8a334dfa..d8bd644322b 100644 > > --- a/configs/verdin-imx8mp_defconfig > > +++ b/configs/verdin-imx8mp_defconfig > > @@ -185,3 +185,12 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 > > CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 > > CONFIG_IMX_WATCHDOG=y > > CONFIG_HEXDUMP=y > > +CONFIG_DM_RESET=y > > +CONFIG_RESET_IMX=y > > +CONFIG_PCI=y > > +CONFIG_PCIE_DW_IMX8=y > > +CONFIG_PHY_IMX8M_PCIE=y > > +CONFIG_CMD_PCI=y > > +CONFIG_NVME=y > > +CONFIG_NVME_PCI=y > > +CONFIG_CMD_NVME=y > > Please don't group all these new config options at the end of the file. > > Use 'make savedefconfig' and then 'cp defconfig > configs/verdin-imx8mp_defconfig' to properly > add these new config options. That sounds better, I will do that for v2. -Sumit
Re: [PATCH 7/7] verdin-imx8mp_defconfig: Enable PCIe/NVMe support
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote: > > On 2/20/24 14:10, Sumit Garg wrote: > > Also, enable reset driver which is a prerequisite for PCIe support. > > Commit message needs to be fixed. Let me reiterate the header here too. Enable PCIe/NVMe support. Also, enable the reset driver which is a prerequisite for PCIe support. -Sumit
[PATCH] bootstd: fix build error when CONFIG_MMC is disabled
This code assumes that CONFIG_MMC and it causes a build error when
the config is disabled.
aarch64-linux-gnu-ld.bfd: test/boot/bootstd_common.o: in function
`bootstd_test_check_mmc_hunter':
test/boot/bootstd_common.c:83:(.text.bootstd_test_check_mmc_hunter+0x70):
undefined reference to `_u_boot_list_2_bootdev_hunter_2_mmc_bootdev_hunter'
Fixes: 66e3dce78750 ("bootstd: Allow hunting for a bootdev by label")
Signed-off-by: Dan Carpenter
---
test/boot/bootstd_common.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/test/boot/bootstd_common.c b/test/boot/bootstd_common.c
index e71a2975c53c..cc97e255e5cb 100644
--- a/test/boot/bootstd_common.c
+++ b/test/boot/bootstd_common.c
@@ -74,6 +74,9 @@ int bootstd_test_check_mmc_hunter(struct unit_test_state *uts)
struct bootstd_priv *std;
uint seq;
+ if (!IS_ENABLED(CONFIG_MMC))
+ return 0;
+
/* get access to the used hunters */
ut_assertok(bootstd_get_priv());
--
2.43.0
[PATCH] bootflow: Fix build error when BOOTMETH_CROS is disabled
The bootflow testing assumes that BOOTMETH_CROS is enabled but it
might not be which leads to a build error.
aarch64-linux-gnu-ld.bfd: test/boot/bootflow.o: in function `prep_mmc_bootdev':
test/boot/bootflow.c:549:(.text.prep_mmc_bootdev+0x1c8):
undefined reference to `_u_boot_list_2_driver_2_bootmeth_cros'
Fixes: d08db02d2d3d ("bootstd: Add a test for bootmeth_cros")
Signed-off-by: Dan Carpenter
---
test/boot/bootflow.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index fa54dde661c8..4845b7121c84 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -544,7 +544,7 @@ static int prep_mmc_bootdev(struct unit_test_state *uts,
const char *mmc_dev,
"bootmeth_script", 0, ofnode_null(), ));
/* Enable the cros bootmeth if needed */
- if (bind_cros) {
+ if (IS_ENABLED(CONFIG_BOOTMETH_CROS) && bind_cros) {
ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, ));
ut_assertok(device_bind(bootstd, DM_DRIVER_REF(bootmeth_cros),
"cros", 0, ofnode_null(), ));
--
2.43.0
Re: [PATCH 6/7] pci: Add DW PCIe controller support for iMX8MP SoC
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
>
> On 2/20/24 14:10, Sumit Garg wrote:
> > pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
> > tied to quite old port of pcie_designware driver from Linux which
> > suffices only iMX6 specific needs.
> >
> > But currently we have the common DWC specific bits which alligns pretty
> > well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
> > bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
> > add support for other iMX8 variants to this driver.
> >
> > iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
> > can reuse the generic PHY infrastructure to power on PCIe PHY.
> >
> > Signed-off-by: Sumit Garg
> > ---
> > drivers/pci/Kconfig| 8 +
> > drivers/pci/Makefile | 1 +
> > drivers/pci/pcie_dw_imx8.c | 348 +
> > 3 files changed, 357 insertions(+)
> > create mode 100644 drivers/pci/pcie_dw_imx8.c
> >
> > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> > index 463ec47eb92..b7c7922b091 100644
> > --- a/drivers/pci/Kconfig
> > +++ b/drivers/pci/Kconfig
> > @@ -413,4 +413,12 @@ config PCIE_STARFIVE_JH7110
> > Say Y here if you want to enable PLDA XpressRich PCIe controller
> > support on StarFive JH7110 SoC.
> >
> > +config PCIE_DW_IMX8
> > + bool "i.MX8 PCIe support"
> > + depends on ARCH_IMX8M
> > + select PCIE_DW_COMMON
> > + help
> > + Say Y here if you want to enable DW PCIe controller support on
> > + iMX8 SoCs.
> > +
> > endif
> > diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> > index 72ef8b4bc77..cddbb902095 100644
> > --- a/drivers/pci/Makefile
> > +++ b/drivers/pci/Makefile
> > @@ -53,3 +53,4 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
> > obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
> > obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
> > obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
> > +obj-$(CONFIG_PCIE_DW_IMX8) += pcie_dw_imx8.o
> > diff --git a/drivers/pci/pcie_dw_imx8.c b/drivers/pci/pcie_dw_imx8.c
> > new file mode 100644
> > index 000..b9921644765
> > --- /dev/null
> > +++ b/drivers/pci/pcie_dw_imx8.c
> > @@ -0,0 +1,348 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2024 Linaro Ltd.
> > + *
> > + * Author: Sumit Garg
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include "pcie_dw_common.h"
> > +
> > +#define PCIE_LINK_CAPABILITY 0x7c
> > +#define TARGET_LINK_SPEED_MASK 0xf
> > +#define LINK_SPEED_GEN_1 0x1
> > +#define LINK_SPEED_GEN_2 0x2
> > +#define LINK_SPEED_GEN_3 0x3
> > +
> > +#define PCIE_MISC_CONTROL_1_OFF 0x8bc
> > +#define PCIE_DBI_RO_WR_ENBIT(0)
> > +
> > +#define PCIE_PORT_DEBUG0 0x728
> > +#define PCIE_PORT_DEBUG1 0x72c
> > +#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
> > +#define PCIE_PORT_DEBUG1_LINK_IN_TRAININGBIT(29)
> > +
> > +#define PCIE_LINK_UP_TIMEOUT_MS 100
> > +
> > +#define IOMUXC_GPR14_OFFSET 0x38
> > +#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
> > +#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
> > +
> > +struct pcie_dw_imx8 {
> > + /* Must be first member of the struct */
> > + struct pcie_dw dw;
> > + struct regmap *iomuxc_gpr;
> > + struct clk pcie;
> > + struct clk pcie_bus;
> > + struct clk pcie_aux;
> > + struct gpio_descreset_gpio;
> > + struct reset_ctlapps_reset;
> > + struct phy phy;
> > +};
> > +
> > +static void pcie_dw_configure(struct pcie_dw_imx8 *priv, u32 cap_speed)
> > +{
> > + u32 val;
> > +
> > + dw_pcie_dbi_write_enable(>dw, true);
> > +
> > + val = readl(priv->dw.dbi_base + PCIE_LINK_CAPABILITY);
> > + val &= ~TARGET_LINK_SPEED_MASK;
> > + val |= cap_speed;
> > + writel(val, priv->dw.dbi_base + PCIE_LINK_CAPABILITY);
>
> clrsetbits_le32()
Ack.
>
> > +
> > + dw_pcie_dbi_write_enable(>dw, false);
> > +}
> > +
> > +static void imx8_pcie_ltssm_enable(struct pcie_dw_imx8 *priv)
> > +{
> > + reset_deassert(>apps_reset);
> > +}
> > +
> > +static void imx8_pcie_ltssm_disable(struct pcie_dw_imx8 *priv)
> > +{
> > + reset_assert(>apps_reset);
> > +}
> > +
> > +static int is_link_up(struct pcie_dw_imx8 *priv)
> > +{
> > + u32 val;
> > +
> > + val = readl(priv->dw.dbi_base + PCIE_PORT_DEBUG1);
> > +
> > + return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
> > + (!(val &
RE: [PATCH v1 1/1] arch:arm: Agilex5 enablement
Hi, > -Original Message- > From: Lim, Jit Loon > Sent: Tuesday, February 20, 2024 10:36 PM > To: u-boot@lists.denx.de > Cc: Jagan Teki ; Marek ; > Simon ; Chee, Tien Fong > ; Hea, Kok Kiang ; > Maniyam, Dinesh ; Ng, Boon Khai > ; Yuslaimi, Alif Zakuan > ; Chong, Teik Heng > ; Zamri, Muhammad Hazim Izzat > ; Lim, Jit Loon > ; Tang, Sieu Mun ; Bin > Meng > Subject: [PATCH v1 1/1] arch:arm: Agilex5 enablement > > This patch is to enable Agilex5 platform for Intel product. Changes, > modification and new files are created for board, dts, configs and makefile to > create the base for Agilex5. > > Signed-off-by: Jit Loon Lim > --- > arch/arm/Kconfig | 9 +- > arch/arm/dts/Makefile | 32 + > .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 11 +- > arch/arm/dts/socfpga_agilex5_socdk.dts| 67 +- > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi| 2 +- > arch/arm/mach-socfpga/Kconfig | 125 +- > arch/arm/mach-socfpga/Makefile| 99 +- > arch/arm/mach-socfpga/board.c | 2 - > .../include/mach/base_addr_soc64.h| 16 +-- > board/intel/agilex5-socdk/MAINTAINERS | 2 + > board/intel/agilex5-socdk/Makefile| 2 +- > board/intel/agilex5-socdk/socfpga.c | 2 +- > configs/socfpga_agilex5_defconfig | 33 - > include/configs/socfpga_agilex5_socdk.h | 2 +- > include/configs/socfpga_soc64_common.h| 40 +- > 15 files changed, 63 insertions(+), 381 deletions(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > 43d5ad346f..c8d91669da 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,7 +28,7 @@ config COUNTER_FREQUENCY > ROCKCHIP_RK3288 || ROCKCHIP_RK322X || > ROCKCHIP_RK3036 > default 2500 if ARCH_LX2160A || ARCH_LX2162A || > ARCH_LS1088A > default 1 if ARCH_ZYNQMP > - default 4 if ARCH_SOCFPGA && ARM64 This patch is not based on latest U-Boot main branch https://source.denx.de/u-boot/u-boot.git, no such code in current main branch. > + default 2 if ARCH_SOCFPGA && ARM64 && > TARGET_SOCFPGA_AGILEX5 > default 0 > help > For platforms with ARMv8-A and ARMv7-A which features a system > @@ -1088,14 +1088,14 @@ config ARCH_SNAPDRAGON > select SPMI > imply CMD_DM > > -config ARCH_SOCFPGA Why remove this? > - bool "Altera SOCFPGA family" > +bool "Altera SOCFPGA family" Why to change this? > select ARCH_EARLY_INIT_R > select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 > select ARM64 if TARGET_SOCFPGA_SOC64 > select CPU_V7A if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select DM > select DM_SERIAL > + select GICV2 > select GPIO_EXTRA_HEADER > select ENABLE_ARM_SOC_BOOT0_HOOK if > TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 > select OF_CONTROL > @@ -1109,7 +1109,7 @@ config ARCH_SOCFPGA > select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 > select SPL_SERIAL > select SPL_SYSRESET > - select SPL_WATCHDOG > + select SPL_WATCHDOG if !TARGET_SOCFPGA_AGILEX5 This can be removed, watchdog is supported in Agilex5 > select SUPPORT_SPL > select SYS_NS16550 > select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 @@ -1123,6 +1123,7 @@ config > ARCH_SOCFPGA > imply DM_SPI > imply DM_SPI_FLASH > imply FAT_WRITE > + imply MTD > imply SPL > imply SPL_DM > imply SPL_DM_SPI > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index > 90d933a9ae..646f4feaf7 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -543,37 +543,7 @@ dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517- > evm.dtb > dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb > > dtb-$(CONFIG_ARCH_SOCFPGA) +=\ > - socfpga_agilex_n6010.dtb\ > - socfpga_agilex_socdk.dtb\ > - socfpga_agilex_socdk_nand.dtb \ > - socfpga_agilex_socdk_qspi.dtb \ > - socfpga_agilex5_socdk.dtb \ > - socfpga_agilex5_emu.dtb \ > - socfpga_agilex7m_socdk.dtb \ > - socfpga_agilex7m_socdk_nand.dtb \ > - socfpga_arria5_secu1.dtb\ > - socfpga_arria5_socdk.dtb\ > - socfpga_arria10_chameleonv3_270_2.dtb \ > - socfpga_arria10_chameleonv3_270_3.dtb \ > - socfpga_arria10_chameleonv3_480_2.dtb \ > - socfpga_arria10_socdk_nand.dtb \ > - socfpga_arria10_socdk_qspi.dtb \ > - socfpga_arria10_socdk_sdmmc.dtb \ > - socfpga_cyclone5_mcvevk.dtb \ > -
Re: [PATCH 5/7] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
>
> On 2/20/24 14:10, Sumit Garg wrote:
> > Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
> > PHY initialization moved to this standalone PHY driver.
> >
> > Signed-off-by: Sumit Garg
>
> Is this based on Linux ? If so, include Linux commit ID from which the
> code was imported.
Yeah it is derived from the corresponding Linux driver (see header for
phy-imx8m-pcie.c file). I can add the corresponding Linux version
(v6.8-rc3) in the commit message.
-Sumit
Re: [PATCH 4/7] imx8mp: power-domain: Expose high performance PLL clock
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
>
> On 2/20/24 14:10, Sumit Garg wrote:
> > PCIe PHY can use it when there is no external refclock provided.
>
> Commit message needs to be fixed.
How about the following?
Expose high performance PLL clock, so the PCIe PHY can
use it when there is no external refclock provided.
>
> > +static int hsio_pll_enable(struct udevice *dev)
> > +{
> > + struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
> > + unsigned long start;
> > + u32 val;
> > +
> > + /* Setup HSIO PLL */
> > + val = readl(priv->base + GPR_REG2);
> > + val &= ~(P_PLL_MASK | M_PLL_MASK | S_PLL_MASK);
> > + val |= (FIELD_PREP(P_PLL_MASK, 12) | FIELD_PREP(M_PLL_MASK, 800) |
> > + FIELD_PREP(S_PLL_MASK, 4));
> > + writel(val, priv->base + GPR_REG2);
>
> clrsetbits_le32()
Ack
>
> > + /* de-assert PLL reset */
> > + setbits_le32(priv->base + GPR_REG3, PLL_RST);
> > +
> > + /* enable PLL */
> > + setbits_le32(priv->base + GPR_REG3, PLL_CKE);
> > +
> > + /* Check if PLL is locked */
> > + start = get_timer(0);
>
> wait_for_bit() or readl_poll_timeout()
Let me use readl_poll_timeout() instead.
>
> > + for (;;) {
> > + if (readl(priv->base + GPR_REG1) & PLL_LOCK)
> > + break;
> > +
> > + if (get_timer(start) > 100) {
> > + dev_err(dev, "failed to lock HSIO PLL\n");
> > + return -ETIMEDOUT;
> > + }
> > +
> > + udelay(10);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void hsio_pll_disable(struct udevice *dev)
> > +{
> > + struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
> > +
> > + /* de-assert PLL reset */
> > + clrbits_le32(priv->base + GPR_REG3, PLL_RST);
> > +
> > + /* enable PLL */
> > + clrbits_le32(priv->base + GPR_REG3, PLL_CKE);
> > +}
> > +
> > static int imx8mp_hsiomix_on(struct power_domain *power_domain)
> > {
> > struct udevice *dev = power_domain->dev;
> > @@ -69,16 +127,23 @@ static int imx8mp_hsiomix_on(struct power_domain
> > *power_domain)
> > if (ret)
> > goto err_clk_pcie;
> >
> > - if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
> > + if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) {
> > setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
> > - else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE)
> > + } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE) {
> > setbits_le32(priv->base + GPR_REG0, PCIE_CLOCK_MODULE_EN);
> > - else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY)
> > + } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY) {
> > setbits_le32(priv->base + GPR_REG0, PCIE_PHY_APB_RST |
> > PCIE_PHY_INIT_RST);
> >
> > + ret = hsio_pll_enable(dev);
>
> Is this how Linux handles this PLL ?
>
> Seems like this should be either syscon or clock driver .
It isn't similar to what Linux does but I can't find suitable
infrastructure in U-Boot to expose it as a regular clock. Are there
any APIs available similar to devm_of_clk_add_hw_provider() in Linux?
-Sumit
>
> [...]
Re: [PATCH 3/7] imx8mp: power-domain: Add PCIe support
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
>
> On 2/20/24 14:10, Sumit Garg wrote:
> > Pre-requisite to enable PCIe support on iMX8MP SoC.
>
> This commit message is useless, write a proper one.
>
How about the following?
Add support for GPCv2 power domains and clock handling
for PCIe and PCIe PHY. It is required to enable PCIe support
on the iMX8MP SoC.
> > Signed-off-by: Sumit Garg
> > ---
> > drivers/power/domain/imx8mp-hsiomix.c | 50 +--
> > 1 file changed, 48 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/power/domain/imx8mp-hsiomix.c
> > b/drivers/power/domain/imx8mp-hsiomix.c
> > index e2d772c5ec7..62145e0261b 100644
> > --- a/drivers/power/domain/imx8mp-hsiomix.c
> > +++ b/drivers/power/domain/imx8mp-hsiomix.c
> > @@ -16,14 +16,19 @@
> > #define GPR_REG00x0
> > #define PCIE_CLOCK_MODULE_EN BIT(0)
> > #define USB_CLOCK_MODULE_ENBIT(1)
> > +#define PCIE_PHY_APB_RSTBIT(4)
> > +#define PCIE_PHY_INIT_RST BIT(5)
> >
> > struct imx8mp_hsiomix_priv {
> > void __iomem *base;
> > struct clk clk_usb;
> > + struct clk clk_pcie;
> > struct power_domain pd_bus;
> > struct power_domain pd_usb;
> > + struct power_domain pd_pcie;
> > struct power_domain pd_usb_phy1;
> > struct power_domain pd_usb_phy2;
> > + struct power_domain pd_pcie_phy;
> > };
> >
> > static int imx8mp_hsiomix_on(struct power_domain *power_domain)
> > @@ -43,6 +48,10 @@ static int imx8mp_hsiomix_on(struct power_domain
> > *power_domain)
> > domain = >pd_usb_phy1;
> > } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) {
> > domain = >pd_usb_phy2;
> > + } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE) {
> > + domain = >pd_pcie;
> > + } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY) {
> > + domain = >pd_pcie_phy;
> > } else {
> > ret = -EINVAL;
> > goto err_pd;
> > @@ -54,14 +63,25 @@ static int imx8mp_hsiomix_on(struct power_domain
> > *power_domain)
> >
> > ret = clk_enable(>clk_usb);
> > if (ret)
> > - goto err_clk;
> > + goto err_clk_usb;
> > +
> > + ret = clk_enable(>clk_pcie);
> > + if (ret)
> > + goto err_clk_pcie;
>
> Does this mean that when USB power domains get enabled, PCIe clock are
> also enabled ? Why ?
>
> What if the PCIe clock enable fails, do USB clock remain enabled ?
Let me gate them behind corresponding power domain IDs.
>
> > if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
> > setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
> > + else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE)
> > + setbits_le32(priv->base + GPR_REG0, PCIE_CLOCK_MODULE_EN);
> > + else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY)
> > + setbits_le32(priv->base + GPR_REG0, PCIE_PHY_APB_RST |
> > + PCIE_PHY_INIT_RST);
>
> Shouldn't the reset bits be cleared here ?
>
Although I can't find their reference in the TRM, as per Linux commit
[1], setting the reset bit is actually deassertion of PCIe PHY reset.
You can think of it like an active low signal.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5506018d3dec41e6678efb92b836586e9ee1d628
-Sumit
Re: [PATCH 2/7] reset: imx: Add support for i.MX8MP reset controller
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
>
> On 2/20/24 14:10, Sumit Garg wrote:
> > Pre-requisite to enable PCIe support on iMX8MP SoC.
>
> Please write a proper commit message .
>
How about the following?
Add support for i.MX8MP reset controller. It is required
to enable PCIe support on the iMX8MP SoC.
> > Signed-off-by: Sumit Garg
> > ---
> > drivers/reset/reset-imx7.c | 114 +
> > 1 file changed, 114 insertions(+)
> >
> > diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
> > index eaef2cc2cdf..c1de84dea8b 100644
> > --- a/drivers/reset/reset-imx7.c
> > +++ b/drivers/reset/reset-imx7.c
> > @@ -10,6 +10,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -252,6 +253,115 @@ static int imx7_reset_assert_imx8mq(struct reset_ctl
> > *rst)
> > return 0;
> > }
> >
> > +enum imx8mp_src_registers {
> > + SRC_SUPERMIX_RCR= 0x0018,
> > + SRC_AUDIOMIX_RCR= 0x001c,
> > + SRC_MLMIX_RCR = 0x0028,
> > + SRC_GPU2D_RCR = 0x0038,
> > + SRC_GPU3D_RCR = 0x003c,
> > + SRC_VPU_G1_RCR = 0x0048,
> > + SRC_VPU_G2_RCR = 0x004c,
> > + SRC_VPUVC8KE_RCR= 0x0050,
> > + SRC_NOC_RCR = 0x0054,
> > +};
>
> This seems copied from Linux, include Linux commit ID as of which this
> was imported from in commit message.
Do you expect imx8mp_src_registers to change? I expect them to be the
same, so does Linux commit ID add any value here?
-Sumit
Re: [PATCH 0/7] imx8mp: Enable PCIe/NVMe support
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
>
> On 2/20/24 14:10, Sumit Garg wrote:
> > pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
> > rather tied to quite old port of pcie_designware driver from Linux which
> > suffices only iMX6 specific needs.
> >
> > But currently we have the common DWC specific bits which alligns pretty
> > well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
> > bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
> > add support for other iMX8 variants to this driver.
> >
> > iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
> > can reuse the generic PHY infrastructure to power on PCIe PHY.
> >
> > Patch #1: Adds PCIe clocks support.
> > Patch #2: Adds i.MX8MP reset controller support.
> > Patch #3: Extend i.MX8MP power domain driver with PCIe support
> > Patch #4: Expose high performance PLL clock required for PCIe PHY
> >on verdin board.
> > Patch #5: Adds standalone PCIe PHY support for i.MX8MP SoC.
> > Patch #6: Adds DW PCIe controller support for iMX8MP SoC.
> > Patch #7: Enable PCIe/NVMe support for verdin board.
> >
> > Testing with this patch-set included:
> >
> > Verdin iMX8MP # pci enum
> > PCIE-0: Link up (Gen1-x1, Bus0)
> > Verdin iMX8MP #
> > Verdin iMX8MP # nvme scan
> > Verdin iMX8MP #
> > Verdin iMX8MP # nvme info
> > Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000720
> > Type: Hard Disk
> > Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
> > Verdin iMX8MP #
> > Verdin iMX8MP # load nvme 0 $loadaddr
> >
> > Sumit Garg (7):
> >clk: imx8mp: Add support for PCIe clocks
> >reset: imx: Add support for i.MX8MP reset controller
> >imx8mp: power-domain: Add PCIe support
> >imx8mp: power-domain: Expose high performance PLL clock
> >phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
> >pci: Add DW PCIe controller support for iMX8MP SoC
> >verdin-imx8mp_defconfig: Enable PCIe/NVMe support
> >
> > configs/verdin-imx8mp_defconfig | 9 +
> > drivers/clk/imx/clk-imx8mp.c | 6 +
> > drivers/pci/Kconfig | 8 +
> > drivers/pci/Makefile | 1 +
> > drivers/pci/pcie_dw_imx8.c| 348 ++
>
> You can call this pcie_dw_imx.c , the imx6 support can be converted over
> to that driver too I guess ?
Yeah I suppose that should be possible, let me rename it as pcie_dw_imx.c.
-Sumit
[PATCH] board: ti: rm-cfg: Update rm-cfg to reflect new resource reservation
With the latest TIFS firmware, an additional virtual interrupt and event is reserved for TIFS usage on am62x and am62ax devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Vishal Mahaveer --- board/ti/am62ax/rm-cfg.yaml | 8 board/ti/am62x/rm-cfg.yaml | 8 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml index 73e8e15f66..cbd087de79 100644 --- a/board/ti/am62ax/rm-cfg.yaml +++ b/board/ti/am62ax/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62A # @@ -519,13 +519,13 @@ rm-cfg: reserved: 0 - start_resource: 44 -num_resource: 36 +num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 -num_resource: 36 +num_resource: 35 type: 1802 host_id: 36 reserved: 0 @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 1038 -num_resource: 498 +num_resource: 497 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml index 725f7c83f0..26d99b03b8 100644 --- a/board/ti/am62x/rm-cfg.yaml +++ b/board/ti/am62x/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62X # @@ -513,13 +513,13 @@ rm-cfg: reserved: 0 - start_resource: 44 -num_resource: 36 +num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 -num_resource: 36 +num_resource: 35 type: 1802 host_id: 36 reserved: 0 @@ -555,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 -num_resource: 627 +num_resource: 626 type: 1805 host_id: 128 reserved: 0 -- 2.43.0
Re: [PATCH v3] test/py: saveenv: Add a test for saveenv command
On Tue, Feb 20, 2024 at 01:11:49PM +0530, Love Kumar wrote: > Add test case for saveenv command in non-JTAG bootmode which saves the > u-boot environment variables in persistent storage. > > Signed-off-by: Love Kumar Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH v3] test/py: reset: Add a test for reset command
On Tue, Feb 20, 2024 at 01:11:38PM +0530, Love Kumar wrote: > Add a test for reset commands which performs resetting of CPU, It does > COLD reset by default and WARM reset with -w option. > > Signed-off-by: Love Kumar Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH v1 5/7] toradex: common: Add sysinfo driver
On Tue, 2024-02-20 at 21:14 +0200, Svyatoslav Ryhel wrote:
> вт, 20 лют. 2024 р. о 20:29 Francesco Dolcini пише:
> >
> > From: Emanuele Ghidoli
> >
> > This commit introduces support for the Toradex sysinfo driver in U-Boot,
> > which uses information from Toradex config block to print correct
> > board model.
> > In case the Toradex config block is not present sysinfo prints the model
> > of the board provided by device tree removing per board specific prints.
> >
> > Signed-off-by: Emanuele Ghidoli
> > Signed-off-by: Francesco Dolcini
> > ---
> > arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 6 +++
> > arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 6 +++
> > .../dts/imx6dl-colibri-eval-v3-u-boot.dtsi | 4 ++
> > arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi | 4 ++
> > .../dts/imx6ull-colibri-eval-v3-u-boot.dtsi | 4 ++
> > .../arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi | 4 ++
> > .../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi | 4 ++
> > .../dts/imx8mp-verdin-wifi-dev-u-boot.dtsi | 4 ++
> > .../dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 4 ++
> > arch/arm/dts/tegra124-apalis-u-boot.dtsi | 12 +
> > arch/arm/dts/tegra20-colibri-u-boot.dtsi | 12 +
> > arch/arm/dts/tegra30-apalis-u-boot.dtsi | 12 +
> > arch/arm/dts/tegra30-colibri-u-boot.dtsi | 12 +
> > .../arm/dts/vf610-colibri-eval-v3-u-boot.dtsi | 4 ++
> > board/toradex/common/Kconfig | 1 +
> > board/toradex/common/tdx-common.c | 50 ---
> > 16 files changed, 136 insertions(+), 7 deletions(-)
> > create mode 100644 arch/arm/dts/tegra124-apalis-u-boot.dtsi
> > create mode 100644 arch/arm/dts/tegra20-colibri-u-boot.dtsi
> > create mode 100644 arch/arm/dts/tegra30-apalis-u-boot.dtsi
> > create mode 100644 arch/arm/dts/tegra30-colibri-u-boot.dtsi
> >
>
> Greetings! Thank you for contribution but may you at split patches
> according to SoC vendor at least? For imx, tegra and ti since it
> would be hard to both review and pick them to correct custodian
> trees.
I would assume for those urgent fixes to go through Tom directly to master.
Thanks!
> > diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
> > b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
> > index c54a59e89c5d..d73be74d2112 100644
> > --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
> > +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
> > @@ -3,6 +3,12 @@
> > * Copyright 2019 Toradex AG
> > */
> >
> > +/ {
> > + sysinfo {
> > + compatible = "toradex,sysinfo";
> > + };
> > +};
> > +
> > {
> > bootph-some-ram;
> > };
> > diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > index 6ab6b1f9ee69..60c4cd6fc01f 100644
> > --- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > @@ -3,6 +3,12 @@
> > * Copyright 2019 Toradex AG
> > */
> >
> > +/ {
> > + sysinfo {
> > + compatible = "toradex,sysinfo";
> > + };
> > +};
> > +
> > &{/imx8qx-pm} {
> >
> > bootph-some-ram;
> > diff --git a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
> > b/arch/arm/dts/imx6dl-colibri-eval-v3-u-
> > boot.dtsi
> > index 0eea4d1862ae..5a91d0aca204 100644
> > --- a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
> > +++ b/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
> > @@ -16,6 +16,10 @@
> > mmc0 =
> > mmc1 =
> > };
> > +
> > + sysinfo {
> > + compatible = "toradex,sysinfo";
> > + };
> > };
> >
> > {
> > diff --git a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
> > b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
> > index 3c6e503d043b..59412635420a 100644
> > --- a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
> > +++ b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
> > @@ -19,6 +19,10 @@
> > mmc1 =
> > mmc2 =
> > };
> > +
> > + sysinfo {
> > + compatible = "toradex,sysinfo";
> > + };
> > };
> >
> > {
> > diff --git a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
> > b/arch/arm/dts/imx6ull-colibri-eval-v3-u-
> > boot.dtsi
> > index 6823b42d4514..731814216e1f 100644
> > --- a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
> > +++ b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
> > @@ -9,6 +9,10 @@
> > usb0 = /* required for ums */
> > display0 =
> > };
> > +
> > + sysinfo {
> > + compatible = "toradex,sysinfo";
> > + };
> > };
> >
> > _uart1 {
> > diff --git a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
> > b/arch/arm/dts/imx7d-colibri-eval-v3-u-
> > boot.dtsi
> > index b2c12a413daf..68142769d360 100644
> > --- a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
> > +++ b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
> > @@ -11,6 +11,10 @@
> > mmc0 =
> > mmc1 =
Re: [PATCH v1 0/7] toradex: fix reset and hardware detection regressions
On Tue, 2024-02-20 at 19:29 +0100, Francesco Dolcini wrote:
> From: Francesco Dolcini
>
> This series fixes two regressions affecting multiple Toradex boards
> (i.MX, TI and TEGRA based) and targets the current master, e.g. v2024.04
> release.
>
> U-Boot `reset` command is broken on all Tordex i.MX6* based SoMs since
> v2023.07, this series fixes it enabling the `wdt-reboot` driver.
>
> Since v2024.04-rc1 reading the Toradex configuration block is not working
> properly anymore, the serial number and the hardware version are not read
> correctly, preventing the board from functioning correctly (wrong mac address,
> wrong DT, ...). This is fixed by reading the config block in `EVT_SETTINGS_R`
> and
> adding a toradex sysinfo driver. In addition to that, we now use a random mac
> address in case the config block is invalid.
>
>
> Reported-by: Sahaj Sarup
> Closes:
> https://lore.kernel.org/all/CAKZ1LvM45MB8N0CqgU+C7i9=bjb6kqntxwo2tv407hklwtc...@mail.gmail.com/
> Reported-by: Marcel Ziswiler
> Closes:
> https://lore.kernel.org/all/e40ed93bd8f371ec56b8fc451dcb458f3ce6dcba.ca...@toradex.com/
> Reported-by: Francesco Dolcini
> Closes: https://lore.kernel.org/all/ZY2ZDWAQuTlRjV9H@francesco-nb/
For the whole series:
Acked-by: Marcel Ziswiler
Tested-by: Marcel Ziswiler # Verdin iMX8M Plus
> Emanuele Ghidoli (6):
> toradex: Fix recursive call to checkboard
> toradex: Remove not necessary model prints from checkboard()
> toradex: common: Use SETTINGS_R event to read toradex config block
> arm: dts: Refactor device trees using "&{/aliases}" syntax
> toradex: common: Add sysinfo driver
> toradex: common: Use random mac address if toradex config block is
> missing
>
> Parth Pancholi (1):
> toradex: imx6*: fix reset using wdt-reboot driver
>
> arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 6 +
> arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 6 +
> .../dts/imx6dl-colibri-eval-v3-u-boot.dtsi | 28 +++-
> arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi | 36 +++--
> .../dts/imx6ull-colibri-eval-v3-u-boot.dtsi | 14 ++
> .../arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi | 14 +-
> .../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi | 16 +-
> .../dts/imx8mp-verdin-wifi-dev-u-boot.dtsi | 16 +-
> .../dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 4 +
> arch/arm/dts/tegra124-apalis-u-boot.dtsi | 12 ++
> arch/arm/dts/tegra20-colibri-u-boot.dtsi | 12 ++
> arch/arm/dts/tegra30-apalis-u-boot.dtsi | 12 ++
> arch/arm/dts/tegra30-colibri-u-boot.dtsi | 12 ++
> .../arm/dts/vf610-colibri-eval-v3-u-boot.dtsi | 4 +
> board/toradex/apalis-imx8/apalis-imx8.c | 10 --
> board/toradex/apalis-tk1/apalis-tk1.c | 7 -
> board/toradex/apalis_imx6/apalis_imx6.c | 21 ---
> board/toradex/apalis_t30/apalis_t30.c | 8 -
> .../toradex/colibri-imx6ull/colibri-imx6ull.c | 7 -
> board/toradex/colibri-imx8x/colibri-imx8x.c | 10 --
> board/toradex/colibri_imx6/colibri_imx6.c | 20 ---
> board/toradex/colibri_imx7/colibri_imx7.c | 8 -
> board/toradex/colibri_t20/colibri_t20.c | 10 --
> board/toradex/colibri_t30/colibri_t30.c | 7 -
> board/toradex/colibri_vf/colibri_vf.c | 10 --
> board/toradex/common/Kconfig | 1 +
> board/toradex/common/tdx-common.c | 137 +-
> board/toradex/common/tdx-common.h | 1 -
> configs/apalis-imx8_defconfig | 1 +
> configs/apalis-tk1_defconfig | 1 +
> configs/apalis_imx6_defconfig | 4 +
> configs/apalis_t30_defconfig | 1 +
> configs/colibri-imx6ull-emmc_defconfig | 4 +
> configs/colibri-imx6ull_defconfig | 4 +
> configs/colibri-imx8x_defconfig | 1 +
> configs/colibri_imx6_defconfig | 4 +
> configs/colibri_imx7_defconfig | 1 +
> configs/colibri_imx7_emmc_defconfig | 1 +
> configs/colibri_t20_defconfig | 1 +
> configs/colibri_t30_defconfig | 1 +
> configs/colibri_vf_defconfig | 1 +
> configs/verdin-am62_a53_defconfig | 1 +
> configs/verdin-am62_r5_defconfig | 1 +
> configs/verdin-imx8mm_defconfig | 1 +
> configs/verdin-imx8mp_defconfig | 1 +
> 45 files changed, 284 insertions(+), 194 deletions(-)
> create mode 100644 arch/arm/dts/tegra124-apalis-u-boot.dtsi
> create mode 100644 arch/arm/dts/tegra20-colibri-u-boot.dtsi
> create mode 100644 arch/arm/dts/tegra30-apalis-u-boot.dtsi
> create mode 100644 arch/arm/dts/tegra30-colibri-u-boot.dtsi
Re: [PATCH] arm64: zynqmp: Support semhosting boot method
On 2/20/24 14:18, Michal Simek wrote:
>
>
> On 2/20/24 19:43, Sean Anderson wrote:
>> On 2/20/24 13:24, Michal Simek wrote:
>>>
>>>
>>> On 2/16/24 17:09, Sean Anderson wrote:
On 2/16/24 11:03, Sean Anderson wrote:
> On 2/16/24 10:06, Michal Simek wrote:
>>
>>
>> On 2/16/24 14:48, Michal Simek wrote:
>>>
>>>
>>> On 2/15/24 20:31, Sean Anderson wrote:
On 2/15/24 14:08, Michal Simek wrote:
>
>
> On 2/15/24 18:19, Sean Anderson wrote:
>> Currently, when we boot from JTAG we try to boot U-Boot from RAM.
>> However, this is a bit tricky to time, since the debugger has to wait
>> for SPL to initialize RAM before it can load U-Boot. This can result
>> in
>> long waits, since occasionally initializing RAM (and other things in
>> psu_init) takes a long time to complete and the debugger must wait
>> for
>> this worst case.
>>
>> Support semihosting if it is enabled, as it lets U-Boot tell the
>> debugger when we are ready for the image. This means we don't have to
>> wait any more than necessary. We don't change the default config to
>> ensure we don't break compatibility with existing debuggers that
>> don't
>> expect us to hit semihosting breakpoints.
>>
>> Signed-off-by: Sean Anderson
>> ---
>>
>> arch/arm/mach-zynqmp/spl.c | 10 --
>> 1 file changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
>> index a0f35f36faa..5af735aa5ce 100644
>> --- a/arch/arm/mach-zynqmp/spl.c
>> +++ b/arch/arm/mach-zynqmp/spl.c
>> @@ -9,6 +9,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>>
>> @@ -66,6 +67,11 @@ void spl_board_init(void)
>> }
>> #endif
>>
>> +static u32 jtag_boot_device(void)
>> +{
>> + return semihosting_enabled() ? BOOT_DEVICE_SMH :
>> BOOT_DEVICE_RAM;
>> +}
>> +
>> void board_boot_order(u32 *spl_boot_list)
>> {
>> spl_boot_list[0] = spl_boot_device();
>> @@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list)
>> if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
>> spl_boot_list[1] = BOOT_DEVICE_MMC1;
>>
>> - spl_boot_list[2] = BOOT_DEVICE_RAM;
>> + spl_boot_list[2] = jtag_boot_device();
>> }
>>
>> u32 spl_boot_device(void)
>> @@ -97,7 +103,7 @@ u32 spl_boot_device(void)
>>
>> switch (bootmode) {
>> case JTAG_MODE:
>> - return BOOT_DEVICE_RAM;
>> + return jtag_boot_device();
>> #ifdef CONFIG_SPL_MMC
>> case SD_MODE1:
>> case SD1_LSHFT_MODE: /* not working on silicon v1 */
>
> Good timing. Can you please tell me how to test this? What's the
> setup?
> Which debugger are you using?
I am using OpenOCD with the patches at
https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2freview.openocd.org%2fc%2fopenocd%2f%2b%2f8133=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-afc15b07b0f91c910f832185958363d84f990a08
>>>
>>> I am trying it on the top of the latest git but getting issue with
>>> event block and no idea how to fix it.
>>>
>>> # sudo openocd -f
>>> /usr/local/share/openocd/scripts/interface/ftdi/digilent_jtag_hs3.cfg
>>> -f /usr/local/share/openocd/scripts/target/xilinx_zynqmp.cfg
>>> Open On-Chip Debugger 0.12.0+dev-01509-g6d288937cb2d (2024-02-16-12:22)
>>> Licensed under GNU GPL v2
>>> For bug reports, read
>>>
>>> https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=http%3a%2f%2fopenocd.org%2fdoc%2fdoxygen%2fbugs.html=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-f501ab9aa5516ff666e387e53598fd624398f1bc
>>> Info : auto-selecting first available session transport "jtag". To
>>> override use 'transport select '.
>>> wrong # args: should be "-event "
>>>
>>>
>>> Do you know how to fix it?
>>
>>
>> I actually bisect it and found that it is caused by
>> jtag: rewrite jim_jtag_configure() as COMMAND_HANDLER
>> ea2e26f7d521f5755b4bfda7bf12d99650277421
>
> Interesting. I have been testing with 0.12.
>
>> # sudo openocd -f
>> /usr/local/share/openocd/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg
>> -f
Re: [PATCH] arm64: zynqmp: Support semhosting boot method
On 2/20/24 19:43, Sean Anderson wrote:
On 2/20/24 13:24, Michal Simek wrote:
On 2/16/24 17:09, Sean Anderson wrote:
On 2/16/24 11:03, Sean Anderson wrote:
On 2/16/24 10:06, Michal Simek wrote:
On 2/16/24 14:48, Michal Simek wrote:
On 2/15/24 20:31, Sean Anderson wrote:
On 2/15/24 14:08, Michal Simek wrote:
On 2/15/24 18:19, Sean Anderson wrote:
Currently, when we boot from JTAG we try to boot U-Boot from RAM.
However, this is a bit tricky to time, since the debugger has to wait
for SPL to initialize RAM before it can load U-Boot. This can result in
long waits, since occasionally initializing RAM (and other things in
psu_init) takes a long time to complete and the debugger must wait for
this worst case.
Support semihosting if it is enabled, as it lets U-Boot tell the
debugger when we are ready for the image. This means we don't have to
wait any more than necessary. We don't change the default config to
ensure we don't break compatibility with existing debuggers that don't
expect us to hit semihosting breakpoints.
Signed-off-by: Sean Anderson
---
arch/arm/mach-zynqmp/spl.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index a0f35f36faa..5af735aa5ce 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
@@ -66,6 +67,11 @@ void spl_board_init(void)
}
#endif
+static u32 jtag_boot_device(void)
+{
+ return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
+}
+
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
@@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list)
if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
spl_boot_list[1] = BOOT_DEVICE_MMC1;
- spl_boot_list[2] = BOOT_DEVICE_RAM;
+ spl_boot_list[2] = jtag_boot_device();
}
u32 spl_boot_device(void)
@@ -97,7 +103,7 @@ u32 spl_boot_device(void)
switch (bootmode) {
case JTAG_MODE:
- return BOOT_DEVICE_RAM;
+ return jtag_boot_device();
#ifdef CONFIG_SPL_MMC
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
Good timing. Can you please tell me how to test this? What's the setup?
Which debugger are you using?
I am using OpenOCD with the patches at
https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2freview.openocd.org%2fc%2fopenocd%2f%2b%2f8133=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-afc15b07b0f91c910f832185958363d84f990a08
I am trying it on the top of the latest git but getting issue with event block
and no idea how to fix it.
# sudo openocd -f
/usr/local/share/openocd/scripts/interface/ftdi/digilent_jtag_hs3.cfg -f
/usr/local/share/openocd/scripts/target/xilinx_zynqmp.cfg
Open On-Chip Debugger 0.12.0+dev-01509-g6d288937cb2d (2024-02-16-12:22)
Licensed under GNU GPL v2
For bug reports, read
https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=http%3a%2f%2fopenocd.org%2fdoc%2fdoxygen%2fbugs.html=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-f501ab9aa5516ff666e387e53598fd624398f1bc
Info : auto-selecting first available session transport "jtag". To override use
'transport select '.
wrong # args: should be "-event "
Do you know how to fix it?
I actually bisect it and found that it is caused by
jtag: rewrite jim_jtag_configure() as COMMAND_HANDLER
ea2e26f7d521f5755b4bfda7bf12d99650277421
Interesting. I have been testing with 0.12.
# sudo openocd -f
/usr/local/share/openocd/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg -f
/usr/local/share/openocd/scripts/target/xilinx_zynqmp.cfg
FWIW after installing the udev rules I do not need sudo
Open On-Chip Debugger 0.12.0+dev-01512-g214206ebb972 (2024-02-16-15:38)
Licensed under GNU GPL v2
For bug reports, read
https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=http%3a%2f%2fopenocd.org%2fdoc%2fdoxygen%2fbugs.html=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-f501ab9aa5516ff666e387e53598fd624398f1bc
none separate
Info : auto-selecting first available session transport "jtag". To override use
'transport select '.
Info : Hardware thread awareness created
boot_apu
Info : Listening on port for tcl connections
Info : Listening on port for telnet connections
Warn : An adapter speed is not selected in the init scripts. OpenOCD will try
to run the adapter at very low speed (100 kHz).
Warn : To remove this warnings and achieve reasonable communication speed with the target, set
"adapter speed" or "jtag_rclk" in the init scripts.
Info : clock speed 100 kHz
Info : TAP uscale.tap does not have valid IDCODE (idcode=0x48e70126)
Info : JTAG tap:
Re: [PATCH v1 5/7] toradex: common: Add sysinfo driver
вт, 20 лют. 2024 р. о 20:29 Francesco Dolcini пише:
>
> From: Emanuele Ghidoli
>
> This commit introduces support for the Toradex sysinfo driver in U-Boot,
> which uses information from Toradex config block to print correct
> board model.
> In case the Toradex config block is not present sysinfo prints the model
> of the board provided by device tree removing per board specific prints.
>
> Signed-off-by: Emanuele Ghidoli
> Signed-off-by: Francesco Dolcini
> ---
> arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi| 6 +++
> arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 6 +++
> .../dts/imx6dl-colibri-eval-v3-u-boot.dtsi| 4 ++
> arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi| 4 ++
> .../dts/imx6ull-colibri-eval-v3-u-boot.dtsi | 4 ++
> .../arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi | 4 ++
> .../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi| 4 ++
> .../dts/imx8mp-verdin-wifi-dev-u-boot.dtsi| 4 ++
> .../dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 4 ++
> arch/arm/dts/tegra124-apalis-u-boot.dtsi | 12 +
> arch/arm/dts/tegra20-colibri-u-boot.dtsi | 12 +
> arch/arm/dts/tegra30-apalis-u-boot.dtsi | 12 +
> arch/arm/dts/tegra30-colibri-u-boot.dtsi | 12 +
> .../arm/dts/vf610-colibri-eval-v3-u-boot.dtsi | 4 ++
> board/toradex/common/Kconfig | 1 +
> board/toradex/common/tdx-common.c | 50 ---
> 16 files changed, 136 insertions(+), 7 deletions(-)
> create mode 100644 arch/arm/dts/tegra124-apalis-u-boot.dtsi
> create mode 100644 arch/arm/dts/tegra20-colibri-u-boot.dtsi
> create mode 100644 arch/arm/dts/tegra30-apalis-u-boot.dtsi
> create mode 100644 arch/arm/dts/tegra30-colibri-u-boot.dtsi
>
Greetings! Thank you for contribution but may you at split patches
according to SoC vendor at least? For imx, tegra and ti since it
would be hard to both review and pick them to correct custodian
trees.
> diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
> b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
> index c54a59e89c5d..d73be74d2112 100644
> --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
> +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
> @@ -3,6 +3,12 @@
> * Copyright 2019 Toradex AG
> */
>
> +/ {
> + sysinfo {
> + compatible = "toradex,sysinfo";
> + };
> +};
> +
> {
> bootph-some-ram;
> };
> diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> index 6ab6b1f9ee69..60c4cd6fc01f 100644
> --- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> @@ -3,6 +3,12 @@
> * Copyright 2019 Toradex AG
> */
>
> +/ {
> + sysinfo {
> + compatible = "toradex,sysinfo";
> + };
> +};
> +
> &{/imx8qx-pm} {
>
> bootph-some-ram;
> diff --git a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
> b/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
> index 0eea4d1862ae..5a91d0aca204 100644
> --- a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
> +++ b/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
> @@ -16,6 +16,10 @@
> mmc0 =
> mmc1 =
> };
> +
> + sysinfo {
> + compatible = "toradex,sysinfo";
> + };
> };
>
> {
> diff --git a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
> b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
> index 3c6e503d043b..59412635420a 100644
> --- a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
> +++ b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
> @@ -19,6 +19,10 @@
> mmc1 =
> mmc2 =
> };
> +
> + sysinfo {
> + compatible = "toradex,sysinfo";
> + };
> };
>
> {
> diff --git a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
> b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
> index 6823b42d4514..731814216e1f 100644
> --- a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
> +++ b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
> @@ -9,6 +9,10 @@
> usb0 = /* required for ums */
> display0 =
> };
> +
> + sysinfo {
> + compatible = "toradex,sysinfo";
> + };
> };
>
> _uart1 {
> diff --git a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
> b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
> index b2c12a413daf..68142769d360 100644
> --- a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
> +++ b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
> @@ -11,6 +11,10 @@
> mmc0 =
> mmc1 =
> };
> +
> + sysinfo {
> + compatible = "toradex,sysinfo";
> + };
> };
>
> {
> diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
> b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
> index 515f195ab759..38db56059d69 100644
> --- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
> @@ -12,6 +12,10 @@
> eeprom2 =
Re: [PATCH v1] include: android_bootloader_message.h: sync with AOSP upstream
Hi Sam,
On Tue, Feb 20, 2024 at 7:29 PM Sam Protsenko
wrote:
>
> On Mon, Feb 19, 2024 at 4:16 AM Igor Opaniuk wrote:
> >
> > This takes the latest changes from AOSP from [1][2] (as this
> > header was split on two) with minimal changes (this could lead
> > to warnings reported by checkpatch).
>
> Do we want to maybe follow that and also carry two different headers
> in U-Boot? Or it doesn't make much sense? I'm thinking in terms of
> future portability mostly: how easy it's to update this header right
> now, and how easy it's going to be further. I didn't form any opinion
> on that, hence asking.
The problem is licensing. android_bootloader_message.h was
re-licensed by Alex Deymo from Google under BSD-3-Clause,
which is GPLv2 compatible. I'm not sure it's legally correct to pull
boot_control_definition.h from AOSP licensed under Apache as a
separate file.
>
> Another thing: are you sure that changing only the header won't break
> anything in U-Boot .c files that use this header?
I've tested both ab_select and avb verify in QEMU. Or do you mean
something else additionally should be tested?
>
> >
> > Some local changes have been applied:
>
> Is it possible to split this work into two patches:
> 1. Bring the original changes only
> 2. Apply all necessary changes for U-Boot
>
> Or does it break the build, etc? Again, thinking in terms of
> portability easiness, and not sure which approach is better -- just
> asking basically.
Yeah, that's the problem, as splitting this on two commits
will lead to the first one reporting warnings/notes.
>
> > 1. Enable static_assert() for defined structures to be sure
> > that all of them have correct sizes.
> > 2. Adjuste types in bootloader_control structure with bitfields
>
> Adjuste -> adjust
Will fix, thanks!
>
> > (uint8_t -> uint16_t). It seems that gcc just doesn't like bitfields
>
> I wonder if all those extra changes can be upstreamed back to AOSP?
> Ideally we'd want to just copy those headers over from AOSP to U-Boot
> with no changes, would make the porting work easier. What are your
> thoughts on that?
Technically we can, I was planning to do that.
>
> > that cross the width of the type. Changing the type doesn't change
> > the layout though.
> > This addresses this gcc note:
> > In file included from boot/android_ab.c:7:
> > include/android_bootloader_message.h:230:1: note: offset of packed
> > bit-field ‘merge_status’ has changed in GCC 4.4
> > 230 | } __attribute__((packed));
> >
> > [1]
> > https://android.googlesource.com/platform/bootable/recovery/+/main/bootloader_message/include/bootloader_message/bootloader_message.h
> > [2]
> > https://android.googlesource.com/platform/hardware/interfaces/+/main/boot/1.1/default/boot_control/include/private/boot_control_definition.h
> >
> > CC: Alex Deymo
> > CC: Sam Protsenko
> > CC: Eugeniu Rosca
> > CC: Simon Glass
> > Signed-off-by: Igor Opaniuk
> > ---
> >
> > include/android_bootloader_message.h | 104 +++
> > 1 file changed, 92 insertions(+), 12 deletions(-)
> >
> > diff --git a/include/android_bootloader_message.h
> > b/include/android_bootloader_message.h
> > index 286d7ab0f31..75198fc9dc2 100644
> > --- a/include/android_bootloader_message.h
> > +++ b/include/android_bootloader_message.h
> > @@ -21,17 +21,22 @@
> > * stddef.h
> > */
> > #include
> > +#include
> > #endif
> >
> > // Spaces used by misc partition are as below:
> > // 0 - 2K For bootloader_message
> > // 2K - 16KUsed by Vendor's bootloader (the 2K - 4K range may be
> > optionally used
> > // as bootloader_message_ab struct)
> > -// 16K - 64KUsed by uncrypt and recovery to store wipe_package for A/B
> > devices
> > +// 16K - 32KUsed by uncrypt and recovery to store wipe_package for A/B
> > devices
> > +// 32K - 64KSystem space, used for miscellanious AOSP features. See
> > below.
> > // Note that these offsets are admitted by bootloader,recovery and
> > uncrypt, so they
> > // are not configurable without changing all of them.
> > static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0;
> > +static const size_t VENDOR_SPACE_OFFSET_IN_MISC = 2 * 1024;
> > static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024;
> > +static const size_t SYSTEM_SPACE_OFFSET_IN_MISC = 32 * 1024;
> > +static const size_t SYSTEM_SPACE_SIZE_IN_MISC = 32 * 1024;
> >
> > /* Bootloader Message (2-KiB)
> > *
> > @@ -81,24 +86,67 @@ struct bootloader_message {
> > char reserved[1184];
> > };
> >
> > +// Holds Virtual A/B merge status information. Current version is 1. New
> > fields
> > +// must be added to the end.
> > +struct misc_virtual_ab_message {
> > + uint8_t version;
> > + uint32_t magic;
> > + uint8_t merge_status; // IBootControl 1.1, MergeStatus enum.
> > + uint8_t source_slot; // Slot number when merge_status was written.
> > + uint8_t reserved[57];
> > +} __attribute__((packed));
> > +
> > +struct misc_memtag_message {
> > + uint8_t
Re: [PATCH] arm64: zynqmp: Support semhosting boot method
On 2/20/24 13:24, Michal Simek wrote:
>
>
> On 2/16/24 17:09, Sean Anderson wrote:
>> On 2/16/24 11:03, Sean Anderson wrote:
>>> On 2/16/24 10:06, Michal Simek wrote:
On 2/16/24 14:48, Michal Simek wrote:
>
>
> On 2/15/24 20:31, Sean Anderson wrote:
>> On 2/15/24 14:08, Michal Simek wrote:
>>>
>>>
>>> On 2/15/24 18:19, Sean Anderson wrote:
Currently, when we boot from JTAG we try to boot U-Boot from RAM.
However, this is a bit tricky to time, since the debugger has to wait
for SPL to initialize RAM before it can load U-Boot. This can result in
long waits, since occasionally initializing RAM (and other things in
psu_init) takes a long time to complete and the debugger must wait for
this worst case.
Support semihosting if it is enabled, as it lets U-Boot tell the
debugger when we are ready for the image. This means we don't have to
wait any more than necessary. We don't change the default config to
ensure we don't break compatibility with existing debuggers that don't
expect us to hit semihosting breakpoints.
Signed-off-by: Sean Anderson
---
arch/arm/mach-zynqmp/spl.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index a0f35f36faa..5af735aa5ce 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
@@ -66,6 +67,11 @@ void spl_board_init(void)
}
#endif
+static u32 jtag_boot_device(void)
+{
+ return semihosting_enabled() ? BOOT_DEVICE_SMH :
BOOT_DEVICE_RAM;
+}
+
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
@@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list)
if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
spl_boot_list[1] = BOOT_DEVICE_MMC1;
- spl_boot_list[2] = BOOT_DEVICE_RAM;
+ spl_boot_list[2] = jtag_boot_device();
}
u32 spl_boot_device(void)
@@ -97,7 +103,7 @@ u32 spl_boot_device(void)
switch (bootmode) {
case JTAG_MODE:
- return BOOT_DEVICE_RAM;
+ return jtag_boot_device();
#ifdef CONFIG_SPL_MMC
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
>>>
>>> Good timing. Can you please tell me how to test this? What's the setup?
>>> Which debugger are you using?
>>
>> I am using OpenOCD with the patches at
>> https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2freview.openocd.org%2fc%2fopenocd%2f%2b%2f8133=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-afc15b07b0f91c910f832185958363d84f990a08
>>
>
> I am trying it on the top of the latest git but getting issue with event
> block and no idea how to fix it.
>
> # sudo openocd -f
> /usr/local/share/openocd/scripts/interface/ftdi/digilent_jtag_hs3.cfg -f
> /usr/local/share/openocd/scripts/target/xilinx_zynqmp.cfg
> Open On-Chip Debugger 0.12.0+dev-01509-g6d288937cb2d (2024-02-16-12:22)
> Licensed under GNU GPL v2
> For bug reports, read
>
> https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=http%3a%2f%2fopenocd.org%2fdoc%2fdoxygen%2fbugs.html=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-f501ab9aa5516ff666e387e53598fd624398f1bc
> Info : auto-selecting first available session transport "jtag". To
> override use 'transport select '.
> wrong # args: should be "-event "
>
>
> Do you know how to fix it?
I actually bisect it and found that it is caused by
jtag: rewrite jim_jtag_configure() as COMMAND_HANDLER
ea2e26f7d521f5755b4bfda7bf12d99650277421
>>>
>>> Interesting. I have been testing with 0.12.
>>>
# sudo openocd -f
/usr/local/share/openocd/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg
-f /usr/local/share/openocd/scripts/target/xilinx_zynqmp.cfg
>>>
>>> FWIW after installing the udev rules I do not need sudo
>>>
Open On-Chip Debugger 0.12.0+dev-01512-g214206ebb972 (2024-02-16-15:38)
Licensed under GNU GPL v2
For bug reports, read
[PATCH V2 4/5] board: beagle: beagleplay: Configure debounce registers
Configure the debounce configuration that makes sense for BeaglePlay
usage model.
Signed-off-by: Nishanth Menon
---
Changes since V1:
* No change
V1: https://lore.kernel.org/r/20240212155332.541949-5...@ti.com
board/beagle/beagleplay/beagleplay.c | 24
1 file changed, 24 insertions(+)
diff --git a/board/beagle/beagleplay/beagleplay.c
b/board/beagle/beagleplay/beagleplay.c
index 2adb2517ef00..fe1c4f920329 100644
--- a/board/beagle/beagleplay/beagleplay.c
+++ b/board/beagle/beagleplay/beagleplay.c
@@ -59,8 +59,32 @@ static void crystal_32k_enable(void)
}
}
+static void debounce_configure(void)
+{
+ /* Configure debounce one time from R5 */
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ /*
+* Setup debounce time registers.
+* arbitrary values. Times are approx
+*/
+ /* 1.9ms debounce @ 32k */
+ writel(0x1, CTRLMMR_DBOUNCE_CFG(1));
+ /* 5ms debounce @ 32k */
+ writel(0x5, CTRLMMR_DBOUNCE_CFG(2));
+ /* 20ms debounce @ 32k */
+ writel(0x14, CTRLMMR_DBOUNCE_CFG(3));
+ /* 46ms debounce @ 32k */
+ writel(0x18, CTRLMMR_DBOUNCE_CFG(4));
+ /* 100ms debounce @ 32k */
+ writel(0x1c, CTRLMMR_DBOUNCE_CFG(5));
+ /* 156ms debounce @ 32k */
+ writel(0x1f, CTRLMMR_DBOUNCE_CFG(6));
+ }
+}
+
void spl_board_init(void)
{
crystal_32k_enable();
+ debounce_configure();
}
#endif
--
2.43.0
[PATCH V2 3/5] arm: mach-k3: am62: Add Debounce configuration register definitions
Add the Debounce configuration registers that need to be configured one time for the platform for the entire SoC. Signed-off-by: Nishanth Menon --- Changes since V1: * Fix 4080 to 0x4080 V1: https://lore.kernel.org/r/20240212155332.541949-4...@ti.com arch/arm/mach-k3/include/mach/am62_hardware.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 54380f36e161..4cf7778a89ee 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -75,6 +75,9 @@ #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170) +/* Debounce register configuration */ +#define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4)) + #define ROM_EXTENDED_BOOT_DATA_INFO0x43c3f1e0 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c3 -- 2.43.0
[PATCH V2 5/5] board: beagle: beagleplay: env: Drop usb and pxe as boot targets
We had enabled USB and network pxe boot with the hope to get it all merged on time. However, it has not panned out. Drop usb and pxe boot else bootflow scan -l throws in: a) Unknown uclass 'usb' in label b) Crashes when attempting pxe - cpsw/mdio driver apparently has missing error handling of what ever form. This is the one that Jan noticed in his log. We can enable these on a later date once things are working. Cc: Roger Quadros Reported-by: Jan Kiszka Closes: https://lore.kernel.org/all/782ea2c0-eef5-478d-a122-cc6e2d066...@siemens.com/ Signed-off-by: Nishanth Menon --- - New patch in V2 of the series. board/beagle/beagleplay/beagleplay.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env index 4f0a94a8113e..db737e069b58 100644 --- a/board/beagle/beagleplay/beagleplay.env +++ b/board/beagle/beagleplay/beagleplay.env @@ -14,6 +14,6 @@ boot=mmc mmcdev=1 bootpart=1:1 bootdir=/boot -boot_targets=mmc1 mmc0 usb pxe +boot_targets=mmc1 mmc0 bootmeths=script extlinux efi pxe rd_spec=- -- 2.43.0
[PATCH V2 0/5] board: beagle: Enable 32k and debounce configuration and fixups
Hi, Rev 2 of the series. This is a follow up from [1] - Without the 32k crystal configuration, wlan doesn't work. Debounce is needed for HDMI Hot plug detect(hpd) gpio interrupt not storming. At least the 32k configuration has been done for toradex and phytec boards, follow similar model of programming. Series is now based off master branch. Bootlog: https://gist.github.com/nmenon/75df38bee907785d1d78d1ec4abd7304 Changes from V2: - Removed depedency on [2] - depending on which way the merge sequence goes, one of the series will need a rebase. - Added a patch for a bug that Jan noticed - Fixup for the fat finger missing 0x in 0x4080 :( V1: https://lore.kernel.org/all/20240212155332.541949-1...@ti.com/ Nishanth Menon : board: beagle: beagleplay: Enable 32k crystal configs: am62x_beagleplay_r5_defconfig: Enable SPL_BOARD_INIT arm: mach-k3: am62: Add Debounce configuration register definitions board: beagle: beagleplay: Configure debounce registers board: beagle: beagleplay: env: Drop usb and pxe as boot targets arch/arm/mach-k3/include/mach/am62_hardware.h | 3 + board/beagle/beagleplay/beagleplay.c | 61 +++ board/beagle/beagleplay/beagleplay.env| 2 +- configs/am62x_beagleplay_r5_defconfig | 1 + 4 files changed, 66 insertions(+), 1 deletion(-) base-commit: 3e6f2a94bfc25f1782ce2d45db27f47ec781feb1 [1] https://lore.kernel.org/u-boot/20230725185253.2123433-4...@ti.com/ [2] https://lore.kernel.org/u-boot/20240212194726.1093771-1...@ti.com/ -- 2.43.0
[PATCH V2 1/5] board: beagle: beagleplay: Enable 32k crystal
Enable the external 32k crystal similar to that found on other
production AM62X board. The trim settings for the crystal is board
dependent, so the sequences tend to be board specific. Since this is
a configuration that needs to be done prior to DM managing the system
and all other muxes get set, do the same from R5 context.
Tested-by: Robert Nelson
Signed-off-by: Nishanth Menon
---
Changes from V1:
* Added Robert's tested by.
V1: https://lore.kernel.org/r/20240212155332.541949-2...@ti.com
board/beagle/beagleplay/beagleplay.c | 37
1 file changed, 37 insertions(+)
diff --git a/board/beagle/beagleplay/beagleplay.c
b/board/beagle/beagleplay/beagleplay.c
index 1c376dea372f..2adb2517ef00 100644
--- a/board/beagle/beagleplay/beagleplay.c
+++ b/board/beagle/beagleplay/beagleplay.c
@@ -11,6 +11,8 @@
#include
#include
+#include
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -27,3 +29,38 @@ int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+
+/*
+ * Enable the 32k Crystal: needed for accurate 32k clock
+ * and external clock sources such as wlan 32k input clock
+ * supplied from the SoC to the wlan chip.
+ *
+ * The trim setup can be very highly board type specific choice of the crystal
+ * So this is done in the board file, though, in this case, no specific trim
+ * is necessary.
+ */
+static void crystal_32k_enable(void)
+{
+ /* Only mess with 32k at the start of boot from R5 */
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ /*
+* We have external 32k crystal, so lets enable it (0x0)
+* and disable bypass (0x0)
+*/
+ writel(0x0, MCU_CTRL_LFXOSC_CTRL);
+
+ /* Add any crystal specific TRIM needed here.. */
+
+ /* Make sure to mux the SoC 32k from the crystal */
+ writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
+ MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
+ }
+}
+
+void spl_board_init(void)
+{
+ crystal_32k_enable();
+}
+#endif
--
2.43.0
[PATCH V2 2/5] configs: am62x_beagleplay_r5_defconfig: Enable SPL_BOARD_INIT
Enable CONFIG_SPL_BOARD_INIT to configure the 32k crystal. Signed-off-by: Nishanth Menon --- Changes since V1: * No change V1: https://lore.kernel.org/r/20240212155332.541949-3...@ti.com configs/am62x_beagleplay_r5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index 2f3264b7ede6..9413c859870f 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y -- 2.43.0
[PATCH v1 6/7] toradex: common: Use random mac address if toradex config block is missing
From: Emanuele Ghidoli
Set CONFIG_NET_RANDOM_ETHADDR=y, which sets random eth address in
case there is no toradex config block programmed.
In case of missing toradex config block the generated mac address was
always the same, linked to serial number 0.
Use random generated mac address instead.
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Francesco Dolcini
---
board/toradex/common/tdx-common.c | 1 -
configs/apalis-imx8_defconfig | 1 +
configs/apalis-tk1_defconfig | 1 +
configs/apalis_imx6_defconfig | 1 +
configs/apalis_t30_defconfig | 1 +
configs/colibri-imx6ull-emmc_defconfig | 1 +
configs/colibri-imx6ull_defconfig | 1 +
configs/colibri-imx8x_defconfig| 1 +
configs/colibri_imx6_defconfig | 1 +
configs/colibri_imx7_defconfig | 1 +
configs/colibri_imx7_emmc_defconfig| 1 +
configs/colibri_t20_defconfig | 1 +
configs/colibri_t30_defconfig | 1 +
configs/colibri_vf_defconfig | 1 +
configs/verdin-am62_a53_defconfig | 1 +
configs/verdin-am62_r5_defconfig | 1 +
configs/verdin-imx8mm_defconfig| 1 +
configs/verdin-imx8mp_defconfig| 1 +
18 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/board/toradex/common/tdx-common.c
b/board/toradex/common/tdx-common.c
index 1f3253f4222e..9f09788137d5 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -126,7 +126,6 @@ static int settings_r(void)
if (read_tdx_cfg_block()) {
printf("MISSING TORADEX CONFIG BLOCK\n");
- get_mac_from_serial(tdx_serial, _eth_addr);
/* Board can run even if config block is not present */
return 0;
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index 982098d81420..da3b0e254899 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -52,6 +52,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_TFTP_TSIZE=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 6ed3898b60c3..20c9c06cdeac 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -52,6 +52,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_TFTP_TSIZE=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 05ff6fa115ce..492550607035 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -75,6 +75,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_USE_IPADDR=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 0a27509a97e6..03a1f2c23906 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -45,6 +45,7 @@ CONFIG_OF_LIVE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_TFTP_TSIZE=y
diff --git a/configs/colibri-imx6ull-emmc_defconfig
b/configs/colibri-imx6ull-emmc_defconfig
index 285fed9e4faf..2b04855770ab 100644
--- a/configs/colibri-imx6ull-emmc_defconfig
+++ b/configs/colibri-imx6ull-emmc_defconfig
@@ -51,6 +51,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_TFTP_TSIZE=y
diff --git a/configs/colibri-imx6ull_defconfig
b/configs/colibri-imx6ull_defconfig
index a8a633063d00..959930cf2e31 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -60,6 +60,7 @@ CONFIG_ENV_RANGE=0x8
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_TFTP_TSIZE=y
diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig
index aa18d28d3e6d..88928b0e4bc5 100644
--- a/configs/colibri-imx8x_defconfig
+++ b/configs/colibri-imx8x_defconfig
@@ -52,6 +52,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_TFTP_TSIZE=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 70cb79531e92..55c71a000d00 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -74,6 +74,7 @@
[PATCH v1 7/7] toradex: imx6*: fix reset using wdt-reboot driver
From: Parth Pancholi
commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()")
introduced a regression that 'reset' command unable to reset
imx6 and imx6ull based Toradex's modules in the u-boot.
This change enables a watchdog-based sysreset driver for
Toradex's colibri-imx6, colibri-imx6ull (with nand and emmc)
and apalis-imx6 which solves the reset command regression on
these modules.
Fixes: 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()")
Signed-off-by: Parth Pancholi
Signed-off-by: Francesco Dolcini
---
arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi | 6 ++
arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi | 6 ++
arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi | 10 ++
configs/apalis_imx6_defconfig| 3 +++
configs/colibri-imx6ull-emmc_defconfig | 3 +++
configs/colibri-imx6ull_defconfig| 3 +++
configs/colibri_imx6_defconfig | 3 +++
7 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
b/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
index 5a91d0aca204..44baaa803243 100644
--- a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
@@ -20,6 +20,12 @@
sysinfo {
compatible = "toradex,sysinfo";
};
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ bootph-pre-ram;
+ };
};
{
diff --git a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
index 59412635420a..103605ac930d 100644
--- a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
+++ b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
@@ -23,6 +23,12 @@
sysinfo {
compatible = "toradex,sysinfo";
};
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ bootph-pre-ram;
+ };
};
{
diff --git a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
index 731814216e1f..8494b1a2c603 100644
--- a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
+++ b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
@@ -13,6 +13,12 @@
sysinfo {
compatible = "toradex,sysinfo";
};
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ bootph-pre-ram;
+ };
};
_uart1 {
@@ -58,3 +64,7 @@
};
};
};
+
+ {
+ bootph-pre-ram;
+};
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 492550607035..fae3dc322471 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -96,6 +96,8 @@ CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_MXC_I2C3_SPEED=40
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
@@ -113,6 +115,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SCSI=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
diff --git a/configs/colibri-imx6ull-emmc_defconfig
b/configs/colibri-imx6ull-emmc_defconfig
index 2b04855770ab..c4ecdc03e2a8 100644
--- a/configs/colibri-imx6ull-emmc_defconfig
+++ b/configs/colibri-imx6ull-emmc_defconfig
@@ -69,6 +69,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x8110
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
@@ -83,6 +85,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
diff --git a/configs/colibri-imx6ull_defconfig
b/configs/colibri-imx6ull_defconfig
index 959930cf2e31..9c68d96b2fd7 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -80,6 +80,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x8110
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
@@ -100,6 +102,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 55c71a000d00..74c54011989c 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -22,6 +22,8 @@ CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_LOAD_ADDR=0x1420
CONFIG_SYS_MEMTEST_START=0x1000
@@ -109,6 +111,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y
[PATCH v1 5/7] toradex: common: Add sysinfo driver
From: Emanuele Ghidoli
This commit introduces support for the Toradex sysinfo driver in U-Boot,
which uses information from Toradex config block to print correct
board model.
In case the Toradex config block is not present sysinfo prints the model
of the board provided by device tree removing per board specific prints.
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Francesco Dolcini
---
arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi| 6 +++
arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 6 +++
.../dts/imx6dl-colibri-eval-v3-u-boot.dtsi| 4 ++
arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi| 4 ++
.../dts/imx6ull-colibri-eval-v3-u-boot.dtsi | 4 ++
.../arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi | 4 ++
.../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi| 4 ++
.../dts/imx8mp-verdin-wifi-dev-u-boot.dtsi| 4 ++
.../dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 4 ++
arch/arm/dts/tegra124-apalis-u-boot.dtsi | 12 +
arch/arm/dts/tegra20-colibri-u-boot.dtsi | 12 +
arch/arm/dts/tegra30-apalis-u-boot.dtsi | 12 +
arch/arm/dts/tegra30-colibri-u-boot.dtsi | 12 +
.../arm/dts/vf610-colibri-eval-v3-u-boot.dtsi | 4 ++
board/toradex/common/Kconfig | 1 +
board/toradex/common/tdx-common.c | 50 ---
16 files changed, 136 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/dts/tegra124-apalis-u-boot.dtsi
create mode 100644 arch/arm/dts/tegra20-colibri-u-boot.dtsi
create mode 100644 arch/arm/dts/tegra30-apalis-u-boot.dtsi
create mode 100644 arch/arm/dts/tegra30-colibri-u-boot.dtsi
diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
index c54a59e89c5d..d73be74d2112 100644
--- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
@@ -3,6 +3,12 @@
* Copyright 2019 Toradex AG
*/
+/ {
+ sysinfo {
+ compatible = "toradex,sysinfo";
+ };
+};
+
{
bootph-some-ram;
};
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
index 6ab6b1f9ee69..60c4cd6fc01f 100644
--- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
@@ -3,6 +3,12 @@
* Copyright 2019 Toradex AG
*/
+/ {
+ sysinfo {
+ compatible = "toradex,sysinfo";
+ };
+};
+
&{/imx8qx-pm} {
bootph-some-ram;
diff --git a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
b/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
index 0eea4d1862ae..5a91d0aca204 100644
--- a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
@@ -16,6 +16,10 @@
mmc0 =
mmc1 =
};
+
+ sysinfo {
+ compatible = "toradex,sysinfo";
+ };
};
{
diff --git a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
index 3c6e503d043b..59412635420a 100644
--- a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
+++ b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
@@ -19,6 +19,10 @@
mmc1 =
mmc2 =
};
+
+ sysinfo {
+ compatible = "toradex,sysinfo";
+ };
};
{
diff --git a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
index 6823b42d4514..731814216e1f 100644
--- a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
+++ b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
@@ -9,6 +9,10 @@
usb0 = /* required for ums */
display0 =
};
+
+ sysinfo {
+ compatible = "toradex,sysinfo";
+ };
};
_uart1 {
diff --git a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
index b2c12a413daf..68142769d360 100644
--- a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
@@ -11,6 +11,10 @@
mmc0 =
mmc1 =
};
+
+ sysinfo {
+ compatible = "toradex,sysinfo";
+ };
};
{
diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
index 515f195ab759..38db56059d69 100644
--- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
@@ -12,6 +12,10 @@
eeprom2 = _display_adapter;
};
+ sysinfo {
+ compatible = "toradex,sysinfo";
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
index 67f1d45ce269..03f211d5f7d3 100644
--- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
@@ -12,6 +12,10 @@
eeprom2 =
[PATCH v1 3/7] toradex: common: Use SETTINGS_R event to read toradex config block
From: Emanuele Ghidoli
Use SETTINGS_R event to read toradex config block and checkboard()
to print board info.
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Francesco Dolcini
---
board/toradex/common/tdx-common.c | 92 ++-
1 file changed, 54 insertions(+), 38 deletions(-)
diff --git a/board/toradex/common/tdx-common.c
b/board/toradex/common/tdx-common.c
index cdf645b14177..6084436b48b4 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -103,54 +103,69 @@ __weak int print_bootinfo(void)
int checkboard(void)
{
- unsigned char ethaddr[6];
-
- if (read_tdx_cfg_block()) {
- printf("MISSING TORADEX CONFIG BLOCK\n");
- get_mac_from_serial(tdx_serial, _eth_addr);
- } else {
- snprintf(tdx_serial_str, sizeof(tdx_serial_str),
-"%08u", tdx_serial);
- snprintf(tdx_board_rev_str, sizeof(tdx_board_rev_str),
-"V%1d.%1d%s",
-tdx_hw_tag.ver_major,
-tdx_hw_tag.ver_minor,
-get_board_assembly(tdx_hw_tag.ver_assembly));
-
- env_set("serial#", tdx_serial_str);
-
+ if (valid_cfgblock) {
printf("Model: Toradex %04d %s %s\n",
tdx_hw_tag.prodid,
toradex_modules[tdx_hw_tag.prodid].name,
tdx_board_rev_str);
printf("Serial#: %s\n", tdx_serial_str);
+ }
+
#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
- if (read_tdx_cfg_block_carrier()) {
- printf("MISSING TORADEX CARRIER CONFIG BLOCKS\n");
- try_migrate_tdx_cfg_block_carrier();
- } else {
- tdx_carrier_board_name =
-
get_toradex_carrier_boards(tdx_car_hw_tag.prodid);
-
- snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str),
-"%08u", tdx_car_serial);
- snprintf(tdx_car_rev_str, sizeof(tdx_car_rev_str),
-"V%1d.%1d%s",
-tdx_car_hw_tag.ver_major,
-tdx_car_hw_tag.ver_minor,
-
get_board_assembly(tdx_car_hw_tag.ver_assembly));
-
- env_set("carrier_serial#", tdx_car_serial_str);
- printf("Carrier: Toradex %s %s, Serial# %s\n",
- tdx_carrier_board_name,
- tdx_car_rev_str,
- tdx_car_serial_str);
- }
+ if (tdx_carrier_board_name)
+ printf("Carrier: Toradex %s %s, Serial# %s\n",
+ tdx_carrier_board_name,
+ tdx_car_rev_str,
+ tdx_car_serial_str);
#endif
- }
print_bootinfo();
+ return 0;
+}
+
+static int settings_r(void)
+{
+ unsigned char ethaddr[6];
+
+ if (read_tdx_cfg_block()) {
+ printf("MISSING TORADEX CONFIG BLOCK\n");
+ get_mac_from_serial(tdx_serial, _eth_addr);
+
+ /* Board can run even if config block is not present */
+ return 0;
+ }
+
+ snprintf(tdx_serial_str, sizeof(tdx_serial_str),
+"%08u", tdx_serial);
+ snprintf(tdx_board_rev_str, sizeof(tdx_board_rev_str),
+"V%1d.%1d%s",
+tdx_hw_tag.ver_major,
+tdx_hw_tag.ver_minor,
+get_board_assembly(tdx_hw_tag.ver_assembly));
+
+ env_set("serial#", tdx_serial_str);
+
+#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
+ if (read_tdx_cfg_block_carrier()) {
+ printf("MISSING TORADEX CARRIER CONFIG BLOCKS\n");
+ try_migrate_tdx_cfg_block_carrier();
+ } else {
+ tdx_carrier_board_name =
+ get_toradex_carrier_boards(tdx_car_hw_tag.prodid);
+
+ snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str),
+"%08u", tdx_car_serial);
+ snprintf(tdx_car_rev_str, sizeof(tdx_car_rev_str),
+"V%1d.%1d%s",
+tdx_car_hw_tag.ver_major,
+tdx_car_hw_tag.ver_minor,
+get_board_assembly(tdx_car_hw_tag.ver_assembly));
+
+ env_set("carrier_serial#", tdx_car_serial_str);
+ }
+#endif
+
/*
* Check if environment contains a valid MAC address,
* set the one from config block if not
@@ -171,6 +186,7 @@ int checkboard(void)
return 0;
}
+EVENT_SPY_SIMPLE(EVT_SETTINGS_R, settings_r);
#ifdef CONFIG_TDX_CFG_BLOCK_USB_GADGET_PID
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
--
2.39.2
[PATCH v1 2/7] toradex: Remove not necessary model prints from checkboard()
From: Emanuele Ghidoli
Sysinfo prints the model obtained from device tree, checkboard()
take info from hardware and tdx_checkboard() use the model retrieved by
toradex config block.
Remove the print from checkboard() function because the model obtained
from toradex config block is the most complete.
If toradex config block is missing the model info from device tree is
enough.
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Francesco Dolcini
---
board/toradex/apalis-imx8/apalis-imx8.c | 10 -
board/toradex/apalis-tk1/apalis-tk1.c | 7 ---
board/toradex/apalis_imx6/apalis_imx6.c | 21 ---
board/toradex/apalis_t30/apalis_t30.c | 8 ---
.../toradex/colibri-imx6ull/colibri-imx6ull.c | 7 ---
board/toradex/colibri-imx8x/colibri-imx8x.c | 10 -
board/toradex/colibri_imx6/colibri_imx6.c | 20 --
board/toradex/colibri_imx7/colibri_imx7.c | 8 ---
board/toradex/colibri_t20/colibri_t20.c | 10 -
board/toradex/colibri_t30/colibri_t30.c | 7 ---
board/toradex/colibri_vf/colibri_vf.c | 10 -
board/toradex/common/tdx-common.c | 9 +++-
board/toradex/common/tdx-common.h | 1 -
13 files changed, 8 insertions(+), 120 deletions(-)
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c
b/board/toradex/apalis-imx8/apalis-imx8.c
index b351ce64abfc..2483a63c6733 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -208,16 +208,6 @@ void board_preboot_os(void)
gpio_direction_output(BKL1_GPIO, 0);
}
-int checkboard(void)
-{
- puts("Model: Toradex Apalis iMX8\n");
-
- build_info();
- print_bootinfo();
-
- return tdx_checkboard();
-}
-
static enum pcb_rev_t get_pcb_revision(void)
{
unsigned int pcb_vers = 0;
diff --git a/board/toradex/apalis-tk1/apalis-tk1.c
b/board/toradex/apalis-tk1/apalis-tk1.c
index 79a1c92da0a0..ee87d9f4145f 100644
--- a/board/toradex/apalis-tk1/apalis-tk1.c
+++ b/board/toradex/apalis-tk1/apalis-tk1.c
@@ -91,13 +91,6 @@ int arch_misc_init(void)
return 0;
}
-int checkboard(void)
-{
- puts("Model: Toradex Apalis TK1 2GB\n");
-
- return tdx_checkboard();
-}
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c
b/board/toradex/apalis_imx6/apalis_imx6.c
index 164fcc41f550..0da245374a0d 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -716,27 +716,6 @@ int board_late_init(void)
}
#endif /* CONFIG_BOARD_LATE_INIT */
-int checkboard(void)
-{
- char it[] = " IT";
- int minc, maxc;
-
- switch (get_cpu_temp_grade(, )) {
- case TEMP_AUTOMOTIVE:
- case TEMP_INDUSTRIAL:
- break;
- case TEMP_EXTCOMMERCIAL:
- default:
- it[0] = 0;
- };
- printf("Model: Toradex Apalis iMX6 %s %s%s\n",
- is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
- (gd->ram_size == 0x8000) ? "2GB" :
- (gd->ram_size == 0x4000) ? "1GB" : "512MB", it);
-
- return tdx_checkboard();
-}
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/toradex/apalis_t30/apalis_t30.c
b/board/toradex/apalis_t30/apalis_t30.c
index b9a2af33f19f..b10beb447965 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -45,14 +45,6 @@ int arch_misc_init(void)
return 0;
}
-int checkboard(void)
-{
- printf("Model: Toradex Apalis T30 %dGB\n",
- (gd->ram_size == 0x4000) ? 1 : 2);
-
- return tdx_checkboard();
-}
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index a775f54eb3f4..9b9fb342c9d9 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -205,13 +205,6 @@ int board_late_init(void)
return 0;
}
-int checkboard(void)
-{
- printf("Model: Toradex Colibri iMX6ULL\n");
-
- return tdx_checkboard();
-}
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c
b/board/toradex/colibri-imx8x/colibri-imx8x.c
index d8cc72f323c5..2c673a4a6b06 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -114,16 +114,6 @@ int board_phy_config(struct phy_device *phydev)
}
#endif
-int checkboard(void)
-{
- puts("Model: Toradex Colibri iMX8X\n");
-
- build_info();
-
[PATCH v1 4/7] arm: dts: Refactor device trees using "&{/aliases}" syntax
From: Emanuele Ghidoli
Use the common syntax to define aliases.
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Francesco Dolcini
---
.../dts/imx6dl-colibri-eval-v3-u-boot.dtsi| 18 -
arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi| 26 ++-
.../arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi | 10 ---
.../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi| 12 -
.../dts/imx8mp-verdin-wifi-dev-u-boot.dtsi| 12 -
5 files changed, 43 insertions(+), 35 deletions(-)
diff --git a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
b/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
index 31f3a48dd9f0..0eea4d1862ae 100644
--- a/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
@@ -5,13 +5,17 @@
#include "imx6qdl-u-boot.dtsi"
-&{/aliases} {
- /* U-Boot won't find PMIC otherwise */
- i2c0 =
- i2c1 =
- /* SDHCI instance order: eMMC, 4-bit SD/MMC (U-Boot won't find
ConfigBlock otherwise) */
- mmc0 =
- mmc1 =
+/ {
+ aliases {
+ /* U-Boot won't find PMIC otherwise */
+ i2c0 =
+ i2c1 =
+ /* SDHCI instance order: eMMC, 4-bit SD/MMC
+* (U-Boot won't find ConfigBlock otherwise)
+*/
+ mmc0 =
+ mmc1 =
+ };
};
{
diff --git a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
index 3d19796cb698..3c6e503d043b 100644
--- a/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
+++ b/arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
@@ -5,18 +5,20 @@
#include "imx6qdl-u-boot.dtsi"
-&{/aliases} {
- /* U-Boot won't find PMIC otherwise */
- i2c0 =
- i2c1 =
- i2c2 =
- /*
-* SDHCI instance order: eMMC, 8-bit SD/MMC, 4-bit SD
-* (U-Boot won't find ConfigBlock otherwise)
-*/
- mmc0 =
- mmc1 =
- mmc2 =
+/ {
+ aliases {
+ /* U-Boot won't find PMIC otherwise */
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ /*
+* SDHCI instance order: eMMC, 8-bit SD/MMC, 4-bit SD
+* (U-Boot won't find ConfigBlock otherwise)
+*/
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
};
{
diff --git a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
index 57ca28edb70d..b2c12a413daf 100644
--- a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
@@ -5,10 +5,12 @@
#include "imx7s-u-boot.dtsi"
-&{/aliases} {
- /* SDHCI instance order: eMMC, SD/MMC */
- mmc0 =
- mmc1 =
+/ {
+ aliases {
+ /* SDHCI instance order: eMMC, SD/MMC */
+ mmc0 =
+ mmc1 =
+ };
};
{
diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
index 8efa4ddc734a..515f195ab759 100644
--- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
@@ -6,6 +6,12 @@
#include "imx8mm-u-boot.dtsi"
/ {
+ aliases {
+ eeprom0 = _module;
+ eeprom1 = _carrier_board;
+ eeprom2 = _display_adapter;
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
@@ -13,12 +19,6 @@
};
};
-&{/aliases} {
- eeprom0 = _module;
- eeprom1 = _carrier_board;
- eeprom2 = _display_adapter;
-};
-
&{/soc@0/bus@3080/i2c@30a2/pmic@25} {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
index 2a1aa1935a76..67f1d45ce269 100644
--- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
@@ -6,6 +6,12 @@
#include "imx8mp-u-boot.dtsi"
/ {
+ aliases {
+ eeprom0 = _module;
+ eeprom1 = _carrier_board;
+ eeprom2 = _display_adapter;
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
@@ -13,12 +19,6 @@
};
};
-&{/aliases} {
- eeprom0 = _module;
- eeprom1 = _carrier_board;
- eeprom2 = _display_adapter;
-};
-
{
bootph-all;
bootph-pre-ram;
--
2.39.2
[PATCH v1 1/7] toradex: Fix recursive call to checkboard
From: Emanuele Ghidoli
Since checkboard() is used instead of show_board_info(), in case toradex
config block is missing or malformed, checkboard is recursively called.
It prints a long list of "MISSING TORADEX CONFIG BLOCK" till the stack
is full.
Fixes: edb0ecd18708 ("toradex: Use checkboard() instead of show_board_info()")
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Francesco Dolcini
---
board/toradex/common/tdx-common.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/board/toradex/common/tdx-common.c
b/board/toradex/common/tdx-common.c
index ed8f0a6a4756..ddc4a175da68 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -103,7 +103,6 @@ int tdx_checkboard(void)
if (read_tdx_cfg_block()) {
printf("MISSING TORADEX CONFIG BLOCK\n");
get_mac_from_serial(tdx_serial, _eth_addr);
- checkboard();
} else {
snprintf(tdx_serial_str, sizeof(tdx_serial_str),
"%08u", tdx_serial);
--
2.39.2
[PATCH v1 0/7] toradex: fix reset and hardware detection regressions
From: Francesco Dolcini
This series fixes two regressions affecting multiple Toradex boards
(i.MX, TI and TEGRA based) and targets the current master, e.g. v2024.04
release.
U-Boot `reset` command is broken on all Tordex i.MX6* based SoMs since
v2023.07, this series fixes it enabling the `wdt-reboot` driver.
Since v2024.04-rc1 reading the Toradex configuration block is not working
properly anymore, the serial number and the hardware version are not read
correctly, preventing the board from functioning correctly (wrong mac address,
wrong DT, ...). This is fixed by reading the config block in `EVT_SETTINGS_R`
and
adding a toradex sysinfo driver. In addition to that, we now use a random mac
address in case the config block is invalid.
Reported-by: Sahaj Sarup
Closes:
https://lore.kernel.org/all/CAKZ1LvM45MB8N0CqgU+C7i9=bjb6kqntxwo2tv407hklwtc...@mail.gmail.com/
Reported-by: Marcel Ziswiler
Closes:
https://lore.kernel.org/all/e40ed93bd8f371ec56b8fc451dcb458f3ce6dcba.ca...@toradex.com/
Reported-by: Francesco Dolcini
Closes: https://lore.kernel.org/all/ZY2ZDWAQuTlRjV9H@francesco-nb/
Emanuele Ghidoli (6):
toradex: Fix recursive call to checkboard
toradex: Remove not necessary model prints from checkboard()
toradex: common: Use SETTINGS_R event to read toradex config block
arm: dts: Refactor device trees using "&{/aliases}" syntax
toradex: common: Add sysinfo driver
toradex: common: Use random mac address if toradex config block is
missing
Parth Pancholi (1):
toradex: imx6*: fix reset using wdt-reboot driver
arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi| 6 +
arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 6 +
.../dts/imx6dl-colibri-eval-v3-u-boot.dtsi| 28 +++-
arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi| 36 +++--
.../dts/imx6ull-colibri-eval-v3-u-boot.dtsi | 14 ++
.../arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi | 14 +-
.../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi| 16 +-
.../dts/imx8mp-verdin-wifi-dev-u-boot.dtsi| 16 +-
.../dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 4 +
arch/arm/dts/tegra124-apalis-u-boot.dtsi | 12 ++
arch/arm/dts/tegra20-colibri-u-boot.dtsi | 12 ++
arch/arm/dts/tegra30-apalis-u-boot.dtsi | 12 ++
arch/arm/dts/tegra30-colibri-u-boot.dtsi | 12 ++
.../arm/dts/vf610-colibri-eval-v3-u-boot.dtsi | 4 +
board/toradex/apalis-imx8/apalis-imx8.c | 10 --
board/toradex/apalis-tk1/apalis-tk1.c | 7 -
board/toradex/apalis_imx6/apalis_imx6.c | 21 ---
board/toradex/apalis_t30/apalis_t30.c | 8 -
.../toradex/colibri-imx6ull/colibri-imx6ull.c | 7 -
board/toradex/colibri-imx8x/colibri-imx8x.c | 10 --
board/toradex/colibri_imx6/colibri_imx6.c | 20 ---
board/toradex/colibri_imx7/colibri_imx7.c | 8 -
board/toradex/colibri_t20/colibri_t20.c | 10 --
board/toradex/colibri_t30/colibri_t30.c | 7 -
board/toradex/colibri_vf/colibri_vf.c | 10 --
board/toradex/common/Kconfig | 1 +
board/toradex/common/tdx-common.c | 137 +-
board/toradex/common/tdx-common.h | 1 -
configs/apalis-imx8_defconfig | 1 +
configs/apalis-tk1_defconfig | 1 +
configs/apalis_imx6_defconfig | 4 +
configs/apalis_t30_defconfig | 1 +
configs/colibri-imx6ull-emmc_defconfig| 4 +
configs/colibri-imx6ull_defconfig | 4 +
configs/colibri-imx8x_defconfig | 1 +
configs/colibri_imx6_defconfig| 4 +
configs/colibri_imx7_defconfig| 1 +
configs/colibri_imx7_emmc_defconfig | 1 +
configs/colibri_t20_defconfig | 1 +
configs/colibri_t30_defconfig | 1 +
configs/colibri_vf_defconfig | 1 +
configs/verdin-am62_a53_defconfig | 1 +
configs/verdin-am62_r5_defconfig | 1 +
configs/verdin-imx8mm_defconfig | 1 +
configs/verdin-imx8mp_defconfig | 1 +
45 files changed, 284 insertions(+), 194 deletions(-)
create mode 100644 arch/arm/dts/tegra124-apalis-u-boot.dtsi
create mode 100644 arch/arm/dts/tegra20-colibri-u-boot.dtsi
create mode 100644 arch/arm/dts/tegra30-apalis-u-boot.dtsi
create mode 100644 arch/arm/dts/tegra30-colibri-u-boot.dtsi
--
2.39.2
Re: [PATCH v1] include: android_bootloader_message.h: sync with AOSP upstream
On Mon, Feb 19, 2024 at 4:16 AM Igor Opaniuk wrote:
>
> This takes the latest changes from AOSP from [1][2] (as this
> header was split on two) with minimal changes (this could lead
> to warnings reported by checkpatch).
Do we want to maybe follow that and also carry two different headers
in U-Boot? Or it doesn't make much sense? I'm thinking in terms of
future portability mostly: how easy it's to update this header right
now, and how easy it's going to be further. I didn't form any opinion
on that, hence asking.
Another thing: are you sure that changing only the header won't break
anything in U-Boot .c files that use this header?
>
> Some local changes have been applied:
Is it possible to split this work into two patches:
1. Bring the original changes only
2. Apply all necessary changes for U-Boot
Or does it break the build, etc? Again, thinking in terms of
portability easiness, and not sure which approach is better -- just
asking basically.
> 1. Enable static_assert() for defined structures to be sure
> that all of them have correct sizes.
> 2. Adjuste types in bootloader_control structure with bitfields
Adjuste -> adjust
> (uint8_t -> uint16_t). It seems that gcc just doesn't like bitfields
I wonder if all those extra changes can be upstreamed back to AOSP?
Ideally we'd want to just copy those headers over from AOSP to U-Boot
with no changes, would make the porting work easier. What are your
thoughts on that?
> that cross the width of the type. Changing the type doesn't change
> the layout though.
> This addresses this gcc note:
> In file included from boot/android_ab.c:7:
> include/android_bootloader_message.h:230:1: note: offset of packed bit-field
> ‘merge_status’ has changed in GCC 4.4
> 230 | } __attribute__((packed));
>
> [1]
> https://android.googlesource.com/platform/bootable/recovery/+/main/bootloader_message/include/bootloader_message/bootloader_message.h
> [2]
> https://android.googlesource.com/platform/hardware/interfaces/+/main/boot/1.1/default/boot_control/include/private/boot_control_definition.h
>
> CC: Alex Deymo
> CC: Sam Protsenko
> CC: Eugeniu Rosca
> CC: Simon Glass
> Signed-off-by: Igor Opaniuk
> ---
>
> include/android_bootloader_message.h | 104 +++
> 1 file changed, 92 insertions(+), 12 deletions(-)
>
> diff --git a/include/android_bootloader_message.h
> b/include/android_bootloader_message.h
> index 286d7ab0f31..75198fc9dc2 100644
> --- a/include/android_bootloader_message.h
> +++ b/include/android_bootloader_message.h
> @@ -21,17 +21,22 @@
> * stddef.h
> */
> #include
> +#include
> #endif
>
> // Spaces used by misc partition are as below:
> // 0 - 2K For bootloader_message
> // 2K - 16KUsed by Vendor's bootloader (the 2K - 4K range may be
> optionally used
> // as bootloader_message_ab struct)
> -// 16K - 64KUsed by uncrypt and recovery to store wipe_package for A/B
> devices
> +// 16K - 32KUsed by uncrypt and recovery to store wipe_package for A/B
> devices
> +// 32K - 64KSystem space, used for miscellanious AOSP features. See
> below.
> // Note that these offsets are admitted by bootloader,recovery and uncrypt,
> so they
> // are not configurable without changing all of them.
> static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0;
> +static const size_t VENDOR_SPACE_OFFSET_IN_MISC = 2 * 1024;
> static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024;
> +static const size_t SYSTEM_SPACE_OFFSET_IN_MISC = 32 * 1024;
> +static const size_t SYSTEM_SPACE_SIZE_IN_MISC = 32 * 1024;
>
> /* Bootloader Message (2-KiB)
> *
> @@ -81,24 +86,67 @@ struct bootloader_message {
> char reserved[1184];
> };
>
> +// Holds Virtual A/B merge status information. Current version is 1. New
> fields
> +// must be added to the end.
> +struct misc_virtual_ab_message {
> + uint8_t version;
> + uint32_t magic;
> + uint8_t merge_status; // IBootControl 1.1, MergeStatus enum.
> + uint8_t source_slot; // Slot number when merge_status was written.
> + uint8_t reserved[57];
> +} __attribute__((packed));
> +
> +struct misc_memtag_message {
> + uint8_t version;
> + uint32_t magic; // magic string for treble compat
> + uint32_t memtag_mode;
> + uint8_t reserved[55];
> +} __attribute__((packed));
> +
> +struct misc_kcmdline_message {
> + uint8_t version;
> + uint32_t magic;
> + uint64_t kcmdline_flags;
> + uint8_t reserved[51];
> +} __attribute__((packed));
> +
> +#define MISC_VIRTUAL_AB_MESSAGE_VERSION 2
> +#define MISC_VIRTUAL_AB_MAGIC_HEADER 0x56740AB0
> +
> +#define MISC_MEMTAG_MESSAGE_VERSION 1
> +#define MISC_MEMTAG_MAGIC_HEADER 0x5afefe5a
> +#define MISC_MEMTAG_MODE_MEMTAG 0x1
> +#define MISC_MEMTAG_MODE_MEMTAG_ONCE 0x2
> +#define MISC_MEMTAG_MODE_MEMTAG_KERNEL 0x4
> +#define MISC_MEMTAG_MODE_MEMTAG_KERNEL_ONCE 0x8
> +#define MISC_MEMTAG_MODE_MEMTAG_OFF 0x10
> +// This is set when the state was overridden forcibly. This does not need to
> be
> +// interpreted by
Re: [PATCH] arm64: zynqmp: Support semhosting boot method
On 2/16/24 17:09, Sean Anderson wrote:
On 2/16/24 11:03, Sean Anderson wrote:
On 2/16/24 10:06, Michal Simek wrote:
On 2/16/24 14:48, Michal Simek wrote:
On 2/15/24 20:31, Sean Anderson wrote:
On 2/15/24 14:08, Michal Simek wrote:
On 2/15/24 18:19, Sean Anderson wrote:
Currently, when we boot from JTAG we try to boot U-Boot from RAM.
However, this is a bit tricky to time, since the debugger has to wait
for SPL to initialize RAM before it can load U-Boot. This can result in
long waits, since occasionally initializing RAM (and other things in
psu_init) takes a long time to complete and the debugger must wait for
this worst case.
Support semihosting if it is enabled, as it lets U-Boot tell the
debugger when we are ready for the image. This means we don't have to
wait any more than necessary. We don't change the default config to
ensure we don't break compatibility with existing debuggers that don't
expect us to hit semihosting breakpoints.
Signed-off-by: Sean Anderson
---
arch/arm/mach-zynqmp/spl.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index a0f35f36faa..5af735aa5ce 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
@@ -66,6 +67,11 @@ void spl_board_init(void)
}
#endif
+static u32 jtag_boot_device(void)
+{
+ return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
+}
+
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
@@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list)
if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
spl_boot_list[1] = BOOT_DEVICE_MMC1;
- spl_boot_list[2] = BOOT_DEVICE_RAM;
+ spl_boot_list[2] = jtag_boot_device();
}
u32 spl_boot_device(void)
@@ -97,7 +103,7 @@ u32 spl_boot_device(void)
switch (bootmode) {
case JTAG_MODE:
- return BOOT_DEVICE_RAM;
+ return jtag_boot_device();
#ifdef CONFIG_SPL_MMC
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
Good timing. Can you please tell me how to test this? What's the setup?
Which debugger are you using?
I am using OpenOCD with the patches at
https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2freview.openocd.org%2fc%2fopenocd%2f%2b%2f8133=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-afc15b07b0f91c910f832185958363d84f990a08
I am trying it on the top of the latest git but getting issue with event block
and no idea how to fix it.
# sudo openocd -f
/usr/local/share/openocd/scripts/interface/ftdi/digilent_jtag_hs3.cfg -f
/usr/local/share/openocd/scripts/target/xilinx_zynqmp.cfg
Open On-Chip Debugger 0.12.0+dev-01509-g6d288937cb2d (2024-02-16-12:22)
Licensed under GNU GPL v2
For bug reports, read
https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=http%3a%2f%2fopenocd.org%2fdoc%2fdoxygen%2fbugs.html=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-f501ab9aa5516ff666e387e53598fd624398f1bc
Info : auto-selecting first available session transport "jtag". To override use
'transport select '.
wrong # args: should be "-event "
Do you know how to fix it?
I actually bisect it and found that it is caused by
jtag: rewrite jim_jtag_configure() as COMMAND_HANDLER
ea2e26f7d521f5755b4bfda7bf12d99650277421
Interesting. I have been testing with 0.12.
# sudo openocd -f
/usr/local/share/openocd/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg -f
/usr/local/share/openocd/scripts/target/xilinx_zynqmp.cfg
FWIW after installing the udev rules I do not need sudo
Open On-Chip Debugger 0.12.0+dev-01512-g214206ebb972 (2024-02-16-15:38)
Licensed under GNU GPL v2
For bug reports, read
https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=http%3a%2f%2fopenocd.org%2fdoc%2fdoxygen%2fbugs.html=6e1be473-0b3f-4bc4-a4f0-403592e74baf=d807158c60b7d2502abde8a2fc01f40662980862-f501ab9aa5516ff666e387e53598fd624398f1bc
none separate
Info : auto-selecting first available session transport "jtag". To override use
'transport select '.
Info : Hardware thread awareness created
boot_apu
Info : Listening on port for tcl connections
Info : Listening on port for telnet connections
Warn : An adapter speed is not selected in the init scripts. OpenOCD will try
to run the adapter at very low speed (100 kHz).
Warn : To remove this warnings and achieve reasonable communication speed with the target, set
"adapter speed" or "jtag_rclk" in the init scripts.
Info : clock speed 100 kHz
Info : TAP uscale.tap does not have valid IDCODE (idcode=0x48e70126)
Info : JTAG tap: uscale.ps tap/device found: 0x24738093 (mfg: 0x049 (Xilinx),
part: 0x4738, ver: 0x2)
Info : JTAG tap:
Re: [PULL] u-boot-usb/master
On Tue, Feb 20, 2024 at 09:35:43AM +0100, Marek Vasut wrote: > The following changes since commit 3e6f2a94bfc25f1782ce2d45db27f47ec781feb1: > > Merge tag 'u-boot-imx-master-20240219' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2024-02-19 08:55:17 > -0500) > > are available in the Git repository at: > > git://source.denx.de/u-boot-usb.git master > > for you to fetch changes up to d9a20fea2ba53db3a999827d3e50e181d5513e09: > > usb: ehci-mx6: Add i.MX93 support (2024-02-19 20:08:51 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Please pull u-boot-samsung master
On Tue, Feb 20, 2024 at 01:25:44PM +0900, Minkyu Kang wrote: > Dear Tom, > > The following changes since commit 15e7927b5a2d33666af19879577bf0c30ab088fe: > > Merge patch series "omap3: Make SPL_OMAP3_ID_NAND depend on > NAND_OMAP_GPMC" (2024-01-22 14:18:55 -0500) > > are available in the git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-samsung.git master > > for you to fetch changes up to 1e81d12e34e874319e041652198a4ba561d751ab: > > MAINTAINERS: Add new Samsung subsystems (2024-01-24 11:23:20 +0900) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] implement policy_pcr commands to lock NV-indexes behind a PCR
I'm kind of new to u-boot and I'm not really able to review this code
as well as I should.
But also I can't apply the patch. It seems white space damaged? The
kernel has a good document on how to do this. I'm pretty sure u-boot
does as well but I'm new.
https://www.kernel.org/doc/Documentation/process/email-clients.rst
Please run your patch through the scripts/checkpatch.pl script. Stuff
like this triggers a warning:
> +static int do_tpm_nv_write_value(struct cmd_tbl *cmdtp, int flag,
> + int argc, char *const argv[]) //TODO: session handle
> from auth session!
> +{
> + struct udevice *dev;
> + u32 nv_addr, nv_size, rc;
> + void *session_addr = NULL;
> + int ret;
> +
> + ret = get_tpm();
> + if (ret)
> + return ret;
> +
> + if (argc < 4)
> + return CMD_RET_USAGE;
WARNING: suspect code indent for conditional statements (0, 0)
#250: FILE: cmd/tpm-v2.c:437:
+ if (ret)
+ return ret;
WARNING: suspect code indent for conditional statements (0, 0)
#253: FILE: cmd/tpm-v2.c:440:
+ if (argc < 4)
+ return CMD_RET_USAGE;
Also the subject should have a subsystem prefix and the information from
the email should be moved into the commit message. Currently the commit
message is empty.
> diff --git a/include/tpm-v2.h b/include/tpm-v2.h
> index 33dd103767..5b60883777 100644
> --- a/include/tpm-v2.h
> +++ b/include/tpm-v2.h
> @@ -301,7 +301,8 @@ enum tpm2_startup_types {
> */
> enum tpm2_handles {
> TPM2_RH_OWNER = 0x4001,
> - TPM2_RS_PW= 0x4009,
> + TPM2_RH_NULL= 0x4007,
> + TPM2_RS_PW = 0x4009,
Changing TPM2_RS_PW is an unrelated whitespace change. Do that as a
separate patch. But I don't get it at all because the TPM2_RS_PW enum
has always been indented correctly as far as I can see. So it's a
puzzle.
I mean there are a lot of TODOs and I understand that you just wanted a
high level review but I kept getting distracted and lost and I couldn't
apply the patch so it was just really hard to figure out what was going
on. :(
regards,
dan carpenter
Re: [PATCH] initcall: break loop immediately on failure
On Mon, Feb 19, 2024 at 06:35:03PM +, Caleb Connolly wrote:
> The current ordering always results in func pointing to the next
> function in the init_sequence. e.g. if fdtdec_setup() fails, ret will
> be set to the error code, then func will be updated to point to
> initf_malloc(), only then is ret checked and the loop broken. The end
> result of this is that the "initcall failed at ..." error will point you
> to initf_malloc(), when the error actually occured in fdtdec_setup()!
>
> This can be quite confusing and result in a lot of time wasted debugging
> code that has nothing to do with the failure (ask me how I know :P).
Heh. Subtle.
>
> Adjust the for loop to check ret immediately after the call and break
> early so that func will correctly reference the failed function.
>
> Signed-off-by: Caleb Connolly
> ---
> lib/initcall.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/lib/initcall.c b/lib/initcall.c
> index ce317af213ab..128242e5ff55 100644
> --- a/lib/initcall.c
> +++ b/lib/initcall.c
> @@ -52,11 +52,11 @@ int initcall_run_list(const init_fnc_t init_sequence[])
> ulong reloc_ofs = calc_reloc_ofs();
> const init_fnc_t *ptr;
> enum event_t type;
> init_fnc_t func;
> - int ret = 0;
> + int ret;
We need to keep this initialization. The bug would be when we're
building for CONFIG_ARC and this is called from board_init_f_r(). The
array is empty except for the NULL sentinal at the end. We don't
enter the loop in that case.
regards,
dan carpenter
>
> - for (ptr = init_sequence; func = *ptr, !ret && func; ptr++) {
> + for (ptr = init_sequence; func = *ptr, func; ptr++) {
> type = initcall_is_event(func);
>
> if (type) {
> if (!CONFIG_IS_ENABLED(EVENT))
> @@ -70,8 +70,10 @@ int initcall_run_list(const init_fnc_t init_sequence[])
> debug("initcall: %p\n", (char *)func - reloc_ofs);
> }
>
> ret = type ? event_notify_null(type) : func();
> + if (ret)
> + break;
> }
>
> if (ret) {
> if (CONFIG_IS_ENABLED(EVENT)) {
> --
> 2.43.1
>
Re: [PATCH v4 16/39] board: dragonboard410c: add chainloaded config fragment
On 20/02/2024 14:19, Peter Robinson wrote: > On Thu, 15 Feb 2024 at 21:03, Caleb Connolly > wrote: >> >> Add a config fragment for building U-Boot such that it can be >> chainloaded by aboot/LK rather than being flashed directly to the aboot >> partition. > > How does this work in practice? I think a lot of devices, one example > I see is signed vs unsigned, or emmc vs other storage, have to > configs, how would a user choose with LK vs the other option here? I'm not sure I understand, maybe the commit message wording was a bit vague... There is only the default mode where U-Boot is flashed to the aboot partition, and then the chainloaded usecase where it's wrapped in an Android boot image and flashed to the boot partition. > >> Reviewed-by: Neil Armstrong >> Signed-off-by: Caleb Connolly >> --- >> board/qualcomm/dragonboard410c/configs/chainloaded.config | 7 +++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config >> b/board/qualcomm/dragonboard410c/configs/chainloaded.config >> new file mode 100644 >> index ..3fd064924a1f >> --- /dev/null >> +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config >> @@ -0,0 +1,7 @@ >> +# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set >> +CONFIG_TEXT_BASE=0x0 >> +# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set >> +# CONFIG_REMAKE_ELF is not set >> +CONFIG_POSITION_INDEPENDENT=y >> +CONFIG_INIT_SP_RELATIVE=y >> +CONFIG_SYS_INIT_SP_BSS_OFFSET=524288 >> >> -- >> 2.43.1 >> -- // Caleb (they/them)
Re: [PATCH v4 1/2] imx: imxrt1050-evk: Add support for SPI flash booting
On Mon, Feb 19, 2024 at 11:50 PM Jesse T wrote: > Huh, this is very interesting and I haven't noticed before. > When sending git send-email lowercases my email. > It seems like all my commits are like this. > Do you want this fixed? Please fix both issues and submit a v5.
Re: HABv4 with SPL and u-boot-dtb.img on i.MX6
On 2/20/24 04:50, Benjamin Lemouzy wrote: > Hello, > > I'm trying to make secure boot work on i.MX6 SABRE with SPL and > u-boot-dtb.img files and I'm not sure how to do it. > > I'm using the U-Boot vanilla master branch (2024.04-rc2) with the following > configuration: > > # Remove some stuff to not exceed file size limit > $ cat <> configs/mx6sabresd_defconfig > CONFIG_BOOTMETH_EFILOADER=n > CONFIG_CMD_NET=n > CONFIG_NET=n > EOF > > # Enable secure boot > $ cat <> configs/mx6sabresd_defconfig > CONFIG_IMX_HAB=y > CONFIG_SPL_LOAD_FIT_ADDRESS=0x1800 > EOF > > $ make ARCH=arm O=build mx6sabresd_defconfig > > $ make ARCH=arm O=build > > I have no issue to generate a working SPL-signed file following > doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt instructions. > > doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt only gives instructions to > sign u-boot-ivt.img but this file doesn't contain device trees listed in > CONFIG_OF_LIST as u-boot-dtb.img does and I need them. > > > > NXP AN4581 lists 2 possible formats to sign additional images: > > - Image format: > > --- +-+ <-- *load_address > ^ | | > | | | > | | Image data | > Signed | | | > Data | | | > | +-+ > | |Padding Next Boundary| > | +-+ <-- *ivt > v | Image Vector Table | > --- +-+ <-- *csf > | | > | Command Sequence File (CSF) | > | | > +-+ > | Padding (optional) | > +-+ > > - FIT image format: > > --- +-+ --- > ^ | |^ > | | || > | | FDT FIT || > | | || > Signed data | | || > | +-+| > | |Padding Next Boundary|| > | +-+| > v | Image Vector Table || > --- +-+| FIT image > | || > | Command Sequence File (CSF) || > | || > +-+| > | Padding (optional) || > --- +-+| > ^ | || > Signed data | | U-Boot|| > v | |v > --- +-+ --- > > And as u-boot-dtb.img is a FIT image, I probably have to use the FIT image > format, right? > > > > I manually craft the signed FIT image using > doc/imx/habv4/csf_examples/mx8m/csf.sh as reference and everything looks fine: > > U-Boot SPL 2024.04-rc2-00025-g9e00b6993f-dirty (Feb 19 2024 - 13:17:31 > +0100) > >>SPL: board_init_r() > spl_init > Trying to boot from MMC1 > fit read offset 11400, size=12800, dst=1800, count=12800 > spl_load_simple_fit_fix_load: ivt: 18001000 offset: 1000 size: 3060 > spl_load_simple_fit_fix_load: ivt self: 18001000 > hab fuse not enabled > > Authenticate image from DDR location 0x1800... > > ivt_offset = 0x1000, ivt addr = 0x18001000 > ivt entry = 0x1800, dcd = 0x, csf = 0x18001020 > Dumping IVT > .. @ > ... > Dumping CSF Header > ..PC...P > > ...< > ...8 > > Calling authenticate_image in ROM > ivt_offset = 0x1000 > start = 0x1800 > bytes = 0x3060 > firmware: 'firmware-1' > External data: dst=1780, offset=3060, size=86138 > Image OS is U-Boot > fdt: 'fdt-1' > Can't get 'load' property from FIT 0x1800, node: offset 464, name > fdt-1 (FDT_ERR_NOTFOUND) > External data: dst=17886140, offset=89198, size=ac00 > Can't get 'entry' property from FIT 0x1800, node: offset 464, name > fdt-1 (FDT_ERR_NOTFOUND) > loadables: 'firmware-1' > no string for index 1 > Jumping to U-Boot... > SPL malloc() used 0x0
Re: [PATCH 7/7] verdin-imx8mp_defconfig: Enable PCIe/NVMe support
On Tue, Feb 20, 2024 at 10:51 AM Sumit Garg wrote: > > Also, enable reset driver which is a prerequisite for PCIe support. > > Signed-off-by: Sumit Garg > --- > configs/verdin-imx8mp_defconfig | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig > index 22b8a334dfa..d8bd644322b 100644 > --- a/configs/verdin-imx8mp_defconfig > +++ b/configs/verdin-imx8mp_defconfig > @@ -185,3 +185,12 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 > CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 > CONFIG_IMX_WATCHDOG=y > CONFIG_HEXDUMP=y > +CONFIG_DM_RESET=y > +CONFIG_RESET_IMX=y > +CONFIG_PCI=y > +CONFIG_PCIE_DW_IMX8=y > +CONFIG_PHY_IMX8M_PCIE=y > +CONFIG_CMD_PCI=y > +CONFIG_NVME=y > +CONFIG_NVME_PCI=y > +CONFIG_CMD_NVME=y Please don't group all these new config options at the end of the file. Use 'make savedefconfig' and then 'cp defconfig configs/verdin-imx8mp_defconfig' to properly add these new config options.
Re: [PATCH 7/7] verdin-imx8mp_defconfig: Enable PCIe/NVMe support
On 2/20/24 14:10, Sumit Garg wrote: Also, enable reset driver which is a prerequisite for PCIe support. Commit message needs to be fixed.
Re: [PATCH 6/7] pci: Add DW PCIe controller support for iMX8MP SoC
On 2/20/24 14:10, Sumit Garg wrote:
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Signed-off-by: Sumit Garg
---
drivers/pci/Kconfig| 8 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_imx8.c | 348 +
3 files changed, 357 insertions(+)
create mode 100644 drivers/pci/pcie_dw_imx8.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 463ec47eb92..b7c7922b091 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -413,4 +413,12 @@ config PCIE_STARFIVE_JH7110
Say Y here if you want to enable PLDA XpressRich PCIe controller
support on StarFive JH7110 SoC.
+config PCIE_DW_IMX8
+ bool "i.MX8 PCIe support"
+ depends on ARCH_IMX8M
+ select PCIE_DW_COMMON
+ help
+ Say Y here if you want to enable DW PCIe controller support on
+ iMX8 SoCs.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 72ef8b4bc77..cddbb902095 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
+obj-$(CONFIG_PCIE_DW_IMX8) += pcie_dw_imx8.o
diff --git a/drivers/pci/pcie_dw_imx8.c b/drivers/pci/pcie_dw_imx8.c
new file mode 100644
index 000..b9921644765
--- /dev/null
+++ b/drivers/pci/pcie_dw_imx8.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Linaro Ltd.
+ *
+ * Author: Sumit Garg
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie_dw_common.h"
+
+#define PCIE_LINK_CAPABILITY 0x7c
+#define TARGET_LINK_SPEED_MASK 0xf
+#define LINK_SPEED_GEN_1 0x1
+#define LINK_SPEED_GEN_2 0x2
+#define LINK_SPEED_GEN_3 0x3
+
+#define PCIE_MISC_CONTROL_1_OFF0x8bc
+#define PCIE_DBI_RO_WR_EN BIT(0)
+
+#define PCIE_PORT_DEBUG0 0x728
+#define PCIE_PORT_DEBUG1 0x72c
+#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
+#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
+
+#define PCIE_LINK_UP_TIMEOUT_MS100
+
+#define IOMUXC_GPR14_OFFSET0x38
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDEBIT(11)
+
+struct pcie_dw_imx8 {
+ /* Must be first member of the struct */
+ struct pcie_dw dw;
+ struct regmap *iomuxc_gpr;
+ struct clk pcie;
+ struct clk pcie_bus;
+ struct clk pcie_aux;
+ struct gpio_descreset_gpio;
+ struct reset_ctlapps_reset;
+ struct phy phy;
+};
+
+static void pcie_dw_configure(struct pcie_dw_imx8 *priv, u32 cap_speed)
+{
+ u32 val;
+
+ dw_pcie_dbi_write_enable(>dw, true);
+
+ val = readl(priv->dw.dbi_base + PCIE_LINK_CAPABILITY);
+ val &= ~TARGET_LINK_SPEED_MASK;
+ val |= cap_speed;
+ writel(val, priv->dw.dbi_base + PCIE_LINK_CAPABILITY);
clrsetbits_le32()
+
+ dw_pcie_dbi_write_enable(>dw, false);
+}
+
+static void imx8_pcie_ltssm_enable(struct pcie_dw_imx8 *priv)
+{
+ reset_deassert(>apps_reset);
+}
+
+static void imx8_pcie_ltssm_disable(struct pcie_dw_imx8 *priv)
+{
+ reset_assert(>apps_reset);
+}
+
+static int is_link_up(struct pcie_dw_imx8 *priv)
+{
+ u32 val;
+
+ val = readl(priv->dw.dbi_base + PCIE_PORT_DEBUG1);
+
+ return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
+ (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
+}
+
+static int wait_link_up(struct pcie_dw_imx8 *priv)
+{
+ unsigned long timeout;
+
+ timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
wait_for_bit() or read_poll_timeout()
+ while (!is_link_up(priv)) {
+ if (get_timer(0) > timeout)
+ return 0;
+ mdelay(10);
+ };
+
+ return 1;
return -ETIMEDOUT ?
+}
+
+static int pcie_link_up(struct pcie_dw_imx8 *priv, u32 cap_speed)
+{
+ if (is_link_up(priv)) {
+ printf("PCI Link
Re: [PATCH 5/7] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
On 2/20/24 14:10, Sumit Garg wrote:
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Signed-off-by: Sumit Garg
Is this based on Linux ? If so, include Linux commit ID from which the
code was imported.
Re: [PATCH 4/7] imx8mp: power-domain: Expose high performance PLL clock
On 2/20/24 14:10, Sumit Garg wrote:
PCIe PHY can use it when there is no external refclock provided.
Commit message needs to be fixed.
+static int hsio_pll_enable(struct udevice *dev)
+{
+ struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
+ unsigned long start;
+ u32 val;
+
+ /* Setup HSIO PLL */
+ val = readl(priv->base + GPR_REG2);
+ val &= ~(P_PLL_MASK | M_PLL_MASK | S_PLL_MASK);
+ val |= (FIELD_PREP(P_PLL_MASK, 12) | FIELD_PREP(M_PLL_MASK, 800) |
+ FIELD_PREP(S_PLL_MASK, 4));
+ writel(val, priv->base + GPR_REG2);
clrsetbits_le32()
+ /* de-assert PLL reset */
+ setbits_le32(priv->base + GPR_REG3, PLL_RST);
+
+ /* enable PLL */
+ setbits_le32(priv->base + GPR_REG3, PLL_CKE);
+
+ /* Check if PLL is locked */
+ start = get_timer(0);
wait_for_bit() or readl_poll_timeout()
+ for (;;) {
+ if (readl(priv->base + GPR_REG1) & PLL_LOCK)
+ break;
+
+ if (get_timer(start) > 100) {
+ dev_err(dev, "failed to lock HSIO PLL\n");
+ return -ETIMEDOUT;
+ }
+
+ udelay(10);
+ }
+
+ return 0;
+}
+
+static void hsio_pll_disable(struct udevice *dev)
+{
+ struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
+
+ /* de-assert PLL reset */
+ clrbits_le32(priv->base + GPR_REG3, PLL_RST);
+
+ /* enable PLL */
+ clrbits_le32(priv->base + GPR_REG3, PLL_CKE);
+}
+
static int imx8mp_hsiomix_on(struct power_domain *power_domain)
{
struct udevice *dev = power_domain->dev;
@@ -69,16 +127,23 @@ static int imx8mp_hsiomix_on(struct power_domain
*power_domain)
if (ret)
goto err_clk_pcie;
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
+ if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) {
setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE)
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE) {
setbits_le32(priv->base + GPR_REG0, PCIE_CLOCK_MODULE_EN);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY)
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY) {
setbits_le32(priv->base + GPR_REG0, PCIE_PHY_APB_RST |
PCIE_PHY_INIT_RST);
+ ret = hsio_pll_enable(dev);
Is this how Linux handles this PLL ?
Seems like this should be either syscon or clock driver .
[...]
Re: [PATCH 3/7] imx8mp: power-domain: Add PCIe support
On 2/20/24 14:10, Sumit Garg wrote:
Pre-requisite to enable PCIe support on iMX8MP SoC.
This commit message is useless, write a proper one.
Signed-off-by: Sumit Garg
---
drivers/power/domain/imx8mp-hsiomix.c | 50 +--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/power/domain/imx8mp-hsiomix.c
b/drivers/power/domain/imx8mp-hsiomix.c
index e2d772c5ec7..62145e0261b 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -16,14 +16,19 @@
#define GPR_REG0 0x0
#define PCIE_CLOCK_MODULE_EN BIT(0)
#define USB_CLOCK_MODULE_EN BIT(1)
+#define PCIE_PHY_APB_RST BIT(4)
+#define PCIE_PHY_INIT_RST BIT(5)
struct imx8mp_hsiomix_priv {
void __iomem *base;
struct clk clk_usb;
+ struct clk clk_pcie;
struct power_domain pd_bus;
struct power_domain pd_usb;
+ struct power_domain pd_pcie;
struct power_domain pd_usb_phy1;
struct power_domain pd_usb_phy2;
+ struct power_domain pd_pcie_phy;
};
static int imx8mp_hsiomix_on(struct power_domain *power_domain)
@@ -43,6 +48,10 @@ static int imx8mp_hsiomix_on(struct power_domain
*power_domain)
domain = >pd_usb_phy1;
} else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) {
domain = >pd_usb_phy2;
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE) {
+ domain = >pd_pcie;
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY) {
+ domain = >pd_pcie_phy;
} else {
ret = -EINVAL;
goto err_pd;
@@ -54,14 +63,25 @@ static int imx8mp_hsiomix_on(struct power_domain
*power_domain)
ret = clk_enable(>clk_usb);
if (ret)
- goto err_clk;
+ goto err_clk_usb;
+
+ ret = clk_enable(>clk_pcie);
+ if (ret)
+ goto err_clk_pcie;
Does this mean that when USB power domains get enabled, PCIe clock are
also enabled ? Why ?
What if the PCIe clock enable fails, do USB clock remain enabled ?
if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE)
+ setbits_le32(priv->base + GPR_REG0, PCIE_CLOCK_MODULE_EN);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY)
+ setbits_le32(priv->base + GPR_REG0, PCIE_PHY_APB_RST |
+ PCIE_PHY_INIT_RST);
Shouldn't the reset bits be cleared here ?
[...]
Re: [PATCH 2/7] reset: imx: Add support for i.MX8MP reset controller
On 2/20/24 14:10, Sumit Garg wrote:
Pre-requisite to enable PCIe support on iMX8MP SoC.
Please write a proper commit message .
Signed-off-by: Sumit Garg
---
drivers/reset/reset-imx7.c | 114 +
1 file changed, 114 insertions(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index eaef2cc2cdf..c1de84dea8b 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -252,6 +253,115 @@ static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
return 0;
}
+enum imx8mp_src_registers {
+ SRC_SUPERMIX_RCR= 0x0018,
+ SRC_AUDIOMIX_RCR= 0x001c,
+ SRC_MLMIX_RCR = 0x0028,
+ SRC_GPU2D_RCR = 0x0038,
+ SRC_GPU3D_RCR = 0x003c,
+ SRC_VPU_G1_RCR = 0x0048,
+ SRC_VPU_G2_RCR = 0x004c,
+ SRC_VPUVC8KE_RCR= 0x0050,
+ SRC_NOC_RCR = 0x0054,
+};
This seems copied from Linux, include Linux commit ID as of which this
was imported from in commit message.
Re: [PATCH 0/7] imx8mp: Enable PCIe/NVMe support
On 2/20/24 14:10, Sumit Garg wrote:
pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
rather tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Patch #1: Adds PCIe clocks support.
Patch #2: Adds i.MX8MP reset controller support.
Patch #3: Extend i.MX8MP power domain driver with PCIe support
Patch #4: Expose high performance PLL clock required for PCIe PHY
on verdin board.
Patch #5: Adds standalone PCIe PHY support for i.MX8MP SoC.
Patch #6: Adds DW PCIe controller support for iMX8MP SoC.
Patch #7: Enable PCIe/NVMe support for verdin board.
Testing with this patch-set included:
Verdin iMX8MP # pci enum
PCIE-0: Link up (Gen1-x1, Bus0)
Verdin iMX8MP #
Verdin iMX8MP # nvme scan
Verdin iMX8MP #
Verdin iMX8MP # nvme info
Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000720
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Verdin iMX8MP #
Verdin iMX8MP # load nvme 0 $loadaddr
Sumit Garg (7):
clk: imx8mp: Add support for PCIe clocks
reset: imx: Add support for i.MX8MP reset controller
imx8mp: power-domain: Add PCIe support
imx8mp: power-domain: Expose high performance PLL clock
phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
pci: Add DW PCIe controller support for iMX8MP SoC
verdin-imx8mp_defconfig: Enable PCIe/NVMe support
configs/verdin-imx8mp_defconfig | 9 +
drivers/clk/imx/clk-imx8mp.c | 6 +
drivers/pci/Kconfig | 8 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_imx8.c| 348 ++
You can call this pcie_dw_imx.c , the imx6 support can be converted over
to that driver too I guess ?
Re: [PATCH V6 07/20] configs: am62x_evm_a53_defconfig: Switch to bootstd
On 08:48-20240220, Jan Kiszka wrote: > On 19.02.24 19:37, Jan Kiszka wrote: > > On 17.02.24 12:36, Alexander Sverdlin wrote: > >> Hi Jan! > >> > >> On Sat, 2024-02-17 at 09:42 +0100, Jan Kiszka wrote: > >>>> U-Boot 2024.01 (Feb 15 2024 - 01:43:17 +0100) > >>>> > >>>> SoC: AM62X SR1.0 HS-FS > >>>> Model: Texas Instruments AM625 SK > >>>> DRAM: 2 GiB > >>>> Core: 56 devices, 23 uclasses, devicetree: separate > >>>> MMC: mmc@fa1: 0, mmc@fa0: 1 > >>>> Loading Environment from nowhere... OK > >>>> In: serial@280 > >>>> Out: serial@280 > >>>> Err: serial@280 > >>>> Net: eth0: ethernet@800port@1 > >>>> Hit any key to stop autoboot: 0 > >>>> switch to partitions #0, OK > >>>> mmc1 is current device > >>>> SD/MMC found on device 1 > >>>> Failed to load 'uEnv.txt' > >>>> Scanning for bootflows in all bootdevs > >>>> Seq Method State Uclass Part Name > >>>> Filename > >>>> --- --- -- > >>>> > >>>> Scanning global bootmeth 'efi_mgr': > >>>> No EFI system partition > >>>> No EFI system partition > >>>> Failed to persist EFI variables > >>>> Scanning bootdev 'mmc@fa0.bootdev': > >>>> Scanning bootdev 'mmc@fa1.bootdev': > >>>> Unknown uclass 'usb' in label > >>>> link up on port 1, speed 100, full duplex > >>>> BOOTP broadcast 1 > >>>> BOOTP broadcast 2 > >>>> BOOTP broadcast 3 I am pretty sure ethernet is not enabled in upstream u-boot. > >>>> ... > >>>> --- > >>>> > >>>> I suppose TI's BSP has older U-Boot... So it's not providing necessary > >>>> script for BOOTSTD, I suppose? > >>>> > >>> > >>> You can make the BeagleBone boot via EFI, but it requires a hybrid > >>> partition table (ROM loader want DOS, EFI needs GPT). A Debian > >>> integration with this can be found for Isar [1] in this series [2]. It's > >>> only using upstream sources (plus still one u-boot patch to get wifi > >>> working). > >>> > >>> If you want legacy script booting, I suspect you need to flip some extra > >>> switches explicitly by now. > >> > >> Thanks for the hints! > >> I'm wondering, if this was a deliberate "let's stop booting all the > >> pre-existing embedded distros" decision? (buildroot, yocto/meta-ti...) It was more of a "lets standardize one way of booting across all ARM devices as much as we can" effort - EBBR and others inclusive. To that effort, distro_boot and bootstd have made significant steps forward. NOTE: yocto, buildroot etc will need a few tweaks to get things operational unfortunately. BUT, note: bootstd was what beagleplay was introduced upstream as default in the first place - so all we are finding is that introduced behavior. > >> > > > > FWIW, I'm not seeing other boot methods being specifically disabled in > > beagleplay in 2024.01 or even newer. I didn't try the result, but this > > may actually be some other issue and real bug, nothing obviously intended. > > > > I'm not even sure about this anymore, though there is still a bug, just > a different one: > > ... > U-Boot 2024.04-rc2-00040-g3e6f2a94bfc (Feb 20 2024 - 08:42:59 +0100) > > SoC: AM62X SR1.0 GP > Model: BeagleBoard.org BeaglePlay > DRAM: 2 GiB > Core: 98 devices, 27 uclasses, devicetree: separate > MMC: mmc@fa1: 0, mmc@fa0: 1, mmc@fa2: 2 > Loading Environment from nowhere... OK > In:serial@280 > Out: serial@280 > Err: serial@280 > Net: No ethernet found. > > Press SPACE to abort autoboot in 2 seconds > => print bootmeths > bootmeths=script extlinux efi pxe > => bootflow scan -l > Scanning for bootflows in all bootdevs > Seq Method State UclassPart Name Filename > --- --- -- > > Scanning bootdev 'mmc@fa0.bootdev': > 0 efi ready mmc 2 mmc@fa0.bootdev.part_ > efi/boot/bootaa64.efi > Scanning bootdev 'mmc@fa1.bootdev': > 1 extlinux ready mmc 1 mmc@fa1.bootdev.part_ >
Re: [PATCH V6 07/20] configs: am62x_evm_a53_defconfig: Switch to bootstd
On 19:37-20240219, Jan Kiszka wrote: > My personal observation is that continuous integration testings with > all-upstream components is not really a common thing. I saw that with > multiple active SoCs from various vendors. For what it is worth, https://software-dl.ti.com/cicd-report/upstream/ -> we are trying to do that on TI side, though it is still in infancy and test coverage is still more to be desired. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Re: [PATCH 1/1] ext4: detect directories in ext4fs_exists()
On 20/02/2024 11:54, Heinrich Schuchardt wrote:
> While fat_exists() reports directories and files as existing
> ext4fs_exists() only recognizes files. This lead to errors
> when using systemd-boot with an ext4 file-system.
>
> Change ext4fs_exists() to find any type of inode:
> files, directories, symbolic links.
>
> Fixes: a1596438a689 ("ext4fs ls load support")
> Signed-off-by: Heinrich Schuchardt
This doesn't entirely fix systemd-boot, the fs_get_size() call still
winds up in ext4fs_open() which fails because it's a directory...
I poked around to see if I could get this working but it seems like it
won't be simple :/
This is still a valid bugfix though, even if it doesn't totally fix the
issue.
Reviwed-by: Caleb Connolly
> ---
> I still need to figure out a good test. Currently 'xxd' is the only command
> invoking fs_exists().
> ---
> fs/ext4/ext4_common.c | 5 ++---
> fs/ext4/ext4_common.h | 2 ++
> fs/ext4/ext4fs.c | 11 +++
> 3 files changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
> index ea9b92298ba..365c5147c4b 100644
> --- a/fs/ext4/ext4_common.c
> +++ b/fs/ext4/ext4_common.c
> @@ -2214,9 +2214,8 @@ static char *ext4fs_read_symlink(struct ext2fs_node
> *node)
> return symlink;
> }
>
> -static int ext4fs_find_file1(const char *currpath,
> - struct ext2fs_node *currroot,
> - struct ext2fs_node **currfound, int *foundtype)
> +int ext4fs_find_file1(const char *currpath, struct ext2fs_node *currroot,
> + struct ext2fs_node **currfound, int *foundtype)
> {
> char fpath[strlen(currpath) + 1];
> char *name = fpath;
> diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h
> index 504c708b064..84500e990aa 100644
> --- a/fs/ext4/ext4_common.h
> +++ b/fs/ext4/ext4_common.h
> @@ -54,6 +54,8 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
> loff_t len,
>char *buf, loff_t *actread);
> int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode,
> struct ext2fs_node **foundnode, int expecttype);
> +int ext4fs_find_file1(const char *currpath, struct ext2fs_node *currroot,
> + struct ext2fs_node **currfound, int *foundtype);
> int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
> struct ext2fs_node **fnode, int *ftype);
>
> diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
> index 3b12ec54fa2..b1359d14909 100644
> --- a/fs/ext4/ext4fs.c
> +++ b/fs/ext4/ext4fs.c
> @@ -208,11 +208,14 @@ int ext4fs_ls(const char *dirname)
>
> int ext4fs_exists(const char *filename)
> {
> - loff_t file_len;
> - int ret;
> + struct ext2fs_node *dirnode = NULL;
> + int filetype;
>
> - ret = ext4fs_open(filename, _len);
> - return ret == 0;
> + if (!filename)
> + return 0;
> +
> + return ext4fs_find_file1(filename, _root->diropen, ,
> + );
> }
>
> int ext4fs_size(const char *filename, loff_t *size)
--
// Caleb (they/them)
Re: [PATCH 1/3] mmc: Convert hs400_tuning flag from u8 to bool
On 20/02/2024 11:27, Marek Vasut wrote: > On 2/20/24 11:57, Paul Barker wrote: >> On 20/02/2024 08:37, Marek Vasut wrote: >>> This hs400_tuning is a flag, make it bool. No functional change. >>> This will be useful in the following patch, which adds another >>> more generic flag, where the compiler can better use the space >>> now reserved for the u8 to store more flags in it. >> >> The minimum size for a bool is one byte so there likely won't be any >> improvement in struct size from using bool instead of u8 for >> `hs400_tuning` here and `tuning` added in the next patch. I still think >> it's a good change to make though, bool is the right type for an on/off >> flag. > > The compiler does not do boolean packing in structures ? The compiler will only pack booleans if you explicitly say that only one bit of memory is needed, e.g.: bool tuning:1; bool hs400_tuning:1; Otherwise the assumption is that you may wish to take the address of each field and so each one must have a distinct address in memory. Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
[PATCH v1 1/1] arch:arm: Agilex5 enablement
This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim --- arch/arm/Kconfig | 9 +- arch/arm/dts/Makefile | 32 + .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 11 +- arch/arm/dts/socfpga_agilex5_socdk.dts| 67 +- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi| 2 +- arch/arm/mach-socfpga/Kconfig | 125 +- arch/arm/mach-socfpga/Makefile| 99 +- arch/arm/mach-socfpga/board.c | 2 - .../include/mach/base_addr_soc64.h| 16 +-- board/intel/agilex5-socdk/MAINTAINERS | 2 + board/intel/agilex5-socdk/Makefile| 2 +- board/intel/agilex5-socdk/socfpga.c | 2 +- configs/socfpga_agilex5_defconfig | 33 - include/configs/socfpga_agilex5_socdk.h | 2 +- include/configs/socfpga_soc64_common.h| 40 +- 15 files changed, 63 insertions(+), 381 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43d5ad346f..c8d91669da 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,7 +28,7 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 2500 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 1 if ARCH_ZYNQMP - default 4 if ARCH_SOCFPGA && ARM64 + default 2 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 default 0 help For platforms with ARMv8-A and ARMv7-A which features a system @@ -1088,14 +1088,14 @@ config ARCH_SNAPDRAGON select SPMI imply CMD_DM -config ARCH_SOCFPGA - bool "Altera SOCFPGA family" +bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 select ARM64 if TARGET_SOCFPGA_SOC64 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL + select GICV2 select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL @@ -1109,7 +1109,7 @@ config ARCH_SOCFPGA select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET - select SPL_WATCHDOG + select SPL_WATCHDOG if !TARGET_SOCFPGA_AGILEX5 select SUPPORT_SPL select SYS_NS16550 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 @@ -1123,6 +1123,7 @@ config ARCH_SOCFPGA imply DM_SPI imply DM_SPI_FLASH imply FAT_WRITE + imply MTD imply SPL imply SPL_DM imply SPL_DM_SPI diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 90d933a9ae..646f4feaf7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -543,37 +543,7 @@ dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ - socfpga_agilex_n6010.dtb\ - socfpga_agilex_socdk.dtb\ - socfpga_agilex_socdk_nand.dtb \ - socfpga_agilex_socdk_qspi.dtb \ - socfpga_agilex5_socdk.dtb \ - socfpga_agilex5_emu.dtb \ - socfpga_agilex7m_socdk.dtb \ - socfpga_agilex7m_socdk_nand.dtb \ - socfpga_arria5_secu1.dtb\ - socfpga_arria5_socdk.dtb\ - socfpga_arria10_chameleonv3_270_2.dtb \ - socfpga_arria10_chameleonv3_270_3.dtb \ - socfpga_arria10_chameleonv3_480_2.dtb \ - socfpga_arria10_socdk_nand.dtb \ - socfpga_arria10_socdk_qspi.dtb \ - socfpga_arria10_socdk_sdmmc.dtb \ - socfpga_cyclone5_mcvevk.dtb \ - socfpga_cyclone5_is1.dtb\ - socfpga_cyclone5_socdk.dtb \ - socfpga_cyclone5_dbm_soc1.dtb \ - socfpga_cyclone5_de0_nano_soc.dtb \ - socfpga_cyclone5_de1_soc.dtb\ - socfpga_cyclone5_de10_nano.dtb \ - socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb \ - socfpga_cyclone5_sr1500.dtb \ - socfpga_cyclone5_vining_fpga.dtb\ - socfpga_n5x_socdk.dtb \ - socfpga_stratix10_socdk.dtb \ - socfpga_stratix10_socdk_nand.dtb\ -
Re: [PATCH] mmc: Drop unused mmc_send_tuning() cmd_error parameter
On 20/02/2024 11:26, Marek Vasut wrote:
> On 2/20/24 11:50, Paul Barker wrote:
>> On 20/02/2024 08:36, Marek Vasut wrote:
>>> The cmd_error parameter is not used, remove it.
>>> [snip]
>>>
>>> diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
>>> index 5a0c61daed5..296aaee7331 100644
>>> --- a/drivers/mmc/mtk-sd.c
>>> +++ b/drivers/mmc/mtk-sd.c
>>> @@ -1131,7 +1131,7 @@ static int hs400_tune_response(struct udevice *dev,
>>> u32 opcode)
>>> i << PAD_CMD_TUNE_RX_DLY3_S);
>>>
>>> for (j = 0; j < 3; j++) {
>>> - mmc_send_tuning(mmc, opcode, _err);
>>> + cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err) {
>>> cmd_delay |= (1 << i);
>>> } else {
>>> @@ -1181,7 +1181,7 @@ static int msdc_tune_response(struct udevice *dev,
>>> u32 opcode)
>>> i << MSDC_PAD_TUNE_CMDRDLY_S);
>>>
>>> for (j = 0; j < 3; j++) {
>>> - mmc_send_tuning(mmc, opcode, _err);
>>> + cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err) {
>>> rise_delay |= (1 << i);
>>> } else {
>>> @@ -1203,7 +1203,7 @@ static int msdc_tune_response(struct udevice *dev,
>>> u32 opcode)
>>> i << MSDC_PAD_TUNE_CMDRDLY_S);
>>>
>>> for (j = 0; j < 3; j++) {
>>> - mmc_send_tuning(mmc, opcode, _err);
>>> + cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err) {
>>> fall_delay |= (1 << i);
>>> } else {
>>> @@ -1238,7 +1238,7 @@ skip_fall:
>>> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
>>> i << MSDC_PAD_TUNE_CMDRRDLY_S);
>>>
>>> - mmc_send_tuning(mmc, opcode, _err);
>>> + cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err)
>>> internal_delay |= (1 << i);
>>> }
>>> @@ -1264,7 +1264,6 @@ static int msdc_tune_data(struct udevice *dev, u32
>>> opcode)
>>> struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
>>> u8 final_delay, final_maxlen;
>>> void __iomem *tune_reg = >base->pad_tune;
>>> - int cmd_err;
>>> int i, ret;
>>>
>>> if (host->dev_comp->pad_tune0)
>>> @@ -1277,10 +1276,10 @@ static int msdc_tune_data(struct udevice *dev, u32
>>> opcode)
>>> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
>>> i << MSDC_PAD_TUNE_DATRRDLY_S);
>>>
>>> - ret = mmc_send_tuning(mmc, opcode, _err);
>>> + ret = mmc_send_tuning(mmc, opcode);
>>> if (!ret) {
>>> rise_delay |= (1 << i);
>>> - } else if (cmd_err) {
>>> + } else {
>>> /* in this case, retune response is needed */
>>> ret = msdc_tune_response(dev, opcode);
>>> if (ret)
>>> @@ -1300,10 +1299,10 @@ static int msdc_tune_data(struct udevice *dev, u32
>>> opcode)
>>> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
>>> i << MSDC_PAD_TUNE_DATRRDLY_S);
>>>
>>> - ret = mmc_send_tuning(mmc, opcode, _err);
>>> + ret = mmc_send_tuning(mmc, opcode);
>>> if (!ret) {
>>> fall_delay |= (1 << i);
>>> - } else if (cmd_err) {
>>> + } else {
>>> /* in this case, retune response is needed */
>>> ret = msdc_tune_response(dev, opcode);
>>> if (ret)
>>
>> This driver (mtk-sd.c) seems to be the only one that really uses the
>> `cmd_error` parameter.
>>
>> Looking at the implementation of mmc_send_tuning() in Linux, this
>> parameter is used so that a caller can differentiate between a command
>> error and a data error. I don't know enough details about MMC to
>> understand the distinction, but I assume there is some reason for this.
>> So I wonder if the mtk-sd driver will still work if those error paths
>> are taken for data errors and not just command errors. Has this change
>> been tested on some board which uses this driver?
>
> Not by me, so far this driver used uninitialized error value and assumed
> it was initialized as far as I can tell, so it is likely already broken.
+To: Ryder Lee, Weijie Gao, Chunfeng Yun
+Cc: gss_mtk_uboot_upstr...@mediatek.com
Do you have any input as ARM MEDIATEK maintainers?
--
Paul Barker
OpenPGP_0x27F4B3459F002257.asc
Description: OpenPGP public key
OpenPGP_signature.asc
Description: OpenPGP digital signature
Re: [PATCH v4 16/39] board: dragonboard410c: add chainloaded config fragment
On Thu, 15 Feb 2024 at 21:03, Caleb Connolly wrote: > > Add a config fragment for building U-Boot such that it can be > chainloaded by aboot/LK rather than being flashed directly to the aboot > partition. How does this work in practice? I think a lot of devices, one example I see is signed vs unsigned, or emmc vs other storage, have to configs, how would a user choose with LK vs the other option here? > Reviewed-by: Neil Armstrong > Signed-off-by: Caleb Connolly > --- > board/qualcomm/dragonboard410c/configs/chainloaded.config | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config > b/board/qualcomm/dragonboard410c/configs/chainloaded.config > new file mode 100644 > index ..3fd064924a1f > --- /dev/null > +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config > @@ -0,0 +1,7 @@ > +# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set > +CONFIG_TEXT_BASE=0x0 > +# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set > +# CONFIG_REMAKE_ELF is not set > +CONFIG_POSITION_INDEPENDENT=y > +CONFIG_INIT_SP_RELATIVE=y > +CONFIG_SYS_INIT_SP_BSS_OFFSET=524288 > > -- > 2.43.1 >
Re: [PATCH v4 38/39] dts: qcs404-evb: replace with upstream DT
On Fri, 16 Feb 2024 at 02:23, Caleb Connolly wrote:
>
> Drop the U-Boot specific DTS in favour of upstream. We'll only include
> the -4000 variant as that is what U-Boot already supported.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/dts/Makefile|2 +-
> arch/arm/dts/pms405.dtsi | 149 +++
> arch/arm/dts/qcs404-evb-4000-u-boot.dtsi | 48 +
> arch/arm/dts/qcs404-evb-4000.dts | 96 ++
> arch/arm/dts/qcs404-evb-uboot.dtsi | 30 -
> arch/arm/dts/qcs404-evb.dts | 390 ---
> arch/arm/dts/qcs404-evb.dtsi | 389 +++
> arch/arm/dts/qcs404.dtsi | 1829
> ++
> 8 files changed, 2512 insertions(+), 421 deletions(-)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 54aaf022c2eb..c4f0873dbb1f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -635,7 +635,7 @@ dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
> apq8096-db820c.dtb \
> sdm845-db845c.dtb \
> sdm845-samsung-starqltechn.dtb \
> - qcs404-evb.dtb
> + qcs404-evb-4000.dtb
>
> dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
>
> diff --git a/arch/arm/dts/pms405.dtsi b/arch/arm/dts/pms405.dtsi
> new file mode 100644
> index ..461ad97032f7
> --- /dev/null
> +++ b/arch/arm/dts/pms405.dtsi
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, Linaro Limited
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +/ {
> + thermal-zones {
> + pms405-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <_temp>;
> +
> + trips {
> + pms405_alert0: pms405-alert0 {
> + temperature = <105000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + pms405_crit: pms405-crit {
> + temperature = <125000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> +};
> +
> +_bus {
> + pms405_0: pms405@0 {
> + compatible = "qcom,pms405", "qcom,spmi-pmic";
> + reg = <0x0 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pms405_gpios: gpio@c000 {
> + compatible = "qcom,pms405-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <_gpios 0 0 12>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + pon@800 {
> + compatible = "qcom,pms405-pon";
> + reg = <0x0800>;
> + mode-bootloader = <0x2>;
> + mode-recovery = <0x1>;
> +
> + pwrkey {
> + compatible = "qcom,pm8941-pwrkey";
> + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> + debounce = <15625>;
> + bias-pull-up;
> + linux,code = ;
> + };
> + };
> +
> + pms405_temp: temp-alarm@2400 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0x2400>;
> + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
> + io-channels = <_adc ADC5_DIE_TEMP>;
> + io-channel-names = "thermal";
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pms405_adc: adc@3100 {
> + compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
> + reg = <0x3100>;
> + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> +
> + channel@0 {
> + reg = ;
> + qcom,pre-scaling = <1 1>;
> + label = "ref_gnd";
> + };
> +
> + channel@1 {
> + reg = ;
> +
Re: [PATCH v4 30/39] dt-bindings: import headers for MSM8916
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote: > > Import the dt-bindings headers in preparation for switching to upstream > DTS for MSM8916. > > Taken from kernel tag v6.7 > > Reviewed-by: Neil Armstrong > Signed-off-by: Caleb Connolly > --- > include/dt-bindings/arm/coresight-cti-dt.h | 37 + > include/dt-bindings/clock/qcom,rpmcc.h | 174 > > include/dt-bindings/interconnect/qcom,msm8916.h | 100 ++ > include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 106 +++ > include/dt-bindings/reset/qcom,gcc-msm8916.h| 100 ++ > include/dt-bindings/sound/apq8016-lpass.h | 9 ++ > include/dt-bindings/sound/qcom,lpass.h | 46 +++ > 7 files changed, 572 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/include/dt-bindings/arm/coresight-cti-dt.h > b/include/dt-bindings/arm/coresight-cti-dt.h > new file mode 100644 > index ..61e7bdf8ea6e > --- /dev/null > +++ b/include/dt-bindings/arm/coresight-cti-dt.h > @@ -0,0 +1,37 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * This header provides constants for the defined trigger signal > + * types on CoreSight CTI. > + */ > + > +#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H > +#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H > + > +#define GEN_IO 0 > +#define GEN_INTREQ 1 > +#define GEN_INTACK 2 > +#define GEN_HALTREQ3 > +#define GEN_RESTARTREQ 4 > +#define PE_EDBGREQ 5 > +#define PE_DBGRESTART 6 > +#define PE_CTIIRQ 7 > +#define PE_PMUIRQ 8 > +#define PE_DBGTRIGGER 9 > +#define ETM_EXTOUT 10 > +#define ETM_EXTIN 11 > +#define SNK_FULL 12 > +#define SNK_ACQCOMP13 > +#define SNK_FLUSHCOMP 14 > +#define SNK_FLUSHIN15 > +#define SNK_TRIGIN 16 > +#define STM_ASYNCOUT 17 > +#define STM_TOUT_SPTE 18 > +#define STM_TOUT_SW19 > +#define STM_TOUT_HETE 20 > +#define STM_HWEVENT21 > +#define ELA_TSTART 22 > +#define ELA_TSTOP 23 > +#define ELA_DBGREQ 24 > +#define CTI_TRIG_MAX 25 > + > +#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */ > diff --git a/include/dt-bindings/clock/qcom,rpmcc.h > b/include/dt-bindings/clock/qcom,rpmcc.h > new file mode 100644 > index ..46309c9953b2 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,rpmcc.h > @@ -0,0 +1,174 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright 2015 Linaro Limited > + */ > + > +#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H > +#define _DT_BINDINGS_CLK_MSM_RPMCC_H > + > +/* RPM clocks */ > +#define RPM_PXO_CLK0 > +#define RPM_PXO_A_CLK 1 > +#define RPM_CXO_CLK2 > +#define RPM_CXO_A_CLK 3 > +#define RPM_APPS_FABRIC_CLK4 > +#define RPM_APPS_FABRIC_A_CLK 5 > +#define RPM_CFPB_CLK 6 > +#define RPM_CFPB_A_CLK 7 > +#define RPM_QDSS_CLK 8 > +#define RPM_QDSS_A_CLK 9 > +#define RPM_DAYTONA_FABRIC_CLK 10 > +#define RPM_DAYTONA_FABRIC_A_CLK 11 > +#define RPM_EBI1_CLK 12 > +#define RPM_EBI1_A_CLK 13 > +#define RPM_MM_FABRIC_CLK 14 > +#define RPM_MM_FABRIC_A_CLK15 > +#define RPM_MMFPB_CLK 16 > +#define RPM_MMFPB_A_CLK17 > +#define RPM_SYS_FABRIC_CLK 18 > +#define RPM_SYS_FABRIC_A_CLK 19 > +#define RPM_SFPB_CLK 20 > +#define RPM_SFPB_A_CLK 21 > +#define RPM_SMI_CLK22 > +#define RPM_SMI_A_CLK 23 > +#define RPM_PLL4_CLK 24 > +#define RPM_XO_D0 25 > +#define RPM_XO_D1 26 > +#define RPM_XO_A0 27 > +#define RPM_XO_A1 28 > +#define RPM_XO_A2 29 > +#define RPM_NSS_FABRIC_0_CLK 30 > +#define RPM_NSS_FABRIC_0_A_CLK 31 > +#define RPM_NSS_FABRIC_1_CLK 32 > +#define RPM_NSS_FABRIC_1_A_CLK 33 > + > +/* SMD RPM clocks */ > +#define RPM_SMD_XO_CLK_SRC 0 > +#define RPM_SMD_XO_A_CLK_SRC 1 > +#define RPM_SMD_PCNOC_CLK 2 > +#define RPM_SMD_PCNOC_A_CLK3 > +#define RPM_SMD_SNOC_CLK 4 > +#define RPM_SMD_SNOC_A_CLK 5 > +#define RPM_SMD_BIMC_CLK 6 > +#define RPM_SMD_BIMC_A_CLK 7 > +#define RPM_SMD_QDSS_CLK 8 > +#define RPM_SMD_QDSS_A_CLK 9 > +#define
Re: [PATCH v4 31/39] dts: msm8916: import PMIC dtsi files
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
>
> Import the supporting pm8916.dtsi and msm8916-pm8916.dtsi files from
> upstream in preparation for switching boards over.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/dts/msm8916-pm8916.dtsi | 157 ++
> arch/arm/dts/pm8916.dtsi | 178
> +++
> 2 files changed, 335 insertions(+)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/msm8916-pm8916.dtsi
> b/arch/arm/dts/msm8916-pm8916.dtsi
> new file mode 100644
> index ..b1a7eafbee31
> --- /dev/null
> +++ b/arch/arm/dts/msm8916-pm8916.dtsi
> @@ -0,0 +1,157 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * msm8916-pm8916.dtsi describes common properties (e.g. regulator
> connections)
> + * that apply to most devices that make use of the MSM8916 SoC and PM8916
> PMIC.
> + * Many regulators have a fixed purpose in the original reference design and
> + * were rarely re-used for different purposes. Devices that deviate from the
> + * typical reference design should not make use of this include and instead
> add
> + * the necessary properties in the board-specific device tree.
> + */
> +
> +#include "msm8916.dtsi"
> +#include "pm8916.dtsi"
> +
> + {
> + vdda-supply = <_l2>;
> +};
> +
> +_dsi0 {
> + vdda-supply = <_l2>;
> + vddio-supply = <_l6>;
> +};
> +
> +_dsi0_phy {
> + vddio-supply = <_l6>;
> +};
> +
> + {
> + pll-supply = <_l7>;
> +};
> +
> +_codec {
> + vdd-cdc-io-supply = <_l5>;
> + vdd-cdc-tx-rx-cx-supply = <_l5>;
> + vdd-micbias-supply = <_l13>;
> +};
> +
> +_1 {
> + vmmc-supply = <_l8>;
> + vqmmc-supply = <_l5>;
> +};
> +
> +_2 {
> + vmmc-supply = <_l11>;
> + vqmmc-supply = <_l12>;
> +};
> +
> +_hs_phy {
> + v1p8-supply = <_l7>;
> + v3p3-supply = <_l13>;
> +};
> +
> + {
> + vddpx-supply = <_l7>;
> +};
> +
> +_iris {
> + vddxo-supply = <_l7>;
> + vddrfa-supply = <_s3>;
> + vddpa-supply = <_l9>;
> + vdddig-supply = <_l5>;
> +};
> +
> +_requests {
> + pm8916_rpm_regulators: regulators {
> + compatible = "qcom,rpm-pm8916-regulators";
> + vdd_l1_l2_l3-supply = <_s3>;
> + vdd_l4_l5_l6-supply = <_s4>;
> + vdd_l7-supply = <_s4>;
> +
> + /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */
> +
> + pm8916_s3: s3 {
> + regulator-min-microvolt = <125>;
> + regulator-max-microvolt = <135>;
> + regulator-always-on; /* Needed for L2 */
> + };
> +
> + pm8916_s4: s4 {
> + regulator-min-microvolt = <185>;
> + regulator-max-microvolt = <215>;
> + regulator-always-on; /* Needed for L5/L7 */
> + };
> +
> + /*
> +* Some of the regulators are unused or managed by another
> +* processor (e.g. the modem). We should still define nodes
> for
> +* them to ensure the vote from the application processor can
> be
> +* dropped in case the regulators are already on during boot.
> +*
> +* The labels for these nodes are omitted on purpose because
> +* boards should configure a proper voltage before using them.
> +*/
> + l1 {};
> +
> + pm8916_l2: l2 {
> + regulator-min-microvolt = <120>;
> + regulator-max-microvolt = <120>;
> + regulator-always-on; /* Needed for LPDDR RAM */
> + };
> +
> + /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */
> +
> + l4 {};
> +
> + pm8916_l5: l5 {
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + regulator-always-on; /* Needed for most digital I/O */
> + };
> +
> + pm8916_l6: l6 {
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + };
> +
> + pm8916_l7: l7 {
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + regulator-always-on; /* Needed for CPU PLL */
> + };
> +
> + pm8916_l8: l8 {
> + regulator-min-microvolt = <290>;
> + regulator-max-microvolt = <290>;
> + };
> +
> + pm8916_l9: l9 {
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt =
Re: [PATCH v4 33/39] dt-bindings: import headers for MSM8996
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote: > > Import dt-binding headers for MSM8996/APQ8096 from Linux. > > Taken from kernel tag v6.7 > > Reviewed-by: Neil Armstrong > Signed-off-by: Caleb Connolly > --- > include/dt-bindings/clock/qcom,gcc-msm8996.h | 362 > + > include/dt-bindings/clock/qcom,mmcc-msm8996.h | 295 + > .../dt-bindings/interconnect/qcom,msm8996-cbf.h| 12 + > include/dt-bindings/interconnect/qcom,msm8996.h| 163 ++ > include/dt-bindings/sound/qcom,wcd9335.h | 15 + > 5 files changed, 847 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h > b/include/dt-bindings/clock/qcom,gcc-msm8996.h > new file mode 100644 > index ..ddfd6fd73081 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h > @@ -0,0 +1,362 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2015, The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H > +#define _DT_BINDINGS_CLK_MSM_GCC_8996_H > + > +#define GPLL0_EARLY0 > +#define GPLL0 1 > +#define GPLL1_EARLY2 > +#define GPLL1 3 > +#define GPLL2_EARLY4 > +#define GPLL2 5 > +#define GPLL3_EARLY6 > +#define GPLL3 7 > +#define GPLL4_EARLY8 > +#define GPLL4 9 > +#define SYSTEM_NOC_CLK_SRC 10 > +/* U-Boot: KConfig check in CI erroneously picks this up, it's unused > + * anyway so comment it out for now > + */ > +//#define CONFIG _NOC_CLK_SRC 11 > +#define PERIPH_NOC_CLK_SRC 12 > +#define MMSS_BIMC_GFX_CLK_SRC 13 > +#define USB30_MASTER_CLK_SRC 14 > +#define USB30_MOCK_UTMI_CLK_SRC15 > +#define USB3_PHY_AUX_CLK_SRC 16 > +#define USB20_MASTER_CLK_SRC 17 > +#define USB20_MOCK_UTMI_CLK_SRC18 > +#define SDCC1_APPS_CLK_SRC 19 > +#define SDCC1_ICE_CORE_CLK_SRC 20 > +#define SDCC2_APPS_CLK_SRC 21 > +#define SDCC3_APPS_CLK_SRC 22 > +#define SDCC4_APPS_CLK_SRC 23 > +#define BLSP1_QUP1_SPI_APPS_CLK_SRC24 > +#define BLSP1_QUP1_I2C_APPS_CLK_SRC25 > +#define BLSP1_UART1_APPS_CLK_SRC 26 > +#define BLSP1_QUP2_SPI_APPS_CLK_SRC27 > +#define BLSP1_QUP2_I2C_APPS_CLK_SRC28 > +#define BLSP1_UART2_APPS_CLK_SRC 29 > +#define BLSP1_QUP3_SPI_APPS_CLK_SRC30 > +#define BLSP1_QUP3_I2C_APPS_CLK_SRC31 > +#define BLSP1_UART3_APPS_CLK_SRC 32 > +#define BLSP1_QUP4_SPI_APPS_CLK_SRC33 > +#define BLSP1_QUP4_I2C_APPS_CLK_SRC34 > +#define BLSP1_UART4_APPS_CLK_SRC 35 > +#define BLSP1_QUP5_SPI_APPS_CLK_SRC36 > +#define BLSP1_QUP5_I2C_APPS_CLK_SRC37 > +#define BLSP1_UART5_APPS_CLK_SRC 38 > +#define BLSP1_QUP6_SPI_APPS_CLK_SRC39 > +#define BLSP1_QUP6_I2C_APPS_CLK_SRC40 > +#define BLSP1_UART6_APPS_CLK_SRC 41 > +#define BLSP2_QUP1_SPI_APPS_CLK_SRC42 > +#define BLSP2_QUP1_I2C_APPS_CLK_SRC43 > +#define BLSP2_UART1_APPS_CLK_SRC 44 > +#define BLSP2_QUP2_SPI_APPS_CLK_SRC45 > +#define BLSP2_QUP2_I2C_APPS_CLK_SRC46 > +#define BLSP2_UART2_APPS_CLK_SRC 47 > +#define BLSP2_QUP3_SPI_APPS_CLK_SRC48 > +#define BLSP2_QUP3_I2C_APPS_CLK_SRC49 > +#define BLSP2_UART3_APPS_CLK_SRC 50 > +#define BLSP2_QUP4_SPI_APPS_CLK_SRC51 > +#define BLSP2_QUP4_I2C_APPS_CLK_SRC52 > +#define BLSP2_UART4_APPS_CLK_SRC 53 > +#define
Re: [PATCH v4 34/39] dts: msm8996: import PMIC dtsi files
On Fri, 16 Feb 2024 at 02:23, Caleb Connolly wrote:
>
> Import PM8994 and PMI8994 DTSI files in preparation for switching
> MSM8996 boards to upstream DTS.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/dts/pm8994.dtsi | 152
> ++
> arch/arm/dts/pmi8994.dtsi | 65
> 2 files changed, 217 insertions(+)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/pm8994.dtsi b/arch/arm/dts/pm8994.dtsi
> new file mode 100644
> index ..d44a95caf04a
> --- /dev/null
> +++ b/arch/arm/dts/pm8994.dtsi
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include
> +#include
> +#include
> +#include
> +
> +/ {
> + thermal-zones {
> + pm8994-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <_temp>;
> +
> + trips {
> + pm8994_alert0: pm8994-alert0 {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + pm8994_crit: pm8994-crit {
> + temperature = <125000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> +};
> +
> +_bus {
> +
> + pmic@0 {
> + compatible = "qcom,pm8994", "qcom,spmi-pmic";
> + reg = <0x0 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + rtc@6000 {
> + compatible = "qcom,pm8941-rtc";
> + reg = <0x6000>, <0x6100>;
> + reg-names = "rtc", "alarm";
> + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> + pm8994_pon: pon@800 {
> + compatible = "qcom,pm8916-pon";
> + reg = <0x800>;
> + mode-bootloader = <0x2>;
> + mode-recovery = <0x1>;
> +
> + pwrkey {
> + compatible = "qcom,pm8941-pwrkey";
> + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> + debounce = <15625>;
> + bias-pull-up;
> + linux,code = ;
> + };
> +
> + pm8994_resin: resin {
> + compatible = "qcom,pm8941-resin";
> + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
> + debounce = <15625>;
> + bias-pull-up;
> + status = "disabled";
> + };
> + };
> +
> + pm8994_temp: temp-alarm@2400 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0x2400>;
> + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
> + io-channels = <_vadc VADC_DIE_TEMP>;
> + io-channel-names = "thermal";
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pm8994_vadc: adc@3100 {
> + compatible = "qcom,spmi-vadc";
> + reg = <0x3100>;
> + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> +
> + channel@7 {
> + reg = ;
> + qcom,pre-scaling = <1 3>;
> + label = "vph_pwr";
> + };
> + channel@8 {
> + reg = ;
> + label = "die_temp";
> + };
> + channel@9 {
> + reg = ;
> + label = "ref_625mv";
> + };
> + channel@a {
> + reg = ;
> + label = "ref_1250mv";
> + };
> + channel@e {
> + reg = ;
> + };
> + channel@f {
> + reg = ;
> + };
> + };
> +
> + pm8994_gpios:
Re: [PATCH v4 35/39] dts: dragonboard820c: use correct bindings for clocks
On Fri, 16 Feb 2024 at 02:23, Caleb Connolly wrote:
>
> Don't use hardcoded clock IDs, use the IDs from the dt-bindings to be
> compatible with upstream.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/dts/dragonboard820c.dts | 5 +++--
> drivers/clk/qcom/clock-apq8096.c | 5 +++--
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/dragonboard820c.dts
> b/arch/arm/dts/dragonboard820c.dts
> index 86b7f83d36d6..282c37e28f42 100644
> --- a/arch/arm/dts/dragonboard820c.dts
> +++ b/arch/arm/dts/dragonboard820c.dts
> @@ -8,6 +8,7 @@
> /dts-v1/;
>
> #include "skeleton64.dtsi"
> +#include
>
> / {
> model = "Qualcomm Technologies, Inc. DB820c";
> @@ -78,7 +79,7 @@
> blsp2_uart2: serial@75b {
> compatible = "qcom,msm-uartdm-v1.4",
> "qcom,msm-uartdm";
> reg = <0x75b 0x1000>;
> - clocks = < 4>;
> + clocks = < GCC_BLSP2_UART2_APPS_CLK>;
> clock-names = "core";
> pinctrl-names = "uart";
> pinctrl-0 = <_uart>;
> @@ -89,7 +90,7 @@
> reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
> index = <0x0>;
> bus-width = <4>;
> - clock = < 0>;
> + clock = < GCC_SDCC1_APPS_CLK>;
> clock-frequency = <2>;
> };
>
> diff --git a/drivers/clk/qcom/clock-apq8096.c
> b/drivers/clk/qcom/clock-apq8096.c
> index 1e6fdb5cd42d..a4731613c5e0 100644
> --- a/drivers/clk/qcom/clock-apq8096.c
> +++ b/drivers/clk/qcom/clock-apq8096.c
> @@ -13,6 +13,7 @@
> #include
> #include
> #include
> +#include
>
> #include "clock-qcom.h"
>
> @@ -107,10 +108,10 @@ static ulong apq8096_clk_set_rate(struct clk *clk,
> ulong rate)
> struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>
> switch (clk->id) {
> - case 0: /* SDC1 */
> + case GCC_SDCC1_APPS_CLK: /* SDC1 */
> return clk_init_sdc(priv, rate);
> break;
> - case 4: /*UART2*/
> + case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
> return clk_init_uart(priv);
> default:
> return 0;
>
> --
> 2.43.1
>
Re: [PATCH v4 37/39] dt-bindings: import headers for qcs404
On Fri, 16 Feb 2024 at 02:23, Caleb Connolly wrote: > > Import the headers needed for QCS404-evb. > > Taken from kernel tag v6.7 > > Reviewed-by: Neil Armstrong > Signed-off-by: Caleb Connolly > --- > include/dt-bindings/clock/qcom,turingcc-qcs404.h | 15 +++ > 1 file changed, 15 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h > b/include/dt-bindings/clock/qcom,turingcc-qcs404.h > new file mode 100644 > index ..838faef57c67 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,turingcc-qcs404.h > @@ -0,0 +1,15 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2019, Linaro Ltd > + */ > + > +#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H > +#define _DT_BINDINGS_CLK_TURING_QCS404_H > + > +#define TURING_Q6SS_Q6_AXIM_CLK0 > +#define TURING_Q6SS_AHBM_AON_CLK 1 > +#define TURING_WRAPPER_AON_CLK 2 > +#define TURING_Q6SS_AHBS_AON_CLK 3 > +#define TURING_WRAPPER_QOS_AHBS_AON_CLK4 > + > +#endif > > -- > 2.43.1 >
Re: [PATCH v4 39/39] MAINTAINERS: Qualcomm: add some missing paths
On Fri, 16 Feb 2024 at 02:23, Caleb Connolly wrote: > > Add drivers and DTS files, as well as regex matches for > qcom/qualcomm/snapdragon. > > Reviewed-by: Neil Armstrong > Signed-off-by: Caleb Connolly > --- > MAINTAINERS | 12 > 1 file changed, 8 insertions(+), 4 deletions(-) > Reviewed-by: Sumit Garg -Sumit > diff --git a/MAINTAINERS b/MAINTAINERS > index 46ba17647f3e..8b048b1faf7c 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -576,18 +576,22 @@ M:Caleb Connolly > M: Neil Armstrong > R: Sumit Garg > S: Maintained > -F: arch/arm/mach-snapdragon/ > -F: drivers/button/button-qcom-pmic.c > -F: drivers/clk/qcom/ > +F: arch/arm/dts/msm8*.dtsi > +F: arch/arm/dts/pm8???.dtsi > +F: arch/arm/dts/pms405.dtsi > +F: arch/arm/dts/sdm845.dtsi > +F: drivers/*/*/pm8???-* > F: drivers/gpio/msm_gpio.c > F: drivers/mmc/msm_sdhci.c > F: drivers/phy/msm8916-usbh-phy.c > -F: drivers/pinctrl/qcom/ > F: drivers/serial/serial_msm.c > F: drivers/serial/serial_msm_geni.c > F: drivers/smem/msm_smem.c > F: drivers/spmi/spmi-msm.c > F: drivers/usb/host/ehci-msm.c > +N: qcom > +N: snapdragon > +N: qualcomm > > ARM STI > M: Patrice Chotard > > -- > 2.43.1 >
Re: [PATCH v4 28/39] dts: sdm845: import supporting dtsi files
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
>
> Import the PM8998 and PMI8998 PMIC DTSI files from Linux as well
> as the common audio codec in preperation for replacing board DTS files
s/preperation/preparation/
> with upstream.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/dts/pm8998.dtsi | 130
> +++
> arch/arm/dts/pmi8998.dtsi| 98 +
> arch/arm/dts/sdm845-wcd9340.dtsi | 86 ++
> 3 files changed, 314 insertions(+)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/pm8998.dtsi b/arch/arm/dts/pm8998.dtsi
> new file mode 100644
> index ..3f82715392c6
> --- /dev/null
> +++ b/arch/arm/dts/pm8998.dtsi
> @@ -0,0 +1,130 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/* Copyright 2018 Google LLC. */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/ {
> + thermal-zones {
> + pm8998-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <_temp>;
> +
> + trips {
> + pm8998_alert0: pm8998-alert0 {
> + temperature = <105000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + pm8998_crit: pm8998-crit {
> + temperature = <125000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> +};
> +
> +_bus {
> + pm8998_lsid0: pmic@0 {
> + compatible = "qcom,pm8998", "qcom,spmi-pmic";
> + reg = <0x0 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8998_pon: pon@800 {
> + compatible = "qcom,pm8998-pon";
> +
> + reg = <0x800>;
> + mode-bootloader = <0x2>;
> + mode-recovery = <0x1>;
> +
> + pm8998_pwrkey: pwrkey {
> + compatible = "qcom,pm8941-pwrkey";
> + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> + debounce = <15625>;
> + bias-pull-up;
> + linux,code = ;
> + };
> +
> + pm8998_resin: resin {
> + compatible = "qcom,pm8941-resin";
> + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
> + debounce = <15625>;
> + bias-pull-up;
> + status = "disabled";
> + };
> + };
> +
> + pm8998_temp: temp-alarm@2400 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0x2400>;
> + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
> + io-channels = <_adc ADC5_DIE_TEMP>;
> + io-channel-names = "thermal";
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pm8998_coincell: charger@2800 {
> + compatible = "qcom,pm8998-coincell",
> "qcom,pm8941-coincell";
> + reg = <0x2800>;
> +
> + status = "disabled";
> + };
> +
> + pm8998_adc: adc@3100 {
> + compatible = "qcom,spmi-adc-rev2";
> + reg = <0x3100>;
> + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> +
> + channel@6 {
> + reg = ;
> + label = "die_temp";
> + };
> + };
> +
> + pm8998_adc_tm: adc-tm@3400 {
> + compatible = "qcom,spmi-adc-tm-hc";
> + reg = <0x3400>;
> + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
> + #thermal-sensor-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + rtc@6000 {
> + compatible = "qcom,pm8941-rtc";
> + reg =
Re: [PATCH v4 27/39] dt-bindings: import headers for SDM845
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote: > > Import the DT bindings headers that are used by SDM845 from Linux. > > Taken from kernel tag v6.7 > > Reviewed-by: Neil Armstrong > Signed-off-by: Caleb Connolly > --- > include/dt-bindings/clock/qcom,camcc-sdm845.h | 116 ++ > include/dt-bindings/clock/qcom,dispcc-sdm845.h | 56 +++ > include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24 ++ > include/dt-bindings/clock/qcom,lpass-sdm845.h | 15 + > include/dt-bindings/clock/qcom,rpmh.h | 37 ++ > include/dt-bindings/clock/qcom,videocc-sdm845.h| 35 ++ > include/dt-bindings/dma/qcom-gpi.h | 11 + > include/dt-bindings/firmware/qcom,scm.h| 39 ++ > include/dt-bindings/iio/qcom,spmi-vadc.h | 300 +++ > include/dt-bindings/interconnect/qcom,osm-l3.h | 15 + > include/dt-bindings/interconnect/qcom,sdm845.h | 150 > include/dt-bindings/phy/phy-qcom-qmp.h | 20 + > include/dt-bindings/phy/phy-qcom-qusb2.h | 37 ++ > include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 164 > include/dt-bindings/power/qcom-rpmpd.h | 412 > + > .../dt-bindings/regulator/qcom,rpmh-regulator.h| 36 ++ > include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 + > include/dt-bindings/reset/qcom,sdm845-pdc.h| 22 ++ > include/dt-bindings/soc/qcom,apr.h | 28 ++ > include/dt-bindings/soc/qcom,rpmh-rsc.h| 14 + > include/dt-bindings/sound/qcom,q6afe.h | 9 + > include/dt-bindings/sound/qcom,q6asm.h | 26 ++ > include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 234 > 23 files changed, 1817 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h > b/include/dt-bindings/clock/qcom,camcc-sdm845.h > new file mode 100644 > index ..4f7a2d2320bf > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,camcc-sdm845.h > @@ -0,0 +1,116 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H > +#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H > + > +/* CAM_CC clock registers */ > +#define CAM_CC_BPS_AHB_CLK 0 > +#define CAM_CC_BPS_AREG_CLK1 > +#define CAM_CC_BPS_AXI_CLK 2 > +#define CAM_CC_BPS_CLK 3 > +#define CAM_CC_BPS_CLK_SRC 4 > +#define CAM_CC_CAMNOC_ATB_CLK 5 > +#define CAM_CC_CAMNOC_AXI_CLK 6 > +#define CAM_CC_CCI_CLK 7 > +#define CAM_CC_CCI_CLK_SRC 8 > +#define CAM_CC_CPAS_AHB_CLK9 > +#define CAM_CC_CPHY_RX_CLK_SRC 10 > +#define CAM_CC_CSI0PHYTIMER_CLK11 > +#define CAM_CC_CSI0PHYTIMER_CLK_SRC12 > +#define CAM_CC_CSI1PHYTIMER_CLK13 > +#define CAM_CC_CSI1PHYTIMER_CLK_SRC14 > +#define CAM_CC_CSI2PHYTIMER_CLK15 > +#define CAM_CC_CSI2PHYTIMER_CLK_SRC16 > +#define CAM_CC_CSI3PHYTIMER_CLK17 > +#define CAM_CC_CSI3PHYTIMER_CLK_SRC18 > +#define CAM_CC_CSIPHY0_CLK 19 > +#define CAM_CC_CSIPHY1_CLK 20 > +#define CAM_CC_CSIPHY2_CLK 21 > +#define CAM_CC_CSIPHY3_CLK 22 > +#define CAM_CC_FAST_AHB_CLK_SRC23 > +#define CAM_CC_FD_CORE_CLK 24 > +#define CAM_CC_FD_CORE_CLK_SRC 25 > +#define CAM_CC_FD_CORE_UAR_CLK 26 > +#define CAM_CC_ICP_APB_CLK 27 > +#define CAM_CC_ICP_ATB_CLK 28 > +#define CAM_CC_ICP_CLK 29 > +#define CAM_CC_ICP_CLK_SRC 30 > +#define CAM_CC_ICP_CTI_CLK 31 > +#define CAM_CC_ICP_TS_CLK 32 > +#define CAM_CC_IFE_0_AXI_CLK 33 > +#define CAM_CC_IFE_0_CLK 34 > +#define CAM_CC_IFE_0_CLK_SRC 35 > +#define CAM_CC_IFE_0_CPHY_RX_CLK 36 > +#define CAM_CC_IFE_0_CSID_CLK 37 > +#define CAM_CC_IFE_0_CSID_CLK_SRC 38 > +#define CAM_CC_IFE_0_DSP_CLK 39 > +#define CAM_CC_IFE_1_AXI_CLK 40 > +#define CAM_CC_IFE_1_CLK 41 > +#define CAM_CC_IFE_1_CLK_SRC 42 > +#define
Re: [PATCH v4 26/39] doc: board/qualcomm: link to APQ8016 TRM
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote: > > The MSM8916/APQ8016 Technical Reference Manual is publicly available and > contains a lot of useful register maps for many core parts of the SoC. > Include an archive.org link to it in the dragonboard410c documentation. > > Signed-off-by: Caleb Connolly > --- > doc/board/qualcomm/dragonboard410c.rst | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/doc/board/qualcomm/dragonboard410c.rst > b/doc/board/qualcomm/dragonboard410c.rst > index d0de9dbcbc9a..34629241110c 100644 > --- a/doc/board/qualcomm/dragonboard410c.rst > +++ b/doc/board/qualcomm/dragonboard410c.rst > @@ -14,6 +14,8 @@ through LK. This is no longer the case, now U-Boot can > replace LK entirely. > > .. _96Boards product page: https://www.96boards.org/product/dragonboard410c/ > > +.. _MSM8916/SD410/APQ8016 Technical Reference Manual: > https://web.archive.org/web/20210525022203/https://developer.qualcomm.com/qfile/35259/lm80-p0436-100_d_snapdragon_410e_apq8016e_tech_reference_manual_revd.pdf > + > Installation > > First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for > ``dragonboard410c``:: > > -- > 2.43.1 >
Re: [PATCH v4 07/39] serial: msm: add debug UART
On Tue, 20 Feb 2024 at 17:09, Caleb Connolly wrote: > > > > On 20/02/2024 06:08, Sumit Garg wrote: > > On Fri, 16 Feb 2024 at 02:22, Caleb Connolly > > wrote: > >> > >> Introduce support for early debugging. This relies on the previous stage > >> bootloader to initialise the UART clocks, when running with U-Boot as > >> the primary bootloader this feature doesn't work. It will require a way > >> to configure the clocks before the driver model is available. > >> > >> Signed-off-by: Caleb Connolly > >> --- > >> drivers/serial/Kconfig | 8 > >> drivers/serial/serial_msm.c | 37 + > >> 2 files changed, 45 insertions(+) > >> > >> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig > >> index 26460c4e0cab..fbd351a47859 100644 > >> --- a/drivers/serial/Kconfig > >> +++ b/drivers/serial/Kconfig > >> @@ -319,6 +319,14 @@ config DEBUG_UART_S5P > >> will need to provide parameters to make this work. The driver > >> will > >> be available until the real driver-model serial is running. > >> > >> +config DEBUG_UART_MSM > >> + bool "Qualcomm QUP UART debug" > >> + depends on ARCH_SNAPDRAGON > > > > Since this debug UART only works for chainloaded configuration, can we > > somehow add explicit dependency here? Something like !REMAKE_ELF? > > With a small patch (which didn't make it into v4 apparently) the > apq8016_clk_init_uart() function from clock-apq8016 can be adjusted to > just take a base address rather than "struct msm_clk_priv". It can then > be called from debug_uart_init() and allows for debug UART to be used > when U-Boot is running as the first stage. > > This is definitely not ideal (although fwiw if the GPLLs were configured > right then this same function could maybe work on QCS404 as well QCS404 is chainloaded config too, so the debug UART should work there. > - the > RCGs are at the same physical addresses), but I don't think gating it > behind REMAKE_ELF or something is a great solution here. I don't have a strong opinion here and I could live with just a documentation update for debug UART too. -Sumit
Re: [PATCH v4 25/39] doc: board/qualcomm: document generic targets
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote: > > Replace the board specific docs with a generic board.rst file which > documents the build/boot process for the sdm845 and qcs404 boards now > that the only differences are the DTB in use. > > At the same time, create a debugging page to document some useful > snippets and tips for working with Qualcomm platforms. > > Reviewed-by: Neil Armstrong > Signed-off-by: Caleb Connolly > --- > doc/board/qualcomm/board.rst | 125 + > doc/board/qualcomm/debugging.rst | 61 ++ > doc/board/qualcomm/index.rst | 4 +- > doc/board/qualcomm/qcs404.rst| 79 -- > doc/board/qualcomm/sdm845.rst| 167 > --- > 5 files changed, 188 insertions(+), 248 deletions(-) > Apart from minor nits below, feel free to add: Reviewed-by: Sumit Garg -Sumit > diff --git a/doc/board/qualcomm/board.rst b/doc/board/qualcomm/board.rst > new file mode 100644 > index ..4d793209f9e3 > --- /dev/null > +++ b/doc/board/qualcomm/board.rst > @@ -0,0 +1,125 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > +.. sectionauthor:: Dzmitry Sankouski > + > +Qualcomm generic boards > +=== > + > +About this > +-- > +This document describes how to build and run U-Boot for Qualcomm generic > +boards. Right now the generic target supports the Snapdragon 845 SoC, however > +it's expected to support more SoCs going forward. > + > +SDM845 - high-end qualcomm chip, introduced in late 2017. > +Mostly used in flagship phones and tablets of 2018. > + > +The current boot flow support loading u-boot as an Android boot image via s/support/supports/ > +Qualcomm's UEFI-based ABL (Android) Bootloader. The DTB used by U-Boot will > +be appended to the U-Boot image the same way as when booting Linux. U-Boot > +will then retrieve the DTB during init. This way the memory layout and KASLR > +offset will be populated by ABL. > + > +Installation > + > +Build > +^ > + > + $ ./tools/buildman/buildman -o .output qcom > + > +This will build ``.output/u-boot-nodtb.bin`` using the ``qcom_defconfig``. > + > +Generate FIT image (optional) > +^ > +See doc/uImage.FIT for more details > + > +Pack android boot image > +^^^ > +We'll assemble android boot image with ``u-boot-nodtb.bin`` instead of linux > kernel, > +and FIT image instead of ``initramfs``. Android bootloader expect gzipped > kernel s/expect/expects/ > +with appended dtb, so let's mimic linux to satisfy stock bootloader. > + > +Boards > +-- > + > +starqlte > + > + > +The starqltechn is a production board for Samsung S9 (SM-G9600) phone, > +based on the Qualcomm SDM845 SoC. > + > +This device is supported by the common qcom_defconfig. > + > +The DTB is called "sdm845-samsung-starqltechn.dtb" > + > +More information can be found on the `Samsung S9 page`_. > + > +dragonboard845c > +^^^ > + > +The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on > +the Qualcomm SDM845 SoC. > + > +This device is supported by the common qcom_defconfig > + > +The DTB is called "sdm845-db845c.dtb" > + > +More information can be found on the `DragonBoard 845c page`_. > + > +qcs404-evb > +^^ > + > +The QCS404 EvB is a Qualcomm Development Platform, based on the Qualcomm > QCS404 SoC. > + > +This device is supported by the common qcom_defconfig > + > +The DTB is called "qcs404-evb-4000.dtb" > + > +Building steps > +-- > + > +Steps: > + > +- Build u-boot > + > +As above:: > + > + ./tools/buildman/buildman -o .output qcom > + > +Or for db410c (and other boards not supported by the generic target):: > + > + make CROSS_COMPILE=aarch64-linux-gnu- O=.output > dragonboard410c_defconfig > + make O=.output -j$(nproc) > + > +- gzip u-boot:: > + > + gzip u-boot-nodtb.bin > + > +- Append dtb to gzipped u-boot:: > + > + cat u-boot-nodtb.bin.gz arch/arm/dts/your-board.dtb > > u-boot-nodtb.bin.gz-dtb > + > +- If you chose to build a FIT image, A ``qcom.its`` file can be found in > ``board/qualcomm/generic/`` s/chose/choose/ > + directory. It expects a folder as ``qcom_imgs/`` in the main directory > containing pre-built kernel, > + dts and ramdisk images. See ``qcom.its`` for full path to images:: > + > + mkimage -f qcom.its qcom.itb > + > +- Now we've got everything to build android boot image:: > + > + mkbootimg --kernel u-boot-nodtb.bin.gz-dtb --ramdisk db845c.itb \ > + --output boot.img --pagesize 4096 --base 0x8000 > + > +Or with no FIT image:: > + > + mkbootimg --kernel u-boot-nodtb.bin.gz-dtb \ > + --output boot.img --pagesize 4096 --base 0x8000 > + > +- Flash boot.img using fastboot and erase dtbo to avoid conflicts with our > DTB: > + > + .. code-block:: bash > + > + fastboot flash boot boot.img > + fastboot erase dtbo > + > +..
[PATCH] pylibfdt: Fix "invalid escape sequence '\w'" in setup.py
From: Florian Schmaus
Once u-boot's build system invokes
python3 scripts/dtc/pylibfdt/setup.py --quiet build_ext --inplace
it may fail with
scripts/dtc/pylibfdt/setup.py:40: SyntaxWarning: invalid escape sequence '\w'
RE_KEY_VALUE = re.compile('(?P\w+) *(?P[+])?= *(?P.*)$')
depending on the used Python version.
Explicitly mark the regex string as raw string to avoid the warning.
Signed-off-by: Florian Schmaus
---
scripts/dtc/pylibfdt/setup.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/dtc/pylibfdt/setup.py b/scripts/dtc/pylibfdt/setup.py
index 8baae08770ca..c6fe5a6a446f 100755
--- a/scripts/dtc/pylibfdt/setup.py
+++ b/scripts/dtc/pylibfdt/setup.py
@@ -37,7 +37,7 @@
long_description = fh.read()
# Decodes a Makefile assignment line into key and value (and plus for +=)
-RE_KEY_VALUE = re.compile('(?P\w+) *(?P[+])?= *(?P.*)$')
+RE_KEY_VALUE = re.compile(r'(?P\w+) *(?P[+])?= *(?P.*)$')
def get_top_builddir():
if '--top-builddir' in sys.argv:
Re: [PATCH v4 24/39] board: qcs404-evb: drop board code
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
>
> This board is entirely supported by the generic arch code and DTS. The
> board code used to handle turning on the vbus regulator, however this is
> now handled via DT.
>
> With this, the board specific defconfig is also no longer needed, so
> drop it as well.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> board/qualcomm/qcs404-evb/Makefile | 6
> board/qualcomm/qcs404-evb/qcs404-evb.c | 49 -
> configs/qcs404evb_defconfig| 56
> --
> 3 files changed, 111 deletions(-)
>
Glad to see qcs404 being supported by generic defconfig.
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/board/qualcomm/qcs404-evb/Makefile
> b/board/qualcomm/qcs404-evb/Makefile
> deleted file mode 100644
> index 4665827e0859..
> --- a/board/qualcomm/qcs404-evb/Makefile
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# (C) Copyright 2022 Sumit Garg
> -#
> -
> -obj-y += qcs404-evb.o
> diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c
> b/board/qualcomm/qcs404-evb/qcs404-evb.c
> deleted file mode 100644
> index 1a4b1f97a3ae..
> --- a/board/qualcomm/qcs404-evb/qcs404-evb.c
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Board init file for QCS404-EVB
> - *
> - * (C) Copyright 2022 Sumit Garg
> - */
> -
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -void qcom_board_init(void)
> -{
> - struct udevice *pmic_gpio;
> - struct gpio_desc usb_vbus_boost_pin;
> - int ret, node;
> -
> - ret = uclass_get_device_by_name(UCLASS_GPIO,
> - "pms405_gpios@c000",
> - _gpio);
> - if (ret < 0) {
> - printf("Failed to find pms405_gpios@c000 node.\n");
> - return;
> - }
> -
> - node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
> - "usb_vbus_boost_pin");
> - if (node < 0) {
> - printf("Failed to find usb_hub_reset_pm dt node.\n");
> - return;
> - }
> - ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
> -_vbus_boost_pin, 0);
> - if (ret < 0) {
> - printf("Failed to request usb_hub_reset_pm gpio.\n");
> - return;
> - }
> -
> - dm_gpio_set_dir_flags(_vbus_boost_pin,
> - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
> -}
> diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
> deleted file mode 100644
> index d85d193895b0..
> --- a/configs/qcs404evb_defconfig
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SYS_BOARD="qcs404-evb"
> -CONFIG_SKIP_LOWLEVEL_INIT=y
> -CONFIG_COUNTER_FREQUENCY=1900
> -CONFIG_POSITION_INDEPENDENT=y
> -CONFIG_ARCH_SNAPDRAGON=y
> -CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
> -CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
> -CONFIG_SYS_LOAD_ADDR=0x8000
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_BOOTDELAY=5
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
> -CONFIG_SAVE_PREV_BL_FDT_ADDR=y
> -CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
> -CONFIG_SYS_CBSIZE=512
> -# CONFIG_DISPLAY_CPUINFO is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_MAXARGS=64
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_GPT=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_PART=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_EXT4=y
> -CONFIG_CMD_EXT4_WRITE=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_FS_GENERIC=y
> -# CONFIG_NET is not set
> -CONFIG_CLK=y
> -CONFIG_CLK_QCOM_QCS404=y
> -CONFIG_MSM_GPIO=y
> -CONFIG_QCOM_PMIC_GPIO=y
> -CONFIG_MISC=y
> -CONFIG_MMC_HS400_SUPPORT=y
> -CONFIG_MMC_SDHCI=y
> -CONFIG_MMC_SDHCI_ADMA=y
> -CONFIG_MMC_SDHCI_MSM=y
> -CONFIG_PHY=y
> -CONFIG_PHY_QCOM_USB_HS_28NM=y
> -CONFIG_PHY_QCOM_USB_SS=y
> -CONFIG_PINCTRL=y
> -CONFIG_PINCTRL_QCOM_QCS404=y
> -CONFIG_DM_PMIC=y
> -CONFIG_PMIC_QCOM=y
> -CONFIG_MSM_SERIAL=y
> -CONFIG_SPMI_MSM=y
> -CONFIG_USB=y
> -CONFIG_USB_XHCI_HCD=y
> -CONFIG_USB_XHCI_DWC3=y
> -CONFIG_USB_DWC3=y
> -CONFIG_USB_DWC3_GENERIC=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_LMB_MAX_REGIONS=64
>
> --
> 2.43.1
>
Re: [PATCH v4 23/39] mach-snapdragon: carve out no-map regions
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
>
> On Qualcomm platforms, the TZ may already have certain memory regions
> under protection by the time U-Boot starts. There is a rare case on some
> platforms where the prefetcher might speculatively access one of these
> regions resulting in a board crash (TZ traps and then resets the board).
>
> We shouldn't be accessing these regions from within U-Boot anyway, so
> let's mark them all with PTE_TYPE_FAULT to prevent any speculative
> access and correctly trap in EL1 rather than EL3.
>
> This is quite costly with caches off (takes ~2 seconds on SDM845 vs 35ms
> with caches on). So to minimise the impact this is only enabled on
> QCS404 for now (where the issue is known to occur).
>
> In the future, we should try to find a more efficient way to handle
> this, perhaps by turning on the MMU in stages.
>
I suppose you forgot to update the commit message since we already
found more or less an efficient way.
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/mach-snapdragon/board.c | 162
> +--
> 1 file changed, 140 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm/mach-snapdragon/board.c
> b/arch/arm/mach-snapdragon/board.c
> index 5a859aabd5c4..f12f5791a136 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -25,6 +25,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -296,7 +297,7 @@ int board_late_init(void)
>
> static void build_mem_map(void)
> {
> - int i;
> + int i, j;
>
> /*
> * Ensure the peripheral block is sized to correctly cover the
> address range
> @@ -312,28 +313,23 @@ static void build_mem_map(void)
> PTE_BLOCK_NON_SHARE |
> PTE_BLOCK_PXN | PTE_BLOCK_UXN;
>
> - debug("Configured memory map:\n");
> - debug(" 0x%016llx - 0x%016llx: Peripheral block\n",
> - mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
> -
> - /*
> -* Now add memory map entries for each DRAM bank, ensuring we don't
> -* overwrite the list terminator
> -*/
> - for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 &&
> gd->bd->bi_dram[i].size; i++) {
> - if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
> - log_warning("Too many DRAM banks!\n");
> - break;
> - }
> - mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
> - mem_map[i + 1].virt = mem_map[i + 1].phys;
> - mem_map[i + 1].size = gd->bd->bi_dram[i].size;
> - mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -PTE_BLOCK_INNER_SHARE;
> -
> - debug(" 0x%016llx - 0x%016llx: DDR bank %d\n",
> - mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i +
> 1].size, i);
> + for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 &&
> gd->bd->bi_dram[j].size; i++, j++) {
> + mem_map[i].phys = gd->bd->bi_dram[j].start;
> + mem_map[i].virt = mem_map[i].phys;
> + mem_map[i].size = gd->bd->bi_dram[j].size;
> + mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
> + PTE_BLOCK_INNER_SHARE;
> }
> +
> + mem_map[i].phys = UINT64_MAX;
> + mem_map[i].size = 0;
> +
> +#ifdef DEBUG
> + debug("Configured memory map:\n");
> + for (i = 0; mem_map[i].size; i++)
> + debug(" 0x%016llx - 0x%016llx: entry %d\n",
> + mem_map[i].phys, mem_map[i].phys + mem_map[i].size, i);
> +#endif
> }
>
> u64 get_page_table_size(void)
> @@ -341,10 +337,132 @@ u64 get_page_table_size(void)
> return SZ_64K;
> }
>
> +static int fdt_cmp_res(const void *v1, const void *v2)
> +{
> + const struct fdt_resource *res1 = v1, *res2 = v2;
> +
> + return res1->start - res2->start;
> +}
> +
> +#define N_RESERVED_REGIONS 32
> +
> +/* Mark all no-map regions as PTE_TYPE_FAULT to prevent speculative access.
> + * On some platforms this is enough to trigger a security violation and trap
> + * to EL3.
> + */
> +static void carve_out_reserved_memory(void)
> +{
> + static struct fdt_resource res[N_RESERVED_REGIONS] = { 0 };
> + int parent, rmem, count, i = 0;
> + phys_addr_t start;
> + size_t size;
> +
> + /* Some reserved nodes must be carved out, as the cache-prefetcher
> may otherwise
> +* attempt to access them, causing a security exception.
> +*/
> + parent = fdt_path_offset(gd->fdt_blob, "/reserved-memory");
> + if (parent <= 0) {
> + log_err("No reserved memory regions found\n");
> + return;
> + }
> +
> + /* Collect the reserved memory regions */
> + fdt_for_each_subnode(rmem, gd->fdt_blob, parent) {
> + const fdt32_t *ptr;
> +
Re: [PATCH v4 22/39] mach-snapdragon: generate fdtfile automatically
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
>
> With just a few basic rules, we can generate the $fdtfile environment
> variable to match the format used in Linux. This uses the root
> compatible property inside u-boot, with specific handling for the
> Dragonboard845c which is a special case, and for the qrb robotics
> boards.
>
> This is known to work on supported platforms, and lets us avoid having a
> big lookup table.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/mach-snapdragon/board.c | 101
> +++
> 1 file changed, 101 insertions(+)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/mach-snapdragon/board.c
> b/arch/arm/mach-snapdragon/board.c
> index f445bed3af00..5a859aabd5c4 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -160,6 +160,106 @@ int board_init(void)
> return 0;
> }
>
> +/* Sets up the "board", and "soc" environment variables as well as
> constructing the devicetree
> + * path, with a few quirks to handle non-standard dtb filenames. This is not
> meant to be a
> + * comprehensive solution to automatically picking the DTB, but aims to be
> correct for the
> + * majority case. For most devices it should be possible to make this
> algorithm work by
> + * adjusting the root compatible property in the U-Boot DTS. Handling
> devices with multiple
> + * variants that are all supported by a single U-Boot image will require
> implementing device-
> + * specific detection.
> + */
> +static void configure_env(void)
> +{
> + const char *first_compat, *last_compat;
> + char *tmp;
> + char buf[32] = { 0 };
> + /*
> +* Most DTB filenames follow the scheme:
> qcom/-[vendor]-.dtb
> +* The vendor is skipped when it's a Qualcomm reference board, or the
> +* db845c.
> +*/
> + char dt_path[64] = { 0 };
> + int compat_count, ret;
> + ofnode root;
> +
> + root = ofnode_root();
> + /* This is almost always 2, but be explicit that we want the first
> and last compatibles
> +* not the first and second.
> +*/
> + compat_count = ofnode_read_string_count(root, "compatible");
> + if (compat_count < 2) {
> + log_warning("%s: only one root compatible bailing!\n",
> __func__);
> + return;
> + }
> +
> + /* The most specific device compatible (e.g. "thundercomm,db845c") */
> + ret = ofnode_read_string_index(root, "compatible", 0, _compat);
> + if (ret < 0) {
> + log_warning("Can't read first compatible\n");
> + return;
> + }
> +
> + /* The last compatible is always the SoC compatible */
> + ret = ofnode_read_string_index(root, "compatible", compat_count - 1,
> _compat);
> + if (ret < 0) {
> + log_warning("Can't read second compatible\n");
> + return;
> + }
> +
> + /* Copy the second compat (e.g. "qcom,sdm845") into buf */
> + strlcpy(buf, last_compat, sizeof(buf) - 1);
> + tmp = buf;
> +
> + /* strsep() is destructive, it replaces the comma with a \0 */
> + if (!strsep(, ",")) {
> + log_warning("second compatible '%s' has no ','\n", buf);
> + return;
> + }
> +
> + /* tmp now points to just the "sdm845" part of the string */
> + env_set("soc", tmp);
> +
> + /* Now figure out the "board" part from the first compatible */
> + memset(buf, 0, sizeof(buf));
> + strlcpy(buf, first_compat, sizeof(buf) - 1);
> + tmp = buf;
> +
> + /* The Qualcomm reference boards (RBx, HDK, etc) */
> + if (!strncmp("qcom", buf, strlen("qcom"))) {
> + /*
> +* They all have the first compatible as "qcom,-"
> +* (e.g. "qcom,qrb5165-rb5"). We extract just the part after
> +* the dash.
> +*/
> + if (!strsep(, "-")) {
> + log_warning("compatible '%s' has no '-'\n", buf);
> + return;
> + }
> + /* tmp is now "rb5" */
> + env_set("board", tmp);
> + } else {
> + if (!strsep(, ",")) {
> + log_warning("compatible '%s' has no ','\n", buf);
> + return;
> + }
> + /* for thundercomm we just want the bit after the comma (e.g.
> "db845c"),
> +* for all other boards we replace the comma with a '-' and
> take both
> +* (e.g. "oneplus-enchilada")
> +*/
> + if (!strncmp("thundercomm", buf, strlen("thundercomm"))) {
> + env_set("board", tmp);
> + } else {
> + *(tmp - 1) = '-';
> + env_set("board", buf);
> + }
> + }
> +
> +
[PATCH 7/7] verdin-imx8mp_defconfig: Enable PCIe/NVMe support
Also, enable reset driver which is a prerequisite for PCIe support. Signed-off-by: Sumit Garg --- configs/verdin-imx8mp_defconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 22b8a334dfa..d8bd644322b 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -185,3 +185,12 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_IMX_WATCHDOG=y CONFIG_HEXDUMP=y +CONFIG_DM_RESET=y +CONFIG_RESET_IMX=y +CONFIG_PCI=y +CONFIG_PCIE_DW_IMX8=y +CONFIG_PHY_IMX8M_PCIE=y +CONFIG_CMD_PCI=y +CONFIG_NVME=y +CONFIG_NVME_PCI=y +CONFIG_CMD_NVME=y -- 2.34.1
[PATCH 1/7] clk: imx8mp: Add support for PCIe clocks
Pre-requisite to enable PCIe support on iMX8MP SoC.
Signed-off-by: Sumit Garg
---
drivers/clk/imx/clk-imx8mp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a21a3ce34bb..7dfc829df2c 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -62,6 +62,10 @@ static const char *imx8mp_dram_apb_sels[] =
{"clock-osc-24m", "sys_pll2_200m", "
"sys_pll1_160m", "sys_pll1_800m",
"sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out",
};
+static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m",
"sys_pll2_200m", "sys_pll2_50m",
+ "sys_pll3_out",
"sys_pll2_100m", "sys_pll1_80m",
+ "sys_pll1_160m",
"sys_pll1_200m", };
+
static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out",
"video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
@@ -272,6 +276,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt",
imx8mp_dram_alt_sels, base + 0xa000));
clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb",
imx8mp_dram_apb_sels, base + 0xa080));
+ clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux",
imx8mp_pcie_aux_sels, base + 0xa400));
clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels,
base + 0xa480));
clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels,
base + 0xa500));
clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos",
imx8mp_enet_qos_sels, base + 0xa880));
@@ -322,6 +327,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2",
base + 0x4180, 0));
clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3",
base + 0x4190, 0));
clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4",
base + 0x41a0, 0));
+ clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux",
base + 0x4250, 0));
clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1",
base + 0x4280, 0));
clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2",
base + 0x4290, 0));
clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3",
base + 0x42a0, 0));
--
2.34.1
[PATCH 5/7] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Signed-off-by: Sumit Garg
---
drivers/phy/Kconfig | 9 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-imx8m-pcie.c | 246 +++
3 files changed, 256 insertions(+)
create mode 100644 drivers/phy/phy-imx8m-pcie.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 60138beca49..110ec8f5008 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -284,6 +284,15 @@ config PHY_IMX8MQ_USB
help
Support the USB3.0 PHY in NXP i.MX8MQ or i.MX8MP SoC
+config PHY_IMX8M_PCIE
+ bool "NXP i.MX8MM/i.MX8MP PCIe PHY Driver"
+ depends on PHY
+ depends on IMX8MM || IMX8MP
+ help
+ Support the PCIe PHY in NXP i.MX8MM or i.MX8MP SoC
+
+ This PHY is found on i.MX8M devices supporting PCIe.
+
config PHY_XILINX_ZYNQMP
tristate "Xilinx ZynqMP PHY driver"
depends on PHY && ARCH_ZYNQMP
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 2e8723186c0..7a2b764492b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
+obj-$(CONFIG_PHY_IMX8M_PCIE) += phy-imx8m-pcie.o
obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
obj-y += cadence/
obj-y += ti/
diff --git a/drivers/phy/phy-imx8m-pcie.c b/drivers/phy/phy-imx8m-pcie.c
new file mode 100644
index 000..d1ad42ff339
--- /dev/null
+++ b/drivers/phy/phy-imx8m-pcie.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Linaro Ltd.
+ *
+ * Derived from Linux counterpart driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define IMX8MM_PCIE_PHY_CMN_REG061 0x184
+#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0)
+#define IMX8MM_PCIE_PHY_CMN_REG062 0x188
+#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3)
+#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C
+#define AUX_PLL_REFCLK_SEL_SYS_PLLGENMASK(7, 6)
+#define IMX8MM_PCIE_PHY_CMN_REG064 0x190
+#define ANA_AUX_RX_TX_SEL_TX BIT(7)
+#define ANA_AUX_RX_TERM_GND_ENBIT(3)
+#define ANA_AUX_TX_TERM BIT(2)
+#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
+#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
+#define ANA_AUX_TX_LVLGENMASK(3, 0)
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
+#define PCIE_PHY_TRSV_REG5 0x414
+#define PCIE_PHY_TRSV_REG6 0x418
+
+#define IMX8MM_GPR_PCIE_REF_CLK_SELGENMASK(25, 24)
+#define IMX8MM_GPR_PCIE_REF_CLK_PLLFIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL,
0x3)
+#define IMX8MM_GPR_PCIE_REF_CLK_EXTFIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL,
0x2)
+#define IMX8MM_GPR_PCIE_AUX_EN BIT(19)
+#define IMX8MM_GPR_PCIE_CMN_RSTBIT(18)
+#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17)
+#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
+#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDEBIT(9)
+
+#define IOMUXC_GPR14_OFFSET0x38
+
+enum imx8_pcie_phy_type {
+ IMX8MM,
+ IMX8MP,
+};
+
+struct imx8_pcie_phy_drvdata {
+ const char*gpr;
+ enumimx8_pcie_phy_type variant;
+};
+
+struct imx8_pcie_phy {
+ ulong base;
+ struct regmap *iomuxc_gpr;
+ struct reset_ctlperst;
+ struct reset_ctlreset;
+ u32 refclk_pad_mode;
+ u32 tx_deemph_gen1;
+ u32 tx_deemph_gen2;
+ boolclkreq_unused;
+ const struct imx8_pcie_phy_drvdata *drvdata;
+};
+
+static int imx8_pcie_phy_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, pad_mode;
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev);
+
+ pad_mode = imx8_phy->refclk_pad_mode;
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ reset_assert(_phy->reset);
+
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_phy->base + PCIE_PHY_TRSV_REG5);
+ if (imx8_phy->tx_deemph_gen2)
+ writel(imx8_phy->tx_deemph_gen2,
+ imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ break;
+ case IMX8MP: /* Do nothing. */
+ break;
+ }
+
+ if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
+ pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
+ /* Configure the pad as input */
+
[PATCH 2/7] reset: imx: Add support for i.MX8MP reset controller
Pre-requisite to enable PCIe support on iMX8MP SoC.
Signed-off-by: Sumit Garg
---
drivers/reset/reset-imx7.c | 114 +
1 file changed, 114 insertions(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index eaef2cc2cdf..c1de84dea8b 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -252,6 +253,115 @@ static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
return 0;
}
+enum imx8mp_src_registers {
+ SRC_SUPERMIX_RCR= 0x0018,
+ SRC_AUDIOMIX_RCR= 0x001c,
+ SRC_MLMIX_RCR = 0x0028,
+ SRC_GPU2D_RCR = 0x0038,
+ SRC_GPU3D_RCR = 0x003c,
+ SRC_VPU_G1_RCR = 0x0048,
+ SRC_VPU_G2_RCR = 0x004c,
+ SRC_VPUVC8KE_RCR= 0x0050,
+ SRC_NOC_RCR = 0x0054,
+};
+
+static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
+ [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
+ [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
+ [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
+ [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
+ [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
+ [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
+ [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
+ [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
+ [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
+ [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
+ [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
+ [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
+ [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
+ [IMX8MP_RESET_A53_SOC_DBG_RESET]= { SRC_A53RCR0, BIT(20) },
+ [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
+ [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
+ [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
+ [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
+ [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
+ [IMX8MP_RESET_PCIEPHY_PERST]= { SRC_PCIEPHY_RCR, BIT(3) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_EN]= { SRC_PCIEPHY_RCR, BIT(6) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
+ [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
+ [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU_RESET]= { SRC_GPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_RESET]= { SRC_VPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
+ [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
+ [IMX8MP_RESET_NOC_RESET]= { SRC_NOC_RCR, BIT(0) },
+};
+
+static int imx7_reset_assert_imx8mp(struct reset_ctl *rst)
+{
+ struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ const struct imx7_src_signal *sig = imx8mp_src_signals;
+ u32 val;
+
+ if (rst->id >= IMX8MP_RESET_NUM)
+ return -EINVAL;
+
+ val = readl(priv->base + sig[rst->id].offset);
+ switch (rst->id) {
+ case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+ case IMX8MP_RESET_PCIEPHY_PERST:
+ val &= ~sig[rst->id].bit;
+ break;
+ default:
+ val |= sig[rst->id].bit;
+ break;
+ }
+ writel(val, priv->base + sig[rst->id].offset);
+
+ return 0;
+}
+
+static int imx7_reset_deassert_imx8mp(struct reset_ctl *rst)
+{
+ struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ const struct imx7_src_signal *sig = imx8mp_src_signals;
+ u32 val;
+
+ if (rst->id >= IMX8MP_RESET_NUM)
+ return -EINVAL;
+
+ if (rst->id == IMX8MP_RESET_PCIEPHY) {
+
[PATCH 0/7] imx8mp: Enable PCIe/NVMe support
pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
rather tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Patch #1: Adds PCIe clocks support.
Patch #2: Adds i.MX8MP reset controller support.
Patch #3: Extend i.MX8MP power domain driver with PCIe support
Patch #4: Expose high performance PLL clock required for PCIe PHY
on verdin board.
Patch #5: Adds standalone PCIe PHY support for i.MX8MP SoC.
Patch #6: Adds DW PCIe controller support for iMX8MP SoC.
Patch #7: Enable PCIe/NVMe support for verdin board.
Testing with this patch-set included:
Verdin iMX8MP # pci enum
PCIE-0: Link up (Gen1-x1, Bus0)
Verdin iMX8MP #
Verdin iMX8MP # nvme scan
Verdin iMX8MP #
Verdin iMX8MP # nvme info
Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000720
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Verdin iMX8MP #
Verdin iMX8MP # load nvme 0 $loadaddr
Sumit Garg (7):
clk: imx8mp: Add support for PCIe clocks
reset: imx: Add support for i.MX8MP reset controller
imx8mp: power-domain: Add PCIe support
imx8mp: power-domain: Expose high performance PLL clock
phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
pci: Add DW PCIe controller support for iMX8MP SoC
verdin-imx8mp_defconfig: Enable PCIe/NVMe support
configs/verdin-imx8mp_defconfig | 9 +
drivers/clk/imx/clk-imx8mp.c | 6 +
drivers/pci/Kconfig | 8 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_imx8.c| 348 ++
drivers/phy/Kconfig | 9 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-imx8m-pcie.c | 246 ++
drivers/power/domain/imx8mp-hsiomix.c | 121 -
drivers/reset/reset-imx7.c| 114 +
10 files changed, 859 insertions(+), 4 deletions(-)
create mode 100644 drivers/pci/pcie_dw_imx8.c
create mode 100644 drivers/phy/phy-imx8m-pcie.c
--
2.34.1
[PATCH 6/7] pci: Add DW PCIe controller support for iMX8MP SoC
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Signed-off-by: Sumit Garg
---
drivers/pci/Kconfig| 8 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_imx8.c | 348 +
3 files changed, 357 insertions(+)
create mode 100644 drivers/pci/pcie_dw_imx8.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 463ec47eb92..b7c7922b091 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -413,4 +413,12 @@ config PCIE_STARFIVE_JH7110
Say Y here if you want to enable PLDA XpressRich PCIe controller
support on StarFive JH7110 SoC.
+config PCIE_DW_IMX8
+ bool "i.MX8 PCIe support"
+ depends on ARCH_IMX8M
+ select PCIE_DW_COMMON
+ help
+ Say Y here if you want to enable DW PCIe controller support on
+ iMX8 SoCs.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 72ef8b4bc77..cddbb902095 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
+obj-$(CONFIG_PCIE_DW_IMX8) += pcie_dw_imx8.o
diff --git a/drivers/pci/pcie_dw_imx8.c b/drivers/pci/pcie_dw_imx8.c
new file mode 100644
index 000..b9921644765
--- /dev/null
+++ b/drivers/pci/pcie_dw_imx8.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Linaro Ltd.
+ *
+ * Author: Sumit Garg
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie_dw_common.h"
+
+#define PCIE_LINK_CAPABILITY 0x7c
+#define TARGET_LINK_SPEED_MASK 0xf
+#define LINK_SPEED_GEN_1 0x1
+#define LINK_SPEED_GEN_2 0x2
+#define LINK_SPEED_GEN_3 0x3
+
+#define PCIE_MISC_CONTROL_1_OFF0x8bc
+#define PCIE_DBI_RO_WR_EN BIT(0)
+
+#define PCIE_PORT_DEBUG0 0x728
+#define PCIE_PORT_DEBUG1 0x72c
+#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
+#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
+
+#define PCIE_LINK_UP_TIMEOUT_MS100
+
+#define IOMUXC_GPR14_OFFSET0x38
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDEBIT(11)
+
+struct pcie_dw_imx8 {
+ /* Must be first member of the struct */
+ struct pcie_dw dw;
+ struct regmap *iomuxc_gpr;
+ struct clk pcie;
+ struct clk pcie_bus;
+ struct clk pcie_aux;
+ struct gpio_descreset_gpio;
+ struct reset_ctlapps_reset;
+ struct phy phy;
+};
+
+static void pcie_dw_configure(struct pcie_dw_imx8 *priv, u32 cap_speed)
+{
+ u32 val;
+
+ dw_pcie_dbi_write_enable(>dw, true);
+
+ val = readl(priv->dw.dbi_base + PCIE_LINK_CAPABILITY);
+ val &= ~TARGET_LINK_SPEED_MASK;
+ val |= cap_speed;
+ writel(val, priv->dw.dbi_base + PCIE_LINK_CAPABILITY);
+
+ dw_pcie_dbi_write_enable(>dw, false);
+}
+
+static void imx8_pcie_ltssm_enable(struct pcie_dw_imx8 *priv)
+{
+ reset_deassert(>apps_reset);
+}
+
+static void imx8_pcie_ltssm_disable(struct pcie_dw_imx8 *priv)
+{
+ reset_assert(>apps_reset);
+}
+
+static int is_link_up(struct pcie_dw_imx8 *priv)
+{
+ u32 val;
+
+ val = readl(priv->dw.dbi_base + PCIE_PORT_DEBUG1);
+
+ return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
+ (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
+}
+
+static int wait_link_up(struct pcie_dw_imx8 *priv)
+{
+ unsigned long timeout;
+
+ timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
+ while (!is_link_up(priv)) {
+ if (get_timer(0) > timeout)
+ return 0;
+ mdelay(10);
+ };
+
+ return 1;
+}
+
+static int pcie_link_up(struct pcie_dw_imx8 *priv, u32 cap_speed)
+{
+ if (is_link_up(priv)) {
+ printf("PCI Link already up before configuration!\n");
+ return 1;
+ }
+
+ /* DW pre link configurations */
+
[PATCH 3/7] imx8mp: power-domain: Add PCIe support
Pre-requisite to enable PCIe support on iMX8MP SoC.
Signed-off-by: Sumit Garg
---
drivers/power/domain/imx8mp-hsiomix.c | 50 +--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/power/domain/imx8mp-hsiomix.c
b/drivers/power/domain/imx8mp-hsiomix.c
index e2d772c5ec7..62145e0261b 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -16,14 +16,19 @@
#define GPR_REG0 0x0
#define PCIE_CLOCK_MODULE_EN BIT(0)
#define USB_CLOCK_MODULE_EN BIT(1)
+#define PCIE_PHY_APB_RST BIT(4)
+#define PCIE_PHY_INIT_RST BIT(5)
struct imx8mp_hsiomix_priv {
void __iomem *base;
struct clk clk_usb;
+ struct clk clk_pcie;
struct power_domain pd_bus;
struct power_domain pd_usb;
+ struct power_domain pd_pcie;
struct power_domain pd_usb_phy1;
struct power_domain pd_usb_phy2;
+ struct power_domain pd_pcie_phy;
};
static int imx8mp_hsiomix_on(struct power_domain *power_domain)
@@ -43,6 +48,10 @@ static int imx8mp_hsiomix_on(struct power_domain
*power_domain)
domain = >pd_usb_phy1;
} else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) {
domain = >pd_usb_phy2;
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE) {
+ domain = >pd_pcie;
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY) {
+ domain = >pd_pcie_phy;
} else {
ret = -EINVAL;
goto err_pd;
@@ -54,14 +63,25 @@ static int imx8mp_hsiomix_on(struct power_domain
*power_domain)
ret = clk_enable(>clk_usb);
if (ret)
- goto err_clk;
+ goto err_clk_usb;
+
+ ret = clk_enable(>clk_pcie);
+ if (ret)
+ goto err_clk_pcie;
if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE)
+ setbits_le32(priv->base + GPR_REG0, PCIE_CLOCK_MODULE_EN);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY)
+ setbits_le32(priv->base + GPR_REG0, PCIE_PHY_APB_RST |
+ PCIE_PHY_INIT_RST);
return 0;
-err_clk:
+err_clk_pcie:
+ clk_disable(>clk_usb);
+err_clk_usb:
power_domain_off(domain);
err_pd:
power_domain_off(>pd_bus);
@@ -75,8 +95,14 @@ static int imx8mp_hsiomix_off(struct power_domain
*power_domain)
if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE)
+ clrbits_le32(priv->base + GPR_REG0, PCIE_CLOCK_MODULE_EN);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY)
+ clrbits_le32(priv->base + GPR_REG0, PCIE_PHY_APB_RST |
+ PCIE_PHY_INIT_RST);
clk_disable(>clk_usb);
+ clk_disable(>clk_pcie);
if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
power_domain_off(>pd_usb);
@@ -84,6 +110,10 @@ static int imx8mp_hsiomix_off(struct power_domain
*power_domain)
power_domain_off(>pd_usb_phy1);
else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2)
power_domain_off(>pd_usb_phy2);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE)
+ power_domain_off(>pd_usb_phy2);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY)
+ power_domain_off(>pd_usb_phy2);
power_domain_off(>pd_bus);
@@ -109,6 +139,10 @@ static int imx8mp_hsiomix_probe(struct udevice *dev)
if (ret < 0)
return ret;
+ ret = clk_get_by_name(dev, "pcie", >clk_pcie);
+ if (ret < 0)
+ return ret;
+
ret = power_domain_get_by_name(dev, >pd_bus, "bus");
if (ret < 0)
return ret;
@@ -125,8 +159,20 @@ static int imx8mp_hsiomix_probe(struct udevice *dev)
if (ret < 0)
goto err_pd_usb_phy2;
+ ret = power_domain_get_by_name(dev, >pd_pcie, "pcie");
+ if (ret < 0)
+ goto err_pd_pcie;
+
+ ret = power_domain_get_by_name(dev, >pd_pcie_phy, "pcie-phy");
+ if (ret < 0)
+ goto err_pd_pcie_phy;
+
return 0;
+err_pd_pcie_phy:
+ power_domain_free(>pd_pcie);
+err_pd_pcie:
+ power_domain_free(>pd_usb_phy2);
err_pd_usb_phy2:
power_domain_free(>pd_usb_phy1);
err_pd_usb_phy1:
--
2.34.1
[PATCH 4/7] imx8mp: power-domain: Expose high performance PLL clock
PCIe PHY can use it when there is no external refclock provided.
Signed-off-by: Sumit Garg
---
drivers/power/domain/imx8mp-hsiomix.c | 79 +--
1 file changed, 73 insertions(+), 6 deletions(-)
diff --git a/drivers/power/domain/imx8mp-hsiomix.c
b/drivers/power/domain/imx8mp-hsiomix.c
index 62145e0261b..4cefe642724 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -9,6 +9,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -18,6 +20,15 @@
#define USB_CLOCK_MODULE_EN BIT(1)
#define PCIE_PHY_APB_RST BIT(4)
#define PCIE_PHY_INIT_RST BIT(5)
+#define GPR_REG1 0x4
+#define PLL_LOCK BIT(13)
+#define GPR_REG2 0x8
+#define P_PLL_MASKGENMASK(5, 0)
+#define M_PLL_MASKGENMASK(15, 6)
+#define S_PLL_MASKGENMASK(18, 16)
+#define GPR_REG3 0xc
+#define PLL_CKE BIT(17)
+#define PLL_RST BIT(31)
struct imx8mp_hsiomix_priv {
void __iomem *base;
@@ -31,6 +42,53 @@ struct imx8mp_hsiomix_priv {
struct power_domain pd_pcie_phy;
};
+static int hsio_pll_enable(struct udevice *dev)
+{
+ struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
+ unsigned long start;
+ u32 val;
+
+ /* Setup HSIO PLL */
+ val = readl(priv->base + GPR_REG2);
+ val &= ~(P_PLL_MASK | M_PLL_MASK | S_PLL_MASK);
+ val |= (FIELD_PREP(P_PLL_MASK, 12) | FIELD_PREP(M_PLL_MASK, 800) |
+ FIELD_PREP(S_PLL_MASK, 4));
+ writel(val, priv->base + GPR_REG2);
+
+ /* de-assert PLL reset */
+ setbits_le32(priv->base + GPR_REG3, PLL_RST);
+
+ /* enable PLL */
+ setbits_le32(priv->base + GPR_REG3, PLL_CKE);
+
+ /* Check if PLL is locked */
+ start = get_timer(0);
+ for (;;) {
+ if (readl(priv->base + GPR_REG1) & PLL_LOCK)
+ break;
+
+ if (get_timer(start) > 100) {
+ dev_err(dev, "failed to lock HSIO PLL\n");
+ return -ETIMEDOUT;
+ }
+
+ udelay(10);
+ }
+
+ return 0;
+}
+
+static void hsio_pll_disable(struct udevice *dev)
+{
+ struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
+
+ /* de-assert PLL reset */
+ clrbits_le32(priv->base + GPR_REG3, PLL_RST);
+
+ /* enable PLL */
+ clrbits_le32(priv->base + GPR_REG3, PLL_CKE);
+}
+
static int imx8mp_hsiomix_on(struct power_domain *power_domain)
{
struct udevice *dev = power_domain->dev;
@@ -69,16 +127,23 @@ static int imx8mp_hsiomix_on(struct power_domain
*power_domain)
if (ret)
goto err_clk_pcie;
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
+ if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) {
setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE)
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE) {
setbits_le32(priv->base + GPR_REG0, PCIE_CLOCK_MODULE_EN);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY)
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY) {
setbits_le32(priv->base + GPR_REG0, PCIE_PHY_APB_RST |
PCIE_PHY_INIT_RST);
+ ret = hsio_pll_enable(dev);
+ if (ret)
+ goto err_hsio_pll;
+ }
+
return 0;
+err_hsio_pll:
+ clk_disable(>clk_pcie);
err_clk_pcie:
clk_disable(>clk_usb);
err_clk_usb:
@@ -93,13 +158,15 @@ static int imx8mp_hsiomix_off(struct power_domain
*power_domain)
struct udevice *dev = power_domain->dev;
struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
+ if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) {
clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE)
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE) {
clrbits_le32(priv->base + GPR_REG0, PCIE_CLOCK_MODULE_EN);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY)
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_PCIE_PHY) {
clrbits_le32(priv->base + GPR_REG0, PCIE_PHY_APB_RST |
PCIE_PHY_INIT_RST);
+ hsio_pll_disable(dev);
+ }
clk_disable(>clk_usb);
clk_disable(>clk_pcie);
--
2.34.1
Re: [PATCH v4 21/39] mach-snapdragon: dynamic load addresses
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
>
> Heavily inspired by Apple board code. Use the LMB allocator to configure
> load addresses at runtime, and implement a lookup table for selecting a
> devicetree.
>
> As some Qualcomm RBx boards have different RAM capacities and base
> addresses, it isn't possible to hardcode these regions.
>
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/mach-snapdragon/board.c | 34
>
> board/qualcomm/dragonboard410c/dragonboard410c.c | 2 +-
> 3 files changed, 36 insertions(+), 1 deletion(-)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 672577d0ddcc..0dba77f86b49 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1095,6 +1095,7 @@ config ARCH_SNAPDRAGON
> select OF_SEPARATE
> select SMEM
> select SPMI
> + select BOARD_LATE_INIT
> select OF_BOARD
> select SAVE_PREV_BL_FDT_ADDR
> select LINUX_KERNEL_IMAGE_HEADER
> diff --git a/arch/arm/mach-snapdragon/board.c
> b/arch/arm/mach-snapdragon/board.c
> index a1867852bcca..f445bed3af00 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -22,6 +22,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -159,6 +160,39 @@ int board_init(void)
> return 0;
> }
>
> +void __weak qcom_late_init(void)
> +{
> +}
> +
> +#define KERNEL_COMP_SIZE SZ_64M
> +
> +#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M)
> +
> +/* Stolen from arch/arm/mach-apple/board.c */
> +int board_late_init(void)
> +{
> + struct lmb lmb;
> + u32 status = 0;
> +
> + lmb_init_and_reserve(, gd->bd, (void *)gd->fdt_blob);
> +
> + /* We need to be fairly conservative here as we support boards with
> just 1G of TOTAL RAM */
> + status |= env_set_hex("kernel_addr_r", addr_alloc(, SZ_128M));
> + status |= env_set_hex("ramdisk_addr_r", addr_alloc(, SZ_128M));
> + status |= env_set_hex("kernel_comp_addr_r", addr_alloc(,
> KERNEL_COMP_SIZE));
> + status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
> + status |= env_set_hex("scriptaddr", addr_alloc(, SZ_4M));
> + status |= env_set_hex("pxefile_addr_r", addr_alloc(, SZ_4M));
> + status |= env_set_hex("fdt_addr_r", addr_alloc(, SZ_2M));
> +
> + if (status)
> + log_warning("%s: Failed to set run time variables\n",
> __func__);
> +
> + qcom_late_init();
> +
> + return 0;
> +}
> +
> static void build_mem_map(void)
> {
> int i;
> diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c
> b/board/qualcomm/dragonboard410c/dragonboard410c.c
> index 0136cc2237de..fbbfc0e65e24 100644
> --- a/board/qualcomm/dragonboard410c/dragonboard410c.c
> +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
> @@ -88,7 +88,7 @@ int misc_init_r(void)
> return 0;
> }
>
> -int board_late_init(void)
> +int qcom_late_init(void)
> {
> char serial[16];
>
>
> --
> 2.43.1
>
Re: [PATCH v4 20/39] mach-snapdragon: generalise board support
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote: > > Historically, Qualcomm boards have relied on heavy hardcoding in U-Boot, > in many cases to the specific SoC but also to the board itself (e.g. > memory map). This has been largely resolved by modernising the Qualcomm > drivers in U-Boot, however the board code still largely follows this > model. > > This patch removes the board specific memory maps and duplicated board > init code, replacing it with generic init code. > > The memory map is now built at runtime based on data read from DT, this > allows for the memory map to be provided without having to recompile > U-Boot. Support is also added for booting with appended DTBs, so that > the first-stage bootloader can populate the memory map for us. > > The sdm845 specific init code is dropped entirely, it set an environment > variable depending on if a button was pressed, but this variable wasn't > used in U-Boot, and could be written to use the button command instead. > > The KASLR detection is also dropped as with appended dtb, the kaslr seed > can be read directly from the DTB passed to U-Boot. > > A new qcom_defconfig is added, with the aim of providing a generic > U-Boot configuration that will work on as many Qualcomm boards as > possible. It replaces the defconfig files for the Dragonboard 845c, > Galaxy S9, and QCS404 EVB. For now the db410c and 820c are excluded as > they still have some board code left. > > Similarly, the config headers for db845c, starqltechn, and qcs404-evb > are replaced by a single qcom header. > > The previously db410c-specific board_usb_init() function is made to be > generic and is added to mach-snapdragon. While we lack proper modelling > for USB configuration, using a well-known named pinctrl state is a > reasonably generic middleground, and works using upstream DT. This > function will do nothing unless the USB node has a pinctrl state named > "device", in which case it will be set when entering USB peripheral > mode. > > Reviewed-by: Neil Armstrong > Signed-off-by: Caleb Connolly > --- > arch/arm/Kconfig | 3 + > arch/arm/dts/Makefile| 9 +- > arch/arm/mach-snapdragon/Kconfig | 96 ++ > arch/arm/mach-snapdragon/Makefile| 6 +- > arch/arm/mach-snapdragon/board.c | 215 > +++ > arch/arm/mach-snapdragon/init_sdm845.c | 73 > arch/arm/mach-snapdragon/sysmap-apq8016.c| 31 > arch/arm/mach-snapdragon/sysmap-apq8096.c| 31 > arch/arm/mach-snapdragon/sysmap-qcs404.c | 43 - > arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 > board/qualcomm/dragonboard410c/Kconfig | 15 -- > board/qualcomm/dragonboard410c/dragonboard410c.c | 41 - > board/qualcomm/dragonboard820c/Kconfig | 15 -- > board/qualcomm/dragonboard820c/dragonboard820c.c | 39 +--- > board/qualcomm/dragonboard845c/Kconfig | 12 -- > board/qualcomm/qcs404-evb/Kconfig| 15 -- > board/qualcomm/qcs404-evb/qcs404-evb.c | 21 +-- > configs/dragonboard410c_defconfig| 6 +- > configs/dragonboard820c_defconfig| 6 +- > configs/dragonboard845c_defconfig| 29 --- > configs/qcom_defconfig | 67 +++ > configs/qcs404evb_defconfig | 5 +- > configs/starqltechn_defconfig| 41 - > include/configs/dragonboard845c.h| 20 --- > include/configs/qcom.h | 21 +++ > include/configs/qcs404-evb.h | 20 --- > include/configs/sdm845.h | 26 --- > 27 files changed, 345 insertions(+), 592 deletions(-) > Reviewed-by: Sumit Garg -Sumit > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 6b072be24634..672577d0ddcc 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1095,6 +1095,9 @@ config ARCH_SNAPDRAGON > select OF_SEPARATE > select SMEM > select SPMI > + select OF_BOARD > + select SAVE_PREV_BL_FDT_ADDR > + select LINUX_KERNEL_IMAGE_HEADER > imply CMD_DM > > config ARCH_SOCFPGA > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index ce10d3dbb07d..751035a577f6 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -631,10 +631,11 @@ dtb-$(CONFIG_TARGET_SL28) += > fsl-ls1028a-kontron-sl28.dtb \ > > dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb > > -dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb > -dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb > -dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb > -dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb > +dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \ > + dragonboard820c.dtb \ > + dragonboard845c.dtb \ > + starqltechn.dtb \ > +
Re: [PATCH] video: simplefb: modernise DT parsing
On Fri, Feb 16, 2024 at 06:38:06PM +, Caleb Connolly wrote:
> @@ -41,17 +41,25 @@ static int simple_video_probe(struct udevice *dev)
>
> debug("%s: Query resolution...\n", __func__);
>
> - uc_priv->xsize = fdtdec_get_uint(blob, node, "width", 0);
> - uc_priv->ysize = fdtdec_get_uint(blob, node, "height", 0);
> - uc_priv->rot = fdtdec_get_uint(blob, node, "rot", 0);
> - if (uc_priv->rot > 3) {
> - log_debug("%s: invalid rot\n", __func__);
> - return log_msg_ret("rot", -EINVAL);
> + ret = ofnode_read_u32(node, "width", );
> + ret = ret ?: ofnode_read_u32(node, "height", );
> + if (ret || !width || !height) {
> + log_err("%s: invalid width or height: %d\n", __func__, ret);
> + return ret;
This should be something like:
return ret ?: -EINVAL;
Perhaps print the width and height in the error message as well.
regards,
dan carpenter
Re: [PATCH v4 19/39] board: dragonboard820c: use LINUX_KERNEL_IMAGE_HEADER
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
>
> db820c predated support for prepending the kernel image header
> automatically, drop it's custom linker script and head.S in favour of
> this generic support.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/mach-snapdragon/Kconfig | 1 +
> board/qualcomm/dragonboard820c/Makefile | 1 -
> board/qualcomm/dragonboard820c/head.S | 33 -
> board/qualcomm/dragonboard820c/u-boot.lds | 111
> --
> 4 files changed, 1 insertion(+), 145 deletions(-)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/mach-snapdragon/Kconfig
> b/arch/arm/mach-snapdragon/Kconfig
> index ad6671081910..f897c393464f 100644
> --- a/arch/arm/mach-snapdragon/Kconfig
> +++ b/arch/arm/mach-snapdragon/Kconfig
> @@ -45,6 +45,7 @@ config TARGET_DRAGONBOARD410C
>
> config TARGET_DRAGONBOARD820C
> bool "96Boards Dragonboard 820C"
> + select LINUX_KERNEL_IMAGE_HEADER
> imply CLK_QCOM_APQ8096
> imply PINCTRL_QCOM_APQ8096
> imply BUTTON_QCOM_PMIC
> diff --git a/board/qualcomm/dragonboard820c/Makefile
> b/board/qualcomm/dragonboard820c/Makefile
> index 643311f5b3ba..2ae6d16364aa 100644
> --- a/board/qualcomm/dragonboard820c/Makefile
> +++ b/board/qualcomm/dragonboard820c/Makefile
> @@ -3,4 +3,3 @@
> # (C) Copyright 2017 Jorge Ramirez-Ortiz
>
> obj-y := dragonboard820c.o
> -extra-y += head.o
> diff --git a/board/qualcomm/dragonboard820c/head.S
> b/board/qualcomm/dragonboard820c/head.S
> deleted file mode 100644
> index b052a858fd32..
> --- a/board/qualcomm/dragonboard820c/head.S
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * ARM64 header for proper chain-loading with Little Kernel.
> - *
> - * Little Kernel shipped with Dragonboard820C boots standard Linux images for
> - * ARM64. This file adds header that is required to boot U-Boot properly.
> - *
> - * For details see:
> - * https://www.kernel.org/doc/Documentation/arm64/booting.txt
> - *
> - * (C) Copyright 2015 Mateusz Kulikowski
> - */
> -
> -#include
> -
> -/*
> - * per document in linux/Doc/arm64/booting.text
> - */
> -.global _arm64_header
> -_arm64_header:
> - b _start
> - .word 0
> - .quad CONFIG_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
> - .quad 0/* Effective size of kernel image, little-endian */
> - .quad 0/* kernel flags, little-endian */
> - .quad 0/* reserved */
> - .quad 0/* reserved */
> - .quad 0/* reserved */
> - .byte 0x41 /* Magic number, "ARM\x64" */
> - .byte 0x52
> - .byte 0x4d
> - .byte 0x64
> - .word 0/* reserved (used for PE COFF offset) */
> diff --git a/board/qualcomm/dragonboard820c/u-boot.lds
> b/board/qualcomm/dragonboard820c/u-boot.lds
> deleted file mode 100644
> index 5251b59fbe76..
> --- a/board/qualcomm/dragonboard820c/u-boot.lds
> +++ /dev/null
> @@ -1,111 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Override linker script for fastboot-readable images
> - *
> - * (C) Copyright 2015 Mateusz Kulikowski
> - *
> - * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
> - */
> -
> -OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64",
> "elf64-littleaarch64")
> -OUTPUT_ARCH(aarch64)
> -ENTRY(_arm64_header)
> -SECTIONS
> -{
> - . = 0x;
> -
> - . = ALIGN(8);
> - .text :
> - {
> - *(.__image_copy_start)
> - board/qualcomm/dragonboard820c/head.o (.text*)
> - CPUDIR/start.o (.text*)
> - }
> -
> - /* This needs to come before *(.text*) */
> - .efi_runtime : {
> -__efi_runtime_start = .;
> - *(.text.efi_runtime*)
> - *(.rodata.efi_runtime*)
> - *(.data.efi_runtime*)
> -__efi_runtime_stop = .;
> - }
> -
> - .text_rest :
> - {
> - *(.text*)
> - }
> -
> - . = ALIGN(8);
> - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
> -
> - . = ALIGN(8);
> - .data : {
> - *(.data*)
> - }
> -
> - . = ALIGN(8);
> -
> - . = .;
> -
> - . = ALIGN(8);
> - __u_boot_list : {
> - KEEP(*(SORT(__u_boot_list*)));
> - }
> -
> - . = ALIGN(8);
> -
> - .efi_runtime_rel : {
> -__efi_runtime_rel_start = .;
> - *(.rel*.efi_runtime)
> - *(.rel*.efi_runtime.*)
> -__efi_runtime_rel_stop = .;
> - }
> -
> - . = ALIGN(8);
> -
> - .image_copy_end :
> - {
> - *(.__image_copy_end)
> - }
> -
> - . = ALIGN(8);
> -
> - .rel_dyn_start :
> - {
> - *(.__rel_dyn_start)
> - }
> -
> - .rela.dyn : {
> - *(.rela*)
> - }
>
Re: [PATCH v4 18/39] board: dragonboard410c: import board code from mach-snapdragon
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
>
> Some of the db410c board support code was written to be generic and
> placed in mach-snapdragon. However, as the db410c is the only board
> using this, move the code out of mach-snapdragon. This makes is more
s/makes is more/makes it more/
> obvious what code is relevant for which targets and helps tidy things up
> a little more.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/mach-snapdragon/Makefile| 2 -
> arch/arm/mach-snapdragon/dram.c | 99
>
> arch/arm/mach-snapdragon/include/mach/dram.h | 12 ---
> arch/arm/mach-snapdragon/include/mach/misc.h | 13
> arch/arm/mach-snapdragon/misc.c | 55 -
> board/qualcomm/dragonboard410c/Makefile | 2 +-
> board/qualcomm/dragonboard410c/dragonboard410c.c | 48 +++-
> 7 files changed, 45 insertions(+), 186 deletions(-)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/mach-snapdragon/Makefile
> b/arch/arm/mach-snapdragon/Makefile
> index 3a3a297c1768..d02432df8b04 100644
> --- a/arch/arm/mach-snapdragon/Makefile
> +++ b/arch/arm/mach-snapdragon/Makefile
> @@ -6,6 +6,4 @@ obj-$(CONFIG_SDM845) += sysmap-sdm845.o
> obj-$(CONFIG_SDM845) += init_sdm845.o
> obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
> obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
> -obj-y += misc.o
> -obj-y += dram.o
> obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
> diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c
> deleted file mode 100644
> index 499dfdf0da6e..
> --- a/arch/arm/mach-snapdragon/dram.c
> +++ /dev/null
> @@ -1,99 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Onboard memory detection for Snapdragon boards
> - *
> - * (C) Copyright 2018 Ramon Fried
> - *
> - */
> -
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -
> -#define SMEM_USABLE_RAM_PARTITION_TABLE 402
> -#define RAM_PART_NAME_LENGTH16
> -#define RAM_NUM_PART_ENTRIES32
> -#define CATEGORY_SDRAM 0x0E
> -#define TYPE_SYSMEM 0x01
> -
> -struct smem_ram_ptable_hdr {
> - u32 magic[2];
> - u32 version;
> - u32 reserved;
> - u32 len;
> -} __attribute__ ((__packed__));
> -
> -struct smem_ram_ptn {
> - char name[RAM_PART_NAME_LENGTH];
> - u64 start;
> - u64 size;
> - u32 attr;
> - u32 category;
> - u32 domain;
> - u32 type;
> - u32 num_partitions;
> - u32 reserved[3];
> -} __attribute__ ((__packed__));
> -
> -struct smem_ram_ptable {
> - struct smem_ram_ptable_hdr hdr;
> - u32 reserved; /* Added for 8 bytes alignment of header */
> - struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES];
> -} __attribute__ ((__packed__));
> -
> -#ifndef MEMORY_BANKS_MAX
> -#define MEMORY_BANKS_MAX 4
> -#endif
> -
> -int msm_fixup_memory(void *blob)
> -{
> - u64 bank_start[MEMORY_BANKS_MAX];
> - u64 bank_size[MEMORY_BANKS_MAX];
> - size_t size;
> - int i;
> - int count = 0;
> - struct udevice *smem;
> - int ret;
> - struct smem_ram_ptable *ram_ptable;
> - struct smem_ram_ptn *p;
> -
> - ret = uclass_get_device_by_name(UCLASS_SMEM, "smem", );
> - if (ret < 0) {
> - printf("Failed to find SMEM node. Check device tree\n");
> - return 0;
> - }
> -
> - ram_ptable = smem_get(smem, -1, SMEM_USABLE_RAM_PARTITION_TABLE,
> );
> -
> - if (!ram_ptable) {
> - printf("Failed to find SMEM partition.\n");
> - return -ENODEV;
> - }
> -
> - /* Check validy of RAM */
> - for (i = 0; i < RAM_NUM_PART_ENTRIES; i++) {
> - p = _ptable->parts[i];
> - if (p->category == CATEGORY_SDRAM && p->type == TYPE_SYSMEM) {
> - bank_start[count] = p->start;
> - bank_size[count] = p->size;
> - debug("Detected memory bank %u: start: 0x%llx size:
> 0x%llx\n",
> - count, p->start, p->size);
> - count++;
> - }
> - }
> -
> - if (!count) {
> - printf("Failed to detect any memory bank\n");
> - return -ENODEV;
> - }
> -
> - ret = fdt_fixup_memory_banks(blob, bank_start, bank_size, count);
> - if (ret)
> - return ret;
> -
> - return 0;
> -}
> diff --git a/arch/arm/mach-snapdragon/include/mach/dram.h
> b/arch/arm/mach-snapdragon/include/mach/dram.h
> deleted file mode 100644
> index 0a9eedda414c..
> --- a/arch/arm/mach-snapdragon/include/mach/dram.h
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Snapdragon DRAM
> - * Copyright (C) 2018 Ramon Fried
> - */
> -
> -#ifndef DRAM_H
>
Re: [PATCH v4 17/39] board: dragonboard410c: upstream DT compat
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
>
> Use the root compatible strings from upstream Linux, add missing
> '#clock-cells' property to the gcc node.
>
> Adjust some of the msm8916/apq8016 drivers to use the correct upstream
> compatible properties and DT bindings.
>
> This prepares us to switch to upstream DT in a future patch.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/dts/dragonboard410c.dts | 25 +++-
> board/qualcomm/dragonboard410c/dragonboard410c.c | 93 +++-
> doc/device-tree-bindings/usb/ehci-msm.txt| 10 --
> drivers/clk/qcom/clock-apq8016.c | 7 +-
> drivers/phy/qcom/msm8916-usbh-phy.c | 4 +-
> drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 +-
> drivers/usb/host/ehci-msm.c | 22 ++-
> include/dt-bindings/clock/qcom,gcc-msm8916.h | 179
> +++
> 8 files changed, 246 insertions(+), 96 deletions(-)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/dragonboard410c.dts
> b/arch/arm/dts/dragonboard410c.dts
> index c395e6cc0427..453642b25705 100644
> --- a/arch/arm/dts/dragonboard410c.dts
> +++ b/arch/arm/dts/dragonboard410c.dts
> @@ -12,7 +12,7 @@
>
> / {
> model = "Qualcomm Technologies, Inc. Dragonboard 410c";
> - compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
> + compatible = "qcom,apq8016-sbc", "qcom,apq8016";
> qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
> qcom,board-id = <0x10018 0x0>;
> #address-cells = <0x2>;
> @@ -79,6 +79,7 @@
> reg = <0x180 0x8>;
> #address-cells = <0x1>;
> #size-cells = <0x0>;
> + #clock-cells = <0x1>;
> };
>
> serial@78b {
> @@ -91,15 +92,25 @@
> };
>
> ehci@78d9000 {
> - compatible = "qcom,ehci-host";
> + compatible = "qcom,ci-hdrc";
> reg = <0x78d9000 0x400>;
> phys = <_phy>;
> - };
>
> - ehci_phy: ehci_phy@78d9000 {
> - compatible = "qcom,apq8016-usbphy";
> - reg = <0x78d9000 0x400>;
> - #phy-cells = <0>;
> + ulpi {
> + usb_hs_phy: phy {
> + compatible =
> "qcom,usb-hs-phy-msm8916",
> +"qcom,usb-hs-phy";
> + #phy-cells = <0>;
> + clocks = <_board>, <
> GCC_USB2A_PHY_SLEEP_CLK>;
> + clock-names = "ref", "sleep";
> + resets = < GCC_USB2A_PHY_BCR>,
> < 0>;
> + reset-names = "phy", "por";
> + qcom,init-seq = /bits/ 8 <0x0 0x44>,
> +<0x1 0x6b>,
> +<0x2 0x24>,
> +<0x3 0x13>;
> + };
> + };
> };
>
> sdhci@07824000 {
> diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c
> b/board/qualcomm/dragonboard410c/dragonboard410c.c
> index 350e0e9e20aa..1adac07569ae 100644
> --- a/board/qualcomm/dragonboard410c/dragonboard410c.c
> +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -23,84 +24,32 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -int dram_init(void)
> -{
> - gd->ram_size = PHYS_SDRAM_1_SIZE;
> -
> - return 0;
> -}
> -
> -int dram_init_banksize(void)
> -{
> - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> -
> - return 0;
> -}
> +#define USB_HUB_RESET_GPIO 2
> +#define USB_SW_SELECT_GPIO 3
>
> int board_usb_init(int index, enum usb_init_type init)
> {
> - static struct udevice *pmic_gpio;
> - static struct gpio_desc hub_reset, usb_sel;
> - int ret = 0, node;
> + struct udevice *usb;
> + int ret = 0;
>
> - if (!pmic_gpio) {
> - ret = uclass_get_device_by_name(UCLASS_GPIO,
> - "pm8916_gpios@c000",
> - _gpio);
> - if (ret < 0) {
> - printf("Failed to find pm8916_gpios@c000 node.\n");
> - return ret;
> - }
> + /* USB device */
> + ret = device_find_global_by_ofnode(ofnode_path("/soc/usb"), );
> + if (ret) {
> +
