date:20240423

Add the board DT file for the Tanix TX1 TV box, with the H313 SoC.
This has been taken from the sunxi/for-next tree, though it has not been
merged into any other tree yet.
So this is a placeholder for now, to enable the board support, and will be
superseded by the regular sync of the DT files later.

Signed-off-by: Andre Przywara 
---
 arch/arm/dts/sun50i-h313-tanix-tx1.dts | 183 +
 1 file changed, 183 insertions(+)
 create mode 100644 arch/arm/dts/sun50i-h313-tanix-tx1.dts

diff --git a/arch/arm/dts/sun50i-h313-tanix-tx1.dts 
b/arch/arm/dts/sun50i-h313-tanix-tx1.dts
new file mode 100644
index 000..bb2cde59bd0
--- /dev/null
+++ b/arch/arm/dts/sun50i-h313-tanix-tx1.dts
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   model = "Tanix TX1";
+   compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616";
+
+   aliases {
+   serial0 = 
+   ethernet0 = _wifi;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+
+   key {
+   label = "hidden";
+   linux,code = ;
+   gpios = < 7 9 GPIO_ACTIVE_LOW>; /* PH9 */
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   led-0 {
+   function = LED_FUNCTION_POWER;
+   color = ;
+   gpios = < 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+   default-state = "on";
+   };
+   };
+
+   wifi_pwrseq: pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = < CLK_OSC32K_FANOUT>;
+   clock-names = "ext_clock";
+   pinctrl-0 = <_fanout_pin>;
+   pinctrl-names = "default";
+   reset-gpios = < 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
+   };
+
+   reg_vcc5v: vcc5v {
+   /* board wide 5V supply directly from the DC input */
+   compatible = "regulator-fixed";
+   regulator-name = "vcc-5v";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
+};
+
+ {
+   cpu-supply = <_dcdc2>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   vmmc-supply = <_dldo1>;
+   vqmmc-supply = <_aldo1>;
+   mmc-pwrseq = <_pwrseq>;
+   bus-width = <4>;
+   non-removable;
+   status = "okay";
+
+   sdio_wifi: wifi@1 {
+   reg = <1>;
+   };
+};
+
+ {
+   vmmc-supply = <_dldo1>;
+   vqmmc-supply = <_aldo1>;
+   bus-width = <8>;
+   non-removable;
+   max-frequency = <1>;
+   cap-mmc-hw-reset;
+   mmc-ddr-1_8v;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   vcc-pc-supply = <_aldo1>;
+   vcc-pf-supply = <_dldo1>;
+   vcc-pg-supply = <_aldo1>;
+   vcc-ph-supply = <_dldo1>;
+   vcc-pi-supply = <_dldo1>;
+};
+
+_i2c {
+   status = "okay";
+
+   axp313: pmic@36 {
+   compatible = "x-powers,axp313a";
+   reg = <0x36>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+
+   vin1-supply = <_vcc5v>;
+   vin2-supply = <_vcc5v>;
+   vin3-supply = <_vcc5v>;
+
+   regulators {
+   /* Supplies VCC-PLL, so needs to be always on. */
+   reg_aldo1: aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vcc1v8";
+   };
+
+   /* Supplies VCC-IO, so needs to be always on. */
+   reg_dldo1: dldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc3v3";
+   };
+
+   reg_dcdc1: dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <81>;
+   regulator-max-microvolt = <99>;
+   regulator-name = "vdd-gpu-sys";
+   };
+
+   reg_dcdc2: dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <81>;
+   regulator-max-microvolt = <112>;
+

[PATCH 4/4] sunxi: H616: add Tanix TX1 support

The Tanix TX1 is a tiny TV box, featuring the Allwinner H313 SoC with up
to 2GB of DRAM and 16GB of eMMC. There is no SD card or Ethernet port on
this small device, but it can be booted via the USB debug "FEL" mode.
The bootloader could then be written to the eMMC.

Add the defconfig for that board, and add the devicetree file to the
Makefile, for it to be built.
The DRAM parameters were taken from the vendor firmware on the eMMC.

Signed-off-by: Andre Przywara 
---
 arch/arm/dts/Makefile   |  1 +
 configs/tanix_tx1_defconfig | 25 +
 2 files changed, 26 insertions(+)
 create mode 100644 configs/tanix_tx1_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 127345975ef..69b0d6a9ad7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -779,6 +779,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-tanix-tx6.dtb \
sun50i-h6-tanix-tx6-mini.dtb
 dtb-$(CONFIG_MACH_SUN50I_H616) += \
+   sun50i-h313-tanix-tx1.dtb \
sun50i-h616-orangepi-zero2.dtb \
sun50i-h618-orangepi-zero2w.dtb \
sun50i-h618-orangepi-zero3.dtb \
diff --git a/configs/tanix_tx1_defconfig b/configs/tanix_tx1_defconfig
new file mode 100644
index 000..9915fff4a00
--- /dev/null
+++ b/configs/tanix_tx1_defconfig
@@ -0,0 +1,25 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h313-tanix-tx1"
+CONFIG_SPL=y
+CONFIG_DRAM_SUN50I_H616_DX_ODT=0x06060606
+CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0d0d0d0d
+CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1919
+CONFIG_DRAM_SUN50I_H616_ODT_EN=0x9988
+CONFIG_DRAM_SUN50I_H616_TPR6=0x2fb08080
+CONFIG_DRAM_SUN50I_H616_TPR10=0x402f4469
+CONFIG_DRAM_SUN50I_H616_TPR11=0x0e0f0d0d
+CONFIG_DRAM_SUN50I_H616_TPR12=0x11131213
+CONFIG_MACH_SUN50I_H616=y
+CONFIG_SUNXI_DRAM_H616_LPDDR3=y
+CONFIG_R_I2C_ENABLE=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=40
+CONFIG_AXP313_POWER=y
+CONFIG_AXP_DCDC3_VOLT=1200
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
-- 
2.35.8

[PATCH 1/4] sunxi: dts: arm/arm64: update devicetree files from Linux-v6.9-rc4

Sync the devicetree files from the official Linux kernel tree, v6.9-rc4.
This is covering Allwinner SoCs with 32-bit and 64-bit ARM cores.

Besides some cosmectic changes, this adds S/PDIF, DMA, and thermal
support to the H616 .dtsi. Nothing that U-Boot needs for itself, but
helpful to pass on to kernels.
This also adds new devicetrees, for some LonganPi H616 board, and the
Remix Mini PC. The latter will get a defconfig next.

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara 
---
 arch/arm/dts/sun50i-h6-beelink-gs1.dts|   2 +
 arch/arm/dts/sun50i-h6-tanix.dtsi |   2 +
 arch/arm/dts/sun50i-h6.dtsi   |   7 +-
 .../dts/sun50i-h616-bigtreetech-cb1-manta.dts |   2 +-
 arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi |   4 +-
 arch/arm/dts/sun50i-h616-bigtreetech-pi.dts   |   2 +-
 arch/arm/dts/sun50i-h616.dtsi | 155 
 .../arm/dts/sun50i-h618-longan-module-3h.dtsi |  75 
 arch/arm/dts/sun50i-h618-longanpi-3h.dts  | 144 +++
 .../arm/dts/sun50i-h618-transpeed-8k618-t.dts |  23 ++
 arch/arm/dts/sun50i-h64-remix-mini-pc.dts | 356 ++
 arch/arm/dts/sun8i-r40-feta40i.dtsi   |   7 +
 12 files changed, 771 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/dts/sun50i-h618-longan-module-3h.dtsi
 create mode 100644 arch/arm/dts/sun50i-h618-longanpi-3h.dts
 create mode 100644 arch/arm/dts/sun50i-h64-remix-mini-pc.dts

diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts 
b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
index d6897ec9799..87432c4f1ff 100644
--- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
@@ -291,6 +291,8 @@
 };
 
  {
+   pinctrl-names = "default";
+   pinctrl-0 = <_tx_pin>;
status = "okay";
 };
 
diff --git a/arch/arm/dts/sun50i-h6-tanix.dtsi 
b/arch/arm/dts/sun50i-h6-tanix.dtsi
index 4903d635811..855b7d43bc5 100644
--- a/arch/arm/dts/sun50i-h6-tanix.dtsi
+++ b/arch/arm/dts/sun50i-h6-tanix.dtsi
@@ -166,6 +166,8 @@
 };
 
  {
+   pinctrl-names = "default";
+   pinctrl-0 = <_tx_pin>;
status = "okay";
 };
 
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
index 3c85c8cc8ea..09e21689284 100644
--- a/arch/arm/dts/sun50i-h6.dtsi
+++ b/arch/arm/dts/sun50i-h6.dtsi
@@ -405,6 +405,7 @@
function = "spi1";
};
 
+   /omit-if-no-ref/
spdif_tx_pin: spdif-tx-pin {
pins = "PH7";
function = "spdif";
@@ -654,10 +655,8 @@
clocks = < CLK_BUS_SPDIF>, < CLK_SPDIF>;
clock-names = "apb", "spdif";
resets = < RST_BUS_SPDIF>;
-   dmas = < 2>;
-   dma-names = "tx";
-   pinctrl-names = "default";
-   pinctrl-0 = <_tx_pin>;
+   dmas = < 2>, < 2>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts 
b/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts
index dbce61b355d..4bfb52609c9 100644
--- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts
+++ b/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2023 Martin Botka .
  */
diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi 
b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi
index 1fed2b46cfe..af421ba24ce 100644
--- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi
+++ b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2023 Martin Botka .
  */
@@ -93,7 +93,7 @@
interrupt-controller;
#interrupt-cells = <1>;
 
-   regulators{
+   regulators {
reg_dcdc1: dcdc1 {
regulator-name = "vdd-gpu-sys";
regulator-min-microvolt = <81>;
diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts 
b/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts
index 832f08b2b26..ff84a379447 100644
--- a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts
+++ b/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2023 Martin Botka .
  */
diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi
index d549d277d97..b2e85e52d1a 100644
--- a/arch/arm/dts/sun50i-h616.dtsi
+++ b/arch/arm/dts/sun50i-h616.dtsi
@@ -9,6 +9,7 @@
 #include 
 #include

[PATCH 2/4] sunxi: a64: Add Remix Mini PC support

The Remix Mini PC is a "mini computer" using the Allwinner H64 SoC,
which appears to be just a relabelled A64. It was launched in 2015 by
the now defunct company Jide, and shipped with a desktop optimised
version of Android. Its appearance and feature set is close to a
typical TV box.

The devicetree file has been imported from the Linux tree already, so
just add a defconfig and enable the DTB build in the Makefile. The SoC
has the "secure boot" fuse burnt, so we need to generate a TOC0 image
instead of the standard Allwinner eGON image format for the SPL.

Signed-off-by: Andre Przywara 
---
 arch/arm/dts/Makefile   |  3 ++-
 configs/remix-mini-pc_defconfig | 14 ++
 2 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 configs/remix-mini-pc_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..127345975ef 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -801,7 +801,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-pinephone-1.2.dtb \
sun50i-a64-pinetab.dtb \
sun50i-a64-sopine-baseboard.dtb \
-   sun50i-a64-teres-i.dtb
+   sun50i-a64-teres-i.dtb \
+   sun50i-h64-remix-mini-pc.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb \
diff --git a/configs/remix-mini-pc_defconfig b/configs/remix-mini-pc_defconfig
new file mode 100644
index 000..fa427a027f8
--- /dev/null
+++ b/configs/remix-mini-pc_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h64-remix-mini-pc"
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=4013533
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_SPL_IMAGE_TYPE_SUNXI_TOC0=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CMD_POWEROFF=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
-- 
2.35.8

[PATCH 0/4] sunxi: devicetree updates plus new boards

This updates the Allwinner related devicetree files from the Linux
kernel repository. The files were taken from Linux v6.9-rc4, and
adjusted to increase compatibility with older kernels.

This also adds board support for two new devices: the old Remix Mini PC,
a TV box like "Android desktop" device from 2015, and the Tanix TX1,
which is a tiny TV box with an H313 SoC.
The DT for the latter is preliminary for now, as it hasn't been merged
into Linus' tree yet - though that's supposed to happen in about a few
weeks time.

Please have a look!

Cheers,
Andre

Andre Przywara (4):
  sunxi: dts: arm/arm64: update devicetree files from Linux-v6.9-rc4
  sunxi: a64: Add Remix Mini PC support
  [DO NOT MERGE] sunxi: dts: arm64: add Tanix TX1 DT from Linux
  sunxi: H616: add Tanix TX1 support

 arch/arm/dts/Makefile |   4 +-
 arch/arm/dts/sun50i-h313-tanix-tx1.dts| 183 +
 arch/arm/dts/sun50i-h6-beelink-gs1.dts|   2 +
 arch/arm/dts/sun50i-h6-tanix.dtsi |   2 +
 arch/arm/dts/sun50i-h6.dtsi   |   7 +-
 .../dts/sun50i-h616-bigtreetech-cb1-manta.dts |   2 +-
 arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi |   4 +-
 arch/arm/dts/sun50i-h616-bigtreetech-pi.dts   |   2 +-
 arch/arm/dts/sun50i-h616.dtsi | 155 
 .../arm/dts/sun50i-h618-longan-module-3h.dtsi |  75 
 arch/arm/dts/sun50i-h618-longanpi-3h.dts  | 144 +++
 .../arm/dts/sun50i-h618-transpeed-8k618-t.dts |  23 ++
 arch/arm/dts/sun50i-h64-remix-mini-pc.dts | 356 ++
 arch/arm/dts/sun8i-r40-feta40i.dtsi   |   7 +
 configs/remix-mini-pc_defconfig   |  14 +
 configs/tanix_tx1_defconfig   |  25 ++
 16 files changed, 996 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/dts/sun50i-h313-tanix-tx1.dts
 create mode 100644 arch/arm/dts/sun50i-h618-longan-module-3h.dtsi
 create mode 100644 arch/arm/dts/sun50i-h618-longanpi-3h.dts
 create mode 100644 arch/arm/dts/sun50i-h64-remix-mini-pc.dts
 create mode 100644 configs/remix-mini-pc_defconfig
 create mode 100644 configs/tanix_tx1_defconfig

-- 
2.35.8

[PATCH] sysreset: psci: drop reliance on SPL support

At the moment enabling CONFIG_SYSRESET_PSCI *selects* SPL_ARM_PSCI_FW,
even though this is a platform design property, so nothing any driver
should enforce. Some platforms load the PSCI runtime (TF-A) only in the
SPL, so PSCI is naturally not available during SPL runtime.

Spit CONFIG_SYSRESET_PSCI up into an SPL and a U-Boot proper version,
and let the former *depend* on SPL_ARM_PSCI_FW.

This allows to enable CONFIG_SYSRESET_PSCI on platforms without SPL PSCI
support.

Signed-off-by: Andre Przywara 
---
 drivers/sysreset/Kconfig  | 8 +++-
 drivers/sysreset/Makefile | 2 +-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 49c0787b26d..62fe9eb6220 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -119,11 +119,17 @@ config SYSRESET_PALMAS
 config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW
-   select SPL_ARM_PSCI_FW if SPL
help
  Enable PSCI SYSTEM_RESET function call.  To use this, PSCI firmware
  must be running on your system.
 
+config SYSRESET_SPL_PSCI
+   bool "Enable support for PSCI System Reset in SPL"
+   depends on SPL_ARM_PSCI_FW
+   help
+ Enable PSCI SYSTEM_RESET function call in the SPL. To use this, PSCI
+ firmware must be running on your system before the SPL.
+
 config SYSRESET_SBI
bool "Enable support for SBI System Reset"
depends on RISCV_SMODE && SBI_V02
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index e0e732205df..8d992ae0930 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
 obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
 obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_PALMAS) += sysreset_palmas.o
-obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_$(SPL_TPL_)SYSRESET_PSCI) += sysreset_psci.o
 obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o
 obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
 obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
-- 
2.35.8

[GIT PULL] please pull fsl-qoriq-2024-4-24

2024-04-23 Thread Peng Fan

Hi Tom,

Please pull fsl-qoriq-2024-4-24

---
move to OF_UPSTREAM for sl28
---
CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/20501

Thanks,
Peng.

The following changes since commit 38ea74d6d5c05224acdb03f799897c1bdd56f8cc:

  Prepare v2024.07-rc1 (2024-04-22 15:10:21 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git 
tags/fsl-qoriq-2024-4-24

for you to fetch changes up to 61ff13283c3b3858989c038a5dc57b1370e5d8ce:

  board: sl28: move to OF_UPSTREAM (2024-04-24 00:22:09 +0800)


Michael Walle (1):
  board: sl28: move to OF_UPSTREAM

 arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts |  59 
 arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts |  65 -
 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts |  15 ---
 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts |  47 -
 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts  | 308 
---
 board/kontron/sl28/spl.c   |  11 +--
 configs/kontron_sl28_defconfig |   5 +-
 7 files changed, 8 insertions(+), 502 deletions(-)
 delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
 delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
 delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts
 delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
 delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts

Re: [PATCH] ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM


On 4/19/24 5:24 PM, Tim Harvey wrote:

On Thu, Apr 18, 2024 at 11:42 AM Marek Vasut  wrote:


On 4/18/24 8:02 PM, Fabio Estevam wrote:

Hi Tim,

On Thu, Apr 18, 2024 at 2:54 PM Tim Harvey  wrote:


Fabio, if you enable CONFIG_DM_RNG on an imx8m{m,p}_evk do you get the
following in the SPL?
Couldn't bind rng driver (-96)
SEC0:  RNG instantiated

sec_init failed!


Yes, if I add CONFIG_DM_RNG=y to imx8mm_evk_defconfig I get:

U-Boot SPL 2024.04-00793-g3434b88d2c2f-dirty (Apr 18 2024 - 14:58:57 -0300)
No pmic
Couldn't bind rng driver (-96)
SEC0:  RNG instantiated

sec_init failed!


Interesting. Which TFA blob version do you use ? I used the mainline
2.10 for my tests.


Marek,

Were you able to reproduce this as well with the board you enabled
DM_RNG for? If it does work fine what dtb were you using... perhaps
there is something in its u-boot.dtsi that we need?


This one arch/arm/dts/imx8mp-dhcom-pdk3.dts , see log below. The build 
has a few extra patches in it, but nothing which affects the KASLR:


$ export SOURCE_DATE_EPOCH=1672531200 ; echo tst > .scmversion
$ make imx8mp_dhcom_pdk3_defconfig ; make

U-Boot SPL 2024.07-rc1tst (Jan 01 2023 - 00:00:00 +)
DDR:   4096 MiB [0x5]
DDR:   Inline ECC enabled
WDT:   Started watchdog@3028 with servicing every 1000ms (60s timeout)
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x1000, pagesize 0x1, ivt offset 0x0
NOTICE:  Do not release JR0 to NS as it can be used by HAB
NOTICE:  BL31: v2.10.0  (release):v2.10.0-5-gfb51ca229
NOTICE:  BL31: Built : 20:30:36, Apr 23 2024


U-Boot 2024.07-rc1tst (Jan 01 2023 - 00:00:00 +)

CPU:   Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 70C
Reset cause: POR
Model: DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)
DRAM:  3.5 GiB
Core:  183 devices, 34 uclasses, devicetree: separate
WDT:   Started watchdog@3028 with servicing every 1000ms (60s timeout)
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from SPIFlash... SF: Detected w25q128jw with page 
size 256 Bytes, erase size 4 KiB, total 16 MiB

OK
In:serial
Out:   serial
Err:   serial
SEC0:  RNG instantiated
Net:   eth1: ethernet@30be, eth0: ethernet@30bf
...


The error -EPFNOSUPPORT is interesting and helps point to the only
place it can be where the comment says the strange errno is to make
this easier to find:
https://elixir.bootlin.com/u-boot/latest/source/drivers/core/uclass.c#L70:
 if (!uc_drv) {
 debug("Cannot find uclass for id %d: please add the
UCLASS_DRIVER() declaration for this UCLASS_... id\n",
   id);
 /*
  * Use a strange error to make this case easier to find. When
  * a uclass is not available it can prevent driver model from
  * starting up and this failure is otherwise hard to debug.
  */
 return -EPFNOSUPPORT;
 }

I'm not very familiar with the dm driver binding - does the
U-BOOT_DRIVER usage in drivers/crypto/fsl/rng.c need to be refactored
to use UCLASS_DRIVER for it to be usable in both SPL and U-Boot?


I don't think you need the CAAM RNG in SPL in the first place, or do you ?


Honestly I don't know why we need DM_RNG in SPL anyway and we could
just add support for disabling it there to avoid unwanted bloat.


I think you can disable it , yes.

Re: [PATCH] usb: dwc2: Add in version 4xx compatibility

On 4/23/24 9:09 AM, Mattijs Korpershoek wrote:

Hi Greg,

On ven., avril 19, 2024 at 15:21, Greg Malysa wrote:

Hi Mattijs,

Please avoid top-posting when replying, it makes following the
discussion more difficult:
https://www.kernel.org/doc/html/latest/process/submitting-patches.html#use-trimmed-interleaved-replies-in-email-discussions

Will do. Sorry about that; I'm still learning about this approach to email.

No worries. There are quite some things to learn and we probably all did
this wrong when starting. Thank you for taking the time to learn and to
contribute!

Looking at
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=65dc2e725286106f99c6f6b78e3d9c52c15f3a9c

we can see that the following is added:
#define DWC2_CORE_REV_MASK 0x

This makes me believe that the versioning follows a well known pattern.

I can submit a v2 next week to bring it in line with the kernel's approach.

To me, it's fine as is.

Note that this change is also part of:
https://lore.kernel.org/all/20240328131811.94559-1-seashell11234...@gmail.com/

Or if you prefer I can also drop our patch and we can pursue this
linked patch with both 4xx compatibility and the 420a reset handling.

I think the patch you submitted is fine by itself, but I'd let Marek
decide since he is the maintainer for this part.

If you have access to the hardware that has a 4.20a dwc2 controller,
maybe you can help testing the patch above patch as well?

+CC Liu on this thread, maybe it is best if the two of you figure out
the best common approach that works for you both ?

Re: [PATCH v4] mmc: Poll CD in case cyclic framework is enabled


On 3/16/24 9:13 PM, Marek Vasut wrote:

In case the cyclic framework is enabled, poll the card detect of already
initialized cards and deinitialize them in case they are removed. Since
the card initialization is a longer process and card initialization is
done on first access to an uninitialized card anyway, avoid initializing
newly detected uninitialized cards in the cyclic callback.


Any input on this ?

[PATCH] ARM: dts: imx: Enable PCIe and NVMe on DH i.MX8M Plus DHCOM PDK3

Enable PCIe/NVMe support on DH i.MX8M Plus DHCOM PDK3. Except for
the configuration options which are enabled, add slight adjustment
to board u-boot.dtsi, which is necessary as there is currently no
driver for the I2C PCIe clock generator. Since the generator is
strapped to be always on, it is possible to supplant the generator
functionality by fixed-clock.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Simon Glass 
Cc: Stefano Babic 
Cc: Tom Rini 
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
 arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi | 12 
 configs/imx8mp_dhcom_pdk3_defconfig|  5 +
 2 files changed, 17 insertions(+)

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi 
b/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi
index 040f333c52d..b0b99d51856 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi
@@ -4,3 +4,15 @@
  */
 
 #include "imx8mp-dhcom-u-boot.dtsi"
+
+/ {
+   clk_pcie100: clk-pcie100 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <1>;
+   };
+};
+
+_phy {
+   clocks = <_pcie100>;
+};
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig 
b/configs/imx8mp_dhcom_pdk3_defconfig
index a42dc27aff8..019595edda8 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -31,6 +31,7 @@ CONFIG_ENV_OFFSET_REDUND=0xFF
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
 CONFIG_SYS_LOAD_ADDR=0x5000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
@@ -104,6 +105,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_BKOPS_ENABLE=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_READ=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -218,7 +220,10 @@ CONFIG_DWC_ETH_QOS_IMX=y
 CONFIG_FEC_MXC=y
 CONFIG_RGMII=y
 CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
 CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PHY_IMX8M_PCIE=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-- 
2.43.0

Re: [PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588

2024-04-23 Thread Jonas Karlman

Hi Quentin,

On 2024-04-15 16:16, Quentin Schulz wrote:
> From: Quentin Schulz 
> 
> Allow RK3568 and RK3588 based boards to get the RAM bank configuration
> from the ROCKCHIP_TPL stage instead of the current logic. This fixes
> both an issue where 256MB of RAM is blocked for devices with >= 4GB
> of RAM and where memory holes need to be defined for devices with
> more than 16GB of RAM. In the event that neither SoC is used or the
> ROCKCHIP_TPL stage is not used, fall back to existing logic.
> 
> The logic handles creating memory holes from reserved memory areas
> defined in mem_map data struct in SoC C files, but only if the DRAM area
> overlaps with one reserved memory area.
> 
> Since mem_map data struct is used, it should be rather straightforward
> to add support for other SoCs if needed.
> 
> The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1
> (e08e32143dd).
> 
> Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as
> well, but the DDR_MEM tag seems to be pretty much stable (though BL31
> seems to be reserving only 1MB for itself at the moment).
> 
> u32 for ATAGS is used because it simplifies the pointer arithmetic and
> it's expected that ATAGS are always below the 4GB limit allowed by u32.
> 
> Co-developed-by: Chris Morgan 
> Signed-off-by: Chris Morgan 
> Signed-off-by: Quentin Schulz 
> ---
>  arch/arm/mach-rockchip/sdram.c | 240 
> +
>  1 file changed, 240 insertions(+)
> 
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 0d9a0aef6f5..5b1ff1e5495 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -8,6 +8,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -35,12 +36,251 @@ struct tos_parameter_t {
>   s64 reserve[8];
>  };
>  
> +/* Tag size and offset */
> +#define ATAGS_SIZE   SZ_8K
> +#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
> +#define ATAGS_PHYS_BASE  (CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
> +#define ATAGS_PHYS_END   (ATAGS_PHYS_BASE + ATAGS_SIZE)
> +
> +/* ATAGS memory structures */
> +
> +enum tag_magic {
> + ATAG_NONE,
> + ATAG_CORE = 0x54410001,
> + ATAG_SERIAL = 0x54410050,
> + ATAG_DDR_MEM = 0x54410052,
> + ATAG_MAX = 0x544100ff,
> +};
> +
> +/*
> + * An ATAG contains the following data:
> + *  - header
> + *u32 size // sizeof(header + tag data) / sizeof(u32)
> + *u32 magic
> + *  - tag data
> + */
> +
> +struct tag_header {
> + u32 size;
> + u32 magic;
> +} __packed;
> +
> +/*
> + * DDR_MEM tag bank is storing data this way:
> + *  - address0
> + *  - address1
> + *  - [...]
> + *  - addressX
> + *  - size0
> + *  - size1
> + *  - [...]
> + *  - sizeX
> + *
> + *  with X being tag_ddr_mem.count - 1.
> + */
> +struct tag_ddr_mem {
> + u32 count;
> + u32 version;
> + u64 bank[20];
> + u32 flags;
> + u32 data[2];
> + u32 hash;
> +} __packed;
> +
> +static u32 js_hash(const void *buf, u32 len)
> +{
> + u32 i, hash = 0x47C6A7E6;
> +
> + if (!buf || !len)
> + return hash;
> +
> + for (i = 0; i < len; i++)
> + hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
> +
> + return hash;
> +}
> +
> +static int rockchip_dram_init_banksize(void)
> +{
> + const struct tag_header *tag_h = NULL;
> + u32 *addr = (void *)ATAGS_PHYS_BASE;
> + struct tag_ddr_mem *ddr_info;
> + u32 calc_hash;
> + u8 i, j;
> +
> + if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
> + !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
> + return -ENOTSUPP;
> +
> + if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
> + return -ENOTSUPP;
> +
> + /* Find DDR_MEM tag */
> + while (addr < (u32 *)ATAGS_PHYS_END) {
> + tag_h = (const struct tag_header *)addr;
> +
> + if (!tag_h->size) {
> + debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
> + return -ENODATA;
> + }
> +
> + if (tag_h->magic == ATAG_DDR_MEM)
> + break;
> +
> + switch (tag_h->magic) {
> + case ATAG_NONE:
> + case ATAG_CORE:
> + case ATAG_SERIAL ... ATAG_MAX:
> + addr += tag_h->size;
> + continue;
> + default:
> + debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
> +   tag_h->magic, addr);
> + return -EINVAL;
> + }
> + }
> +
> + if (addr >= (u32 *)ATAGS_PHYS_END ||
> + (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
> + debug("End of ATAGS, no DDR_MEM found\n");
> + return -ENODATA;
> + }
> +
> + /* Data is right after the magic member of the tag_header struct */
> + ddr_info = (struct tag_ddr_mem *)(_h->magic + 1);
> + if

Re: [PULL] Please pull qcom/qcom-main

2024-04-23 Thread Tom Rini

On Tue, Apr 23, 2024 at 03:46:19PM +0200, Caleb Connolly wrote:

> Overshot the -rc1 deadline, but I hope these can still make in for 2024.07.
> 
> Support is added for 5 new Qualcomm SoCs:
> 
> * QCM2290 and SM6115 are low and mid range SoCs used on the RB1 and RB2
>   respectively. SM6115 is also used in some mid-range smartphones/tablets.
>   Initial support includes buttons and USB (host and gadget).
> * SM8250 is a flagship SoC from 2020 used on the RB5, as well as many flagship
>   smartphones. The board can boot to a U-Boot prompt, but is missing 
> regulators
>   necessary for USB support.
> * SM8550, and SM8650 are flagship mobile SoCs from 2023 and 2024
>   respectively. Found on many high end smartphones.
> 
> In addition:
> 
> * Support is added for the Schneider HMIBSC board.
> * mach-snapdragon switches to OF_UPSTREAM
> * IPQ40xx gets several regressions fixed and some overall cleanup.
> * The MSM serial driver gains the ability to generate the bit-clock
>   automatically, no longer relying on a custom DT property.
> * The Qualcomm SMMU driver gets a generic compatible (so per-SoC compatibles
>   don't need to be added).
> * Support for the GENI I2C controller is added.
> * The qcom SPMI driver has SPMI v5 support fixed, and v7 support added.
> * The qcom sdhci driver gets some fixes for SDCC v5 support.
> * SDM845 gains sdcard support
> * Support is added for the Synopsys eUSB2 PHY driver (used on SM8550 and 
> SM8650)
> * SYS_INIT_SP_BSS_OFFSET is set to 1.5M to give us more space for FDTs.
> * RB2 gets a work-around to fix the USB dr_mode property before booting Linux.
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH] cmd: gpt: initialize partition table

2024-04-23 Thread Kishan Dudhatra

Yes, You are right I observed the issue in MMC device, device required reboot 
after writing partitions.

I have checked the fix is required for all the blk device's not just mmc device.

I have updated the changes in v2.

Thanks,
Kishan






From: Tom Rini 
Sent: Monday, April 22, 2024 11:14:47 PM
To: Kishan Dudhatra 
Cc: u-boot@lists.denx.de 
Subject: Re: [PATCH] cmd: gpt: initialize partition table

CAUTION: This email originated from outside the organization. Do not click 
links or open attachments unless you recognize the sender and know the content 
is safe.

[PATCH 3/3] ARM: dts: imx: Convert i.MX8M flash.bin image generation to binman

Rework the flash.bin image generation such that it uses the new binman
nxp_imx8mimage etype. This way, the flash.bin is assembled in correct
order using plain binman, without any workarounds or sections assembled
in special DT node order.

Signed-off-by: Marek Vasut 
---
WARNING: This is very likely to break corner case uses, so please do
 test this on your platform.
NOTE: This also opens the implementation for proper CST signing etype,
  the CST signing would look similar to nxp-imx8mimage section, and
  it would likely wrap the whole topmost section {} in the binman
  node.
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Adam Ford 
Cc: Alper Nebi Yasak 
Cc: Andrejs Cainikovs 
Cc: Angus Ainslie 
Cc: Emanuele Ghidoli 
Cc: Fabio Estevam 
Cc: Francesco Dolcini 
Cc: Marcel Ziswiler 
Cc: Rasmus Villemoes 
Cc: Simon Glass 
Cc: Stefan Eichenberger 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tom Rini 
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
 arch/arm/dts/imx8mm-u-boot.dtsi   | 126 ++-
 .../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi|   8 +-
 arch/arm/dts/imx8mn-u-boot.dtsi   | 147 +++---
 arch/arm/dts/imx8mp-dhcom-u-boot.dtsi |   2 +-
 arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi|   2 +-
 arch/arm/dts/imx8mp-u-boot.dtsi   |  96 +---
 arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi|  15 +-
 arch/arm/dts/imx8mq-u-boot.dtsi   | 109 +
 8 files changed, 203 insertions(+), 302 deletions(-)

diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 06f2f73a03f..6ab8f66256e 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -5,7 +5,6 @@
 
 / {
binman: binman {
-   multiple-images;
};
 
 #ifdef CONFIG_OPTEE
@@ -43,56 +42,61 @@
 };
 
  {
-   u-boot-spl-ddr {
-   align = <4>;
-   align-size = <4>;
-   filename = "u-boot-spl-ddr.bin";
-   pad-byte = <0xff>;
-
-   u-boot-spl {
-   align-end = <4>;
-   filename = "u-boot-spl.bin";
-   };
+   filename = "flash.bin";
+   section {
+   pad-byte = <0x00>;
 
-   ddr-1d-imem-fw {
-   filename = "lpddr4_pmu_train_1d_imem.bin";
-   align-end = <4>;
+#ifdef CONFIG_FSPI_CONF_HEADER
+   fspi_conf_block {
+   filename = CONFIG_FSPI_CONF_FILE;
type = "blob-ext";
+   size = <0x1000>;
};
+#endif
 
-   ddr-1d-dmem-fw {
-   filename = "lpddr4_pmu_train_1d_dmem.bin";
-   align-end = <4>;
-   type = "blob-ext";
-   };
+   nxp-imx8mimage {
+   filename = "u-boot-spl-mkimage.bin";
+   nxp,boot-from = "sd";
+   nxp,rom-version = <1>;
+   nxp,loader-address = ;
+   args;   /* Needed by mkimage etype superclass */
 
-   ddr-2d-imem-fw {
-   filename = "lpddr4_pmu_train_2d_imem.bin";
-   align-end = <4>;
-   type = "blob-ext";
-   };
+   section {
+   align = <4>;
+   align-size = <4>;
+   filename = "u-boot-spl-ddr.bin";
+   pad-byte = <0xff>;
 
-   ddr-2d-dmem-fw {
-   filename = "lpddr4_pmu_train_2d_dmem.bin";
-   align-end = <4>;
-   type = "blob-ext";
-   };
-   };
+   u-boot-spl {
+   align-end = <4>;
+   filename = "u-boot-spl.bin";
+   };
 
-   spl {
-   filename = "spl.bin";
+   ddr-1d-imem-fw {
+   filename = 
"lpddr4_pmu_train_1d_imem.bin";
+   align-end = <4>;
+   type = "blob-ext";
+   };
 
-   mkimage {
-   args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 
0x7e1000";
+   ddr-1d-dmem-fw {
+   filename = 
"lpddr4_pmu_train_1d_dmem.bin";
+   align-end = <4>;
+   type = "blob-ext";
+   };
 
-   blob {
-   filename = "u-boot-spl-ddr.bin";
+   ddr-2d-imem-fw {
+   filename =

[PATCH 2/3] ARM: dts: imx: Switch Ronetix iMX8MQ-CM to imx8mq-u-boot.dtsi

Include imx8mq-u-boot.dtsi in the board -u-boot.dtsi to pull in binman
configuration instead of duplicating it in the board -u-boot.dtsi again.
Drop the duplicate binman configuration.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Adam Ford 
Cc: Alper Nebi Yasak 
Cc: Andrejs Cainikovs 
Cc: Angus Ainslie 
Cc: Emanuele Ghidoli 
Cc: Fabio Estevam 
Cc: Francesco Dolcini 
Cc: Marcel Ziswiler 
Cc: Rasmus Villemoes 
Cc: Simon Glass 
Cc: Stefan Eichenberger 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tom Rini 
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
 arch/arm/dts/imx8mq-cm-u-boot.dtsi | 111 +
 1 file changed, 1 insertion(+), 110 deletions(-)

diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi 
b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
index e23998f5aba..819501337e9 100644
--- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
@@ -3,11 +3,7 @@
  * Copyright 2019 NXP
  */
 
-/ {
-   binman: binman {
-   multiple-images;
-   };
-};
+#include "imx8mq-u-boot.dtsi"
 
 _uart1 {
bootph-pre-ram;
@@ -16,108 +12,3 @@
  {
bootph-pre-ram;
 };
-
- {
-u-boot-spl-ddr {
-   filename = "u-boot-spl-ddr.bin";
-   pad-byte = <0xff>;
-   align-size = <4>;
-   align = <4>;
-
-   u-boot-spl {
-   align-end = <4>;
-   };
-
-   ddr-1d-imem-fw {
-   filename = "lpddr4_pmu_train_1d_imem.bin";
-   type = "blob-ext";
-   align-end = <4>;
-   };
-
-   ddr-1d-dmem-fw {
-   filename = "lpddr4_pmu_train_1d_dmem.bin";
-   type = "blob-ext";
-   align-end = <4>;
-   };
-
-   ddr-2d-imem-fw {
-   filename = "lpddr4_pmu_train_2d_imem.bin";
-   type = "blob-ext";
-   align-end = <4>;
-   };
-
-   ddr-2d-dmem-fw {
-   filename = "lpddr4_pmu_train_2d_dmem.bin";
-   type = "blob-ext";
-   align-end = <4>;
-   };
-   };
-
-   flash {
-   mkimage {
-   args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 
0x7e1000";
-
-   blob {
-   filename = "u-boot-spl-ddr.bin";
-   };
-   };
-   };
-
-   itb {
-   filename = "u-boot.itb";
-
-   fit {
-   description = "Configuration to load ATF before U-Boot";
-   #address-cells = <1>;
-   fit,external-offset = ;
-
-   images {
-   uboot {
-   description = "U-Boot (64-bit)";
-   type = "standalone";
-   arch = "arm64";
-   compression = "none";
-   load = ;
-
-   uboot_blob: blob-ext {
-   filename = "u-boot-nodtb.bin";
-   };
-   };
-
-   atf {
-   description = "ARM Trusted Firmware";
-   type = "firmware";
-   arch = "arm64";
-   compression = "none";
-   load = <0x91>;
-   entry = <0x91>;
-
-   atf_blob: blob-ext {
-   filename = "bl31.bin";
-   };
-   };
-
-   fdt {
-   description = "NAME";
-   type = "flat_dt";
-   compression = "none";
-
-   uboot_fdt_blob: blob-ext {
-   filename = "u-boot.dtb";
-   };
-   };
-   };
-
-   configurations {
-   default = "conf";
-
-   conf {
-   description = "NAME";
-   firmware = "uboot";
-   loadables = "atf";
-   fdt = "fdt";
-   };
-   };
-   };
-   };
-};
-- 
2.43.0

[PATCH 1/3] binman: Add nxp_imx8mimage etype

Add new binman etype derived from mkimage etype which generates configuration
input file for mkimage -T imx8mimage, and runs the mkimage on input data. The
mkimage -T imx8mimage is used to generate combined image with SPL and DDR PHY
blobs which is bootable on i.MX8M.

The configuration file generated here is equivalent of imx8mimage.cfg, which
is the file passed to '$ mkimage -T imx8mimage -n imx8mimage.cfg ...' . The
settings generated into the imx8mimage.cfg file are configured via supported
binman DT properties, nxp,boot-from, nxp,loader-address, nxp,rom-version.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Adam Ford 
Cc: Alper Nebi Yasak 
Cc: Andrejs Cainikovs 
Cc: Angus Ainslie 
Cc: Emanuele Ghidoli 
Cc: Fabio Estevam 
Cc: Francesco Dolcini 
Cc: Marcel Ziswiler 
Cc: Rasmus Villemoes 
Cc: Simon Glass 
Cc: Stefan Eichenberger 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tom Rini 
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
 tools/binman/etype/nxp_imx8mimage.py | 73 
 1 file changed, 73 insertions(+)
 create mode 100644 tools/binman/etype/nxp_imx8mimage.py

diff --git a/tools/binman/etype/nxp_imx8mimage.py 
b/tools/binman/etype/nxp_imx8mimage.py
new file mode 100644
index 000..5a106e0a76e
--- /dev/null
+++ b/tools/binman/etype/nxp_imx8mimage.py
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023-2024 Marek Vasut 
+# Written with much help from Simon Glass 
+#
+# Entry-type module for generating the i.MX8M mkimage -T imx8mimage
+# configuration file and invocation of mkimage -T imx8mimage on the
+# configuration file and input data.
+#
+
+from collections import OrderedDict
+
+from binman.entry import Entry
+from binman.etype.mkimage import Entry_mkimage
+from binman import elf
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+class Entry_nxp_imx8mimage(Entry_mkimage):
+"""NXP i.MX8M imx8mimage .cfg file generator and mkimage invoker
+
+Properties / Entry arguments:
+- nxp,boot-from - device to boot from (e.g. 'sd')
+- nxp,loader-address - loader address (SPL text base)
+- nxp,rom-version - BootROM version ('2' for i.MX8M Nano and Plus)
+"""
+
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node)
+self.required_props = ['nxp,boot-from', 'nxp,rom-version', 
'nxp,loader-address']
+
+def ReadNode(self):
+super().ReadNode()
+self.boot_from = fdt_util.GetString(self._node, 'nxp,boot-from')
+self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address')
+self.rom_version = fdt_util.GetInt(self._node, 'nxp,rom-version')
+self.ReadEntries()
+
+def BuildSectionData(self, required):
+_, input_fname, uniq = self.collect_contents_to_file(
+self._entries.values(), 'input')
+# Generate mkimage configuration file similar to imx8mimage.cfg
+# and pass it to mkimage to generate SPL image for us here.
+cfg_fname = tools.get_output_filename('nxp.imx8mimage.cfg.%s' % uniq)
+with open(cfg_fname, 'w') as outf:
+print('ROM_VERSION v%d' % self.rom_version, file=outf)
+print('BOOT_FROM %s' % self.boot_from, file=outf)
+print('LOADER %s %#x' % (input_fname, self.loader_address), 
file=outf)
+
+output_fname = tools.get_output_filename(f'cfg-out.{uniq}')
+args = ['-d', input_fname, '-n', cfg_fname, '-T', 'imx8mimage',
+output_fname]
+if self.mkimage.run_cmd(*args) is not None:
+return tools.read_file(output_fname)
+else:
+# Bintool is missing; just use the input data as the output
+self.record_missing_bintool(self.mkimage)
+return data
+
+def SetImagePos(self, image_pos):
+# Customized SoC specific SetImagePos which skips the mkimage etype
+# implementation and removes the 0x48 offset introduced there. That
+# offset is only used for uImage/fitImage, which is not the case in
+# here.
+upto = 0x00
+for entry in super().GetEntries().values():
+entry.SetOffsetSize(upto, None)
+
+# Give up if any entries lack a size
+if entry.size is None:
+return
+upto += entry.size
+
+super(Entry_mkimage, self).SetImagePos(image_pos)
-- 
2.43.0

Re: [PATCH 2/2] tools: type arguemnts

2024-04-23 Thread Fabio Estevam

On Fri, Apr 19, 2024 at 9:13 AM Heinrich Schuchardt
 wrote:
>
> %s/arguemnts/arguemnts/

There is a typo in the Subject: %s/type/typo/

[PATCH v1] board: toradex: colibri-imx(6ull|imx7): Fix missing fdt_fixup boot error

2024-04-23 Thread Francesco Dolcini

From: Francesco Dolcini 

In commit 51aaaf5e7975 ("board: toradex: imx: Remove not needed env variables")
the empty definition of fdt_fixup variable was removed, however this was
still referenced from the boot command leading to boot failures:
 ## Error: \"fdt_fixup\" not defined`

Fix this by removing "run fdt_fixup" from the boot command and instead
enable CONFIG_OF_ENV_SETUP in the defconfig that would achieve the same
but in a more robust way (it works fine even if the variable is not
defined).

Fixes: 51aaaf5e7975 ("board: toradex: imx: Remove not needed env variables")
Signed-off-by: Francesco Dolcini 
---
 configs/colibri-imx6ull_defconfig | 1 +
 configs/colibri_imx7_defconfig| 1 +
 include/configs/colibri-imx6ull.h | 2 +-
 include/configs/colibri_imx7.h| 2 +-
 4 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/configs/colibri-imx6ull_defconfig 
b/configs/colibri-imx6ull_defconfig
index fc10d7f66a60..4a0ff029ac75 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -18,6 +18,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
+CONFIG_OF_ENV_SETUP=y
 CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;"
 CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile 
imx6ull-colibri${variant}-${fdt_board}.dtb"
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 16f923b07c22..f2802b10fa8a 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -19,6 +19,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
+CONFIG_OF_ENV_SETUP=y
 CONFIG_BOOTCOMMAND="run ubiboot ; echo ; echo ubiboot failed ; run 
distro_bootcmd;"
 CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile 
${soc}-colibri-${fdt_board}.dtb "
diff --git a/include/configs/colibri-imx6ull.h 
b/include/configs/colibri-imx6ull.h
index 7c9d633b68d9..8860ceec1a0a 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -53,7 +53,7 @@
"ubi part ubi &&" \
"ubi read ${kernel_addr_r} kernel && " \
"ubi read ${fdt_addr_r} dtb && " \
-   "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+   "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
 #if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_NAND)
 /* Run Distro Boot script if ubiboot fails */
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index c34f1f903df6..33133a0b96e1 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -94,7 +94,7 @@
"ubi part ubi && run m4boot && " \
"ubi read ${kernel_addr_r} kernel && " \
"ubi read ${fdt_addr_r} dtb && " \
-   "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+   "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
 #if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
 #define MODULE_EXTRA_ENV_SETTINGS \
-- 
2.39.2

Re: RISC-V u-boot unable to boot QEMU using '-cpu max'

2024-04-23 Thread Conor Dooley

On Tue, Apr 23, 2024 at 09:52:06AM -0300, Daniel Henrique Barboza wrote:
> 
> 
> On 4/23/24 09:41, Conor Dooley wrote:
> > On Tue, Apr 23, 2024 at 01:34:42PM +0800, Leo Liang wrote:
> > > On Mon, Apr 22, 2024 at 04:43:59PM -0300, Daniel Henrique Barboza wrote:
> > > > [EXTERNAL MAIL]
> > > > 
> > > > Hi,
> > > > 
> > > > In QEMU we have a 'max' type CPU that implements (almost) all 
> > > > extensions that QEMU
> > > > is able to emulate. Recently, in QEMU commit 249e0905d05, we bumped the 
> > > > extensions
> > > > for this CPU.
> > > > 
> > > > And after this commit this CPU is now unable to boot a guest using 
> > > > upstream
> > > > u-boot. Here's the error being thrown:
> > > > 
> > > > qemu-system-riscv64 \
> > > >  -machine virt -nographic -m 8G -smp 8 \
> > > >  -cpu max -kernel uboot.elf (...)
> > > > (...)
> > > > 
> > > > initcall sequence 8027c3e8 failed at call 8021259e 
> > > > (err=-28)
> > > > ### ERROR ### Please RESET the board ###
> > > > 
> > > > 
> > > > I can get the guest to boot if I disable the following extensions from 
> > > > the 'max' CPU:
> > > > 
> > > >   -cpu max,zfbfmin=false,zvfbfmin=false,zvfbfwma=false
> > > > 
> > > > Due to QEMU extension dependencies I'm not able to disable these 
> > > > individually. What I can
> > > > say is that u-boot isn't playing ball to at least one of them.
> > > > 
> > > > Is this an u-boot bug? Up to this point I was assuming that u-boot 
> > > > would silently ignore
> > > > hart extensions that it doesn't support.
> > > 
> > > Hi Daniel,
> > > 
> > > Which u-boot version are you using?
> > > 
> > > I think this issue is fixed by the following patch set sent by Conor.
> > > 
> > >   f39b1b77d8 riscv: support extension probing using riscv, isa-extensions
> > >   b90edde701 riscv: don't read riscv, isa in the riscv cpu's get_desc()
> > > 
> > > I've tested and can reproduce the issue you mentioned if these two 
> > > patches are reverted.
> > > 
> > > Could you try with the lastest u-boot master branch again?
> > > 
> > > 
> > > For reference, my testing commands are as follows:
> > > 1. cd ${u-boot} && make qemu-riscv64_defconfig && make -j`nproc`
> > > 2. ./${qemu}/build/qemu-system-riscv64 -nographic -machine virt -cpu max 
> > > -bios u-boot.bin -m 8G -smp 8
> > > 
> > > - u-boot branch (commit): master (38ea74d6d5c0 "Prepare v2024.07-rc1")
> > > - qemu branch (commit): master (62dbe54c24db "Update version for 
> > > v9.0.0-rc4 release")
> > 
> > I'll go take a look at this, it's possible that my patches only hide the
> > problem due to the new property being prioritised.
> 
> 
> Don't bother. I just checked with most recent u-boot master and I can't 
> reproduce the
> problem, as Leo said.

My "fear" was that new QEMU + new U-Boot meant that the
riscv,isa-extensions codepath was in use and there was something lurking in
the riscv,isa parsing which had a problem. Fortunately, I think that's
not the case, as the fix seems to be b90edde701 "riscv: don't read riscv,isa
in the riscv cpu's get_desc()" rather than f39b1b77d8 "riscv: support
extension probing using riscv, isa-extensions".

I am, however, not going to look into why exactly it was failing before,
I'm satisfied once the riscv,isa parsing isn't broken in master.

> 
> I apologize for the noise. I failed to fetch the latest upstream and do a last
> test before posting it here.
> 
> We were discussing here and there about disabling these extensions in the 
> 'max'
> CPU in QEMU if u-boot wasn't able to handle them. I'm happy to see that u-boot
> is now able to do so and we can keep the 'max' CPU as is.
> 
> 
> Thanks for the help,
> 
> Daniel
> 


signature.asc
Description: PGP signature

[PATCH v2] usb: dwc3: support USB 3.1 controllers

The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.

Equivalent upstream Linux patch:
690fb3718a70 ("usb: dwc3: Support Synopsys USB 3.1 IP")

Reviewed-by: Neil Armstrong 
Tested-by: Neil Armstrong  # on SM8550
Reviewed-by: Mattijs Korpershoek 
Reviewed-by: Marek Vasut 
Signed-off-by: Caleb Connolly 
---
Changes since v1:
* Reference Linux patch
* V1: 
https://lore.kernel.org/u-boot/20240411160527.835767-1-caleb.conno...@linaro.org
---
 drivers/usb/dwc3/core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 96e850b7170f..db045f5822d4 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -594,9 +594,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
int ret;
 
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
/* This should read as U3 followed by revision number */
-   if ((reg & DWC3_GSNPSID_MASK) != 0x5533) {
+   if ((reg & DWC3_GSNPSID_MASK) != 0x5533 &&
+   (reg & DWC3_GSNPSID_MASK) != 0x3331) {
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
ret = -ENODEV;
goto err0;
}
-- 
2.44.0

Re: [PATCH] sysreset: add Qualcomm PSHOLD reset driver


Hi Robert,

On 23/04/2024 13:33, Robert Marko wrote:

Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD
(Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff.

Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based
on the upstream Linux one, it is DT compatible as well.


Thanks for the patch.


Signed-off-by: Robert Marko 
---
  drivers/sysreset/Kconfig   |  6 +++
  drivers/sysreset/Makefile  |  1 +
  drivers/sysreset/sysreset_msm-pshold.c | 56 ++
  3 files changed, 63 insertions(+)
  create mode 100644 drivers/sysreset/sysreset_msm-pshold.c

diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 49c0787b26..30ff9e576d 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -235,6 +235,12 @@ config SYSRESET_RAA215300
help
  Add support for the system reboot via the Renesas RAA215300 PMIC.
  
+config SYSRESET_MSM_PSHOLD


For the sake of consistency, please use QCOM instead of MSM (ditto for 
the driver).


With that,

Reviewed-by: Caleb Connolly 

+   bool "Support sysreset for Qualcomm SoCs via PSHOLD"
+   depends on ARCH_IPQ40XX
+   help
+ Add support for the system reboot on Qualcomm SoCs via PSHOLD.
+
  endif
  
  endmenu

diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index e0e732205d..da61dca8e2 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -28,4 +28,5 @@ obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
  obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
  obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
  obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
+obj-$(CONFIG_SYSRESET_MSM_PSHOLD) += sysreset_msm-pshold.o
  obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_msm-pshold.c 
b/drivers/sysreset/sysreset_msm-pshold.c
new file mode 100644
index 00..d25a412954
--- /dev/null
+++ b/drivers/sysreset/sysreset_msm-pshold.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm PSHOLD reset driver
+ *
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko 
+ * Based on the Linux msm-poweroff driver.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct msm_pshold_priv {
+   phys_addr_t base;
+};
+
+static int msm_pshold_request(struct udevice *dev, enum sysreset_t type)
+{
+   struct msm_pshold_priv *priv = dev_get_priv(dev);
+
+   writel(0, priv->base);
+   mdelay(1);
+
+   return 0;
+}
+
+static struct sysreset_ops msm_pshold_ops = {
+   .request = msm_pshold_request,
+};
+
+static int msm_pshold_probe(struct udevice *dev)
+{
+   struct msm_pshold_priv *priv = dev_get_priv(dev);
+
+   priv->base = dev_read_addr(dev);
+   return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const struct udevice_id msm_pshold_ids[] = {
+   { .compatible = "qcom,pshold", },
+   { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(msm_pshold) = {
+   .name   = "msm_pshold",
+   .id = UCLASS_SYSRESET,
+   .of_match   = msm_pshold_ids,
+   .probe  = msm_pshold_probe,
+   .priv_auto  = sizeof(struct msm_pshold_priv),
+   .ops= _pshold_ops,
+};


--
// Caleb (they/them)

Re: [PATCH] arm: mach-k3: am642: Fix reset for workaround errata ID i2331

2024-04-23 Thread Wadim Egorov





Am 18.04.24 um 19:58 schrieb Andrew Davis:

To workaround an issue in AM642 we reset the SoC in early boot. For that
we first probed the sysreset driver by calling uclass_get_device(). The
ti-sci sysreset driver is now probed during the ti-sci firmware probe.
Update this call to probe the firmware driver which will then probe
the sysreset driver allowing do_reset() to again function as expected.

Reported-by: Jonathan Humphreys 
Fixes: fc5d40283483 ("firmware: ti_sci: Bind sysreset driver when enabled")
Signed-off-by: Andrew Davis 


Tested-by: Wadim Egorov 

on phycore-am64x


---
  arch/arm/mach-k3/am642_init.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index ddf47ef0a9b..80c3cb3479f 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -226,7 +226,7 @@ void board_init_f(ulong dummy)
 * The warm reset realigns internal clocks and prevents the lockup from
 * happening.
 */
-   ret = uclass_first_device_err(UCLASS_SYSRESET, );
+   ret = uclass_get_device_by_driver(UCLASS_FIRMWARE, DM_DRIVER_GET(ti_sci), 
);
if (ret)
printf("\n%s:uclass device error [%d]\n",__func__,ret);

[PULL] Please pull qcom/qcom-main

Overshot the -rc1 deadline, but I hope these can still make in for 2024.07.

Support is added for 5 new Qualcomm SoCs:

* QCM2290 and SM6115 are low and mid range SoCs used on the RB1 and RB2
  respectively. SM6115 is also used in some mid-range smartphones/tablets.
  Initial support includes buttons and USB (host and gadget).
* SM8250 is a flagship SoC from 2020 used on the RB5, as well as many flagship
  smartphones. The board can boot to a U-Boot prompt, but is missing regulators
  necessary for USB support.
* SM8550, and SM8650 are flagship mobile SoCs from 2023 and 2024
  respectively. Found on many high end smartphones.

In addition:

* Support is added for the Schneider HMIBSC board.
* mach-snapdragon switches to OF_UPSTREAM
* IPQ40xx gets several regressions fixed and some overall cleanup.
* The MSM serial driver gains the ability to generate the bit-clock
  automatically, no longer relying on a custom DT property.
* The Qualcomm SMMU driver gets a generic compatible (so per-SoC compatibles
  don't need to be added).
* Support for the GENI I2C controller is added.
* The qcom SPMI driver has SPMI v5 support fixed, and v7 support added.
* The qcom sdhci driver gets some fixes for SDCC v5 support.
* SDM845 gains sdcard support
* Support is added for the Synopsys eUSB2 PHY driver (used on SM8550 and SM8650)
* SYS_INIT_SP_BSS_OFFSET is set to 1.5M to give us more space for FDTs.
* RB2 gets a work-around to fix the USB dr_mode property before booting Linux.

---

The following changes since commit 38ea74d6d5c05224acdb03f799897c1bdd56f8cc:

  Prepare v2024.07-rc1 (2024-04-22 15:10:21 -0600)

are available in the Git repository at:

  g...@source.denx.de:u-boot/custodians/u-boot-snapdragon.git qcom-main

for you to fetch changes up to ad12acd7a8f5aeea5816d5c2fc37c205c403eee0:

  configs: qcom_defconfig: enable GENI I2C Driver (2024-04-23 13:29:32 +0200)


Caleb Connolly (32):
  pinctrl: qcom: add qcm2290 pinctrl driver
  pinctrl: qcom: add sm6115 pinctrl driver
  pinctrl: qcom: add sm8250 pinctrl driver
  qcom_defconfig: enable pinctrl for new qcm2290/sm6115/sm8250
  clk/qcom: add driver for qcm2290 GCC
  clk/qcom: add driver for sm6115 GCC
  clk/qcom: add driver for sm8250 GCC
  qcom_defconfig: enable clocks for qcm2290/sm6115/sm8250
  mmc: msm_sdhci: correct vendor_spec_cap0 register for v5
  mmc: msm_sdhci: use modern DT handling
  mmc: msm_sdhci: print core version
  mmc: msm_sdhci: use a more sensible default clock rate
  clk/qcom: sdm845: enable SDCC2 core clock
  pinctrl: qcom: sdm845: add special pin names
  dts: sdm845-db845c-u-boot: adjust MMC clocks
  MAINTAINERS: add Qualcomm mailing list
  mmc: msm_sdhci: fix vendor_spec_cap0 registers
  clk/qcom: apq8016: return valid rate when setting UART clock
  clk/qcom: ipq4019: return valid rate when setting UART clock
  serial: msm: calculate bit clock divider
  mach-snapdragon: use OF_UPSTREAM
  arm: dts: drop qcom dts files
  qcom_defconfig: set SYS_INIT_SP_BSS_OFFSET
  gpio: qcom_pmic: add pm6125
  gpio: qcom_pmic: add pm8150l
  iommu: qcom-smmu: add qcom generic compatible
  phy: qcom: snps-femto-v2: drop clocks
  arm: dts: qrb4210-rb2-u-boot: add u-boot fixups
  mach-snapdragon: implement ft_board_setup() for USB role selection
  qcom_defconfig: enable OF_BOARD_SETUP
  qcom_defconfig: define safe default SYS_LOAD_ADDR
  qcom_defconfig: generate SMBIOS tables

Neil Armstrong (17):
  phy: qcom: add Synopsys eUSB2 PHY driver
  qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver
  pinctrl: qcom: Add SM8550 pinctrl driver
  pinctrl: qcom: Add SM8650 pinctrl driver
  qcom_defconfig: enable SM8550 & SM8650 pinctrl driver
  gpio: qcom_pmic_gpio: add support for pm8550-gpio
  button: qcom-pmic: move node name checks to btn_data struct
  button: qcom-pmic: add support for pmk8350 button configs
  clk: qcom: Add SM8550 clock driver
  clk: qcom: Add SM8650 clock driver
  qcom_defconfig: enable SM8550 & SM8650 clock driver
  spmi: msm: fix version 5 support
  spmi: msm: properly format command
  spmi: msm: handle peripheral ownership
  spmi: msm: support controller version 7
  i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
  configs: qcom_defconfig: enable GENI I2C Driver

Robert Marko (8):
  serial: allow selecting MSM debug UART with ARCH_IPQ40XX
  serial: msm_serial: remove .clk_rate from debug UART
  arm: mach-ipq40xx: dont select SMEM by default
  pinctrl: qcom: allow selecting with ARCH_IPQ40XX
  mach-ipq40xx: import GPIO header from mach-snapgradon
  pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS
  pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC
  pinctrl: qcom: ipq4019: support all pin functions

Sumit Garg (8):

Re: [PATCH v2 1/3] net: eth-uclass: Introduce NET_PREFER_ROM_MAC_ADDR


On 4/23/24 3:35 PM, Detlev Casanova wrote:

On Monday, April 22, 2024 3:47:21 P.M. EDT Marek Vasut wrote:

On 4/22/24 3:56 PM, Detlev Casanova wrote:

On some boards, a MAC address is set based on the CPU ID or other
information. This is usually done in the misc_init_r() function.

This becomes a problem for net devices that are probed after the call to
misc_init_r(), for example, when the ethernet is on a PCI port, which
needs to be enumerated.

In this case, misc_init_r() will set the ethaddr variable, then, when
the ethernet device is probed, if it has a ROM address, u-boot will warn
about a MAC address mismatch and use the misc_init_r() address instead
of the one in ROM.

The operating system later will most likely use the ROM MAC address,
which can be confusing.

To avoid that, this commit introduces NET_PREFER_ROM_MAC_ADDR that can
be set for boards that have such an interface.

Signed-off-by: Detlev Casanova 


Won't the system pick ROM MAC if $ethaddr is not set ?


Yes, and in the case of rockchip, misc_init_r() will set an $ethaddr based on
the cpuid, which makes the eth driver use that instead of the ROM one.


Shouldn't the rockchip misc_init_r be fixed then ?

Re: [PATCH v2 1/3] net: eth-uclass: Introduce NET_PREFER_ROM_MAC_ADDR

2024-04-23 Thread Detlev Casanova

On Monday, April 22, 2024 3:47:21 P.M. EDT Marek Vasut wrote:
> On 4/22/24 3:56 PM, Detlev Casanova wrote:
> > On some boards, a MAC address is set based on the CPU ID or other
> > information. This is usually done in the misc_init_r() function.
> > 
> > This becomes a problem for net devices that are probed after the call to
> > misc_init_r(), for example, when the ethernet is on a PCI port, which
> > needs to be enumerated.
> > 
> > In this case, misc_init_r() will set the ethaddr variable, then, when
> > the ethernet device is probed, if it has a ROM address, u-boot will warn
> > about a MAC address mismatch and use the misc_init_r() address instead
> > of the one in ROM.
> > 
> > The operating system later will most likely use the ROM MAC address,
> > which can be confusing.
> > 
> > To avoid that, this commit introduces NET_PREFER_ROM_MAC_ADDR that can
> > be set for boards that have such an interface.
> > 
> > Signed-off-by: Detlev Casanova 
> 
> Won't the system pick ROM MAC if $ethaddr is not set ?

Yes, and in the case of rockchip, misc_init_r() will set an $ethaddr based on 
the cpuid, which makes the eth driver use that instead of the ROM one.


signature.asc
Description: This is a digitally signed message part.

Re: [PATCH v2] usb: cdns3: gadget.c: Set fast access bit


On 4/23/24 10:24 AM, Ravi Gunasekaran wrote:

From: Aswath Govindraju 

When the device port is in a low power state [U3/L2/Not Connected],
accesses to usb device registers may take a long time. This could lead to
potential core hang when the controller registers are accessed after the
port is disabled by setting DEVDS field. Setting the fast register access
bit ensures that the PHY clock is keeping up in active state.

Therefore, set fast access bit to ensure the accesses to device registers
are quick even in low power states.

Signed-off-by: Aswath Govindraju 
Signed-off-by: Ravi Gunasekaran 
Reviewed-by: Roger Quadros 
---
v1 was posted and was reviewed as well. But it did not get merged.
This change is present in upstream linux kernel as well.
Upstream Linux kernel commit: b5148d946f45 ("usb: cdns3: gadget: set fast access 
bit")


This commit ^ should be mentioned in the commit message.

With that fixed:

Reviewed-by: Marek Vasut 

Thanks !

Re: [RFC PATCH 1/1] net: dwc_eth_qos: mdio: Implement clause 45


On 4/23/24 10:51 AM, Philip Oberfichtner wrote:

Bevor this commit, only clause 22 access was possible. After this commit,
clause 45 direct access will available as well.

Note that there is a slight change of behavior: Before this commit, the
C45E bit was set to whatever value was left in the register from the
previous access. After this commit, we adopt the common practice of
discerning C45 from C22 using the devad argument.

Signed-off-by: Philip Oberfichtner 
---

Notes:
 This patch is labeled RFC as there is a slight change of behavior (see
 commit message). I'm not sure in fact if this solution works for
 everybody - this is up for discussion!
 
 My implementation is tested on an Intel Elkhart lake SOC. Driver code

 for dwc_eth_qos_intel coming soon in a separate patch series.

  drivers/net/dwc_eth_qos.c | 66 ++-
  drivers/net/dwc_eth_qos.h |  1 +
  2 files changed, 45 insertions(+), 22 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 86d989e244..64a9bff6bb 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -162,6 +162,25 @@ static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
 100, true);
  }
  
+/* Bitmask common for mdio_read and mdio_write */

+#define EQOS_MDIO_BITFIELD(pa, rda, cr) \
+   (pa  << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT)  | \


Parenthesis around (pa) are missing, DTTO for the rest of this.

However, better use FIELD_GET/FIELD_PREP macros instead.

[...]

Re: RISC-V u-boot unable to boot QEMU using '-cpu max'

2024-04-23 Thread Daniel Henrique Barboza





On 4/23/24 09:41, Conor Dooley wrote:

On Tue, Apr 23, 2024 at 01:34:42PM +0800, Leo Liang wrote:

On Mon, Apr 22, 2024 at 04:43:59PM -0300, Daniel Henrique Barboza wrote:

[EXTERNAL MAIL]

Hi,

In QEMU we have a 'max' type CPU that implements (almost) all extensions that 
QEMU
is able to emulate. Recently, in QEMU commit 249e0905d05, we bumped the 
extensions
for this CPU.

And after this commit this CPU is now unable to boot a guest using upstream
u-boot. Here's the error being thrown:

qemu-system-riscv64 \
 -machine virt -nographic -m 8G -smp 8 \
 -cpu max -kernel uboot.elf (...)
(...)

initcall sequence 8027c3e8 failed at call 8021259e (err=-28)
### ERROR ### Please RESET the board ###


I can get the guest to boot if I disable the following extensions from the 
'max' CPU:

  -cpu max,zfbfmin=false,zvfbfmin=false,zvfbfwma=false

Due to QEMU extension dependencies I'm not able to disable these individually. 
What I can
say is that u-boot isn't playing ball to at least one of them.

Is this an u-boot bug? Up to this point I was assuming that u-boot would 
silently ignore
hart extensions that it doesn't support.


Hi Daniel,

Which u-boot version are you using?

I think this issue is fixed by the following patch set sent by Conor.

f39b1b77d8 riscv: support extension probing using riscv, isa-extensions
b90edde701 riscv: don't read riscv, isa in the riscv cpu's get_desc()

I've tested and can reproduce the issue you mentioned if these two patches are 
reverted.

Could you try with the lastest u-boot master branch again?


For reference, my testing commands are as follows:
1. cd ${u-boot} && make qemu-riscv64_defconfig && make -j`nproc`
2. ./${qemu}/build/qemu-system-riscv64 -nographic -machine virt -cpu max -bios 
u-boot.bin -m 8G -smp 8

- u-boot branch (commit): master (38ea74d6d5c0 "Prepare v2024.07-rc1")
- qemu branch (commit): master (62dbe54c24db "Update version for v9.0.0-rc4 
release")


I'll go take a look at this, it's possible that my patches only hide the
problem due to the new property being prioritised.



Don't bother. I just checked with most recent u-boot master and I can't 
reproduce the
problem, as Leo said.

I apologize for the noise. I failed to fetch the latest upstream and do a last
test before posting it here.

We were discussing here and there about disabling these extensions in the 'max'
CPU in QEMU if u-boot wasn't able to handle them. I'm happy to see that u-boot
is now able to do so and we can keep the 'max' CPU as is.


Thanks for the help,

Daniel

Re: RISC-V u-boot unable to boot QEMU using '-cpu max'

2024-04-23 Thread Conor Dooley

On Tue, Apr 23, 2024 at 01:34:42PM +0800, Leo Liang wrote:
> On Mon, Apr 22, 2024 at 04:43:59PM -0300, Daniel Henrique Barboza wrote:
> > [EXTERNAL MAIL]
> > 
> > Hi,
> > 
> > In QEMU we have a 'max' type CPU that implements (almost) all extensions 
> > that QEMU
> > is able to emulate. Recently, in QEMU commit 249e0905d05, we bumped the 
> > extensions
> > for this CPU.
> > 
> > And after this commit this CPU is now unable to boot a guest using upstream
> > u-boot. Here's the error being thrown:
> > 
> > qemu-system-riscv64 \
> > -machine virt -nographic -m 8G -smp 8 \
> > -cpu max -kernel uboot.elf (...)
> > (...)
> > 
> > initcall sequence 8027c3e8 failed at call 8021259e (err=-28)
> > ### ERROR ### Please RESET the board ###
> > 
> > 
> > I can get the guest to boot if I disable the following extensions from the 
> > 'max' CPU:
> > 
> >  -cpu max,zfbfmin=false,zvfbfmin=false,zvfbfwma=false
> > 
> > Due to QEMU extension dependencies I'm not able to disable these 
> > individually. What I can
> > say is that u-boot isn't playing ball to at least one of them.
> > 
> > Is this an u-boot bug? Up to this point I was assuming that u-boot would 
> > silently ignore
> > hart extensions that it doesn't support.
> 
> Hi Daniel,
> 
> Which u-boot version are you using?
> 
> I think this issue is fixed by the following patch set sent by Conor.
> 
>   f39b1b77d8 riscv: support extension probing using riscv, isa-extensions
>   b90edde701 riscv: don't read riscv, isa in the riscv cpu's get_desc()
> 
> I've tested and can reproduce the issue you mentioned if these two patches 
> are reverted.
> 
> Could you try with the lastest u-boot master branch again?
> 
> 
> For reference, my testing commands are as follows:
> 1. cd ${u-boot} && make qemu-riscv64_defconfig && make -j`nproc`
> 2. ./${qemu}/build/qemu-system-riscv64 -nographic -machine virt -cpu max 
> -bios u-boot.bin -m 8G -smp 8
> 
> - u-boot branch (commit): master (38ea74d6d5c0 "Prepare v2024.07-rc1")
> - qemu branch (commit): master (62dbe54c24db "Update version for v9.0.0-rc4 
> release")

I'll go take a look at this, it's possible that my patches only hide the
problem due to the new property being prioritised.


signature.asc
Description: PGP signature

[PATCH v2] rockchip: rv1108: Convert to OF_UPSTREAM

2024-04-23 Thread Fabio Estevam

Instead of using the local rv1108 devicetree copies from U-Boot,
let's convert the rv1108 boards to OF_UPSTREAM so that the upstream kernel
devicetrees can be used instead.

Tested on a rv1108-elgin-r1 board.

Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Fixed typo in commit log.

 arch/arm/dts/rv1108-elgin-r1.dts |  59 
 arch/arm/dts/rv1108-evb.dts  |  79 -
 arch/arm/dts/rv1108.dtsi | 581 ---
 arch/arm/mach-rockchip/Kconfig   |   1 +
 configs/elgin-rv1108_defconfig   |   2 +-
 configs/evb-rv1108_defconfig |   2 +-
 6 files changed, 3 insertions(+), 721 deletions(-)
 delete mode 100644 arch/arm/dts/rv1108-elgin-r1.dts
 delete mode 100644 arch/arm/dts/rv1108-evb.dts
 delete mode 100644 arch/arm/dts/rv1108.dtsi

diff --git a/arch/arm/dts/rv1108-elgin-r1.dts b/arch/arm/dts/rv1108-elgin-r1.dts
deleted file mode 100644
index 83e8b3183847..
--- a/arch/arm/dts/rv1108-elgin-r1.dts
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rv1108.dtsi"
-
-/ {
-   model = "Elgin RV1108 R1 board";
-   compatible = "elgin,rv1108-elgin", "rockchip,rv1108";
-
-   memory@6000 {
-   device_type = "memory";
-   reg = <0x6000 0x0800>;
-   };
-
-   chosen {
-   stdout-path = "serial2:150n8";
-   };
-};
-
- {
-   pinctrl-names = "default";
-   pinctrl-0 = <_clk _cmd _bus8>;
-   bus-width = <8>;
-   cap-mmc-highspeed;
-   disable-wp;
-   non-removable;
-   status = "okay";
-};
-
- {
-   status = "okay";
-
-   u2phy_otg: otg-port {
-   status = "okay";
-   };
-};
-
- {
-   pinctrl-names = "default";
-   pinctrl-0 = <_xfer_pullup>;
-   status = "okay";
-};
-
-_otg {
-   status = "okay";
-};
-
- {
-   uart2m0 {
-   uart2m0_xfer_pullup: uart2m0-xfer-pullup {
-   rockchip,pins = <2 RK_PD2 RK_FUNC_1 
_pull_up_drv_8ma>,
-   <2 RK_PD1 RK_FUNC_1 
_pull_up_drv_8ma>;
-   };
-   };
-};
diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts
deleted file mode 100644
index c91776bc106e..
--- a/arch/arm/dts/rv1108-evb.dts
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rv1108.dtsi"
-
-/ {
-   model = "Rockchip RV1108 Evaluation board";
-   compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
-
-   memory@6000 {
-   device_type = "memory";
-   reg = <0x6000 0x0800>;
-   };
-
-   chosen {
-   stdout-path = "serial2:150n8";
-   };
-
-   vcc5v0_otg: vcc5v0-otg-drv {
-   compatible = "regulator-fixed";
-   enable-active-high;
-   regulator-name = "vcc5v0_otg";
-   gpio = < RK_PB0 GPIO_ACTIVE_HIGH>;
-   regulator-min-microvolt = <500>;
-   regulator-max-microvolt = <500>;
-   };
-};
-
- {
-   status = "okay";
-   clock_in_out = <0>;
-   snps,reset-active-low;
-   snps,reset-delays-us = <0 1 100>;
-   snps,reset-gpio = < RK_PC1 GPIO_ACTIVE_LOW>;
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-   flash@0 {
-   compatible = "gd25q256","jedec,spi-nor";
-   reg = <0>;
-   spi-tx-bus-width = <1>;
-   spi-rx-bus-width = <1>;
-   spi-max-frequency = <9600>;
-   };
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
-_otg {
-   vbus-supply = <_otg>;
-   status = "okay";
-};
-
-_host_ehci {
-   status = "okay";
-};
-
-_host_ohci {
-   status = "okay";
-};
diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
deleted file mode 100644
index 215d88522587..
--- a/arch/arm/dts/rv1108.dtsi
+++ /dev/null
@@ -1,581 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-/ {
-   #address-cells = <1>;
-   #size-cells = <1>;
-
-   compatible = "rockchip,rv1108";
-
-   interrupt-parent = <>;
-
-   aliases {
-   serial0 = 
-   serial1 = 
-   serial2 = 
-   spi0= 
-   };
-
-   cpus {
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   cpu0: cpu@f00 {
-   device_type = "cpu";
-   compatible = "arm,cortex-a7";
-   reg = <0xf00>;
-   };
-   };
-
-   arm-pmu {
-   compatible = "arm,cortex-a7-pmu";
-   interrupts = ;
-   };
-
-

[PATCH] rockchip: rv1108: Convert to OF_UPSTREAM

2024-04-23 Thread Fabio Estevam

Instead of using the local rv1108 devicetree copies from U-Boot,
let's convert the rv11008 board to OF_UPSTREAM so that the upstream kernel
devicetrees can be used instead.

Tested on a rv1108-elgin-r1 board.

Signed-off-by: Fabio Estevam 
---
 arch/arm/dts/rv1108-elgin-r1.dts |  59 
 arch/arm/dts/rv1108-evb.dts  |  79 -
 arch/arm/dts/rv1108.dtsi | 581 ---
 arch/arm/mach-rockchip/Kconfig   |   1 +
 configs/elgin-rv1108_defconfig   |   2 +-
 configs/evb-rv1108_defconfig |   2 +-
 6 files changed, 3 insertions(+), 721 deletions(-)
 delete mode 100644 arch/arm/dts/rv1108-elgin-r1.dts
 delete mode 100644 arch/arm/dts/rv1108-evb.dts
 delete mode 100644 arch/arm/dts/rv1108.dtsi

diff --git a/arch/arm/dts/rv1108-elgin-r1.dts b/arch/arm/dts/rv1108-elgin-r1.dts
deleted file mode 100644
index 83e8b3183847..
--- a/arch/arm/dts/rv1108-elgin-r1.dts
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rv1108.dtsi"
-
-/ {
-   model = "Elgin RV1108 R1 board";
-   compatible = "elgin,rv1108-elgin", "rockchip,rv1108";
-
-   memory@6000 {
-   device_type = "memory";
-   reg = <0x6000 0x0800>;
-   };
-
-   chosen {
-   stdout-path = "serial2:150n8";
-   };
-};
-
- {
-   pinctrl-names = "default";
-   pinctrl-0 = <_clk _cmd _bus8>;
-   bus-width = <8>;
-   cap-mmc-highspeed;
-   disable-wp;
-   non-removable;
-   status = "okay";
-};
-
- {
-   status = "okay";
-
-   u2phy_otg: otg-port {
-   status = "okay";
-   };
-};
-
- {
-   pinctrl-names = "default";
-   pinctrl-0 = <_xfer_pullup>;
-   status = "okay";
-};
-
-_otg {
-   status = "okay";
-};
-
- {
-   uart2m0 {
-   uart2m0_xfer_pullup: uart2m0-xfer-pullup {
-   rockchip,pins = <2 RK_PD2 RK_FUNC_1 
_pull_up_drv_8ma>,
-   <2 RK_PD1 RK_FUNC_1 
_pull_up_drv_8ma>;
-   };
-   };
-};
diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts
deleted file mode 100644
index c91776bc106e..
--- a/arch/arm/dts/rv1108-evb.dts
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rv1108.dtsi"
-
-/ {
-   model = "Rockchip RV1108 Evaluation board";
-   compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
-
-   memory@6000 {
-   device_type = "memory";
-   reg = <0x6000 0x0800>;
-   };
-
-   chosen {
-   stdout-path = "serial2:150n8";
-   };
-
-   vcc5v0_otg: vcc5v0-otg-drv {
-   compatible = "regulator-fixed";
-   enable-active-high;
-   regulator-name = "vcc5v0_otg";
-   gpio = < RK_PB0 GPIO_ACTIVE_HIGH>;
-   regulator-min-microvolt = <500>;
-   regulator-max-microvolt = <500>;
-   };
-};
-
- {
-   status = "okay";
-   clock_in_out = <0>;
-   snps,reset-active-low;
-   snps,reset-delays-us = <0 1 100>;
-   snps,reset-gpio = < RK_PC1 GPIO_ACTIVE_LOW>;
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-   flash@0 {
-   compatible = "gd25q256","jedec,spi-nor";
-   reg = <0>;
-   spi-tx-bus-width = <1>;
-   spi-rx-bus-width = <1>;
-   spi-max-frequency = <9600>;
-   };
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
-_otg {
-   vbus-supply = <_otg>;
-   status = "okay";
-};
-
-_host_ehci {
-   status = "okay";
-};
-
-_host_ohci {
-   status = "okay";
-};
diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
deleted file mode 100644
index 215d88522587..
--- a/arch/arm/dts/rv1108.dtsi
+++ /dev/null
@@ -1,581 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-/ {
-   #address-cells = <1>;
-   #size-cells = <1>;
-
-   compatible = "rockchip,rv1108";
-
-   interrupt-parent = <>;
-
-   aliases {
-   serial0 = 
-   serial1 = 
-   serial2 = 
-   spi0= 
-   };
-
-   cpus {
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   cpu0: cpu@f00 {
-   device_type = "cpu";
-   compatible = "arm,cortex-a7";
-   reg = <0xf00>;
-   };
-   };
-
-   arm-pmu {
-   compatible = "arm,cortex-a7-pmu";
-   interrupts = ;
-   };
-
-   timer {
-   compatible =

Re: [PATCH v4 0/7] Add SE HMBSC board support

2024-04-23 Thread Sumit Garg

On Tue, 23 Apr 2024 at 17:29, Caleb Connolly  wrote:
>
> Applied, thanks.

Thanks.

>
> (b4 didn't seem to detect this series properly, hence the manual mail).
>

Switching my workflow to b4 is on my ToDo list. I hope to do it sooner
rather than later.

-Sumit

> On 12/04/2024 11:54, Sumit Garg wrote:
> > SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major
> > difference from db410c is serial port where HMIBSC board uses UART1 as
> > the debug console with an RS232 port, patch #2 - #5 adds corresponding
> > driver support.
> >
> > Patch #6 adds main HMIBSC board specific bits, features:
> > - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
> > - 2GiB RAM
> > - 64GiB eMMC, SD slot
> > - WiFi and Bluetooth
> > - 2x Host, 1x Device USB port
> > - HDMI
> > - Discrete TPM2 chip over SPI
> >
> > Features enabled in U-Boot:
> > - RAUC updates (refer [2] for more details)
> > - Environment protection
> > - USB based ethernet adaptors
> >
> > Feedback is very much welcome.
> >
> > Changes in v4:
> > - Rebased on top of qcom-main [4].
> > - Split out board DTS patch as #6.
> > - Convert to text based environment as hmibsc.env.
> > - MMC regression has been reported for qcom-main branch here [5].
> > - Collected further review tag.
> >
> > Changes in v3:
> > - Rebased on top of qcom-next [1].
> > - Collected some review tags.
> > - Incorporated misc. comments from Caleb and Stephen.
> > - Split patch#4 as requested.
> > - Linux HMIBSC board DTS has already been reviewed here [3], I have
> >incorporated that for U-Boot too.
> >
> > Changes in v2:
> > - Rebased on top on qcom-next [1].
> > - Added patch#1 as a fix for generic qcom board support.
> > - Added patch#4 to enable driving GPIO pins based on pinctrl
> >configuration. This replaces the custom GPIO configuration.
> > - Added proper DTS file for HMIBSC board based on Linux DT pattern.
> > - Merged board support patches into a single patch#5.
> >
> > [1] 
> > https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-next?ref_type=heads
> > [2] https://rauc.readthedocs.io/en/latest/
> > [3] 
> > https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.g...@linaro.org/
> > [4] 
> > https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-main/?ref_type=heads
> > [5] 
> > https://lore.kernel.org/all/cafa6wyo+3vroudfuvh390taviqx8pmqroqdtsn0yu6bd5yy...@mail.gmail.com/
> >
> > Sumit Garg (7):
> >qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default
> >apq8016: Add support for UART1 clocks and pinmux
> >serial_msm: Enable RS232 flow control
> >pinctrl: qcom: Add support for driving GPIO pins output
> >pinctrl: qcom: apq8016: Add GPIO pinctrl function
> >arm: dts: qcom: Add Schneider HMIBSC board dts
> >board: add support for Schneider HMIBSC board
> >
> >   arch/arm/Kconfig  |   2 +-
> >   arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++
> >   board/schneider/hmibsc/MAINTAINERS|   6 +
> >   board/schneider/hmibsc/hmibsc.env |  40 ++
> >   configs/hmibsc_defconfig  |  87 
> >   doc/board/index.rst   |   1 +
> >   doc/board/schneider/hmibsc.rst|  45 ++
> >   doc/board/schneider/index.rst |   9 +
> >   drivers/clk/qcom/clock-apq8016.c  |  38 +-
> >   drivers/pinctrl/qcom/pinctrl-apq8016.c|   2 +
> >   drivers/pinctrl/qcom/pinctrl-qcom.c   |  25 +-
> >   drivers/serial/serial_msm.c   |  24 +-
> >   include/configs/hmibsc.h  |  16 +
> >   13 files changed, 760 insertions(+), 26 deletions(-)
> >   create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts
> >   create mode 100644 board/schneider/hmibsc/MAINTAINERS
> >   create mode 100644 board/schneider/hmibsc/hmibsc.env
> >   create mode 100644 configs/hmibsc_defconfig
> >   create mode 100644 doc/board/schneider/hmibsc.rst
> >   create mode 100644 doc/board/schneider/index.rst
> >   create mode 100644 include/configs/hmibsc.h
> >
>
> --
> // Caleb (they/them)

Re: [PATCH v2 3/3] board: starfive: Call spl_dram_init() for DRAM initialization

2024-04-23 Thread Heinrich Schuchardt


On 23.04.24 11:14, lukas.funke-...@weidmueller.com wrote:

From: Lukas Funke 

Call spl_dram_init() since this is commonly used for dram initialization
in u-boot.

Signed-off-by: Lukas Funke 
---

Changes in v2:
  - capitalized acronym DRAM

  board/starfive/visionfive2/spl.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 45848db6d8..ca61b5be22 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -285,9 +285,9 @@ int spl_board_init_f(void)

jh7110_jtag_init();

-   ret = spl_soc_init();
+   ret = spl_dram_init();


We want to be able to use git bisect. This requires that the source
builds after each individual patch.

This change must be in the same patch in which you rename the function
for the VisionFive 2.

Please, resubmit your series with two patches: one for SiFive, one for
StarFive.

Best regards

Heinrich


if (ret) {
-   debug("JH7110 SPL init failed: %d\n", ret);
+   debug("JH7110 DRAM init failed: %d\n", ret);
return ret;
}

Re: [PATCH v3 02/19] board: am64x: Define capsule update firmware info

2024-04-23 Thread Roger Quadros




On 19/04/2024 23:56, Jonathan Humphreys wrote:
> Define the firmware components updatable via EFI capsule update, including
> defining capsule GUIDs for the various firmware components for the AM64x SK.
> 
> Signed-off-by: Jonathan Humphreys 
> ---
>  board/ti/am64x/evm.c| 33 +
>  include/configs/am64x_evm.h | 24 
>  2 files changed, 57 insertions(+)
> 
> diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
> index b8de69da06c..83df75a6911 100644
> --- a/board/ti/am64x/evm.c
> +++ b/board/ti/am64x/evm.c
> @@ -7,6 +7,7 @@
>   *
>   */
>  
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -27,6 +28,38 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)

Checkpatch warns:

WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where 
possible
#31: FILE: board/ti/am64x/evm.c:31:
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)


How about we drop the #if here and instead see possible solution below.

> +struct efi_fw_image fw_images[] = {
> + {
> + .image_type_id = AM64X_SK_TIBOOT3_IMAGE_GUID,
> + .fw_name = u"AM64X_SK_TIBOOT3",
> + .image_index = 1,
> + },
> + {
> + .image_type_id = AM64X_SK_SPL_IMAGE_GUID,
> + .fw_name = u"AM64X_SK_SPL",
> + .image_index = 2,
> + },
> + {
> + .image_type_id = AM64X_SK_UBOOT_IMAGE_GUID,
> + .fw_name = u"AM64X_SK_UBOOT",
> + .image_index = 3,
> + }
> +};
> +
> +struct efi_capsule_update_info update_info = {
> + .dfu_string = "sf 0:0=tiboot3.bin raw 0 10;tispl.bin raw 10 
> 20;u-boot.img raw 30 40",
> + .num_images = ARRAY_SIZE(fw_images),
> + .images = fw_images,
> +};
> +
> +void set_dfu_alt_info(char *interface, char *devstr)
> +{

set the environment variable only if relevant config is enabled.

if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))

> + env_set("dfu_alt_info", update_info.dfu_string);

> +}
> +
> +#endif /* EFI_HAVE_CAPSULE_SUPPORT */
> +
>  int board_init(void)
>  {
>   return 0;
> diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
> index f9f8c7bc2f6..9db83621ea8 100644
> --- a/include/configs/am64x_evm.h
> +++ b/include/configs/am64x_evm.h
> @@ -9,6 +9,30 @@
>  #ifndef __CONFIG_AM642_EVM_H
>  #define __CONFIG_AM642_EVM_H
>  
> +/**
> + * define AM64X_SK_TIBOOT3_IMAGE_GUID - firmware GUID for AM64X sk 
> tiboot3.bin
> + * define AM64X_SK_SPL_IMAGE_GUID - firmware GUID for AM64X sk SPL
> + * define AM64X_SK_UBOOT_IMAGE_GUID   - firmware GUID for AM64X sk UBOOT
> + *
> + * These GUIDs are used in capsules updates to identify the corresponding
> + * firmware object.
> + *
> + * Board developers using this as a starting reference should
> + * define their own GUIDs to ensure that firmware repositories (like
> + * LVFS) do not confuse them.
> + */
> +#define AM64X_SK_TIBOOT3_IMAGE_GUID \
> + EFI_GUID(0xede0a0d5, 0x9116, 0x4bfb, 0xaa, 0x54, \
> + 0x09, 0xe9, 0x7b, 0x5a, 0xfe, 0x1a)
> +
> +#define AM64X_SK_SPL_IMAGE_GUID \
> + EFI_GUID(0x77678f5c, 0x64d4, 0x4910, 0xad, 0x75, \
> + 0x52, 0xc9, 0xd9, 0x5c, 0xdb, 0x1d)
> +
> +#define AM64X_SK_UBOOT_IMAGE_GUID \
> + EFI_GUID(0xc6ad43a9, 0x7d31, 0x4f5d, 0x83, 0xe9, \
> + 0xb8, 0xef, 0xec, 0xae, 0x05, 0xbf)
> +
>  /* Now for the remaining common defines */
>  #include 
>  

-- 
cheers,
-roger

Re: [PATCH v3 03/19] configs: am64x: Enable EFI capsule update

2024-04-23 Thread Roger Quadros

Checkpatch warns:

WARNING: Missing commit description - Add an appropriate one


On 19/04/2024 23:56, Jonathan Humphreys wrote:
> Signed-off-by: Jonathan Humphreys 
> ---
>  configs/am64x_evm_a53_defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
> index e000549d6d0..c9bdd7b54cc 100644
> --- a/configs/am64x_evm_a53_defconfig
> +++ b/configs/am64x_evm_a53_defconfig
> @@ -178,3 +178,5 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y
>  CONFIG_SPL_DFU=y
>  CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
>  CONFIG_EFI_SET_TIME=y
> +CONFIG_EFI_CAPSULE_ON_DISK=y
> +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y

-- 
cheers,
-roger

Re: [PATCH v4 0/7] Add SE HMBSC board support


Applied, thanks.

(b4 didn't seem to detect this series properly, hence the manual mail).

On 12/04/2024 11:54, Sumit Garg wrote:

SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major
difference from db410c is serial port where HMIBSC board uses UART1 as
the debug console with an RS232 port, patch #2 - #5 adds corresponding
driver support.

Patch #6 adds main HMIBSC board specific bits, features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI

Features enabled in U-Boot:
- RAUC updates (refer [2] for more details)
- Environment protection
- USB based ethernet adaptors

Feedback is very much welcome.

Changes in v4:
- Rebased on top of qcom-main [4].
- Split out board DTS patch as #6.
- Convert to text based environment as hmibsc.env.
- MMC regression has been reported for qcom-main branch here [5].
- Collected further review tag.

Changes in v3:
- Rebased on top of qcom-next [1].
- Collected some review tags.
- Incorporated misc. comments from Caleb and Stephen.
- Split patch#4 as requested.
- Linux HMIBSC board DTS has already been reviewed here [3], I have
   incorporated that for U-Boot too.

Changes in v2:
- Rebased on top on qcom-next [1].
- Added patch#1 as a fix for generic qcom board support.
- Added patch#4 to enable driving GPIO pins based on pinctrl
   configuration. This replaces the custom GPIO configuration.
- Added proper DTS file for HMIBSC board based on Linux DT pattern.
- Merged board support patches into a single patch#5.

[1] 
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-next?ref_type=heads
[2] https://rauc.readthedocs.io/en/latest/
[3] 
https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.g...@linaro.org/
[4] 
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-main/?ref_type=heads
[5] 
https://lore.kernel.org/all/cafa6wyo+3vroudfuvh390taviqx8pmqroqdtsn0yu6bd5yy...@mail.gmail.com/

Sumit Garg (7):
   qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default
   apq8016: Add support for UART1 clocks and pinmux
   serial_msm: Enable RS232 flow control
   pinctrl: qcom: Add support for driving GPIO pins output
   pinctrl: qcom: apq8016: Add GPIO pinctrl function
   arm: dts: qcom: Add Schneider HMIBSC board dts
   board: add support for Schneider HMIBSC board

  arch/arm/Kconfig  |   2 +-
  arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++
  board/schneider/hmibsc/MAINTAINERS|   6 +
  board/schneider/hmibsc/hmibsc.env |  40 ++
  configs/hmibsc_defconfig  |  87 
  doc/board/index.rst   |   1 +
  doc/board/schneider/hmibsc.rst|  45 ++
  doc/board/schneider/index.rst |   9 +
  drivers/clk/qcom/clock-apq8016.c  |  38 +-
  drivers/pinctrl/qcom/pinctrl-apq8016.c|   2 +
  drivers/pinctrl/qcom/pinctrl-qcom.c   |  25 +-
  drivers/serial/serial_msm.c   |  24 +-
  include/configs/hmibsc.h  |  16 +
  13 files changed, 760 insertions(+), 26 deletions(-)
  create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts
  create mode 100644 board/schneider/hmibsc/MAINTAINERS
  create mode 100644 board/schneider/hmibsc/hmibsc.env
  create mode 100644 configs/hmibsc_defconfig
  create mode 100644 doc/board/schneider/hmibsc.rst
  create mode 100644 doc/board/schneider/index.rst
  create mode 100644 include/configs/hmibsc.h



--
// Caleb (they/them)

Re: [PATCH v2 0/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller



On Mon, 22 Apr 2024 11:33:51 +0200, Neil Armstrong wrote:
> Add Support for the Qualcomm Generic Interface (GENI) I2C interface
> found on newer Qualcomm SoCs.
> 
> The Generic Interface (GENI) is a firmware based Qualcomm Universal
> Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple
> bus protocols depending on the firmware type loaded at early boot time
> based on system configuration.
> 
> [...]

Applied, thanks!

[1/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
  commit: 75db9ede12d06693a3ced8c901b74065a1922a23
[2/2] configs: qcom_defconfig: enable GENI I2C Driver
  commit: ad12acd7a8f5aeea5816d5c2fc37c205c403eee0

Best regards,
-- 
Caleb Connolly

Re: [PATCH 0/9] qcom: RBx fixes and USB support



On Thu, 18 Apr 2024 18:25:43 +0100, Caleb Connolly wrote:
> This series is a few loosely connected patches to get the RB1 and 2
> boards booting from USB with upstream U-Boot, and a few preperatory
> patches for rb5.
> 
> Unfortunately the RB5 board requires a regulator on the RPMh peripheral
> to be turned on for the USB VBUS rail. Support for this will be added in
> future patches.
> 
> [...]

Applied, thanks!

[1/9] gpio: qcom_pmic: add pm6125
  commit: 733f6d982099c639c0872ed535be9eede2765a2d
[2/9] gpio: qcom_pmic: add pm8150l
  commit: 8bf1eb9a2e1e68ee18db084f24e8961e655926c4
[3/9] iommu: qcom-smmu: add qcom generic compatible
  commit: 2bd5bcaf7d23fc6ad9b2caf351fdb0b1bf712999
[4/9] phy: qcom: snps-femto-v2: drop clocks
  commit: 82a99b3ab8f022656a13e6dffdac93f5b1bc1d54
[5/9] arm: dts: qrb4210-rb2-u-boot: add u-boot fixups
  commit: 956f6e4de48f5f6c549d403a9f6db78a8deef689
[6/9] mach-snapdragon: implement ft_board_setup() for USB role selection
  commit: e64503f1fcdfa4e836c192ab7d16075fda864d19
[7/9] qcom_defconfig: enable OF_BOARD_SETUP
  commit: 9050686c1b9d9d9ac03a3f685458ab5eb2969e15
[8/9] qcom_defconfig: define safe default SYS_LOAD_ADDR
  commit: 9861ebac77d46674243886136275aac1deb7f982
[9/9] qcom_defconfig: generate SMBIOS tables
  commit: d286220078505727c8c0baf9cd9c832a1fcad805

Best regards,
-- 
Caleb Connolly

Re: [PATCH 0/4] smpi: msm: fix version 5 and add version 7 support



On Fri, 05 Apr 2024 10:21:52 +0200, Neil Armstrong wrote:
> First, fix version 5 support by using the right ch_offset in
> then msm_spmi_write() reg accesses.
> 
> Then:
> - properly format command by importing helpers from Linux driver and
>   use a switch/case to handle all versions in msm_spmi_write/read() command.
> - handle peripheral ownership by poking into the cnfg registers and
>   mark periperal as read-only when the owner id doesn't match
> - finally add version 7 defines
> 
> [...]

Applied, thanks!

[1/4] spmi: msm: fix version 5 support
  commit: c2de620d64d462c1404ca383ad55aecf3f5a972e
[2/4] spmi: msm: properly format command
  commit: f0b604d9491dc92c9cb092a9e4c0fdf2036cdb8d
[3/4] spmi: msm: handle peripheral ownership
  commit: 59e0482b5edc1fceded3967306561a57f60ba4b3
[4/4] spmi: msm: support controller version 7
  commit: ee1d8aa5ecf77991d3bbcfea2d5b37d88bb19473

Best regards,
-- 
Caleb Connolly

Re: [PATCH v2] mach-snapdragon: Allow other board vendors apart from Qcom



On Thu, 11 Apr 2024 18:07:26 +0530, Sumit Garg wrote:
> Qcom SoCs derived boards can come from various OEMs/ODMs and not just
> Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly
> corressponding to the actual board vendor.
> 
> 

Applied, thanks!

[1/1] mach-snapdragon: Allow other board vendors apart from Qcom
  commit: b01c8a8ea420a422bbb0550f7dff8ec5a2a03979

Best regards,
-- 
Caleb Connolly

Re: [PATCH v2 1/5] pinctrl: qcom: allow selecting with ARCH_IPQ40XX



On Mon, 22 Apr 2024 13:43:24 +0200, Robert Marko wrote:
> IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl
> directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus
> PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used.
> 
> 

Applied, thanks!

[1/5] pinctrl: qcom: allow selecting with ARCH_IPQ40XX
  commit: 622f676801f3d4a45524874ab8bf6ee498acbb5c
[2/5] mach-ipq40xx: import GPIO header from mach-snapgradon
  commit: a2830931490952b3130c22fd3259123b27ee9889
[3/5] pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS
  commit: c88f0b12595f250ae7192c7427a9ca75dbdc59d9
[4/5] pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC
  commit: 1dd073b3a9738325569c71028962924ab69a3e1c
[5/5] pinctrl: qcom: ipq4019: support all pin functions
  commit: 8c4c6a268e35523e6a8130f93c51b60a6341e8a2

Best regards,
-- 
Caleb Connolly

Re: [PATCH] arm: mach-ipq40xx: dont select SMEM by default



On Thu, 18 Apr 2024 11:17:00 +0200, Robert Marko wrote:
> IPQ40xx SoC-s dont have proper SMEM support like more modern Qualcomm
> SoC-s so there is no point in selecting the required drivers.
> 
> 

Applied, thanks!

[1/1] arm: mach-ipq40xx: dont select SMEM by default
  commit: c38dcb217c8be0aae7e8e1bb1fb3c31850fa89c3

Best regards,
-- 
Caleb Connolly

Re: [PATCH 0/3] qcom: switch to OF_UPSTREAM