Re: [U-Boot] [PATCH v0 1/5] pci: mvebu: Fix Armada 38x support

[Anton Schubert]

Am 18.11.2015 um 13:48 schrieb Dirk Eibach:
> I assume the idea is to go to the next port if the current port is
> disabled. But adding 3 to the index does not seem to be the right
> thing to do, since Armada XP has ports with 4 lanes, but also with
> ports with one lane.
> I assume that iterating over all lanes would not be a problem, but by
> mistake the pcie->lane == 0  was left in the condition. 
Yeah you are right. The additional condition was superfluous in the
original version.

> So this should perform better:
>
> /* Don't read at all from pci registers if port power is down */
> if (SELECT(soc_ctrl, pcie->port) == 0) {
> if (pcie->lane == 0)
> debug("%s: skipping port %d\n", __func__, pcie->port);
> continue;
> }
I agree.

Regards,
Anton
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Re: [U-Boot] [PATCH v0 1/5] pci: mvebu: Fix Armada 38x support

[Anton Schubert]

Hi Dirk,

2015-10-28 16:44 GMT+01:00 :

> From: Dirk Eibach 
>
> @@ -344,7 +345,6 @@ void pci_init_board(void)
>
> /* Don't read at all from pci registers if port power is
> down */
> if (pcie->lane == 0 && SELECT(soc_ctrl, pcie->port) == 0) {
> -   i += 3;
> debug("%s: skipping port %d\n", __func__,
> pcie->port);
> continue;
> }
>

Is there a specific reason why you removed this line or was it just by
mistake? Because I think doing so would break Armada XP in certain Serdes
Configurations, as it doesn't like it's PCI registers being read if the
port is off.

Kind Regards,
Anton
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[U-Boot] [PATCH] arm: mvebu: add multiple usb-hostcontroller support for AXP

[Anton Schubert]

This patch adds support for multiple hostcontrollers to the ehci-marvell driver
and enables all 3 usb-hcs on the db-mv784mp-gp board.

It depends on the initial Armada XP usb support patch from Stefan.

Signed-off-by: Anton Schubert anton.schub...@gmx.de
Cc: Stefan Roese s...@denx.de
Cc: Luka Perkov luka.per...@sartura.hr
---
 drivers/usb/host/ehci-marvell.c | 23 ---
 include/configs/db-mv784mp-gp.h |  1 +
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 826e7f7..6548cb2 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -22,7 +22,8 @@
 DECLARE_GLOBAL_DATA_PTR;

 #define rdl(off)   readl(MVUSB0_BASE + (off))
-#define wrl(off, val)  writel((val), MVUSB0_BASE + (off))
+#define wrl(port, off, val)writel((val), MVUSB0_BASE + (off) + \
+   ((port)  12))

 #define USB_WINDOW_CTRL(i) (0x320 + ((i)  4))
 #define USB_WINDOW_BASE(i) (0x324 + ((i)  4))
@@ -47,7 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * to the common mvebu archticture including the mbus setup, this
  * will be the only function needed to configure the access windows
  */
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(int index)
 {
const struct mbus_dram_target_info *dram;
int i;
@@ -55,24 +56,24 @@ static void usb_brg_adrdec_setup(void)
dram = mvebu_mbus_dram_info();

for (i = 0; i  4; i++) {
-   wrl(USB_WINDOW_CTRL(i), 0);
-   wrl(USB_WINDOW_BASE(i), 0);
+   wrl(index, USB_WINDOW_CTRL(i), 0);
+   wrl(index, USB_WINDOW_BASE(i), 0);
}

for (i = 0; i  dram-num_cs; i++) {
const struct mbus_dram_window *cs = dram-cs + i;

/* Write size, attributes and target id to control register */
-   wrl(USB_WINDOW_CTRL(i),
+   wrl(index, USB_WINDOW_CTRL(i),
((cs-size - 1)  0x) | (cs-mbus_attr  8) |
(dram-mbus_dram_target_id  4) | 1);

/* Write base address to base register */
-   wrl(USB_WINDOW_BASE(i), cs-base);
+   wrl(index, USB_WINDOW_BASE(i), cs-base);
}
 }
 #else
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(int index)
 {
int i;
u32 size, base, attrib;
@@ -102,13 +103,13 @@ static void usb_brg_adrdec_setup(void)
size = gd-bd-bi_dram[i].size;
base = gd-bd-bi_dram[i].start;
if ((size)  (attrib))
-   wrl(USB_WINDOW_CTRL(i),
+   wrl(index, USB_WINDOW_CTRL(i),
MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
attrib, MVCPU_WIN_ENABLE));
else
-   wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+   wrl(index, USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);

-   wrl(USB_WINDOW_BASE(i), base);
+   wrl(index, USB_WINDOW_BASE(i), base);
}
 }
 #endif
@@ -120,7 +121,7 @@ static void usb_brg_adrdec_setup(void)
 int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-   usb_brg_adrdec_setup();
+   usb_brg_adrdec_setup(index);

*hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 1314fd3..21581e2 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -47,6 +47,7 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_MARVELL
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3

 /* SPI NOR flash default params, used by sf commands */
 #define CONFIG_SF_DEFAULT_SPEED100
--
2.3.6
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Re: [U-Boot] [PATCH v2] arm: mvebu: add multiple usb-hostcontroller support for AXP

[Anton Schubert]

Sry, forgot the cc again.

Anton
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[U-Boot] [PATCH v2] arm: mvebu: add multiple usb-hostcontroller support for AXP

[Anton Schubert]

This patch adds support for multiple hostcontrollers to the ehci-marvell driver
and enables all 3 usb-hcs on the db-mv784mp-gp board.

It depends on the initial Armada XP usb support patch from Stefan.

Signed-off-by: Anton Schubert anton.schub...@gmx.de
Reviewed-by: Stefan Roese s...@denx.de
Cc: Luka Perkov luka.per...@sartura.hr
---
Changes in v2:
- don't use the wrl accessor function
- use the correct hccr pointer

 drivers/usb/host/ehci-marvell.c | 17 +
 include/configs/db-mv784mp-gp.h |  1 +
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index fda812e..daff0d7 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -38,13 +38,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MVUSB0_BASE\
(mvebu_soc_family() == MVEBU_SOC_A38X ? \
 MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
+#define MVUSB_BASE(port)   MVUSB0_BASE + ((port)  12)

 /*
  * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
  * to the common mvebu archticture including the mbus setup, this
  * will be the only function needed to configure the access windows
  */
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(int index)
 {
const struct mbus_dram_target_info *dram;
int i;
@@ -52,8 +53,8 @@ static void usb_brg_adrdec_setup(void)
dram = mvebu_mbus_dram_info();

for (i = 0; i  4; i++) {
-   writel(0, MVUSB0_BASE + USB_WINDOW_CTRL(i));
-   writel(0, MVUSB0_BASE + USB_WINDOW_BASE(i));
+   writel(0, MVUSB_BASE(index) + USB_WINDOW_CTRL(i));
+   writel(0, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
}

for (i = 0; i  dram-num_cs; i++) {
@@ -62,14 +63,14 @@ static void usb_brg_adrdec_setup(void)
/* Write size, attributes and target id to control register */
writel(((cs-size - 1)  0x) | (cs-mbus_attr  8) |
   (dram-mbus_dram_target_id  4) | 1,
-  MVUSB0_BASE + USB_WINDOW_CTRL(i));
+  MVUSB_BASE(index) + USB_WINDOW_CTRL(i));

/* Write base address to base register */
-   writel(cs-base, MVUSB0_BASE + USB_WINDOW_BASE(i));
+   writel(cs-base, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
}
 }
 #else
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(int index)
 {
int i;
u32 size, base, attrib;
@@ -118,9 +119,9 @@ static void usb_brg_adrdec_setup(void)
 int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-   usb_brg_adrdec_setup();
+   usb_brg_adrdec_setup(index);

-   *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+   *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 1314fd3..21581e2 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -47,6 +47,7 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_MARVELL
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3

 /* SPI NOR flash default params, used by sf commands */
 #define CONFIG_SF_DEFAULT_SPEED100
--
2.3.6
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[U-Boot] [PATCH] arm: mvebu: increase delay after setting ddr3 training patterns

[Anton Schubert]

The mv78260 needs atleast 10ms after setting the ddr3 training patterns
or else the cpu will hang.

This patch increases said delay to 20ms just to be safe.

Signed-off-by: Anton Schubert anton.schub...@gmx.de
Cc: Stefan Roese s...@denx.de
Cc: Luka Perkov luka.per...@sartura.hr 
---
 drivers/ddr/mvebu/ddr3_hw_training.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/mvebu/ddr3_hw_training.c 
b/drivers/ddr/mvebu/ddr3_hw_training.c
index a8c5e6a..c9c9272 100644
--- a/drivers/ddr/mvebu/ddr3_hw_training.c
+++ b/drivers/ddr/mvebu/ddr3_hw_training.c
@@ -674,7 +674,7 @@ int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume)
 
reg_write(REG_DRAM_TRAINING_ADDR, reg);
 
-   udelay(100);
+   mdelay(20);
 
/* Check if Successful */
if (reg_read(REG_DRAM_TRAINING_ADDR) 
-- 
2.3.6

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[U-Boot] [PATCH] arm: mvebu: add Armada XP SATA support

[Anton Schubert]

This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.

Signed-off-by: Anton Schubert anton.schub...@gmx.de
Cc: Stefan Roese s...@denx.de
Cc: Luka Perkov luka.per...@sartura.hr 
---
 arch/arm/mach-mvebu/include/mach/soc.h |  1 +
 drivers/block/mvsata_ide.c | 41 ++
 include/configs/db-mv784mp-gp.h| 27 ++
 3 files changed, 69 insertions(+)

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h 
b/arch/arm/mach-mvebu/include/mach/soc.h
index 1aaea67..619bc7e 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -52,6 +52,7 @@
 #define MVEBU_USB20_BASE   (MVEBU_REGISTER(0x58000))
 #define MVEBU_EGIGA0_BASE  (MVEBU_REGISTER(0x7))
 #define MVEBU_EGIGA1_BASE  (MVEBU_REGISTER(0x74000))
+#define MVEBU_AXP_SATA_BASE(MVEBU_REGISTER(0xa))
 #define MVEBU_SATA0_BASE   (MVEBU_REGISTER(0xa8000))
 #define MVEBU_SDIO_BASE(MVEBU_REGISTER(0xd8000))
 
diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index e54d564..52c1602 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -13,6 +13,8 @@
 #include asm/arch/orion5x.h
 #elif defined(CONFIG_KIRKWOOD)
 #include asm/arch/soc.h
+#elif defined(CONFIG_ARMADA_XP)
+#include linux/mbus.h
 #endif
 
 /* SATA port registers */
@@ -90,6 +92,41 @@ struct mvsata_port_registers {
 #define MVSATA_STATUS_TIMEOUT  -1
 
 /*
+ * Registers for SATA MBUS memory windows
+ */
+
+#define MVSATA_WIN_CONTROL(w)  (MVEBU_AXP_SATA_BASE + 0x30 + ((w)  4))
+#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w)  4))
+
+/*
+ * Initialize SATA memory windows for Armada XP
+ */
+
+#ifdef CONFIG_ARMADA_XP
+static void mvsata_ide_conf_mbus_windows(void)
+{
+   const struct mbus_dram_target_info *dram;
+   int i;
+
+   dram = mvebu_mbus_dram_info();
+
+   /* Disable windows, Set Size/Base to 0  */
+   for (i = 0; i  4; i++) {
+   writel(0, MVSATA_WIN_CONTROL(i));
+   writel(0, MVSATA_WIN_BASE(i));
+   }
+
+   for (i = 0; i  dram-num_cs; i++) {
+   const struct mbus_dram_window *cs = dram-cs + i;
+   writel(((cs-size - 1)  0x) | (cs-mbus_attr  8) |
+   (dram-mbus_dram_target_id  4) | 1,
+   MVSATA_WIN_CONTROL(i));
+   writel(cs-base  0x, MVSATA_WIN_BASE(i));
+   }
+}
+#endif
+
+/*
  * Initialize one MVSATAHC port: set SControl's IPM to always active
  * and DET to reset, then wait for SStatus's DET to become device and
  * comm ok (or time out after 50 us if no device), then set SControl's
@@ -137,6 +174,10 @@ int ide_preinit(void)
int ret = MVSATA_STATUS_TIMEOUT;
int status;
 
+#ifdef CONFIG_ARMADA_XP
+   mvsata_ide_conf_mbus_windows();
+#endif
+
/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
 #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
status = mvsata_ide_initialize_port(
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index c33a588..1a322d5 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -60,6 +60,33 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET  /* don't print console @ startup */
 #define CONFIG_SYS_ALT_MEMTEST
 
+/* SATA support */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE
+
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+
+#define CONFIG_SYS_ATA_REG_OFFSET  0x0100  /* Offset for normal 
register accesses*/
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100  /* Offset for data I/O */
+#define CONFIG_SYS_ATA_ALT_OFFSET  0x0100
+
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE  4
+
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS  2
+#define CONFIG_SYS_IDE_MAXDEVICE   4
+
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR   MVEBU_AXP_SATA_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
+
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_CMD_IDE */
+
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros
-- 
2.3.6

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[U-Boot] [PATCH v3] arm: mvebu: add Armada XP SATA support

[Anton Schubert]

This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.

Signed-off-by: Anton Schubert anton.schub...@gmx.de
Tested-by: Stefan Roese s...@denx.de
Cc: Luka Perkov luka.per...@sartura.hr
---
Changes v3:
 - fix config formatting

 arch/arm/mach-mvebu/include/mach/soc.h |  1 +
 drivers/block/mvsata_ide.c | 41 ++
 include/configs/db-mv784mp-gp.h| 29 
 3 files changed, 71 insertions(+)

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h 
b/arch/arm/mach-mvebu/include/mach/soc.h
index 1aaea67..619bc7e 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -52,6 +52,7 @@
 #define MVEBU_USB20_BASE   (MVEBU_REGISTER(0x58000))
 #define MVEBU_EGIGA0_BASE  (MVEBU_REGISTER(0x7))
 #define MVEBU_EGIGA1_BASE  (MVEBU_REGISTER(0x74000))
+#define MVEBU_AXP_SATA_BASE(MVEBU_REGISTER(0xa))
 #define MVEBU_SATA0_BASE   (MVEBU_REGISTER(0xa8000))
 #define MVEBU_SDIO_BASE(MVEBU_REGISTER(0xd8000))
 
diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index e54d564..52c1602 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -13,6 +13,8 @@
 #include asm/arch/orion5x.h
 #elif defined(CONFIG_KIRKWOOD)
 #include asm/arch/soc.h
+#elif defined(CONFIG_ARMADA_XP)
+#include linux/mbus.h
 #endif
 
 /* SATA port registers */
@@ -90,6 +92,41 @@ struct mvsata_port_registers {
 #define MVSATA_STATUS_TIMEOUT  -1
 
 /*
+ * Registers for SATA MBUS memory windows
+ */
+
+#define MVSATA_WIN_CONTROL(w)  (MVEBU_AXP_SATA_BASE + 0x30 + ((w)  4))
+#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w)  4))
+
+/*
+ * Initialize SATA memory windows for Armada XP
+ */
+
+#ifdef CONFIG_ARMADA_XP
+static void mvsata_ide_conf_mbus_windows(void)
+{
+   const struct mbus_dram_target_info *dram;
+   int i;
+
+   dram = mvebu_mbus_dram_info();
+
+   /* Disable windows, Set Size/Base to 0  */
+   for (i = 0; i  4; i++) {
+   writel(0, MVSATA_WIN_CONTROL(i));
+   writel(0, MVSATA_WIN_BASE(i));
+   }
+
+   for (i = 0; i  dram-num_cs; i++) {
+   const struct mbus_dram_window *cs = dram-cs + i;
+   writel(((cs-size - 1)  0x) | (cs-mbus_attr  8) |
+   (dram-mbus_dram_target_id  4) | 1,
+   MVSATA_WIN_CONTROL(i));
+   writel(cs-base  0x, MVSATA_WIN_BASE(i));
+   }
+}
+#endif
+
+/*
  * Initialize one MVSATAHC port: set SControl's IPM to always active
  * and DET to reset, then wait for SStatus's DET to become device and
  * comm ok (or time out after 50 us if no device), then set SControl's
@@ -137,6 +174,10 @@ int ide_preinit(void)
int ret = MVSATA_STATUS_TIMEOUT;
int status;
 
+#ifdef CONFIG_ARMADA_XP
+   mvsata_ide_conf_mbus_windows();
+#endif
+
/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
 #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
status = mvsata_ide_initialize_port(
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index c33a588..a78b639 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -27,6 +27,7 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
@@ -60,6 +61,34 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET  /* don't print console @ startup */
 #define CONFIG_SYS_ALT_MEMTEST
 
+/* SATA support */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE
+
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+
+#define CONFIG_SYS_ATA_REG_OFFSET  0x0100 /* Offset for register access */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
+#define CONFIG_SYS_ATA_ALT_OFFSET  0x0100
+
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE  4
+
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS  2
+#define CONFIG_SYS_IDE_MAXDEVICE   CONFIG_SYS_IDE_MAXBUS
+
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR   MVEBU_AXP_SATA_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
+
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_CMD_IDE */
+
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros
-- 
2.3.6

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[U-Boot] [PATCH v2] add Armada XP SATA support

[Anton Schubert]

This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.

Changes v2:
 - add second bus offset
 - only allow one device per bus
 - enable CONFIG_CMD_IDE per default

Signed-off-by: Anton Schubert anton.schub...@gmx.de
Cc: Stefan Roese s...@denx.de
Cc: Luka Perkov luka.per...@sartura.hr 
---
 arch/arm/mach-mvebu/include/mach/soc.h |  1 +
 drivers/block/mvsata_ide.c | 41 ++
 include/configs/db-mv784mp-gp.h| 29 
 3 files changed, 71 insertions(+)

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h 
b/arch/arm/mach-mvebu/include/mach/soc.h
index 1aaea67..619bc7e 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -52,6 +52,7 @@
 #define MVEBU_USB20_BASE   (MVEBU_REGISTER(0x58000))
 #define MVEBU_EGIGA0_BASE  (MVEBU_REGISTER(0x7))
 #define MVEBU_EGIGA1_BASE  (MVEBU_REGISTER(0x74000))
+#define MVEBU_AXP_SATA_BASE(MVEBU_REGISTER(0xa))
 #define MVEBU_SATA0_BASE   (MVEBU_REGISTER(0xa8000))
 #define MVEBU_SDIO_BASE(MVEBU_REGISTER(0xd8000))
 
diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index e54d564..52c1602 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -13,6 +13,8 @@
 #include asm/arch/orion5x.h
 #elif defined(CONFIG_KIRKWOOD)
 #include asm/arch/soc.h
+#elif defined(CONFIG_ARMADA_XP)
+#include linux/mbus.h
 #endif
 
 /* SATA port registers */
@@ -90,6 +92,41 @@ struct mvsata_port_registers {
 #define MVSATA_STATUS_TIMEOUT  -1
 
 /*
+ * Registers for SATA MBUS memory windows
+ */
+
+#define MVSATA_WIN_CONTROL(w)  (MVEBU_AXP_SATA_BASE + 0x30 + ((w)  4))
+#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w)  4))
+
+/*
+ * Initialize SATA memory windows for Armada XP
+ */
+
+#ifdef CONFIG_ARMADA_XP
+static void mvsata_ide_conf_mbus_windows(void)
+{
+   const struct mbus_dram_target_info *dram;
+   int i;
+
+   dram = mvebu_mbus_dram_info();
+
+   /* Disable windows, Set Size/Base to 0  */
+   for (i = 0; i  4; i++) {
+   writel(0, MVSATA_WIN_CONTROL(i));
+   writel(0, MVSATA_WIN_BASE(i));
+   }
+
+   for (i = 0; i  dram-num_cs; i++) {
+   const struct mbus_dram_window *cs = dram-cs + i;
+   writel(((cs-size - 1)  0x) | (cs-mbus_attr  8) |
+   (dram-mbus_dram_target_id  4) | 1,
+   MVSATA_WIN_CONTROL(i));
+   writel(cs-base  0x, MVSATA_WIN_BASE(i));
+   }
+}
+#endif
+
+/*
  * Initialize one MVSATAHC port: set SControl's IPM to always active
  * and DET to reset, then wait for SStatus's DET to become device and
  * comm ok (or time out after 50 us if no device), then set SControl's
@@ -137,6 +174,10 @@ int ide_preinit(void)
int ret = MVSATA_STATUS_TIMEOUT;
int status;
 
+#ifdef CONFIG_ARMADA_XP
+   mvsata_ide_conf_mbus_windows();
+#endif
+
/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
 #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
status = mvsata_ide_initialize_port(
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index c33a588..0fdf3a5 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -32,6 +32,7 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_TFTPPUT
 #define CONFIG_CMD_TIME
+#define CONFIG_CMD_IDE
 
 /* I2C */
 #define CONFIG_SYS_I2C
@@ -60,6 +61,34 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET  /* don't print console @ startup */
 #define CONFIG_SYS_ALT_MEMTEST
 
+/* SATA support */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE
+
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+
+#define CONFIG_SYS_ATA_REG_OFFSET  0x0100  /* Offset for normal 
register accesses*/
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100  /* Offset for data I/O */
+#define CONFIG_SYS_ATA_ALT_OFFSET  0x0100
+
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE  4
+
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS  2
+#define CONFIG_SYS_IDE_MAXDEVICE   CONFIG_SYS_IDE_MAXBUS
+
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR   MVEBU_AXP_SATA_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
+
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_CMD_IDE */
+
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros
-- 
2.3.6

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Re: [U-Boot] [PATCH] arm: mvebu: increase delay after setting ddr3 training patterns

[Anton Schubert]

Hi Stefan,

Your timer patch fixes the booting problems for me so this delay isn't
necessary anymore.

Thanks,
Anton
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Re: [U-Boot] [PATCH] arm: mvebu: increase delay after setting ddr3 training patterns

[Anton Schubert]

Hi Luka,

My Patch isn't necessary anymore and as Stefan said potentially breaking on
other chip versions.

Anton
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Re: [U-Boot] [PATCH] arm: mvebu: Call timer_init early before PHY and DDR init

[Anton Schubert]

Tested-by: Anton Schubert anton.schub...@gmx.de

Tested on custom mv78260 board.

Anton
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Re: [U-Boot] [PATCH] arm: mvebu: increase delay after setting ddr3 training patterns

[Anton Schubert]

Hi Luka

2015-07-15 17:04 GMT+02:00 Luka Perkov luka.per...@sartura.hr:

 I think everything is merged correctly as was intended. Please check.


Is correct.

Thanks, Anton
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Re: [U-Boot] Marvell Armada XP SATA support

[Anton Schubert]

Hi Stefan,

2015-07-01 12:39 GMT+02:00 Stefan Roese s...@denx.de:

 Hi Anton,

 On 01.07.2015 12:20, Anton Schubert wrote:

 I figured out my problem was just ATA security. After unlocking the code
 above works fine for MV78260.


 Great. Then please send a patch to the list to add support for SATA on AXP.

 Thanks,
 Stefan


Should i move the mbus init code to mach-mvebu/cpu.c for that purpose?
Additionally, what would you recommend for the MVEBU_SATA_BASE define as it
would be ambiguous after the a38x patch.

Thanks,
Anton
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Re: [U-Boot] Marvell Armada XP SATA support

[Anton Schubert]

Hi,

I figured out my problem was just ATA security. After unlocking the code
above works fine for MV78260.

Thanks,
 Anton

2015-06-30 11:28 GMT+02:00 Anton Schubert anton.schub...@gmx.de:

 That should be it. Although it's probably a good idea to do this in cpu.c
 as you did with your a38x ahci support.
 Thanks for your help.

 Anton

 ---
  arch/arm/mach-mvebu/include/mach/soc.h |  1 +
  drivers/block/mvsata_ide.c | 46
 ++
  include/configs/db-mv784mp-gp.h| 29 +
  3 files changed, 76 insertions(+)

 diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
 b/arch/arm/mach-mvebu/include/mach/soc.h
 index 0a9307c..2a8234d 100644
 --- a/arch/arm/mach-mvebu/include/mach/soc.h
 +++ b/arch/arm/mach-mvebu/include/mach/soc.h
 @@ -51,6 +51,7 @@
  #define MVEBU_REG_PCIE_BASE(MVEBU_REGISTER(0x4))
  #define MVEBU_EGIGA0_BASE(MVEBU_REGISTER(0x7))
  #define MVEBU_EGIGA1_BASE(MVEBU_REGISTER(0x74000))
 +#define MVEBU_SATA_BASE(MVEBU_REGISTER(0xA))

  #define SDRAM_MAX_CS4
  #define SDRAM_ADDR_MASK0xFF00
 diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
 index e54d564..ace061a 100644
 --- a/drivers/block/mvsata_ide.c
 +++ b/drivers/block/mvsata_ide.c
 @@ -13,6 +13,8 @@
  #include asm/arch/orion5x.h
  #elif defined(CONFIG_KIRKWOOD)
  #include asm/arch/soc.h
 +#elif defined(CONFIG_ARMADA_XP)
 +#include linux/mbus.h
  #endif

  /* SATA port registers */
 @@ -90,6 +92,46 @@ struct mvsata_port_registers {
  #define MVSATA_STATUS_TIMEOUT-1

  /*
 + * Registers for SATA MBUS memory windows
 + */
 +
 +#define MVSATA_WIN_CONTROL(w)(MVEBU_SATA_BASE + 0x30 + ((w)  4))
 +#define MVSATA_WIN_BASE(w)(MVEBU_SATA_BASE + 0x34 + ((w)  4))
 +
 +/*
 + * Initialize SATA memory windows for Armada XP
 + */
 +
 +#ifdef CONFIG_ARMADA_XP
 +static void mvsata_ide_conf_mbus_windows(void)
 +{
 +const struct mbus_dram_target_info *dram;
 +int i;
 +
 +dram = mvebu_mbus_dram_info();
 +
 +/* Disable windows, Set Size/Base to 0  */
 +for (i = 0; i  4; i++) {
 +writel(0, MVSATA_WIN_CONTROL(i));
 +writel(0, MVSATA_WIN_BASE(i));
 +}
 +
 +for (i = 0; i  dram-num_cs; i++) {
 +const struct mbus_dram_window *cs = dram-cs + i;
 +
 +printf(%s: sata window %d\n, __func__, i);
 +printf(%s: size %04x, attr %02x, target %01x\n, __func__,
 cs-size, cs-mbus_attr, dram-mbus_dram_target_id);
 +printf(%s: base %04x\n\n, __func__, cs-base);
 +
 +writel(((cs-size - 1)  0x) | (cs-mbus_attr  8) |
 +(dram-mbus_dram_target_id  4) | 1,
 +MVSATA_WIN_CONTROL(i));
 +writel(cs-base  0x, MVSATA_WIN_BASE(i));
 +}
 +}
 +#endif
 +
 +/*
   * Initialize one MVSATAHC port: set SControl's IPM to always active
   * and DET to reset, then wait for SStatus's DET to become device and
   * comm ok (or time out after 50 us if no device), then set SControl's
 @@ -137,6 +179,10 @@ int ide_preinit(void)
  int ret = MVSATA_STATUS_TIMEOUT;
  int status;

 +#ifdef CONFIG_ARMADA_XP
 +mvsata_ide_conf_mbus_windows();
 +#endif
 +
  /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
  #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
  status = mvsata_ide_initialize_port(
 diff --git a/include/configs/db-mv784mp-gp.h
 b/include/configs/db-mv784mp-gp.h
 index c33a588..299bc82 100644
 --- a/include/configs/db-mv784mp-gp.h
 +++ b/include/configs/db-mv784mp-gp.h
 @@ -32,6 +32,8 @@
  #define CONFIG_CMD_SPI
  #define CONFIG_CMD_TFTPPUT
  #define CONFIG_CMD_TIME
 +#define CONFIG_CMD_BOOTZ
 +#define CONFIG_CMD_IDE

  /* I2C */
  #define CONFIG_SYS_I2C
 @@ -60,6 +62,33 @@
  #define CONFIG_SYS_CONSOLE_INFO_QUIET/* don't print console @ startup
 */
  #define CONFIG_SYS_ALT_MEMTEST

 +/* IDE/ATA/SATA */
 +#ifdef CONFIG_CMD_IDE
 +#define __io
 +#define CONFIG_IDE_PREINIT
 +#define CONFIG_MVSATA_IDE
 +
 +/* Needs byte-swapping for ATA data register */
 +#define CONFIG_IDE_SWAP_IO
 +
 +#define CONFIG_SYS_ATA_REG_OFFSET0x0100  /* Offset for normal
 register accesses*/
 +#define CONFIG_SYS_ATA_DATA_OFFSET0x0100  /* Offset for data I/O
 */
 +#define CONFIG_SYS_ATA_ALT_OFFSET0x0100  /* Offset for data I/O */
 +
 +/* Each 8-bit ATA register is aligned to a 4-bytes address */
 +#define CONFIG_SYS_ATA_STRIDE4
 +
 +/* CONFIG_CMD_IDE requires some #defines for ATA registers */
 +#define CONFIG_SYS_IDE_MAXBUS  2
 +#define CONFIG_SYS_IDE_MAXDEVICE   2
 +
 +/* ATA registers base is at SATA controller base */
 +#define CONFIG_SYS_ATA_BASE_ADDRMVEBU_SATA_BASE
 +#define CONFIG_SYS_ATA_IDE0_OFFSET0x2000
 +
 +#define CONFIG_DOS_PARTITION
 +#endif /* CONFIG_CMD_IDE */
 +
  /*
   * mv-common.h should be defined after CMD configs since it used them
   * to enable certain macros
 --
 2.3.6


 2015-06-30 8:57 GMT+02:00 Stefan Roese s...@denx.de:

 Hi Anton,

 On 29.06.2015 19:01

Re: [U-Boot] Marvell Armada XP SATA support

[Anton Schubert]

Hi Stefan,

2015-07-01 16:55 GMT+02:00 Stefan Roese s...@denx.de:

 Hi Anton,

 On 01.07.2015 15:41, Anton Schubert wrote:

 2015-07-01 12:39 GMT+02:00 Stefan Roese s...@denx.de mailto:s...@denx.de:

 Hi Anton,

 On 01.07.2015 12:20, Anton Schubert wrote:

 I figured out my problem was just ATA security. After unlocking
 the code
 above works fine for MV78260.


 Great. Then please send a patch to the list to add support for SATA
 on AXP.

 Thanks,
 Stefan


 Should i move the mbus init code to mach-mvebu/cpu.c for that purpose?


 No, please keep it in the driver. I only moved it into cpu.c since there
 is no MVEBU specific driver in the AHCI/SATA case.

  Additionally, what would you recommend for the MVEBU_SATA_BASE define as
 it would be ambiguous after the a38x patch.


 Why not just use the same name/macro?


I think it would be a bit confusing with MVEBU_SATA0_BASE for A38X and
MVEBU_SATA_BASE for AXP in the same header. (As I don't have access to the
A38X Spec I don't know how similar they really are)

Anton
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Re: [U-Boot] Marvell Armada XP SATA support

[Anton Schubert]

That should be it. Although it's probably a good idea to do this in cpu.c
as you did with your a38x ahci support.
Thanks for your help.

Anton

---
 arch/arm/mach-mvebu/include/mach/soc.h |  1 +
 drivers/block/mvsata_ide.c | 46
++
 include/configs/db-mv784mp-gp.h| 29 +
 3 files changed, 76 insertions(+)

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
b/arch/arm/mach-mvebu/include/mach/soc.h
index 0a9307c..2a8234d 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -51,6 +51,7 @@
 #define MVEBU_REG_PCIE_BASE(MVEBU_REGISTER(0x4))
 #define MVEBU_EGIGA0_BASE(MVEBU_REGISTER(0x7))
 #define MVEBU_EGIGA1_BASE(MVEBU_REGISTER(0x74000))
+#define MVEBU_SATA_BASE(MVEBU_REGISTER(0xA))

 #define SDRAM_MAX_CS4
 #define SDRAM_ADDR_MASK0xFF00
diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index e54d564..ace061a 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -13,6 +13,8 @@
 #include asm/arch/orion5x.h
 #elif defined(CONFIG_KIRKWOOD)
 #include asm/arch/soc.h
+#elif defined(CONFIG_ARMADA_XP)
+#include linux/mbus.h
 #endif

 /* SATA port registers */
@@ -90,6 +92,46 @@ struct mvsata_port_registers {
 #define MVSATA_STATUS_TIMEOUT-1

 /*
+ * Registers for SATA MBUS memory windows
+ */
+
+#define MVSATA_WIN_CONTROL(w)(MVEBU_SATA_BASE + 0x30 + ((w)  4))
+#define MVSATA_WIN_BASE(w)(MVEBU_SATA_BASE + 0x34 + ((w)  4))
+
+/*
+ * Initialize SATA memory windows for Armada XP
+ */
+
+#ifdef CONFIG_ARMADA_XP
+static void mvsata_ide_conf_mbus_windows(void)
+{
+const struct mbus_dram_target_info *dram;
+int i;
+
+dram = mvebu_mbus_dram_info();
+
+/* Disable windows, Set Size/Base to 0  */
+for (i = 0; i  4; i++) {
+writel(0, MVSATA_WIN_CONTROL(i));
+writel(0, MVSATA_WIN_BASE(i));
+}
+
+for (i = 0; i  dram-num_cs; i++) {
+const struct mbus_dram_window *cs = dram-cs + i;
+
+printf(%s: sata window %d\n, __func__, i);
+printf(%s: size %04x, attr %02x, target %01x\n, __func__,
cs-size, cs-mbus_attr, dram-mbus_dram_target_id);
+printf(%s: base %04x\n\n, __func__, cs-base);
+
+writel(((cs-size - 1)  0x) | (cs-mbus_attr  8) |
+(dram-mbus_dram_target_id  4) | 1,
+MVSATA_WIN_CONTROL(i));
+writel(cs-base  0x, MVSATA_WIN_BASE(i));
+}
+}
+#endif
+
+/*
  * Initialize one MVSATAHC port: set SControl's IPM to always active
  * and DET to reset, then wait for SStatus's DET to become device and
  * comm ok (or time out after 50 us if no device), then set SControl's
@@ -137,6 +179,10 @@ int ide_preinit(void)
 int ret = MVSATA_STATUS_TIMEOUT;
 int status;

+#ifdef CONFIG_ARMADA_XP
+mvsata_ide_conf_mbus_windows();
+#endif
+
 /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
 #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
 status = mvsata_ide_initialize_port(
diff --git a/include/configs/db-mv784mp-gp.h
b/include/configs/db-mv784mp-gp.h
index c33a588..299bc82 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -32,6 +32,8 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_TFTPPUT
 #define CONFIG_CMD_TIME
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_IDE

 /* I2C */
 #define CONFIG_SYS_I2C
@@ -60,6 +62,33 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET/* don't print console @ startup
*/
 #define CONFIG_SYS_ALT_MEMTEST

+/* IDE/ATA/SATA */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE
+
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+
+#define CONFIG_SYS_ATA_REG_OFFSET0x0100  /* Offset for normal
register accesses*/
+#define CONFIG_SYS_ATA_DATA_OFFSET0x0100  /* Offset for data I/O */
+#define CONFIG_SYS_ATA_ALT_OFFSET0x0100  /* Offset for data I/O */
+
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE4
+
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS  2
+#define CONFIG_SYS_IDE_MAXDEVICE   2
+
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDRMVEBU_SATA_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET0x2000
+
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_CMD_IDE */
+
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros
-- 
2.3.6


2015-06-30 8:57 GMT+02:00 Stefan Roese s...@denx.de:

 Hi Anton,

 On 29.06.2015 19:01, Anton Schubert wrote:

 2015-06-23 14:38 GMT+02:00 Stefan Roese s...@denx.de mailto:s...@denx.de:

 Hi Anton,

 On 23.06.2015 13:23, Bin Meng wrote:

 On Tue, Jun 23, 2015 at 5:35 PM, Anton Schubert
 anton.schub...@gmx.de mailto:anton.schub...@gmx.de wrote



 but noticed that there doesn't seem

Re: [U-Boot] Marvell Armada XP SATA support

[Anton Schubert]

2015-06-23 14:38 GMT+02:00 Stefan Roese s...@denx.de:

 Hi Anton,

 On 23.06.2015 13:23, Bin Meng wrote:

 On Tue, Jun 23, 2015 at 5:35 PM, Anton Schubert anton.schub...@gmx.de
 wrote


 but noticed that there doesn't seem to be a driver for the SATA
 controller.
 Are there any plans to support SATA on Armada XP or is our only option to
 migrate the old driver?


 Is the Marvell SATA controller AHCI compatible? If yes, U-Boot has the
 AHCI driver which should work.


 No, the AXP SATA controller is unfortunately not AHCI compatible (the A38x
 seems to be though). The mvsata driver (drivers/block/mvsata_ide.c) might
 be a pretty good start for the AXP though (I didn't check this closely).


Hi,
many thanks for your hints.

I managed to get ide_ident working with mvsata_ide.c by setting the Sata
address windows (using mbus.c analogous to the mvneta driver). But I'm kind
of stuck now as ATA reads will just result in timeouts:

ide_read dev 0 start 0, blocks 1 buffer at 7FBA9C60
ide_outb (dev= 0, port= 0x118, val= 0xe0) : @ 0xf10a2118
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c - 0x50
ide_outb (dev= 0, port= 0x11c, val= 0xe5) : @ 0xf10a211c
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c - 0x50
ide_inb (dev= 0, port= 0x108) : @ 0xf10a2108 - 0xff
Powersaving FF
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c - 0x50
ide_outb (dev= 0, port= 0x108, val= 0x01) : @ 0xf10a2108
ide_outb (dev= 0, port= 0x10c, val= 0x00) : @ 0xf10a210c
ide_outb (dev= 0, port= 0x110, val= 0x00) : @ 0xf10a2110
ide_outb (dev= 0, port= 0x114, val= 0x00) : @ 0xf10a2114
ide_outb (dev= 0, port= 0x118, val= 0xe0) : @ 0xf10a2118
ide_outb (dev= 0, port= 0x11c, val= 0x20) : @ 0xf10a211c
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c - 0xd0
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c - 0x51
Error (no IRQ) dev 0 blk 0: status 0x51


This is my current ide config:
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE

/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO

#define CONFIG_SYS_ATA_REG_OFFSET0x0100  /* Offset for normal
register accesses*/
#define CONFIG_SYS_ATA_DATA_OFFSET0x0100  /* Offset for data I/O */
#define CONFIG_SYS_ATA_ALT_OFFSET0x0100  /* Offset for data I/O
*/

/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE4

/* CONFIG_CMD_IDE requires some #defines for ATA registers */
#define CONFIG_SYS_IDE_MAXBUS  2
#define CONFIG_SYS_IDE_MAXDEVICE   2

/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDRMVEBU_SATA_BASE /* 0xA */
#define CONFIG_SYS_ATA_IDE0_OFFSET0x2000

#define CONFIG_DOS_PARTITION

I would be grateful for any pointers.

Regards,
Anton
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[U-Boot] Marvell Armada XP SATA support

[Anton Schubert]

Hello,

we are trying to replace an old marvell uboot on mv78260 with the current
version, but noticed that there doesn't seem to be a driver for the SATA
controller.
Are there any plans to support SATA on Armada XP or is our only option to
migrate the old driver?

Regards
Anton
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