[PATCH 1/5] brppt1: Remove unused board variants
The SPI and NAND board variants never went into production.
Drop those board variants.
Signed-off-by: Bernhard Messerklinger
---
arch/arm/dts/Makefile | 2 -
arch/arm/dts/am335x-brppt1-nand.dts | 374 ---
arch/arm/dts/am335x-brppt1-spi.dts | 377
board/BuR/brppt1/board.c| 4 +-
board/BuR/brppt1/mux.c | 39 +--
configs/brppt1_nand_defconfig | 122 -
configs/brppt1_spi_defconfig| 130 --
include/configs/brppt1.h| 64 +
8 files changed, 7 insertions(+), 1105 deletions(-)
delete mode 100644 arch/arm/dts/am335x-brppt1-nand.dts
delete mode 100644 arch/arm/dts/am335x-brppt1-spi.dts
delete mode 100644 configs/brppt1_nand_defconfig
delete mode 100644 configs/brppt1_spi_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7330121dba..5bff2e65b7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -388,8 +388,6 @@ dtb-$(CONFIG_AM33XX) += \
am335x-boneblack-wireless.dtb \
am335x-boneblue.dtb \
am335x-brppt1-mmc.dtb \
- am335x-brppt1-nand.dtb \
- am335x-brppt1-spi.dtb \
am335x-brxre1.dtb \
am335x-brsmarc1.dtb \
am335x-draco.dtb \
diff --git a/arch/arm/dts/am335x-brppt1-nand.dts
b/arch/arm/dts/am335x-brppt1-nand.dts
deleted file mode 100644
index 67c609739f..00
--- a/arch/arm/dts/am335x-brppt1-nand.dts
+++ /dev/null
@@ -1,374 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 B Industrial Automation GmbH
- * http://www.br-automation.com
- *
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-
-/ {
- model = "BRPPT1 (NAND) Panel";
- compatible = "ti,am33xx";
-
- fset: factory-settings {
- bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
- version = <0x0100>;
- order-no= "6PPT30 (NAND)";
- hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
- serial-no = "0";
- device-id = <0x0>;
- parent-id = <0x0>;
- hw-variant = <0x1>;
- };
-
- aliases {
- ds1bkl0 =
- ds1bkl1 = _bl;
- ds1timing =
- ds1ctrl =
- gpmc =
- mmc =
- fset =
- };
-
- chosen {
- bootargs = "console=ttyO0,115200 earlyprintk";
- stdout-path =
- };
-
- memory {
- device_type = "memory";
- reg = <0x8000 0x1000>; /* 256 MB */
- };
-
- panel {
- status = "disabled";
-
- compatible = "ti,tilcdc,panel";
- enable-gpios = < 6 GPIO_ACTIVE_LOW>;
-
- backlight = <>;
- bkl-pwm = <>;
- bkl-tps = <_bl>;
-
- panel-info {
- ac-bias = <255>;
- ac-bias-intrpt = <0>;
- dma-burst-sz= <16>;
- bpp = <32>;
- fdd = <0x80>;
- sync-edge = <0>;
- sync-ctrl = <1>;
- raster-order= <0>;
- fifo-th = <0>;
- };
-
- display-timings {
- native-mode = <>;
- timing0: lcd {
- clock-frequency = <3200>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch= <2>;
- hback-porch = <192>;
- hsync-len = <1>;
- vfront-porch= <20>;
- vback-porch = <2>;
- vsync-len = <1>;
- hsync-active= <1>;
- vsync-active= <1>;
- pupdelay= <10>;
- pondelay= <10>;
- };
- };
- };
-
- vmmcsd_fixed: fixedregulator@0 {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsd_fixed";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- };
-
- pwm0: omap-pwm@timer5 {
- compatible = "ti,omap-dmtimer-pwm"
[PATCH 0/5] Fix, update and cleanup brppt1 board
Drop board variants that were never produced, fix the SPL loader, and update environment. Bernhard Messerklinger (5): brppt1: Remove unused board variants brppt1: Fix SPL boot stage brppt1: Cleanup device tree include: configs: brppt1: Fix commit 0ea4fc4dcf90 brppt1: Update environment to support new boot concept arch/arm/dts/Makefile | 2 - arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi | 112 ++ arch/arm/dts/am335x-brppt1-mmc.dts | 201 --- arch/arm/dts/am335x-brppt1-nand.dts| 374 arch/arm/dts/am335x-brppt1-spi.dts | 377 - board/BuR/brppt1/board.c | 4 +- board/BuR/brppt1/mux.c | 39 +-- configs/brppt1_mmc_defconfig | 6 +- configs/brppt1_nand_defconfig | 122 --- configs/brppt1_spi_defconfig | 130 --- include/configs/brppt1.h | 83 + 11 files changed, 135 insertions(+), 1315 deletions(-) create mode 100644 arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi delete mode 100644 arch/arm/dts/am335x-brppt1-nand.dts delete mode 100644 arch/arm/dts/am335x-brppt1-spi.dts delete mode 100644 configs/brppt1_nand_defconfig delete mode 100644 configs/brppt1_spi_defconfig -- 2.37.2
[PATCH 3/5] brppt1: Cleanup device tree
* Remove unnecessary device tree nodes which are not needed in
U-Boot directly.
* Move all U-Boot specific device tree properties to u-boot dtsi.
Signed-off-by: Bernhard Messerklinger
---
arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi | 32
arch/arm/dts/am335x-brppt1-mmc.dts | 201 -
2 files changed, 32 insertions(+), 201 deletions(-)
diff --git a/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi
b/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi
index 0b9a1ccef4..a3d5650e48 100644
--- a/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi
+++ b/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi
@@ -78,3 +78,35 @@
_clocks {
compatible = "simple-bus";
};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/am335x-brppt1-mmc.dts
b/arch/arm/dts/am335x-brppt1-mmc.dts
index bd2f6c2e3e..4db279b65e 100644
--- a/arch/arm/dts/am335x-brppt1-mmc.dts
+++ b/arch/arm/dts/am335x-brppt1-mmc.dts
@@ -12,25 +12,10 @@
model = "BRPPT1 (MMC) Panel";
compatible = "ti,am33xx";
- fset: factory-settings {
- bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
- version = <0x0100>;
- order-no= "6PPT30 (MMC)";
- hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
- serial-no = "0";
- device-id = <0x0>;
- parent-id = <0x0>;
- hw-variant = <0x1>;
- };
aliases {
- ds1bkl0 =
- ds1bkl1 = _bl;
- ds1timing =
- ds1ctrl =
gpmc =
mmc =
- fset =
};
chosen {
@@ -43,110 +28,21 @@
reg = <0x8000 0x1000>; /* 256 MB */
};
- panel {
- status = "disabled";
-
- compatible = "ti,tilcdc,panel";
- enable-gpios = < 6 GPIO_ACTIVE_LOW>;
-
- backlight = <>;
- bkl-pwm = <>;
- bkl-tps = <_bl>;
-
- panel-info {
- ac-bias = <255>;
- ac-bias-intrpt = <0>;
- dma-burst-sz= <16>;
- bpp = <32>;
- fdd = <0x80>;
- sync-edge = <0>;
- sync-ctrl = <1>;
- raster-order= <0>;
- fifo-th = <0>;
- };
-
- display-timings {
- native-mode = <>;
- timing0: lcd {
- clock-frequency = <3200>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch= <2>;
- hback-porch = <192>;
- hsync-len = <1>;
- vfront-porch= <20>;
- vback-porch = <2>;
- vsync-len = <1>;
- hsync-active= <1>;
- vsync-active= <1>;
- pupdelay= <10>;
- pondelay= <10>;
- };
- };
- };
-
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
};
-
- pwm0: omap-pwm@timer5 {
- compatible = "ti,omap-dmtimer-pwm";
- ti,timers = <>;
- #pwm-cells = <3>;
- };
-
- pwm1: omap-pwm@timer6 {
- compatible = "ti,omap-dmtimer-pwm";
- ti,timers = <>;
- #pwm-cells = <3>;
- };
-
- beeper: pwm-beep {
- compatible = "pwm-beeper";
- pwms = < 0 0 0>;
- };
-
- pwmbacklight: pwm-bkl {
- compatible = "pwm-backlight";
- pwms = < 0 500 0>;
-
- default-brightness-level = <255>;
- brightn
[PATCH 5/5] brppt1: Update environment to support new boot concept
* Drop legacy /boot/PPTImage.md5 check
* Update device tree naming
* Update t30args#0 root cmd line property to support latest kernel
versions (root=/dev/mmcblk0p2 for linux < 4 and
root=/dev/mmcblk1p2 for linux >= 4)
* Add custom bootloader version string
* Destroy invalid dtb at ${dtbaddr} and configuration script at
${cfgaddr} to ensure proper boot in warm restart case.
Signed-off-by: Bernhard Messerklinger
---
configs/brppt1_mmc_defconfig | 4 +++-
include/configs/brppt1.h | 18 --
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 6da6d58bfd..a45604de16 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -17,6 +17,8 @@ CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x5
CONFIG_SYS_LOAD_ADDR=0x8000
+CONFIG_LOCALVERSION="-2.0.0"
+# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
# CONFIG_EXPERT is not set
@@ -26,7 +28,7 @@ CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="mw ${dtbaddr} 0; run cfgscr; run brdefaultip"
+CONFIG_PREBOOT="mw ${cfgaddr} 0; mw ${dtbaddr} 0; run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
index aaf3f8b4a5..2c5236aa58 100644
--- a/include/configs/brppt1.h
+++ b/include/configs/brppt1.h
@@ -29,18 +29,16 @@
#define MMC_TGTS \
"t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
- "b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \
+ "b_mode=${b_mode} root=${root_dev} rootfstype=ext4 rootwait\0" \
"b_t30lgcy#0=" \
- "load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \
"load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
- "load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \
- "load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\
+ "run load_dtb && " \
"run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
"t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
"b_mode=${b_mode}\0" \
"b_t30lgcy#1=" \
"load ${loaddev}:1 ${loadaddr} zImage && " \
- "load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \
+ "load ${loaddev}:1 ${dtbaddr} am335x-brppt30.dtb && " \
"load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \
"run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \
"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
@@ -48,11 +46,19 @@
"b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \
"b_tgts_rcy=t30lgcy#1 usb0 net\0" \
"b_tgts_pme=net usb0 mmc0 mmc1\0" \
-"loaddev=mmc 1\0"
+"loaddev=mmc 1\0" \
+"root_dev=/dev/mmcblk0p2\0" \
+"load_dtb=load ${loaddev}:2 ${dtbaddr} /boot/am335x-brppt30.dtb; " \
+"if test $? -eq 0; then " \
+"setenv root_dev /dev/mmcblk1p2; " \
+"else; " \
+"load ${loaddev}:1 ${dtbaddr} am335x-brppt30-legacy.dtb; " \
+"fi;\0"
#ifdef CONFIG_ENV_IS_IN_MMC
#define MMCTGTS \
MMC_TGTS \
+"cfgscr=mw ${cfgaddr} 0;" \
" mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
#else
--
2.37.2
[PATCH 2/5] brppt1: Fix SPL boot stage
Commit 6337d53fdf45 ("arm: dts: sync am33xx with Linux 5.9-rc7") syncs
the am335x device tree with the latest linux kernel am335x device tree.
That causes problems with device tree in SPL stage.
To fix the issues CONFIG_SPL_OF_TRANSLATE must be set to handle the
synced bus addresses correctly.
A custom U-Boot device tree is also needed since the SPL build removes
bus properties from bus nodes which are not explicitly marked with the
u-boot,dm-spl or u-boot,dm-pre-reloc flag. Therefore all parent buses of
the in the SPL needed devices must be marked with u-boot,dm-pre-reloc.
Also since there is no driver for "ti,sysc" compatible property in SPL
the buses marked with this compatible string must also be marked with
compatible = "simple-bus" to make the underlying devices visible in
SPL. Otherwise the matching device drivers aren't found and the uclass
drivers are dropped.
Signed-off-by: Bernhard Messerklinger
---
arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi | 80 ++
configs/brppt1_mmc_defconfig | 2 +-
2 files changed, 81 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi
diff --git a/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi
b/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi
new file mode 100644
index 00..0b9a1ccef4
--- /dev/null
+++ b/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 B Industrial Automation GmbH -
+ * https://www.br-automation.com/
+ */
+
+/ {
+ ocp {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+_wkup {
+ u-boot,dm-pre-reloc;
+ segment@20 {
+ u-boot,dm-pre-reloc;
+ target-module@0
+ {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ };
+ target-module@7000 {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ };
+ target-module@9000 {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ };
+ };
+};
+
+_cm {
+ u-boot,dm-pre-reloc;
+};
+
+_wkup_clkctrl {
+ u-boot,dm-pre-reloc;
+};
+
+_per {
+ u-boot,dm-pre-reloc;
+ segment@0 {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ target-module@4c000 {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ };
+ };
+
+ segment@10 {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ target-module@ac000 {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ };
+ target-module@ae000 {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ };
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+_target {
+ u-boot,dm-pre-reloc;
+};
+
+_clocks {
+ compatible = "simple-bus";
+};
+
+_clocks {
+ compatible = "simple-bus";
+};
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index b1ed2bcd68..716650aac9 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -90,7 +90,7 @@ CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-# CONFIG_OF_TRANSLATE is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
--
2.37.2
[PATCH 4/5] include: configs: brppt1: Fix commit 0ea4fc4dcf90
Commit 0ea4fc4dcf90 ("board/BuR: invalidate ${dtbaddr} before cfgscr")
destroys the boot targets b_t30lgcy#0 and b_t30lgcy#1. The reason behind
this is, that b_t30lgcy#0 and b_t30lgcy#1 both load the for booting
needed device trees from mmc and the cfgscr script patches those. Because
of this, cfgscr is not allowed to destroy the previously loaded device
tree otherwise cfgscr will fail.
This patch moves the device trees invalidation on warm restart to the
PREBOOT cmd to fix that issue.
Fixes: 0ea4fc4dcf90 ("board/BuR: invalidate ${dtbaddr} before cfgscr")
Signed-off-by: Bernhard Messerklinger
---
configs/brppt1_mmc_defconfig | 2 +-
include/configs/brppt1.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 716650aac9..6da6d58bfd 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -26,7 +26,7 @@ CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="run cfgscr; run brdefaultip"
+CONFIG_PREBOOT="mw ${dtbaddr} 0; run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
index 481473ae2c..aaf3f8b4a5 100644
--- a/include/configs/brppt1.h
+++ b/include/configs/brppt1.h
@@ -53,7 +53,6 @@
#ifdef CONFIG_ENV_IS_IN_MMC
#define MMCTGTS \
MMC_TGTS \
-"cfgscr=mw ${dtbaddr} 0;" \
" mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
#else
--
2.37.2
[PATCH 2/2] arch: x86: apl: Update FSP parameters
Add missing parameters to support full configuration of the latest FSP
MR6 release.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_bindings.c| 23 +++
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 5 +++-
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 9 +++-
.../fsp/fsp2/apollolake/fsp-m.txt | 3 +++
.../fsp/fsp2/apollolake/fsp-s.txt | 6 +
5 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c
b/arch/x86/cpu/apollolake/fsp_bindings.c
index 130366b403..bbf04b5009 100644
--- a/arch/x86/cpu/apollolake/fsp_bindings.c
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -633,6 +633,17 @@ const struct fsp_binding fsp_m_bindings[] = {
.offset = offsetof(struct fsp_m_config, variable_nvs_buffer_ptr),
.propname = "fspm,variable-nvs-buffer-ptr",
}, {
+ .type = FSP_UINT64,
+ .offset = offsetof(struct fsp_m_config,
start_timer_ticker_of_pfet_assert),
+ .propname = "fspm,start-timer-ticker-of-pfet-assert",
+ }, {
+ .type = FSP_UINT8, .offset = offsetof(struct fsp_m_config, rt_en),
+ .propname = "fspm,rt-en",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_m_config, skip_pcie_power_sequence),
+ .propname = "fspm,skip-pcie-power-sequence",
+ }, {
.propname = NULL
}
};
@@ -1822,6 +1833,18 @@ const struct fsp_binding fsp_s_bindings[] = {
.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
port_usb20_hs_npre_drv_sel),
}, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, os_selection),
+ .propname = "fsps,os-selection",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, dptf_enabled),
+ .propname = "fsps,dptf-enabled",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, pwm_enabled),
+ .propname = "fsps,pwm-enabled",
+ }, {
.propname = NULL
}
};
diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
index 5275b75f3b..78c338e9ff 100644
--- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
+++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
@@ -122,7 +122,10 @@ struct __packed fsp_m_config {
/* 0x150 */
void*variable_nvs_buffer_ptr;
- u8 reserved_fspm_upd[12];
+ u64 start_timer_ticker_of_pfet_assert;
+ u8 rt_en;
+ u8 skip_pcie_power_sequence;
+ u8 reserved_fspm_upd[2];
};
/** FSP-M UPD Configuration */
diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h
b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h
index 451a7a254a..be80f5db09 100644
--- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h
+++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h
@@ -351,7 +351,10 @@ struct __packed fsp_s_config {
u8 port_usb20_hs_npre_drv_sel[8];
/* 0x370 */
- u8 reserved_fsps_upd[16];
+ u8 os_selection;
+ u8 dptf_enabled;
+ u8 pwm_enabled;
+ u8 reserved_fsps_upd[13];
};
/** struct fsps_upd - FSP-S Configuration */
@@ -563,4 +566,8 @@ struct __packed fsps_upd {
#define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0
#define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1
+#define OS_SELECTION_WINDOWS 0
+#define OS_SELECTION_ANDROID 1
+#define OS_SELECTION_LINUX 3
+
#endif
diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
index 5311938f43..666400e085 100644
--- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
+++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
@@ -240,6 +240,9 @@ Optional properties:
- fspm,enable-reset-system: Enable Reset System
- fspm,enable-s3-heci2: Enable HECI2 in S3 resume path
- fspm,variable-nvs-buffer-ptr:
+- fspm,start-timer-ticker-of-pfet-assert: PCIE SLOT Power Enable Assert Time -
PFET
+- fspm,rt-en: Real Time Enabling
+- fspm,skip-pcie-power-sequence: Skip Pcie Power Sequence
Example:
diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
index 973d253ada..731a310cf8 100644
--- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
+++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
@@ -463,6 +463,12 @@ Optional properties:
- fsps,port-usb20-i-usb-tx-emphasis-en: PerPort HS Transmitter Emphasis
- fsps,port-usb20-per-port-rxi-set: PerPort HS Receiver Bias
- fsps,port-usb20-hs-npre-drv-sel: Delay/skew's strength control for HS driver
+- fsps,os-selection: OS Selection
+ 0: Windows
+ 1: Android
+ 3: Linux
+- fsps,dptf-enabled: DPTF
+- fsps,pwm-enabled: PWM Enabled
Example:
--
2.27.0
[PATCH 1/2] x86: apl: fsp_bindings: Add support for u64 parameters
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter
update.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_bindings.c| 28 +++
.../asm/arch-apollolake/fsp_bindings.h| 1 +
2 files changed, 29 insertions(+)
diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c
b/arch/x86/cpu/apollolake/fsp_bindings.c
index 9130af9ce0..130366b403 100644
--- a/arch/x86/cpu/apollolake/fsp_bindings.c
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -89,6 +89,28 @@ static void read_u32_prop(ofnode node, char *name, size_t
count, u32 *dst)
ofnode_read_u32_array(node, name, dst, count);
}
+/**
+ * read_u64_prop() - Read an u64 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ */
+static int read_u64_prop(ofnode node, char *name, size_t count, u64 *dst)
+{
+ if (count == 0) {
+ ofnode_read_u64(node, name, dst);
+ } else {
+ debug("ERROR: %s u64 arrays not supported!\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
/**
* read_string_prop() - Read a string property from devicetree
* @node: Valid node reference to read property from
@@ -206,6 +228,12 @@ static int fsp_update_config_from_dtb(ofnode node, u8 *cfg,
read_u32_prop(node, fspb->propname, fspb->count,
(u32 *)[fspb->offset]);
break;
+ case FSP_UINT64:
+ ret = read_u64_prop(node, fspb->propname, fspb->count,
+ (u64 *)[fspb->offset]);
+ if (ret)
+ return ret;
+ break;
case FSP_STRING:
read_string_prop(node, fspb->propname, fspb->count,
(char *)[fspb->offset]);
diff --git a/arch/x86/include/asm/arch-apollolake/fsp_bindings.h
b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h
index b4939519ce..a80e66bbfa 100644
--- a/arch/x86/include/asm/arch-apollolake/fsp_bindings.h
+++ b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h
@@ -17,6 +17,7 @@ enum conf_type {
FSP_UINT8,
FSP_UINT16,
FSP_UINT32,
+ FSP_UINT64,
FSP_STRING,
FSP_LPDDR4_SWIZZLE,
};
--
2.27.0
[PATCH 0/2] Update Apollo Lake FSP parameters
This patch set adds new paramters and functions to allow full configuration of the latest FSP MR6 release. Bernhard Messerklinger (2): x86: apl: fsp_bindings: Add support for u64 parameters arch: x86: apl: Update FSP parameters arch/x86/cpu/apollolake/fsp_bindings.c| 51 +++ .../asm/arch-apollolake/fsp/fsp_m_upd.h | 5 +- .../asm/arch-apollolake/fsp/fsp_s_upd.h | 9 +++- .../asm/arch-apollolake/fsp_bindings.h| 1 + .../fsp/fsp2/apollolake/fsp-m.txt | 3 ++ .../fsp/fsp2/apollolake/fsp-s.txt | 6 +++ 6 files changed, 73 insertions(+), 2 deletions(-) -- 2.27.0
[PATCH v4 3/3] arch: x86: apl: Use devicetree for FSP-S configuration
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard Messerklinger
Reviewed-by: Simon Glass
Tested on coral:
Tested-by: Simon Glass
---
Changes in v4: None
Changes in v3:
Split patch into FSP-M and FSP-S
Fix #if defined macro for FSP-S path to reduce SPL size
Changes in v2:
Integration of the review comments
Fix swizzle size bug
arch/x86/cpu/apollolake/fsp_bindings.c| 1189 +
arch/x86/cpu/apollolake/fsp_s.c | 386 +-
arch/x86/dts/chromebook_coral.dts | 35 +-
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 +++
.../asm/arch-apollolake/fsp_bindings.h| 14 +
.../fsp/fsp2/apollolake/fsp-s.txt | 483 +++
6 files changed, 1922 insertions(+), 387 deletions(-)
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c
b/arch/x86/cpu/apollolake/fsp_bindings.c
index 34131e1108..501cbb7ef3 100644
--- a/arch/x86/cpu/apollolake/fsp_bindings.c
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -612,3 +612,1192 @@ int fsp_m_update_config_from_dtb(ofnode node, struct
fsp_m_config *cfg)
return fsp_update_config_from_dtb(node, (u8 *)cfg, fsp_m_bindings);
}
#endif
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+const struct fsp_binding fsp_s_bindings[] = {
+ {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, active_processor_cores),
+ .propname = "fsps,active-processor-cores",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, disable_core1),
+ .propname = "fsps,disable-core1",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, disable_core2),
+ .propname = "fsps,disable-core2",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, disable_core3),
+ .propname = "fsps,disable-core3",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, vmx_enable),
+ .propname = "fsps,vmx-enable",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, proc_trace_mem_size),
+ .propname = "fsps,proc-trace-mem-size",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, proc_trace_enable),
+ .propname = "fsps,proc-trace-enable",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, eist),
+ .propname = "fsps,eist",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, boot_p_state),
+ .propname = "fsps,boot-p-state",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, enable_cx),
+ .propname = "fsps,enable-cx",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, c1e),
+ .propname = "fsps,c1e",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, bi_proc_hot),
+ .propname = "fsps,bi-proc-hot",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, pkg_c_state_limit),
+ .propname = "fsps,pkg-c-state-limit",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, c_state_auto_demotion),
+ .propname = "fsps,c-state-auto-demotion",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, c_state_un_demotion),
+ .propname = "fsps,c-state-un-demotion",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, max_core_c_state),
+ .propname = "fsps,max-core-c-state",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, pkg_c_state_demotion),
+ .propname = "fsps,pkg-c-state-demotion",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, pkg_c_state_un_demotion),
+ .propname = "fsps,pkg-c-state-un-demotion",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, turbo_mode),
+ .propname = "fsps,turbo-mode",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, hda_verb_table_entry_num),
+ .propname = "fsps,hda-verb-table-entry-num",
+ }, {
+ .type = FSP_UINT32,
+ .offset = offsetof(struct fsp_s_config, hda_verb_table_ptr),
+ .propname = "fsps,hda-verb-table-ptr",
+ }, {
+ .type = FSP_UINT8
[PATCH v4 2/3] arch: x86: apl: Use devicetree for FSP-M configuration
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard Messerklinger
Reviewed-by: Simon Glass
Tested on coral:
Tested-by: Simon Glass
---
Changes in v4: None
Changes in v3:
Enable fspm,dual-rank-support-enable on chromebook coral
Split patch into FSP-M and FSP-S
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/fsp_bindings.c| 614 ++
arch/x86/cpu/apollolake/fsp_m.c | 169 +
arch/x86/dts/chromebook_coral.dts | 38 +-
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 +
.../asm/arch-apollolake/fsp_bindings.h| 96 +++
.../fsp/fsp2/apollolake/fsp-m.txt | 320 +
7 files changed, 1242 insertions(+), 164 deletions(-)
create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 578e15c4bf..3aa2a55676 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -10,6 +10,7 @@ obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
obj-y += cpu.o
obj-y += punit.o
+obj-y += fsp_bindings.o
ifdef CONFIG_SPL_BUILD
obj-y += fsp_m.o
endif
diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c
b/arch/x86/cpu/apollolake/fsp_bindings.c
new file mode 100644
index 00..34131e1108
--- /dev/null
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 B Industrial Automation GmbH - http://www.br-automation.com
+ */
+
+#include
+#include
+#include
+
+/**
+ * read_u8_prop() - Read an u8 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * Set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ */
+static void read_u8_prop(ofnode node, char *name, size_t count, u8 *dst)
+{
+ u32 tmp;
+ const u8 *buf;
+ int ret;
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, );
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ buf = ofnode_read_u8_array_ptr(node, name, count);
+ if (buf)
+ memcpy(dst, buf, count);
+ }
+}
+
+/**
+ * read_u16_prop() - Read an u16 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * Set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ * @return 0 on success, -ve on error
+ */
+static int read_u16_prop(ofnode node, char *name, size_t count, u16 *dst)
+{
+ u32 tmp;
+ u32 buf[32];
+ int ret;
+
+ if (ARRAY_SIZE(buf) < count) {
+ debug("ERROR: %s buffer to small!\n", __func__);
+ return -ENOSPC;
+ }
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, );
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ ret = ofnode_read_u32_array(node, name, buf, count);
+ if (ret == 0)
+ for (int i = 0; i < count; i++)
+ dst[i] = buf[i];
+ }
+
+ return 0;
+}
+
+/**
+ * read_u32_prop() - Read an u32 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ */
+static void read_u32_prop(ofnode node, char *name, size_t count, u32 *dst)
+{
+ if (count == 0)
+ ofnode_read_u32(node, name, dst);
+ else
+ ofnode_read_u32_array(node, name, dst, count);
+}
+
+/**
+ * read_string_prop() - Read a string property from devicetree
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: Size of the destination buffer
+ * @dst: Pointe
[PATCH v4 1/3] arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
Reviewed-by: Simon Glass
Tested on coral:
Tested-by: Simon Glass
---
Changes in v4:
Fix comment alignment
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 46 ++---
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 7ef169b147..be283818e3 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -327,28 +327,32 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
{
struct fsp_s_config *cfg = >config;
struct apl_config *apl;
- struct binman_entry vbt;
- void *buf;
- int ret;
-
- ret = binman_entry_find("intel-vbt", );
- if (ret)
- return log_msg_ret("Cannot find VBT", ret);
- vbt.image_pos += rom_offset;
- buf = malloc(vbt.size);
- if (!buf)
- return log_msg_ret("Alloc VBT", -ENOMEM);
- /*
-* Load VBT before devicetree-specific config. This only supports
-* memory-mapped SPI at present.
-*/
- bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
- memcpy(buf, (void *)vbt.image_pos, vbt.size);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
- if (*(u32 *)buf != VBT_SIGNATURE)
- return log_msg_ret("VBT signature", -EINVAL);
- cfg->graphics_config_ptr = (ulong)buf;
+ if (IS_ENABLED(CONFIG_HAVE_VBT)) {
+ struct binman_entry vbt;
+ void *vbt_buf;
+ int ret;
+
+ ret = binman_entry_find("intel-vbt", );
+ if (ret)
+ return log_msg_ret("Cannot find VBT", ret);
+ vbt.image_pos += rom_offset;
+ vbt_buf = malloc(vbt.size);
+ if (!vbt_buf)
+ return log_msg_ret("Alloc VBT", -ENOMEM);
+
+ /*
+* Load VBT before devicetree-specific config. This only
+* supports memory-mapped SPI at present.
+*/
+ bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
+ memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
+ if (*(u32 *)vbt_buf != VBT_SIGNATURE)
+ return log_msg_ret("VBT signature", -EINVAL);
+
+ cfg->graphics_config_ptr = (ulong)vbt_buf;
+ }
apl = malloc(sizeof(*apl));
if (!apl)
--
2.26.0
[PATCH v4 0/3] Move FSP configuration to devicetree
This patch series moves the configuration of FPS-S and FSP-M for Apollo Lake based SoCs from the code to the devicetree. In order to make the FSP configuration easy to extend and maintain new binding structs for FSP-M and FSP-S are introduced. These structs contain the information of which devicetree settings need to be copied to which offset in the FSP config structure. The actual code handling these structs is rather small, and generic for both FSP-S and FSP-M. This patch series replaces the previous sent patches: "arch: x86: apl: Read FSP-M configuration from device-tree" [1] "Move FSP-S configuration to device-tree" [2] Changes to [1] and [2]: - No default settings within U-Boot, the default settings in FSP are used directly - The code for copying the data was simplified, and the information of what needs to be copied was moved to newly introduced structures [1]: https://lists.denx.de/pipermail/u-boot/2020-April/405852.html [2]: https://lists.denx.de/pipermail/u-boot/2020-April/406590.html Changes in v4: Fix comment alignment Changes in v3: Enable fspm,dual-rank-support-enable on chromebook coral Split patch into FSP-M and FSP-S Split patch into FSP-M and FSP-S Fix #if defined macro for FSP-S path to reduce SPL size Changes in v2: Integration of the review comments Fix swizzle size bug Bernhard Messerklinger (3): arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled arch: x86: apl: Use devicetree for FSP-M configuration arch: x86: apl: Use devicetree for FSP-S configuration arch/x86/cpu/apollolake/Makefile |1 + arch/x86/cpu/apollolake/fsp_bindings.c| 1803 + arch/x86/cpu/apollolake/fsp_m.c | 169 +- arch/x86/cpu/apollolake/fsp_s.c | 430 +--- arch/x86/dts/chromebook_coral.dts | 73 +- .../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 ++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 ++ .../asm/arch-apollolake/fsp_bindings.h| 110 + .../fsp/fsp2/apollolake/fsp-m.txt | 320 +++ .../fsp/fsp2/apollolake/fsp-s.txt | 483 + 10 files changed, 3188 insertions(+), 571 deletions(-) create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt -- 2.26.0
[PATCH v3 0/3] Move FSP configuration to devicetree
This patch series moves the configuration of FPS-S and FSP-M for Apollo Lake based SoCs from the code to the devicetree. In order to make the FSP configuration easy to extend and maintain new binding structs for FSP-M and FSP-S are introduced. These structs contain the information of which devicetree settings need to be copied to which offset in the FSP config structure. The actual code handling these structs is rather small, and generic for both FSP-S and FSP-M. This patch series replaces the previous sent patches: "arch: x86: apl: Read FSP-M configuration from device-tree" [1] "Move FSP-S configuration to device-tree" [2] Changes to [1] and [2]: - No default settings within U-Boot, the default settings in FSP are used directly - The code for copying the data was simplified, and the information of what needs to be copied was moved to newly introduced structures [1]: https://lists.denx.de/pipermail/u-boot/2020-April/405852.html [2]: https://lists.denx.de/pipermail/u-boot/2020-April/406590.html Changes in v3: Enable fspm,dual-rank-support-enable on chromebook coral Split patch into FSP-M and FSP-S Split patch into FSP-M and FSP-S Fix #if defined macro for FSP-S path to reduce SPL size Changes in v2: Integration of the review comments Fix swizzle size bug Bernhard Messerklinger (3): arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled arch: x86: apl: Use devicetree for FSP-M configuration arch: x86: apl: Use devicetree for FSP-S configuration arch/x86/cpu/apollolake/Makefile |1 + arch/x86/cpu/apollolake/fsp_bindings.c| 1803 + arch/x86/cpu/apollolake/fsp_m.c | 169 +- arch/x86/cpu/apollolake/fsp_s.c | 430 +--- arch/x86/dts/chromebook_coral.dts | 73 +- .../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 ++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 ++ .../asm/arch-apollolake/fsp_bindings.h| 110 + .../fsp/fsp2/apollolake/fsp-m.txt | 320 +++ .../fsp/fsp2/apollolake/fsp-s.txt | 483 + 10 files changed, 3188 insertions(+), 571 deletions(-) create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt -- 2.26.0
[PATCH v3 2/3] arch: x86: apl: Use devicetree for FSP-M configuration
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard Messerklinger
---
Changes in v3:
Enable fspm,dual-rank-support-enable on chromebook coral
Split patch into FSP-M and FSP-S
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/fsp_bindings.c| 614 ++
arch/x86/cpu/apollolake/fsp_m.c | 169 +
arch/x86/dts/chromebook_coral.dts | 38 +-
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 +
.../asm/arch-apollolake/fsp_bindings.h| 96 +++
.../fsp/fsp2/apollolake/fsp-m.txt | 320 +
7 files changed, 1242 insertions(+), 164 deletions(-)
create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 578e15c4bf..3aa2a55676 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -10,6 +10,7 @@ obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
obj-y += cpu.o
obj-y += punit.o
+obj-y += fsp_bindings.o
ifdef CONFIG_SPL_BUILD
obj-y += fsp_m.o
endif
diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c
b/arch/x86/cpu/apollolake/fsp_bindings.c
new file mode 100644
index 00..34131e1108
--- /dev/null
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 B Industrial Automation GmbH - http://www.br-automation.com
+ */
+
+#include
+#include
+#include
+
+/**
+ * read_u8_prop() - Read an u8 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * Set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ */
+static void read_u8_prop(ofnode node, char *name, size_t count, u8 *dst)
+{
+ u32 tmp;
+ const u8 *buf;
+ int ret;
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, );
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ buf = ofnode_read_u8_array_ptr(node, name, count);
+ if (buf)
+ memcpy(dst, buf, count);
+ }
+}
+
+/**
+ * read_u16_prop() - Read an u16 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * Set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ * @return 0 on success, -ve on error
+ */
+static int read_u16_prop(ofnode node, char *name, size_t count, u16 *dst)
+{
+ u32 tmp;
+ u32 buf[32];
+ int ret;
+
+ if (ARRAY_SIZE(buf) < count) {
+ debug("ERROR: %s buffer to small!\n", __func__);
+ return -ENOSPC;
+ }
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, );
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ ret = ofnode_read_u32_array(node, name, buf, count);
+ if (ret == 0)
+ for (int i = 0; i < count; i++)
+ dst[i] = buf[i];
+ }
+
+ return 0;
+}
+
+/**
+ * read_u32_prop() - Read an u32 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ */
+static void read_u32_prop(ofnode node, char *name, size_t count, u32 *dst)
+{
+ if (count == 0)
+ ofnode_read_u32(node, name, dst);
+ else
+ ofnode_read_u32_array(node, name, dst, count);
+}
+
+/**
+ * read_string_prop() - Read a string property from devicetree
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: Size of the destination buffer
+ * @dst: Pointer to destination of where to save the values read
+ * from devicetree
+
[PATCH v3 3/3] arch: x86: apl: Use devicetree for FSP-S configuration
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard Messerklinger
---
Changes in v3:
Split patch into FSP-M and FSP-S
Fix #if defined macro for FSP-S path to reduce SPL size
Changes in v2:
Integration of the review comments
Fix swizzle size bug
arch/x86/cpu/apollolake/fsp_bindings.c| 1189 +
arch/x86/cpu/apollolake/fsp_s.c | 386 +-
arch/x86/dts/chromebook_coral.dts | 35 +-
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 +++
.../asm/arch-apollolake/fsp_bindings.h| 14 +
.../fsp/fsp2/apollolake/fsp-s.txt | 483 +++
6 files changed, 1922 insertions(+), 387 deletions(-)
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c
b/arch/x86/cpu/apollolake/fsp_bindings.c
index 34131e1108..501cbb7ef3 100644
--- a/arch/x86/cpu/apollolake/fsp_bindings.c
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -612,3 +612,1192 @@ int fsp_m_update_config_from_dtb(ofnode node, struct
fsp_m_config *cfg)
return fsp_update_config_from_dtb(node, (u8 *)cfg, fsp_m_bindings);
}
#endif
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+const struct fsp_binding fsp_s_bindings[] = {
+ {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, active_processor_cores),
+ .propname = "fsps,active-processor-cores",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, disable_core1),
+ .propname = "fsps,disable-core1",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, disable_core2),
+ .propname = "fsps,disable-core2",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, disable_core3),
+ .propname = "fsps,disable-core3",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, vmx_enable),
+ .propname = "fsps,vmx-enable",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, proc_trace_mem_size),
+ .propname = "fsps,proc-trace-mem-size",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, proc_trace_enable),
+ .propname = "fsps,proc-trace-enable",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, eist),
+ .propname = "fsps,eist",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, boot_p_state),
+ .propname = "fsps,boot-p-state",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, enable_cx),
+ .propname = "fsps,enable-cx",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, c1e),
+ .propname = "fsps,c1e",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, bi_proc_hot),
+ .propname = "fsps,bi-proc-hot",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, pkg_c_state_limit),
+ .propname = "fsps,pkg-c-state-limit",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, c_state_auto_demotion),
+ .propname = "fsps,c-state-auto-demotion",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, c_state_un_demotion),
+ .propname = "fsps,c-state-un-demotion",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, max_core_c_state),
+ .propname = "fsps,max-core-c-state",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, pkg_c_state_demotion),
+ .propname = "fsps,pkg-c-state-demotion",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, pkg_c_state_un_demotion),
+ .propname = "fsps,pkg-c-state-un-demotion",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, turbo_mode),
+ .propname = "fsps,turbo-mode",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, hda_verb_table_entry_num),
+ .propname = "fsps,hda-verb-table-entry-num",
+ }, {
+ .type = FSP_UINT32,
+ .offset = offsetof(struct fsp_s_config, hda_verb_table_ptr),
+ .propname = "fsps,hda-verb-table-ptr",
+ }, {
+ .type = FSP_UINT8,
+ .offset = offsetof(struct fsp_s_config, p2sb_unhide),
+ .propname =
[PATCH v3 1/3] arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 46 ++---
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 7ef169b147..9b13b16eaf 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -327,28 +327,32 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
{
struct fsp_s_config *cfg = >config;
struct apl_config *apl;
- struct binman_entry vbt;
- void *buf;
- int ret;
-
- ret = binman_entry_find("intel-vbt", );
- if (ret)
- return log_msg_ret("Cannot find VBT", ret);
- vbt.image_pos += rom_offset;
- buf = malloc(vbt.size);
- if (!buf)
- return log_msg_ret("Alloc VBT", -ENOMEM);
- /*
-* Load VBT before devicetree-specific config. This only supports
-* memory-mapped SPI at present.
-*/
- bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
- memcpy(buf, (void *)vbt.image_pos, vbt.size);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
- if (*(u32 *)buf != VBT_SIGNATURE)
- return log_msg_ret("VBT signature", -EINVAL);
- cfg->graphics_config_ptr = (ulong)buf;
+ if (IS_ENABLED(CONFIG_HAVE_VBT)) {
+ struct binman_entry vbt;
+ void *vbt_buf;
+ int ret;
+
+ ret = binman_entry_find("intel-vbt", );
+ if (ret)
+ return log_msg_ret("Cannot find VBT", ret);
+ vbt.image_pos += rom_offset;
+ vbt_buf = malloc(vbt.size);
+ if (!vbt_buf)
+ return log_msg_ret("Alloc VBT", -ENOMEM);
+
+ /*
+ * Load VBT before devicetree-specific config. This only supports
+ * memory-mapped SPI at present.
+ */
+ bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
+ memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
+ if (*(u32 *)vbt_buf != VBT_SIGNATURE)
+ return log_msg_ret("VBT signature", -EINVAL);
+
+ cfg->graphics_config_ptr = (ulong)vbt_buf;
+ }
apl = malloc(sizeof(*apl));
if (!apl)
--
2.26.0
[PATCH v2 2/2] arch: x86: apl: Use devicetree for FSP configuration
A the moment the FSP configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M and FSP-S full configurable from devicetree by
adding binding properties for all FSP parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard Messerklinger
---
Changes in v2:
Integration of the review comments
Fix swizzle size bug
arch/x86/cpu/apollolake/Makefile |1 +
arch/x86/cpu/apollolake/fsp_bindings.c| 1803 +
arch/x86/cpu/apollolake/fsp_m.c | 169 +-
arch/x86/cpu/apollolake/fsp_s.c | 386 +---
arch/x86/dts/chromebook_coral.dts | 72 +-
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 ++
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 ++
.../asm/arch-apollolake/fsp_bindings.h| 110 +
.../fsp/fsp2/apollolake/fsp-m.txt | 320 +++
.../fsp/fsp2/apollolake/fsp-s.txt | 483 +
10 files changed, 3163 insertions(+), 551 deletions(-)
create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 578e15c4bf..3aa2a55676 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -10,6 +10,7 @@ obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
obj-y += cpu.o
obj-y += punit.o
+obj-y += fsp_bindings.o
ifdef CONFIG_SPL_BUILD
obj-y += fsp_m.o
endif
diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c
b/arch/x86/cpu/apollolake/fsp_bindings.c
new file mode 100644
index 00..84d48dbeff
--- /dev/null
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -0,0 +1,1803 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 B Industrial Automation GmbH - http://www.br-automation.com
+ */
+
+#include
+#include
+#include
+
+/**
+ * read_u8_prop() - Read an u8 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * Set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ */
+static void read_u8_prop(ofnode node, char *name, size_t count, u8 *dst)
+{
+ u32 tmp;
+ const u8 *buf;
+ int ret;
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, );
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ buf = ofnode_read_u8_array_ptr(node, name, count);
+ if (buf)
+ memcpy(dst, buf, count);
+ }
+}
+
+/**
+ * read_u16_prop() - Read an u16 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * Set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ * @return 0 on success, -ve on error
+ */
+static int read_u16_prop(ofnode node, char *name, size_t count, u16 *dst)
+{
+ u32 tmp;
+ u32 buf[32];
+ int ret;
+
+ if (ARRAY_SIZE(buf) < count) {
+ debug("ERROR: %s buffer to small!\n", __func__);
+ return -ENOSPC;
+ }
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, );
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ ret = ofnode_read_u32_array(node, name, buf, count);
+ if (ret == 0)
+ for (int i = 0; i < count; i++)
+ dst[i] = buf[i];
+ }
+
+ return 0;
+}
+
+/**
+ * read_u32_prop() - Read an u32 property from devicetree (scalar or array)
+ * @node: Valid node reference to read property from
+ * @name: Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ * number of expected elements
+ * set to 0 if the property is expected to be a scalar
+ * @dst: Pointer to destination of where to save the value(s) read
+ * from devicetree
+ */
+static void read_u32_prop(ofnode node, char *name, size_t count, u32 *dst)
+{
+ if (count == 0)
+ ofnode_read_u32(node, name, dst);
+ else
+ ofnode_read_u32_array(node, name, dst, count);
+}
+
+/**
+ * read_string_prop() - Read a string property from devicetree
+ * @node: Valid node reference to read propert
[PATCH v2 0/2] Move FSP configuration to devicetree
This patch series moves the configuration of FPS-S and FSP-M for Apollo Lake based SoCs from the code to the devicetree. In order to make the FSP configuration easy to extend and maintain new binding structs for FSP-M and FSP-S are introduced. These structs contain the information of which devicetree settings need to be copied to which offset in the FSP config structure. The actual code handling these structs is rather small, and generic for both FSP-S and FSP-M. This patch series replaces the previous sent patches: "arch: x86: apl: Read FSP-M configuration from device-tree" [1] "Move FSP-S configuration to device-tree" [2] Changes to [1] and [2]: - No default settings within U-Boot, the default settings in FSP are used directly - The code for copying the data was simplified, and the information of what needs to be copied was moved to newly introduced structures [1]: https://lists.denx.de/pipermail/u-boot/2020-April/405852.html [2]: https://lists.denx.de/pipermail/u-boot/2020-April/406590.html Changes in v2: Integration of the review comments Fix swizzle size bug Bernhard Messerklinger (2): arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled arch: x86: apl: Use devicetree for FSP configuration arch/x86/cpu/apollolake/Makefile |1 + arch/x86/cpu/apollolake/fsp_bindings.c| 1803 + arch/x86/cpu/apollolake/fsp_m.c | 169 +- arch/x86/cpu/apollolake/fsp_s.c | 430 +--- arch/x86/dts/chromebook_coral.dts | 72 +- .../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 ++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 ++ .../asm/arch-apollolake/fsp_bindings.h| 110 + .../fsp/fsp2/apollolake/fsp-m.txt | 320 +++ .../fsp/fsp2/apollolake/fsp-s.txt | 483 + 10 files changed, 3187 insertions(+), 571 deletions(-) create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt -- 2.26.0
[PATCH v2 1/2] arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 46 ++---
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 17cf1682ad..583259bf90 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -327,28 +327,32 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
{
struct fsp_s_config *cfg = >config;
struct apl_config *apl;
- struct binman_entry vbt;
- void *buf;
- int ret;
-
- ret = binman_entry_find("intel-vbt", );
- if (ret)
- return log_msg_ret("Cannot find VBT", ret);
- vbt.image_pos += rom_offset;
- buf = malloc(vbt.size);
- if (!buf)
- return log_msg_ret("Alloc VBT", -ENOMEM);
- /*
-* Load VBT before devicetree-specific config. This only supports
-* memory-mapped SPI at present.
-*/
- bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
- memcpy(buf, (void *)vbt.image_pos, vbt.size);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
- if (*(u32 *)buf != VBT_SIGNATURE)
- return log_msg_ret("VBT signature", -EINVAL);
- cfg->graphics_config_ptr = (ulong)buf;
+ if (IS_ENABLED(CONFIG_HAVE_VBT)) {
+ struct binman_entry vbt;
+ void *vbt_buf;
+ int ret;
+
+ ret = binman_entry_find("intel-vbt", );
+ if (ret)
+ return log_msg_ret("Cannot find VBT", ret);
+ vbt.image_pos += rom_offset;
+ vbt_buf = malloc(vbt.size);
+ if (!vbt_buf)
+ return log_msg_ret("Alloc VBT", -ENOMEM);
+
+ /*
+ * Load VBT before devicetree-specific config. This only supports
+ * memory-mapped SPI at present.
+ */
+ bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
+ memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
+ if (*(u32 *)vbt_buf != VBT_SIGNATURE)
+ return log_msg_ret("VBT signature", -EINVAL);
+
+ cfg->graphics_config_ptr = (ulong)vbt_buf;
+ }
apl = malloc(sizeof(*apl));
if (!apl)
--
2.26.0
Antwort: Re: [RFC PATCH 2/2] arch: x86: apl: Use devicetree for FSP configuration
Hi Simon, >Hi Bernhard, > >On Thu, 30 Apr 2020 at 03:16, Bernhard Messerklinger > wrote: >> >> A the moment the FSP configuration is a mix of hard coded values >and >> devicetree properties. >> This patch makes FSP-M and FSP-S full configurable from devicetree >by >> adding binding properties for all FSP parameters. >> >> Co-developed-by: Wolfgang Wallner > >> Signed-off-by: Wolfgang Wallner > >> Signed-off-by: Bernhard Messerklinger > >> >> --- >> >> arch/x86/cpu/apollolake/Makefile |1 + >> arch/x86/cpu/apollolake/fsp_bindings.c| 2096 >+ >> arch/x86/cpu/apollolake/fsp_m.c | 164 +- >> arch/x86/cpu/apollolake/fsp_s.c | 382 +-- >> arch/x86/dts/chromebook_coral.dts | 72 +- >> .../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 ++ >> .../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 ++ >> .../asm/arch-apollolake/fsp_bindings.h| 74 + >> .../fsp/fsp2/apollolake/fsp-m.txt | 320 +++ >> .../fsp/fsp2/apollolake/fsp-s.txt | 483 >> 10 files changed, 3422 insertions(+), 540 deletions(-) >> create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c >> create mode 100644 >arch/x86/include/asm/arch-apollolake/fsp_bindings.h >> create mode 100644 >doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt >> create mode 100644 >doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt >> > >Tested on coral: >Tested-by: Simon Glass > >This looks good to me. I wonder if one day the binding table could be >created from the binding .txt file, or compared with it >programmatically? Yes that's true. But at the moment its just copy paste. I generated the binding table from the fsp_s and fsp_m config struct with a python script. But this script is also far from being finished. > ... >> +#if defined(CONFIG_SPL_BUILD) > >Do you need these #ifs? I would hope the compiler would only include >them if needed. Without the #ifs the SPL size stays the same but the u-boot proper size increases by about 2 kb. > ... >> +void fsp_s_update_config_from_dtb(ofnode node, struct fsp_s_config >*cfg); > >function comments > >Regards, >Simon Regards, Bernhard
Re: [RFC PATCH 1/2] arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Hi Simon,
>Hi Bernhard,
>
>On Thu, 30 Apr 2020 at 03:16, Bernhard Messerklinger
> wrote:
>>
>> Only load VBT if it's present in the u-boot.rom.
>>
>
>I think you can drop the RFC from this series. The approach seems
>good to me.
>
>Also, what APL boards have you tested with?
I tested our custom APL smarc board.
I also have a Oxbow Hill CRB but can't test it there at the moment
(currently I am working from home).
>
>> Signed-off-by: Bernhard Messerklinger
>
>> ---
>>
>> arch/x86/cpu/apollolake/fsp_s.c | 18 --
>> 1 file changed, 8 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/x86/cpu/apollolake/fsp_s.c
>b/arch/x86/cpu/apollolake/fsp_s.c
>> index 17cf1682ad..8f1d6f3008 100644
>> --- a/arch/x86/cpu/apollolake/fsp_s.c
>> +++ b/arch/x86/cpu/apollolake/fsp_s.c
>> @@ -327,16 +327,17 @@ int fsps_update_config(struct udevice *dev,
>ulong rom_offset,
>> {
>> struct fsp_s_config *cfg = >config;
>> struct apl_config *apl;
>> +#ifdef CONFIG_HAVE_VBT
>
>Please use if (IS_ENABLED(CONFIG_HAVE_VBT))
>
>We should try to avoid #ifdef unless needed as it adds different
>build paths.
>
>> struct binman_entry vbt;
>> - void *buf;
>> + void *vbt_buf;
>> int ret;
>>
>> ret = binman_entry_find("intel-vbt", );
>> if (ret)
>> return log_msg_ret("Cannot find VBT", ret);
>> vbt.image_pos += rom_offset;
>> - buf = malloc(vbt.size);
>> - if (!buf)
>> + vbt_buf = malloc(vbt.size);
>> + if (!vbt_buf)
>> return log_msg_ret("Alloc VBT", -ENOMEM);
>>
>> /*
>> @@ -344,16 +345,13 @@ int fsps_update_config(struct udevice *dev,
>ulong rom_offset,
>> * memory-mapped SPI at present.
>> */
>> bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
>> - memcpy(buf, (void *)vbt.image_pos, vbt.size);
>> + memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
>> bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
>> - if (*(u32 *)buf != VBT_SIGNATURE)
>> + if (*(u32 *)vbt_buf != VBT_SIGNATURE)
>> return log_msg_ret("VBT signature", -EINVAL);
>> - cfg->graphics_config_ptr = (ulong)buf;
>>
>> - apl = malloc(sizeof(*apl));
>> - if (!apl)
>> - return log_msg_ret("config", -ENOMEM);
>> - get_config(dev, apl);
>
>Should not drop the above code.
>
>> + cfg->graphics_config_ptr = (ulong)vbt_buf;
>> +#endif
>>
>> cfg->ish_enable = 0;
>> cfg->enable_sata = 0;
>> --
>> 2.26.0
>>
>>
>
>Regards,
>Simon
Regards,
Bernhard
[RFC PATCH 2/2] arch: x86: apl: Use devicetree for FSP configuration
A the moment the FSP configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M and FSP-S full configurable from devicetree by
adding binding properties for all FSP parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/Makefile |1 +
arch/x86/cpu/apollolake/fsp_bindings.c| 2096 +
arch/x86/cpu/apollolake/fsp_m.c | 164 +-
arch/x86/cpu/apollolake/fsp_s.c | 382 +--
arch/x86/dts/chromebook_coral.dts | 72 +-
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 ++
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 ++
.../asm/arch-apollolake/fsp_bindings.h| 74 +
.../fsp/fsp2/apollolake/fsp-m.txt | 320 +++
.../fsp/fsp2/apollolake/fsp-s.txt | 483
10 files changed, 3422 insertions(+), 540 deletions(-)
create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 578e15c4bf..3aa2a55676 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -10,6 +10,7 @@ obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
obj-y += cpu.o
obj-y += punit.o
+obj-y += fsp_bindings.o
ifdef CONFIG_SPL_BUILD
obj-y += fsp_m.o
endif
diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c
b/arch/x86/cpu/apollolake/fsp_bindings.c
new file mode 100644
index 00..9c10e7328a
--- /dev/null
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -0,0 +1,2096 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 B Industrial Automation GmbH - http://www.br-automation.com
+ */
+
+#include
+#include
+#include
+
+static void read_u8_prop(ofnode node, u8 *dst, char *name, size_t count)
+{
+ u32 tmp;
+ const u8 *buf;
+ int ret;
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, );
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ buf = ofnode_read_u8_array_ptr(node, name, count);
+ if (buf)
+ memcpy(dst, buf, count);
+ }
+}
+
+static void read_u16_prop(ofnode node, u16 *dst, char *name, size_t count)
+{
+ u32 tmp;
+ u32 buf[32];
+ int ret;
+
+ if (ARRAY_SIZE(buf) < count) {
+ printf("ERROR: %s buffer to small!\n", __func__);
+ return;
+ }
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, );
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ ret = ofnode_read_u32_array(node, name, buf, count);
+ if (ret == 0)
+ for (int i = 0; i < count; i++)
+ dst[i] = buf[i];
+ }
+}
+
+static void read_u32_prop(ofnode node, u32 *dst, char *name, size_t count)
+{
+ if (count == 0)
+ ofnode_read_u32(node, name, dst);
+ else
+ ofnode_read_u32_array(node, name, dst, count);
+}
+
+static void read_string_prop(ofnode node, char *dst, char *name, int count)
+{
+ const char *string_buf;
+
+ if (count > 0) {
+ string_buf = ofnode_read_string(node, name);
+ if (string_buf) {
+ strncpy(dst, string_buf, count);
+ dst[count - 1] = '\0';
+ }
+ }
+}
+
+static void read_swizzle_prop(ofnode node, u8 *dst, char *name, int count)
+{
+ const struct lpddr4_chan_swizzle_cfg *sch;
+ /* Number of bytes to copy per DQS */
+ const size_t sz = DQ_BITS_PER_DQS;
+ const struct lpddr4_swizzle_cfg *swizzle_cfg;
+
+ swizzle_cfg = (const struct lpddr4_swizzle_cfg *)
+ ofnode_read_u8_array_ptr(node, name, count);
+
+ if (!swizzle_cfg)
+ return;
+ /*
+* CH0_DQB byte lanes in the bit swizzle configuration field are
+* not 1:1. The mapping within the swizzling field is:
+* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
+* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
+* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
+*/
+ sch = _cfg->phys[LP4_PHYS_CH0B];
+ memcpy([0 * DQ_BITS_PER_DQS], >dqs[LP4_DQS1], sz);
+ memcpy([1 * DQ_BITS_PER_DQS], >dqs[LP4_DQS0], sz);
+ memcpy([2 * DQ_BITS_PER_DQS], >dqs[LP4_DQS3], sz);
+ memcpy([3 * DQ_BITS_PER_DQS], >dqs[LP4_DQS2], sz);
+
+ /*
+* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
+*/
+
Re: [RFC PATCH v3] arch: x86: apl: Read FSP-M configuration from device-tree
Hi Bin, Simon, > >Move FSP-M configuration to the device-tree like it's already done >for >other SoCs (Baytrail). > >Signed-off-by: Bernhard Messerklinger > >--- >With this patch I moved the FSP-M configuration to the device-tree >based >on the Baytrail boards. > >Changes in v3: >Added doc binding file >Added fspm prefix to some variables > >Changes in v2: >Added commit notes > ... Please drop this series. This series is superseded by: "Move FSP configuration to devicetree" [1] [1]: https://lists.denx.de/pipermail/u-boot/2020-April/409505.html Regards, Bernhard
Re: [RFC PATCH v2 0/2] Move FSP-S configuration to device-tree
Hi Bin, Simon, >This patch series moves the configuration of FPS-S for Apollo Lake >based SoCs from the code to the device-tree. > >This is similar to the previous patch series for FSP-M. >If wanted, I can also send FSP-M and FSP-S patch as a single series. > Please drop this series. This series is superseded by: "Move FSP configuration to devicetree" [1] [1]: https://lists.denx.de/pipermail/u-boot/2020-April/409505.html >Changes in v2: >Remove FSP-M binding file > >Bernhard Messerklinger (2): > arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled > arch: x86: apl: Read FSP-S configuration from device-tree > > arch/x86/cpu/apollolake/fsp_s.c | 1084 >+++-- > arch/x86/dts/chromebook_coral.dts | 35 +- > .../asm/arch-apollolake/fsp/fsp_s_upd.h | 268 > .../fsp/fsp2/apollolake/fsp-s.txt | 485 > 4 files changed, 1497 insertions(+), 375 deletions(-) > create mode 100644 >doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt > >-- >2.26.0 > > Regards, Bernhard
[RFC PATCH 0/2] Move FSP configuration to devicetree
This patch series moves the configuration of FPS-S and FSP-M for Apollo Lake based SoCs from the code to the devicetree. In order to make the FSP configuration easy to extend and maintain new binding structs for FSP-M and FSP-S are introduced. These structs contain the information of which devicetree settings need to be copied to which offset in the FSP config structure. The actual code handling these structs is rather small, and generic for both FSP-S and FSP-M. This patch series replaces the previous sent patches: "arch: x86: apl: Read FSP-M configuration from device-tree" [1] "Move FSP-S configuration to device-tree" [2] Changes to [1] and [2]: - No default settings within U-Boot, the default settings in FSP are used directly - The code for copying the data was simplified, and the information of what needs to be copied was moved to newly introduced structures [1]: https://lists.denx.de/pipermail/u-boot/2020-April/405852.html [2]: https://lists.denx.de/pipermail/u-boot/2020-April/406590.html Bernhard Messerklinger (2): arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled arch: x86: apl: Use devicetree for FSP configuration arch/x86/cpu/apollolake/Makefile |1 + arch/x86/cpu/apollolake/fsp_bindings.c| 2096 + arch/x86/cpu/apollolake/fsp_m.c | 164 +- arch/x86/cpu/apollolake/fsp_s.c | 404 +--- arch/x86/dts/chromebook_coral.dts | 72 +- .../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 ++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 ++ .../asm/arch-apollolake/fsp_bindings.h| 74 + .../fsp/fsp2/apollolake/fsp-m.txt | 320 +++ .../fsp/fsp2/apollolake/fsp-s.txt | 483 10 files changed, 3432 insertions(+), 552 deletions(-) create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt -- 2.26.0
[RFC PATCH 1/2] arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 17cf1682ad..8f1d6f3008 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -327,16 +327,17 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
{
struct fsp_s_config *cfg = >config;
struct apl_config *apl;
+#ifdef CONFIG_HAVE_VBT
struct binman_entry vbt;
- void *buf;
+ void *vbt_buf;
int ret;
ret = binman_entry_find("intel-vbt", );
if (ret)
return log_msg_ret("Cannot find VBT", ret);
vbt.image_pos += rom_offset;
- buf = malloc(vbt.size);
- if (!buf)
+ vbt_buf = malloc(vbt.size);
+ if (!vbt_buf)
return log_msg_ret("Alloc VBT", -ENOMEM);
/*
@@ -344,16 +345,13 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
* memory-mapped SPI at present.
*/
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
- memcpy(buf, (void *)vbt.image_pos, vbt.size);
+ memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
- if (*(u32 *)buf != VBT_SIGNATURE)
+ if (*(u32 *)vbt_buf != VBT_SIGNATURE)
return log_msg_ret("VBT signature", -EINVAL);
- cfg->graphics_config_ptr = (ulong)buf;
- apl = malloc(sizeof(*apl));
- if (!apl)
- return log_msg_ret("config", -ENOMEM);
- get_config(dev, apl);
+ cfg->graphics_config_ptr = (ulong)vbt_buf;
+#endif
cfg->ish_enable = 0;
cfg->enable_sata = 0;
--
2.26.0
Re: Re: Re: [RFC PATCH v2 2/2] arch: x86: apl: Read FSP-S configuration from device-tree
Hi Simon,
>
>Hi Bernhard,
>
>On Mon, 20 Apr 2020 at 07:11, Bernhard Messerklinger
> wrote:
>>
>> Hi Simon,
>>
>> >Hi Bernhard,
>> >
>> >On Tue, 14 Apr 2020 at 03:26, Bernhard Messerklinger
>> > wrote:
>> >>
>> >> Move FSP-S configuration to the device-tree like it's already
>done
>> >for
>> >> other SoCs (Baytrail).
>> >>
>> >> Signed-off-by: Bernhard Messerklinger
>> >
>> >> ---
>> >>
>> >> Changes in v2:
>> >> Remove FSP-M binding file
>> >>
>> >> arch/x86/cpu/apollolake/fsp_s.c | 1070
>> >+++--
>> >> arch/x86/dts/chromebook_coral.dts | 35 +-
>> >> .../asm/arch-apollolake/fsp/fsp_s_upd.h | 268 +
>> >> .../fsp/fsp2/apollolake/fsp-s.txt | 485
>> >> 4 files changed, 1489 insertions(+), 369 deletions(-)
>> >> create mode 100644
>> >doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
>> >
>> >Tested on chromebook-coral:
>> >Tested-by: Simon Glass
>> >
>> >>
>> >> diff --git a/arch/x86/cpu/apollolake/fsp_s.c
>> >b/arch/x86/cpu/apollolake/fsp_s.c
>> >> index 458825bc49..7d516adc92 100644
>> >> --- a/arch/x86/cpu/apollolake/fsp_s.c
>> >> +++ b/arch/x86/cpu/apollolake/fsp_s.c
>> >[..]
>> >
>> >> +
>> >> +const u8 pcie_rp_clk_req_number_def[6] = { 0x4, 0x5, 0x0, 0x1,
>> >0x2, 0x3 };
>> >> +const u8 physical_slot_number_def[6] = { 0x0, 0x1, 0x2, 0x3,
>0x4,
>> >0x5 };
>> >> +const u8 ipc_def[16] = { 0xf8, 0xef, 0xff, 0xff, 0xff, 0xff,
>0xff,
>> >0xff, 0xff,
>> >> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
>};
>> >> +const u8 port_usb20_per_port_pe_txi_set_def[8] = { 0x07, 0x06,
>> >0x06, 0x06, 0x07,
>> >> + 0x07, 0x07,
>0x01
>> >};
>> >> +const u8 port_usb20_per_port_txi_set_def[8] = { 0x00, 0x00,
>0x00,
>> >0x00, 0x00,
>> >> + 0x00, 0x00,
>0x03};
>> >> +const u8 port_usb20_hs_skew_sel_def[8] = { 0x00, 0x00, 0x00,
>0x00,
>> >0x00, 0x00,
>> >> + 0x00, 0x01 };
>> >> +const u8 port_usb20_i_usb_tx_emphasis_en_def[8] = { 0x03, 0x03,
>> >0x03, 0x03,
>> >> + 0x03, 0x03,
>> >0x03, 0x01 };
>> >> +const u8 port_usb20_hs_npre_drv_sel_def[8] = { 0x00, 0x00,
>0x00,
>> >0x00, 0x00,
>> >> + 0x00, 0x00, 0x03
>};
>> >
>> >Do we actually need these, or does the FSP have these defaults in
>the
>> >right place anyway?
>>
>> The FSP would already have these default values included.
>> Whether we use them or not is a design decision.
>>
>> My current approach tries the following:
>> * only non-default values should require a devicetree entry
>> * boolean FSP parameters are implemented with boolean
>>devicetree properties
>>
>> A limitation for boolean properties in devicetree is that they
>> are true when they are present, and false when they are not
>> present. But it is not possible to leave them out and use some
>> default value in this case.
>>
>> --> For boolean properties, this patch uses the devicetree value
>> (either the entry is present or it is not present)
>> unconditionally and overwrites any default values included
>> in the FSP.
>
>I think it would be better to use int properties for the booleans.
>Perhaps we can add a new dev_read_opt_bool() to handle it.
>
>>
>> Non-boolean devicetree properties on the other hand support
>> default values. But it needs to be decided where these default
>> values should come from:
>>
>>a) from the default values within FSP
>>b) from default values within U-Boot
>
>OK. I had assumed that U-Boot itself wouldn't have any particular
>defaults.
>
>>
>> I have implemented option b) in this patch, as for this option
>> we don't rely on other tools to configure FSP default values
>> and IMHO it feels slightly more consistent with how boolean
>> properties are handled.
>> This is why the variables above are defined.
>>
>> But I have no strong opinion on this topic, and could implement
&
Antwort: Re: [RFC PATCH v2 2/2] arch: x86: apl: Read FSP-S configuration from device-tree
Hi Simon,
>Hi Bernhard,
>
>On Tue, 14 Apr 2020 at 03:26, Bernhard Messerklinger
> wrote:
>>
>> Move FSP-S configuration to the device-tree like it's already done
>for
>> other SoCs (Baytrail).
>>
>> Signed-off-by: Bernhard Messerklinger
>
>> ---
>>
>> Changes in v2:
>> Remove FSP-M binding file
>>
>> arch/x86/cpu/apollolake/fsp_s.c | 1070
>+++--
>> arch/x86/dts/chromebook_coral.dts | 35 +-
>> .../asm/arch-apollolake/fsp/fsp_s_upd.h | 268 +
>> .../fsp/fsp2/apollolake/fsp-s.txt | 485
>> 4 files changed, 1489 insertions(+), 369 deletions(-)
>> create mode 100644
>doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
>
>Tested on chromebook-coral:
>Tested-by: Simon Glass
>
>>
>> diff --git a/arch/x86/cpu/apollolake/fsp_s.c
>b/arch/x86/cpu/apollolake/fsp_s.c
>> index 458825bc49..7d516adc92 100644
>> --- a/arch/x86/cpu/apollolake/fsp_s.c
>> +++ b/arch/x86/cpu/apollolake/fsp_s.c
>[..]
>
>> +
>> +const u8 pcie_rp_clk_req_number_def[6] = { 0x4, 0x5, 0x0, 0x1,
>0x2, 0x3 };
>> +const u8 physical_slot_number_def[6] = { 0x0, 0x1, 0x2, 0x3, 0x4,
>0x5 };
>> +const u8 ipc_def[16] = { 0xf8, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff,
>0xff, 0xff,
>> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
>> +const u8 port_usb20_per_port_pe_txi_set_def[8] = { 0x07, 0x06,
>0x06, 0x06, 0x07,
>> + 0x07, 0x07, 0x01
>};
>> +const u8 port_usb20_per_port_txi_set_def[8] = { 0x00, 0x00, 0x00,
>0x00, 0x00,
>> + 0x00, 0x00, 0x03};
>> +const u8 port_usb20_hs_skew_sel_def[8] = { 0x00, 0x00, 0x00, 0x00,
>0x00, 0x00,
>> + 0x00, 0x01 };
>> +const u8 port_usb20_i_usb_tx_emphasis_en_def[8] = { 0x03, 0x03,
>0x03, 0x03,
>> + 0x03, 0x03,
>0x03, 0x01 };
>> +const u8 port_usb20_hs_npre_drv_sel_def[8] = { 0x00, 0x00, 0x00,
>0x00, 0x00,
>> + 0x00, 0x00, 0x03 };
>
>Do we actually need these, or does the FSP have these defaults in the
>right place anyway?
The FSP would already have these default values included.
Whether we use them or not is a design decision.
My current approach tries the following:
* only non-default values should require a devicetree entry
* boolean FSP parameters are implemented with boolean
devicetree properties
A limitation for boolean properties in devicetree is that they
are true when they are present, and false when they are not
present. But it is not possible to leave them out and use some
default value in this case.
--> For boolean properties, this patch uses the devicetree value
(either the entry is present or it is not present)
unconditionally and overwrites any default values included
in the FSP.
Non-boolean devicetree properties on the other hand support
default values. But it needs to be decided where these default
values should come from:
a) from the default values within FSP
b) from default values within U-Boot
I have implemented option b) in this patch, as for this option
we don't rely on other tools to configure FSP default values
and IMHO it feels slightly more consistent with how boolean
properties are handled.
This is why the variables above are defined.
But I have no strong opinion on this topic, and could implement
it differently depending on the feedback I receive.
Open questions:
* Should boolean properties of the FSP be implemented by
boolean devicetree properties? The alternative would be
to use u32 for everything.
advantage: support for default values
drawback: devicetree gets bigger
* For non-boolean properties: Should the default value from
FSP be used, or a default value defined in U-Boot?
Feedback on these questions would be appreciated.
>>> +
>> +static int read_u8_array(u8 prop[], ofnode node, const char
>*propname, int sz,
>> + u8 def)
>
>Please add function comment
>
>> {
>> const u8 *ptr;
>
>[..]
>
>
>> + ptr = ofnode_read_u8_array_ptr(node, propname, sz);
>> + if (ptr) {
>> + memcpy(prop, ptr, sz);
>> + } else {
>> + memset(prop, def, sz);
>> + return -EINVAL;
>> + }
>>
>> return 0;
>> }
>>
>> -static void apl_fsp_silicon_init_params_cb(struct apl_config *apl,
>> - struct fsp_s_config
>*cfg)
>> +static int read_u16_array
[RFC PATCH v2 0/2] Move FSP-S configuration to device-tree
This patch series moves the configuration of FPS-S for Apollo Lake based SoCs from the code to the device-tree. This is similar to the previous patch series for FSP-M. If wanted, I can also send FSP-M and FSP-S patch as a single series. Changes in v2: Remove FSP-M binding file Bernhard Messerklinger (2): arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled arch: x86: apl: Read FSP-S configuration from device-tree arch/x86/cpu/apollolake/fsp_s.c | 1084 +++-- arch/x86/dts/chromebook_coral.dts | 35 +- .../asm/arch-apollolake/fsp/fsp_s_upd.h | 268 .../fsp/fsp2/apollolake/fsp-s.txt | 485 4 files changed, 1497 insertions(+), 375 deletions(-) create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt -- 2.26.0
[RFC PATCH v2 2/2] arch: x86: apl: Read FSP-S configuration from device-tree
Move FSP-S configuration to the device-tree like it's already done for
other SoCs (Baytrail).
Signed-off-by: Bernhard Messerklinger
---
Changes in v2:
Remove FSP-M binding file
arch/x86/cpu/apollolake/fsp_s.c | 1070 +++--
arch/x86/dts/chromebook_coral.dts | 35 +-
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 268 +
.../fsp/fsp2/apollolake/fsp-s.txt | 485
4 files changed, 1489 insertions(+), 369 deletions(-)
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 458825bc49..7d516adc92 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -27,309 +27,90 @@
#define INTEL_GSPI_MAX 3
#define MAX_USB2_PORTS 8
-enum {
- CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
- CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
-};
-
-/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
-enum serirq_mode {
- SERIRQ_QUIET,
- SERIRQ_CONTINUOUS,
- SERIRQ_OFF,
-};
-
-struct gspi_cfg {
- /* Bus speed in MHz */
- u32 speed_mhz;
- /* Bus should be enabled prior to ramstage with temporary base */
- u8 early_init;
-};
-
-/*
- * This structure will hold data required by common blocks.
- * These are soc specific configurations which will be filled by soc.
- * We'll fill this structure once during init and use the data in common block.
- */
-struct soc_intel_common_config {
- int chipset_lockdown;
- struct gspi_cfg gspi[INTEL_GSPI_MAX];
-};
-
-enum pnp_settings {
- PNP_PERF,
- PNP_POWER,
- PNP_PERF_POWER,
-};
-
-struct usb2_eye_per_port {
- u8 per_port_tx_pe_half;
- u8 per_port_pe_txi_set;
- u8 per_port_txi_set;
- u8 hs_skew_sel;
- u8 usb_tx_emphasis_en;
- u8 per_port_rxi_set;
- u8 hs_npre_drv_sel;
- u8 override_en;
-};
-
-struct apl_config {
- /* Common structure containing soc config data required by common code*/
- struct soc_intel_common_config common_soc_config;
-
- /*
-* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
-* four CLKREQ inputs, but six root ports. Root ports without an
-* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
-*/
- u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
-
- /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
- u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
-
- /* De-emphasis enable configuration for each PCIe root port */
- u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
-
- /*
-* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
-*/
- u32 emmc_tx_cmd_cntl;
-
- /*
-* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
-*/
- u32 emmc_tx_data_cntl1;
-
- /*
-* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
-* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
-* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR12/Compatibility mode Number of dealy elements.
-* Each = 125pSec.
-*/
- u32 emmc_tx_data_cntl2;
-
- /*
-* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
-* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
-* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR12/Compatibility mode Number of dealy elements.
-* Each = 125pSec.
-*/
- u32 emmc_rx_cmd_data_cntl1;
-
- /*
-* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
-* [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
-*/
- u32 emmc_rx_strobe_cntl;
-
- /*
-* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
-*/
- u32 emmc_rx_cmd_data_cntl2;
-
- /* Select the eMMC max speed allowed */
- u32 emmc_host_max_speed;
-
- /* Specifies on which IRQ the SCI will internally appear */
- u32 sci_irq;
-
- /* Configure serial IRQ (SERIRQ) line */
- enum serirq_mode serirq_mode;
-
- /* Configure LPSS S0ix Enable */
- bool lpss_s0ix_enable;
-
- /* Enable DPTF support */
- bool dptf_enable;
-
- /* TCC activation offset value in degrees Celsius */
- int tcc_offset;
-
- /*
-* Configure Audio clk gate and power gate
-* IOSF-SB port ID 92 offset 0x530 [5] and [3]
-*/
- bool hdaudio_clk_gate_enable;
- bool hdaudio_pwr_gate_enable;
-
[RFC PATCH v2 1/2] arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 1f22c1ea3c..458825bc49 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -327,16 +327,17 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
{
struct fsp_s_config *cfg = >config;
struct apl_config *apl;
+#ifdef CONFIG_HAVE_VBT
struct binman_entry vbt;
- void *buf;
int ret;
+ void *vbt_buf;
ret = binman_entry_find("intel-vbt", );
if (ret)
return log_msg_ret("Cannot find VBT", ret);
vbt.image_pos += rom_offset;
- buf = malloc(vbt.size);
- if (!buf)
+ vbt_buf = malloc(vbt.size);
+ if (!vbt_buf)
return log_msg_ret("Alloc VBT", -ENOMEM);
/*
@@ -344,11 +345,12 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
* memory-mapped SPI at present.
*/
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
- memcpy(buf, (void *)vbt.image_pos, vbt.size);
+ memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
- if (*(u32 *)buf != VBT_SIGNATURE)
+ if (*(u32 *)vbt_buf != VBT_SIGNATURE)
return log_msg_ret("VBT signature", -EINVAL);
- cfg->graphics_config_ptr = (ulong)buf;
+ cfg->graphics_config_ptr = (ulong)vbt_buf;
+#endif
apl = malloc(sizeof(*apl));
if (!apl)
--
2.26.0
[RFC PATCH 0/2] Move FSP-S configuration to device-tree
This patch series moves the configuration of FPS-S for Apollo Lake based SoCs from the code to the device-tree. This is similar to the previous patch series for FSP-M. Bernhard Messerklinger (2): arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled arch: x86: apl: Read FSP-S configuration from device-tree arch/x86/cpu/apollolake/fsp_s.c | 1084 +++-- arch/x86/dts/chromebook_coral.dts | 35 +- .../asm/arch-apollolake/fsp/fsp_s_upd.h | 268 .../fsp/fsp2/apollolake/fsp-m.txt | 310 + .../fsp/fsp2/apollolake/fsp-s.txt | 485 5 files changed, 1807 insertions(+), 375 deletions(-) create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt -- 2.26.0
[RFC PATCH 2/2] arch: x86: apl: Read FSP-S configuration from device-tree
Move FSP-S configuration to the device-tree like it's already done for
other SoCs (Baytrail).
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 1070 +++--
arch/x86/dts/chromebook_coral.dts | 35 +-
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 268 +
.../fsp/fsp2/apollolake/fsp-m.txt | 310 +
.../fsp/fsp2/apollolake/fsp-s.txt | 485
5 files changed, 1799 insertions(+), 369 deletions(-)
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 458825bc49..7d516adc92 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -27,309 +27,90 @@
#define INTEL_GSPI_MAX 3
#define MAX_USB2_PORTS 8
-enum {
- CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
- CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
-};
-
-/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
-enum serirq_mode {
- SERIRQ_QUIET,
- SERIRQ_CONTINUOUS,
- SERIRQ_OFF,
-};
-
-struct gspi_cfg {
- /* Bus speed in MHz */
- u32 speed_mhz;
- /* Bus should be enabled prior to ramstage with temporary base */
- u8 early_init;
-};
-
-/*
- * This structure will hold data required by common blocks.
- * These are soc specific configurations which will be filled by soc.
- * We'll fill this structure once during init and use the data in common block.
- */
-struct soc_intel_common_config {
- int chipset_lockdown;
- struct gspi_cfg gspi[INTEL_GSPI_MAX];
-};
-
-enum pnp_settings {
- PNP_PERF,
- PNP_POWER,
- PNP_PERF_POWER,
-};
-
-struct usb2_eye_per_port {
- u8 per_port_tx_pe_half;
- u8 per_port_pe_txi_set;
- u8 per_port_txi_set;
- u8 hs_skew_sel;
- u8 usb_tx_emphasis_en;
- u8 per_port_rxi_set;
- u8 hs_npre_drv_sel;
- u8 override_en;
-};
-
-struct apl_config {
- /* Common structure containing soc config data required by common code*/
- struct soc_intel_common_config common_soc_config;
-
- /*
-* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
-* four CLKREQ inputs, but six root ports. Root ports without an
-* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
-*/
- u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
-
- /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
- u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
-
- /* De-emphasis enable configuration for each PCIe root port */
- u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
-
- /*
-* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
-*/
- u32 emmc_tx_cmd_cntl;
-
- /*
-* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
-*/
- u32 emmc_tx_data_cntl1;
-
- /*
-* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
-* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
-* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR12/Compatibility mode Number of dealy elements.
-* Each = 125pSec.
-*/
- u32 emmc_tx_data_cntl2;
-
- /*
-* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
-* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
-* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR12/Compatibility mode Number of dealy elements.
-* Each = 125pSec.
-*/
- u32 emmc_rx_cmd_data_cntl1;
-
- /*
-* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
-* [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
-*/
- u32 emmc_rx_strobe_cntl;
-
- /*
-* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
-*/
- u32 emmc_rx_cmd_data_cntl2;
-
- /* Select the eMMC max speed allowed */
- u32 emmc_host_max_speed;
-
- /* Specifies on which IRQ the SCI will internally appear */
- u32 sci_irq;
-
- /* Configure serial IRQ (SERIRQ) line */
- enum serirq_mode serirq_mode;
-
- /* Configure LPSS S0ix Enable */
- bool lpss_s0ix_enable;
-
- /* Enable DPTF support */
- bool dptf_enable;
-
- /* TCC activation offset value in degrees Celsius */
- int tcc_offset;
-
- /*
-* Configure Audio clk gate and power gate
-* IOSF-SB port ID 92 offset 0x530
[RFC PATCH 1/2] arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 1f22c1ea3c..458825bc49 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -327,16 +327,17 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
{
struct fsp_s_config *cfg = >config;
struct apl_config *apl;
+#ifdef CONFIG_HAVE_VBT
struct binman_entry vbt;
- void *buf;
int ret;
+ void *vbt_buf;
ret = binman_entry_find("intel-vbt", );
if (ret)
return log_msg_ret("Cannot find VBT", ret);
vbt.image_pos += rom_offset;
- buf = malloc(vbt.size);
- if (!buf)
+ vbt_buf = malloc(vbt.size);
+ if (!vbt_buf)
return log_msg_ret("Alloc VBT", -ENOMEM);
/*
@@ -344,11 +345,12 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
* memory-mapped SPI at present.
*/
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
- memcpy(buf, (void *)vbt.image_pos, vbt.size);
+ memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
- if (*(u32 *)buf != VBT_SIGNATURE)
+ if (*(u32 *)vbt_buf != VBT_SIGNATURE)
return log_msg_ret("VBT signature", -EINVAL);
- cfg->graphics_config_ptr = (ulong)buf;
+ cfg->graphics_config_ptr = (ulong)vbt_buf;
+#endif
apl = malloc(sizeof(*apl));
if (!apl)
--
2.26.0
[RFC PATCH v3] arch: x86: apl: Read FSP-M configuration from device-tree
Move FSP-M configuration to the device-tree like it's already done for
other SoCs (Baytrail).
Signed-off-by: Bernhard Messerklinger
---
With this patch I moved the FSP-M configuration to the device-tree based
on the Baytrail boards.
Changes in v3:
Added doc binding file
Added fspm prefix to some variables
Changes in v2:
Added commit notes
arch/x86/cpu/apollolake/fsp_m.c | 341 --
arch/x86/dts/chromebook_coral.dts | 35 ++
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 165 +
.../fsp/fsp2/apollolake/fsp-m.txt | 312
4 files changed, 733 insertions(+), 120 deletions(-)
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c
index 5308af8ed4..81004fba6f 100644
--- a/arch/x86/cpu/apollolake/fsp_m.c
+++ b/arch/x86/cpu/apollolake/fsp_m.c
@@ -12,21 +12,6 @@
#include
#include
-/*
- * ODT settings:
- * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B,
- * choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A
- * and LOW for ODT_B, choose ODT_A_B_HIGH_LOW.
- *
- * Note that the enum values correspond to the interpreted UPD fields
- * within Ch[3:0]_OdtConfig parameters.
- */
-enum {
- ODT_A_B_HIGH_LOW= 0 << 1,
- ODT_A_B_HIGH_HIGH = 1 << 1,
- N_WR_24 = 1 << 5,
-};
-
/*
* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
* There are four physical LPDDR4 channels, each 32-bits wide. There are two
@@ -67,122 +52,238 @@ struct lpddr4_swizzle_cfg {
struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
};
-static void setup_sdram(struct fsp_m_config *cfg,
- const struct lpddr4_swizzle_cfg *swizzle_cfg)
-{
- const struct lpddr4_chan_swizzle_cfg *sch;
- /* Number of bytes to copy per DQS */
- const size_t sz = DQ_BITS_PER_DQS;
- int chan;
-
- cfg->memory_down = 1;
- cfg->scrambler_support = 1;
- cfg->channel_hash_mask = 0x36;
- cfg->slice_hash_mask = 9;
- cfg->interleaved_mode = 2;
- cfg->channels_slices_enable = 0;
- cfg->min_ref_rate2x_enable = 0;
- cfg->dual_rank_support_enable = 1;
-
- /* LPDDR4 is memory down so no SPD addresses */
- cfg->dimm0_spd_address = 0;
- cfg->dimm1_spd_address = 0;
-
- for (chan = 0; chan < 4; chan++) {
- struct fsp_ram_channel *ch = >chan[chan];
-
- ch->rank_enable = 1;
- ch->device_width = 1;
- ch->dram_density = 2;
- ch->option = 3;
- ch->odt_config = ODT_A_B_HIGH_HIGH;
- }
-
- /*
-* CH0_DQB byte lanes in the bit swizzle configuration field are
-* not 1:1. The mapping within the swizzling field is:
-* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
-* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
-* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
-* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
-*/
- sch = _cfg->phys[LP4_PHYS_CH0B];
- memcpy(>ch_bit_swizzling[0][0], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[0][8], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[0][16], >dqs[LP4_DQS3], sz);
- memcpy(>ch_bit_swizzling[0][24], >dqs[LP4_DQS2], sz);
-
- /*
-* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
-*/
- sch = _cfg->phys[LP4_PHYS_CH0A];
- memcpy(>ch_bit_swizzling[1][0], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[1][8], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[1][16], >dqs[LP4_DQS2], sz);
- memcpy(>ch_bit_swizzling[1][24], >dqs[LP4_DQS3], sz);
-
- sch = _cfg->phys[LP4_PHYS_CH1B];
- memcpy(>ch_bit_swizzling[2][0], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[2][8], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[2][16], >dqs[LP4_DQS3], sz);
- memcpy(>ch_bit_swizzling[2][24], >dqs[LP4_DQS2], sz);
-
- /*
-* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
-*/
- sch = _cfg->phys[LP4_PHYS_CH1A];
- memcpy(>ch_bit_swizzling[3][0], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[3][8], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[3][16], >dqs[LP4_DQS2], sz);
- memcpy(>ch_bit_swizzling[3][24], >dqs[LP4_DQS3], sz);
-}
-
int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
{
struct fsp_m_config *cfg = >config;
struct fspm_arch_upd *arch = >arch;
+ char chx_buf[30];
+ const struct lpddr4_chan_swizzle_cfg *sch;
+ const struct lpddr4_swizzl
Antwort: Re: Re: x86: apl: PCI enumeration issue
Hi Bin, >Hi Bernhard, > >On Mon, Mar 30, 2020 at 4:25 PM Bernhard Messerklinger > wrote: >> >> Hi Bin, >> >> >Hi Bernhard, >> > >> >On Mon, Mar 30, 2020 at 3:35 PM Bernhard Messerklinger >> > wrote: >> >> >> >> Hi Simon, Bin, >> >> >> >> I am facing problems with the PCI enumeration at SPL loader >stage. >> >> On our HW we have PCIe x2 port connected to a FPGA. Since SPL >does >> >pci >> >> enumeration before FSP-S has been called the enumeration of the >> >second port of >> >> the pci x2 connection causes the system to hang. >> > >> >Do you know why the 2nd port hang happens, but not the 1st port? >Is >> >that because in order to get 2nd port working something is done in >> >FSP-S? >> >> I know that the problem happens because of the PCIe FIT tool >configuration. >> If I change the configuration to PCIe x1 on all root ports of the >SoC the >> issue doesn't occur. >> I think FSP-S hides the second port because it's no real PCIe root >port, > >That's not common. If FSP-S is hiding the 2nd port, it should not be >visible in the PCI configuration space. Do you know if this is a bug >of the silicon or it just behaves like this? No I think the point is, that at the time (SPL) where the first pci enumeration is done the FSP-S init is not done. The FSP-S init is called later in the main u-boot. After FSP-S init it works fine. >>> it's just the second lane of the first port. I also did some >research in the >> intel FSP-S code. In the FSP-S code some not documented fuse >registers are >> accessed and then the second port is deactivated depending of the >FIT >> configuration. > >Regards, >Bin > Regards, Bernhard
Antwort: Re: x86: apl: PCI enumeration issue
Hi Bin,
>Hi Bernhard,
>
>On Mon, Mar 30, 2020 at 3:35 PM Bernhard Messerklinger
> wrote:
>>
>> Hi Simon, Bin,
>>
>> I am facing problems with the PCI enumeration at SPL loader stage.
>> On our HW we have PCIe x2 port connected to a FPGA. Since SPL does
>pci
>> enumeration before FSP-S has been called the enumeration of the
>second port of
>> the pci x2 connection causes the system to hang.
>
>Do you know why the 2nd port hang happens, but not the 1st port? Is
>that because in order to get 2nd port working something is done in
>FSP-S?
I know that the problem happens because of the PCIe FIT tool configuration.
If I change the configuration to PCIe x1 on all root ports of the SoC the
issue doesn't occur.
I think FSP-S hides the second port because it's no real PCIe root port,
it's just the second lane of the first port. I also did some research in the
intel FSP-S code. In the FSP-S code some not documented fuse registers are
accessed and then the second port is deactivated depending of the FIT
configuration.
>>
>> In my configuration PCI 0.13.0 is a X2 port. So, if the
>pci_bind_bus_devices
>> function wants to read the PCI_VENDOR_ID from the PCI device 0.13.1
>the system
>> hangs.
>>
>> int pci_bind_bus_devices(struct udevice *bus)
>> {
>> ulong vendor, device;
>> ulong header_type;
>> pci_dev_t bdf, end;
>> bool found_multi;
>> int ret;
>>
>> found_multi = false;
>> end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
>> PCI_MAX_PCI_FUNCTIONS - 1);
>> for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
>> bdf += PCI_BDF(0, 0, 1)) {
>> struct pci_child_platdata *pplat;
>> struct udevice *dev;
>> ulong class;
>>
>> if (!PCI_FUNC(bdf))
>> found_multi = false;
>> if (PCI_FUNC(bdf) && !found_multi)
>> continue;
>>
>> #if defined(CONFIG_SPL_BUILD)
>> if (PCI_DEV(bdf) == 0x13 && PCI_FUNC(bdf) == 1)
>> continue;
>> #endif
>>
>> /* Check only the first access, we don't expect
>problems */
>> ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID,
>,
>> PCI_SIZE_16);
>>
>> At the moment, I fixed this issue by adding an #ifdef which skips
>the config read
>> on this device.
>>
>> I think a way to solve this issue could be to add a new devic-tree
>property
>> like it's done here with "pci,no-autoconfig":
>> https://lists.denx.de/pipermail/u-boot/2020-March/402276.html
>>
>> But i don't know if it's good to put more apollolake specific stuff
>into the
>> pci-uclass.
>>
>> Maybe we should add an apollolake specific pci_uclass_post_probe
>override.
>> This could maybe be done by adding a spcecific pci driver like
>pci_x86 for
>> apollolake platform and override the post_probe argument of the
>pci_uclass.
>> Then we could also move the other apollolake specific things into
>this driver.
>>
>> What do you think about this?
>> Do you have better/other ideas?
>>
>
>Regards,
>Bin
>
Regards,
Bernhard
Antwort: Re: [RFC PATCH v2] arch: x86: apl: Read FSP-M configuration from device-tree
Hi Simon, >>> With this patch I moved the fsp-m configuration to the device-tree >>> based on the baytrail boards. >>> I have tried to build it so that only entries that differ from the >>> default configuration need to be added. As a minimum the ddr >>> configuration must be present. >>> If you like this way of configuration, I am also willing to do the >>> same >>> for the fsp-s. >>> Can you please provide me some feedback? >>> >>> Changes in v2: >>> Added commit notes >>> >>> arch/x86/cpu/apollolake/fsp_m.c | 337 >>+++--- >>> arch/x86/dts/chromebook_coral.dts | 35 ++ >>> .../asm/arch-apollolake/fsp/fsp_m_upd.h | 162 + >>> 3 files changed, 414 insertions(+), 120 deletions(-) >> >>Reviewed-by: Simon Glass >>Tested on chromebook_coral: >>Tested-by: Simon Glass >> >>Do you think we should add a binding file for this though? > >Yes, I will create v3 with a binding file in >doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt. Sorry after some more detailed research I don't know if my first understanding of binding file was right. With binding file do you mean a header file for defines in /include/dt-bindings or a documentation in doc/device-tree-bindings? >>Is that ok for you? > >Do you also agree to change the fsp-s configuration in the same way? Regards, Bernhard
x86: apl: PCI enumeration issue
Hi Simon, Bin,
I am facing problems with the PCI enumeration at SPL loader stage.
On our HW we have PCIe x2 port connected to a FPGA. Since SPL does pci
enumeration before FSP-S has been called the enumeration of the second port of
the pci x2 connection causes the system to hang.
In my configuration PCI 0.13.0 is a X2 port. So, if the pci_bind_bus_devices
function wants to read the PCI_VENDOR_ID from the PCI device 0.13.1 the system
hangs.
int pci_bind_bus_devices(struct udevice *bus)
{
ulong vendor, device;
ulong header_type;
pci_dev_t bdf, end;
bool found_multi;
int ret;
found_multi = false;
end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
PCI_MAX_PCI_FUNCTIONS - 1);
for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
bdf += PCI_BDF(0, 0, 1)) {
struct pci_child_platdata *pplat;
struct udevice *dev;
ulong class;
if (!PCI_FUNC(bdf))
found_multi = false;
if (PCI_FUNC(bdf) && !found_multi)
continue;
#if defined(CONFIG_SPL_BUILD)
if (PCI_DEV(bdf) == 0x13 && PCI_FUNC(bdf) == 1)
continue;
#endif
/* Check only the first access, we don't expect problems */
ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, ,
PCI_SIZE_16);
At the moment, I fixed this issue by adding an #ifdef which skips the config
read
on this device.
I think a way to solve this issue could be to add a new devic-tree property
like it's done here with "pci,no-autoconfig":
https://lists.denx.de/pipermail/u-boot/2020-March/402276.html
But i don't know if it's good to put more apollolake specific stuff into the
pci-uclass.
Maybe we should add an apollolake specific pci_uclass_post_probe override.
This could maybe be done by adding a spcecific pci driver like pci_x86 for
apollolake platform and override the post_probe argument of the pci_uclass.
Then we could also move the other apollolake specific things into this driver.
What do you think about this?
Do you have better/other ideas?
Regards,
Bernhard
Antwort: Re: [RFC PATCH v2] arch: x86: apl: Read FSP-M configuration from device-tree
Hi Simon, >> With this patch I moved the fsp-m configuration to the device-tree >> based on the baytrail boards. >> I have tried to build it so that only entries that differ from the >> default configuration need to be added. As a minimum the ddr >> configuration must be present. >> If you like this way of configuration, I am also willing to do the >> same >> for the fsp-s. >> Can you please provide me some feedback? >> >> Changes in v2: >> Added commit notes >> >> arch/x86/cpu/apollolake/fsp_m.c | 337 >+++--- >> arch/x86/dts/chromebook_coral.dts | 35 ++ >> .../asm/arch-apollolake/fsp/fsp_m_upd.h | 162 + >> 3 files changed, 414 insertions(+), 120 deletions(-) > >Reviewed-by: Simon Glass >Tested on chromebook_coral: >Tested-by: Simon Glass > >Do you think we should add a binding file for this though? Yes, I will create v3 with a binding file in doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt. Is that ok for you? Do you also agree to change the fsp-s configuration in the same way? Regards, Bernhard
[RFC PATCH v2] arch: x86: apl: Read FSP-M configuration from device-tree
Move FSP-M configuration to the device-tree like it's already done for
other SoCs (Baytaril).
Signed-off-by: Bernhard Messerklinger
---
With this patch I moved the fsp-m configuration to the device-tree based
on the baytrail boards.
I have tried to build it so that only entries that differ from the
default configuration need to be added. As a minimum the ddr
configuration must be present.
If you like this way of configuration, I am also willing to do the same
for the fsp-s.
Can you please provide me some feedback?
Changes in v2:
Added commit notes
arch/x86/cpu/apollolake/fsp_m.c | 337 +++---
arch/x86/dts/chromebook_coral.dts | 35 ++
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 162 +
3 files changed, 414 insertions(+), 120 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c
index 5308af8ed4..ee84231acb 100644
--- a/arch/x86/cpu/apollolake/fsp_m.c
+++ b/arch/x86/cpu/apollolake/fsp_m.c
@@ -12,21 +12,6 @@
#include
#include
-/*
- * ODT settings:
- * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B,
- * choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A
- * and LOW for ODT_B, choose ODT_A_B_HIGH_LOW.
- *
- * Note that the enum values correspond to the interpreted UPD fields
- * within Ch[3:0]_OdtConfig parameters.
- */
-enum {
- ODT_A_B_HIGH_LOW= 0 << 1,
- ODT_A_B_HIGH_HIGH = 1 << 1,
- N_WR_24 = 1 << 5,
-};
-
/*
* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
* There are four physical LPDDR4 channels, each 32-bits wide. There are two
@@ -67,122 +52,234 @@ struct lpddr4_swizzle_cfg {
struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
};
-static void setup_sdram(struct fsp_m_config *cfg,
- const struct lpddr4_swizzle_cfg *swizzle_cfg)
-{
- const struct lpddr4_chan_swizzle_cfg *sch;
- /* Number of bytes to copy per DQS */
- const size_t sz = DQ_BITS_PER_DQS;
- int chan;
-
- cfg->memory_down = 1;
- cfg->scrambler_support = 1;
- cfg->channel_hash_mask = 0x36;
- cfg->slice_hash_mask = 9;
- cfg->interleaved_mode = 2;
- cfg->channels_slices_enable = 0;
- cfg->min_ref_rate2x_enable = 0;
- cfg->dual_rank_support_enable = 1;
-
- /* LPDDR4 is memory down so no SPD addresses */
- cfg->dimm0_spd_address = 0;
- cfg->dimm1_spd_address = 0;
-
- for (chan = 0; chan < 4; chan++) {
- struct fsp_ram_channel *ch = >chan[chan];
-
- ch->rank_enable = 1;
- ch->device_width = 1;
- ch->dram_density = 2;
- ch->option = 3;
- ch->odt_config = ODT_A_B_HIGH_HIGH;
- }
-
- /*
-* CH0_DQB byte lanes in the bit swizzle configuration field are
-* not 1:1. The mapping within the swizzling field is:
-* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
-* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
-* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
-* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
-*/
- sch = _cfg->phys[LP4_PHYS_CH0B];
- memcpy(>ch_bit_swizzling[0][0], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[0][8], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[0][16], >dqs[LP4_DQS3], sz);
- memcpy(>ch_bit_swizzling[0][24], >dqs[LP4_DQS2], sz);
-
- /*
-* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
-*/
- sch = _cfg->phys[LP4_PHYS_CH0A];
- memcpy(>ch_bit_swizzling[1][0], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[1][8], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[1][16], >dqs[LP4_DQS2], sz);
- memcpy(>ch_bit_swizzling[1][24], >dqs[LP4_DQS3], sz);
-
- sch = _cfg->phys[LP4_PHYS_CH1B];
- memcpy(>ch_bit_swizzling[2][0], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[2][8], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[2][16], >dqs[LP4_DQS3], sz);
- memcpy(>ch_bit_swizzling[2][24], >dqs[LP4_DQS2], sz);
-
- /*
-* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
-*/
- sch = _cfg->phys[LP4_PHYS_CH1A];
- memcpy(>ch_bit_swizzling[3][0], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[3][8], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[3][16], >dqs[LP4_DQS2], sz);
- memcpy(>ch_bit_swizzling[3][24], >dqs[LP4_DQS3], sz);
-}
-
int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
{
struct fsp_m_config *cfg = >config;
struct fspm_arch_upd *arch = >arch;
+ char chx_buf[30];
+ const struct lpddr4_chan_swi
[RFC PATCH] arch: x86: apl: Read FSP-M configuration from device-tree
Move FSP-M configuration to the device-tree like it's already done for
other SoCs (Baytaril).
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_m.c | 337 +++---
arch/x86/dts/chromebook_coral.dts | 35 ++
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 162 +
3 files changed, 414 insertions(+), 120 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c
index 5308af8ed4..ee84231acb 100644
--- a/arch/x86/cpu/apollolake/fsp_m.c
+++ b/arch/x86/cpu/apollolake/fsp_m.c
@@ -12,21 +12,6 @@
#include
#include
-/*
- * ODT settings:
- * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B,
- * choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A
- * and LOW for ODT_B, choose ODT_A_B_HIGH_LOW.
- *
- * Note that the enum values correspond to the interpreted UPD fields
- * within Ch[3:0]_OdtConfig parameters.
- */
-enum {
- ODT_A_B_HIGH_LOW= 0 << 1,
- ODT_A_B_HIGH_HIGH = 1 << 1,
- N_WR_24 = 1 << 5,
-};
-
/*
* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
* There are four physical LPDDR4 channels, each 32-bits wide. There are two
@@ -67,122 +52,234 @@ struct lpddr4_swizzle_cfg {
struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
};
-static void setup_sdram(struct fsp_m_config *cfg,
- const struct lpddr4_swizzle_cfg *swizzle_cfg)
-{
- const struct lpddr4_chan_swizzle_cfg *sch;
- /* Number of bytes to copy per DQS */
- const size_t sz = DQ_BITS_PER_DQS;
- int chan;
-
- cfg->memory_down = 1;
- cfg->scrambler_support = 1;
- cfg->channel_hash_mask = 0x36;
- cfg->slice_hash_mask = 9;
- cfg->interleaved_mode = 2;
- cfg->channels_slices_enable = 0;
- cfg->min_ref_rate2x_enable = 0;
- cfg->dual_rank_support_enable = 1;
-
- /* LPDDR4 is memory down so no SPD addresses */
- cfg->dimm0_spd_address = 0;
- cfg->dimm1_spd_address = 0;
-
- for (chan = 0; chan < 4; chan++) {
- struct fsp_ram_channel *ch = >chan[chan];
-
- ch->rank_enable = 1;
- ch->device_width = 1;
- ch->dram_density = 2;
- ch->option = 3;
- ch->odt_config = ODT_A_B_HIGH_HIGH;
- }
-
- /*
-* CH0_DQB byte lanes in the bit swizzle configuration field are
-* not 1:1. The mapping within the swizzling field is:
-* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
-* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
-* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
-* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
-*/
- sch = _cfg->phys[LP4_PHYS_CH0B];
- memcpy(>ch_bit_swizzling[0][0], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[0][8], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[0][16], >dqs[LP4_DQS3], sz);
- memcpy(>ch_bit_swizzling[0][24], >dqs[LP4_DQS2], sz);
-
- /*
-* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
-*/
- sch = _cfg->phys[LP4_PHYS_CH0A];
- memcpy(>ch_bit_swizzling[1][0], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[1][8], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[1][16], >dqs[LP4_DQS2], sz);
- memcpy(>ch_bit_swizzling[1][24], >dqs[LP4_DQS3], sz);
-
- sch = _cfg->phys[LP4_PHYS_CH1B];
- memcpy(>ch_bit_swizzling[2][0], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[2][8], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[2][16], >dqs[LP4_DQS3], sz);
- memcpy(>ch_bit_swizzling[2][24], >dqs[LP4_DQS2], sz);
-
- /*
-* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
-*/
- sch = _cfg->phys[LP4_PHYS_CH1A];
- memcpy(>ch_bit_swizzling[3][0], >dqs[LP4_DQS0], sz);
- memcpy(>ch_bit_swizzling[3][8], >dqs[LP4_DQS1], sz);
- memcpy(>ch_bit_swizzling[3][16], >dqs[LP4_DQS2], sz);
- memcpy(>ch_bit_swizzling[3][24], >dqs[LP4_DQS3], sz);
-}
-
int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
{
struct fsp_m_config *cfg = >config;
struct fspm_arch_upd *arch = >arch;
+ char chx_buf[30];
+ const struct lpddr4_chan_swizzle_cfg *sch;
+ const struct lpddr4_swizzle_cfg *swizzle_cfg;
+ const size_t sz = DQ_BITS_PER_DQS;
+ bool tmp;
+ const u8 *gpio_table_pins;
+ const char *oem_file;
arch->nvs_buffer_ptr = NULL;
prepare_mrc_cache(upd);
arch->stack_base = (void *)0xfef96000;
arch->boot_loader_tolum_size = 0;
-
arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURA
[PATCH v3] arm: imx6: configure NoC on i.MX6DQP
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Co-developed-by: Filip Brozović
Signed-off-by: Bernhard Messerklinger
---
This patch is a revised version of the patch "arm: imx6: configure NoC on
i.MX6DQP" from the original author Filip Brozovic .
It takes care of the review notes for the original patch.
patchwork: https://patchwork.ozlabs.org/patch/670208/
mail-archive: https://lists.denx.de/pipermail/u-boot/2016-September/27.html
@Filip: I added the Co-Developed-by: tag, can you please reply with your
Signed-off-by.
@Maintainers: Can you please provide some feedback regarding this patch and
the way I want to handle the authorship?
Changes in v3:
- Add Co-Developed-by tag for Filip Brozović
Changes in v2:
- Added missing link to lkml discussion
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 19 +
arch/arm/mach-imx/mx6/ddr.c | 96 +
2 files changed, 115 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 19d2f1d9c5..25168c9865 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -307,6 +307,25 @@ struct mx6dq_iomux_grp_regs {
u32 grp_b6ds;
};
+/*
+ * NoC scheduler registers - only on IMX6DQP
+ */
+#define MX6DQP_NOC_SCHED_BASE 0x00bb
+struct mx6dqp_noc_sched_regs {
+ u32 coreid;
+ u32 revid;
+ u32 ddrconf;
+ u32 ddrtiming;
+ u32 ddrmode;
+ u32 rlat;
+ u32 res1[4];
+ u32 ipu1;
+ u32 ipu2;
+ u32 res2[2];
+ u32 activate;
+ u32 res3[16];
+};
+
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 6e5e40dd1a..3521d8eac7 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -936,6 +936,27 @@ void mx6sdl_dram_iocfg(unsigned width,
mmdc1->entry = value; \
} while (0)
+/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
+#define BOOT_CFG3_DDR_MASK 0x30
+#define BOOT_CFG3_EXT_DDR_MASK 0x33
+
+#define DDR_MMAP_NOC_SINGLE0
+#define DDR_MMAP_NOC_DUAL 0x31
+
+/* NoC ACTIVATE shifts */
+#define NOC_RD_SHIFT 0
+#define NOC_FAW_PERIOD_SHIFT 4
+#define NOC_FAW_BANKS_SHIFT10
+
+/* NoC DdrTiming shifts */
+#define NOC_ACT_TO_ACT_SHIFT 0
+#define NOC_RD_TO_MISS_SHIFT 6
+#define NOC_WR_TO_MISS_SHIFT 12
+#define NOC_BURST_LEN_SHIFT18
+#define NOC_RD_TO_WR_SHIFT 21
+#define NOC_WR_TO_RD_SHIFT 26
+#define NOC_BW_RATIO_SHIFT 31
+
/*
* According JESD209-2B-LPDDR2: Table 103
* WL: write latency
@@ -1225,6 +1246,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u8 soc_boot_cfg3 = (readl(_regs->sbmr1) >> 16) & 0xff;
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -1517,6 +1540,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
+ /*
+* Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
+* configure it and disable MMDC arbitration/reordering (see EB828)
+*/
+ if (is_mx6dqp() &&
+ ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
+ (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
+ struct mx6dqp_noc_sched_regs *noc_sched =
+ (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
+
+ /*
+* These values are fixed based on integration parameters and
+* should not be modified
+*/
+ noc_sched->rlat = 0x0040;
+ noc_sched->ipu1 = 0x0020;
+ noc_sched->ipu2 = 0x0020;
+
+ noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
+ (tfaw << NOC_FAW_PERIOD_SHIFT) |
+ (trrd << NOC_RD_SHIFT);
+ noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
+<< NOC_BW_RATIO_SHIFT) |
+ ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
+ ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT)
|
+
[PATCH v2] arm: imx6: configure NoC on i.MX6DQP
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Signed-off-by: Bernhard Messerklinger
---
This patch is a revised version of the patch "arm: imx6: configure NoC on
i.MX6DQP" from the original author Filip Brozovic .
It takes care of the review notes for the original patch.
patchwork: https://patchwork.ozlabs.org/patch/670208/
mail-archive: https://lists.denx.de/pipermail/u-boot/2016-September/27.html
I'm not sure how to handle a patch which is based on a patch from another
author. Guidance from the maintainers regarding this question would be welcome.
My assumption would be that this can be solved by adding "Co-Developed-by:" and
"Signed-off-by:" lines to this patch for Filip Brozovic (see [1] for a
discussion of this topic on LKML). Filip, would this be ok for you?
[1] http://lkml.iu.edu/hypermail/linux/kernel/1711.2/00256.html
Changes in v2:
- Added missing link to lkml discussion
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 19 +
arch/arm/mach-imx/mx6/ddr.c | 96 +
2 files changed, 115 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 19d2f1d9c5..25168c9865 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -307,6 +307,25 @@ struct mx6dq_iomux_grp_regs {
u32 grp_b6ds;
};
+/*
+ * NoC scheduler registers - only on IMX6DQP
+ */
+#define MX6DQP_NOC_SCHED_BASE 0x00bb
+struct mx6dqp_noc_sched_regs {
+ u32 coreid;
+ u32 revid;
+ u32 ddrconf;
+ u32 ddrtiming;
+ u32 ddrmode;
+ u32 rlat;
+ u32 res1[4];
+ u32 ipu1;
+ u32 ipu2;
+ u32 res2[2];
+ u32 activate;
+ u32 res3[16];
+};
+
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 6e5e40dd1a..3521d8eac7 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -936,6 +936,27 @@ void mx6sdl_dram_iocfg(unsigned width,
mmdc1->entry = value; \
} while (0)
+/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
+#define BOOT_CFG3_DDR_MASK 0x30
+#define BOOT_CFG3_EXT_DDR_MASK 0x33
+
+#define DDR_MMAP_NOC_SINGLE0
+#define DDR_MMAP_NOC_DUAL 0x31
+
+/* NoC ACTIVATE shifts */
+#define NOC_RD_SHIFT 0
+#define NOC_FAW_PERIOD_SHIFT 4
+#define NOC_FAW_BANKS_SHIFT10
+
+/* NoC DdrTiming shifts */
+#define NOC_ACT_TO_ACT_SHIFT 0
+#define NOC_RD_TO_MISS_SHIFT 6
+#define NOC_WR_TO_MISS_SHIFT 12
+#define NOC_BURST_LEN_SHIFT18
+#define NOC_RD_TO_WR_SHIFT 21
+#define NOC_WR_TO_RD_SHIFT 26
+#define NOC_BW_RATIO_SHIFT 31
+
/*
* According JESD209-2B-LPDDR2: Table 103
* WL: write latency
@@ -1225,6 +1246,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u8 soc_boot_cfg3 = (readl(_regs->sbmr1) >> 16) & 0xff;
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -1517,6 +1540,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
+ /*
+* Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
+* configure it and disable MMDC arbitration/reordering (see EB828)
+*/
+ if (is_mx6dqp() &&
+ ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
+ (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
+ struct mx6dqp_noc_sched_regs *noc_sched =
+ (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
+
+ /*
+* These values are fixed based on integration parameters and
+* should not be modified
+*/
+ noc_sched->rlat = 0x0040;
+ noc_sched->ipu1 = 0x0020;
+ noc_sched->ipu2 = 0x0020;
+
+ noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
+ (tfaw << NOC_FAW_PERIOD_SHIFT) |
+ (trrd << NOC_RD_SHIFT);
+ noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
+<< NOC_BW_RATIO_SHIFT) |
+
[PATCH] arm: imx6: configure NoC on i.MX6DQP
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Signed-off-by: Bernhard Messerklinger
---
This patch is a revised version of the patch "arm: imx6: configure NoC on
i.MX6DQP" from the original author Filip Brozovic .
It takes care of the review notes for the original patch.
patchwork: https://patchwork.ozlabs.org/patch/670208/
mail-archive: https://lists.denx.de/pipermail/u-boot/2016-September/27.html
I'm not sure how to handle a patch which is based on a patch from another
author. Guidance from the maintainers regarding this question would be welcome.
My assumption would be that this can be solved by adding "Co-Developed-by:" and
"Signed-off-by:" lines to this patch for Filip Brozovic (see [1] for a
discussion of this topic on LKML). Filip, would this be ok for you?
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 19 +
arch/arm/mach-imx/mx6/ddr.c | 96 +
2 files changed, 115 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 19d2f1d9c5..25168c9865 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -307,6 +307,25 @@ struct mx6dq_iomux_grp_regs {
u32 grp_b6ds;
};
+/*
+ * NoC scheduler registers - only on IMX6DQP
+ */
+#define MX6DQP_NOC_SCHED_BASE 0x00bb
+struct mx6dqp_noc_sched_regs {
+ u32 coreid;
+ u32 revid;
+ u32 ddrconf;
+ u32 ddrtiming;
+ u32 ddrmode;
+ u32 rlat;
+ u32 res1[4];
+ u32 ipu1;
+ u32 ipu2;
+ u32 res2[2];
+ u32 activate;
+ u32 res3[16];
+};
+
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 6e5e40dd1a..3521d8eac7 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -936,6 +936,27 @@ void mx6sdl_dram_iocfg(unsigned width,
mmdc1->entry = value; \
} while (0)
+/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
+#define BOOT_CFG3_DDR_MASK 0x30
+#define BOOT_CFG3_EXT_DDR_MASK 0x33
+
+#define DDR_MMAP_NOC_SINGLE0
+#define DDR_MMAP_NOC_DUAL 0x31
+
+/* NoC ACTIVATE shifts */
+#define NOC_RD_SHIFT 0
+#define NOC_FAW_PERIOD_SHIFT 4
+#define NOC_FAW_BANKS_SHIFT10
+
+/* NoC DdrTiming shifts */
+#define NOC_ACT_TO_ACT_SHIFT 0
+#define NOC_RD_TO_MISS_SHIFT 6
+#define NOC_WR_TO_MISS_SHIFT 12
+#define NOC_BURST_LEN_SHIFT18
+#define NOC_RD_TO_WR_SHIFT 21
+#define NOC_WR_TO_RD_SHIFT 26
+#define NOC_BW_RATIO_SHIFT 31
+
/*
* According JESD209-2B-LPDDR2: Table 103
* WL: write latency
@@ -1225,6 +1246,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u8 soc_boot_cfg3 = (readl(_regs->sbmr1) >> 16) & 0xff;
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -1517,6 +1540,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
+ /*
+* Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
+* configure it and disable MMDC arbitration/reordering (see EB828)
+*/
+ if (is_mx6dqp() &&
+ ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
+ (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
+ struct mx6dqp_noc_sched_regs *noc_sched =
+ (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
+
+ /*
+* These values are fixed based on integration parameters and
+* should not be modified
+*/
+ noc_sched->rlat = 0x0040;
+ noc_sched->ipu1 = 0x0020;
+ noc_sched->ipu2 = 0x0020;
+
+ noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
+ (tfaw << NOC_FAW_PERIOD_SHIFT) |
+ (trrd << NOC_RD_SHIFT);
+ noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
+<< NOC_BW_RATIO_SHIFT) |
+ ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
+ ((tcl - tcwl + 2) << NOC_RD_TO
Re: arm: imx6: configure NoC on i.MX6DQP
-"U-Boot" schrieb: - > Hi Stefano, Filip, > > I found this patch on the mailing list: > https://patchwork.ozlabs.org/patch/670208/ > > As far as I can see this patch never made it to mainline. > I have tested and reviewed the patch and it works for me. > With this patch my i.MX6QP DDR3 NoC configuration works fine. > > What is the current state of the patch? > Is anyone still working on it? > If no, what would I have to do to get it mainline? > > Regards, > Bernhard Hi Stefano, Filip, I am still looking for feedback regarding this question? Can anybody help me? Regards, Bernhard
arm: imx6: configure NoC on i.MX6DQP
Hi Stefano, Filip, I found this patch on the mailing list: https://patchwork.ozlabs.org/patch/670208/ As far as I can see this patch never made it to mainline. I have tested and reviewed the patch and it works for me. With this patch my i.MX6QP DDR3 NoC configuration works fine. What is the current state of the patch? Is anyone still working on it? If no, what would I have to do to get it mainline? Regards, Bernhard
[U-Boot] [PATCH v4] x86: ich-spi: Convert driver to spi-mem ops
With the introduction of the new spi-mem model operations changed
slightly. The new spi-mem operations make things a bit easier to
handle for ich-spi flash interface. This patch converts the ich-spi
driver by using spi-mem operations.
Signed-off-by: Bernhard Messerklinger
---
Changes in v4:
- fix changelog; fix local variable types and order
Changes in v3:
- update erase op code handling to work with latest master
spi-nor driver
Changes in v2:
- make 2 routines static; update commit message a little bit
drivers/spi/ich.c | 258 +-
drivers/spi/ich.h | 9 +-
2 files changed, 95 insertions(+), 172 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 03531a8c0c..60589dfb61 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -14,6 +14,8 @@
#include
#include
#include
+#include
+#include
#include "ich.h"
@@ -171,18 +173,6 @@ static int ich_init_controller(struct udevice *dev,
return 0;
}
-static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
-{
- trans->out += bytes;
- trans->bytesout -= bytes;
-}
-
-static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
-{
- trans->in += bytes;
- trans->bytesin -= bytes;
-}
-
static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
{
if (plat->ich_version == ICHV_7) {
@@ -213,47 +203,12 @@ static bool spi_lock_status(struct ich_spi_platdata
*plat, void *sbase)
return lock != 0;
}
-static void spi_setup_type(struct spi_trans *trans, int data_bytes)
-{
- trans->type = 0xFF;
-
- /* Try to guess spi type from read/write sizes */
- if (trans->bytesin == 0) {
- if (trans->bytesout + data_bytes > 4)
- /*
-* If bytesin = 0 and bytesout > 4, we presume this is
-* a write data operation, which is accompanied by an
-* address.
-*/
- trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
- else
- trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
- return;
- }
-
- if (trans->bytesout == 1) { /* and bytesin is > 0 */
- trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
- return;
- }
-
- if (trans->bytesout == 4) /* and bytesin is > 0 */
- trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
-
- /* Fast read command is called with 5 bytes instead of 4 */
- if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
- trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
- --trans->bytesout;
- }
-}
-
static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
bool lock)
{
uint16_t optypes;
uint8_t opmenu[ctlr->menubytes];
- trans->opcode = trans->out[0];
- spi_use_out(trans, 1);
if (!lock) {
/* The lock is off, so just use index 0. */
ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
@@ -285,12 +240,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr,
struct spi_trans *trans,
optypes = ich_readw(ctlr, ctlr->optype);
optype = (optypes >> (opcode_index * 2)) & 0x3;
- if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
- optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
- trans->bytesout >= 3) {
- /* We guessed wrong earlier. Fix it up. */
- trans->type = optype;
- }
+
if (optype != trans->type) {
printf("ICH SPI: Transaction doesn't fit type %d\n",
optype);
@@ -300,26 +250,6 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr,
struct spi_trans *trans,
}
}
-static int spi_setup_offset(struct spi_trans *trans)
-{
- /* Separate the SPI address and data */
- switch (trans->type) {
- case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
- case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
- return 0;
- case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
- case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
- trans->offset = ((uint32_t)trans->out[0] << 16) |
- ((uint32_t)trans->out[1] << 8) |
- ((uint32_t)trans->out[2] << 0);
- spi_use_out(trans, 3);
- return 1;
- default:
- printf("Unrecognized SPI transaction type %#x\n", trans->type);
- return -EPROTO;
- }
-}
-
/*
* Wait for up to 6s til status
[U-Boot] [PATCH v3] x86: ich-spi: Convert driver to spi-mem ops
With the introduction of the new spi-mem model operations changed
slightly. The new spi-mem operations make things a bit easier to
handle for ich-spi flash interface. This patch converts the ich-spi
driver by using spi-mem operations.
---
Changes in v2:
- make 2 routines static; update commit message a little bit
Changes in v3:
- update erase op code handling to work with latest master
spi-nor driver
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/ich.c | 267 +-
drivers/spi/ich.h | 9 +-
2 files changed, 100 insertions(+), 176 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 03531a8c0c..179f801d42 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -14,6 +14,8 @@
#include
#include
#include
+#include
+#include
#include "ich.h"
@@ -171,18 +173,6 @@ static int ich_init_controller(struct udevice *dev,
return 0;
}
-static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
-{
- trans->out += bytes;
- trans->bytesout -= bytes;
-}
-
-static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
-{
- trans->in += bytes;
- trans->bytesin -= bytes;
-}
-
static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
{
if (plat->ich_version == ICHV_7) {
@@ -213,47 +203,12 @@ static bool spi_lock_status(struct ich_spi_platdata
*plat, void *sbase)
return lock != 0;
}
-static void spi_setup_type(struct spi_trans *trans, int data_bytes)
-{
- trans->type = 0xFF;
-
- /* Try to guess spi type from read/write sizes */
- if (trans->bytesin == 0) {
- if (trans->bytesout + data_bytes > 4)
- /*
-* If bytesin = 0 and bytesout > 4, we presume this is
-* a write data operation, which is accompanied by an
-* address.
-*/
- trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
- else
- trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
- return;
- }
-
- if (trans->bytesout == 1) { /* and bytesin is > 0 */
- trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
- return;
- }
-
- if (trans->bytesout == 4) /* and bytesin is > 0 */
- trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
-
- /* Fast read command is called with 5 bytes instead of 4 */
- if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
- trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
- --trans->bytesout;
- }
-}
-
static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
bool lock)
{
uint16_t optypes;
uint8_t opmenu[ctlr->menubytes];
- trans->opcode = trans->out[0];
- spi_use_out(trans, 1);
if (!lock) {
/* The lock is off, so just use index 0. */
ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
@@ -285,12 +240,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr,
struct spi_trans *trans,
optypes = ich_readw(ctlr, ctlr->optype);
optype = (optypes >> (opcode_index * 2)) & 0x3;
- if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
- optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
- trans->bytesout >= 3) {
- /* We guessed wrong earlier. Fix it up. */
- trans->type = optype;
- }
+
if (optype != trans->type) {
printf("ICH SPI: Transaction doesn't fit type %d\n",
optype);
@@ -300,26 +250,6 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr,
struct spi_trans *trans,
}
}
-static int spi_setup_offset(struct spi_trans *trans)
-{
- /* Separate the SPI address and data */
- switch (trans->type) {
- case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
- case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
- return 0;
- case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
- case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
- trans->offset = ((uint32_t)trans->out[0] << 16) |
- ((uint32_t)trans->out[1] << 8) |
- ((uint32_t)trans->out[2] << 0);
- spi_use_out(trans, 3);
- return 1;
- default:
- printf("Unrecognized SPI transaction type %#x\n", trans->type);
- return -EPROTO;
- }
-}
-
/*
* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
[U-Boot] Antwort: [PATCH v2] x86: ich-spi: Convert driver to spi-mem ops
Hello Bin,
> Von: "Bin Meng"
> An: "Simon Glass" , "Bernhard Messerklinger"
> , "Vignesh Raghavendra"
> , "U-Boot Mailing List"
> Kopie: "Bernhard Messerklinger"
> Datum: 07/28/2019 01:31 PM
> Betreff: [PATCH v2] x86: ich-spi: Convert driver to spi-mem ops
>
> From: Bernhard Messerklinger
>
> With the introduction of the new spi-mem model operations changed
> slightly. The new spi-mem operations make things a bit easier to
> handle for ich-spi flash interface. This patch converts the ich-spi
> driver by using spi-mem operations.
>
> Signed-off-by: Bernhard Messerklinger automation.com>
> Reviewed-by: Bin Meng
> Tested-by: Bin Meng
> [bmeng: make 2 routines static; update commit message a little bit]
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - make 2 routines static; update commit message a little bit
> +--
> + if (op->data.dir == SPI_MEM_DATA_OUT) {
> + if (op->addr.nbytes ||
> + (!op->addr.nbytes && op->data.nbytes == 3))
> + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
> + else
> + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
> + } else {
> + if (op->addr.nbytes)
> + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
> + else
> + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
> + }
> +
> opcode_index = spi_setup_opcode(ctlr, trans, lock);
> if (opcode_index < 0)
>return -EINVAL;
> - with_address = spi_setup_offset(trans);
> - if (with_address < 0)
> - return -EINVAL;
> +
> + /* Handle special case for erase where address is stored in data */
> + if (op->addr.nbytes) {
> + trans->offset = op->addr.val;
> + with_address = 1;
> + } else if (op->data.nbytes == 3 && trans->bytesout) {
> + trans->offset = ((uint32_t)trans->out[0] << 16) |
> +((uint32_t)trans->out[1] << 8) |
> +((uint32_t)trans->out[2] << 0);
> + with_address = 1;
> + trans->bytesout = 0;
> + }
this patch is a bit out of sync with the latest master spi-nor driver.
Commit f909ddb3e1770a5ef18606b46000e0d3eaf63b2e changes the erase
behavior.
I allready fixed this so if desired I could send a v3 for review.
Regards,
Bernhard
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[U-Boot] [PATCH] x86: ich-spi: Convert driver to spi-mem ops
With the introduction of the new spi-mem model operations changed
slightly, which broke the ich-spi driver. The new spi-mem operations
make things a bit easier to handle for ich flash interface. This patch
makes ich-spi work again by using spi-mem operations.
Signed-off-by: Bernhard Messerklinger
---
Unfortunately I only have apollo lake HW so I can't test
with the other boards. Please give feedback if anybody is interested in
this patch or any errors appear.
drivers/spi/ich.c | 250 +-
drivers/spi/ich.h | 9 +-
2 files changed, 96 insertions(+), 163 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 03531a8c0c..6e6e606da9 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -14,6 +14,8 @@
#include
#include
#include
+#include
+#include
#include "ich.h"
@@ -171,18 +173,6 @@ static int ich_init_controller(struct udevice *dev,
return 0;
}
-static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
-{
- trans->out += bytes;
- trans->bytesout -= bytes;
-}
-
-static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
-{
- trans->in += bytes;
- trans->bytesin -= bytes;
-}
-
static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
{
if (plat->ich_version == ICHV_7) {
@@ -213,47 +203,12 @@ static bool spi_lock_status(struct ich_spi_platdata
*plat, void *sbase)
return lock != 0;
}
-static void spi_setup_type(struct spi_trans *trans, int data_bytes)
-{
- trans->type = 0xFF;
-
- /* Try to guess spi type from read/write sizes */
- if (trans->bytesin == 0) {
- if (trans->bytesout + data_bytes > 4)
- /*
-* If bytesin = 0 and bytesout > 4, we presume this is
-* a write data operation, which is accompanied by an
-* address.
-*/
- trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
- else
- trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
- return;
- }
-
- if (trans->bytesout == 1) { /* and bytesin is > 0 */
- trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
- return;
- }
-
- if (trans->bytesout == 4) /* and bytesin is > 0 */
- trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
-
- /* Fast read command is called with 5 bytes instead of 4 */
- if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
- trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
- --trans->bytesout;
- }
-}
-
static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
bool lock)
{
uint16_t optypes;
uint8_t opmenu[ctlr->menubytes];
- trans->opcode = trans->out[0];
- spi_use_out(trans, 1);
if (!lock) {
/* The lock is off, so just use index 0. */
ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
@@ -300,26 +255,6 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr,
struct spi_trans *trans,
}
}
-static int spi_setup_offset(struct spi_trans *trans)
-{
- /* Separate the SPI address and data */
- switch (trans->type) {
- case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
- case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
- return 0;
- case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
- case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
- trans->offset = ((uint32_t)trans->out[0] << 16) |
- ((uint32_t)trans->out[1] << 8) |
- ((uint32_t)trans->out[2] << 0);
- spi_use_out(trans, 3);
- return 1;
- default:
- printf("Unrecognized SPI transaction type %#x\n", trans->type);
- return -EPROTO;
- }
-}
-
/*
* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
* below is true) or 0. In case the wait was for the bit(s) to set - write
@@ -365,73 +300,35 @@ void ich_spi_config_opcode(struct udevice *dev)
ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
}
-static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
{
- struct udevice *bus = dev_get_parent(dev);
+ struct udevice *bus = dev_get_parent(slave->dev);
struct ich_spi_platdata *plat = dev_get_platdata(bus);
struct ich_spi_priv *ctlr = dev_get_priv(bus);
- uint16_t control;
- int16_t opcode_index;
- int with
[U-Boot] [PATCH] spi: spi-mem: Check if exec_op function is set before calling it
Add check if exec_op is set before calling it.
At the moment it is called unconditionally, which leads to a crash if it
is not set correctly.
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/spi-mem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 1bb0987edb..b86eee75bc 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -214,7 +214,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
if (ret < 0)
return ret;
- if (ops->mem_ops) {
+ if (ops->mem_ops && ops->mem_ops->exec_op) {
#ifndef __UBOOT__
/*
* Flush the message queue before executing our SPI memory
--
2.21.0
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[U-Boot] Antwort: [PATCH v2] fs: fat: fix reading non-cluster-aligned root directory
Reviewed-by: Bernhard Messerklinger
Tested-by: Bernhard Messerklinger
Von:Anssi Hannula
An: u-boot@lists.denx.de, Bernhard Messerklinger
Kopie: Hannes Schmelzer
Datum: 02/27/2019 11:56 AM
Betreff:[PATCH v2] fs: fat: fix reading non-cluster-aligned root
directory
A FAT12/FAT16 root directory location is specified by a sector offset and
it might not start at a cluster boundary. It also resides before the
data area (before cluster 2).
However, the current code assumes that the root directory is located at
a beginning of a cluster, causing no files to be found if that is not
the case.
Since the FAT12/FAT16 root directory is located before the data area
and is not aligned to clusters, using unsigned cluster numbers to refer
to the root directory does not work well (the "cluster number" may be
negative, and even allowing it be signed would not make it properly
aligned).
Modify the code to not use the normal cluster numbering when referring to
the root directory of FAT12/FAT16 and instead use a cluster-sized
offsets counted from the root directory start sector.
This is a relatively common case as at least the filesystem formatter on
Win7 seems to create such filesystems by default on 2GB USB sticks when
"FAT" is selected (cluster size 64 sectors, rootdir size 32 sectors,
rootdir starts at half a cluster before cluster 2).
dosfstools mkfs.vfat does not seem to create affected filesystems.
Signed-off-by: Anssi Hannula
---
v2: Rewrite to avoid negative "cluster numbers".
Hi,
I'm sorry about not responding in a timely manner.
Bernhard Messerklinger wrote:
> clust_size = 2
> rootdir_sect = 113
> dara_begin = 132
>
> sect_to_clust: 0xfff1 = (0x113 - 132) / 2
> sect_to_clust: 114 = 132 + 0xfff1 * 2
>
> Now my root_cluster is above the root dir but it should be below it
(112).
You are right, root_cluster going negative is not being handled properly.
However, I'd rather avoid that in the first place, as the code generally
assumes that cluster numbers are unsigned - which is the reality as well,
it is just that the FAT12/16 rootdir is located before the clusters.
So here is a different take on the original patch that instead avoids
using the "cluster numbers" to refer to the root directory on FAT12/16
altogether.
fs/fat/fat.c | 47 ++-
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 6ade4ea54e..c5997c2173 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -602,8 +602,13 @@ static int get_fs_info(fsdata *mydata)
mydata->data_begin = mydata->rootdir_sect
+
mydata->rootdir_size -
(mydata->clust_size * 2);
-mydata->root_cluster =
-sect_to_clust(mydata,
mydata->rootdir_sect);
+
+/*
+ * The root directory is not
cluster-aligned and may be on a
+ * "negative" cluster, this will be
handled specially in
+ * next_cluster().
+ */
+mydata->root_cluster = 0;
}
mydata->fatbufnum = -1;
@@ -733,20 +738,38 @@ static void fat_itr_child(fat_itr *itr, fat_itr
*parent)
itr->last_cluster = 0;
}
-static void *next_cluster(fat_itr *itr)
+static void *next_cluster(fat_itr *itr, unsigned *nbytes)
{
fsdata *mydata = itr->fsdata; /* for silly macros */
int ret;
u32 sect;
+u32 read_size;
/* have we reached the end? */
if (itr->last_cluster)
return NULL;
-sect = clust_to_sect(itr->fsdata, itr->next_clust);
+if (itr->is_root && itr->fsdata->fatsize != 32) {
+/*
+ * The root directory is located before
the data area and
+ * cannot be indexed using the regular
unsigned cluster
+ * numbers (it may start at a "negative"
cluster or not at a
+ * cluster boundary at all), so consider
itr->next_clust to be
+ * a offset in cluster-sized units from
the start of rootdir.
+ */
+unsigned sect_offset = itr->next_clust *
itr->fsdata->clust_size;
+unsigned remaining_sects =
itr->fsdata->rootdir_size - sect_offset;
+sect = itr->fsdata->rootdir_sect +
sect_offset;
+/*
[U-Boot] [PATCH v3] x86: tsc: Add support for native calibration of TSC freq
Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does in arch/x86/kernel/tsc.c.
Fixes booting for Apollo Lake processors.
Signed-off-by: Bernhard Messerklinger
---
I hope this patch won't break other x86 board.
I only can test it with APL board.
Changes in v4:
- Fix commit message
- Update macro names
- Order macro numbers
- Check cpuid eax and ebx return value
drivers/timer/tsc_timer.c | 55 +++
1 file changed, 55 insertions(+)
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index ba940ebf1c..919caba8a1 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -19,8 +19,59 @@
#define MAX_NUM_FREQS 9
+#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
+#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
+#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
+#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
+#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
+#define INTEL_FAM6_KABYLAKE_DESKTOP0x9E
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * native_calibrate_tsc
+ * Determine TSC frequency via CPUID, else return 0.
+ */
+static unsigned long native_calibrate_tsc(void)
+{
+ struct cpuid_result tsc_info;
+ unsigned int crystal_freq;
+
+ if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+ return 0;
+
+ if (cpuid_eax(0) < 0x15)
+ return 0;
+
+ tsc_info = cpuid(0x15);
+
+ if (tsc_info.ebx == 0 || tsc_info.eax == 0)
+ return 0;
+
+ crystal_freq = tsc_info.ecx / 1000;
+
+ if (!crystal_freq) {
+ switch (gd->arch.x86_model) {
+ case INTEL_FAM6_SKYLAKE_MOBILE:
+ case INTEL_FAM6_SKYLAKE_DESKTOP:
+ case INTEL_FAM6_KABYLAKE_MOBILE:
+ case INTEL_FAM6_KABYLAKE_DESKTOP:
+ crystal_freq = 24000; /* 24.0 MHz */
+ break;
+ case INTEL_FAM6_ATOM_GOLDMONT_X:
+ crystal_freq = 25000; /* 25.0 MHz */
+ break;
+ case INTEL_FAM6_ATOM_GOLDMONT:
+ crystal_freq = 19200; /* 19.2 MHz */
+ break;
+ default:
+ return 0;
+ }
+ }
+
+ return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
+}
+
static unsigned long cpu_mhz_from_cpuid(void)
{
if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
@@ -350,6 +401,10 @@ static void tsc_timer_ensure_setup(bool early)
if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
+ fast_calibrate = native_calibrate_tsc();
+ if (fast_calibrate)
+ goto done;
+
fast_calibrate = cpu_mhz_from_cpuid();
if (fast_calibrate)
goto done;
--
2.20.1
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[U-Boot] [PATCH v2] x86: tsc: Add support for native calibration of TSC freq
Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does arch/x86/kernel/tsc.c.
Fixes booting for Apollo Lake processors.
Signed-off-by: Bernhard Messerklinger
---
I hope this patch won't break other x86 board.
I only can test it with APL board.
Changes in v1:
- Update to linux way of dealing with TSC calibration
drivers/timer/tsc_timer.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index ba940ebf1c..ec7f05db17 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -19,8 +19,56 @@
#define MAX_NUM_FREQS 9
+#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
+#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
+#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
+#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
+#define INTEL_FAM6_KABYLAKE_DESKTOP0x9E
+#define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * native_calibrate_tsc
+ * Determine TSC frequency via CPUID, else return 0.
+ */
+static unsigned long native_calibrate_tsc(void)
+{
+ struct cpuid_result tsc_info;
+ unsigned int crystal_freq;
+
+ if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+ return 0;
+
+ if (cpuid_eax(0) < 0x15)
+ return 0;
+
+ tsc_info = cpuid(0x15);
+
+ crystal_freq = tsc_info.ecx / 1000;
+
+ if (!crystal_freq) {
+ switch (gd->arch.x86_model) {
+ case INTEL_FAM6_SKYLAKE_MOBILE:
+ case INTEL_FAM6_SKYLAKE_DESKTOP:
+ case INTEL_FAM6_KABYLAKE_MOBILE:
+ case INTEL_FAM6_KABYLAKE_DESKTOP:
+ crystal_freq = 24000; /* 24.0 MHz */
+ break;
+ case INTEL_FAM6_ATOM_DENVERTON:
+ crystal_freq = 25000; /* 25.0 MHz */
+ break;
+ case INTEL_FAM6_ATOM_GOLDMONT:
+ crystal_freq = 19200; /* 19.2 MHz */
+ break;
+ default:
+ return 0;
+ }
+ }
+
+ return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
+}
+
static unsigned long cpu_mhz_from_cpuid(void)
{
if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
@@ -350,6 +398,10 @@ static void tsc_timer_ensure_setup(bool early)
if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
+ fast_calibrate = native_calibrate_tsc();
+ if (fast_calibrate)
+ goto done;
+
fast_calibrate = cpu_mhz_from_cpuid();
if (fast_calibrate)
goto done;
--
2.20.1
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[U-Boot] Antwort: Re: Re: [PATCH] x86: tsc: Add support for APL soc
> > > > > > Are you saying that if doing cpu_mhz_from_cpuid() you can't
get
> > > > > > correct frequency? Can you investigate why your core crystal
clock
> > is
> > > > > > always zero?
> > > > >
> > > > > Yes, this has to be investigated.
> > > > >
> > > > > > Can we do it something like VLV2?
> > > > >
> > > > > Please, don't. I see no evidence in the latest Linux kernel
sources
> > > > > that Apollo Lake has such issue as Intel MID family of Atom
SoCs.
> > > >
> > > > Sorry, I slipped one code in my consideration, i.e.
> > > >
> > > > unsigned long native_calibrate_tsc(void)
> > > > {
> > > > ...
> > > > if (crystal_khz == 0) {
> > > > switch (boot_cpu_data.x86_model) {
> > > > ...
> > > > case INTEL_FAM6_ATOM_GOLDMONT:
> > > > crystal_khz = 19200; /* 19.2 MHz */
> > > > break;
> > > > }
> > > > ...
> > > > if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> > > > setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > > > ...
> > > > }
> > > >
> > > > So, that's what we need to do in U-boot.
> > > >
> > >
> > > Thanks for the investigation. Could you please send a proper patch?
> > do you want to take charge of this?
> > Otherwise I will post patch V2.
>
> I'm busy with something else, so, if you don't mind, please, consider
> v2 which takes into consideration my findings.
Ok, as soon as I am done I will post v2.
--
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[U-Boot] Antwort: Re: [PATCH] x86: tsc: Add support for APL soc
Hi Andy,
> Von: Bin Meng
> An: Andy Shevchenko ,
> Kopie: Bernhard Messerklinger automation.com>, U-Boot Mailing List
> Datum: 25.11.2018 15:50
> Betreff: Re: [U-Boot] [PATCH] x86: tsc: Add support for APL soc
>
> Hi Andy,
>
> On Sun, Nov 25, 2018 at 10:43 PM Andy Shevchenko
> wrote:
> >
> > On Sun, Nov 25, 2018 at 4:31 PM Andy Shevchenko
> > wrote:
> > > On Sat, Nov 24, 2018 at 5:39 PM Bin Meng wrote:
> >
> > > > Are you saying that if doing cpu_mhz_from_cpuid() you can't get
> > > > correct frequency? Can you investigate why your core crystal clock
is
> > > > always zero?
> > >
> > > Yes, this has to be investigated.
> > >
> > > > Can we do it something like VLV2?
> > >
> > > Please, don't. I see no evidence in the latest Linux kernel sources
> > > that Apollo Lake has such issue as Intel MID family of Atom SoCs.
> >
> > Sorry, I slipped one code in my consideration, i.e.
> >
> > unsigned long native_calibrate_tsc(void)
> > {
> > ...
> > if (crystal_khz == 0) {
> > switch (boot_cpu_data.x86_model) {
> > ...
> > case INTEL_FAM6_ATOM_GOLDMONT:
> > crystal_khz = 19200; /* 19.2 MHz */
> > break;
> > }
> > ...
> > if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> > setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > ...
> > }
> >
> > So, that's what we need to do in U-boot.
> >
>
> Thanks for the investigation. Could you please send a proper patch?
do you want to take charge of this?
Otherwise I will post patch V2.
>
> Regards,
> Bin
Regards,
Bernhard
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[U-Boot] Antwort: Re: [PATCH] x86: tsc: Add support for APL soc
Hi Bin,
> Missing commit message
I will fix this.
>
> APL means ApolloLake? Could you please spell it out?
I will fix this.
>
> > Signed-off-by: Bernhard Messerklinger automation.com>
> > ---
> >
> > drivers/timer/tsc_timer.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> > index da7c812908..b2a982812a 100644
> > --- a/drivers/timer/tsc_timer.c
> > +++ b/drivers/timer/tsc_timer.c
> > @@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = {
> > 8, 93300, 9, 88900, 87500 } },
> > /* Ivybridge */
> > { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> > + /* Intel Atom processor E3900 series */
> > + { 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
>
> Please avoid hardcoding TSC freq this way. Isn't calibrating from MSR
> not working for ApolloLake?
I found two ways to get the TSC freq.
1. Read the necessary parameters with cpuid(instruction 15) like it is
done in
the kernel.
The problem with this way is that for some reason my core crystal clock is
always set to zero, so I would need to add the crystal frequency
somewhere.
2. Read it from MSR.
That?s actually the way I do it in this patch. I only need to add my cpu
family/model to avoid return with 0 at the begin of cpu_mhz_from_msr.
Please tell me if I overlook something.
Regards,
Bernhard
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[U-Boot] Antwort: [PATCH] fs: fat: fix reading non-cluster-aligned root directory
Hi Anssi, I tested your patch because i faced the same problem. But I need an addition to your patch to get everything to work. Since for fat12/16 the sect_to_clust() calculation is always a negative value the division through the cluster size with an odd negative value cuts the rest. With the next clust_to_sect() call the now even cluster number is multiplied by the cluster size and and the data_begin section is added. So after the calculation without the rest the negative value is smaller and my rootdir_sect is higher then the actual rootdir_sect. In my case: clust_size = 2 rootdir_sect = 113 dara_begin = 132 sect_to_clust: 0xfff1 = (0x113 - 132) / 2 sect_to_clust: 114 = 132 + 0xfff1 * 2 Now my root_cluster is above the root dir but it should be below it (112). I fixed this with the following patch: --- fs/fat/fat.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index de5c7210be..695b6323b1 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -587,7 +587,9 @@ static int get_fs_info(fsdata *mydata) mydata->rootdir_size - (mydata->clust_size * 2); mydata->root_cluster = - sect_to_clust(mydata, mydata->rootdir_sect); + sect_to_clust(mydata, mydata->rootdir_sect - + (mydata->rootdir_sect % + mydata->clust_size)); } mydata->fatbufnum = -1; After patch: sect_to_clust: 0xfff0 = (0x112 - 132) / 2 sect_to_clust: 112 = 132 + 0xfff0 * 2 Can you verify this? If yes? Is it maybe possible to add this to your patch? Regards, Bernhard ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Antwort: Re: [PATCH] spi: mxc_spi: Fix chipselect with DM_SPI in SPL
> Von: Bernhard Messerklinger/Eggelsberg/AT/B > An: Jagan Teki , > Kopie: Jagan Teki , U-Boot-Denx > Datum: 04.09.2018 10:54 > Betreff: Antwort: Re: [U-Boot] [PATCH] spi: mxc_spi: Fix chipselect > with DM_SPI in SPL > > Hi Jagan, > > it's not about any size constraint. > To my understanding the macro CONFIG_IS_ENABLED(DM_SPI) is true if > CONFIG_SPL_DM_SPI is defined during SPL build. Please tell me if I am wrong. > At the moment this configuration parameter doesn't exist, so I used a #ifdef > which works with CONFIG_DM_SPI. > > Would you prefer to add CONFIG_SPL_DM_SPI as configuration parameter? > > Bernhard > > Von: Jagan Teki > An: Bernhard Messerklinger , > Kopie: U-Boot-Denx , Jagan Teki > Datum: 03.09.2018 18:33 > Betreff: Re: [U-Boot] [PATCH] spi: mxc_spi: Fix chipselect with DM_SPI in SPL > > On Mon, Sep 3, 2018 at 4:02 PM, Bernhard Messerklinger > wrote: > > Since CONFIG_IS_ENABLED(DM_SPI) is not working in SPL because > > CONFIG_SPL_DM_SPI is not defined we should go with #ifdef CONFIG_DM_SPI. > > Better enabled it for SPL, did you find any size constraint? if yet > try for platdata? Hi Jagan, Are there any news? Regards, Bernhard ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] x86: tsc: Add support for APL soc
Signed-off-by: Bernhard Messerklinger
---
drivers/timer/tsc_timer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index da7c812908..b2a982812a 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = {
8, 93300, 9, 88900, 87500 } },
/* Ivybridge */
{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ /* Intel Atom processor E3900 series */
+ { 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
};
static int match_cpu(u8 family, u8 model)
--
2.19.1
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[U-Boot] [PATCH 2/2] spi: ich-spi: Add DT spi-max-frequency support
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/ich.c | 7 +++
drivers/spi/ich.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index d84bbdb2e5..4ec107d323 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -213,6 +213,10 @@ static int ich_init_controller(struct udevice *dev,
return -EINVAL;
}
+ /* Check devicetree for max frequency */
+ if (plat->max_speed)
+ ctlr->max_speed = plat->max_speed;
+
debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
plat->ich_version, ctlr->base, ctlr->max_speed);
@@ -784,6 +788,9 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev)
plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node,
"intel,spi-lock-down");
+ plat->max_speed = fdtdec_get_uint(gd->fdt_blob, node,
+ "spi-max-frequency", 0);
+
return ret;
}
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index 5e3ac2d2c2..85ddc171cc 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -214,6 +214,7 @@ struct ich_spi_platdata {
enum ich_version ich_version; /* Controller version*/
bool lockdown; /* lock down controller settings? */
unsigned long base; /* PCI device BAR */
+ unsigned long max_speed;
};
struct ich_spi_priv {
--
2.19.1
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[U-Boot] [PATCH 1/2] spi: ich-spi: Add APL support
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/ich.c | 168 +-
drivers/spi/ich.h | 46 -
2 files changed, 178 insertions(+), 36 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 03531a8c0c..d84bbdb2e5 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -110,6 +110,34 @@ static int ich9_can_do_33mhz(struct udevice *dev)
return speed == 1;
}
+/* @return speed register bit mask from speed */
+static int ich_speed_to_mask(enum ich_version ver, unsigned long speed)
+{
+ int size = 0;
+ const unsigned long *list = NULL;
+ int i;
+ int act = 0;
+ int64_t diff = 0;
+
+ if (ver == ICHV_9) {
+ size = ARRAY_SIZE(ich9_speed);
+ list = ich9_speed;
+ } else if (ver == ICUV_APL) {
+ size = ARRAY_SIZE(pcu_apl_speed);
+ list = pcu_apl_speed;
+ }
+
+ for (i = 1; i < size; i++) {
+ diff = speed - list[i];
+ if (diff >= 0) {
+ if (diff < (speed - list[act]))
+ act = i;
+ }
+ }
+
+ return act;
+}
+
static int ich_init_controller(struct udevice *dev,
struct ich_spi_platdata *plat,
struct ich_spi_priv *ctlr)
@@ -117,9 +145,14 @@ static int ich_init_controller(struct udevice *dev,
ulong sbase_addr;
void *sbase;
- /* SBASE is similar */
- pch_get_spi_base(dev->parent, _addr);
- sbase = (void *)sbase_addr;
+ if (plat->ich_version == ICHV_7 ||
+ plat->ich_version == ICHV_9) {
+ /* SBASE is similar */
+ pch_get_spi_base(dev->parent, _addr);
+ sbase = (void *)sbase_addr;
+ } else {
+ sbase = (void *)plat->base;
+ }
debug("%s: sbase=%p\n", __func__, sbase);
if (plat->ich_version == ICHV_7) {
@@ -136,6 +169,7 @@ static int ich_init_controller(struct udevice *dev,
ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
ctlr->preop = offsetof(struct ich7_spi_regs, preop);
ctlr->base = ich7_spi;
+ ctlr->max_speed = 2000;
} else if (plat->ich_version == ICHV_9) {
struct ich9_spi_regs *ich9_spi = sbase;
@@ -153,20 +187,38 @@ static int ich_init_controller(struct udevice *dev,
ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
ctlr->pr = _spi->pr[0];
ctlr->base = ich9_spi;
+ if (ich9_can_do_33mhz(dev))
+ ctlr->max_speed = 3300;
+ else
+ ctlr->max_speed = 2000;
+ } else if (plat->ich_version == ICUV_APL) {
+ struct pcu_apl_spi_regs *pcu_spi = sbase;
+
+ ctlr->opmenu = offsetof(struct pcu_apl_spi_regs, opmenu);
+ ctlr->menubytes = sizeof(pcu_spi->opmenu);
+ ctlr->optype = offsetof(struct pcu_apl_spi_regs, optype);
+ ctlr->addr = offsetof(struct pcu_apl_spi_regs, faddr);
+ ctlr->data = offsetof(struct pcu_apl_spi_regs, fdata);
+ ctlr->databytes = sizeof(pcu_spi->fdata);
+ ctlr->status = offsetof(struct pcu_apl_spi_regs, ssfs);
+ ctlr->control = offsetof(struct pcu_apl_spi_regs, ssfc);
+ ctlr->speed = ctlr->control + 2;
+ ctlr->preop = offsetof(struct pcu_apl_spi_regs, preop);
+ ctlr->pr = _spi->pr[0];
+ ctlr->base = pcu_spi;
+ ctlr->max_speed = 12000;
} else {
debug("ICH SPI: Unrecognised ICH version %d\n",
plat->ich_version);
return -EINVAL;
}
- /* Work out the maximum speed we can support */
- ctlr->max_speed = 2000;
- if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
- ctlr->max_speed = 3300;
debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
plat->ich_version, ctlr->base, ctlr->max_speed);
- ich_set_bbar(ctlr, 0);
+ if (plat->ich_version == ICHV_7 ||
+ plat->ich_version == ICHV_9)
+ ich_set_bbar(ctlr, 0);
return 0;
}
@@ -193,6 +245,10 @@ static void spi_lock_down(struct ich_spi_platdata *plat,
void *sbase)
struct ich9_spi_regs *ich9_spi = sbase;
setbits_le16(_spi->hsfs, HSFS_FLOCKDN);
+ } else if (plat->ich_version == ICUV_APL) {
+ struct pcu_apl_spi_regs *ipcu_spi = sbase;
+
+ setbits_le16(_spi->hsfs, HSFS_FLOCKDN);
}
}
@@ -208,6 +264,10 @@ static bool sp
[U-Boot] Antwort: Re: [PATCH] spi: mxc_spi: Fix chipselect with DM_SPI in SPL
Hi Jagan, it's not about any size constraint. To my understanding the macro CONFIG_IS_ENABLED(DM_SPI) is true if CONFIG_SPL_DM_SPI is defined during SPL build. Please tell me if I am wrong. At the moment this configuration parameter doesn't exist, so I used a #ifdef which works with CONFIG_DM_SPI. Would you prefer to add CONFIG_SPL_DM_SPI as configuration parameter? Bernhard Von:Jagan Teki An: Bernhard Messerklinger , Kopie: U-Boot-Denx , Jagan Teki Datum: 03.09.2018 18:33 Betreff:Re: [U-Boot] [PATCH] spi: mxc_spi: Fix chipselect with DM_SPI in SPL On Mon, Sep 3, 2018 at 4:02 PM, Bernhard Messerklinger wrote: > Since CONFIG_IS_ENABLED(DM_SPI) is not working in SPL because > CONFIG_SPL_DM_SPI is not defined we should go with #ifdef CONFIG_DM_SPI. Better enabled it for SPL, did you find any size constraint? if yet try for platdata? ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] spi: mxc_spi: Fix chipselect with DM_SPI in SPL
Since CONFIG_IS_ENABLED(DM_SPI) is not working in SPL because
CONFIG_SPL_DM_SPI is not defined we should go with #ifdef CONFIG_DM_SPI.
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/mxc_spi.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 0dccc38b82..bd31e79505 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -57,26 +57,30 @@ static inline struct mxc_spi_slave *to_mxc_spi_slave(struct
spi_slave *slave)
return container_of(slave, struct mxc_spi_slave, slave);
}
+#ifdef CONFIG_DM_SPI
static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
- if (CONFIG_IS_ENABLED(DM_SPI)) {
- dm_gpio_set_value(>ss, 1);
- } else {
- if (mxcs->gpio > 0)
- gpio_set_value(mxcs->gpio, mxcs->ss_pol);
- }
+ dm_gpio_set_value(>ss, 1);
}
static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
- if (CONFIG_IS_ENABLED(DM_SPI)) {
- dm_gpio_set_value(>ss, 0);
- } else {
- if (mxcs->gpio > 0)
- gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
- }
+ dm_gpio_set_value(>ss, 0);
+}
+#else
+static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
+{
+ if (mxcs->gpio > 0)
+ gpio_set_value(mxcs->gpio, mxcs->ss_pol);
}
+static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
+{
+ if (mxcs->gpio > 0)
+ gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
+}
+#endif
+
u32 get_cspi_div(u32 div)
{
int i;
--
2.18.0
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[U-Boot] [PATCH] serial: mxc: Add match string for i.mx6 quad/dual lite serial
Signed-off-by: Bernhard Messerklinger
---
drivers/serial/serial_mxc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 4f1f822c58..e586c18cf0 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -339,6 +339,7 @@ static int mxc_serial_ofdata_to_platdata(struct udevice
*dev)
static const struct udevice_id mxc_serial_ids[] = {
{ .compatible = "fsl,imx6ul-uart" },
{ .compatible = "fsl,imx7d-uart" },
+ { .compatible = "fsl,imx6q-uart" },
{ }
};
#endif
--
2.18.0
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Re: [U-Boot] [PATCH] pci: Fix decode regions for memory banks
Hi,
Thanks for the report.
I am answering from my private email. At the moment I can't find any issue
regarding my patch. It should make no difference since dram_init_banksize in
quark/dram.c should set the dram bank. I will continue my investigation and
contact you if I find out something.
Regards,
Bernhard
On Thu, Mar 22, 2018 at 10:06 AM, Bin Meng <bmeng...@gmail.com> wrote:
> Hi,
>
> On Thu, Feb 15, 2018 at 3:59 PM, Bernhard Messerklinger
> <bernhard.messerklin...@br-automation.com> wrote:
>> Since memory banks may not be located behind each other we need to add
>> them separately.
>>
>> Signed-off-by: Bernhard Messerklinger
>> <bernhard.messerklin...@br-automation.com>
>> ---
>>
>> drivers/pci/pci-uclass.c | 17 -
>> 1 file changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
>> index 5a24eb6428..ad43e8a27c 100644
>> --- a/drivers/pci/pci-uclass.c
>> +++ b/drivers/pci/pci-uclass.c
>> @@ -815,7 +815,6 @@ static int decode_regions(struct pci_controller *hose,
>> ofnode parent_node,
>> ofnode node)
>> {
>> int pci_addr_cells, addr_cells, size_cells;
>> - phys_addr_t base = 0, size;
>> int cells_per_record;
>> const u32 *prop;
>> int len;
>> @@ -874,6 +873,21 @@ static int decode_regions(struct pci_controller *hose,
>> ofnode parent_node,
>> }
>>
>> /* Add a region for our local memory */
>> +#ifdef CONFIG_NR_DRAM_BANKS
>> + bd_t *bd = gd->bd;
>> +
>> + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
>> + if (bd->bi_dram[i].size) {
>> + pci_set_region(hose->regions + hose->region_count++,
>> + bd->bi_dram[i].start,
>> + bd->bi_dram[i].start,
>> + bd->bi_dram[i].size,
>> + PCI_REGION_MEM |
>> PCI_REGION_SYS_MEMORY);
>> + }
>> + }
>> +#else
>
> Sorry for jumping out. With this commit, Intel Galileo board does not
> boot any more. x86 defines CONFIG_NR_DRAM_BANKS in x86-common.h, so
> this commit forces x86 to use the new logic instead of the old one,
> which breaks things. I have not debugged this on how to fix it. Any
> ideas?
>
>> + phys_addr_t base = 0, size;
>> +
>> size = gd->ram_size;
>> #ifdef CONFIG_SYS_SDRAM_BASE
>> base = CONFIG_SYS_SDRAM_BASE;
>> @@ -882,6 +896,7 @@ static int decode_regions(struct pci_controller *hose,
>> ofnode parent_node,
>> size = gd->pci_ram_top - base;
>> pci_set_region(hose->regions + hose->region_count++, base, base,
>>size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
>> +#endif
>>
>> return 0;
>> }
>> --
>
> Regards,
> Bin
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[U-Boot] [PATCH] x86: mmc: Fix mapping of BAR memory
Use dm_pci_map_bar function for BAR mapping. This has the advantage of clearing BAR flags and and only accepting mapped memory. Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com> --- drivers/mmc/pci_mmc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 05c0044a7a..616af5afbf 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -29,11 +29,10 @@ static int pci_mmc_probe(struct udevice *dev) struct pci_mmc_plat *plat = dev_get_platdata(dev); struct pci_mmc_priv *priv = dev_get_priv(dev); struct sdhci_host *host = >host; - u32 ioaddr; int ret; - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, ); - host->ioaddr = map_sysmem(ioaddr, 0); + host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); host->name = dev->name; ret = sdhci_setup_cfg(>cfg, host, 0, 0); if (ret) -- 2.16.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ns16550: Fix mem mapped endian check
Do a explicit check for CONFIG_SYS_BIG_ENDIAN and
CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both
are undefined (x86).
Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com>
---
drivers/serial/ns16550.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 6f9ce689cf..53550bfa88 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -55,7 +55,7 @@ static inline void serial_out_shift(void *addr, int shift,
int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
outb(value, (ulong)addr);
-#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
+#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
out_le32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
out_be32(addr, value);
@@ -72,7 +72,7 @@ static inline int serial_in_shift(void *addr, int shift)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
return inb((ulong)addr);
-#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
+#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
return in_le32(addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
return in_be32(addr);
--
2.16.1
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[U-Boot] [PATCH] pci: Fix decode regions for memory banks
Since memory banks may not be located behind each other we need to add
them separately.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com>
---
drivers/pci/pci-uclass.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 5a24eb6428..ad43e8a27c 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -815,7 +815,6 @@ static int decode_regions(struct pci_controller *hose,
ofnode parent_node,
ofnode node)
{
int pci_addr_cells, addr_cells, size_cells;
- phys_addr_t base = 0, size;
int cells_per_record;
const u32 *prop;
int len;
@@ -874,6 +873,21 @@ static int decode_regions(struct pci_controller *hose,
ofnode parent_node,
}
/* Add a region for our local memory */
+#ifdef CONFIG_NR_DRAM_BANKS
+ bd_t *bd = gd->bd;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ pci_set_region(hose->regions + hose->region_count++,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ }
+ }
+#else
+ phys_addr_t base = 0, size;
+
size = gd->ram_size;
#ifdef CONFIG_SYS_SDRAM_BASE
base = CONFIG_SYS_SDRAM_BASE;
@@ -882,6 +896,7 @@ static int decode_regions(struct pci_controller *hose,
ofnode parent_node,
size = gd->pci_ram_top - base;
pci_set_region(hose->regions + hose->region_count++, base, base,
size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+#endif
return 0;
}
--
2.16.1
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[U-Boot] [PATCH] net: e1000: Fix e1000_igb semaphore handling
Fix commit f1bcad22dd19 ("net: e1000: add support for writing to
EEPROM").
Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com>
---
drivers/net/e1000.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 8316854bc1..5cc54efe48 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -1181,7 +1181,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
return;
swsm = E1000_READ_REG(hw, SWSM);
- if (hw->mac_type == e1000_80003es2lan) {
+ if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
/* Release both semaphores. */
swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
} else
--
2.16.1
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[U-Boot] [PATCH] cmd/fdt.c align data buffer to avoid unaligned word access
Since the compiler is free to place a char array to any address in memory (in this case the stack), also to a non word aligned address the function "fdt_prop_parse" runs into troubles upon it wants to write some (fdt32_t *) to such a variable (if it has been placed to a none word aligned address). To avoid this we tell the compiler to always align this scratchpad to a word aligned address. Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com> --- cmd/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/fdt.c b/cmd/fdt.c index d7654b2c4f..aa9cb4b3c1 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -256,7 +256,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *pathp;/* path */ char *prop; /* property */ int nodeoffset;/* node offset from libfdt */ - static char data[SCRATCHPAD]; /* storage for the property */ + static char data[SCRATCHPAD] __aligned(4);/* property storage */ const void *ptmp; int len; /* new length of the property */ int ret; /* return value */ -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] i.MX6DL USB OTG Gadget ether with DM_USB and DM_ETH?
Hi,
I am trying to use the usb otg port of our custom board as usb_ether
interface.
Everything works fine without device model enabled. But since everything
new should
be done with DM I tried to use usb_ether with CONFIG_DM_ETH and
CONFIG_DM_USB.
The usb_ether driver searches for an UCLASS_USB_DEV_GENERIC, but the only
way to
get such a device is to init usb. whenever I init the usb OTG port gets
detected as hub.
I looked at the u-boot usb stack code and did not think its possible to
use usb gadget driver
with DM enabled at this time.
Can somebody who is more familiar with the u-boot usb stack confirm this?
Or is it just my fault?
Devicetree entry:
{
disable-over-current;
dr_mode = "peripheral";
status = "okay";
};
Defconfig:
CONFIG_DM_ETH=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DUALSPEED=y
Config Include:
/* USB Configs */
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET/* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS0
/* USB Ethernet Configs */
#define CONFIG_USBD_HS
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_CDC
#define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01"
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:ef:00:02"
Thanks!
Bernhard Messerklinger
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