Re: [PATCH v2 01/21] mmc: sdhci: Add helper functions for UHS modes
Jaehoon,
On 21/10/20 5:08 pm, Jaehoon Chung wrote:
> Hi Faiz,
>
> On 10/16/20 8:08 PM, Faiz Abbas wrote:
>> Add a set_voltage() function which handles the switch from 3.3V to 1.8V
>> for SD card UHS modes.
>>
>> Signed-off-by: Faiz Abbas
>> ---
>> drivers/mmc/sdhci.c | 51 +
>> include/sdhci.h | 1 +
>> 2 files changed, 52 insertions(+)
>>
>> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
>> index 7673219fb3..a69f058191 100644
>> --- a/drivers/mmc/sdhci.c
>> +++ b/drivers/mmc/sdhci.c
>> @@ -20,6 +20,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> static void sdhci_reset(struct sdhci_host *host, u8 mask)
>> {
>> @@ -556,6 +557,56 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
>> sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
>> }
>>
>> +#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
>> +static void sdhci_set_voltage(struct sdhci_host *host)
>> +{
>> +struct mmc *mmc = (struct mmc *)host->mmc;
>> +u32 ctrl;
>> +
>> +ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
>> +
>> +switch (mmc->signal_voltage) {
>> +case MMC_SIGNAL_VOLTAGE_330:
>> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
>> +if (mmc->vqmmc_supply) {
>> +regulator_set_enable(mmc->vqmmc_supply, false);
>> +regulator_set_value(mmc->vqmmc_supply, 330);
>
> Doesn't need to consider about fail to set its value?
You're right. I'll handle the failure case in v3.
>
>> +regulator_set_enable(mmc->vqmmc_supply, true);
>> +}
>> +#endif
>> +mdelay(5);
>
> For what purpose about mdelay(5)?
I'm following this from the kernel implementation here:
https://github.com/torvalds/linux/blob/master/drivers/mmc/host/sdhci.c#L2547
Not sure if this a part of the spec or not though.
>
>
>> +if (IS_SD(mmc)) {
>> +ctrl &= ~SDHCI_CTRL_VDD_180;
>> +sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
>> +}
>> +break;
>> +case MMC_SIGNAL_VOLTAGE_180:
>> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
>> +if (mmc->vqmmc_supply) {
>> +regulator_set_enable(mmc->vqmmc_supply, false);
>> +regulator_set_value(mmc->vqmmc_supply, 180);
>> +regulator_set_enable(mmc->vqmmc_supply, true);
>> +}
>> +#endif
>> +if (IS_SD(mmc)) {
>> +ctrl |= SDHCI_CTRL_VDD_180;
>> +sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
>> +}
>> +break;
>> +default:
>> +/* No signal voltage switch required */
>> +return;
>> +}
>> +}
>> +#else
>> +static void sdhci_set_voltage(struct sdhci_host *host) { }
>> +#endif
>> +void sdhci_set_control_reg(struct sdhci_host *host)
>
> this function is called as callback function in sdhci_set_ios().
> it's strange... set_control_reg callback is for host specific control
> register.
>
> I think that it doesn't need to assign to callback.
This is the default set_control_reg() implementation which is defined
in the sdhci spec. Any host that that wants default implementation
case assign this as their callback.
Hosts that have custom implementations can add in their own drivers.
Thanks,
Faiz
[PATCH v2 19/21] arm: dts: k3-am65-main: Add itapdly and clkbuf-sel values
Add the appropriate itapdly and clkbuf-sel values required for some lower speed modes. Signed-off-by: Faiz Abbas --- arch/arm/dts/k3-am65-main.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index d151e27028..a7b03dc669 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -109,6 +109,11 @@ ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x5>; ti,otap-del-sel-hs400 = <0x0>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-mmc-hs = <0x1>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; + ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; }; @@ -130,6 +135,10 @@ ti,otap-del-sel-ddr50 = <0x4>; ti,otap-del-sel-ddr52 = <0x4>; ti,otap-del-sel-hs200 = <0x7>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-mmc-hs = <0x1>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; -- 2.17.1
[PATCH v2 17/21] configs: j7200_evm: Add support for UHS modes
Add configs to support UHS modes for the SD card and HS200 for the eMMC. Signed-off-by: Faiz Abbas --- configs/j7200_evm_a72_defconfig | 8 configs/j7200_evm_r5_defconfig | 1 + 2 files changed, 9 insertions(+) diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 7c900b1d2e..c932500dc4 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -110,11 +110,16 @@ CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -142,6 +147,9 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_REMOTEPROC_TI_K3_R5F=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 3820fc508b..b20698fd0e 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -89,6 +89,7 @@ CONFIG_K3_SEC_PROXY=y CONFIG_FS_LOADER=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y -- 2.17.1
[PATCH v2 20/21] arm: dts: k3-am654-base-board: Limit Sd card to High speed modes
There's an issue with the base board in which the power cycle circuit takes way longer to power down than expected by mmc core. code. This prevents the card from enumerating in UHS modes. Disable UHS modes for this board until a new board revision fixes the issue. Signed-off-by: Faiz Abbas --- arch/arm/dts/k3-am654-base-board.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index 33a1b9fdc4..830526a1e4 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -144,6 +144,7 @@ pinctrl-names = "default"; pinctrl-0 = <_mmc1_pins_default>; ti,driver-strength-ohm = <50>; + sdhci-caps-mask = <0x7 0x0>; disable-wp; }; -- 2.17.1
[PATCH v2 18/21] i2c: Makefile: Add SPL_DM_I2C_GPIO
Add an SPL flag to DM_I2C_GPIO to prevent it building automatically in SPL. Signed-off-by: Faiz Abbas --- drivers/i2c/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index bd248cbf52..b37198036c 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_DM_I2C) += i2c-uclass.o ifdef CONFIG_ACPIGEN obj-$(CONFIG_DM_I2C) += acpi_i2c.o endif -obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o +obj-$(CONFIG_$(SPL_)DM_I2C_GPIO) += i2c-gpio.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o -- 2.17.1
[PATCH v2 21/21] configs: am65x_evm: Add configs for UHS modes
Add configs for voltage switching and UHS modes for the SD card and HS200 for the eMMC. Signed-off-by: Faiz Abbas --- configs/am65x_evm_a53_defconfig | 8 configs/am65x_evm_r5_defconfig | 2 ++ 2 files changed, 10 insertions(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 8a94ad1530..fd7eaef58b 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -95,12 +95,17 @@ CONFIG_TI_SCI_PROTOCOL=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -132,6 +137,9 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 96c4351196..b9b11010a1 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -85,6 +85,8 @@ CONFIG_K3_SEC_PROXY=y CONFIG_K3_AVS0=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y -- 2.17.1
[PATCH v2 14/21] arm: dts: k3-j7200-main: Add support for gpio0
Add support for the main_gpio0 node
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-j7200-main.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index c25f03cf23..b722204c44 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -197,6 +197,28 @@
clock-names = "fclk";
};
+ main_gpio0: gpio@60 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x0060 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
+<105 1 IRQ_TYPE_EDGE_RISING>,
+<105 2 IRQ_TYPE_EDGE_RISING>,
+<105 3 IRQ_TYPE_EDGE_RISING>,
+<105 4 IRQ_TYPE_EDGE_RISING>,
+<105 5 IRQ_TYPE_EDGE_RISING>,
+<105 6 IRQ_TYPE_EDGE_RISING>,
+<105 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 105 0>;
+ clock-names = "gpio";
+ };
+
main_sdhci0: sdhci@4f8 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x04f8 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
--
2.17.1
[PATCH v2 11/21] arm: dts: k3-am65: Fix mmc nodes
Because of fundamental interface issues in am65x pg1, only the
initial sdhci1 node at 25 MHz was added in the u-boot.dtsi
from which both the base-board.dts and r5-base-board.dts
inherit the node. Move the node out to k3-am65-main.dtsi
where it belongs and add the board specific properties
in base-board.dts and r5-base-board.dts
This ensures dts compatibility with the kernel dts in the
base-board.dts and enables the SD card interface at 50 MHz
and High Speed mode
While we are here, also fix the main_mmc0_pins_default
property to be included and inherit from the base-board.dts
instead of the u-boot.dtsi
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-am65-main.dtsi | 22 +++
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 67 +++-
arch/arm/dts/k3-am654-base-board.dts | 25
arch/arm/dts/k3-am654-r5-base-board.dts | 20 +-
4 files changed, 74 insertions(+), 60 deletions(-)
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 028f57379b..d151e27028 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -113,6 +113,28 @@
dma-coherent;
};
+ sdhci1: sdhci@4fa {
+ compatible = "ti,am654-sdhci-5.1";
+ reg = <0x0 0x4fa 0x0 0x260>, <0x0 0x4fb 0x0 0x134>;
+ power-domains = <_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 48 0>, <_clks 48 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ interrupts = ;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0x0>;
+ ti,otap-del-sel-sdr25 = <0x0>;
+ ti,otap-del-sel-sdr50 = <0x8>;
+ ti,otap-del-sel-sdr104 = <0x7>;
+ ti,otap-del-sel-ddr50 = <0x4>;
+ ti,otap-del-sel-ddr52 = <0x4>;
+ ti,otap-del-sel-hs200 = <0x7>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ };
+
main_i2c0: i2c@200 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x200 0x0 0x100>;
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index d75d1b1c28..88fab99698 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -19,28 +19,6 @@
_main{
u-boot,dm-spl;
-
- sdhci1: sdhci@04FA {
- compatible = "ti,am654-sdhci-5.1";
- reg = <0x0 0x4FA 0x0 0x1000>,
- <0x0 0x4FB 0x0 0x400>;
- clocks =<_clks 48 0>, <_clks 48 1>;
- clock-names = "clk_ahb", "clk_xin";
- power-domains = <_pds 48 TI_SCI_PD_EXCLUSIVE>;
- max-frequency = <2500>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x4>;
- ti,otap-del-sel-ddr52 = <0x4>;
- ti,otap-del-sel-hs200 = <0x7>;
- ti,trm-icp = <0x8>;
- };
-
};
_mcu {
@@ -107,38 +85,6 @@
u-boot,dm-spl;
};
- main_mmc0_pins_default: main_mmc0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /*
(B25) MMC0_CLK */
- AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0)/*
(B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0)/*
(A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0)/*
(E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0)/*
(C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0)/*
(A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0)/*
(E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0)/*
(A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0)/*
(B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0)/*
(D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b4, PIN_IN
[PATCH v2 13/21] arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD card
Add support for regulators to power cycle and switch IO voltage to the
SD card. This enables support for UHS modes.
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-j721e-common-proc-board.dts | 32 +
1 file changed, 32 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts
b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 496a15e1d1..6b29200bba 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "k3-j721e-som-p0.dtsi"
+#include
/ {
chosen {
@@ -24,6 +25,29 @@
remoteproc7 = _1;
remoteproc8 = _0;
};
+
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = < 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: gpio-regulator-TLV71033 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <_sd_dv_alt_pins_default>;
+ regulator-name = "tlv71033";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ gpios = <_gpio0 117 GPIO_ACTIVE_HIGH>;
+ states = <180 0x0
+ 330 0x1>;
+ };
};
_uart0 {
@@ -79,6 +103,12 @@
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>;
};
+
+ vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4)
SPI1_CS1.GPIO0_117 */
+ >;
+ };
};
_sdhci0 {
@@ -92,6 +122,8 @@
pinctrl-names = "default";
pinctrl-0 = <_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
+ vmmc-supply = <_mmc1>;
+ vqmmc-supply = <_sd_dv_alt>;
};
_pmx0 {
--
2.17.1
[PATCH v2 16/21] configs: j721e_evm: Add support for UHS modes
Add configs to support UHS modes for the SD card and HS200 for the eMMC. Signed-off-by: Faiz Abbas --- configs/j721e_evm_a72_defconfig | 8 configs/j721e_evm_r5_defconfig | 1 + 2 files changed, 9 insertions(+) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 6de8666956..3991100832 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -107,11 +107,16 @@ CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -140,6 +145,9 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_REMOTEPROC_TI_K3_DSP=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 4128548100..7b4f0afce6 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -89,6 +89,7 @@ CONFIG_K3_AVS0=y CONFIG_ESM_PMIC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y -- 2.17.1
[PATCH v2 15/21] arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes
Add support for UHS modes by adding the regulators to power cycle
and voltage switch the card. Also add pinmuxes required for each
node
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-j7200-common-proc-board.dts | 49 ++-
arch/arm/dts/k3-j7200-main.dtsi | 1 +
.../arm/dts/k3-j7200-r5-common-proc-board.dts | 15 ++
3 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index cc3d933cbb..20974aff59 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -7,6 +7,7 @@
#include
#include "k3-j7200-som-p0.dtsi"
+#include
/ {
chosen {
@@ -20,6 +21,29 @@
remoteproc2 = _r5fss0_core0;
remoteproc3 = _r5fss0_core1;
};
+
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = < 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv: gpio-regulator-vdd-sd-dv {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_sd_dv";
+ pinctrl-names = "default";
+ pinctrl-0 = <_sd_dv_pins_default>;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ gpios = <_gpio0 55 GPIO_ACTIVE_HIGH>;
+ states = <180 0x0
+ 330 0x1>;
+ };
};
_pmx0 {
@@ -69,6 +93,25 @@
>;
};
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1)
TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
+ vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (T5)
SPI0_D1.GPIO0_55 */
+ >;
+ };
+
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS
*/
@@ -140,10 +183,12 @@
_sdhci1 {
/* SD card */
+ pinctrl-0 = <_mmc1_pins_default>;
+ pinctrl-names = "default";
+ vmmc-supply = <_mmc1>;
+ vqmmc-supply = <_sd_dv>;
ti,driver-strength-ohm = <50>;
disable-wp;
- no-1-8-v;
- sdhci-caps-mask = <0x800F 0x0>;
};
_i2c0 {
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index b722204c44..8150ff6332 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -253,6 +253,7 @@
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,clkbuf-sel = <0x7>;
dma-coherent;
};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index db63d93777..288f4bf565 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -161,6 +161,19 @@
>;
};
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1)
TIMER_IO0.MMC1_SDCD */
+
[PATCH v2 12/21] arm: dts: k3-j721e-main: Update otap-delay values
Update otap delay values to match with the latest Data Manual[1].
[1] https://www.ti.com/lit/gpn/dra829v
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-j721e-main.dtsi | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index 33db74a267..e08e743706 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -235,11 +235,14 @@
ti,trm-icp = <0x8>;
dma-coherent;
mmc-ddr-1_8v;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-legacy = <0xf>;
+ ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
ti,otap-del-sel-hs400 = <0x0>;
+ ti,itap-del-sel-legacy = <0x10>;
+ ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,itap-del-sel-ddr52 = <0x3>;
};
main_sdhci1: sdhci@4fb {
@@ -256,7 +259,6 @@
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,trm-icp = <0x8>;
dma-coherent;
--
2.17.1
[PATCH v2 08/21] mmc: am654_sdhci: Add support for software tuning
With the new SW tuning App note[1], a custom tuning algorithm is
required for eMMC HS200, HS400 and SD card UHS modes. The algorithm
involves running through the 32 possible input tap delay values and
sending the appropriate tuning command (CMD19/21) for each of them
to get a fail or pass result for each of the values. Typically, the
range will have a small contiguous failing window. Considering the
tuning range as a circular buffer, the algorithm then sets a final
tuned value directly opposite to the failing window.
[1] https://www.ti.com/lit/pdf/spract9
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 45 +++
1 file changed, 45 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index fa118fc56c..79b4331c3c 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -368,7 +369,48 @@ static int am654_sdhci_deferred_probe(struct sdhci_host
*host)
return sdhci_probe(dev);
}
+#ifdef MMC_SUPPORTS_TUNING
+#define ITAP_MAX 32
+static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct udevice *dev = mmc->dev;
+ struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
+ u32 itap;
+
+ /* Enable ITAPDLY */
+ regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
+ 1 << ITAPDLYENA_SHIFT);
+
+ for (itap = 0; itap < ITAP_MAX; itap++) {
+ am654_sdhci_write_itapdly(plat, itap);
+
+ cur_val = !mmc_send_tuning(mmc, opcode, NULL);
+ if (cur_val && !prev_val)
+ pass_window = itap;
+
+ if (!cur_val)
+ fail_len++;
+
+ prev_val = cur_val;
+ }
+ /*
+* Having determined the length of the failing window and start of
+* the passing window calculate the length of the passing window and
+* set the final value halfway through it considering the range as a
+* circular buffer
+*/
+ pass_len = ITAP_MAX - fail_len;
+ itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
+ am654_sdhci_write_itapdly(plat, itap);
+
+ return 0;
+}
+#endif
const struct sdhci_ops am654_sdhci_ops = {
+#ifdef MMC_SUPPORTS_TUNING
+ .platform_execute_tuning = am654_sdhci_execute_tuning,
+#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _sdhci_set_ios_post,
.set_control_reg= _sdhci_set_control_reg,
@@ -408,6 +450,9 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host
*host)
}
const struct sdhci_ops j721e_4bit_sdhci_ops = {
+#ifdef MMC_SUPPORTS_TUNING
+ .platform_execute_tuning = am654_sdhci_execute_tuning,
+#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _4bit_sdhci_set_ios_post,
};
--
2.17.1
[PATCH v2 09/21] mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes
According to the AM654x Data Manual[1], the setup timing in lower speed
modes can only be met if the controller uses a falling edge data launch.
To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be
cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25
speed modes.
Use the sdhci writeb callback to implement this condition.
[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1
Signed-off-by: Faiz Abbas
---
drivers/mmc/Kconfig | 1 +
drivers/mmc/am654_sdhci.c | 25 +++--
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 0c252e34c7..525445949d 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -521,6 +521,7 @@ config MMC_SDHCI_AM654
depends on MMC_SDHCI
depends on DM_MMC && OF_CONTROL && BLK
depends on REGMAP
+ select MMC_SDHCI_IO_ACCESSORS
help
Support for Secure Digital Host Controller Interface (SDHCI)
controllers present on TI's AM654 SOCs.
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 79b4331c3c..410517398a 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -369,6 +369,26 @@ static int am654_sdhci_deferred_probe(struct sdhci_host
*host)
return sdhci_probe(dev);
}
+static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
+{
+ if (reg == SDHCI_HOST_CONTROL) {
+ switch (host->mmc->selected_mode) {
+ /*
+* According to the data manual, HISPD bit
+* should not be set in these speed modes.
+*/
+ case SD_HS:
+ case MMC_HS:
+ case UHS_SDR12:
+ case UHS_SDR25:
+ val &= ~SDHCI_CTRL_HISPD;
+ default:
+ break;
+ }
+ }
+
+ writeb(val, host->ioaddr + reg);
+}
#ifdef MMC_SUPPORTS_TUNING
#define ITAP_MAX 32
static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
@@ -414,6 +434,7 @@ const struct sdhci_ops am654_sdhci_ops = {
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _sdhci_set_ios_post,
.set_control_reg= _sdhci_set_control_reg,
+ .write_b= am654_sdhci_write_b,
};
const struct am654_driver_data am654_drv_data = {
@@ -455,6 +476,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = {
#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _4bit_sdhci_set_ios_post,
+ .write_b= am654_sdhci_write_b,
};
const struct am654_driver_data j721e_4bit_drv_data = {
@@ -532,6 +554,7 @@ static int am654_sdhci_probe(struct udevice *dev)
host->max_clk = clock;
host->mmc = >mmc;
host->mmc->dev = dev;
+ host->ops = drv_data->ops;
ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
AM654_SDHCI_MIN_FREQ);
if (ret)
@@ -541,8 +564,6 @@ static int am654_sdhci_probe(struct udevice *dev)
if (ret)
return ret;
- host->ops = drv_data->ops;
-
/* Update ops based on SoC revision */
soc = soc_device_match(am654_sdhci_soc_attr);
if (soc && soc->data) {
--
2.17.1
[PATCH v2 07/21] mmc: am654_sdhci: Add support for writing to clkbuf_sel
Add support for writing new clock buffer select property for both
the am654x and j721e 4 bit IPs
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index f472672152..fa118fc56c 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -48,6 +48,8 @@
#define SEL100_MASKBIT(SEL100_SHIFT)
#define FREQSEL_SHIFT 8
#define FREQSEL_MASK GENMASK(10, 8)
+#define CLKBUFSEL_SHIFT0
+#define CLKBUFSEL_MASK GENMASK(2, 0)
#define DLL_TRIM_ICP_SHIFT 4
#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
#define DR_TY_SHIFT20
@@ -92,6 +94,7 @@ struct am654_sdhci_plat {
u32 trm_icp;
u32 drv_strength;
u32 strb_sel;
+ u32 clkbuf_sel;
u32 flags;
#define DLL_PRESENTBIT(0)
#define IOMUX_PRESENT BIT(1)
@@ -295,6 +298,9 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
am654_sdhci_setup_delay_chain(plat, mode);
}
+ regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
+ plat->clkbuf_sel);
+
return 0;
}
@@ -395,6 +401,9 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host
*host)
val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
+ regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
+ plat->clkbuf_sel);
+
return 0;
}
@@ -548,6 +557,8 @@ static int am654_sdhci_ofdata_to_platdata(struct udevice
*dev)
}
}
+ dev_read_u32(dev, "ti,clkbuf-sel", >clkbuf_sel);
+
ret = mmc_of_parse(dev, cfg);
if (ret)
return ret;
--
2.17.1
[PATCH v2 10/21] mmc: am654_sdhci: Use sdhci_set_control_reg()
Use the generic sdhci_set_control_reg() instead of duplicating
in platform driver.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 410517398a..92aac8c0e7 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -151,21 +151,6 @@ struct am654_driver_data {
u32 flags;
};
-static void am654_sdhci_set_control_reg(struct sdhci_host *host)
-{
- struct mmc *mmc = (struct mmc *)host->mmc;
- u32 reg;
-
- if (IS_SD(host->mmc) &&
- mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
- reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- reg |= SDHCI_CTRL_VDD_180;
- sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
- }
-
- sdhci_set_uhs_timing(host);
-}
-
static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,
unsigned int speed)
{
@@ -433,7 +418,7 @@ const struct sdhci_ops am654_sdhci_ops = {
#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _sdhci_set_ios_post,
- .set_control_reg= _sdhci_set_control_reg,
+ .set_control_reg= sdhci_set_control_reg,
.write_b= am654_sdhci_write_b,
};
@@ -476,6 +461,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = {
#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _4bit_sdhci_set_ios_post,
+ .set_control_reg= sdhci_set_control_reg,
.write_b= am654_sdhci_write_b,
};
--
2.17.1
[PATCH v2 03/21] mmc: am654_sdhci: Convert flag fields to BIT macro
Convert the flags field defines to use the BIT() macro.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 15a47f1e71..10350d8d61 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -80,10 +80,10 @@ struct am654_sdhci_plat {
u32 drv_strength;
u32 strb_sel;
u32 flags;
-#define DLL_PRESENT(1 << 0)
-#define IOMUX_PRESENT (1 << 1)
-#define FREQSEL_2_BIT (1 << 2)
-#define STRBSEL_4_BIT (1 << 3)
+#define DLL_PRESENTBIT(0)
+#define IOMUX_PRESENT BIT(1)
+#define FREQSEL_2_BIT BIT(2)
+#define STRBSEL_4_BIT BIT(3)
};
struct timing_data {
--
2.17.1
[PATCH v2 05/21] mmc: am654_sdhci: Add support for AM65x SR2.0
Add Support for AM65x PG2.0. Use the SoC bus framework to fixup
the platform data and do DLL calibration if the revision is 1.0
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 145373ad46..71798be765 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -292,6 +293,11 @@ const struct sdhci_ops am654_sdhci_ops = {
};
const struct am654_driver_data am654_drv_data = {
+ .ops = _sdhci_ops,
+ .flags = DLL_PRESENT | IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT,
+};
+
+const struct am654_driver_data am654_sr1_drv_data = {
.ops = _sdhci_ops,
.flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB |
STRBSEL_4_BIT,
@@ -326,6 +332,11 @@ const struct am654_driver_data j721e_4bit_drv_data = {
.flags = IOMUX_PRESENT,
};
+const struct soc_attr am654_sdhci_soc_attr[] = {
+ { .family = "AM65X", .revision = "SR1.0", .data = _sr1_drv_data},
+ {/* sentinel */}
+};
+
static int sdhci_am654_get_otap_delay(struct udevice *dev,
struct mmc_config *cfg)
{
@@ -365,6 +376,8 @@ static int am654_sdhci_probe(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct mmc_config *cfg = >cfg;
+ const struct soc_attr *soc;
+ const struct am654_driver_data *soc_drv_data;
struct clk clk;
unsigned long clock;
int ret;
@@ -394,6 +407,14 @@ static int am654_sdhci_probe(struct udevice *dev)
return ret;
host->ops = drv_data->ops;
+
+ /* Update ops based on SoC revision */
+ soc = soc_device_match(am654_sdhci_soc_attr);
+ if (soc && soc->data) {
+ soc_drv_data = soc->data;
+ host->ops = soc_drv_data->ops;
+ }
+
host->mmc->priv = host;
upriv->mmc = host->mmc;
@@ -458,9 +479,18 @@ static int am654_sdhci_bind(struct udevice *dev)
struct am654_driver_data *drv_data =
(struct am654_driver_data *)dev_get_driver_data(dev);
struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ const struct soc_attr *soc;
+ const struct am654_driver_data *soc_drv_data;
plat->flags = drv_data->flags;
+ /* Update flags based on SoC revision */
+ soc = soc_device_match(am654_sdhci_soc_attr);
+ if (soc && soc->data) {
+ soc_drv_data = soc->data;
+ plat->flags = soc_drv_data->flags;
+ }
+
return sdhci_bind(dev, >mmc, >cfg);
}
--
2.17.1
[PATCH v2 01/21] mmc: sdhci: Add helper functions for UHS modes
Add a set_voltage() function which handles the switch from 3.3V to 1.8V
for SD card UHS modes.
Signed-off-by: Faiz Abbas
---
drivers/mmc/sdhci.c | 51 +
include/sdhci.h | 1 +
2 files changed, 52 insertions(+)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 7673219fb3..a69f058191 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
@@ -556,6 +557,56 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
}
+#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
+static void sdhci_set_voltage(struct sdhci_host *host)
+{
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u32 ctrl;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ switch (mmc->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vqmmc_supply) {
+ regulator_set_enable(mmc->vqmmc_supply, false);
+ regulator_set_value(mmc->vqmmc_supply, 330);
+ regulator_set_enable(mmc->vqmmc_supply, true);
+ }
+#endif
+ mdelay(5);
+ if (IS_SD(mmc)) {
+ ctrl &= ~SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
+ break;
+ case MMC_SIGNAL_VOLTAGE_180:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vqmmc_supply) {
+ regulator_set_enable(mmc->vqmmc_supply, false);
+ regulator_set_value(mmc->vqmmc_supply, 180);
+ regulator_set_enable(mmc->vqmmc_supply, true);
+ }
+#endif
+ if (IS_SD(mmc)) {
+ ctrl |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
+ break;
+ default:
+ /* No signal voltage switch required */
+ return;
+ }
+}
+#else
+static void sdhci_set_voltage(struct sdhci_host *host) { }
+#endif
+void sdhci_set_control_reg(struct sdhci_host *host)
+{
+ sdhci_set_voltage(host);
+ sdhci_set_uhs_timing(host);
+}
+
#ifdef CONFIG_DM_MMC
static int sdhci_set_ios(struct udevice *dev)
{
diff --git a/include/sdhci.h b/include/sdhci.h
index 94fc3ed56a..d3f8741042 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -492,6 +492,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host);
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
+void sdhci_set_control_reg(struct sdhci_host *host);
extern const struct dm_mmc_ops sdhci_ops;
#else
#endif
--
2.17.1
[PATCH v2 06/21] mmc: am654_sdhci: Add support for input tap delay
DLL need only be enabled for speed modes and clock frequencies at or
above 50 MHz. For speed modes that don't enable the DLL, we need to
configure a static input delay value. This involves reading an optional
itap-del-sel-* value from the device tree and configuring it for the
appropriate speed mode.
Therefore, move all dll configurations to their own functions and gate it
with 50 MHz speed and a minimum mode. If both these conditions are not
satisfied then configure delay chain modes.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 241 +-
1 file changed, 161 insertions(+), 80 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 71798be765..f472672152 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -62,6 +62,16 @@
#define CALDONE_MASK BIT(CALDONE_SHIFT)
#define RETRIM_SHIFT 17
#define RETRIM_MASKBIT(RETRIM_SHIFT)
+#define SELDLYTXCLK_SHIFT 17
+#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
+#define SELDLYRXCLK_SHIFT 16
+#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
+#define ITAPDLYSEL_SHIFT 0
+#define ITAPDLYSEL_MASKGENMASK(4, 0)
+#define ITAPDLYENA_SHIFT 8
+#define ITAPDLYENA_MASKBIT(ITAPDLYENA_SHIFT)
+#define ITAPCHGWIN_SHIFT 9
+#define ITAPCHGWIN_MASKBIT(ITAPCHGWIN_SHIFT)
#define DRIVER_STRENGTH_50_OHM 0x0
#define DRIVER_STRENGTH_33_OHM 0x1
@@ -70,6 +80,7 @@
#define DRIVER_STRENGTH_40_OHM 0x4
#define AM654_SDHCI_MIN_FREQ 40
+#define CLOCK_TOO_SLOW_HZ 5000
struct am654_sdhci_plat {
struct mmc_config cfg;
@@ -77,6 +88,7 @@ struct am654_sdhci_plat {
struct regmap *base;
bool non_removable;
u32 otap_del_sel[MMC_MODES_END];
+ u32 itap_del_sel[MMC_MODES_END];
u32 trm_icp;
u32 drv_strength;
u32 strb_sel;
@@ -89,22 +101,45 @@ struct am654_sdhci_plat {
};
struct timing_data {
- const char *binding;
+ const char *otap_binding;
+ const char *itap_binding;
u32 capability;
};
static const struct timing_data td[] = {
- [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
- [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
- [SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
- [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
- [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
- [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
- [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
- [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
- [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
- [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
- [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
+ [MMC_LEGACY]= {"ti,otap-del-sel-legacy",
+ "ti,itap-del-sel-legacy",
+ 0},
+ [MMC_HS]= {"ti,otap-del-sel-mmc-hs",
+ "ti,itap-del-sel-mms-hs",
+ MMC_CAP(MMC_HS)},
+ [SD_HS] = {"ti,otap-del-sel-sd-hs",
+ "ti,itap-del-sel-sd-hs",
+ MMC_CAP(SD_HS)},
+ [UHS_SDR12] = {"ti,otap-del-sel-sdr12",
+ "ti,itap-del-sel-sdr12",
+ MMC_CAP(UHS_SDR12)},
+ [UHS_SDR25] = {"ti,otap-del-sel-sdr25",
+ "ti,itap-del-sel-sdr25",
+ MMC_CAP(UHS_SDR25)},
+ [UHS_SDR50] = {"ti,otap-del-sel-sdr50",
+ NULL,
+ MMC_CAP(UHS_SDR50)},
+ [UHS_SDR104]= {"ti,otap-del-sel-sdr104",
+ NULL,
+ MMC_CAP(UHS_SDR104)},
+ [UHS_DDR50] = {"ti,otap-del-sel-ddr50",
+ NULL,
+ MMC_CAP(UHS_DDR50)},
+ [MMC_DDR_52]= {"ti,otap-del-sel-ddr52",
+ "ti,itap-del-sel-ddr52",
+ MMC_CAP(MMC_DDR_52)},
+ [MMC_HS_200]= {"ti,otap-del-sel-hs200",
+ NULL,
+ MMC_CAP(MMC_HS_200)},
+ [MMC_HS_400]= {"ti,otap-del-sel-hs400",
+ NULL,
+ MMC_CAP(MMC_HS_400)},
};
struct am654_driver_data {
@@ -127,12 +162,99 @@ static void am654_sdhci_set_control_reg(struct sdhci_host
*host)
sdhci_set_uhs_timing(host);
}
+static int am654_sdhci_setup_dll(struct am654_sdhc
[PATCH v2 04/21] mmc: am654_sdhci: Add flag for PHY calibration
Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB
flag to indicate the same.
Also move the write of trm_icp and driver strength to the set_clock()
function to match the kernel configuration flow.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 10350d8d61..145373ad46 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -84,6 +84,7 @@ struct am654_sdhci_plat {
#define IOMUX_PRESENT BIT(1)
#define FREQSEL_2_BIT BIT(2)
#define STRBSEL_4_BIT BIT(3)
+#define DLL_CALIB BIT(4)
};
struct timing_data {
@@ -195,6 +196,15 @@ static int am654_sdhci_set_ios_post(struct sdhci_host
*host)
freqsel << FREQSEL_SHIFT);
}
+ /* Configure DLL TRIM */
+ mask = DLL_TRIM_ICP_MASK;
+ val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
+
+ /* Configure DLL driver strength */
+ mask |= DR_TY_MASK;
+ val |= plat->drv_strength << DR_TY_SHIFT;
+ regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
+
/* Enable DLL */
regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
0x1 << ENDLL_SHIFT);
@@ -221,7 +231,7 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat)
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
- if (plat->flags & DLL_PRESENT) {
+ if (plat->flags & DLL_CALIB) {
regmap_read(plat->base, PHY_STAT1, );
if (~val & CALDONE_MASK) {
/* Calibrate IO lines */
@@ -233,15 +243,6 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat)
if (ret)
return ret;
}
-
- /* Configure DLL TRIM */
- mask = DLL_TRIM_ICP_MASK;
- val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
-
- /* Configure DLL driver strength */
- mask |= DR_TY_MASK;
- val |= plat->drv_strength << DR_TY_SHIFT;
- regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
}
/* Enable pins by setting IO mux to 0 */
@@ -292,12 +293,13 @@ const struct sdhci_ops am654_sdhci_ops = {
const struct am654_driver_data am654_drv_data = {
.ops = _sdhci_ops,
- .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
+ .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB |
+STRBSEL_4_BIT,
};
const struct am654_driver_data j721e_8bit_drv_data = {
.ops = _sdhci_ops,
- .flags = DLL_PRESENT,
+ .flags = DLL_PRESENT | DLL_CALIB,
};
static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
--
2.17.1
[PATCH v2 00/21] Add support for MMC higher speed modes for TI's am65x, j721e and j7200 platforms
The following patches add support for higher speeds in the SD card and eMMC for TI's am65x, j721e, j7200 platforms. With these patches, the following max speeds are supported: j721e: DDR50, HS200 j7200: SDR104, HS200 am65x: SDR104*, HS200 v2: 1. Added patches to support UHS modes for the SD card even in am654x platforms. 2. Fixed an issue with patch 1 that was breaking builds on some platforms. * There's an issue with the am65x base board such that the power cycle circuit to the card takes way longer than the wait time in mmc core. Until this is fixed, am654x-evm and -idk will only support High speed mode at 3.3V (see patch 20) but this shouldn't block us from adding UHS modes in the dtsi as well as in the configs so other boards can still take advantage of the higher speed. UHS modes have been tested by adding the appropriate delay in the power cycle circuit. Link to v1: https://patchwork.ozlabs.org/project/uboot/list/?series=206622 Faiz Abbas (21): mmc: sdhci: Add helper functions for UHS modes mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post() mmc: am654_sdhci: Convert flag fields to BIT macro mmc: am654_sdhci: Add flag for PHY calibration mmc: am654_sdhci: Add support for AM65x SR2.0 mmc: am654_sdhci: Add support for input tap delay mmc: am654_sdhci: Add support for writing to clkbuf_sel mmc: am654_sdhci: Add support for software tuning mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes mmc: am654_sdhci: Use sdhci_set_control_reg() arm: dts: k3-am65: Fix mmc nodes arm: dts: k3-j721e-main: Update otap-delay values arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD card arm: dts: k3-j7200-main: Add support for gpio0 arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes configs: j721e_evm: Add support for UHS modes configs: j7200_evm: Add support for UHS modes i2c: Makefile: Add SPL_DM_I2C_GPIO arm: dts: k3-am65-main: Add itapdly and clkbuf-sel values arm: dts: k3-am654-base-board: Limit Sd card to High speed modes configs: am65x_evm: Add configs for UHS modes arch/arm/dts/k3-am65-main.dtsi| 31 ++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 67 +-- arch/arm/dts/k3-am654-base-board.dts | 26 ++ arch/arm/dts/k3-am654-r5-base-board.dts | 20 +- arch/arm/dts/k3-j7200-common-proc-board.dts | 49 ++- arch/arm/dts/k3-j7200-main.dtsi | 23 ++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 15 + arch/arm/dts/k3-j721e-common-proc-board.dts | 32 ++ arch/arm/dts/k3-j721e-main.dtsi | 8 +- configs/am65x_evm_a53_defconfig | 8 + configs/am65x_evm_r5_defconfig| 2 + configs/j7200_evm_a72_defconfig | 8 + configs/j7200_evm_r5_defconfig| 1 + configs/j721e_evm_a72_defconfig | 8 + configs/j721e_evm_r5_defconfig| 1 + drivers/i2c/Makefile | 2 +- drivers/mmc/Kconfig | 1 + drivers/mmc/am654_sdhci.c | 384 +- drivers/mmc/sdhci.c | 51 +++ include/sdhci.h | 1 + 20 files changed, 564 insertions(+), 174 deletions(-) -- 2.17.1
[PATCH v2 02/21] mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post()
There are some speed modes that work without switching the dll on.
Unconditionally switch off the DLL before setting clock frequency to
support this case. The software will automatically enable DLL for speed
modes that require it. This also means the dll_on priv data member is no
longer required.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 82abf484e4..15a47f1e71 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -84,7 +84,6 @@ struct am654_sdhci_plat {
#define IOMUX_PRESENT (1 << 1)
#define FREQSEL_2_BIT (1 << 2)
#define STRBSEL_4_BIT (1 << 3)
- bool dll_on;
};
struct timing_data {
@@ -141,12 +140,7 @@ static int am654_sdhci_set_ios_post(struct sdhci_host
*host)
val &= ~SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
- /* power off phy */
- if (plat->dll_on) {
- regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
-
- plat->dll_on = false;
- }
+ regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
/* restart clock */
sdhci_set_clock(host->mmc, speed);
@@ -212,8 +206,6 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
val & DLLRDY_MASK, 1000, 100);
if (ret)
return ret;
-
- plat->dll_on = true;
}
return 0;
--
2.17.1
Re: [PATCH 01/17] mmc: sdhci: Add helper functions for UHS modes
Hi, On 08/10/20 10:42 am, Faiz Abbas wrote: > Add a set_voltage() function which handles the switch from 3.3V to 1.8V > for SD card UHS modes. > > Signed-off-by: Faiz Abbas > --- Travisci is showing build issues for this patch with some boards. Will fix and repost for v2. Thanks, Faiz
[PATCH 16/17] configs: j721e_evm: Add support for UHS modes
Add configs to support UHS modes for the SD card and HS200 for the eMMC. Signed-off-by: Faiz Abbas --- configs/j721e_evm_a72_defconfig | 8 configs/j721e_evm_r5_defconfig | 1 + 2 files changed, 9 insertions(+) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 6de8666956..3991100832 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -107,11 +107,16 @@ CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -140,6 +145,9 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_REMOTEPROC_TI_K3_DSP=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 4128548100..7b4f0afce6 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -89,6 +89,7 @@ CONFIG_K3_AVS0=y CONFIG_ESM_PMIC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y -- 2.17.1
[PATCH 17/17] configs: j7200_evm: Add support for UHS modes
Add configs to support UHS modes for the SD card and HS200 for the eMMC. Signed-off-by: Faiz Abbas --- configs/j7200_evm_a72_defconfig | 8 configs/j7200_evm_r5_defconfig | 1 + 2 files changed, 9 insertions(+) diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 7c900b1d2e..c932500dc4 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -110,11 +110,16 @@ CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -142,6 +147,9 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_REMOTEPROC_TI_K3_R5F=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 3820fc508b..b20698fd0e 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -89,6 +89,7 @@ CONFIG_K3_SEC_PROXY=y CONFIG_FS_LOADER=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y -- 2.17.1
[PATCH 15/17] arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes
Add support for UHS modes by adding the regulators to power cycle
and voltage switch the card. Also add pinmuxes required for each
node.
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-j7200-common-proc-board.dts | 49 ++-
.../arm/dts/k3-j7200-r5-common-proc-board.dts | 15 ++
2 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index cc3d933cbb..20974aff59 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -7,6 +7,7 @@
#include
#include "k3-j7200-som-p0.dtsi"
+#include
/ {
chosen {
@@ -20,6 +21,29 @@
remoteproc2 = _r5fss0_core0;
remoteproc3 = _r5fss0_core1;
};
+
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = < 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv: gpio-regulator-vdd-sd-dv {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_sd_dv";
+ pinctrl-names = "default";
+ pinctrl-0 = <_sd_dv_pins_default>;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ gpios = <_gpio0 55 GPIO_ACTIVE_HIGH>;
+ states = <180 0x0
+ 330 0x1>;
+ };
};
_pmx0 {
@@ -69,6 +93,25 @@
>;
};
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1)
TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
+ vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (T5)
SPI0_D1.GPIO0_55 */
+ >;
+ };
+
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS
*/
@@ -140,10 +183,12 @@
_sdhci1 {
/* SD card */
+ pinctrl-0 = <_mmc1_pins_default>;
+ pinctrl-names = "default";
+ vmmc-supply = <_mmc1>;
+ vqmmc-supply = <_sd_dv>;
ti,driver-strength-ohm = <50>;
disable-wp;
- no-1-8-v;
- sdhci-caps-mask = <0x800F 0x0>;
};
_i2c0 {
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index db63d93777..288f4bf565 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -161,6 +161,19 @@
>;
};
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1)
TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS
*/
@@ -197,6 +210,8 @@
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
+ pinctrl-0 = <_mmc1_pins_default>;
+ pinctrl-names = "default";
clock-names = "clk_xin";
clocks = <_200mhz>;
ti,driver-strength-ohm = <50>;
--
2.17.1
[PATCH 12/17] arm: dts: k3-j721e-main: Update otap-delay values
Update otap delay values to match with the latest Data Manual[1]. [1] https://www.ti.com/lit/gpn/dra829v Signed-off-by: Faiz Abbas --- arch/arm/dts/k3-j721e-main.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 33db74a267..bd979840dc 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -235,8 +235,8 @@ ti,trm-icp = <0x8>; dma-coherent; mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-legacy = <0xf>; + ti,otap-del-sel-mmc-hs = <0xf>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; ti,otap-del-sel-hs400 = <0x0>; @@ -256,7 +256,6 @@ ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; ti,otap-del-sel-ddr50 = <0xc>; ti,trm-icp = <0x8>; dma-coherent; -- 2.17.1
[PATCH 13/17] arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD card
Add support for regulators to power cycle and switch IO voltage to the
SD card. This enables support for UHS modes.
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-j721e-common-proc-board.dts | 32 +
1 file changed, 32 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts
b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 496a15e1d1..6b29200bba 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "k3-j721e-som-p0.dtsi"
+#include
/ {
chosen {
@@ -24,6 +25,29 @@
remoteproc7 = _1;
remoteproc8 = _0;
};
+
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = < 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: gpio-regulator-TLV71033 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <_sd_dv_alt_pins_default>;
+ regulator-name = "tlv71033";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ gpios = <_gpio0 117 GPIO_ACTIVE_HIGH>;
+ states = <180 0x0
+ 330 0x1>;
+ };
};
_uart0 {
@@ -79,6 +103,12 @@
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>;
};
+
+ vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4)
SPI1_CS1.GPIO0_117 */
+ >;
+ };
};
_sdhci0 {
@@ -92,6 +122,8 @@
pinctrl-names = "default";
pinctrl-0 = <_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
+ vmmc-supply = <_mmc1>;
+ vqmmc-supply = <_sd_dv_alt>;
};
_pmx0 {
--
2.17.1
[PATCH 14/17] arm: dts: k3-j7200-main: Add support for gpio0
Add support for the main_gpio0 node
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-j7200-main.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index c25f03cf23..b722204c44 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -197,6 +197,28 @@
clock-names = "fclk";
};
+ main_gpio0: gpio@60 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x0060 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
+<105 1 IRQ_TYPE_EDGE_RISING>,
+<105 2 IRQ_TYPE_EDGE_RISING>,
+<105 3 IRQ_TYPE_EDGE_RISING>,
+<105 4 IRQ_TYPE_EDGE_RISING>,
+<105 5 IRQ_TYPE_EDGE_RISING>,
+<105 6 IRQ_TYPE_EDGE_RISING>,
+<105 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 105 0>;
+ clock-names = "gpio";
+ };
+
main_sdhci0: sdhci@4f8 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x04f8 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
--
2.17.1
[PATCH 11/17] arm: dts: k3-am65: Fix mmc nodes
Because of fundamental interface issues in am65x pg1, only the
initial sdhci1 node at 25 MHz was added in the u-boot.dtsi
from which both the base-board.dts and r5-base-board.dts
inherit the node. Move the node out to k3-am65-main.dtsi
where it belongs and add the board specific properties
in base-board.dts and r5-base-board.dts
This ensures dts compatibility with the kernel dts in the
base-board.dts and enables the SD card interface at 50 MHz
and High Speed mode
While we are here, also fix the main_mmc0_pins_default
property to be included and inherit from the base-board.dts
instead of the u-boot.dtsi
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-am65-main.dtsi | 22 +++
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 67 +++-
arch/arm/dts/k3-am654-base-board.dts | 25
arch/arm/dts/k3-am654-r5-base-board.dts | 20 +-
4 files changed, 74 insertions(+), 60 deletions(-)
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 028f57379b..d151e27028 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -113,6 +113,28 @@
dma-coherent;
};
+ sdhci1: sdhci@4fa {
+ compatible = "ti,am654-sdhci-5.1";
+ reg = <0x0 0x4fa 0x0 0x260>, <0x0 0x4fb 0x0 0x134>;
+ power-domains = <_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 48 0>, <_clks 48 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ interrupts = ;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0x0>;
+ ti,otap-del-sel-sdr25 = <0x0>;
+ ti,otap-del-sel-sdr50 = <0x8>;
+ ti,otap-del-sel-sdr104 = <0x7>;
+ ti,otap-del-sel-ddr50 = <0x4>;
+ ti,otap-del-sel-ddr52 = <0x4>;
+ ti,otap-del-sel-hs200 = <0x7>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ };
+
main_i2c0: i2c@200 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x200 0x0 0x100>;
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index d75d1b1c28..88fab99698 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -19,28 +19,6 @@
_main{
u-boot,dm-spl;
-
- sdhci1: sdhci@04FA {
- compatible = "ti,am654-sdhci-5.1";
- reg = <0x0 0x4FA 0x0 0x1000>,
- <0x0 0x4FB 0x0 0x400>;
- clocks =<_clks 48 0>, <_clks 48 1>;
- clock-names = "clk_ahb", "clk_xin";
- power-domains = <_pds 48 TI_SCI_PD_EXCLUSIVE>;
- max-frequency = <2500>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x4>;
- ti,otap-del-sel-ddr52 = <0x4>;
- ti,otap-del-sel-hs200 = <0x7>;
- ti,trm-icp = <0x8>;
- };
-
};
_mcu {
@@ -107,38 +85,6 @@
u-boot,dm-spl;
};
- main_mmc0_pins_default: main_mmc0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /*
(B25) MMC0_CLK */
- AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0)/*
(B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0)/*
(A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0)/*
(E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0)/*
(C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0)/*
(A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0)/*
(E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0)/*
(A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0)/*
(B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0)/*
(D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b4, PIN_IN
[PATCH 10/17] mmc: am654_sdhci: Use sdhci_set_control_reg()
Use the generic sdhci_set_control_reg() instead of duplicating
in platform driver.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 410517398a..92aac8c0e7 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -151,21 +151,6 @@ struct am654_driver_data {
u32 flags;
};
-static void am654_sdhci_set_control_reg(struct sdhci_host *host)
-{
- struct mmc *mmc = (struct mmc *)host->mmc;
- u32 reg;
-
- if (IS_SD(host->mmc) &&
- mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
- reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- reg |= SDHCI_CTRL_VDD_180;
- sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
- }
-
- sdhci_set_uhs_timing(host);
-}
-
static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,
unsigned int speed)
{
@@ -433,7 +418,7 @@ const struct sdhci_ops am654_sdhci_ops = {
#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _sdhci_set_ios_post,
- .set_control_reg= _sdhci_set_control_reg,
+ .set_control_reg= sdhci_set_control_reg,
.write_b= am654_sdhci_write_b,
};
@@ -476,6 +461,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = {
#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _4bit_sdhci_set_ios_post,
+ .set_control_reg= sdhci_set_control_reg,
.write_b= am654_sdhci_write_b,
};
--
2.17.1
[PATCH 08/17] mmc: am654_sdhci: Add support for software tuning
With the new SW tuning App note[1], a custom tuning algorithm is
required for eMMC HS200, HS400 and SD card UHS modes. The algorithm
involves running through the 32 possible input tap delay values and
sending the appropriate tuning command (CMD19/21) for each of them
to get a fail or pass result for each of the values. Typically, the
range will have a small contiguous failing window. Considering the
tuning range as a circular buffer, the algorithm then sets a final
tuned value directly opposite to the failing window.
[1] https://www.ti.com/lit/pdf/spract9
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 45 +++
1 file changed, 45 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index fa118fc56c..79b4331c3c 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -368,7 +369,48 @@ static int am654_sdhci_deferred_probe(struct sdhci_host
*host)
return sdhci_probe(dev);
}
+#ifdef MMC_SUPPORTS_TUNING
+#define ITAP_MAX 32
+static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct udevice *dev = mmc->dev;
+ struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
+ u32 itap;
+
+ /* Enable ITAPDLY */
+ regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
+ 1 << ITAPDLYENA_SHIFT);
+
+ for (itap = 0; itap < ITAP_MAX; itap++) {
+ am654_sdhci_write_itapdly(plat, itap);
+
+ cur_val = !mmc_send_tuning(mmc, opcode, NULL);
+ if (cur_val && !prev_val)
+ pass_window = itap;
+
+ if (!cur_val)
+ fail_len++;
+
+ prev_val = cur_val;
+ }
+ /*
+* Having determined the length of the failing window and start of
+* the passing window calculate the length of the passing window and
+* set the final value halfway through it considering the range as a
+* circular buffer
+*/
+ pass_len = ITAP_MAX - fail_len;
+ itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
+ am654_sdhci_write_itapdly(plat, itap);
+
+ return 0;
+}
+#endif
const struct sdhci_ops am654_sdhci_ops = {
+#ifdef MMC_SUPPORTS_TUNING
+ .platform_execute_tuning = am654_sdhci_execute_tuning,
+#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _sdhci_set_ios_post,
.set_control_reg= _sdhci_set_control_reg,
@@ -408,6 +450,9 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host
*host)
}
const struct sdhci_ops j721e_4bit_sdhci_ops = {
+#ifdef MMC_SUPPORTS_TUNING
+ .platform_execute_tuning = am654_sdhci_execute_tuning,
+#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _4bit_sdhci_set_ios_post,
};
--
2.17.1
[PATCH 07/17] mmc: am654_sdhci: Add support for writing to clkbuf_sel
Add support for writing new clock buffer select property for both
the am654x and j721e 4 bit IPs
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index f472672152..fa118fc56c 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -48,6 +48,8 @@
#define SEL100_MASKBIT(SEL100_SHIFT)
#define FREQSEL_SHIFT 8
#define FREQSEL_MASK GENMASK(10, 8)
+#define CLKBUFSEL_SHIFT0
+#define CLKBUFSEL_MASK GENMASK(2, 0)
#define DLL_TRIM_ICP_SHIFT 4
#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
#define DR_TY_SHIFT20
@@ -92,6 +94,7 @@ struct am654_sdhci_plat {
u32 trm_icp;
u32 drv_strength;
u32 strb_sel;
+ u32 clkbuf_sel;
u32 flags;
#define DLL_PRESENTBIT(0)
#define IOMUX_PRESENT BIT(1)
@@ -295,6 +298,9 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
am654_sdhci_setup_delay_chain(plat, mode);
}
+ regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
+ plat->clkbuf_sel);
+
return 0;
}
@@ -395,6 +401,9 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host
*host)
val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
+ regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
+ plat->clkbuf_sel);
+
return 0;
}
@@ -548,6 +557,8 @@ static int am654_sdhci_ofdata_to_platdata(struct udevice
*dev)
}
}
+ dev_read_u32(dev, "ti,clkbuf-sel", >clkbuf_sel);
+
ret = mmc_of_parse(dev, cfg);
if (ret)
return ret;
--
2.17.1
[PATCH 09/17] mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes
According to the AM654x Data Manual[1], the setup timing in lower speed
modes can only be met if the controller uses a falling edge data launch.
To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be
cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25
speed modes.
Use the sdhci writeb callback to implement this condition.
[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1
Signed-off-by: Faiz Abbas
---
drivers/mmc/Kconfig | 1 +
drivers/mmc/am654_sdhci.c | 25 +++--
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 0c252e34c7..525445949d 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -521,6 +521,7 @@ config MMC_SDHCI_AM654
depends on MMC_SDHCI
depends on DM_MMC && OF_CONTROL && BLK
depends on REGMAP
+ select MMC_SDHCI_IO_ACCESSORS
help
Support for Secure Digital Host Controller Interface (SDHCI)
controllers present on TI's AM654 SOCs.
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 79b4331c3c..410517398a 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -369,6 +369,26 @@ static int am654_sdhci_deferred_probe(struct sdhci_host
*host)
return sdhci_probe(dev);
}
+static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
+{
+ if (reg == SDHCI_HOST_CONTROL) {
+ switch (host->mmc->selected_mode) {
+ /*
+* According to the data manual, HISPD bit
+* should not be set in these speed modes.
+*/
+ case SD_HS:
+ case MMC_HS:
+ case UHS_SDR12:
+ case UHS_SDR25:
+ val &= ~SDHCI_CTRL_HISPD;
+ default:
+ break;
+ }
+ }
+
+ writeb(val, host->ioaddr + reg);
+}
#ifdef MMC_SUPPORTS_TUNING
#define ITAP_MAX 32
static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
@@ -414,6 +434,7 @@ const struct sdhci_ops am654_sdhci_ops = {
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _sdhci_set_ios_post,
.set_control_reg= _sdhci_set_control_reg,
+ .write_b= am654_sdhci_write_b,
};
const struct am654_driver_data am654_drv_data = {
@@ -455,6 +476,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = {
#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = _4bit_sdhci_set_ios_post,
+ .write_b= am654_sdhci_write_b,
};
const struct am654_driver_data j721e_4bit_drv_data = {
@@ -532,6 +554,7 @@ static int am654_sdhci_probe(struct udevice *dev)
host->max_clk = clock;
host->mmc = >mmc;
host->mmc->dev = dev;
+ host->ops = drv_data->ops;
ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
AM654_SDHCI_MIN_FREQ);
if (ret)
@@ -541,8 +564,6 @@ static int am654_sdhci_probe(struct udevice *dev)
if (ret)
return ret;
- host->ops = drv_data->ops;
-
/* Update ops based on SoC revision */
soc = soc_device_match(am654_sdhci_soc_attr);
if (soc && soc->data) {
--
2.17.1
[PATCH 06/17] mmc: am654_sdhci: Add support for input tap delay
DLL need only be enabled for speed modes and clock frequencies at or
above 50 MHz. For speed modes that don't enable the DLL, we need to
configure a static input delay value. This involves reading an optional
itap-del-sel-* value from the device tree and configuring it for the
appropriate speed mode.
Therefore, move all dll configurations to their own functions and gate it
with 50 MHz speed and a minimum mode. If both these conditions are not
satisfied then configure delay chain modes.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 241 +-
1 file changed, 161 insertions(+), 80 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 71798be765..f472672152 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -62,6 +62,16 @@
#define CALDONE_MASK BIT(CALDONE_SHIFT)
#define RETRIM_SHIFT 17
#define RETRIM_MASKBIT(RETRIM_SHIFT)
+#define SELDLYTXCLK_SHIFT 17
+#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
+#define SELDLYRXCLK_SHIFT 16
+#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
+#define ITAPDLYSEL_SHIFT 0
+#define ITAPDLYSEL_MASKGENMASK(4, 0)
+#define ITAPDLYENA_SHIFT 8
+#define ITAPDLYENA_MASKBIT(ITAPDLYENA_SHIFT)
+#define ITAPCHGWIN_SHIFT 9
+#define ITAPCHGWIN_MASKBIT(ITAPCHGWIN_SHIFT)
#define DRIVER_STRENGTH_50_OHM 0x0
#define DRIVER_STRENGTH_33_OHM 0x1
@@ -70,6 +80,7 @@
#define DRIVER_STRENGTH_40_OHM 0x4
#define AM654_SDHCI_MIN_FREQ 40
+#define CLOCK_TOO_SLOW_HZ 5000
struct am654_sdhci_plat {
struct mmc_config cfg;
@@ -77,6 +88,7 @@ struct am654_sdhci_plat {
struct regmap *base;
bool non_removable;
u32 otap_del_sel[MMC_MODES_END];
+ u32 itap_del_sel[MMC_MODES_END];
u32 trm_icp;
u32 drv_strength;
u32 strb_sel;
@@ -89,22 +101,45 @@ struct am654_sdhci_plat {
};
struct timing_data {
- const char *binding;
+ const char *otap_binding;
+ const char *itap_binding;
u32 capability;
};
static const struct timing_data td[] = {
- [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
- [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
- [SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
- [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
- [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
- [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
- [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
- [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
- [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
- [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
- [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
+ [MMC_LEGACY]= {"ti,otap-del-sel-legacy",
+ "ti,itap-del-sel-legacy",
+ 0},
+ [MMC_HS]= {"ti,otap-del-sel-mmc-hs",
+ "ti,itap-del-sel-mms-hs",
+ MMC_CAP(MMC_HS)},
+ [SD_HS] = {"ti,otap-del-sel-sd-hs",
+ "ti,itap-del-sel-sd-hs",
+ MMC_CAP(SD_HS)},
+ [UHS_SDR12] = {"ti,otap-del-sel-sdr12",
+ "ti,itap-del-sel-sdr12",
+ MMC_CAP(UHS_SDR12)},
+ [UHS_SDR25] = {"ti,otap-del-sel-sdr25",
+ "ti,itap-del-sel-sdr25",
+ MMC_CAP(UHS_SDR25)},
+ [UHS_SDR50] = {"ti,otap-del-sel-sdr50",
+ NULL,
+ MMC_CAP(UHS_SDR50)},
+ [UHS_SDR104]= {"ti,otap-del-sel-sdr104",
+ NULL,
+ MMC_CAP(UHS_SDR104)},
+ [UHS_DDR50] = {"ti,otap-del-sel-ddr50",
+ NULL,
+ MMC_CAP(UHS_DDR50)},
+ [MMC_DDR_52]= {"ti,otap-del-sel-ddr52",
+ "ti,itap-del-sel-ddr52",
+ MMC_CAP(MMC_DDR_52)},
+ [MMC_HS_200]= {"ti,otap-del-sel-hs200",
+ NULL,
+ MMC_CAP(MMC_HS_200)},
+ [MMC_HS_400]= {"ti,otap-del-sel-hs400",
+ NULL,
+ MMC_CAP(MMC_HS_400)},
};
struct am654_driver_data {
@@ -127,12 +162,99 @@ static void am654_sdhci_set_control_reg(struct sdhci_host
*host)
sdhci_set_uhs_timing(host);
}
+static int am654_sdhci_setup_dll(struct am654_sdhc
[PATCH 02/17] mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post()
There are some speed modes that work without switching the dll on.
Unconditionally switch off the DLL before setting clock frequency to
support this case. The software will automatically enable DLL for speed
modes that require it. This also means the dll_on priv data member is no
longer required.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 82abf484e4..15a47f1e71 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -84,7 +84,6 @@ struct am654_sdhci_plat {
#define IOMUX_PRESENT (1 << 1)
#define FREQSEL_2_BIT (1 << 2)
#define STRBSEL_4_BIT (1 << 3)
- bool dll_on;
};
struct timing_data {
@@ -141,12 +140,7 @@ static int am654_sdhci_set_ios_post(struct sdhci_host
*host)
val &= ~SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
- /* power off phy */
- if (plat->dll_on) {
- regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
-
- plat->dll_on = false;
- }
+ regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
/* restart clock */
sdhci_set_clock(host->mmc, speed);
@@ -212,8 +206,6 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
val & DLLRDY_MASK, 1000, 100);
if (ret)
return ret;
-
- plat->dll_on = true;
}
return 0;
--
2.17.1
[PATCH 04/17] mmc: am654_sdhci: Add flag for PHY calibration
Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB
flag to indicate the same.
Also move the write of trm_icp and driver strength to the set_clock()
function to match the kernel configuration flow.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 10350d8d61..145373ad46 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -84,6 +84,7 @@ struct am654_sdhci_plat {
#define IOMUX_PRESENT BIT(1)
#define FREQSEL_2_BIT BIT(2)
#define STRBSEL_4_BIT BIT(3)
+#define DLL_CALIB BIT(4)
};
struct timing_data {
@@ -195,6 +196,15 @@ static int am654_sdhci_set_ios_post(struct sdhci_host
*host)
freqsel << FREQSEL_SHIFT);
}
+ /* Configure DLL TRIM */
+ mask = DLL_TRIM_ICP_MASK;
+ val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
+
+ /* Configure DLL driver strength */
+ mask |= DR_TY_MASK;
+ val |= plat->drv_strength << DR_TY_SHIFT;
+ regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
+
/* Enable DLL */
regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
0x1 << ENDLL_SHIFT);
@@ -221,7 +231,7 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat)
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
- if (plat->flags & DLL_PRESENT) {
+ if (plat->flags & DLL_CALIB) {
regmap_read(plat->base, PHY_STAT1, );
if (~val & CALDONE_MASK) {
/* Calibrate IO lines */
@@ -233,15 +243,6 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat)
if (ret)
return ret;
}
-
- /* Configure DLL TRIM */
- mask = DLL_TRIM_ICP_MASK;
- val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
-
- /* Configure DLL driver strength */
- mask |= DR_TY_MASK;
- val |= plat->drv_strength << DR_TY_SHIFT;
- regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
}
/* Enable pins by setting IO mux to 0 */
@@ -292,12 +293,13 @@ const struct sdhci_ops am654_sdhci_ops = {
const struct am654_driver_data am654_drv_data = {
.ops = _sdhci_ops,
- .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
+ .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB |
+STRBSEL_4_BIT,
};
const struct am654_driver_data j721e_8bit_drv_data = {
.ops = _sdhci_ops,
- .flags = DLL_PRESENT,
+ .flags = DLL_PRESENT | DLL_CALIB,
};
static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
--
2.17.1
[PATCH 01/17] mmc: sdhci: Add helper functions for UHS modes
Add a set_voltage() function which handles the switch from 3.3V to 1.8V
for SD card UHS modes.
Signed-off-by: Faiz Abbas
---
drivers/mmc/sdhci.c | 49 +
include/sdhci.h | 1 +
2 files changed, 50 insertions(+)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 7673219fb3..987055d970 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
@@ -556,6 +557,54 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
}
+#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
+static void sdhci_set_voltage(struct sdhci_host *host)
+{
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u32 ctrl;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ switch (mmc->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+ if (mmc->vqmmc_supply) {
+ regulator_set_enable(mmc->vqmmc_supply, false);
+ regulator_set_value(mmc->vqmmc_supply, 330);
+ regulator_set_enable(mmc->vqmmc_supply, true);
+ }
+
+ mdelay(5);
+ if (IS_SD(mmc)) {
+ ctrl &= ~SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
+ break;
+ case MMC_SIGNAL_VOLTAGE_180:
+ if (mmc->vqmmc_supply) {
+ regulator_set_enable(mmc->vqmmc_supply, false);
+ regulator_set_value(mmc->vqmmc_supply, 180);
+ regulator_set_enable(mmc->vqmmc_supply, true);
+ }
+
+ if (IS_SD(mmc)) {
+ ctrl |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
+ break;
+ default:
+ /* No signal voltage switch required */
+ return;
+ }
+}
+#else
+static void sdhci_set_voltage(struct sdhci_host *host) { }
+#endif
+void sdhci_set_control_reg(struct sdhci_host *host)
+{
+ sdhci_set_voltage(host);
+ sdhci_set_uhs_timing(host);
+}
+
#ifdef CONFIG_DM_MMC
static int sdhci_set_ios(struct udevice *dev)
{
diff --git a/include/sdhci.h b/include/sdhci.h
index 94fc3ed56a..d3f8741042 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -492,6 +492,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host);
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
+void sdhci_set_control_reg(struct sdhci_host *host);
extern const struct dm_mmc_ops sdhci_ops;
#else
#endif
--
2.17.1
[PATCH 05/17] mmc: am654_sdhci: Add support for AM65x SR2.0
Add Support for AM65x PG2.0. Use the SoC bus framework to fixup
the platform data and do DLL calibration if the revision is 1.0
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 145373ad46..71798be765 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -292,6 +293,11 @@ const struct sdhci_ops am654_sdhci_ops = {
};
const struct am654_driver_data am654_drv_data = {
+ .ops = _sdhci_ops,
+ .flags = DLL_PRESENT | IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT,
+};
+
+const struct am654_driver_data am654_sr1_drv_data = {
.ops = _sdhci_ops,
.flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB |
STRBSEL_4_BIT,
@@ -326,6 +332,11 @@ const struct am654_driver_data j721e_4bit_drv_data = {
.flags = IOMUX_PRESENT,
};
+const struct soc_attr am654_sdhci_soc_attr[] = {
+ { .family = "AM65X", .revision = "SR1.0", .data = _sr1_drv_data},
+ {/* sentinel */}
+};
+
static int sdhci_am654_get_otap_delay(struct udevice *dev,
struct mmc_config *cfg)
{
@@ -365,6 +376,8 @@ static int am654_sdhci_probe(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct mmc_config *cfg = >cfg;
+ const struct soc_attr *soc;
+ const struct am654_driver_data *soc_drv_data;
struct clk clk;
unsigned long clock;
int ret;
@@ -394,6 +407,14 @@ static int am654_sdhci_probe(struct udevice *dev)
return ret;
host->ops = drv_data->ops;
+
+ /* Update ops based on SoC revision */
+ soc = soc_device_match(am654_sdhci_soc_attr);
+ if (soc && soc->data) {
+ soc_drv_data = soc->data;
+ host->ops = soc_drv_data->ops;
+ }
+
host->mmc->priv = host;
upriv->mmc = host->mmc;
@@ -458,9 +479,18 @@ static int am654_sdhci_bind(struct udevice *dev)
struct am654_driver_data *drv_data =
(struct am654_driver_data *)dev_get_driver_data(dev);
struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ const struct soc_attr *soc;
+ const struct am654_driver_data *soc_drv_data;
plat->flags = drv_data->flags;
+ /* Update flags based on SoC revision */
+ soc = soc_device_match(am654_sdhci_soc_attr);
+ if (soc && soc->data) {
+ soc_drv_data = soc->data;
+ plat->flags = soc_drv_data->flags;
+ }
+
return sdhci_bind(dev, >mmc, >cfg);
}
--
2.17.1
[PATCH 03/17] mmc: am654_sdhci: Convert flag fields to BIT macro
Convert the flags field defines to use the BIT() macro.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 15a47f1e71..10350d8d61 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -80,10 +80,10 @@ struct am654_sdhci_plat {
u32 drv_strength;
u32 strb_sel;
u32 flags;
-#define DLL_PRESENT(1 << 0)
-#define IOMUX_PRESENT (1 << 1)
-#define FREQSEL_2_BIT (1 << 2)
-#define STRBSEL_4_BIT (1 << 3)
+#define DLL_PRESENTBIT(0)
+#define IOMUX_PRESENT BIT(1)
+#define FREQSEL_2_BIT BIT(2)
+#define STRBSEL_4_BIT BIT(3)
};
struct timing_data {
--
2.17.1
[PATCH 00/17] Add support for MMC higher speed modes for TI's am65x, j721e and j7200 platforms
The following patches add support for higher speeds in the SD card and eMMC for TI's am65x, j721e, j7200 platforms. After these patches j721e and j7200 will support ultra high speed while am65x will support upto high speed modes. Faiz Abbas (17): mmc: sdhci: Add helper functions for UHS modes mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post() mmc: am654_sdhci: Convert flag fields to BIT macro mmc: am654_sdhci: Add flag for PHY calibration mmc: am654_sdhci: Add support for AM65x SR2.0 mmc: am654_sdhci: Add support for input tap delay mmc: am654_sdhci: Add support for writing to clkbuf_sel mmc: am654_sdhci: Add support for software tuning mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes mmc: am654_sdhci: Use sdhci_set_control_reg() arm: dts: k3-am65: Fix mmc nodes arm: dts: k3-j721e-main: Update otap-delay values arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD card arm: dts: k3-j7200-main: Add support for gpio0 arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes configs: j721e_evm: Add support for UHS modes configs: j7200_evm: Add support for UHS modes arch/arm/dts/k3-am65-main.dtsi| 22 + arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 67 +-- arch/arm/dts/k3-am654-base-board.dts | 25 ++ arch/arm/dts/k3-am654-r5-base-board.dts | 20 +- arch/arm/dts/k3-j7200-common-proc-board.dts | 49 ++- arch/arm/dts/k3-j7200-main.dtsi | 22 + .../arm/dts/k3-j7200-r5-common-proc-board.dts | 15 + arch/arm/dts/k3-j721e-common-proc-board.dts | 32 ++ arch/arm/dts/k3-j721e-main.dtsi | 5 +- configs/j7200_evm_a72_defconfig | 8 + configs/j7200_evm_r5_defconfig| 1 + configs/j721e_evm_a72_defconfig | 8 + configs/j721e_evm_r5_defconfig| 1 + drivers/mmc/Kconfig | 1 + drivers/mmc/am654_sdhci.c | 384 +- drivers/mmc/sdhci.c | 49 +++ include/sdhci.h | 1 + 17 files changed, 537 insertions(+), 173 deletions(-) -- 2.17.1
[PATCH v2 5/5] configs: Add spiboot support for am335x
am335x internal SRAM is too small to support the addition of
SPI bootmode to the default defconfig. Add a separate spiboot_defconfig
Signed-off-by: Faiz Abbas
---
board/ti/am335x/MAINTAINERS | 1 +
configs/am335x_evm_spiboot_defconfig | 93
2 files changed, 94 insertions(+)
create mode 100644 configs/am335x_evm_spiboot_defconfig
diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index e100adfd68..219c8715bf 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS
@@ -5,3 +5,4 @@ F: board/ti/am335x/
F: include/configs/am335x_evm.h
F: configs/am335x_boneblack_vboot_defconfig
F: configs/am335x_evm_defconfig
+F: configs/am335x_evm_spiboot_defconfig
diff --git a/configs/am335x_evm_spiboot_defconfig
b/configs/am335x_evm_spiboot_defconfig
new file mode 100644
index 00..d71a7ce75c
--- /dev/null
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_ENV_OFFSET=0x10
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x2
+CONFIG_SPL_DM_SPI=y
+CONFIG_AM33XX=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run
findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_LOGLEVEL=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
+# CONFIG_SPL_FS_EXT4 is not set
+CONFIG_SPL_MTD_SUPPORT=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_SPL=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk
am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_ENV_OVERWRITE=y
+# CONFIG_ENV_IS_IN_FAT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+# CONFIG_SPL_NAND_AM33XX_BCH is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
+CONFIG_DYNAMIC_CRC_TABLE=y
+CONFIG_RSA=y
+CONFIG_LZO=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
--
2.17.1
[PATCH v2 1/5] arm: dts: am335x-icev2: Add spi node
Add spi and spi nor flash nodes for am335x-icev2.
Signed-off-by: Faiz Abbas
---
arch/arm/dts/am335x-icev2.dts | 50 +++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
index 37484cb6f5..2a1b3a53e9 100644
--- a/arch/arm/dts/am335x-icev2.dts
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -436,3 +436,53 @@
reg = <3>;
};
};
+
+ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+
+ sn65hvs882@1 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ load-gpios = < 18 GPIO_ACTIVE_LOW>;
+
+ reg = <1>;
+ spi-max-frequency = <100>;
+ spi-cpol;
+ };
+
+ spi_nor: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q64", "jedec,spi-nor";
+ spi-max-frequency = <8000>;
+ m25p,fast-read;
+ reg = <0>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x8>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "u-boot";
+ reg = <0x8 0x10>;
+ read-only;
+ };
+
+ partition@2 {
+ label = "u-boot-env";
+ reg = <0x18 0x2>;
+ read-only;
+ };
+
+ partition@3 {
+ label = "misc";
+ reg = <0x1A 0x66>;
+ };
+ };
+};
--
2.17.1
[PATCH v2 4/5] spi: omap3_spi: Read platform data in ofdata_to_platdata()
Add an ofdata_to_platdata() callback to access dts in U-boot and
access all platform data in it. This prepares the driver for supporting
both device tree as well as static platform data structures in SPL.
Signed-off-by: Faiz Abbas
---
drivers/spi/omap3_spi.c | 37 ++---
1 file changed, 26 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index fb1cf360fc..56cb217486 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -414,17 +414,10 @@ static int omap3_spi_set_wordlen(struct udevice *dev,
unsigned int wordlen)
static int omap3_spi_probe(struct udevice *dev)
{
struct omap3_spi_priv *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
+ struct omap3_spi_plat *plat = dev_get_platdata(dev);
- struct omap2_mcspi_platform_config* data =
- (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
-
- priv->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
- if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
- priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
- else
- priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+ priv->regs = plat->regs;
+ priv->pin_dir = plat->pin_dir;
priv->wordlen = SPI_DEFAULT_WORDLEN;
spi_reset(priv->regs);
@@ -476,6 +469,7 @@ static const struct dm_spi_ops omap3_spi_ops = {
*/
};
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static struct omap2_mcspi_platform_config omap2_pdata = {
.regs_offset = 0,
};
@@ -484,16 +478,37 @@ static struct omap2_mcspi_platform_config omap4_pdata = {
.regs_offset = OMAP4_MCSPI_REG_OFFSET,
};
+static int omap3_spi_ofdata_to_platdata(struct udevice *dev)
+{
+ struct omap2_mcspi_platform_config *data =
+ (struct omap2_mcspi_platform_config *)dev_get_driver_data(dev);
+ struct omap3_spi_plat *plat = dev_get_platdata(dev);
+
+ plat->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
+
+ if (dev_read_bool(dev, "ti,pindir-d0-out-d1-in"))
+ plat->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+ else
+ plat->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+
+ return 0;
+}
+
static const struct udevice_id omap3_spi_ids[] = {
{ .compatible = "ti,omap2-mcspi", .data = (ulong)_pdata },
{ .compatible = "ti,omap4-mcspi", .data = (ulong)_pdata },
{ }
};
-
+#endif
U_BOOT_DRIVER(omap3_spi) = {
.name = "omap3_spi",
.id = UCLASS_SPI,
+ .flags = DM_FLAG_PRE_RELOC,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap3_spi_ids,
+ .ofdata_to_platdata = omap3_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct omap3_spi_plat),
+#endif
.probe = omap3_spi_probe,
.ops= _spi_ops,
.priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
--
2.17.1
[PATCH v2 0/5] Add spi boot support to am335x-icev2
The following patches add spi boot support to TI's am335x-icev2 platform v2: 1. Changed order of patches to avoid breaking build 2. Changed SPI_OFFSET to SPI0_OFFSET and moved the define arch/arm/mach-omap2/am335x/board.c 3. Updated MAINTAINERS list with the new defconfig. Faiz Abbas (5): arm: dts: am335x-icev2: Add spi node spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failures arm: mach-omap2: am33xx: Add device structure for spi spi: omap3_spi: Read platform data in ofdata_to_platdata() configs: Add spiboot support for am335x arch/arm/dts/am335x-icev2.dts| 50 + arch/arm/mach-omap2/am33xx/board.c | 18 + board/ti/am335x/MAINTAINERS | 1 + configs/am335x_evm_spiboot_defconfig | 93 +++ drivers/spi/omap3_spi.c | 107 +++ drivers/spi/spi-uclass.c | 2 +- include/configs/am335x_evm.h | 2 - include/omap3_spi.h | 78 +++ 8 files changed, 268 insertions(+), 83 deletions(-) create mode 100644 configs/am335x_evm_spiboot_defconfig create mode 100644 include/omap3_spi.h -- 2.17.1
[PATCH v2 3/5] arm: mach-omap2: am33xx: Add device structure for spi
Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.
Signed-off-by: Faiz Abbas
---
arch/arm/mach-omap2/am33xx/board.c | 18 +++
drivers/spi/omap3_spi.c| 70 +--
include/configs/am335x_evm.h | 2 -
include/omap3_spi.h| 78 ++
4 files changed, 97 insertions(+), 71 deletions(-)
create mode 100644 include/omap3_spi.h
diff --git a/arch/arm/mach-omap2/am33xx/board.c
b/arch/arm/mach-omap2/am33xx/board.c
index a7b56b6bb3..2888390d24 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -49,6 +50,12 @@
#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
#define AM43XX_RDWRLVLFULL_START 0x8000
+/* SPI flash. */
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+#define AM33XX_SPI0_BASE 0x4803
+#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
@@ -142,6 +149,17 @@ U_BOOT_DEVICES(am33xx_gpios) = {
#endif
};
#endif
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct omap3_spi_plat omap3_spi_pdata = {
+ .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
+ .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
+};
+
+U_BOOT_DEVICE(am33xx_spi) = {
+ .name = "omap3_spi",
+ .platdata = _spi_pdata,
+};
+#endif
#endif
#if !CONFIG_IS_ENABLED(DM_GPIO)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index fbf9575851..fb1cf360fc 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -22,82 +22,14 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
-#define OMAP4_MCSPI_REG_OFFSET 0x100
-
struct omap2_mcspi_platform_config {
unsigned int regs_offset;
};
-/* per-register bitmasks */
-#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
-
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
-
-#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
-#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
-#define OMAP3_MCSPI_MODULCTRL_STESTBIT(3)
-
-#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
-#define OMAP3_MCSPI_CHCONF_POL BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
-#define OMAP3_MCSPI_CHCONF_EPOLBIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
-#define OMAP3_MCSPI_CHCONF_TRM_MASKGENMASK(13, 12)
-#define OMAP3_MCSPI_CHCONF_DMAWBIT(14)
-#define OMAP3_MCSPI_CHCONF_DMARBIT(15)
-#define OMAP3_MCSPI_CHCONF_DPE0BIT(16)
-#define OMAP3_MCSPI_CHCONF_DPE1BIT(17)
-#define OMAP3_MCSPI_CHCONF_IS BIT(18)
-#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
-#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
-#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
-#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
-
-#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
-#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
-
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
-#define MCSPI_PINDIR_D0_IN_D1_OUT 0
-#define MCSPI_PINDIR_D0_OUT_D1_IN 1
-
-#define OMAP3_MCSPI_MAX_FREQ 4800
-#define SPI_WAIT_TIMEOUT 10
-
-/* OMAP3 McSPI registers */
-struct mcspi_channel {
- unsigned int chconf;/* 0x2C, 0x40, 0x54, 0x68 */
- unsigned int chstat;/* 0x30, 0x44, 0x58, 0x6C */
- unsigned int chctrl;/* 0x34, 0x48, 0x5C, 0x70 */
- unsigned int tx;/* 0x38, 0x4C, 0x60, 0x74 */
- unsigned int rx;/* 0x3C, 0x50, 0x64, 0x78 */
-};
-
-struct mcspi {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned int irqstatus; /* 0x18 */
- unsigned int irqenable; /* 0x1C */
- unsigned int wakeupenable; /* 0x20 */
- unsigned int syst; /* 0x24 */
- unsigned int modulctrl; /* 0x28 */
- struct mcspi_channel channel[4];
- /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
- /* channel1: 0x40 - 0x50, bus 0 & 1 */
- /* channel2: 0x54 - 0x64, bus 0 & 1 */
- /* channel3: 0x68 - 0x78, bus 0 */
-};
-
struct omap3_spi_priv {
struct mcspi *regs;
unsigned int cs;
diff --git a/include/configs/am335x_evm.h b
[PATCH v2 2/5] spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failures
There are devices which don't use OF_CONTROL or OF_PLATDATA but instead
rely on statically defined platdata. Block dm_scan_fdt_dev() with both
configs to avoid build failures under this condition.
Signed-off-by: Faiz Abbas
Reviewed-by: Jagan Teki
---
drivers/spi/spi-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index cffd9cf0b0..55a8eed890 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -497,7 +497,7 @@ UCLASS_DRIVER(spi) = {
.id = UCLASS_SPI,
.name = "spi",
.flags = DM_UC_FLAG_SEQ_ALIAS,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.post_bind = dm_scan_fdt_dev,
#endif
.post_probe = spi_post_probe,
--
2.17.1
Re: [PATCH 0/5] Add spi boot support to am335x-icev2
Hi Lokesh, On 11/09/20 8:16 am, Lokesh Vutla wrote: > > > On 02/09/20 4:47 pm, Faiz Abbas wrote: >> The following patches add spi boot support to TI's am335x-icev2 platform > > > Can you post v2 with comments addressed? I am waiting on this for sending a PR > Will do that by today. Thanks, Faiz
Re: [PATCH 5/5] arm: mach-omap2: am33xx: Add device structure for spi
Hi Vignesh,
On 07/09/20 5:49 pm, Vignesh Raghavendra wrote:
> Hi,
>
> On 9/7/20 4:02 PM, Faiz Abbas wrote:
>> Hi Vignesh,
>>
>> On 07/09/20 1:48 pm, Vignesh Raghavendra wrote:
>>>
>>>
>>> On 9/7/20 12:36 PM, Faiz Abbas wrote:
>>>> Hi Lokesh,
>>>>
>>>> On 07/09/20 12:08 pm, Lokesh Vutla wrote:
>>>>>
> [...]
>>>>>> struct omap3_spi_priv {
>>>>>> struct mcspi *regs;
>>>>>> unsigned int cs;
>>>>>> diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
>>>>>> index 9c4ef369c5..db1a89ad30 100644
>>>>>> --- a/include/configs/am335x_evm.h
>>>>>> +++ b/include/configs/am335x_evm.h
>>>>>> @@ -281,6 +281,10 @@
>>>>>> #endif
>>>>>>
>>>>>> /* SPI flash. */
>>>>>> +#if CONFIG_IS_ENABLED(DM_SPI)
>>>>>> +#define AM33XX_SPI_BASE 0x4803
>>>
>>> Could this be more specific? AM33XX_SPI_BASE?
>>
>> Isn't there only one McSPI instance in am335x?
>>
>
> No, there are 2 SPI ports on AM335x (see arch/arm/dts/am33xx.dtsi).
I see. I'll make the change in v2.
>
>>>
>>>>>> +#define AM33XX_SPI_OFFSET (AM33XX_SPI_BASE +
>>>>>> OMAP4_MCSPI_REG_OFFSET)
>>>>>
>>>>> Can we get the SPI base from DT?
>>>>>
>>>>
>>>> We are doing that in U-boot (see the ofdata_to_platdata() callback in
>>>> patch 4).
>>>> We need hardcoded static platdata for SPL. Was this not clear from the
>>>> commit
>>>> message?
>>>>
>>>
>>> Then why not move these defines to arch/arm/mach-omap2/am33xx/board.c as
>>> well?
>>
>> All the other base addresses used in arch/arm/mach-omap2/am33xx/board.c are
>> included
>> from here. For example see UART platdata (struct ns16550_platdata
>> am33xx_serial[]).
>>
>
> UART is bad example as those #defines were added in 2012 which predate
> platdata introduction...
>
> Besides what happens when derivative of AM335x (see
> include/configs/am335x_*.h) want to enable SPI boot? Would each such
> files need to duplicate this snippet?
>
Ok. I'll move the base address to the board file.
Thanks,
Faiz
Re: [PATCH 5/5] arm: mach-omap2: am33xx: Add device structure for spi
Hi Vignesh,
On 07/09/20 1:48 pm, Vignesh Raghavendra wrote:
>
>
> On 9/7/20 12:36 PM, Faiz Abbas wrote:
>> Hi Lokesh,
>>
>> On 07/09/20 12:08 pm, Lokesh Vutla wrote:
>>>
>>>
>>> On 02/09/20 4:48 pm, Faiz Abbas wrote:
>>>> Add platform data and a device structure for the spi device
>>>> present on am335x-icev2. This requires moving all omap3_spi
>>>> platform data structures and symbols to an omap3_spi.h so that
>>>> the board file can access them.
>>>>
>>>> Signed-off-by: Faiz Abbas
>>>> ---
>>>> arch/arm/mach-omap2/am33xx/board.c | 12 +
>>>> drivers/spi/omap3_spi.c| 70 +--
>>>> include/configs/am335x_evm.h | 4 ++
>>>> include/omap3_spi.h| 78 ++
>>>> 4 files changed, 95 insertions(+), 69 deletions(-)
>>>> create mode 100644 include/omap3_spi.h
>>>>
>>>> diff --git a/arch/arm/mach-omap2/am33xx/board.c
>>>> b/arch/arm/mach-omap2/am33xx/board.c
>>>> index a7b56b6bb3..2c2b38721f 100644
>>>> --- a/arch/arm/mach-omap2/am33xx/board.c
>>>> +++ b/arch/arm/mach-omap2/am33xx/board.c
>>>> @@ -14,6 +14,7 @@
>>>> #include
>>>> #include
>>>> #include
>>>> +#include
>>>> #include
>>>> #include
>>>> #include
>>>> @@ -142,6 +143,17 @@ U_BOOT_DEVICES(am33xx_gpios) = {
>>>> #endif
>>>> };
>>>> #endif
>>>> +#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
>>>> +static const struct omap3_spi_plat omap3_spi_pdata = {
>>>> + .regs = (struct mcspi *)AM33XX_SPI_OFFSET,
>>>> + .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
>>>> +};
>>>> +
>>>> +U_BOOT_DEVICE(am33xx_spi) = {
>>>> + .name = "omap3_spi",
>>>> + .platdata = _spi_pdata,
>>>> +};
>>>> +#endif
>>>> #endif
>>>>
>>>> #if !CONFIG_IS_ENABLED(DM_GPIO)
>>>> diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
>>>> index 08daacf6f0..56cb217486 100644
>>>> --- a/drivers/spi/omap3_spi.c
>>>> +++ b/drivers/spi/omap3_spi.c
>>>> @@ -22,82 +22,14 @@
>>>> #include
>>>> #include
>>>> #include
>>>> +#include
>>>>
>>>> DECLARE_GLOBAL_DATA_PTR;
>>>>
>>>> -#define OMAP4_MCSPI_REG_OFFSET0x100
>>>> -
>>>> struct omap2_mcspi_platform_config {
>>>>unsigned int regs_offset;
>>>> };
>>>>
>>>> -/* per-register bitmasks */
>>>> -#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
>>>> -#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
>>>> -#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLEBIT(0)
>>>> -#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
>>>> -
>>>> -#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
>>>> -
>>>> -#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
>>>> -#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
>>>> -#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
>>>> -
>>>> -#define OMAP3_MCSPI_CHCONF_PHABIT(0)
>>>> -#define OMAP3_MCSPI_CHCONF_POLBIT(1)
>>>> -#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
>>>> -#define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
>>>> -#define OMAP3_MCSPI_CHCONF_WL_MASKGENMASK(11, 7)
>>>> -#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLYBIT(12)
>>>> -#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLYBIT(13)
>>>> -#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
>>>> -#define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
>>>> -#define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
>>>> -#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
>>>> -#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
>>>> -#define OMAP3_MCSPI_CHCONF_IS BIT(18)
>>>> -#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
>>>> -#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
>>>> -
>>>> -#define OMAP3_MCSPI_CHSTAT_RXSBIT(0)
>>>> -#define OMAP3_MCSPI_CHSTAT_TXSBIT(1)
>>>> -#define OMAP3_MCSPI_CHSTAT_EOTBIT(2)
>>>> -
>>>> -#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
>>>
Re: [PATCH 5/5] arm: mach-omap2: am33xx: Add device structure for spi
Hi Lokesh,
On 07/09/20 12:08 pm, Lokesh Vutla wrote:
>
>
> On 02/09/20 4:48 pm, Faiz Abbas wrote:
>> Add platform data and a device structure for the spi device
>> present on am335x-icev2. This requires moving all omap3_spi
>> platform data structures and symbols to an omap3_spi.h so that
>> the board file can access them.
>>
>> Signed-off-by: Faiz Abbas
>> ---
>> arch/arm/mach-omap2/am33xx/board.c | 12 +
>> drivers/spi/omap3_spi.c| 70 +--
>> include/configs/am335x_evm.h | 4 ++
>> include/omap3_spi.h| 78 ++
>> 4 files changed, 95 insertions(+), 69 deletions(-)
>> create mode 100644 include/omap3_spi.h
>>
>> diff --git a/arch/arm/mach-omap2/am33xx/board.c
>> b/arch/arm/mach-omap2/am33xx/board.c
>> index a7b56b6bb3..2c2b38721f 100644
>> --- a/arch/arm/mach-omap2/am33xx/board.c
>> +++ b/arch/arm/mach-omap2/am33xx/board.c
>> @@ -14,6 +14,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -142,6 +143,17 @@ U_BOOT_DEVICES(am33xx_gpios) = {
>> #endif
>> };
>> #endif
>> +#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
>> +static const struct omap3_spi_plat omap3_spi_pdata = {
>> +.regs = (struct mcspi *)AM33XX_SPI_OFFSET,
>> +.pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
>> +};
>> +
>> +U_BOOT_DEVICE(am33xx_spi) = {
>> +.name = "omap3_spi",
>> +.platdata = _spi_pdata,
>> +};
>> +#endif
>> #endif
>>
>> #if !CONFIG_IS_ENABLED(DM_GPIO)
>> diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
>> index 08daacf6f0..56cb217486 100644
>> --- a/drivers/spi/omap3_spi.c
>> +++ b/drivers/spi/omap3_spi.c
>> @@ -22,82 +22,14 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> -#define OMAP4_MCSPI_REG_OFFSET 0x100
>> -
>> struct omap2_mcspi_platform_config {
>> unsigned int regs_offset;
>> };
>>
>> -/* per-register bitmasks */
>> -#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
>> -#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
>> -#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
>> -#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
>> -
>> -#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
>> -
>> -#define OMAP3_MCSPI_MODULCTRL_SINGLEBIT(0)
>> -#define OMAP3_MCSPI_MODULCTRL_MSBIT(2)
>> -#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
>> -
>> -#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
>> -#define OMAP3_MCSPI_CHCONF_POL BIT(1)
>> -#define OMAP3_MCSPI_CHCONF_CLKD_MASKGENMASK(5, 2)
>> -#define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
>> -#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
>> -#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
>> -#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
>> -#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
>> -#define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
>> -#define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
>> -#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
>> -#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
>> -#define OMAP3_MCSPI_CHCONF_IS BIT(18)
>> -#define OMAP3_MCSPI_CHCONF_TURBOBIT(19)
>> -#define OMAP3_MCSPI_CHCONF_FORCEBIT(20)
>> -
>> -#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
>> -#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
>> -#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
>> -
>> -#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
>> -#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
>> -
>> -#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
>> -#define MCSPI_PINDIR_D0_IN_D1_OUT 0
>> -#define MCSPI_PINDIR_D0_OUT_D1_IN 1
>> -
>> -#define OMAP3_MCSPI_MAX_FREQ4800
>> -#define SPI_WAIT_TIMEOUT10
>> -
>> -/* OMAP3 McSPI registers */
>> -struct mcspi_channel {
>> -unsigned int chconf;/* 0x2C, 0x40, 0x54, 0x68 */
>> -unsigned int chstat;/* 0x30, 0x44, 0x58, 0x6C */
>> -unsigned int chctrl;/* 0x34, 0x48, 0x5C, 0x70 */
>> -unsigned int tx;/* 0x38, 0x4C, 0x60, 0x74 */
>> -unsigned int rx;/* 0x3C, 0x50, 0x64, 0x78 */
>> -};
>> -
>> -struct mcspi {
>> -unsigned char res1[0x10];
&g
[PATCH 5/5] arm: mach-omap2: am33xx: Add device structure for spi
Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.
Signed-off-by: Faiz Abbas
---
arch/arm/mach-omap2/am33xx/board.c | 12 +
drivers/spi/omap3_spi.c| 70 +--
include/configs/am335x_evm.h | 4 ++
include/omap3_spi.h| 78 ++
4 files changed, 95 insertions(+), 69 deletions(-)
create mode 100644 include/omap3_spi.h
diff --git a/arch/arm/mach-omap2/am33xx/board.c
b/arch/arm/mach-omap2/am33xx/board.c
index a7b56b6bb3..2c2b38721f 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -142,6 +143,17 @@ U_BOOT_DEVICES(am33xx_gpios) = {
#endif
};
#endif
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct omap3_spi_plat omap3_spi_pdata = {
+ .regs = (struct mcspi *)AM33XX_SPI_OFFSET,
+ .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
+};
+
+U_BOOT_DEVICE(am33xx_spi) = {
+ .name = "omap3_spi",
+ .platdata = _spi_pdata,
+};
+#endif
#endif
#if !CONFIG_IS_ENABLED(DM_GPIO)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 08daacf6f0..56cb217486 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -22,82 +22,14 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
-#define OMAP4_MCSPI_REG_OFFSET 0x100
-
struct omap2_mcspi_platform_config {
unsigned int regs_offset;
};
-/* per-register bitmasks */
-#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
-
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
-
-#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
-#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
-#define OMAP3_MCSPI_MODULCTRL_STESTBIT(3)
-
-#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
-#define OMAP3_MCSPI_CHCONF_POL BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
-#define OMAP3_MCSPI_CHCONF_EPOLBIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
-#define OMAP3_MCSPI_CHCONF_TRM_MASKGENMASK(13, 12)
-#define OMAP3_MCSPI_CHCONF_DMAWBIT(14)
-#define OMAP3_MCSPI_CHCONF_DMARBIT(15)
-#define OMAP3_MCSPI_CHCONF_DPE0BIT(16)
-#define OMAP3_MCSPI_CHCONF_DPE1BIT(17)
-#define OMAP3_MCSPI_CHCONF_IS BIT(18)
-#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
-#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
-#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
-#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
-
-#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
-#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
-
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
-#define MCSPI_PINDIR_D0_IN_D1_OUT 0
-#define MCSPI_PINDIR_D0_OUT_D1_IN 1
-
-#define OMAP3_MCSPI_MAX_FREQ 4800
-#define SPI_WAIT_TIMEOUT 10
-
-/* OMAP3 McSPI registers */
-struct mcspi_channel {
- unsigned int chconf;/* 0x2C, 0x40, 0x54, 0x68 */
- unsigned int chstat;/* 0x30, 0x44, 0x58, 0x6C */
- unsigned int chctrl;/* 0x34, 0x48, 0x5C, 0x70 */
- unsigned int tx;/* 0x38, 0x4C, 0x60, 0x74 */
- unsigned int rx;/* 0x3C, 0x50, 0x64, 0x78 */
-};
-
-struct mcspi {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned int irqstatus; /* 0x18 */
- unsigned int irqenable; /* 0x1C */
- unsigned int wakeupenable; /* 0x20 */
- unsigned int syst; /* 0x24 */
- unsigned int modulctrl; /* 0x28 */
- struct mcspi_channel channel[4];
- /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
- /* channel1: 0x40 - 0x50, bus 0 & 1 */
- /* channel2: 0x54 - 0x64, bus 0 & 1 */
- /* channel3: 0x68 - 0x78, bus 0 */
-};
-
struct omap3_spi_priv {
struct mcspi *regs;
unsigned int cs;
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 9c4ef369c5..db1a89ad30 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -281,6 +281,10 @@
#endif
/* SPI flash. */
+#if CONFIG_IS_ENABLED(DM_SPI)
+#define AM33XX_SPI_BASE0x4803
+#define AM33XX_SPI_OFFSET (AM33XX_SPI_BASE + OMAP4_MCSPI_REG_OFFSET)
+#endif
/* Network. */
/* Enable Atheros phy driver */
diff --git a/inclu
[PATCH 4/5] spi: omap3_spi: Read platform data in ofdata_to_platdata()
Add an ofdata_to_platdata() callback to access dts in U-boot and
access all platform data in it. This prepares the driver for supporting
both device tree as well as static platform data structures in SPL.
Signed-off-by: Faiz Abbas
---
drivers/spi/omap3_spi.c | 37 ++---
1 file changed, 26 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index fbf9575851..08daacf6f0 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -482,17 +482,10 @@ static int omap3_spi_set_wordlen(struct udevice *dev,
unsigned int wordlen)
static int omap3_spi_probe(struct udevice *dev)
{
struct omap3_spi_priv *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
+ struct omap3_spi_plat *plat = dev_get_platdata(dev);
- struct omap2_mcspi_platform_config* data =
- (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
-
- priv->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
- if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
- priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
- else
- priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+ priv->regs = plat->regs;
+ priv->pin_dir = plat->pin_dir;
priv->wordlen = SPI_DEFAULT_WORDLEN;
spi_reset(priv->regs);
@@ -544,6 +537,7 @@ static const struct dm_spi_ops omap3_spi_ops = {
*/
};
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static struct omap2_mcspi_platform_config omap2_pdata = {
.regs_offset = 0,
};
@@ -552,16 +546,37 @@ static struct omap2_mcspi_platform_config omap4_pdata = {
.regs_offset = OMAP4_MCSPI_REG_OFFSET,
};
+static int omap3_spi_ofdata_to_platdata(struct udevice *dev)
+{
+ struct omap2_mcspi_platform_config *data =
+ (struct omap2_mcspi_platform_config *)dev_get_driver_data(dev);
+ struct omap3_spi_plat *plat = dev_get_platdata(dev);
+
+ plat->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
+
+ if (dev_read_bool(dev, "ti,pindir-d0-out-d1-in"))
+ plat->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+ else
+ plat->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+
+ return 0;
+}
+
static const struct udevice_id omap3_spi_ids[] = {
{ .compatible = "ti,omap2-mcspi", .data = (ulong)_pdata },
{ .compatible = "ti,omap4-mcspi", .data = (ulong)_pdata },
{ }
};
-
+#endif
U_BOOT_DRIVER(omap3_spi) = {
.name = "omap3_spi",
.id = UCLASS_SPI,
+ .flags = DM_FLAG_PRE_RELOC,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap3_spi_ids,
+ .ofdata_to_platdata = omap3_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct omap3_spi_plat),
+#endif
.probe = omap3_spi_probe,
.ops= _spi_ops,
.priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
--
2.17.1
[PATCH 3/5] spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failures
There are devices which don't use OF_CONTROL or OF_PLATDATA but instead
rely on statically defined platdata. Block dm_scan_fdt_dev() with both
configs to avoid build failures under this condition.
Signed-off-by: Faiz Abbas
---
drivers/spi/spi-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index cffd9cf0b0..55a8eed890 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -497,7 +497,7 @@ UCLASS_DRIVER(spi) = {
.id = UCLASS_SPI,
.name = "spi",
.flags = DM_UC_FLAG_SEQ_ALIAS,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.post_bind = dm_scan_fdt_dev,
#endif
.post_probe = spi_post_probe,
--
2.17.1
[PATCH 2/5] configs: Add spiboot support for am335x
am335x internal SRAM is too small to support the addition of
SPI bootmode to the default defconfig. Add a separate spiboot_defconfig
Signed-off-by: Faiz Abbas
---
configs/am335x_evm_spiboot_defconfig | 93
1 file changed, 93 insertions(+)
create mode 100644 configs/am335x_evm_spiboot_defconfig
diff --git a/configs/am335x_evm_spiboot_defconfig
b/configs/am335x_evm_spiboot_defconfig
new file mode 100644
index 00..d71a7ce75c
--- /dev/null
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_ENV_OFFSET=0x10
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x2
+CONFIG_SPL_DM_SPI=y
+CONFIG_AM33XX=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run
findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_LOGLEVEL=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
+# CONFIG_SPL_FS_EXT4 is not set
+CONFIG_SPL_MTD_SUPPORT=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_SPL=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk
am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_ENV_OVERWRITE=y
+# CONFIG_ENV_IS_IN_FAT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+# CONFIG_SPL_NAND_AM33XX_BCH is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
+CONFIG_DYNAMIC_CRC_TABLE=y
+CONFIG_RSA=y
+CONFIG_LZO=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
--
2.17.1
[PATCH 0/5] Add spi boot support to am335x-icev2
The following patches add spi boot support to TI's am335x-icev2 platform Faiz Abbas (5): arm: dts: am335x-icev2: Add spi node configs: Add spiboot support for am335x spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failures spi: omap3_spi: Read platform data in ofdata_to_platdata() arm: mach-omap2: am33xx: Add device structure for spi arch/arm/dts/am335x-icev2.dts| 50 + arch/arm/mach-omap2/am33xx/board.c | 12 +++ configs/am335x_evm_spiboot_defconfig | 93 +++ drivers/spi/omap3_spi.c | 107 +++ drivers/spi/spi-uclass.c | 2 +- include/configs/am335x_evm.h | 4 + include/omap3_spi.h | 78 +++ 7 files changed, 265 insertions(+), 81 deletions(-) create mode 100644 configs/am335x_evm_spiboot_defconfig create mode 100644 include/omap3_spi.h -- 2.17.1
[PATCH 1/5] arm: dts: am335x-icev2: Add spi node
Add spi and spi nor flash nodes for am335x-icev2.
Signed-off-by: Faiz Abbas
---
arch/arm/dts/am335x-icev2.dts | 50 +++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
index 37484cb6f5..2a1b3a53e9 100644
--- a/arch/arm/dts/am335x-icev2.dts
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -436,3 +436,53 @@
reg = <3>;
};
};
+
+ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+
+ sn65hvs882@1 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ load-gpios = < 18 GPIO_ACTIVE_LOW>;
+
+ reg = <1>;
+ spi-max-frequency = <100>;
+ spi-cpol;
+ };
+
+ spi_nor: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q64", "jedec,spi-nor";
+ spi-max-frequency = <8000>;
+ m25p,fast-read;
+ reg = <0>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x8>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "u-boot";
+ reg = <0x8 0x10>;
+ read-only;
+ };
+
+ partition@2 {
+ label = "u-boot-env";
+ reg = <0x18 0x2>;
+ read-only;
+ };
+
+ partition@3 {
+ label = "misc";
+ reg = <0x1A 0x66>;
+ };
+ };
+};
--
2.17.1
Re: [PATCH] Revert "mmc: disable UHS modes if Vcc cannot be switched on and off"
Pali, On 11/08/20 1:19 pm, Pali Rohár wrote: > On Tuesday 11 August 2020 08:39:24 Faiz Abbas wrote: >> Pali, Peng, >> >> On 10/08/20 6:25 am, Peng Fan wrote: >>> Faiz, Jean >>> >>>> Subject: [PATCH] Revert "mmc: disable UHS modes if Vcc cannot be switched >>>> on and off" >>> >>> Got time to take a look? >>> >> >> When this issue was reported in the last thread, Pali said that he was >> unable to get >> prints because of the constant reboot loops? Shouldn't it be easy to put >> while(1) >> at different points in this execution and see which step causes the reboot >> loop? > > In May in that last thread I wrote details which I was able to gather: > > Month ago I was able to detect that problem is somewhere in function > mmc_set_ios() from mmc.c file. I put long debug line prior and also > after mmc_set_ios() call. And it was printed only prior. Not after. > So I think NULL pointer dereference is in mmc_set_ios() function. > > I could try with that while(1) loop to print detailed log message and > read/capture it. But what information for debugging you need? Or what do > you want to print which could help you? > You can continue to bisect into omap_hsmmc_set_ios() to see at what point the NULL pointer gets triggered and what the NULL pointer is. Also can you point to your config file? Thanks, Faiz
Re: [PATCH] Revert "mmc: disable UHS modes if Vcc cannot be switched on and off"
Pali, Peng, On 10/08/20 6:25 am, Peng Fan wrote: > Faiz, Jean > >> Subject: [PATCH] Revert "mmc: disable UHS modes if Vcc cannot be switched >> on and off" > > Got time to take a look? > When this issue was reported in the last thread, Pali said that he was unable to get prints because of the constant reboot loops? Shouldn't it be easy to put while(1) at different points in this execution and see which step causes the reboot loop? Thanks, Faiz
Re: [PATCH 06/13] arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modes
Hi Vignesh,
On 03/07/20 1:04 pm, Vignesh Raghavendra wrote:
> Hi,
>
> On 02/07/20 1:32 pm, Faiz Abbas wrote:
>
> [...]
>> int am6_spl_early_init(void)
>
> Can this be static or do you intend to use this outside of this func file?
Fixed this in v2.
>
>> +{
>> +int ret;
>> +#if CONFIG_VAL(SYS_MALLOC_F_LEN)
>> +#ifdef CONFIG_MALLOC_F_ADDR
>> +gd->malloc_base = CONFIG_MALLOC_F_ADDR;
>> +#endif
>> +gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN);
>> +gd->malloc_ptr = 0;
>> +#endif
>> +ret = fdtdec_setup();
>> +if (ret) {
>> +printf("fdtdec_setup() returned error %d\n", ret);
>> +return ret;
>> +}
>> +
>> +#if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
>> +fixup_usb_boot();
>> +#endif
>> +/* With CONFIG_SPL_OF_PLATDATA, bring in all devices */
>> +ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA));
>> +if (ret) {
>> +printf("dm_init_and_scan() returned error %d\n", ret);
>> +return ret;
>> +}
>> +
>> +gd->flags |= GD_FLG_SPL_EARLY_INIT;
>> +
>> +return 0;
>> +}
>> void board_init_f(ulong dummy)
>> {
>> #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
>> @@ -141,9 +206,8 @@ void board_init_f(ulong dummy)
>> disable_linefill_optimization();
>> setup_k3_mpu_regions();
>> #endif
>> -
>> /* Init DM early in-order to invoke system controller */
>> -spl_early_init();
>
> I don't like this part as patch now open codes part of spl_early_init()
> here and any fixes/enhancements to that core code would not be available
> for am6 unless explicitly ported
>
> How about having a arch specific post fdtdec_setup() hook instead, that
> gets called from spl_common_init()?
>
there was an fdtdec_board_setup() which can be overridden for this. Implemented
using that in v2.
Thanks,
Faiz
[PATCH v2 09/13] arm: dts: k3-am654-base-board: Add support for USB0 in SPL
Add nodes for USB0 in SPL to enable USB host boot mode
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 27
1 file changed, 27 insertions(+)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index a30680d3e0..d75d1b1c28 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -139,6 +139,12 @@
u-boot,dm-spl;
};
+ usb0_pins_default: usb0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9)
USB0_DRVVBUS */
+ >;
+ u-boot,dm-spl;
+ };
};
_pmx1 {
@@ -250,3 +256,24 @@
{
u-boot,dm-spl;
};
+
+_0 {
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+_phy {
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ dr_mode = "peripheral";
+ u-boot,dm-spl;
+};
+
+_conf {
+ u-boot,dm-spl;
+};
--
2.17.1
[PATCH v2 13/13] configs: Add new config for supporting USB mass storage boot
Because of space constraints, create a new USB defconfig for R5 to faciliate booting from USB mass storage devices Signed-off-by: Faiz Abbas --- configs/am65x_evm_r5_usbmsc_defconfig | 119 ++ 1 file changed, 119 insertions(+) create mode 100644 configs/am65x_evm_r5_usbmsc_defconfig diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig new file mode 100644 index 00..14682c8d27 --- /dev/null +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -0,0 +1,119 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x55000 +CONFIG_SOC_K3_AM6=y +CONFIG_K3_EARLY_CONS=y +CONFIG_TARGET_AM654_R5_EVM=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_ENV_SIZE=0x2 +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_TEXT_BASE=0x41c0 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BLK=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_GPIO=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_K3_AVS0=y +# CONFIG_MMC is not set +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_OMAP_USB2_PHY=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_TPS62360=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -- 2.17.1
[PATCH v2 08/13] arm: dts: k3-am654-r5-base-board: Add USB0 nodes
Add USB0 nodes and set them to host mode to support USB host and
peripheral boot modes
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-am654-r5-base-board.dts | 35 +
1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts
b/arch/arm/dts/k3-am654-r5-base-board.dts
index e6b78643c1..d43a4edc71 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -278,3 +278,38 @@
#size-cells = <1>;
};
};
+
+_pmx0 {
+ u-boot,dm-spl;
+ usb0_pins_default: usb0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9)
USB0_DRVVBUS */
+ >;
+ u-boot,dm-spl;
+ };
+};
+
+_0 {
+ status = "okay";
+ u-boot,dm-spl;
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+_phy {
+ status = "okay";
+ u-boot,dm-spl;
+ /delete-property/ clocks;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ dr_mode = "peripheral";
+ u-boot,dm-spl;
+};
+
+_conf {
+ u-boot,dm-spl;
+};
--
2.17.1
[PATCH v2 11/13] configs: am65x_evm_a53: Enable USB Mass storage and DFU boot modes
Enable configs to facilitate booting from USB Mass Storage devices
as well as USB peripheral boot
Signed-off-by: Faiz Abbas
---
configs/am65x_evm_a53_defconfig | 10 ++
include/configs/am65x_evm.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 86bd940e2e..654002c71a 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -26,6 +26,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
@@ -36,15 +37,21 @@ CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
@@ -73,6 +80,7 @@ CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
@@ -113,6 +121,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_KEYSTONE=y
CONFIG_PHY=y
+CONFIG_SPL_PHY=y
CONFIG_AM654_PHY=y
CONFIG_OMAP_USB2_PHY=y
CONFIG_PINCTRL=y
@@ -138,6 +147,7 @@ CONFIG_SYSRESET_TI_SCI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 902b5ba398..aa360224ac 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -148,6 +148,8 @@
#define CONFIG_SYS_MMC_ENV_PART1
#endif
+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
+
/* Now for the remaining common defines */
#include
--
2.17.1
[PATCH v2 12/13] configs: Add defconfig for USB DFU bootmode
Because of space constraints, create a new USB defconfig for R5 to faciliate booting in USB peripheral (DFU) bootmode Signed-off-by: Faiz Abbas --- configs/am65x_evm_r5_usbdfu_defconfig | 120 ++ 1 file changed, 120 insertions(+) create mode 100644 configs/am65x_evm_r5_usbdfu_defconfig diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig new file mode 100644 index 00..2343b161eb --- /dev/null +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x55000 +CONFIG_SOC_K3_AM6=y +CONFIG_K3_EARLY_CONS=y +CONFIG_TARGET_AM654_R5_EVM=y +CONFIG_ENV_SIZE=0x2 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x41c0 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8008 +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BLK=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_K3_AVS0=y +# CONFIG_MMC is not set +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_OMAP_USB2_PHY=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_TPS62360=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -- 2.17.1
[PATCH v2 10/13] configs: am65x_evm: Add support for DFU related configs
Add offset and environment related configs used for booting from DFU. Signed-off-by: Faiz Abbas --- include/configs/am65x_evm.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 19d861d402..902b5ba398 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -22,6 +22,7 @@ #ifdef CONFIG_TARGET_AM654_A53_EVM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE +\ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x2 #else /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as @@ -44,6 +45,7 @@ /* Configure R5 SPL post-relocation malloc pool in DDR */ #define CONFIG_SYS_SPL_MALLOC_START0x8400 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x5000 #endif #ifdef CONFIG_SYS_K3_SPL_ATF @@ -124,8 +126,8 @@ "rootfstype=ubifs root=ubi0:rootfs rw ubi.mtd=ospi.rootfs\0" #define EXTRA_ENV_DFUARGS \ - "dfu_bufsiz=0x2\0" \ DFU_ALT_INFO_MMC\ + DFU_ALT_INFO_RAM\ DFU_ALT_INFO_EMMC \ DFU_ALT_INFO_OSPI -- 2.17.1
[PATCH v2 07/13] arm: mach-k3: am6_init: Add support for USB boot mode
Add support for identifying USB host and device boot modes
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/am6_init.c | 5 +
arch/arm/mach-k3/include/mach/am6_hardware.h | 2 ++
arch/arm/mach-k3/include/mach/am6_spl.h | 3 ++-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index c6d4f05a01..9cb3086014 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -333,6 +333,11 @@ static u32 __get_primary_bootmedia(u32 devstat)
CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
if (port == 0x1)
bootmode = BOOT_DEVICE_MMC2;
+ } else if (bootmode == BOOT_DEVICE_DFU) {
+ u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
+ CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
+ if (mode == 0x2)
+ bootmode = BOOT_DEVICE_USB;
}
return bootmode;
diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h
b/arch/arm/mach-k3/include/mach/am6_hardware.h
index a91ef5f735..1908a13f0f 100644
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -25,6 +25,8 @@
#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT 14
#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASKGENMASK(17, 17)
#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 12
+#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT9
+#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9)
#define WKUP_CTRL_MMR0_BASE0x4300
#define MCU_CTRL_MMR0_BASE 0x40f0
diff --git a/arch/arm/mach-k3/include/mach/am6_spl.h
b/arch/arm/mach-k3/include/mach/am6_spl.h
index e97d8143c6..61e0380927 100644
--- a/arch/arm/mach-k3/include/mach/am6_spl.h
+++ b/arch/arm/mach-k3/include/mach/am6_spl.h
@@ -14,7 +14,8 @@
#define BOOT_DEVICE_I2C0x05
#define BOOT_DEVICE_MMC2 0x06
#define BOOT_DEVICE_ETHERNET 0x07
-#define BOOT_DEVICE_USB0x08
+#define BOOT_DEVICE_DFU0x08
+#define BOOT_DEVICE_USB0x408
#define BOOT_DEVICE_PCIE 0x09
#define BOOT_DEVICE_UART 0x0a
#define BOOT_DEVICE_NAND 0x0c
--
2.17.1
[PATCH v2 06/13] arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modes
U-boot only supports either USB host or device mode for a node at a
time in dts. To support both host and dfu bootmodes, set "peripheral"
as the default dr_mode but fixup property to "host" if host bootmode
is detected.
This needs to happen before the dwc3 generic layer binds the usb device
to a host or device driver. Therefore, add an fdtdec_setup_board()
implementation to fixup the dt based on the boot mode.
Also use the same fixup function to set the USB-PCIe Serdes mux to PCIe
in both the host and device cases. This is required for accessing the
interface at USB 2.0 speeds.
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/am6_init.c | 40 +
1 file changed, 40 insertions(+)
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 42d13a39f8..c6d4f05a01 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -7,6 +7,7 @@
*/
#include
+#include
#include
#include
#include
@@ -22,6 +23,8 @@
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_K3_LOAD_SYSFW
#ifdef CONFIG_TI_SECURE_DEVICE
@@ -119,7 +122,44 @@ void k3_mmc_restart_clock(void)
void k3_mmc_stop_clock(void) {}
void k3_mmc_restart_clock(void) {}
#endif
+#if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
+#define CTRLMMR_SERDES0_CTRL 0x00104080
+#define PCIE_LANE0 0x1
+static int fixup_usb_boot(void)
+{
+ int ret;
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_USB:
+ /*
+* If bootmode is Host bootmode, fixup the dr_mode to host
+* before the dwc3 bind takes place
+*/
+ ret = fdt_find_and_setprop((void *)gd->fdt_blob,
+ "/interconnect@10/dwc3@400/usb@1",
+ "dr_mode", "host", 11, 0);
+ if (ret)
+ printf("%s: fdt_find_and_setprop() failed:%d\n",
__func__,
+ ret);
+ fallthrough;
+ case BOOT_DEVICE_DFU:
+ /*
+* The serdes mux between PCIe and USB3 needs to be set to PCIe
for
+* accessing the interface at USB 2.0
+*/
+ writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+ return fixup_usb_boot();
+}
+#endif
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
--
2.17.1
[PATCH v2 04/13] arm: mach-k3: sysfw-loader: Add support to load SYSFW from USB
Add support for loading system firmware from a USB mass storage device
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/sysfw-loader.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 513be09c68..0ebd8c56a7 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -299,6 +299,17 @@ void k3_sysfw_loader(void (*config_pm_pre_callback) (void),
ret = k3_sysfw_dfu_download(sysfw_load_address);
break;
#endif
+#if CONFIG_IS_ENABLED(USB_STORAGE)
+ case BOOT_DEVICE_USB:
+ ret = spl_usb_load(_image, ,
+ CONFIG_SYS_USB_FAT_BOOT_PARTITION,
+#ifdef CONFIG_K3_SYSFW_IMAGE_NAME
+ CONFIG_K3_SYSFW_IMAGE_NAME);
+#else
+ NULL);
+#endif
+#endif
+ break;
default:
panic("Loading SYSFW image from device %u not supported!\n",
bootdev.boot_device);
--
2.17.1
[PATCH v2 05/13] arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate config
Gate mmc related system related configurations with DM_MMC to avoid build
errors when MMC is not enabled
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/am6_init.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 74557c4bb7..42d13a39f8 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -90,7 +90,7 @@ static void store_boot_index_from_rom(void)
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
}
-#if defined(CONFIG_K3_LOAD_SYSFW)
+#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
void k3_mmc_stop_clock(void)
{
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
@@ -115,6 +115,9 @@ void k3_mmc_restart_clock(void)
mmc_set_clock(mmc, mmc->saved_clock, false);
}
}
+#else
+void k3_mmc_stop_clock(void) {}
+void k3_mmc_restart_clock(void) {}
#endif
void board_init_f(ulong dummy)
--
2.17.1
[PATCH v2 03/13] armv7R: K3: am654: Use full malloc in SPL both pre and post reloc
In order to be able to use things like file system drivers early on in
SPL (before relocation) in a memory-constrained environment when DDR is
not yet available we cannot use the simple malloc scheme which does not
implement the freeing of previously allocated memory blocks. To address
this issue go ahead and enable the use of the full malloc by manually
initializing the required functionality inside board_init_f by creating
a full malloc pool inside the pre-relocation malloc pool.
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/am6_init.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 516a02e8a8..74557c4bb7 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -18,7 +18,9 @@
#include
#include
#include
+#include
#include
+#include
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_K3_LOAD_SYSFW
@@ -119,6 +121,8 @@ void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
struct udevice *dev;
+ size_t pool_size;
+ void *pool_addr;
int ret;
#endif
/*
@@ -149,6 +153,20 @@ void board_init_f(ulong dummy)
#endif
#ifdef CONFIG_K3_LOAD_SYSFW
+ /*
+* Initialize an early full malloc environment. Do so by allocating a
+* new malloc area inside the currently active pre-relocation "first"
+* malloc pool of which we use all that's left.
+*/
+ pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
+ pool_addr = malloc(pool_size);
+ if (!pool_addr)
+ panic("ERROR: Can't allocate full malloc pool!\n");
+
+ mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+ debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx
bytes\n",
+ __func__, (unsigned long)pool_addr, (unsigned long)pool_size);
/*
* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
* regardless of the result of pinctrl. Do this without probing the
--
2.17.1
[PATCH v2 02/13] spl: usb: Only init usb once
usb_init() may be called multiple times for fetching multiple images
from SPL. Skip reinitializing USB if its already been done
Signed-off-by: Faiz Abbas
---
common/spl/spl_usb.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index 92ae96f66e..3648de3492 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -22,11 +22,16 @@ int spl_usb_load(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev, int partition,
const char *filename)
{
- int err;
+ int err = 0;
struct blk_desc *stor_dev;
+ static bool usb_init_pending = true;
+
+ if (usb_init_pending) {
+ usb_stop();
+ err = usb_init();
+ usb_init_pending = false;
+ }
- usb_stop();
- err = usb_init();
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: usb init failed: err - %d\n", __func__, err);
--
2.17.1
[PATCH v2 00/13] Add support for USB host and peripheral bootmodes on am65x-idk
The following patches add support for USB mass storage and USB dfu bootmodes on am654x-idk. Because of space constrains and the size of the USB stack, there are two different usbmsc and usbdfu defconfigs for building R5 SPL. Fitting both of these into one defconfig requires some changes in the USB subsystem which is a longer term effort v2: Using fdtdec_board_setup() function override in patch 6 instead of open coding spl_common_init() Faiz Abbas (13): spl: usb: Create an API spl_usb_load() spl: usb: Only init usb once armv7R: K3: am654: Use full malloc in SPL both pre and post reloc arm: mach-k3: sysfw-loader: Add support to load SYSFW from USB arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate config arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modes arm: mach-k3: am6_init: Add support for USB boot mode arm: dts: k3-am654-r5-base-board: Add USB0 nodes arm: dts: k3-am654-base-board: Add support for USB0 in SPL configs: am65x_evm: Add support for DFU related configs configs: am65x_evm_a53: Enable USB Mass storage and DFU boot modes configs: Add defconfig for USB DFU bootmode configs: Add new config for supporting USB mass storage boot arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 27 + arch/arm/dts/k3-am654-r5-base-board.dts | 35 ++ arch/arm/mach-k3/am6_init.c | 68 ++- arch/arm/mach-k3/include/mach/am6_hardware.h | 2 + arch/arm/mach-k3/include/mach/am6_spl.h | 3 +- arch/arm/mach-k3/sysfw-loader.c | 11 ++ common/spl/spl_usb.c | 31 +++-- configs/am65x_evm_a53_defconfig | 10 ++ configs/am65x_evm_r5_usbdfu_defconfig| 120 +++ configs/am65x_evm_r5_usbmsc_defconfig| 119 ++ include/configs/am65x_evm.h | 6 +- include/spl.h| 14 +++ 12 files changed, 433 insertions(+), 13 deletions(-) create mode 100644 configs/am65x_evm_r5_usbdfu_defconfig create mode 100644 configs/am65x_evm_r5_usbmsc_defconfig -- 2.17.1
[PATCH v2 01/13] spl: usb: Create an API spl_usb_load()
Create a new API spl_usb_load() that takes the filename as a parameter
instead of taking the default U-boot PAYLOAD_NAME
Signed-off-by: Faiz Abbas
---
common/spl/spl_usb.c | 20 +---
include/spl.h| 14 ++
2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index 08837b38fc..92ae96f66e 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -18,8 +18,9 @@
static int usb_stor_curr_dev = -1; /* current device */
-static int spl_usb_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
+int spl_usb_load(struct spl_image_info *spl_image,
+struct spl_boot_device *bootdev, int partition,
+const char *filename)
{
int err;
struct blk_desc *stor_dev;
@@ -43,13 +44,10 @@ static int spl_usb_load_image(struct spl_image_info
*spl_image,
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() ||
- spl_load_image_fat_os(spl_image, stor_dev,
- CONFIG_SYS_USB_FAT_BOOT_PARTITION))
+ spl_load_image_fat_os(spl_image, stor_dev, partition))
#endif
{
- err = spl_load_image_fat(spl_image, stor_dev,
- CONFIG_SYS_USB_FAT_BOOT_PARTITION,
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ err = spl_load_image_fat(spl_image, stor_dev, partition,
filename);
}
if (err) {
@@ -59,4 +57,12 @@ static int spl_usb_load_image(struct spl_image_info
*spl_image,
return 0;
}
+
+static int spl_usb_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ return spl_usb_load(spl_image, bootdev,
+ CONFIG_SYS_USB_FAT_BOOT_PARTITION,
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+}
SPL_LOAD_IMAGE_METHOD("USB", 0, BOOT_DEVICE_USB, spl_usb_load_image);
diff --git a/include/spl.h b/include/spl.h
index 580e4e024f..b72dfc7e3d 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -503,6 +503,20 @@ int spl_mmc_load(struct spl_image_info *spl_image,
int raw_part,
unsigned long raw_sect);
+/**
+ * spl_usb_load() - Load an image file from USB mass storage
+ *
+ * @param spl_imageImage data filled in by loading process
+ * @param bootdev Describes which device to load from
+ * @param raw_part Fat partition to load from
+ * @param filename Name of file to load
+ *
+ * @return 0 on success, otherwise error code
+ */
+int spl_usb_load(struct spl_image_info *spl_image,
+struct spl_boot_device *bootdev,
+int partition, const char *filename);
+
int spl_ymodem_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev);
--
2.17.1
Re: [PATCH] mmc: sdhci: Setup HS modes based on HISPD bit
Hi, On 29/07/20 8:27 pm, Michal Simek wrote: > There is no reason to setup HS modes by default without checking bit in > capability register. > Setting up HS mode by default breaks option to disable HS mode via > sdhci-caps-mask DT property. > > Disabling HS mode can be done via DT as: > sdhci-caps-mask = <0 0x20>; > > Signed-off-by: Michal Simek > --- > I've already posted this fix here: https://patchwork.ozlabs.org/project/uboot/patch/20200723041219.2438-1-faiz_ab...@ti.com/ Thanks, Faiz
[PATCH] mmc: am654_sdhci: Use MMC_MODES_END value instead of hardcoded value
The hardcoded array size leads to array overflows with changes in
speed modes enum in mmc core. Use MMC_MODES_END for otap_del_sel
array declaration to fix this.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index cbc531dc53..82abf484e4 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -75,7 +75,7 @@ struct am654_sdhci_plat {
struct mmc mmc;
struct regmap *base;
bool non_removable;
- u32 otap_del_sel[11];
+ u32 otap_del_sel[MMC_MODES_END];
u32 trm_icp;
u32 drv_strength;
u32 strb_sel;
--
2.17.1
Re: [PATCH 15/18] arm: dts: k3-j7200: Add dts support
Hi Lokesh,
Hi Lokesh,
On 23/07/20 2:17 pm, Lokesh Vutla wrote:
> Add the basic r5 and a72 basic dts for j7200. Following nodes were
> supported:
> - UART
> - MMC SD
> - I2C
> - TISCI communication
>
> Signed-off-by: Lokesh Vutla
> Signed-off-by: Vignesh Raghavendra
> Signed-off-by: Vishal Mahaveer
> Signed-off-by: Faiz Abbas
> ---
> arch/arm/dts/Makefile | 4 +-
> .../k3-j7200-common-proc-board-u-boot.dtsi| 92 +
> arch/arm/dts/k3-j7200-common-proc-board.dts | 94 ++
> arch/arm/dts/k3-j7200-main.dtsi | 313 ++
> arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 117 +++
> .../arm/dts/k3-j7200-r5-common-proc-board.dts | 191 +++
> arch/arm/dts/k3-j7200-som-p0.dtsi | 29 ++
> arch/arm/dts/k3-j7200.dtsi| 175 ++
> 8 files changed, 1014 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
> create mode 100644 arch/arm/dts/k3-j7200-common-proc-board.dts
> create mode 100644 arch/arm/dts/k3-j7200-main.dtsi
> create mode 100644 arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
> create mode 100644 arch/arm/dts/k3-j7200-r5-common-proc-board.dts
> create mode 100644 arch/arm/dts/k3-j7200-som-p0.dtsi
> create mode 100644 arch/arm/dts/k3-j7200.dtsi
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index cee10f533f..cdca20206f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -938,7 +938,9 @@ dtb-$(CONFIG_STM32MP15x) += \
>
...
> +
> + main_sdhci0: sdhci@4f8000 {
/s/4f8000/4f8
> + compatible = "ti,j7200-sdhci-8bit";
Replace with compatible = "ti,j7200-sdhci-8bit", ti,j721e-sdhci-8bit";
> + reg = <0x0 0x04f8 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
> + interrupts = ;
> + power-domains = <_pds 91 TI_SCI_PD_EXCLUSIVE>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <_clks 91 3>, <_clks 91 0>;
> + ti,otap-del-sel-legacy = <0x0>;
> + ti,otap-del-sel-mmc-hs = <0x0>;
> + ti,otap-del-sel-ddr52 = <0x6>;
> + ti,otap-del-sel-hs200 = <0x8>;
> + ti,otap-del-sel-hs400 = <0x0>;
> + ti,strobe-sel = <0x77>;
> + ti,trm-icp = <0x8>;
> + bus-width = <8>;
> + mmc-hs200-1_8v;
> + mmc-ddr-1_8v;
> + dma-coherent;
> + };
> +
> + main_sdhci1: sdhci@4fb000 {
/s/4fb000/4fb
> + compatible = "ti,j7200-sdhci-4bit";
Replace with compatible = "ti,j7200-sdhci-4bit", ti,j721e-sdhci-4bit";
> + reg = <0x0 0x04fb 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
> + interrupts = ;
> + power-domains = <_pds 92 TI_SCI_PD_EXCLUSIVE>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <_clks 92 2>, <_clks 92 1>;
> + ti,otap-del-sel-legacy = <0x0>;
> + ti,otap-del-sel-sd-hs = <0x0>;
> + ti,otap-del-sel-sdr12 = <0xf>;
> + ti,otap-del-sel-sdr25 = <0xf>;
> + ti,otap-del-sel-sdr50 = <0xc>;
> + ti,otap-del-sel-sdr104 = <0x5>;
> + ti,otap-del-sel-ddr50 = <0xc>;
> + dma-coherent;
> + };
> +
Thanks,
Faiz
Re: [PATCH 14/18] mmc: am654_sdhci: Add support for J7200 devices
Hi Lokesh, On 23/07/20 2:17 pm, Lokesh Vutla wrote: > From: Faiz Abbas > > Add support for SDHCI controllers present on the J7200 device > > Signed-off-by: Faiz Abbas > --- This patch is not required. Lets have both j721e and j7200 compatibles in the dt and use only j721e in the driver for now. Thanks, Faiz
Re: am654_sdhci: mmc fail to send stop cmd
Jan, On 23/07/20 8:55 am, Faiz Abbas wrote: > Jan, > > On 21/07/20 10:52 pm, Jan Kiszka wrote: >> On 21.07.20 19:03, Faiz Abbas wrote: >>> Jan, >>> >>> On 21/07/20 12:06 pm, Jan Kiszka wrote: >>>> On 21.07.20 01:23, Jaehoon Chung wrote: >>>>> On 7/20/20 10:21 AM, Peng Fan wrote: >>>>>> Hi Jan, >>>>>> >>>>>>> Subject: am654_sdhci: mmc fail to send stop cmd >>>>>>> >>>>>>> Hi all, >>>>>>> >>>>>>> on one device with one specific SD-card (possibly an aging one), I'm >>>>>>> seeing >>>>>>> frequent "mmc fail to send stop cmd" messages, followed by read errors >>>>>>> when loading kernel and dtb. -ETIMEDOUT is returned by mmd_send_cmd. >>>>>>> However, I can always resolve this by simply retrying the stop command >>>>>>> like >>>>>>> this: >>>>>>> ... >>>> >>> >>> Its a command timeout for which we cannot program a higher timeout. >>> >>> Can you send a full failure log? >>> >> >> [unrelated fsbl, spl stuff] >> >> U-Boot 2020.07-00883-g4d6da10ce6-dirty (Jul 20 2020 - 06:30:08 +0200) >> >> Model: Siemens IOT2050 Advanced Base Board >> DRAM: 2 GiB >> MMC: sdhci@4f8: 1, sdhci@04FA: 0 >> Loading Environment from SPI Flash... SF: Detected w25q128 with page size >> 256 Bytes, erase size 64 KiB, total 16 MiB >> OK >> In:serial >> Out: serial >> Err: serial >> Hit any key to stop autoboot: 0 >> stat: 18000 >> stat: 18000 >> stat: 208000 >> switch to partitions #0, OK >> mmc1(part 0) is current device >> ** No partition table - mmc 1 ** >> switch to partitions #0, OK >> mmc0 is current device >> Scanning mmc 0:1... >> Found U-Boot script /boot/boot.scr >> 784 bytes read in 2 ms (382.8 KiB/s) >> ## Executing script at 8300 >> 65329 bytes read in 11 ms (5.7 MiB/s) >> stat: 18000 >> mmc fail to send stop cmd, -110 >> retrying... >> 17113096 bytes read in 1409 ms (11.6 MiB/s) >> Moving Image from 0x8008 to 0x8020, end=812c >> ## Flattened Device Tree blob at 8200 >>Booting using the fdt blob at 0x8200 >>Loading Device Tree to fdf0f000, end fdf21f30 ... OK >> >> [kernel boot] >> >> The diff I'm carrying on top of [1] is below. >> >>> Also, does the same card + board combination work in kernel? That should >>> help us point to hardware vs U-boot. >>> >> >> The same card on the same board works without complaints with the kernel >> driver (5.8-rc5 at the moment). Even more strange, the same card a >> different board (IOT2050 Basic, some SoC series, slightly different >> type) does not throw those errors with the same U-Boot. > > Was this card working with an older U-boot version and only failing in > mainline? > >> >> Note that we are still carrying those clock swapping changes in [2]. >> I've also tried to remove it, but it has no impact on this issue. >> > > One more thing to try is to reduce the speed mode to default as we are > already gating frequency > to 25 MHz. Can you modify the sdhci-caps-mask to the following for sdhci1? > > sdhci-caps-mask = <0x7 0x20>; > You'll need to apply this fix for this mask to work: https://patchwork.ozlabs.org/project/uboot/patch/20200723041219.2438-1-faiz_ab...@ti.com/ Thanks, Faiz
[PATCH] mmc: sdhci: Enable high speed conditional on the correspnding bit
The capabilities register has a field to indicate whether the host
supports high speed mode or not. Add high speed host_caps based on
this bit instead of enabling it by default.
Signed-off-by: Faiz Abbas
---
drivers/mmc/sdhci.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 16989dcf05..48d639fe93 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -866,7 +866,10 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct
sdhci_host *host,
if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
cfg->voltages |= host->voltages;
- cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+ if (caps & SDHCI_CAN_DO_HISPD)
+ cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+
+ cfg->host_caps |= MMC_MODE_4BIT;
/* Since Host Controller Version3.0 */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
--
2.17.1
Re: am654_sdhci: mmc fail to send stop cmd
Jan,
On 21/07/20 10:52 pm, Jan Kiszka wrote:
> On 21.07.20 19:03, Faiz Abbas wrote:
>> Jan,
>>
>> On 21/07/20 12:06 pm, Jan Kiszka wrote:
>>> On 21.07.20 01:23, Jaehoon Chung wrote:
>>>> On 7/20/20 10:21 AM, Peng Fan wrote:
>>>>> Hi Jan,
>>>>>
>>>>>> Subject: am654_sdhci: mmc fail to send stop cmd
>>>>>>
>>>>>> Hi all,
>>>>>>
>>>>>> on one device with one specific SD-card (possibly an aging one), I'm
>>>>>> seeing
>>>>>> frequent "mmc fail to send stop cmd" messages, followed by read errors
>>>>>> when loading kernel and dtb. -ETIMEDOUT is returned by mmd_send_cmd.
>>>>>> However, I can always resolve this by simply retrying the stop command
>>>>>> like
>>>>>> this:
>>>>>>
>>>>>> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index
>>>>>> f36d11ddc8..9019d9f2ed 100644
>>>>>> --- a/drivers/mmc/mmc.c
>>>>>> +++ b/drivers/mmc/mmc.c
>>>>>> @@ -406,7 +406,11 @@ static int mmc_read_blocks(struct mmc *mmc, void
>>>>>> *dst, lbaint_t start, #if !defined(CONFIG_SPL_BUILD) ||
>>>>>> defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
>>>>>> pr_err("mmc fail to send stop cmd\n"); #endif
>>>>>> - return 0;
>>>>>> + pr_err("retrying...\n");
>>>>>> + if (mmc_send_cmd(mmc, , NULL)) {
>>>>>> + pr_err("failed again\n");
>>>>>> + return 0;
>>>>>> + }
>>>>>> }
>>>>>> }
>>>>>>
>>>>>>
>>>>>> Hardware is our IOT2050, baseline is today's master (1c4b5038afcc) with
>>>>>> board-enabling and a bunch of patches from your tree [1]. However,
>>>>>> already
>>>>>> 4d6da10ce611 exposes the problem.
>>>>>>
>>>>>> What could cause this?
>>>>>
>>>>> Where the timeout happen in driver?
>>>>>
>>>>> Did you try enlarge the timeout value?
>>>>
>>>> how about adding SDHCI_QUIRK_WAIT_SEND_CMD?
>>>
>>> I tried that already, but the result was even worse, a non-working mmc.
>>>
>>>> And as Peng's comment, It needs to find where return error in driver code.
>>>>
>>>
>>> As written in my other reply:
>>> https://gitlab.denx.de/u-boot/u-boot/-/blob/f12341a9529540113f01989149bbbeb68662a829/drivers/mmc/sdhci.c#L385
>>> Thus, it's reported by the hw.
>>>
>>
>> Its a command timeout for which we cannot program a higher timeout.
>>
>> Can you send a full failure log?
>>
>
> [unrelated fsbl, spl stuff]
>
> U-Boot 2020.07-00883-g4d6da10ce6-dirty (Jul 20 2020 - 06:30:08 +0200)
>
> Model: Siemens IOT2050 Advanced Base Board
> DRAM: 2 GiB
> MMC: sdhci@4f8: 1, sdhci@04FA: 0
> Loading Environment from SPI Flash... SF: Detected w25q128 with page size 256
> Bytes, erase size 64 KiB, total 16 MiB
> OK
> In:serial
> Out: serial
> Err: serial
> Hit any key to stop autoboot: 0
> stat: 18000
> stat: 18000
> stat: 208000
> switch to partitions #0, OK
> mmc1(part 0) is current device
> ** No partition table - mmc 1 **
> switch to partitions #0, OK
> mmc0 is current device
> Scanning mmc 0:1...
> Found U-Boot script /boot/boot.scr
> 784 bytes read in 2 ms (382.8 KiB/s)
> ## Executing script at 8300
> 65329 bytes read in 11 ms (5.7 MiB/s)
> stat: 18000
> mmc fail to send stop cmd, -110
> retrying...
> 17113096 bytes read in 1409 ms (11.6 MiB/s)
> Moving Image from 0x8008 to 0x8020, end=812c
> ## Flattened Device Tree blob at 8200
>Booting using the fdt blob at 0x8200
>Loading Device Tree to fdf0f000, end fdf21f30 ... OK
>
> [kernel boot]
>
> The diff I'm carrying on top of [1] is below.
>
>> Also, does the same card + board combination work in kernel? That should
>> help us point to hardware vs U-boot.
>>
>
> The same card on the same board works without complaints with the kernel
> driver (5.8-rc5 at the moment). Even more strange, the same card a
> different board (IOT2050 Basic, some SoC series, slightly different
> type) does not throw those errors with the same U-Boot.
Was this card working with an older U-boot version and only failing in mainline?
>
> Note that we are still carrying those clock swapping changes in [2].
> I've also tried to remove it, but it has no impact on this issue.
>
One more thing to try is to reduce the speed mode to default as we are already
gating frequency
to 25 MHz. Can you modify the sdhci-caps-mask to the following for sdhci1?
sdhci-caps-mask = <0x7 0x20>;
Thanks,
Faiz
Re: am654_sdhci: mmc fail to send stop cmd
Jan,
On 21/07/20 12:06 pm, Jan Kiszka wrote:
> On 21.07.20 01:23, Jaehoon Chung wrote:
>> On 7/20/20 10:21 AM, Peng Fan wrote:
>>> Hi Jan,
>>>
Subject: am654_sdhci: mmc fail to send stop cmd
Hi all,
on one device with one specific SD-card (possibly an aging one), I'm seeing
frequent "mmc fail to send stop cmd" messages, followed by read errors
when loading kernel and dtb. -ETIMEDOUT is returned by mmd_send_cmd.
However, I can always resolve this by simply retrying the stop command like
this:
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index
f36d11ddc8..9019d9f2ed 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -406,7 +406,11 @@ static int mmc_read_blocks(struct mmc *mmc, void
*dst, lbaint_t start, #if !defined(CONFIG_SPL_BUILD) ||
defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
pr_err("mmc fail to send stop cmd\n"); #endif
- return 0;
+ pr_err("retrying...\n");
+ if (mmc_send_cmd(mmc, , NULL)) {
+ pr_err("failed again\n");
+ return 0;
+ }
}
}
Hardware is our IOT2050, baseline is today's master (1c4b5038afcc) with
board-enabling and a bunch of patches from your tree [1]. However, already
4d6da10ce611 exposes the problem.
What could cause this?
>>>
>>> Where the timeout happen in driver?
>>>
>>> Did you try enlarge the timeout value?
>>
>> how about adding SDHCI_QUIRK_WAIT_SEND_CMD?
>
> I tried that already, but the result was even worse, a non-working mmc.
>
>> And as Peng's comment, It needs to find where return error in driver code.
>>
>
> As written in my other reply:
> https://gitlab.denx.de/u-boot/u-boot/-/blob/f12341a9529540113f01989149bbbeb68662a829/drivers/mmc/sdhci.c#L385
> Thus, it's reported by the hw.
>
Its a command timeout for which we cannot program a higher timeout.
Can you send a full failure log?
Also, does the same card + board combination work in kernel? That should help
us point to hardware vs U-boot.
Thanks,
Faiz
Re: [PATCH] mmc: omap_hsmmc: Set 3.3V for IO voltage on all places
Hi,
On 04/07/20 2:28 am, Pali Rohár wrote:
> In commit commit d2c05f50e12f ("mmc: omap_hsmmc: Set 3.3V for IO voltage")
> was changed 3.0V IO voltage to 3.3V but it was not done on all places in
> omap_hsmmc driver. That commit broke eMMC support on Nokia N900.
>
> This patch fixes that problematic commit and changes 3.0V to 3.3V on all
> remaining places in omap_hsmmc driver.
>
> Fixes: d2c05f50e12f ("mmc: omap_hsmmc: Set 3.3V for IO voltage")
> Signed-off-by: Pali Rohár
> ---
Reviewed-by: Faiz Abbas
Thanks,
Faiz
[PATCH 10/13] configs: am65x_evm: Add support for DFU related configs
Add offset and environment related configs used for booting from DFU. Signed-off-by: Faiz Abbas --- include/configs/am65x_evm.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 19d861d402..5435ef85c7 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -22,6 +22,9 @@ #ifdef CONFIG_TARGET_AM654_A53_EVM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE +\ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +/* Image load address in RAM for DFU boot*/ +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x8100 +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x2 #else /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as @@ -44,6 +47,9 @@ /* Configure R5 SPL post-relocation malloc pool in DDR */ #define CONFIG_SYS_SPL_MALLOC_START0x8400 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +/* Image load address in RAM for DFU boot*/ +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x8008 +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x5000 #endif #ifdef CONFIG_SYS_K3_SPL_ATF @@ -124,8 +130,8 @@ "rootfstype=ubifs root=ubi0:rootfs rw ubi.mtd=ospi.rootfs\0" #define EXTRA_ENV_DFUARGS \ - "dfu_bufsiz=0x2\0" \ DFU_ALT_INFO_MMC\ + DFU_ALT_INFO_RAM\ DFU_ALT_INFO_EMMC \ DFU_ALT_INFO_OSPI -- 2.17.1
[PATCH 11/13] configs: am65x_evm_a53: Enable USB Mass storage and DFU boot modes
Enable configs to facilitate booting from USB Mass Storage devices as well as USB peripheral boot Signed-off-by: Faiz Abbas --- configs/am65x_evm_a53_defconfig | 9 + include/configs/am65x_evm.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index d74a2d0930..6a10e0b97d 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -33,14 +33,20 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y @@ -69,6 +75,7 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y @@ -109,6 +116,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_KEYSTONE=y CONFIG_PHY=y +CONFIG_SPL_PHY=y CONFIG_AM654_PHY=y CONFIG_OMAP_USB2_PHY=y CONFIG_PINCTRL=y @@ -132,6 +140,7 @@ CONFIG_SYSRESET_TI_SCI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 5435ef85c7..9ae8c23c62 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -152,6 +152,8 @@ #define CONFIG_SYS_MMC_ENV_PART1 #endif +#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 + /* Now for the remaining common defines */ #include -- 2.17.1
[PATCH 12/13] configs: Add new config for supporting USB mass storage boot
Because of space constraints, create a new USB defconfig for R5 to faciliate booting from USB mass storage devices Signed-off-by: Faiz Abbas --- configs/am65x_evm_r5_usbmsc_defconfig | 119 ++ 1 file changed, 119 insertions(+) create mode 100644 configs/am65x_evm_r5_usbmsc_defconfig diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig new file mode 100644 index 00..14682c8d27 --- /dev/null +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -0,0 +1,119 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x55000 +CONFIG_SOC_K3_AM6=y +CONFIG_K3_EARLY_CONS=y +CONFIG_TARGET_AM654_R5_EVM=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_ENV_SIZE=0x2 +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_TEXT_BASE=0x41c0 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BLK=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_GPIO=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_K3_AVS0=y +# CONFIG_MMC is not set +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_OMAP_USB2_PHY=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_TPS62360=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -- 2.17.1
[PATCH 13/13] configs: Add defconfig for USB DFU bootmode
Because of space constraints, create a new USB defconfig for R5 to faciliate booting in USB peripheral (DFU) bootmode Signed-off-by: Faiz Abbas --- configs/am65x_evm_r5_usbdfu_defconfig | 119 ++ 1 file changed, 119 insertions(+) create mode 100644 configs/am65x_evm_r5_usbdfu_defconfig diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig new file mode 100644 index 00..2dd671e562 --- /dev/null +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -0,0 +1,119 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x55000 +CONFIG_SOC_K3_AM6=y +CONFIG_K3_EARLY_CONS=y +CONFIG_TARGET_AM654_R5_EVM=y +CONFIG_ENV_SIZE=0x2 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x41c0 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BLK=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_K3_AVS0=y +# CONFIG_MMC is not set +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_OMAP_USB2_PHY=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_TPS62360=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -- 2.17.1
[PATCH 08/13] arm: dts: k3-am654-r5-base-board: Add USB0 nodes
Add USB0 nodes and set them to host mode to support USB host and
peripheral boot modes
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-am654-r5-base-board.dts | 35 +
1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts
b/arch/arm/dts/k3-am654-r5-base-board.dts
index e6b78643c1..d43a4edc71 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -278,3 +278,38 @@
#size-cells = <1>;
};
};
+
+_pmx0 {
+ u-boot,dm-spl;
+ usb0_pins_default: usb0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9)
USB0_DRVVBUS */
+ >;
+ u-boot,dm-spl;
+ };
+};
+
+_0 {
+ status = "okay";
+ u-boot,dm-spl;
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+_phy {
+ status = "okay";
+ u-boot,dm-spl;
+ /delete-property/ clocks;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ dr_mode = "peripheral";
+ u-boot,dm-spl;
+};
+
+_conf {
+ u-boot,dm-spl;
+};
--
2.17.1
[PATCH 09/13] arm: dts: k3-am654-base-board: Add support for USB0 in SPL
Add nodes for USB0 in SPL to enable USB host boot mode
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 27
1 file changed, 27 insertions(+)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index a7e5eb0553..b3d609430c 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -287,6 +287,12 @@
u-boot,dm-spl;
};
+ usb0_pins_default: usb0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9)
USB0_DRVVBUS */
+ >;
+ u-boot,dm-spl;
+ };
};
_pmx1 {
@@ -393,3 +399,24 @@
u-boot,dm-spl;
};
};
+
+_0 {
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+_phy {
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ dr_mode = "peripheral";
+ u-boot,dm-spl;
+};
+
+_conf {
+ u-boot,dm-spl;
+};
--
2.17.1
[PATCH 06/13] arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modes
U-boot only supports either USB host or device mode for a node at a time in dts
To support both host and dfu bootmodes, set "peripheral" as the default dr_mode
but fixup property to "host" if host bootmode is detected
This needs to happen before the dwc3 generic layer binds the usb device to a
host
or device driver. Therefore, open code the configurations in spl_early_init()
and add the fixup after the fdtdec_setup() and before the dm_init_scan()
Also use the same fixup function to set the USB-PCIe Serdes mux to PCIe in both
the
host and device cases. This is required for accessing the interface at USB 2.0
speeds
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/am6_init.c | 68 +++--
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 42d13a39f8..b65860fef3 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -7,6 +7,7 @@
*/
#include
+#include
#include
#include
#include
@@ -17,11 +18,15 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_K3_LOAD_SYSFW
#ifdef CONFIG_TI_SECURE_DEVICE
@@ -119,7 +124,67 @@ void k3_mmc_restart_clock(void)
void k3_mmc_stop_clock(void) {}
void k3_mmc_restart_clock(void) {}
#endif
+#if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
+#define CTRLMMR_SERDES0_CTRL 0x00104080
+#define PCIE_LANE0 0x1
+void fixup_usb_boot(void)
+{
+ int ret;
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_USB:
+ /*
+* If bootmode is Host bootmode, fixup the dr_mode to host
+* before the dwc3 bind takes place
+*/
+ ret = fdt_find_and_setprop((void *)gd->fdt_blob,
+ "/interconnect@10/dwc3@400/usb@1",
+ "dr_mode", "host", 11, 0);
+ if (ret)
+ printf("%s: fdt_find_and_setprop() failed:%d\n",
__func__,
+ ret);
+ /* fallthrough */
+ case BOOT_DEVICE_DFU:
+ /*
+* The serdes mux between PCIe and USB3 needs to be set to PCIe
for
+* accessing the interface at USB 2.0
+*/
+ writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
+ default:
+ ;
+ }
+}
+#endif
+int am6_spl_early_init(void)
+{
+ int ret;
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#ifdef CONFIG_MALLOC_F_ADDR
+ gd->malloc_base = CONFIG_MALLOC_F_ADDR;
+#endif
+ gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN);
+ gd->malloc_ptr = 0;
+#endif
+ ret = fdtdec_setup();
+ if (ret) {
+ printf("fdtdec_setup() returned error %d\n", ret);
+ return ret;
+ }
+
+#if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
+ fixup_usb_boot();
+#endif
+ /* With CONFIG_SPL_OF_PLATDATA, bring in all devices */
+ ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA));
+ if (ret) {
+ printf("dm_init_and_scan() returned error %d\n", ret);
+ return ret;
+ }
+
+ gd->flags |= GD_FLG_SPL_EARLY_INIT;
+
+ return 0;
+}
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
@@ -141,9 +206,8 @@ void board_init_f(ulong dummy)
disable_linefill_optimization();
setup_k3_mpu_regions();
#endif
-
/* Init DM early in-order to invoke system controller */
- spl_early_init();
+ am6_spl_early_init();
#ifdef CONFIG_K3_EARLY_CONS
/*
--
2.17.1
[PATCH 07/13] arm: mach-k3: am6_init: Add support for USB boot mode
Add support for identifying USB host and device boot modes
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/am6_init.c | 5 +
arch/arm/mach-k3/include/mach/am6_hardware.h | 2 ++
arch/arm/mach-k3/include/mach/am6_spl.h | 3 ++-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index b65860fef3..59ab782116 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -357,6 +357,11 @@ static u32 __get_primary_bootmedia(u32 devstat)
CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
if (port == 0x1)
bootmode = BOOT_DEVICE_MMC2;
+ } else if (bootmode == BOOT_DEVICE_DFU) {
+ u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
+ CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
+ if (mode == 0x2)
+ bootmode = BOOT_DEVICE_USB;
}
return bootmode;
diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h
b/arch/arm/mach-k3/include/mach/am6_hardware.h
index a91ef5f735..1908a13f0f 100644
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -25,6 +25,8 @@
#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT 14
#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASKGENMASK(17, 17)
#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 12
+#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT9
+#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9)
#define WKUP_CTRL_MMR0_BASE0x4300
#define MCU_CTRL_MMR0_BASE 0x40f0
diff --git a/arch/arm/mach-k3/include/mach/am6_spl.h
b/arch/arm/mach-k3/include/mach/am6_spl.h
index e97d8143c6..61e0380927 100644
--- a/arch/arm/mach-k3/include/mach/am6_spl.h
+++ b/arch/arm/mach-k3/include/mach/am6_spl.h
@@ -14,7 +14,8 @@
#define BOOT_DEVICE_I2C0x05
#define BOOT_DEVICE_MMC2 0x06
#define BOOT_DEVICE_ETHERNET 0x07
-#define BOOT_DEVICE_USB0x08
+#define BOOT_DEVICE_DFU0x08
+#define BOOT_DEVICE_USB0x408
#define BOOT_DEVICE_PCIE 0x09
#define BOOT_DEVICE_UART 0x0a
#define BOOT_DEVICE_NAND 0x0c
--
2.17.1
[PATCH 01/13] spl: usb: Create an API spl_usb_load()
Create a new API spl_usb_load() that takes the filename as a parameter
instead of taking the default U-boot PAYLOAD_NAME
Signed-off-by: Faiz Abbas
---
common/spl/spl_usb.c | 20 +---
include/spl.h| 14 ++
2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index 08837b38fc..92ae96f66e 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -18,8 +18,9 @@
static int usb_stor_curr_dev = -1; /* current device */
-static int spl_usb_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
+int spl_usb_load(struct spl_image_info *spl_image,
+struct spl_boot_device *bootdev, int partition,
+const char *filename)
{
int err;
struct blk_desc *stor_dev;
@@ -43,13 +44,10 @@ static int spl_usb_load_image(struct spl_image_info
*spl_image,
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() ||
- spl_load_image_fat_os(spl_image, stor_dev,
- CONFIG_SYS_USB_FAT_BOOT_PARTITION))
+ spl_load_image_fat_os(spl_image, stor_dev, partition))
#endif
{
- err = spl_load_image_fat(spl_image, stor_dev,
- CONFIG_SYS_USB_FAT_BOOT_PARTITION,
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ err = spl_load_image_fat(spl_image, stor_dev, partition,
filename);
}
if (err) {
@@ -59,4 +57,12 @@ static int spl_usb_load_image(struct spl_image_info
*spl_image,
return 0;
}
+
+static int spl_usb_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ return spl_usb_load(spl_image, bootdev,
+ CONFIG_SYS_USB_FAT_BOOT_PARTITION,
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+}
SPL_LOAD_IMAGE_METHOD("USB", 0, BOOT_DEVICE_USB, spl_usb_load_image);
diff --git a/include/spl.h b/include/spl.h
index b31c9bb4ab..9c050efcf9 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -503,6 +503,20 @@ int spl_mmc_load(struct spl_image_info *spl_image,
int raw_part,
unsigned long raw_sect);
+/**
+ * spl_usb_load() - Load an image file from USB mass storage
+ *
+ * @param spl_imageImage data filled in by loading process
+ * @param bootdev Describes which device to load from
+ * @param raw_part Fat partition to load from
+ * @param filename Name of file to load
+ *
+ * @return 0 on success, otherwise error code
+ */
+int spl_usb_load(struct spl_image_info *spl_image,
+struct spl_boot_device *bootdev,
+int partition, const char *filename);
+
int spl_ymodem_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev);
--
2.17.1
[PATCH 05/13] arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate config
Gate mmc related system related configurations with DM_MMC to avoid build
errors when MMC is not enabled
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/am6_init.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 74557c4bb7..42d13a39f8 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -90,7 +90,7 @@ static void store_boot_index_from_rom(void)
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
}
-#if defined(CONFIG_K3_LOAD_SYSFW)
+#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
void k3_mmc_stop_clock(void)
{
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
@@ -115,6 +115,9 @@ void k3_mmc_restart_clock(void)
mmc_set_clock(mmc, mmc->saved_clock, false);
}
}
+#else
+void k3_mmc_stop_clock(void) {}
+void k3_mmc_restart_clock(void) {}
#endif
void board_init_f(ulong dummy)
--
2.17.1
[PATCH 04/13] arm: mach-k3: sysfw-loader: Add support to load SYSFW from USB
Add support for loading system firmware from a USB mass storage device
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/sysfw-loader.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 513be09c68..0ebd8c56a7 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -299,6 +299,17 @@ void k3_sysfw_loader(void (*config_pm_pre_callback) (void),
ret = k3_sysfw_dfu_download(sysfw_load_address);
break;
#endif
+#if CONFIG_IS_ENABLED(USB_STORAGE)
+ case BOOT_DEVICE_USB:
+ ret = spl_usb_load(_image, ,
+ CONFIG_SYS_USB_FAT_BOOT_PARTITION,
+#ifdef CONFIG_K3_SYSFW_IMAGE_NAME
+ CONFIG_K3_SYSFW_IMAGE_NAME);
+#else
+ NULL);
+#endif
+#endif
+ break;
default:
panic("Loading SYSFW image from device %u not supported!\n",
bootdev.boot_device);
--
2.17.1
[PATCH 00/13] Add support for USB host and peripheral bootmodes on am65x-idk
The following patches add support for USB mass storage and USB dfu bootmodes on am654x-idk. Because of space constrains and the size of the USB stack, there are two different usbmsc and usbdfu defconfigs for building R5 SPL. Fitting both of these into one defconfig requires some changes in the USB subsystem which is a longer term effort Faiz Abbas (13): spl: usb: Create an API spl_usb_load() spl: usb: Only init usb once armv7R: K3: am654: Use full malloc in SPL both pre and post reloc arm: mach-k3: sysfw-loader: Add support to load SYSFW from USB arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate config arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modes arm: mach-k3: am6_init: Add support for USB boot mode arm: dts: k3-am654-r5-base-board: Add USB0 nodes arm: dts: k3-am654-base-board: Add support for USB0 in SPL configs: am65x_evm: Add support for DFU related configs configs: am65x_evm_a53: Enable USB Mass storage and DFU boot modes configs: Add new config for supporting USB mass storage boot configs: Add defconfig for USB DFU bootmode arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 27 + arch/arm/dts/k3-am654-r5-base-board.dts | 35 ++ arch/arm/mach-k3/am6_init.c | 96 ++- arch/arm/mach-k3/include/mach/am6_hardware.h | 2 + arch/arm/mach-k3/include/mach/am6_spl.h | 3 +- arch/arm/mach-k3/sysfw-loader.c | 11 ++ common/spl/spl_usb.c | 31 +++-- configs/am65x_evm_a53_defconfig | 9 ++ configs/am65x_evm_r5_usbdfu_defconfig| 119 +++ configs/am65x_evm_r5_usbmsc_defconfig| 119 +++ include/configs/am65x_evm.h | 10 +- include/spl.h| 14 +++ 12 files changed, 461 insertions(+), 15 deletions(-) create mode 100644 configs/am65x_evm_r5_usbdfu_defconfig create mode 100644 configs/am65x_evm_r5_usbmsc_defconfig -- 2.17.1
[PATCH 03/13] armv7R: K3: am654: Use full malloc in SPL both pre and post reloc
In order to be able to use things like file system drivers early on in
SPL (before relocation) in a memory-constrained environment when DDR is
not yet available we cannot use the simple malloc scheme which does not
implement the freeing of previously allocated memory blocks. To address
this issue go ahead and enable the use of the full malloc by manually
initializing the required functionality inside board_init_f by creating
a full malloc pool inside the pre-relocation malloc pool.
Signed-off-by: Faiz Abbas
---
arch/arm/mach-k3/am6_init.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 516a02e8a8..74557c4bb7 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -18,7 +18,9 @@
#include
#include
#include
+#include
#include
+#include
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_K3_LOAD_SYSFW
@@ -119,6 +121,8 @@ void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
struct udevice *dev;
+ size_t pool_size;
+ void *pool_addr;
int ret;
#endif
/*
@@ -149,6 +153,20 @@ void board_init_f(ulong dummy)
#endif
#ifdef CONFIG_K3_LOAD_SYSFW
+ /*
+* Initialize an early full malloc environment. Do so by allocating a
+* new malloc area inside the currently active pre-relocation "first"
+* malloc pool of which we use all that's left.
+*/
+ pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
+ pool_addr = malloc(pool_size);
+ if (!pool_addr)
+ panic("ERROR: Can't allocate full malloc pool!\n");
+
+ mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+ debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx
bytes\n",
+ __func__, (unsigned long)pool_addr, (unsigned long)pool_size);
/*
* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
* regardless of the result of pinctrl. Do this without probing the
--
2.17.1
[PATCH 02/13] spl: usb: Only init usb once
usb_init() may be called multiple times for fetching multiple images
from SPL. Skip reinitializing USB if its already been done
Signed-off-by: Faiz Abbas
---
common/spl/spl_usb.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index 92ae96f66e..3648de3492 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -22,11 +22,16 @@ int spl_usb_load(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev, int partition,
const char *filename)
{
- int err;
+ int err = 0;
struct blk_desc *stor_dev;
+ static bool usb_init_pending = true;
+
+ if (usb_init_pending) {
+ usb_stop();
+ err = usb_init();
+ usb_init_pending = false;
+ }
- usb_stop();
- err = usb_init();
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: usb init failed: err - %d\n", __func__, err);
--
2.17.1
Re: Bisected: omap_hsmmc 3.3V IO voltage incompatible with N900 (Was: Re: Bisected: mmc cause reboot loops on N900)
Hi Pali, On 01/07/20 2:02 pm, Pali Rohár wrote: > On Friday 12 June 2020 15:03:06 Pali Rohár wrote: >> On Tuesday 26 May 2020 19:49:54 Pali Rohár wrote: >>> On Thursday 07 May 2020 17:19:38 Pali Rohár wrote: >>>> On Thursday 07 May 2020 19:10:14 Faiz Abbas wrote: >>>>> On 26/04/20 3:59 am, Pali Rohár wrote: >>>>>> On Sunday 26 April 2020 00:20:07 Pali Rohár wrote: >>>>>>> On Saturday 25 April 2020 23:26:15 Pali Rohár wrote: >>>>>>>> Now I tried git bisect and here is problematic commit which caused >>>>>>>> whole >>>>>>>> reboot loop: >>>>>>>> ... >>> >>> Hello Faiz! >>> >>> Now I figured out what is the root cause of second 3.0V vs 3.3V problem. >>> >>> In commit d2c05f50e12f87128597a28146de7092aaa847c3 you forgot to replace >>> one usage of 3.0V by 3.3V. Below is patch which changes also this last >>> one usage. Applying it has same effect on Nokia N900 as reverting >>> that problematic commit d2c05f50e12f87128597a28146de7092aaa847c3: >>> >>> diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c >>> index 8636cd713a..dc26e54795 100644 >>> --- a/drivers/mmc/omap_hsmmc.c >>> +++ b/drivers/mmc/omap_hsmmc.c >>> @@ -840,7 +840,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) >>> omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ? >>> MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180); >>> #else >>> - writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, _base->hctl); >>> + writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V3, _base->hctl); >>> writel(readl(_base->capa) | VS33_3V3SUP | VS18_1V8SUP, >>> _base->capa); >>> #endif >>> >>> So eMMC on real N900 is working fine either with 3.0V or 3.3V. But 3.3V >>> needs to be configured on all places. >> >> Hello! Could you please take a look at this issue and my above fix? > > Ping. Any comment for above issue or my fix? > Sorry I missed this earlier. The fix makes sense to me. I can give my reviewed by to the your fix once you send the patch. Thanks, Faiz
Re: [PATCH 2/7] mmc: zynq_sdhci: Define timing macro's
Hi Ashok,
On 10/06/20 2:48 pm, Ashok Reddy Soma wrote:
> Hi Faiz,
>
>> -Original Message-----
>> From: Faiz Abbas
>> Sent: Wednesday, May 27, 2020 12:28 PM
>> To: Jaehoon Chung ; Michal Simek
>> ; u-boot@lists.denx.de; git
>> Cc: Ashok Reddy Soma ; Heinrich Schuchardt
>> ; Lokesh Vutla ; Marek Vasut
>> ; Masahiro Yamada ;
>> Peng Fan ; Sam Protsenko
>> ; Simon Glass ; Yann
>> Gautier
>> Subject: Re: [PATCH 2/7] mmc: zynq_sdhci: Define timing macro's
>>
>> Michal,
>>
>> On 27/05/20 12:17 pm, Jaehoon Chung wrote:
>>> On 5/22/20 7:44 PM, Michal Simek wrote:
>>>> From: Ashok Reddy Soma
>>>>
>>>> Define timing macro's for all the available speeds of mmc. This is
>>>> done similar to linux. Replace other macro's used in zynq_sdhci.c
>>>> with these new macro's.
>>>
>>> Even though it's similar to linux, does it need to add new macro?
>>>
>>>>
>>>> Signed-off-by: Ashok Reddy Soma
>>>> Signed-off-by: Michal Simek
>>>> ---
>>>>
>>>> drivers/mmc/zynq_sdhci.c | 24 +++-
>>>> include/mmc.h| 13 +
>>>> 2 files changed, 24 insertions(+), 13 deletions(-)
>>>>
>>>> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
>>>> index 94c69cf1c1bd..02583f76f936 100644
>>>> --- a/drivers/mmc/zynq_sdhci.c
>>>> +++ b/drivers/mmc/zynq_sdhci.c
>>>> @@ -32,20 +32,18 @@ struct arasan_sdhci_priv { };
>>>>
>>>> #if defined(CONFIG_ARCH_ZYNQMP)
>>>> -#define MMC_HS200_BUS_SPEED 5
>>>> -
>>>> static const u8 mode2timing[] = {
>>>> - [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
>>>> - [MMC_HS] = HIGH_SPEED_BUS_SPEED,
>>>> - [SD_HS] = HIGH_SPEED_BUS_SPEED,
>>>> - [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
>>>> - [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
>>>> - [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
>>>> - [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
>>>> - [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
>>>> - [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
>>>> - [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
>>>> - [MMC_HS_200] = MMC_HS200_BUS_SPEED,
>>>> + [MMC_LEGACY] = MMC_TIMING_LEGACY,
>>>> + [MMC_HS] = MMC_TIMING_MMC_HS,
>>>> + [SD_HS] = MMC_TIMING_SD_HS,
>>>> + [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
>>>> + [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
>>>> + [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
>>>> + [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
>>>> + [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
>>>> + [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
>>>> + [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
>>>> + [MMC_HS_200] = MMC_TIMING_MMC_HS200,
>>>> };
>>>>
>>>> #define SDHCI_TUNING_LOOP_COUNT 40
>>>> diff --git a/include/mmc.h b/include/mmc.h index
>>>> 82562193cc48..05d8ab8eeac6 100644
>>>> --- a/include/mmc.h
>>>> +++ b/include/mmc.h
>>>> @@ -360,6 +360,19 @@ enum mmc_voltage {
>>>> #define MMC_NUM_BOOT_PARTITION2
>>>> #define MMC_PART_RPMB 3 /* RPMB partition number */
>>>>
>>>> +/* timing specification used */
>>>> +#define MMC_TIMING_LEGACY 0
>>>> +#define MMC_TIMING_MMC_HS 1
>>>> +#define MMC_TIMING_SD_HS 2
>>>> +#define MMC_TIMING_UHS_SDR12 3
>>>> +#define MMC_TIMING_UHS_SDR25 4
>>>> +#define MMC_TIMING_UHS_SDR50 5
>>>> +#define MMC_TIMING_UHS_SDR104 6
>>>> +#define MMC_TIMING_UHS_DDR50 7
>>>> +#define MMC_TIMING_MMC_DDR52 8
>>>> +#define MMC_TIMING_MMC_HS200 9
>>>> +#define MMC_TIMING_MMC_HS400 10
>>>> +
>>>> /* Driver model support */
>>>>
>>
>> There's already an
>>
>> enum bus_mode {
>> MMC_LEGACY,
>> MMC_HS,
>> SD_HS,
>> MMC_HS_52,
>> MMC_DDR_52,
>> UHS_SDR12,
>> UHS_SDR25,
>> UHS_SDR50,
>> UHS_DDR50,
>> UHS_SDR104,
>> MMC_HS_200,
>> MMC_HS_400,
>> MMC_HS_400_ES,
>> MMC_MODES_END
>> };
>>
>> in this file. Thats what the mmc core uses to represent timing. Please use
>> the
>> same symbols.
>
> The enum and macro differ in values. For example UHS_SDR12 macro value is 3
> whereas enum will be 5.
> This is a problem when accessing below arrays. I take these reference values
> from linux driver.
> If the values change in future, it will be easy for u-boot driver to just
> copy and paste from linux driver if we use macro's.
>
> /* Default settings for ZynqMP Clock Phases */
> const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0};
> const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0};
>
> I also see that xenon_sdhci.c has defined these macro's locally.
> https://gitlab.denx.de/u-boot/u-boot/-/blob/master/drivers/mmc/xenon_sdhci.c#L98
>
> So I have added these macro's in include/mmc.h for everyone's use.
>
A better approach would be to try to bring the U-boot macro in line with kernel.
That way more drivers can take advantage of the similarities. Adding extra
symbols
just confuses people about which ones are being used in core and which ones in
your driver.
Thanks,
Faiz
