Re: [PATCH] net: uclass: Save ethernet MAC address when generated

[Grygorii Strashko]

On 02/11/2021 12:27, Michal Simek wrote:



On 11/2/21 10:00, Michael Walle wrote:

On Fri, Oct 29, 2021 at 2:14 PM Michal Simek  wrote:


When MAC address is randomly generated it should be also saved to
variables. This step is there when MAC address is passed via pdata but not
when it is randomly generated.

Signed-off-by: Michal Simek 
---

  net/eth-uclass.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 0da0e85be031..58c308f33276 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -583,6 +583,8 @@ static int eth_post_probe(struct udevice *dev)
 net_random_ethaddr(pdata->enetaddr);
 printf("\nWarning: %s (eth%d) using random MAC address - 
%pM\n",
    dev->name, dev_seq(dev), pdata->enetaddr);
+   eth_env_set_enetaddr_by_index("eth", dev_seq(dev),
+ pdata->enetaddr);
  #else
 printf("\nError: %s address not set.\n",
    dev->name);
--
2.33.1


Reviewed-by: Ramon Fried 


Please note, that this will change behavior. Before this commit, the
random mac address was local to u-boot (at least for most network drivers).
After this commit, it will also be communicated to linux.

I'm not sure what to think of this. At the very least, this should be
documented in the commit message and in the Kconfig help text.


Thanks for bringing this up. I have no issue that this address is being 
propagated to Linux but others can feel this as an issue.
I can definitely extend commit message to say it.


Propagating random MAC to Linux might be not a good idea as Linux will silently 
use it while in many cases it means that smth is wrong,
and message like "Driver uses random MAC!" helps narrow down issues earlier.
For example, we occasionally copy-pasted wrong mac in DT and detected this only 
after some time when started connecting
similar boards to each other :(
Also, Linux may have it's own way to retrieve MAC if not provided by u-boot.

Wouldn't be enough to just print MAC console when random is used?



I found this via net list command where you can see controllers but you can't 
see their mac addresses which is IMHO wrong.



--
Best regards,
grygorii

Re: [PATCH v3 2/5] arm/dts: k3-j7200-r5-common: Add pmic lp876441 node

[Grygorii Strashko]

On 14/07/2021 23:52, Gowtham Tammana wrote:

Add pmic lp876411 node needed for CPU AVS support.

Signed-off-by: Gowtham Tammana 
---
  .../arm/dts/k3-j7200-r5-common-proc-board.dts | 26 +++
  1 file changed, 26 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts 
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 8dc1809979..6ef92145ef 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -239,6 +239,32 @@
ti,driver-strength-ohm = <50>;
  };
  
+_i2c0 {

+   u-boot,dm-spl;
+   lp876441: lp876441@4c {
+   compatible = "ti,lp876441";
+   reg = <0x4c>;
+   u-boot,dm-spl;
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c0_pins_default>;
+   clock-frequency = <40>;


pls, send follow up fix to place pimux and freq props correctly in i2c node


+
+   regulators: regulators {
+   u-boot,dm-spl;
+   buck1_reg: buck1 {
+   /*VDD_CPU_AVS_REG*/
+   regulator-name = "buck1";
+   regulator-min-microvolt = <80>;
+   regulator-max-microvolt = <125>;
+   regulator-always-on;
+   regulator-boot-on;
+   u-boot,dm-spl;
+   };
+   };
+   };
+
+};
+
  _i2c0 {
pinctrl-names = "default";
pinctrl-0 = <_i2c0_pins_default>;



--
Best regards,
grygorii

Re: [PATCH v2 00/30] Add DM support for omap PWM backlight

[Grygorii Strashko]

On 17/09/2020 22:23, Dario Binacchi wrote:

Hi Grygorii,


Il 17/09/2020 08:57 Grygorii Strashko  ha scritto:

  
Hi Dario,


On 06/09/2020 15:08, Dario Binacchi wrote:


The series was born from the need to manage the PWM backlight of the
display connected to my beaglebone board. To hit the target, I had to
develop drivers for PWM management which in turn relied on drivers for
managing timers and clocks, all developed according to the driver model.
My intention was to use the SoC-specific API only at strictly necessary
points in the code. My previous patches for migrating the AM335x display
driver to the driver model had required the implementation of additional
functions outside the concerns of the driver, (settings for dividing the
pixel clock rate, configuring the display DPLL rate, ) not being
able to use the API of the related clock drivers. This series shouldn't
have repeated the same kind of mistake. Furthermore, I also wanted to fix
that kind of forced choice. Almost everything should have been accessible
via the driver model API. In the series there are also some patches that
could be submitted separately, but which I have however inserted to avoid
applying future patches to incorporate them.
With this last consideration, I hope I have convincingly justified the
large number of patches in the series.

The patch enabling address translation into a CPU physical address from
device-tree even in case of crossing levels with #size-cells = <0>, is
crucial for the series. The previous implementation was unable to
perform the address translation required by the am33xx device tree.
I tried to apply in a conservative way as few changes as possible and
to verify the execution of all the tests already developed, as well as
the new ones I added for the new feature.


Thank you for you patches.

In my opinion it's better if you split this series as it is
- too big
- modifies different subsystems
- contains as fixes as new features


I agree with you.
I've been thinking about it for some time too.
Hope in the weekend. Anyway, next patches upload
will split this series.


I'd recommend to separate
- fixes first, like
clk: remove a redundant header
arch: sandbox: fix typo in clk.h
fdt: translate address if #size-cells = <0>
omap: timer: fix the rate setting
dm: core: add a function to decode display timings
..
- clk patches
- pwm/backlight patches
- video: omap: panel patches

And I'd recommend not to port device tree bindings in u-boot as it's just 
duplication of
kernel binding which u-boot shell follow.
Just providing links to Kernel binding in commit messages should be enough.


I have already added device-tree bindings in patches that have been accepted. 
No one has ever
pointed out what you recommend to me. Also, the doc/device-tree-bindings 
directory seems very
crowded. I have read that device-tree bindings are often evolving and I think 
that not copying
them in uboot does not favor their consultation. Also I wonder if it is enough 
to report in the
commit message the kernel file path or to refer to a particular file version by 
specifying the
commit sha1. Can you help me figure out what to do?



It depends, if you porting code to u-boot it's most probably that kernel bindings 
evolved already (>1 commit).
In such case link on file may be preferable, i think.
if it's new driver which just has been accepted to the Kernel with bindings - 
it could be sha1.
Note. Common practice for u-boot is to accept new drivers only after their 
binding accepted in Linux Kernel.

--
Best regards,
grygorii

Re: [PATCH] dma: ti: k3-udma: Reset the channel during release

[Grygorii Strashko]

On 17/09/2020 17:41, Vignesh Raghavendra wrote:

Reset the channel completely during channel release in order to clear
teardown bit before handing over to next user or jumping to Linux.

Signed-off-by: Vignesh Raghavendra 
---
  drivers/dma/ti/k3-udma.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 57d9fbfabb..94216045cc 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -1134,7 +1134,9 @@ err_free_res:
  
  static void udma_free_chan_resources(struct udma_chan *uc)

  {
-   /* Some configuration to UDMA-P channel: disable, reset, whatever */
+   /* Hard reset UDMA channel */
+   udma_stop_hard(uc);
+   udma_reset_counters(uc);
  
  	/* Release PSI-L pairing */

udma_navss_psil_unpair(uc->ud, uc->config.src_thread, 
uc->config.dst_thread);



Thank you.
Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH v2 00/30] Add DM support for omap PWM backlight

[Grygorii Strashko]

Hi Dario,

On 06/09/2020 15:08, Dario Binacchi wrote:


The series was born from the need to manage the PWM backlight of the
display connected to my beaglebone board. To hit the target, I had to
develop drivers for PWM management which in turn relied on drivers for
managing timers and clocks, all developed according to the driver model.
My intention was to use the SoC-specific API only at strictly necessary
points in the code. My previous patches for migrating the AM335x display
driver to the driver model had required the implementation of additional
functions outside the concerns of the driver, (settings for dividing the
pixel clock rate, configuring the display DPLL rate, ) not being
able to use the API of the related clock drivers. This series shouldn't
have repeated the same kind of mistake. Furthermore, I also wanted to fix
that kind of forced choice. Almost everything should have been accessible
via the driver model API. In the series there are also some patches that
could be submitted separately, but which I have however inserted to avoid
applying future patches to incorporate them.
With this last consideration, I hope I have convincingly justified the
large number of patches in the series.

The patch enabling address translation into a CPU physical address from
device-tree even in case of crossing levels with #size-cells = <0>, is
crucial for the series. The previous implementation was unable to
perform the address translation required by the am33xx device tree.
I tried to apply in a conservative way as few changes as possible and
to verify the execution of all the tests already developed, as well as
the new ones I added for the new feature.


Thank you for you patches.

In my opinion it's better if you split this series as it is
- too big
- modifies different subsystems
- contains as fixes as new features

I'd recommend to separate
- fixes first, like
  clk: remove a redundant header
  arch: sandbox: fix typo in clk.h
  fdt: translate address if #size-cells = <0>
  omap: timer: fix the rate setting
  dm: core: add a function to decode display timings
  ..
- clk patches
- pwm/backlight patches
- video: omap: panel patches

And I'd recommend not to port device tree bindings in u-boot as it's just 
duplication of
kernel binding which u-boot shell follow.
Just providing links to Kernel binding in commit messages should be enough.



Changes in v2:
- Add the clk_ prefix to the divider functions.
- Add kernel-doc comments to the exported functions.
- Merged to patch [09/31] clk: ti: refactor mux and divider clock
   drivers.
- Remove the 'ti_am3_prcm_clocks' driver. Handle 'prcm_clocks' node in
   the 'ti_am3_prcm' driver.
- Update the commit message.
- Fix a missing line in the commit message.
- Add dm_flags to global_data structure and GD_DM_FLG_SIZE_CELLS_0 macro
   to test without recompiling.
- Update the OF_CHECK_COUNTS macro in order to have just one
   #define by bringing the GD_DM_FLG_SIZE_CELLS_0 into the expression.
- Lower-case the 0xC019 hex number.
- Remove the 'ti_am3_scm_clocks' driver. Handle 'scm_clocks' node in
   the 'ti_am3_scm' driver.
- Update the commit message.

Dario Binacchi (30):
   clk: remove a redundant header
   clk: export generic routines
   arch: sandbox: fix typo in clk.h
   clk: add clk_round_rate()
   clk: ti: add mux clock driver
   arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro
   clk: ti: am33xx: add DPLL clock drivers
   clk: ti: add divider clock driver
   clk: ti: add gate clock driver
   ti: am33xx: fix do_enable_clocks() to accept NULL parameters
   clk: ti: add support for clkctrl clocks
   clk: ti: move drivers to 'ti' directory
   clk: ti: omap4: add clock manager driver
   clk: ti: am335x: add clock manager driver
   fdt: translate address if #size-cells = <0>
   omap: timer: fix the rate setting
   misc: am33xx: add control module driver
   pwm: ti: am33xx: add enhanced pwm driver
   pwm: ti: am33xx: add subsystem driver
   video: backlight: fix pwm's duty cycle calculation
   video: backlight: fix pwm data structure description
   dm: core: improve uclass_get_device_by_phandle_id() description
   gpio: fix gpio_request_by_name() description
   dm: core: add a function to decode display timings
   video: omap: add panel driver
   video: omap: enable LCD clock domain through DM API
   video: omap: set LCD clock rate through DM API
   video: omap: split the legacy code from the DM code
   video: omap: move drivers to 'ti' directory
   board: ti: am335x-ice: get CDCE913 clock device




--
Best regards,
grygorii

Re: [PATCH 0/6] J2700: Enable various peripherals

[Grygorii Strashko]

On 06/08/2020 21:56, Vignesh Raghavendra wrote:

Enable USB, HyperFlasha and CPSW on J7200 SoC

Based on top of https://patchwork.ozlabs.org/project/uboot/list/?series=194305

Vignesh Raghavendra (6):
   arm: dts: k3-j7200: Add USB related DT entries
   board: ti: j721e: Add support for HyperFlash detection
   ARM: dts: k3-j7200: Add wkup gpio node
   ARM: dts: k3-j7200: Add HyperBus and HyperFlash nodes
   ARM: dts: k3-j7200-mcu-wakeup: Add CPSW2G support
   arm: dts: k3-j7200-common-proc-board: Enable CPSW2G port

  .../k3-j7200-common-proc-board-u-boot.dtsi|  29 
  arch/arm/dts/k3-j7200-common-proc-board.dts   |  72 
  arch/arm/dts/k3-j7200-main.dtsi   |  30 
  arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 155 ++
  .../arm/dts/k3-j7200-r5-common-proc-board.dts |  18 ++
  arch/arm/dts/k3-j7200-som-p0.dtsi |  33 
  arch/arm/dts/k3-j7200.dtsi|   6 +-
  board/ti/j721e/evm.c  |  30 
  8 files changed, 371 insertions(+), 2 deletions(-)



Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH 07/18] arm: mach-k3: j721e: Add detection for j721e

[Grygorii Strashko]

On 23/07/2020 11:47, Lokesh Vutla wrote:

Add an api soc_is_j721e(), and use it to enable certain functionality
that is available only on j721e.

Signed-off-by: Lokesh Vutla 
Signed-off-by: Suman Anna 
---
  arch/arm/mach-k3/common.c | 10 ++
  arch/arm/mach-k3/include/mach/sys_proto.h |  2 ++
  arch/arm/mach-k3/j721e_init.c |  3 +++
  3 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index eb72451d06..aec6c600b9 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -355,6 +355,16 @@ int print_cpuinfo(void)
  }
  #endif
  
+bool soc_is_j721e(void)

+{
+   u32 soc;
+
+   soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
+   JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
+
+   return soc == J721E;
+}


Shouldn't it be done using UCLASS_SOC introduce by Dave Gerlach 


https://patchwork.ozlabs.org/project/uboot/cover/20200716044004.6014-1-d-gerl...@ti.com/


+
  #ifdef CONFIG_ARM64
  void board_prep_linux(bootm_headers_t *images)
  {
diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h 
b/arch/arm/mach-k3/include/mach/sys_proto.h
index 3c825aa3d1..48b11178c3 100644
--- a/arch/arm/mach-k3/include/mach/sys_proto.h
+++ b/arch/arm/mach-k3/include/mach/sys_proto.h
@@ -16,4 +16,6 @@ int do_board_detect(void);
  void release_resources_for_core_shutdown(void);
  int fdt_disable_node(void *blob, char *node_path);
  
+bool soc_is_j721e(void);

+
  #endif
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 461a9d7f8f..3b15da2d7c 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -361,6 +361,9 @@ void start_non_linux_remote_cores(void)
int size = 0, ret;
u32 loadaddr = 0;
  
+	if (!soc_is_j721e())

+   return;
+
size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
 );
if (size <= 0)



--
Best regards,
grygorii

Re: [PATCH v2 0/9] Introduce UCLASS_SOC

[Grygorii Strashko]

On 16/07/2020 07:39, Dave Gerlach wrote:

Hi,

This is v2 of the series to introduce UCLASS_SOC to be used for SOC
identification and attribute matching based on SoC ID info. The first
version of this series can be found at [1].

Biggest change is the addition of a patch to add documentation for the
SOC ID framework as requested by several folks.  Otherwise, several
comments were addressed in the patch to introduce the UCLASS_SOC
implementation:

* Renamed soc_device_attribute to soc_attr.
* Added inline docs for same struct.
* Moved ifdef for CONFIG_SOC_DEVICE to only include functions
* Documented NULL return possiblity for soc_device_match.

And a change to SOC Revision macro naming in the soc_ti_k3 driver
to use SR consistently instead of PG.

Regards,
Dave

[1] https://lists.denx.de/pipermail/u-boot/2020-June/418109.html

Dave Gerlach (9):
   doc: Add new doc for soc ID driver model
   dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matching
   test: Add tests for SOC uclass
   dm: soc: Introduce soc_ti_k3 driver for TI K3 SoCs
   arm: dts: k3-am65-wakeup: Introduce chipid node
   arm: dts: k3-j721e-mcu-wakeup: Introduce chipid node
   configs: am65x_evm: Enable CONFIG_SOC_DEVICE and
 CONFIG_SOC_DEVICE_TI_K3
   configs: j721e_evm: Enable CONFIG_SOC_DEVICE and
 CONFIG_SOC_DEVICE_TI_K3
   arm: mach-k3: Use SOC driver for device identification

  arch/arm/dts/k3-am65-wakeup.dtsi  |   5 +
  arch/arm/dts/k3-am654-base-board-u-boot.dtsi  |   4 +
  .../k3-j721e-common-proc-board-u-boot.dtsi|   4 +
  arch/arm/dts/k3-j721e-mcu-wakeup.dtsi |   5 +
  arch/arm/mach-k3/common.c |  48 +++---
  arch/arm/mach-k3/common.h |   6 -
  arch/arm/mach-k3/include/mach/hardware.h  |   1 -
  arch/sandbox/dts/test.dts |   4 +
  configs/am65x_evm_a53_defconfig   |   2 +
  configs/am65x_evm_r5_defconfig|   2 +
  configs/am65x_hs_evm_a53_defconfig|   2 +
  configs/am65x_hs_evm_r5_defconfig |   2 +
  configs/j721e_evm_a72_defconfig   |   2 +
  configs/j721e_evm_r5_defconfig|   2 +
  configs/j721e_hs_evm_a72_defconfig|   2 +
  configs/j721e_hs_evm_r5_defconfig |   2 +
  configs/sandbox64_defconfig   |   1 +
  configs/sandbox_defconfig |   1 +
  configs/sandbox_flattree_defconfig|   1 +
  configs/sandbox_spl_defconfig |   1 +
  doc/driver-model/index.rst|   1 +
  doc/driver-model/soc-framework.rst|  68 
  drivers/soc/Kconfig   |  16 ++
  drivers/soc/Makefile  |   3 +
  drivers/soc/soc-uclass.c  | 102 
  drivers/soc/soc_sandbox.c |  56 +++
  drivers/soc/soc_ti_k3.c   | 124 +++
  include/dm/uclass-id.h|   1 +
  include/soc.h | 145 ++
  test/dm/Makefile  |   1 +
  test/dm/soc.c | 120 +++
  31 files changed, 698 insertions(+), 36 deletions(-)
  create mode 100644 doc/driver-model/soc-framework.rst
  create mode 100644 drivers/soc/soc-uclass.c
  create mode 100644 drivers/soc/soc_sandbox.c
  create mode 100644 drivers/soc/soc_ti_k3.c
  create mode 100644 include/soc.h
  create mode 100644 test/dm/soc.c



Thank you.
Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH 0/5] TI: AM654/J721e: Sync CPSW DT node from kernel

[Grygorii Strashko]

On 06/07/2020 11:06, Vignesh Raghavendra wrote:

Make necessary driver changes to sync DT nodes from kernel.
Depends on [1]

Due to the dependencies, I would like this entire series to be merged via TI
tree.

Tested on AM654 and J721e boards

[1]  https://patchwork.ozlabs.org/project/uboot/list/?series=186589


Vignesh Raghavendra (5):
   net: ti: am65-cpsw-nuss: Remove dead code
   net: ti: am65-cpsw-nuss: Set ALE default thread enable
   net: ti: am65-cpsw-nuss: Update driver to use kernel DT
   arm: dts: k3-j721e: Sync CPSW DT node from kernel
   arm: dts: k3-am65: Sync CPSW DT node from kernel

  arch/arm/dts/k3-am65-mcu.dtsi | 84 +++
  arch/arm/dts/k3-am654-base-board-u-boot.dtsi  | 54 +---
  .../k3-j721e-common-proc-board-u-boot.dtsi| 74 +---
  arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 74 
  drivers/net/ti/am65-cpsw-nuss.c   | 15 ++--
  5 files changed, 167 insertions(+), 134 deletions(-)



Thank you - minor coment.
Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH 4/5] arm: dts: k3-j721e: Sync CPSW DT node from kernel

[Grygorii Strashko]

On 06/07/2020 11:06, Vignesh Raghavendra wrote:

Sync CPSW DT node from Kernel and move it out of -u-boot.dtsi file.

Signed-off-by: Vignesh Raghavendra 
---
  .../k3-j721e-common-proc-board-u-boot.dtsi| 74 +--
  arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 74 +++
  2 files changed, 75 insertions(+), 73 deletions(-)

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 6273133303..6e748bfebb 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -31,20 +31,6 @@
u-boot,dm-spl;
};
  
-	mcu_conf: scm_conf@40f0 {

-   compatible = "syscon", "simple-mfd";
-   reg = <0x0 0x40f0 0x0 0x2>;
-   #address-cells = <1>;
-   #size-cells = <1>;
-   ranges = <0x0 0x0 0x40f0 0x2>;
-
-   phy_sel: cpsw-phy-sel@4040 {
-   compatible = "ti,am654-cpsw-phy-sel";
-   reg = <0x4040 0x4>;
-   reg-names = "gmii-sel";
-   };
-   };
-
mcu_navss {
u-boot,dm-spl;
  
@@ -56,65 +42,6 @@

u-boot,dm-spl;
};
};
-
-   mcu_cpsw: ethernet@04600 {
-   compatible = "ti,j721e-cpsw-nuss";
-   #address-cells = <2>;
-   #size-cells = <2>;
-   reg = <0x0 0x4600 0x0 0x20>;
-   reg-names = "cpsw_nuss";
-   ranges;
-   dma-coherent;
-   clocks = <_clks 18 22>;
-   clock-names = "fck";
-   power-domains = <_pds 18 TI_SCI_PD_EXCLUSIVE>;
-   cpsw-phy-sel = <_sel>;
-
-   dmas = <_udmap 0xf000>,
-  <_udmap 0xf001>,
-  <_udmap 0xf002>,
-  <_udmap 0xf003>,
-  <_udmap 0xf004>,
-  <_udmap 0xf005>,
-  <_udmap 0xf006>,
-  <_udmap 0xf007>,
-  <_udmap 0x7000>;
-   dma-names = "tx0", "tx1", "tx2", "tx3",
-   "tx4", "tx5", "tx6", "tx7",
-   "rx";
-
-   ports {
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   host: host@0 {
-   reg = <0>;
-   ti,label = "host";
-   };
-
-   cpsw_port1: port@1 {
-   reg = <1>;
-   ti,mac-only;
-   ti,label = "port1";
-   ti,syscon-efuse = <_conf 0x200>;
-   };
-   };
-
-   davinci_mdio: mdio {
-   #address-cells = <1>;
-   #size-cells = <0>;
-   bus_freq = <100>;
-   };
-
-   cpts {
-   clocks = <_clks 18 2>;
-   clock-names = "cpts";
-   interrupts-extended = < GIC_SPI 858 
IRQ_TYPE_LEVEL_HIGH>;
-   interrupt-names = "cpts";
-   ti,cpts-ext-ts-inputs = <4>;
-   ti,cpts-periodic-outputs = <2>;
-   };
-   };
  };
  
  _proxy_main {

@@ -224,6 +151,7 @@
reg = <0x0 0x4600 0x0 0x20>,
  <0x0 0x40f00200 0x0 0x2>;
reg-names = "cpsw_nuss", "mac_efuse";
+   /delete-property/ ranges;
  
  	cpsw-phy-sel@40f04040 {

compatible = "ti,am654-cpsw-phy-sel";
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi 
b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 70d5bcaa72..e6c99ab698 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -35,6 +35,20 @@
};
};
  
+	mcu_conf: syscon@40f0 {

+   compatible = "syscon", "simple-mfd";
+   reg = <0x0 0x40f0 0x0 0x2>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0x0 0x0 0x40f0 0x2>;
+
+   phy_gmii_sel: phy@4040 {
+   compatible = "ti,am654-phy-gmii-sel";
+   reg = <0x4040 0x4>;
+   #phy-cells = <1>;
+   };
+   };
+
wkup_pmx0: pinmux@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
@@ -242,4 +256,64 @@
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
};
+
+   mcu_cpsw: ethernet@4600 {
+   compatible = "ti,j721e-cpsw-nuss";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   reg = <0x0 0x4600 

Re: [PATCH 0/6] TI: AM654/j721e: Ringacc and UDMA updates

[Grygorii Strashko]

On 06/07/2020 10:56, Vignesh Raghavendra wrote:

Align Ringacc and UDMA driver with kernel updates.

Depends on [1]

[1] https://patchwork.ozlabs.org/project/uboot/list/?series=186589

Vignesh Raghavendra (6):
   soc: ti: k3-ringacc: Move state tracking variables under a struct
   soc: ti: k3-ringacc: Add an API to request pair of rings
   soc: ti: k3-ringacc: Separate soc specific initialization
   dma: ti: k3-udma: Introduce udma_chan_config struct
   dma: ti: k3-udma: Move RX descriptor ring entries to rflow struct
   dma: ti: k3-udma: Switch to k3_ringacc_request_rings_pair

  drivers/dma/ti/k3-udma.c| 281 
  drivers/soc/ti/k3-navss-ringacc.c   | 161 +-
  include/linux/soc/ti/k3-navss-ringacc.h |   4 +
  3 files changed, 254 insertions(+), 192 deletions(-)



Thank you.
Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH 0/3] AM654/J721e: Sync UDMA bindings

[Grygorii Strashko]

On 22/06/2020 09:55, Vignesh Raghavendra wrote:

UDMA DT bindings have deviated from kernel's DT for AM654 and J721e.
This series updates UDMA driver and sync DT bindings

Tested OSPI and CPSW on AM654 and J721e after the changes

Lokesh,

Patch 2/3 and 3/3 should ideally go as a single patch to avoid breaking of
functionality but, that makes harder to review. Feel free to squash them
while merging or I can repost with 2/3 and 3/3 squashed


I think it should be ok, but It  has to be mentioned in Patch 2 description
that it will break boot.



Vignesh Raghavendra (3):
   dma: ti: Add static PSIL endpoint information
   dma: ti: k3-udma: Update driver to use static endpoint Data
   arm: dts: k3-am65/j721e: Sync DMA DT bindings from Kernel DT

  arch/arm/dts/k3-am65-mcu.dtsi |  44 
  arch/arm/dts/k3-am654-base-board-u-boot.dtsi  | 121 +-
  .../k3-j721e-common-proc-board-u-boot.dtsi| 118 +-
  arch/arm/dts/k3-j721e-mcu-wakeup.dtsi |  43 
  drivers/dma/ti/Kconfig|   4 +
  drivers/dma/ti/Makefile   |   1 +
  drivers/dma/ti/k3-psil-am654.c| 175 ++
  drivers/dma/ti/k3-psil-j721e.c| 222 ++
  drivers/dma/ti/k3-psil-priv.h |  43 
  drivers/dma/ti/k3-psil.c  |  42 
  drivers/dma/ti/k3-psil.h  |  67 ++
  drivers/dma/ti/k3-udma.c  | 145 
  include/dt-bindings/dma/k3-udma.h |  31 ---
  13 files changed, 768 insertions(+), 288 deletions(-)
  create mode 100644 drivers/dma/ti/k3-psil-am654.c
  create mode 100644 drivers/dma/ti/k3-psil-j721e.c
  create mode 100644 drivers/dma/ti/k3-psil-priv.h
  create mode 100644 drivers/dma/ti/k3-psil.c
  create mode 100644 drivers/dma/ti/k3-psil.h
  delete mode 100644 include/dt-bindings/dma/k3-udma.h



Thank you.
Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH] board: ti: am335x_evm: Remove duplicate setting of bd_ram_ofs member

[Grygorii Strashko]

On 04/06/2020 23:01, Tom Rini wrote:

With clang we get a report that we are setting this member twice.
Fortunately it is to the same value, so drop the hard-coded value line.

Signed-off-by: Tom Rini 
---
  board/ti/am335x/board.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 4199bee2e64a..123ccaac44e5 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -912,7 +912,6 @@ struct cpsw_platform_data am335_eth_data = {
.slaves = 2,
.slave_data = slave_data,
.ale_entries= 1024,
-   .bd_ram_ofs = 0x2000,
.mac_control= 0x20,
.active_slave   = 0,
.mdio_base  = 0x4a101000,



Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH] net: cpsw: Add __maybe_unused to generated inlines

[Grygorii Strashko]

On 04/06/2020 23:05, Tom Rini wrote:

We generate a number of helper inline functions to make accesses easier.
However not all permutations of each function will be used and clang
will warn about unused ones.  Decorate all of them with __maybe_unused
because of this.

Cc: Lokesh Vutla 
Signed-off-by: Tom Rini 
---
  drivers/net/ti/cpsw.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 95761fffc0f0..9d4332f45048 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -17,6 +17,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -247,11 +248,11 @@ static inline void cpsw_ale_set_field(u32 *ale_entry, u32 
start, u32 bits,
  }
  
  #define DEFINE_ALE_FIELD(name, start, bits)\

-static inline int cpsw_ale_get_##name(u32 *ale_entry)  \
+static inline int __maybe_unused cpsw_ale_get_##name(u32 *ale_entry)   \
  { \
return cpsw_ale_get_field(ale_entry, start, bits);  \
  } \
-static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)  \
+static inline void __maybe_unused cpsw_ale_set_##name(u32 *ale_entry, u32 
value)   \
  { \
cpsw_ale_set_field(ale_entry, start, bits, value);  \
  }



Thank you.
Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH v4 0/5] TI Ethernet PHY changes

[Grygorii Strashko]

On 05/05/2020 00:14, Dan Murphy wrote:

Hello

The addition of the DP83867 driver to uboot was done in a generic way that
made it a bit difficult to bring in new PHY drivers.  The difficulty came in the
config flags and the phy_init function.  The change is to make the flags and
init for the DP83867 more specific to the DP83867 device to make way to add
more TI PHYs to uBoot.

In addition the DP8382X PHY is a generic PHY driver that does not need any
special handling to establish a link.  Customers have requested that at the very
least there be a way to know if the PHY attached is the PHY that is connected
as "Generic PHY" is not really descriptive.  These patches adds the
registrations for TI Generic PHYs to associcate a TI PHY ID with a PHY name.

Porting PHY helper routines to set and clear bits to facilitate easier side
porting of ethernet kernel drivers to uBoot.

Also fixed and added missing or kernel doc documentation in the phy.h file.

Dan

Dan Murphy (5):
   net: phy: Add missing kernel doc to phy functions
   net: phy: Fix kernel doc issues in phy.h
   net: phy: Add helper routines to set and clear bits
   net: phy: Add support for TI PHY init
   net: phy: Add DP8382x phy registration to TI PHY init

  configs/am65x_evm_a53_defconfig  |   2 +-
  configs/am65x_hs_evm_a53_defconfig   |   2 +-
  configs/dra7xx_evm_defconfig |   2 +-
  configs/dra7xx_hs_evm_defconfig  |   2 +-
  configs/dra7xx_hs_evm_usb_defconfig  |   2 +-
  configs/j721e_evm_a72_defconfig  |   2 +-
  configs/j721e_hs_evm_a72_defconfig   |   2 +-
  configs/k2g_evm_defconfig|   2 +-
  configs/xilinx_versal_virt_defconfig |   2 +-
  configs/xilinx_zynqmp_virt_defconfig |   2 +-
  drivers/net/phy/Kconfig  |  15 
  drivers/net/phy/Makefile |   3 +-
  drivers/net/phy/dp83867.c|   3 +-
  drivers/net/phy/ti_phy_init.c| 101 
  drivers/net/phy/ti_phy_init.h|  15 
  include/phy.h| 112 ---
  16 files changed, 246 insertions(+), 23 deletions(-)
  create mode 100644 drivers/net/phy/ti_phy_init.c
  create mode 100644 drivers/net/phy/ti_phy_init.h



Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [PATCH] net: ethernet: ti: am65-cpsw-nuss: enable 10Mbps link speed in rgmii mode

[Grygorii Strashko]

On 20/04/2020 14:10, Murali Karicheri wrote:

+ Lokesh

On 04/17/2020 11:12 AM, Murali Karicheri wrote:

In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is
configured for External Control ("in band") mode
CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1

Hence update am65_cpsw_update_link() to follow documentation.

Signed-off-by: Murali Karicheri 
---
  drivers/net/ti/am65-cpsw-nuss.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 2b77213001..7531a07203 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -61,6 +61,7 @@
  #define AM65_CPSW_MACSL_CTL_REG    0x0
  #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A    BIT(15)
+#define AM65_CPSW_MACSL_CTL_EXT_EN    BIT(18)
  #define AM65_CPSW_MACSL_CTL_REG_GIG    BIT(7)
  #define AM65_CPSW_MACSL_CTL_REG_GMII_EN    BIT(5)
  #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK    BIT(1)
@@ -187,6 +188,9 @@ static int am65_cpsw_update_link(struct am65_cpsw_priv 
*priv)
    AM65_CPSW_MACSL_CTL_REG_GMII_EN;
  if (phy->speed == 1000)
  mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
+    if (phy->speed == 10 && phy_interface_is_rgmii(phy))
+    /* Can be used with in band mode only */
+    mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN;
  if (phy->duplex == DUPLEX_FULL)
  mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
  if (phy->speed == 100)





Reviewed-by: Grygorii Strashko 

--
Best regards,
grygorii

Re: [RFC PATCH 1/3] net: phy: Add a generic phy file for TI generic PHYs

[Grygorii Strashko]

On 21/04/2020 14:48, Dan Murphy wrote:

Michal

On 4/21/20 2:57 AM, Michal Simek wrote:

On 20. 04. 20 20:53, Dan Murphy wrote:

Add a TI Generic init file that will initialize TI PHYs that follow that
not require special handling.  These PHYs can connect with the standard
MII register set.  This generice file will register the PHY IDs and
names of the PHYs so when the command 'mdio list' is executed the PHY
name will display as opposed to 'Generic PHY'.

The DP8382X PHY series is a generic PHY that requires the generic
registration.

The DP83867 driver was updated to rename the init to a more PHY specific
init call.

Signed-off-by: Dan Murphy 

I would personally do it with two patches.


I was going to do 2 patches but I wanted to show the viability of why this 
generic file was needed.  Without the DP8382X PHY added it looks like I was 
just moving things around for the DP83867 and changing names.

I will break it up in v2 (non-RFC if no one has serious objections to this)




---
  configs/am65x_evm_a53_defconfig  |   2 +-
  configs/am65x_hs_evm_a53_defconfig   |   2 +-
  configs/dra7xx_evm_defconfig |   2 +-
  configs/dra7xx_hs_evm_defconfig  |   2 +-
  configs/dra7xx_hs_evm_usb_defconfig  |   2 +-
  configs/j721e_evm_a72_defconfig  |   2 +-
  configs/j721e_hs_evm_a72_defconfig   |   2 +-
  configs/k2g_evm_defconfig    |   2 +-
  configs/xilinx_versal_virt_defconfig |   2 +-
  configs/xilinx_zynqmp_virt_defconfig |   2 +-
  drivers/net/phy/Kconfig  |   8 ++
  drivers/net/phy/Makefile |   3 +-
  drivers/net/phy/dp83867.c    |   3 +-
  drivers/net/phy/ti_phy_init.c    | 106 +++
  drivers/net/phy/ti_phy_init.h    |  16 
  15 files changed, 144 insertions(+), 12 deletions(-)
  create mode 100644 drivers/net/phy/ti_phy_init.c
  create mode 100644 drivers/net/phy/ti_phy_init.h

diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 542bbd992c53..7051d6c40505 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -101,7 +101,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT
  CONFIG_SPI_FLASH_STMICRO=y
  # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_DP83867=y

Don't know why this name was chosen but don't you want to label it with TI?

CONFIG_PHY_TI_DP83867 ?

Kernel is using different symbol anyway.
CONFIG_DP83867_PHY


ACK.  I will make it CONFIG_PHY_TI_DP83867.  That follows the Kconfig uBoot 
standard for PHYs


yep. It definitely has to be split

Cover?

--
Best regards,
grygorii

Re: [PATCH] net: phy: dp83867: Do not check sgmii if rgmii is already used

[Grygorii Strashko]

On 13/02/2020 18:05, Michal Simek wrote:

On 13. 02. 20 16:49, Grygorii Strashko wrote:



On 13/02/2020 08:23, Michal Simek wrote:

On 12. 02. 20 21:24, Grygorii Strashko wrote:



On 11/02/2020 10:11, Michal Simek wrote:

On 10. 02. 20 13:07, Grygorii Strashko wrote:



On 07/02/2020 13:31, Michal Simek wrote:

There is no reason to check sgmii branch again when it is clear that
phy
interface is rgmii.

Signed-off-by: Michal Simek 
---

     drivers/net/phy/dp83867.c | 4 +---
     1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 4d796e289c45..3178787ff1c7 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -327,9 +327,7 @@ static int dp83867_config(struct phy_device
*phydev)
       phy_write_mmd(phydev, DP83867_DEVADDR,
   DP83867_RGMIIDCTL, delay);
-    }
-
-    if (phy_interface_is_sgmii(phydev)) {
+    } else if (phy_interface_is_sgmii(phydev)) {
     phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
   (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));



   From one side I have no objections, but from another - I'd prefer to
keep as is.


Can you please be elaborate on this one more?


- keep the same way as in the Kernel


If kernel does it in the same way it should be also fixed.

I have been checking yesterday dt binding docs in u-boot and in Linux
and surprisingly they are different.

ti,dp83867-rxctrl-strap-quirk is supported in u-boot but not described

ti,clk-output-sel is supported but even in code is said that it is
optional property.

ti,min-output-impedance, ti,max-output-impedance and ti,fifo-depth  are
not documented in dt binding doc

ti,sgmii-ref-clock-output-enable is not supported in u-boot but it is in
Linux and we are using this feature.



My understanding is that u-boot goal is to have uboot-dt == kernel-dt
and current
approach add DT+bindings to the kernel first.

So, if you check most of u-boot bindings are missed or obsolete.


Can you please sync it if you want to keep it in the same was as is done
in Linux?


So, may be it can be just deleted.


I am ok with that.






- code readability


I don't think this is really changing code readability. For improving
readability would be the best to move bodies of these ifs to separate
functions and not have dp83867_config() ~140 lines long.


It really too minor change to fight for. But if you wish you can update
kernel
driver as per-above your proposal and then port it in u-boot.


I was looking at latest kernel code and it is designed differently there.
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/net/phy/dp83867.c?h=next-20200213#n479


there is
if rgmii or sgmii
if rgmii
io impedance
if sgmii

in u-boot you have
if rgmii
if sgmii
io impedance

I am ok with having this in sync but that's not what we have today.


Yes. Unfortunately, The kernel moves forward faster than u-boot and people not 
always
interesting to port their patches in u-boot :(
Plus, not all functionality, enabled in the kernel, is really required by 
u-boot.


--
Best regards,
grygorii

Re: [PATCH] dt-bindings: net: dp83867: Remove binding doc from U-Boot tree

[Grygorii Strashko]

On 17/02/2020 11:38, Michal Simek wrote:

U-Boot is having DT which doesn't cover all options currently supported by
driver. DT binding is aligned with Linux kernel version available here.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/ti,dp83867.txt
Based on my talk with Grygorii Strashko better will be to remove it.

Also Linux kernel bindings are being converted to yaml that's another
reason to do it only at one place.

Signed-off-by: Michal Simek 
---



I agree and see no reason to duplicate bindings in u-boot tree.
Reviewed-by: Grygorii Strashko 


  doc/device-tree-bindings/net/ti,dp83867.txt | 35 -
  1 file changed, 35 deletions(-)
  delete mode 100644 doc/device-tree-bindings/net/ti,dp83867.txt

diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt 
b/doc/device-tree-bindings/net/ti,dp83867.txt
deleted file mode 100644
index 268220964aab..
--- a/doc/device-tree-bindings/net/ti,dp83867.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-* Texas Instruments - dp83867 Giga bit ethernet phy
-
-Required properties:
-   - reg - The ID number for the phy, usually a small integer
-   - ti,rx-internal-delay - RGMII Recieve Clock Delay - see 
dt-bindings/net/ti-dp83867.h
-   for applicable values
-   - ti,tx-internal-delay - RGMII Transmit Clock Delay - see 
dt-bindings/net/ti-dp83867.h
-   for applicable values
-   - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
-   for applicable values
-   - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
-   compensate for the board being designed with the lanes swapped.
-   - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
-   TX/RX lanes.
-   - ti,clk-output-sel - Muxing option for CLK_OUT pin.  See 
dt-bindings/net/ti-dp83867.h
- for applicable values.  The CLK_OUT pin can also
- be disabled by this property.  When omitted, the
- PHY's default will be left as is.
-
-Default child nodes are standard Ethernet PHY device
-nodes as described in doc/devicetree/bindings/net/ethernet.txt
-
-Example:
-
-   ethernet-phy@0 {
-   reg = <0>;
-   ti,rx-internal-delay = ;
-   ti,tx-internal-delay = ;
-   ti,fifo-depth = ;
-   enet-phy-lane-no-swap;
-   ti,clk-output-sel = ;
-   };
-
-Datasheet can be found:
-http://www.ti.com/product/DP83867IR/datasheet



--
Best regards,
grygorii

Re: [PATCH] net: phy: dp83867: Do not check sgmii if rgmii is already used

[Grygorii Strashko]

On 13/02/2020 08:23, Michal Simek wrote:

On 12. 02. 20 21:24, Grygorii Strashko wrote:



On 11/02/2020 10:11, Michal Simek wrote:

On 10. 02. 20 13:07, Grygorii Strashko wrote:



On 07/02/2020 13:31, Michal Simek wrote:

There is no reason to check sgmii branch again when it is clear that
phy
interface is rgmii.

Signed-off-by: Michal Simek 
---

    drivers/net/phy/dp83867.c | 4 +---
    1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 4d796e289c45..3178787ff1c7 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -327,9 +327,7 @@ static int dp83867_config(struct phy_device
*phydev)
      phy_write_mmd(phydev, DP83867_DEVADDR,
  DP83867_RGMIIDCTL, delay);
-    }
-
-    if (phy_interface_is_sgmii(phydev)) {
+    } else if (phy_interface_is_sgmii(phydev)) {
    phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
   


  From one side I have no objections, but from another - I'd prefer to
keep as is.


Can you please be elaborate on this one more?


- keep the same way as in the Kernel


If kernel does it in the same way it should be also fixed.

I have been checking yesterday dt binding docs in u-boot and in Linux
and surprisingly they are different.

ti,dp83867-rxctrl-strap-quirk is supported in u-boot but not described

ti,clk-output-sel is supported but even in code is said that it is
optional property.

ti,min-output-impedance, ti,max-output-impedance and ti,fifo-depth  are
not documented in dt binding doc

ti,sgmii-ref-clock-output-enable is not supported in u-boot but it is in
Linux and we are using this feature.



My understanding is that u-boot goal is to have uboot-dt == kernel-dt and 
current
approach add DT+bindings to the kernel first.

So, if you check most of u-boot bindings are missed or obsolete.


Can you please sync it if you want to keep it in the same was as is done
in Linux?


So, may be it can be just deleted.




- code readability


I don't think this is really changing code readability. For improving
readability would be the best to move bodies of these ifs to separate
functions and not have dp83867_config() ~140 lines long.


It really too minor change to fight for. But if you wish you can update kernel
driver as per-above your proposal and then port it in u-boot.

--
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grygorii

Re: [PATCH] net: phy: dp83867: Do not check sgmii if rgmii is already used

[Grygorii Strashko]

On 11/02/2020 10:11, Michal Simek wrote:

On 10. 02. 20 13:07, Grygorii Strashko wrote:



On 07/02/2020 13:31, Michal Simek wrote:

There is no reason to check sgmii branch again when it is clear that phy
interface is rgmii.

Signed-off-by: Michal Simek 
---

   drivers/net/phy/dp83867.c | 4 +---
   1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 4d796e289c45..3178787ff1c7 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -327,9 +327,7 @@ static int dp83867_config(struct phy_device *phydev)
     phy_write_mmd(phydev, DP83867_DEVADDR,
     DP83867_RGMIIDCTL, delay);
-    }
-
-    if (phy_interface_is_sgmii(phydev)) {
+    } else if (phy_interface_is_sgmii(phydev)) {
   phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
     (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
  


 From one side I have no objections, but from another - I'd prefer to
keep as is.


Can you please be elaborate on this one more?


- keep the same way as in the Kernel
- code readability


--
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grygorii

Re: [PATCH] net: phy: dp83867: Do not check sgmii if rgmii is already used

[Grygorii Strashko]

On 07/02/2020 13:31, Michal Simek wrote:

There is no reason to check sgmii branch again when it is clear that phy
interface is rgmii.

Signed-off-by: Michal Simek 
---

  drivers/net/phy/dp83867.c | 4 +---
  1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 4d796e289c45..3178787ff1c7 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -327,9 +327,7 @@ static int dp83867_config(struct phy_device *phydev)
  
  		phy_write_mmd(phydev, DP83867_DEVADDR,

  DP83867_RGMIIDCTL, delay);
-   }
-
-   if (phy_interface_is_sgmii(phydev)) {
+   } else if (phy_interface_is_sgmii(phydev)) {
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
  



From one side I have no objections, but from another - I'd prefer to keep as is.

--
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grygorii

Re: [PATCH] net: phy: dp83867: Clean force link good bit

[Grygorii Strashko]

On 06/02/2020 17:03, Michal Simek wrote:

On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.

Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.

Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek 
---


Reviewed-by: Grygorii Strashko 



  drivers/net/phy/dp83867.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index a43793cd4274..4d796e289c45 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -64,6 +64,7 @@
  #define DP83867_PHYCR_FIFO_DEPTH_SHIFT14
  #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
  #define DP83867_PHYCR_RESERVED_MASK   BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD  BIT(10)
  #define DP83867_MDI_CROSSOVER 5
  #define DP83867_MDI_CROSSOVER_MDIX2
  #define DP83867_PHYCTRL_SGMIIEN   0x0800
@@ -283,6 +284,9 @@ static int dp83867_config(struct phy_device *phydev)
val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
  
+		/* Do not force link good */

+   val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
+
/* The code below checks if "port mirroring" N/A MODE4 has been
 * enabled during power on bootstrap.
 *



--
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grygorii

Re: [U-Boot] [PATCH v2 0/6] J721e: Add networking support

[Grygorii Strashko]

On 02/12/2019 10:59, Vignesh Raghavendra wrote:

This patch enables networking support for TI's J721e SoC.
Patch 1 adds a new interface to DMA uclass to get channel specific
private/configuration data. Patch 2 to 4 use this interface to pass data
from J721e's UDMA driver to CPSW ethernet driver. Last two patches add
DMA and CPSW DT nodes and configs.

Depends on [1] for ethernet to work

[1] http://patchwork.ozlabs.org/project/uboot/list/?series=145954

v2:
Address comments from Grygorii.
Collect Acks


Few minor comments.

Reviewed-by: Grygorii Strashko 



Vignesh Raghavendra (6):
   dma: Introduce dma_get_cfg() interface
   dma: ti: k3-udma: Implement dma_get_cfg() interface
   net: ti: am65-cpsw-nuss: Rework RX flow ID handling
   net: ti: am65-cpsw-nuss: Add new compatible for J721e
   arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT
 nodes
   configs: j721e_evm_a72_defconfig: Enable DMA and Ethernet

  .../k3-j721e-common-proc-board-u-boot.dtsi| 239 ++
  configs/j721e_evm_a72_defconfig   |   8 +
  drivers/dma/dma-uclass.c  |  12 +
  drivers/dma/ti/k3-udma.c  |  30 ++-
  drivers/net/ti/am65-cpsw-nuss.c   |  14 +-
  include/dma-uclass.h  |  11 +
  include/dma.h |  11 +
  include/linux/soc/ti/ti-udma.h|  19 ++
  8 files changed, 334 insertions(+), 10 deletions(-)



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Re: [U-Boot] [PATCH v2 5/6] arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT nodes

[Grygorii Strashko]

On 02/12/2019 10:59, Vignesh Raghavendra wrote:

Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.

Signed-off-by: Vignesh Raghavendra 
Acked-by: Joe Hershberger 
---
  .../k3-j721e-common-proc-board-u-boot.dtsi| 239 ++
  1 file changed, 239 insertions(+)

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 541da22c4889..f3857b9100bb 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -3,11 +3,18 @@
   * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   */
  
+#include 

+#include 
+
  / {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = 
};
+
+   aliases {
+   ethernet0 = _port1;
+   };
  };
  
  _main{

@@ -24,6 +31,184 @@
clock-frequency = <2500>;
u-boot,dm-spl;
};
+


[...]


+_mdio {
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   /* TODO: phy reset: 
TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */


Could you drop this TODO pls?


+   ti,rx-internal-delay = ;
+   ti,fifo-depth = ;
+   };
+};
+
+_port1 {
+   phy-mode = "rgmii-rxid";
+   phy-handle = <>;
+};
+
+_cpsw {
+   reg = <0x0 0x4600 0x0 0x20>,
+ <0x0 0x40f00200 0x0 0x2>;
+   reg-names = "cpsw_nuss", "mac_efuse";
+
+   cpsw-phy-sel@40f04040 {
+   compatible = "ti,am654-cpsw-phy-sel";
+   reg= <0x0 0x40f04040 0x0 0x4>;
+   reg-names = "gmii-sel";
+   };
+};



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Re: [U-Boot] [PATCH v2 3/6] net: ti: am65-cpsw-nuss: Rework RX flow ID handling

[Grygorii Strashko]

On 02/12/2019 10:59, Vignesh Raghavendra wrote:

Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.

Signed-off-by: Vignesh Raghavendra 
Acked-by: Joe Hershberger 
---
  drivers/net/ti/am65-cpsw-nuss.c | 13 -
  1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 06b06639506a..2e14f4be862f 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -99,7 +99,6 @@ struct am65_cpsw_common {
  
  	u32			port_num;

struct am65_cpsw_port   ports[AM65_CPSW_CPSWNU_MAX_PORTS];
-   u32 rflow_id_base;
  
  	struct mii_dev		*bus;

u32 bus_freq;
@@ -276,6 +275,7 @@ static int am65_cpsw_start(struct udevice *dev)
struct am65_cpsw_common *common = priv->cpsw_common;
struct am65_cpsw_port *port = >ports[priv->port_id];
struct am65_cpsw_port *port0 = >ports[0];
+   struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data;
int ret, i;
  
  	ret = power_domain_on(>pwrdmn);

@@ -341,7 +341,8 @@ static int am65_cpsw_start(struct udevice *dev)
writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
  
  	/* set base flow_id */

-   writel(common->rflow_id_base,
+   dma_get_cfg(>dma_rx, 0, (void **)_rx_cfg_data);
+   writel(dma_rx_cfg_data->flow_id_base,
   port0->port_base + AM65_CPSW_P0_FLOW_ID_REG);


Could you add dbg print here, hence you've dropped it below, pls?

  
  	/* Reset and enable the ALE */

@@ -669,11 +670,6 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev)
AM65_CPSW_CPSW_NU_ALE_BASE;
cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
  
-	cpsw_common->rflow_id_base = 0;

-   cpsw_common->rflow_id_base =
-   dev_read_u32_default(dev, "ti,rx-flow-id-base",
-cpsw_common->rflow_id_base);
-
ports_np = dev_read_subnode(dev, "ports");
if (!ofnode_valid(ports_np)) {
ret = -ENOENT;
@@ -761,12 +757,11 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev)
if (ret)
goto out;
  
-	dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u rflow_id_base:%u mdio_freq:%u\n",

+   dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X 
Ports:%u mdio_freq:%u\n",
 readl(cpsw_common->ss_base),
 readl(cpsw_common->cpsw_base),
 readl(cpsw_common->ale_base),
 cpsw_common->port_num,
-cpsw_common->rflow_id_base,
 cpsw_common->bus_freq);
  
  out:




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Re: [U-Boot] [PATCH RESEND v2 00/10] dma: ti: k3-udma: Add support for J721e

[Grygorii Strashko]

On 02/12/2019 10:54, Vignesh Raghavendra wrote:

This series adds DMA support for J721e using exist K3 UDMA driver.

One main change is thati, on J721e, DMA resources such as DMA channels are
shared between different entities running on different cores of the SoC.
Therefore, U-Boot running on A72 core should request range of resources
allocated to it from centralized resource management core (DMSC) and use
only the allocated resource.

First two patches adds support for dynamically querying and using
allocated resources. Remaining patches fix issues when using UDMA driver
on a 32 bit core like R5. Last patch adds a new compatible for J721e

Vignesh Raghavendra (10):
   lib: Import few bitmap functions from Linux
   dma: ti: k3-udma: Query DMA channels allocated from Resource Manager
   soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop
   soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandle
   dma: ti: k3-udma: Remove coherency check for cache ops
   dma: ti: k3-udma: Fix debug prints during enabling MEM_TO_DEV
 transfers
   dma: ti: k3-udma: Switch to exposed ring mode
   dma: ti: k3-udma: Fix ring push operation for 32 bit cores
   dma: ti: k3-udma: Fix build warnings when building for 32 bit
 platforms
   dma: ti: k3-udma: Add new compatible to J721e

  drivers/dma/ti/k3-udma-hwdef.h|  19 ++
  drivers/dma/ti/k3-udma.c  | 346 --
  drivers/soc/ti/k3-navss-ringacc.c |  13 +-
  include/linux/bitmap.h| 133 
  include/linux/bitops.h|  12 ++
  5 files changed, 403 insertions(+), 120 deletions(-)



minor comment to patch 2.
Otherwise:
Reviewed-by: Grygorii Strashko 

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Re: [U-Boot] [PATCH RESEND v2 02/10] dma: ti: k3-udma: Query DMA channels allocated from Resource Manager

[Grygorii Strashko]

On 02/12/2019 10:54, Vignesh Raghavendra wrote:

On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.

Signed-off-by: Vignesh Raghavendra 
---
v2:
Address comments on v1 from Grygorii
Squash patch 5 (of v1) into this patch

  drivers/dma/ti/k3-udma-hwdef.h |  19 +++
  drivers/dma/ti/k3-udma.c   | 274 +++--
  2 files changed, 214 insertions(+), 79 deletions(-)

diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h
index c88399a815ea..228a44cb73cf 100644
--- a/drivers/dma/ti/k3-udma-hwdef.h
+++ b/drivers/dma/ti/k3-udma-hwdef.h
@@ -181,4 +181,23 @@
  #define PDMA_STATIC_TR_Z(x)   \
(((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK)
  
+enum udma_rm_range {

+   RM_RANGE_TCHAN = 0,
+   RM_RANGE_RCHAN,
+   RM_RANGE_RFLOW,
+   RM_RANGE_LAST,
+};
+
+struct udma_tisci_rm {
+   const struct ti_sci_handle *tisci;
+   const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
+   u32  tisci_dev_id;
+
+   /* tisci information for PSI-L thread pairing/unpairing */
+   const struct ti_sci_rm_psil_ops *tisci_psil_ops;
+   u32  tisci_navss_dev_id;
+
+   struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
+};


I'd move it in k3-udma.c


+
  #endif /* K3_NAVSS_UDMA_HWDEF_H_ */
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index a5fc7809bc41..2f82ab0955a4 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -11,12 +11,14 @@
  #include 


[...]

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[U-Boot] [PATCH] board: ti: am43xx: remove net platform code

[Grygorii Strashko]

The TI AM43xx platform has DM_ETH and OF_CONTROL enabled,
so remove networking platform code.

Signed-off-by: Grygorii Strashko 
---
 board/ti/am43xx/board.c | 106 +---
 1 file changed, 1 insertion(+), 105 deletions(-)

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index f5ecf871bc..7ec9c38e6a 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -8,6 +8,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -26,8 +27,6 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
@@ -851,109 +850,6 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
 
-#ifdef CONFIG_DRIVER_TI_CPSW
-
-static void cpsw_control(int enabled)
-{
-   /* Additional controls can be added here */
-   return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-   {
-   .slave_reg_ofs  = 0x208,
-   .sliver_reg_ofs = 0xd80,
-   .phy_addr   = 16,
-   },
-   {
-   .slave_reg_ofs  = 0x308,
-   .sliver_reg_ofs = 0xdc0,
-   .phy_addr   = 1,
-   },
-};
-
-static struct cpsw_platform_data cpsw_data = {
-   .mdio_base  = CPSW_MDIO_BASE,
-   .cpsw_base  = CPSW_BASE,
-   .mdio_div   = 0xff,
-   .channels   = 8,
-   .cpdma_reg_ofs  = 0x800,
-   .slaves = 1,
-   .slave_data = cpsw_slaves,
-   .ale_reg_ofs= 0xd00,
-   .ale_entries= 1024,
-   .host_port_reg_ofs  = 0x108,
-   .hw_stats_reg_ofs   = 0x900,
-   .bd_ram_ofs = 0x2000,
-   .mac_control= (1 << 5),
-   .control= cpsw_control,
-   .host_port_num  = 0,
-   .version= CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
-   int rv;
-   uint8_t mac_addr[6];
-   uint32_t mac_hi, mac_lo;
-
-   /* try reading mac address from efuse */
-   mac_lo = readl(>macid0l);
-   mac_hi = readl(>macid0h);
-   mac_addr[0] = mac_hi & 0xFF;
-   mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-   mac_addr[2] = (mac_hi & 0xFF) >> 16;
-   mac_addr[3] = (mac_hi & 0xFF00) >> 24;
-   mac_addr[4] = mac_lo & 0xFF;
-   mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-   if (!env_get("ethaddr")) {
-   puts(" not set. Validating first E-fuse MAC\n");
-   if (is_valid_ethaddr(mac_addr))
-   eth_env_set_enetaddr("ethaddr", mac_addr);
-   }
-
-   mac_lo = readl(>macid1l);
-   mac_hi = readl(>macid1h);
-   mac_addr[0] = mac_hi & 0xFF;
-   mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-   mac_addr[2] = (mac_hi & 0xFF) >> 16;
-   mac_addr[3] = (mac_hi & 0xFF00) >> 24;
-   mac_addr[4] = mac_lo & 0xFF;
-   mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-   if (!env_get("eth1addr")) {
-   if (is_valid_ethaddr(mac_addr))
-   eth_env_set_enetaddr("eth1addr", mac_addr);
-   }
-
-   if (board_is_eposevm()) {
-   writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, >miisel);
-   cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
-   cpsw_slaves[0].phy_addr = 16;
-   } else if (board_is_sk()) {
-   writel(RGMII_MODE_ENABLE, >miisel);
-   cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
-   cpsw_slaves[0].phy_addr = 4;
-   cpsw_slaves[1].phy_addr = 5;
-   } else if (board_is_idk()) {
-   writel(RGMII_MODE_ENABLE, >miisel);
-   cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
-   cpsw_slaves[0].phy_addr = 0;
-   } else {
-   writel(RGMII_MODE_ENABLE, >miisel);
-   cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
-   cpsw_slaves[0].phy_addr = 0;
-   }
-
-   rv = cpsw_register(_data);
-   if (rv < 0)
-   printf("Error %d registering CPSW switch\n", rv);
-
-   return rv;
-}
-#endif
-
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, bd_t *bd)
 {
-- 
2.17.1

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[U-Boot] [PATCH] board: ti: dra7-evm: remove net platform code

[Grygorii Strashko]

The DRA7 has DM_ETH and OF_CONTROL enabled, so remove networking platform
code.

Signed-off-by: Grygorii Strashko 
---
 board/ti/dra7xx/evm.c | 106 +-
 1 file changed, 1 insertion(+), 105 deletions(-)

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 74d04bb1e3..b1e1e5403c 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -11,6 +11,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -29,7 +30,6 @@
 #include 
 #include 
 #include 
-#include 
 
 #include "mux_data.h"
 #include "../common/board_detect.h"
@@ -45,10 +45,6 @@
 #define board_ti_get_emif_size()   board_ti_get_emif1_size() + \
board_ti_get_emif2_size()
 
-#ifdef CONFIG_DRIVER_TI_CPSW
-#include 
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 /* GPIO 7_11 */
@@ -989,106 +985,6 @@ int spl_start_uboot(void)
 }
 #endif
 
-#ifdef CONFIG_DRIVER_TI_CPSW
-extern u32 *const omap_si_rev;
-
-static void cpsw_control(int enabled)
-{
-   /* VTP can be added here */
-
-   return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-   {
-   .slave_reg_ofs  = 0x208,
-   .sliver_reg_ofs = 0xd80,
-   .phy_addr   = 2,
-   },
-   {
-   .slave_reg_ofs  = 0x308,
-   .sliver_reg_ofs = 0xdc0,
-   .phy_addr   = 3,
-   },
-};
-
-static struct cpsw_platform_data cpsw_data = {
-   .mdio_base  = CPSW_MDIO_BASE,
-   .cpsw_base  = CPSW_BASE,
-   .mdio_div   = 0xff,
-   .channels   = 8,
-   .cpdma_reg_ofs  = 0x800,
-   .slaves = 2,
-   .slave_data = cpsw_slaves,
-   .ale_reg_ofs= 0xd00,
-   .ale_entries= 1024,
-   .host_port_reg_ofs  = 0x108,
-   .hw_stats_reg_ofs   = 0x900,
-   .bd_ram_ofs = 0x2000,
-   .mac_control= (1 << 5),
-   .control= cpsw_control,
-   .host_port_num  = 0,
-   .version= CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
-   int ret;
-   uint8_t mac_addr[6];
-   uint32_t mac_hi, mac_lo;
-   uint32_t ctrl_val;
-
-   /* try reading mac address from efuse */
-   mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
-   mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
-   mac_addr[0] = (mac_hi & 0xFF) >> 16;
-   mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-   mac_addr[2] = mac_hi & 0xFF;
-   mac_addr[3] = (mac_lo & 0xFF) >> 16;
-   mac_addr[4] = (mac_lo & 0xFF00) >> 8;
-   mac_addr[5] = mac_lo & 0xFF;
-
-   if (!env_get("ethaddr")) {
-   printf(" not set. Validating first E-fuse MAC\n");
-
-   if (is_valid_ethaddr(mac_addr))
-   eth_env_set_enetaddr("ethaddr", mac_addr);
-   }
-
-   mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
-   mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
-   mac_addr[0] = (mac_hi & 0xFF) >> 16;
-   mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-   mac_addr[2] = mac_hi & 0xFF;
-   mac_addr[3] = (mac_lo & 0xFF) >> 16;
-   mac_addr[4] = (mac_lo & 0xFF00) >> 8;
-   mac_addr[5] = mac_lo & 0xFF;
-
-   if (!env_get("eth1addr")) {
-   if (is_valid_ethaddr(mac_addr))
-   eth_env_set_enetaddr("eth1addr", mac_addr);
-   }
-
-   ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
-   ctrl_val |= 0x22;
-   writel(ctrl_val, (*ctrl)->control_core_control_io1);
-
-   if (*omap_si_rev == DRA722_ES1_0)
-   cpsw_data.active_slave = 1;
-
-   if (board_is_dra72x_revc_or_later()) {
-   cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
-   cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
-   }
-
-   ret = cpsw_register(_data);
-   if (ret < 0)
-   printf("Error %d registering CPSW switch\n", ret);
-
-   return ret;
-}
-#endif
-
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 /* VTT regulator enable */
 static inline void vtt_regulator_enable(void)
-- 
2.17.1

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Re: [U-Boot] [PATCH 0/6] J721e: Add networking support

[Grygorii Strashko]

On 18/11/2019 12:59, Vignesh Raghavendra wrote:

This patch enables networking support for TI's J721e SoC.
Patch 1 adds a new interface to DMA uclass to get channel specific
private/configuration data. Patch 2 to 4 use this interface to pass data
from J721e's UDMA driver to CPSW ethernet driver. Last two patches add
DMA and CPSW DT nodes and configs.



I assume this series has dependencies. Right?



Vignesh Raghavendra (6):
   dma: Introduce dma_get_cfg() interface
   dma: ti: k3-udma: Implement dma_get_cfg() interface
   net: ti: am65-cpsw-nuss: Rework RX flow ID handling
   net: ti: am65-cpsw-nuss: Add new compatible for J721e
   arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT
 nodes
   configs: j721e_evm_a72_defconfig: Enable DMA and Ethernet

  .../k3-j721e-common-proc-board-u-boot.dtsi| 268 ++
  configs/j721e_evm_a72_defconfig   |   8 +
  drivers/dma/dma-uclass.c  |  12 +
  drivers/dma/ti/k3-udma.c  |  28 ++
  drivers/net/ti/am65-cpsw-nuss.c   |  14 +-
  include/dma-uclass.h  |  11 +
  include/dma.h |  11 +
  include/linux/soc/ti/ti-udma.h|  19 ++
  8 files changed, 362 insertions(+), 9 deletions(-)



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grygorii
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Re: [U-Boot] [PATCH v4 4/5] doc: bindings: add mdio-handle property to ethernet nodes

[Grygorii Strashko]

On 21/11/2019 12:36, Alexandru Marginean wrote:

On 11/20/2019 10:51 AM, Grygorii Strashko wrote:



On 19/11/2019 20:58, Grygorii Strashko wrote:



On 19/11/2019 01:31, Alexandru Marginean wrote:


On 11/18/2019 8:11 PM, Grygorii Strashko wrote:



On 14/11/2019 17:04, Alex Marginean wrote:

Adds an optional mdio-handle property which identifies a MDIO bus which can
be scanned to find the relevant PHY.  The property is ignored if phy-handle
is also present.

Signed-off-by: Alex Marginean 
---
  doc/device-tree-bindings/net/ethernet.txt | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/doc/device-tree-bindings/net/ethernet.txt 
b/doc/device-tree-bindings/net/ethernet.txt
index 3fc360523b..9f9629f8d6 100644
--- a/doc/device-tree-bindings/net/ethernet.txt
+++ b/doc/device-tree-bindings/net/ethernet.txt
@@ -9,6 +9,8 @@ The following properties are common to the Ethernet controllers:
  - max-speed: number, specifies maximum speed in Mbit/s supported by the 
device;
  - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather 
than
    the maximum frame size (there's contradiction in ePAPR).
+- mdio-handle: phandle, specifies a reference to a MDIO bus to be scanned to
+  find the PHY device.  Ignored if phy-handle is also present.


Sry, but it looks redundant. The Ethernet-controller bindings
expects to use phy-handle which, in turn, allows to get MDIO node.


The problem I'm trying to solve is not that I don't want to get the
parent MDIO bus of a PHY referenced though phy-handle, but rather that I
want to avoid having a specific U-Boot DT for each PHY plug-in card that
could be used in our systems.  I'll explain that in more detail.

We have these QDS systems which support plug-in cards with PHYs on them.
The way it works is that a given ethernet interface is associated with
one of the QDS slots that should contain a plug-in card.  Each of the
slots has a MDIO bus associated with it, this bus is accessed through a
MDIO MUX on the QDS board.
The slot may be populated with one of several types of cards, which
are different designs, have different types of PHYs and more importantly
use different PHY addresses on the MDIO bus.

So now the summary is that an Ethernet interface is associated with a
MDIO bus that could be scanned to find the relevant PHY, while using the
existing phy-handle binding requires that U-Boot DT is edited whenever
a different card is plugged in, which is not practical and avoidable.


Thank you for explanation. It's clear now.
I think above description is good to have as part of commit message.





So, if your platform is DT based and can use DT then it's reasonable to follow 
standard binding,
which, in addition, allows to specify Ethernet PHY properties.


Sure, and we do that on boards and for PHYs which are at fixed addresses
on MDIO bus, but that is impractical with the swappable cards.



Some thought, which i think might help.
- u-boot allows phy node not to have "reg" property.
- phy_connect() will return first PHY discovered on the MDIO bus if addr<=0

So, if MDIO assignment per ethernet interface/slot is fixed DT can look like

mdioX {
 mdiox_phy0: ethernet-phy@0 {
 };
}

ethernetX {
 phy-handle = <_phy0>;
}

and so on. driver's parsing code can ignore PHY "reg" prop in phy
node and pass addr<=0 to phy_connect().

Functionally that's what I'm looking for, yes.  There is the problem of
not strictly following the kernel binding and at the end of the day I
will have the same problem with the kernel too, so I should take this
topic to the netdev list anyway.

Having 'reg' made optional is actually an interesting idea.  I think
'mdio-handle' is a bit more clear what it is, but having an actual PHY
node allows passing DT properties on to the PHY driver which is
certainly useful for some PHYs.  It's like saying I don't know what PHY
I'm going to find, but if it's a PHY that has these configurable
properties here is your configuration.


Another good question is "phy-connection-type"/"phy-mode".
Are all your cards works in the same mode? And how is this solved?

Is there anything common with SFP? Linux: bindings/net/sff,sfp.txt





It seems, current Linux approach is to have PHY "reg" property as required, but 
your case might be the reason to change this. >

I'll have to do a better write-up for the kernel list and we'll see
how this will go.
In the meantime any feedback on the other patches, except the one
introducing mdio-handle?  For instance I should deal with fixed links
in the dm_eth_phy_connect helper too (calling phy_connect_fixed),
my intent is to take some code that is otherwise pretty generic out of
the drivers.


From one side, it look nice. From another, in my case MDIO is not a device,
so can't try it.

But, any way, I'd like to share some notes I have. It may help you or may
save your time by reducing number of possible regressions.

To be honest, there is a l

[U-Boot] [PATCH v2] arm: ti: dra7: move BOOTP_DNS2 and PHY_TI in defconfig

[Grygorii Strashko]

Move BOOTP_DNS2 and PHY_TI from dra7xx_evm.h to
dra7xx_evm_defconfig.

Signed-off-by: Grygorii Strashko 
---
 configs/dra7xx_evm_defconfig| 2 ++
 configs/dra7xx_hs_evm_defconfig | 2 ++
 configs/dra7xx_hs_evm_usb_defconfig | 2 ++
 include/configs/dra7xx_evm.h| 2 --
 4 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index cb2cdcb350..c711d7eaaa 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -34,6 +34,7 @@ CONFIG_CMD_SPL=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
 
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),2m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
@@ -82,6 +83,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=7680
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_TI=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 1dff889975..7811938b68 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -37,6 +37,7 @@ CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
+CONFIG_BOOTP_DNS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
 
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),2m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
@@ -85,6 +86,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=7680
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_TI=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig 
b/configs/dra7xx_hs_evm_usb_defconfig
index fa18e1d076..621d7271e2 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
@@ -83,6 +84,7 @@ CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=7680
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_TI=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 0ad23ce4b9..0eb1cff33e 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -64,10 +64,8 @@
 #define CONFIG_HSMMC2_8BIT
 
 /* CPSW Ethernet */
-#define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_TI
 
 /*
  * Default to using SPI for environment, etc.
-- 
2.17.1

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Re: [U-Boot] [PATCH v4 4/5] doc: bindings: add mdio-handle property to ethernet nodes

[Grygorii Strashko]

On 19/11/2019 20:58, Grygorii Strashko wrote:



On 19/11/2019 01:31, Alexandru Marginean wrote:


On 11/18/2019 8:11 PM, Grygorii Strashko wrote:



On 14/11/2019 17:04, Alex Marginean wrote:

Adds an optional mdio-handle property which identifies a MDIO bus which can
be scanned to find the relevant PHY.  The property is ignored if phy-handle
is also present.

Signed-off-by: Alex Marginean 
---
  doc/device-tree-bindings/net/ethernet.txt | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/doc/device-tree-bindings/net/ethernet.txt 
b/doc/device-tree-bindings/net/ethernet.txt
index 3fc360523b..9f9629f8d6 100644
--- a/doc/device-tree-bindings/net/ethernet.txt
+++ b/doc/device-tree-bindings/net/ethernet.txt
@@ -9,6 +9,8 @@ The following properties are common to the Ethernet controllers:
  - max-speed: number, specifies maximum speed in Mbit/s supported by the 
device;
  - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather 
than
    the maximum frame size (there's contradiction in ePAPR).
+- mdio-handle: phandle, specifies a reference to a MDIO bus to be scanned to
+  find the PHY device.  Ignored if phy-handle is also present.


Sry, but it looks redundant. The Ethernet-controller bindings
expects to use phy-handle which, in turn, allows to get MDIO node.


The problem I'm trying to solve is not that I don't want to get the
parent MDIO bus of a PHY referenced though phy-handle, but rather that I
want to avoid having a specific U-Boot DT for each PHY plug-in card that
could be used in our systems.  I'll explain that in more detail.

We have these QDS systems which support plug-in cards with PHYs on them.
The way it works is that a given ethernet interface is associated with
one of the QDS slots that should contain a plug-in card.  Each of the
slots has a MDIO bus associated with it, this bus is accessed through a
MDIO MUX on the QDS board.
The slot may be populated with one of several types of cards, which
are different designs, have different types of PHYs and more importantly
use different PHY addresses on the MDIO bus.

So now the summary is that an Ethernet interface is associated with a
MDIO bus that could be scanned to find the relevant PHY, while using the
existing phy-handle binding requires that U-Boot DT is edited whenever
a different card is plugged in, which is not practical and avoidable.


Thank you for explanation. It's clear now.
I think above description is good to have as part of commit message.





So, if your platform is DT based and can use DT then it's reasonable to follow 
standard binding,
which, in addition, allows to specify Ethernet PHY properties.


Sure, and we do that on boards and for PHYs which are at fixed addresses
on MDIO bus, but that is impractical with the swappable cards.



Some thought, which i think might help.
- u-boot allows phy node not to have "reg" property.
- phy_connect() will return first PHY discovered on the MDIO bus if addr<=0

So, if MDIO assignment per ethernet interface/slot is fixed DT can look like

mdioX {
mdiox_phy0: ethernet-phy@0 {
};
}

ethernetX {
phy-handle = <_phy0>;
}

and so on. driver's parsing code can ignore PHY "reg" prop in phy node and pass
addr<=0 to phy_connect().

It seems, current Linux approach is to have PHY "reg" property as required, but
your case might be the reason to change this.

--
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grygorii
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Re: [U-Boot] [PATCH] arm: ti: dra7: move BOOTP_DNS2 and PHY_TI in defconfig

[Grygorii Strashko]

On 20/11/2019 06:30, Lokesh Vutla wrote:



On 20/11/19 12:14 AM, Grygorii Strashko wrote:

Move BOOTP_DNS2 and PHY_TI from dra7xx_evm.h to
dra7xx_evm_defconfig.

Signed-off-by: Grygorii Strashko 
---
  configs/dra7xx_evm_defconfig| 2 ++
  configs/dra7xx_hs_evm_defconfig | 2 ++
  configs/dra7xx_hs_evm_usb_defconfig | 2 ++
  include/configs/dra7xx_evm.h| 2 --
  4 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index cb2cdcb350..cae8431bc6 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -117,3 +117,5 @@ CONFIG_USB_GADGET=y
  CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
  CONFIG_USB_GADGET_VENDOR_NUM=0x0451
  CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_BOOTP_DNS2=y
+CONFIG_PHY_TI=y


Is this done using savedefconfig?


No. I'll update and resend



[...]

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grygorii
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Re: [U-Boot] [PATCH v4 4/5] doc: bindings: add mdio-handle property to ethernet nodes

[Grygorii Strashko]

On 19/11/2019 01:31, Alexandru Marginean wrote:


On 11/18/2019 8:11 PM, Grygorii Strashko wrote:



On 14/11/2019 17:04, Alex Marginean wrote:

Adds an optional mdio-handle property which identifies a MDIO bus which can
be scanned to find the relevant PHY.  The property is ignored if phy-handle
is also present.

Signed-off-by: Alex Marginean 
---
  doc/device-tree-bindings/net/ethernet.txt | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/doc/device-tree-bindings/net/ethernet.txt 
b/doc/device-tree-bindings/net/ethernet.txt
index 3fc360523b..9f9629f8d6 100644
--- a/doc/device-tree-bindings/net/ethernet.txt
+++ b/doc/device-tree-bindings/net/ethernet.txt
@@ -9,6 +9,8 @@ The following properties are common to the Ethernet controllers:
  - max-speed: number, specifies maximum speed in Mbit/s supported by the 
device;
  - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather 
than
    the maximum frame size (there's contradiction in ePAPR).
+- mdio-handle: phandle, specifies a reference to a MDIO bus to be scanned to
+  find the PHY device.  Ignored if phy-handle is also present.


Sry, but it looks redundant. The Ethernet-controller bindings
expects to use phy-handle which, in turn, allows to get MDIO node.


The problem I'm trying to solve is not that I don't want to get the
parent MDIO bus of a PHY referenced though phy-handle, but rather that I
want to avoid having a specific U-Boot DT for each PHY plug-in card that
could be used in our systems.  I'll explain that in more detail.

We have these QDS systems which support plug-in cards with PHYs on them.
The way it works is that a given ethernet interface is associated with
one of the QDS slots that should contain a plug-in card.  Each of the
slots has a MDIO bus associated with it, this bus is accessed through a
MDIO MUX on the QDS board.
The slot may be populated with one of several types of cards, which
are different designs, have different types of PHYs and more importantly
use different PHY addresses on the MDIO bus.

So now the summary is that an Ethernet interface is associated with a
MDIO bus that could be scanned to find the relevant PHY, while using the
existing phy-handle binding requires that U-Boot DT is edited whenever
a different card is plugged in, which is not practical and avoidable.


Thank you for explanation. It's clear now.
I think above description is good to have as part of commit message.





So, if your platform is DT based and can use DT then it's reasonable to follow 
standard binding,
which, in addition, allows to specify Ethernet PHY properties.


Sure, and we do that on boards and for PHYs which are at fixed addresses
on MDIO bus, but that is impractical with the swappable cards.


More over, your series does not provide user for this new property.


That's true, I was planning to send the QDS DT after this was merged,
but if it helps I can add it to this patch set.

Alex


Personally I do not see even reasons to have 
doc/device-tree-bindings/net/ethernet.txt in u-boot
and think we should follow [1]


  - phy-mode: string, operation mode of the PHY interface; supported values are
    "mii", "gmii", "sgmii", "qsgmii", "tbi", "rev-mii", "rmii", "rgmii", 
"rgmii-id",
    "rgmii-rxid", "rgmii-txid", "rtbi", "smii", "xgmii"; this is now a de-facto



[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/ethernet-controller.yaml



--
Best regards,
grygorii
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[U-Boot] [PATCH] arm: ti: dra7: move BOOTP_DNS2 and PHY_TI in defconfig

[Grygorii Strashko]

Move BOOTP_DNS2 and PHY_TI from dra7xx_evm.h to
dra7xx_evm_defconfig.

Signed-off-by: Grygorii Strashko 
---
 configs/dra7xx_evm_defconfig| 2 ++
 configs/dra7xx_hs_evm_defconfig | 2 ++
 configs/dra7xx_hs_evm_usb_defconfig | 2 ++
 include/configs/dra7xx_evm.h| 2 --
 4 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index cb2cdcb350..cae8431bc6 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -117,3 +117,5 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_BOOTP_DNS2=y
+CONFIG_PHY_TI=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 1dff889975..f57c249f90 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -120,3 +120,5 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_BOOTP_DNS2=y
+CONFIG_PHY_TI=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig 
b/configs/dra7xx_hs_evm_usb_defconfig
index fa18e1d076..1385782567 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -115,3 +115,5 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_BOOTP_DNS2=y
+CONFIG_PHY_TI=y
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 0ad23ce4b9..0eb1cff33e 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -64,10 +64,8 @@
 #define CONFIG_HSMMC2_8BIT
 
 /* CPSW Ethernet */
-#define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_TI
 
 /*
  * Default to using SPI for environment, etc.
-- 
2.17.1

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[U-Boot] [PATCH 8/8] arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to rgmii-rxid

[Grygorii Strashko]

The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.

Signed-off-by: Grygorii Strashko 
---
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi 
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 8589f76d23..bea80c5d00 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -336,13 +336,12 @@
reg = <0>;
/* TODO: phy reset: 
TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
ti,rx-internal-delay = ;
-   ti,tx-internal-delay = ;
ti,fifo-depth = ;
};
 };
 
 _port1 {
-   phy-mode = "rgmii-id";
+   phy-mode = "rgmii-rxid";
phy-handle = <>;
 };
 
-- 
2.17.1

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[U-Boot] [PATCH 7/8] net: phy: dp83867: refactor rgmii configuration

[Grygorii Strashko]

Refactor SGMII configuration to group all settings together and reduce
number of MDIO transactions.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/phy/dp83867.c | 75 +++
 1 file changed, 36 insertions(+), 39 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index f9bb925646..a43793cd42 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -62,9 +62,9 @@
 
 /* PHY CTRL bits */
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
+#define DP83867_PHYCR_FIFO_DEPTH_MASK  GENMASK(15, 14)
 #define DP83867_PHYCR_RESERVED_MASKBIT(11)
 #define DP83867_MDI_CROSSOVER  5
-#define DP83867_MDI_CROSSOVER_AUTO 2
 #define DP83867_MDI_CROSSOVER_MDIX 2
 #define DP83867_PHYCTRL_SGMIIEN0x0800
 #define DP83867_PHYCTRL_RXFIFO_SHIFT   12
@@ -277,11 +277,11 @@ static int dp83867_config(struct phy_device *phydev)
}
 
if (phy_interface_is_rgmii(phydev)) {
-   ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
-   (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
-   (dp83867->fifo_depth << 
DP83867_PHYCR_FIFO_DEPTH_SHIFT));
-   if (ret)
+   val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
+   if (val < 0)
goto err_out;
+   val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
+   val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 
/* The code below checks if "port mirroring" N/A MODE4 has been
 * enabled during power on bootstrap.
@@ -293,16 +293,39 @@ static int dp83867_config(struct phy_device *phydev)
 * register's bit 11 (marked as RESERVED).
 */
 
-   bs = phy_read_mmd(phydev, DP83867_DEVADDR,
- DP83867_STRAP_STS1);
-   val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
-   if (bs & DP83867_STRAP_STS1_RESERVED) {
+   bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
+   if (bs & DP83867_STRAP_STS1_RESERVED)
val &= ~DP83867_PHYCR_RESERVED_MASK;
-   phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
- val);
-   }
 
-   } else if (phy_interface_is_sgmii(phydev)) {
+   ret = phy_write(phydev, MDIO_DEVAD_NONE,
+   MII_DP83867_PHYCTRL, val);
+
+   val = phy_read_mmd(phydev, DP83867_DEVADDR,
+  DP83867_RGMIICTL);
+
+   val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
+DP83867_RGMII_RX_CLK_DELAY_EN);
+   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+   val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
+   DP83867_RGMII_RX_CLK_DELAY_EN);
+
+   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+   val |= DP83867_RGMII_TX_CLK_DELAY_EN;
+
+   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+   val |= DP83867_RGMII_RX_CLK_DELAY_EN;
+
+   phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
+
+   delay = (dp83867->rx_id_delay |
+   (dp83867->tx_id_delay <<
+   DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+
+   phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_RGMIIDCTL, delay);
+   }
+
+   if (phy_interface_is_sgmii(phydev)) {
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 
@@ -327,32 +350,6 @@ static int dp83867_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
}
 
-   if (phy_interface_is_rgmii(phydev)) {
-   val = phy_read_mmd(phydev, DP83867_DEVADDR,
-  DP83867_RGMIICTL);
-
-   val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
-DP83867_RGMII_RX_CLK_DELAY_EN);
-   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
-   val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
-   DP83867_RGMII_RX_CLK_DELAY_EN);
-
-   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
-   val |= DP83867_RGMII_TX_CLK_DELAY_EN;
-
-   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
-   val |= DP83867_RGMII_RX_CLK_DELAY_EN;
-
-   phy_write_mmd(phydev, DP83867_DEVADDR,
- DP83867_RGMIICTL, val);
-
-   delay = (dp83867->rx_

[U-Boot] [PATCH 6/8] net: phy: dp83867: io impedance is not dependent on RGMII delay

[Grygorii Strashko]

Based on commit 27708eb5481b ("net: phy: dp83867: IO impedance is not
dependent on RGMII delay") of mainline linux kernel.

The driver would only set the IO impedance value when RGMII internal delays
were enabled.  There is no reason for this.  Move the IO impedance block
out of the RGMII delay block.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/phy/dp83867.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 1721f6892b..f9bb925646 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -351,17 +351,17 @@ static int dp83867_config(struct phy_device *phydev)
 
phy_write_mmd(phydev, DP83867_DEVADDR,
  DP83867_RGMIIDCTL, delay);
+   }
 
-   if (dp83867->io_impedance >= 0) {
-   val = phy_read_mmd(phydev,
-  DP83867_DEVADDR,
-  DP83867_IO_MUX_CFG);
-   val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
-   val |= dp83867->io_impedance &
-  DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
-   phy_write_mmd(phydev, DP83867_DEVADDR,
- DP83867_IO_MUX_CFG, val);
-   }
+   if (dp83867->io_impedance >= 0) {
+   val = phy_read_mmd(phydev,
+  DP83867_DEVADDR,
+  DP83867_IO_MUX_CFG);
+   val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
+   val |= dp83867->io_impedance &
+  DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
+   phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG, val);
}
 
if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
-- 
2.17.1

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[U-Boot] [PATCH 5/8] net: phy: dp83867: rework delay rgmii delay handling

[Grygorii Strashko]

Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay
handling") of mainline linux kernel.

The current code is assuming the reset default of the delay control
register was to have delay disabled.  This is what the datasheet shows as
the register's initial value.  However, that's not actually true: the
default is controlled by the PHY's pin strapping.

This patch:
- insures the other direction's delay is disabled If the interface mode is
selected as RX or TX delay only
- validates the delay values and fail if they are not in range
- checks if the board is strapped to have a delay and is configured to use
"rgmii" mode and warning is generated that "rgmii-id" should have been
used.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/phy/dp83867.c | 76 ---
 1 file changed, 64 insertions(+), 12 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index cd3c1c596a..1721f6892b 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -25,6 +25,7 @@
 #define DP83867_CFG4   0x0031
 #define DP83867_RGMIICTL   0x0032
 #define DP83867_STRAP_STS1 0x006E
+#define DP83867_STRAP_STS2 0x006f
 #define DP83867_RGMIIDCTL  0x0086
 #define DP83867_IO_MUX_CFG 0x0170
 
@@ -52,6 +53,13 @@
 /* STRAP_STS1 bits */
 #define DP83867_STRAP_STS1_RESERVEDBIT(11)
 
+/* STRAP_STS2 bits */
+#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASKGENMASK(6, 4)
+#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT   4
+#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASKGENMASK(2, 0)
+#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT   0
+#define DP83867_STRAP_STS2_CLK_SKEW_NONE   BIT(2)
+
 /* PHY CTRL bits */
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
 #define DP83867_PHYCR_RESERVED_MASKBIT(11)
@@ -63,7 +71,9 @@
 #define DP83867_PHYCTRL_TXFIFO_SHIFT   14
 
 /* RGMIIDCTL bits */
+#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT   4
+#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
 
 /* CFG2 bits */
 #define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
@@ -74,8 +84,6 @@
 #define MII_DP83867_CFG2_MASK  0x003F
 
 /* User setting - can be taken from DTS */
-#define DEFAULT_RX_ID_DELAYDP83867_RGMIIDCTL_2_25_NS
-#define DEFAULT_TX_ID_DELAYDP83867_RGMIIDCTL_2_75_NS
 #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
 
 /* IO_MUX_CFG bits */
@@ -98,8 +106,8 @@ enum {
 };
 
 struct dp83867_private {
-   int rx_id_delay;
-   int tx_id_delay;
+   u32 rx_id_delay;
+   u32 tx_id_delay;
int fifo_depth;
int io_impedance;
bool rxctrl_strap_quirk;
@@ -168,13 +176,55 @@ static int dp83867_of_init(struct phy_device *phydev)
 
if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
dp83867->rxctrl_strap_quirk = true;
-   dp83867->rx_id_delay = ofnode_read_u32_default(node,
-  "ti,rx-internal-delay",
-  DEFAULT_RX_ID_DELAY);
 
-   dp83867->tx_id_delay = ofnode_read_u32_default(node,
-  "ti,tx-internal-delay",
-  DEFAULT_TX_ID_DELAY);
+   /* Existing behavior was to use default pin strapping delay in rgmii
+* mode, but rgmii should have meant no delay.  Warn existing users.
+*/
+   if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
+   u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
+  DP83867_STRAP_STS2);
+   u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
+DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
+   u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
+DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
+
+   if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
+   rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
+   pr_warn("PHY has delays via pin strapping, but phy-mode 
= 'rgmii'\n"
+   "Should be 'rgmii-id' to use internal 
delays\n");
+   }
+
+   /* RX delay *must* be specified if internal delay of RX is used. */
+   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+   phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+   ret = ofnode_read_u32(node, "ti,rx-internal-delay",
+ >rx_id_delay);
+   if (ret) {
+   pr_debug("ti,rx-internal-delay must be specified\n");
+   return ret;
+   }
+   if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELA

[U-Boot] [PATCH 4/8] net: phy: dp83867: Add ability to disable output clock

[Grygorii Strashko]

Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable
output clock") of mainline linux kernel.

Generally, the output clock pin is only used for testing and only serves as
a source of RF noise after this.  It could be used to daisy-chain PHYs, but
this is uncommon.  Since the PHY can disable the output, make doing so an
option.  I do this by adding another enumeration to the allowed values of
ti,clk-output-sel.

The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might
expect: to select the REF_CLK as the output.  Rather it meant "keep clock
output setting as is", which, depending on PHY strapping, might not be
outputting REF_CLK.

Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output.
Omitting the property will leave the setting as is (which was the previous
behavior in this case).

Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK.
Change this so they generate an error.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/phy/dp83867.c | 53 ++-
 1 file changed, 36 insertions(+), 17 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 8dc2163342..cd3c1c596a 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -83,6 +83,7 @@
 
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX0x0
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN0x1f
+#define DP83867_IO_MUX_CFG_CLK_O_DISABLE   BIT(6)
 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK  \
GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
@@ -103,6 +104,7 @@ struct dp83867_private {
int io_impedance;
bool rxctrl_strap_quirk;
int port_mirroring;
+   bool set_clk_output;
unsigned int clk_output_sel;
 };
 
@@ -134,16 +136,28 @@ static int dp83867_of_init(struct phy_device *phydev)
 {
struct dp83867_private *dp83867 = phydev->priv;
ofnode node;
-   u16 val;
+   int ret;
 
node = phy_get_ofnode(phydev);
if (!ofnode_valid(node))
return -EINVAL;
 
-   /* Keep the default value if ti,clk-output-sel is not set */
-   dp83867->clk_output_sel =
-   ofnode_read_u32_default(node, "ti,clk-output-sel",
-   DP83867_CLK_O_SEL_REF_CLK);
+   /* Optional configuration */
+   ret = ofnode_read_u32(node, "ti,clk-output-sel",
+ >clk_output_sel);
+   /* If not set, keep default */
+   if (!ret) {
+   dp83867->set_clk_output = true;
+   /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
+* DP83867_CLK_O_SEL_OFF.
+*/
+   if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
+   dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
+   pr_debug("ti,clk-output-sel value %u out of range\n",
+dp83867->clk_output_sel);
+   return -EINVAL;
+   }
+   }
 
if (ofnode_read_bool(node, "ti,max-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
@@ -170,18 +184,6 @@ static int dp83867_of_init(struct phy_device *phydev)
if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 
-
-   /* Clock output selection if muxing property is set */
-   if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
-   val = phy_read_mmd(phydev, DP83867_DEVADDR,
-  DP83867_IO_MUX_CFG);
-   val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
-   val |= (dp83867->clk_output_sel <<
-   DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
-   phy_write_mmd(phydev, DP83867_DEVADDR,
- DP83867_IO_MUX_CFG, val);
-   }
-
return 0;
 }
 #else
@@ -313,6 +315,23 @@ static int dp83867_config(struct phy_device *phydev)
if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
dp83867_config_port_mirroring(phydev);
 
+   /* Clock output selection if muxing property is set */
+   if (dp83867->set_clk_output) {
+   val = phy_read_mmd(phydev, DP83867_DEVADDR,
+  DP83867_IO_MUX_CFG);
+
+   if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
+   val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
+   } else {
+   val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
+DP83867_IO_MUX_CFG_CLK_O_DISABLE);
+   val |= dp83867->clk_output_sel <<
+  DP83867_IO_MUX_C

[U-Boot] [PATCH 3/8] dt-bindings: phy: dp83867: Add documentation for disabling clock output

[Grygorii Strashko]

Based on commit 980066e6d964 ("dt-bindings: phy: dp83867: Add documentation
for disabling clock output") of mainline linux kernel.

The clock output is generally only used for testing and development and not
used to daisy-chain PHYs.  It's just a source of RF noise afterward.

Add a mux value for "off".  I've added it as another enumeration to the
output property.  In the actual PHY, the mux and the output enable are
independently controllable.  However, it doesn't seem useful to be able
to describe the mux setting when the output is disabled.

Document that PHY's default setting will be left as is if the property
is omitted.

Signed-off-by: Grygorii Strashko 
---
 doc/device-tree-bindings/net/ti,dp83867.txt | 6 --
 include/dt-bindings/net/ti-dp83867.h| 3 ++-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt 
b/doc/device-tree-bindings/net/ti,dp83867.txt
index 034146f5f8..268220964a 100644
--- a/doc/device-tree-bindings/net/ti,dp83867.txt
+++ b/doc/device-tree-bindings/net/ti,dp83867.txt
@@ -12,8 +12,10 @@ Required properties:
compensate for the board being designed with the lanes swapped.
- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
TX/RX lanes.
-   - ti,clk-output-sel - Clock output select - see 
dt-bindings/net/ti-dp83867.h
-   for applicable values
+   - ti,clk-output-sel - Muxing option for CLK_OUT pin.  See 
dt-bindings/net/ti-dp83867.h
+ for applicable values.  The CLK_OUT pin can also
+ be disabled by this property.  When omitted, the
+ PHY's default will be left as is.
 
 Default child nodes are standard Ethernet PHY device
 nodes as described in doc/devicetree/bindings/net/ethernet.txt
diff --git a/include/dt-bindings/net/ti-dp83867.h 
b/include/dt-bindings/net/ti-dp83867.h
index 85d08f6974..cde5aa7e27 100644
--- a/include/dt-bindings/net/ti-dp83867.h
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -45,5 +45,6 @@
 #define DP83867_CLK_O_SEL_CHN_C_TCLK   0xA
 #define DP83867_CLK_O_SEL_CHN_D_TCLK   0xB
 #define DP83867_CLK_O_SEL_REF_CLK  0xC
-
+/* Special flag to indicate clock should be off */
+#define DP83867_CLK_O_SEL_OFF  0x
 #endif
-- 
2.17.1

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[U-Boot] [PATCH 1/8] net: phy: ti: rename ti.c to dp83867.c

[Grygorii Strashko]

The driver ti.c is actually driver for TI DP83867x PHYs, so rename it
accordingly.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/phy/Makefile| 2 +-
 drivers/net/phy/{ti.c => dp83867.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename drivers/net/phy/{ti.c => dp83867.c} (100%)

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 76b6197009..78955c57a8 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
 obj-$(CONFIG_PHY_REALTEK) += realtek.o
 obj-$(CONFIG_PHY_SMSC) += smsc.o
 obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
-obj-$(CONFIG_PHY_TI) += ti.o
+obj-$(CONFIG_PHY_TI) += dp83867.o
 obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
 obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
 obj-$(CONFIG_PHY_VITESSE) += vitesse.o
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/dp83867.c
similarity index 100%
rename from drivers/net/phy/ti.c
rename to drivers/net/phy/dp83867.c
-- 
2.17.1

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[U-Boot] [PATCH 2/8] net: phy: dp83867: move static initialization to .probe()

[Grygorii Strashko]

Move static, one-time initialization to .probe() callback.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/phy/dp83867.c | 29 +
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 7509936465..8dc2163342 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -204,18 +204,11 @@ static int dp83867_config(struct phy_device *phydev)
unsigned int val, delay, cfg2;
int ret, bs;
 
-   if (!phydev->priv) {
-   dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
-   if (!dp83867)
-   return -ENOMEM;
+   dp83867 = (struct dp83867_private *)phydev->priv;
 
-   phydev->priv = dp83867;
-   ret = dp83867_of_init(phydev);
-   if (ret)
-   goto err_out;
-   } else {
-   dp83867 = (struct dp83867_private *)phydev->priv;
-   }
+   ret = dp83867_of_init(phydev);
+   if (ret)
+   return ret;
 
/* Restart the PHY.  */
val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
@@ -324,15 +317,27 @@ static int dp83867_config(struct phy_device *phydev)
return 0;
 
 err_out:
-   kfree(dp83867);
return ret;
 }
 
+static int dp83867_probe(struct phy_device *phydev)
+{
+   struct dp83867_private *dp83867;
+
+   dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
+   if (!dp83867)
+   return -ENOMEM;
+
+   phydev->priv = dp83867;
+   return 0;
+}
+
 static struct phy_driver DP83867_driver = {
.name = "TI DP83867",
.uid = 0x2000a231,
.mask = 0xfff0,
.features = PHY_GBIT_FEATURES,
+   .probe = dp83867_probe,
.config = _config,
.startup = _startup,
.shutdown = _shutdown,
-- 
2.17.1

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[U-Boot] [PATCH 0/8] net: phy: dp83867: ti: sync with linux kernel and

[Grygorii Strashko]

hi

The intention of this series is to sync TI DP83867 driver with mainline Linux
kernel and ensure that proper PHY configuration in "rgmii-rxid" mode, which
is done in the Patch 8.

It also some code refactoring and optimization: patches 2,7.

Grygorii Strashko (8):
  net: phy: ti: rename ti.c to dp83867.c
  net: phy: dp83867: move static initialization to .probe()
  dt-bindings: phy: dp83867: Add documentation for disabling clock
output
  net: phy: dp83867: Add ability to disable output clock
  net: phy: dp83867: rework delay rgmii delay handling
  net: phy: dp83867: io impedance is not dependent on RGMII delay
  net: phy: dp83867: refactor rgmii configuration
  arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to
rgmii-rxid

 arch/arm/dts/k3-am654-base-board-u-boot.dtsi |   3 +-
 doc/device-tree-bindings/net/ti,dp83867.txt  |   6 +-
 drivers/net/phy/Makefile |   2 +-
 drivers/net/phy/{ti.c => dp83867.c}  | 243 ---
 include/dt-bindings/net/ti-dp83867.h |   3 +-
 5 files changed, 166 insertions(+), 91 deletions(-)
 rename drivers/net/phy/{ti.c => dp83867.c} (63%)

-- 
2.17.1

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Re: [U-Boot] [PATCH 02/11] dma: ti: k3-udma: Query DMA channels allocated from Resource Manager

[Grygorii Strashko]

On 14/11/2019 11:14, Vignesh Raghavendra wrote:

On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.

Signed-off-by: Vignesh Raghavendra 
---
  drivers/dma/ti/k3-udma-hwdef.h |  19 
  drivers/dma/ti/k3-udma.c   | 179 -
  2 files changed, 171 insertions(+), 27 deletions(-)

diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h
index c88399a815ea..228a44cb73cf 100644
--- a/drivers/dma/ti/k3-udma-hwdef.h
+++ b/drivers/dma/ti/k3-udma-hwdef.h
@@ -181,4 +181,23 @@
  #define PDMA_STATIC_TR_Z(x)   \
(((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK)
  
+enum udma_rm_range {

+   RM_RANGE_TCHAN = 0,
+   RM_RANGE_RCHAN,
+   RM_RANGE_RFLOW,
+   RM_RANGE_LAST,
+};
+
+struct udma_tisci_rm {
+   const struct ti_sci_handle *tisci;
+   const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
+   u32  tisci_dev_id;
+
+   /* tisci information for PSI-L thread pairing/unpairing */
+   const struct ti_sci_rm_psil_ops *tisci_psil_ops;
+   u32  tisci_navss_dev_id;
+
+   struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];


it looks like TBD. only rm_ranges field is used.


+};
+
  #endif /* K3_NAVSS_UDMA_HWDEF_H_ */
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index a5fc7809bc41..2380780879f5 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -11,12 +11,14 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -30,6 +32,8 @@
  #define RINGACC_RING_USE_PROXY(1)
  #endif
  
+#define K3_UDMA_MAX_RFLOWS 1024

+
  struct udma_chan;
  
  enum udma_mmr {

@@ -64,9 +68,10 @@ struct udma_rflow {
  };
  
  struct udma_dev {

-   struct device *dev;
+   struct udevice *dev;
void __iomem *mmrs[MMR_LAST];
  
+	struct udma_tisci_rm tisci_rm;

struct k3_nav_ringacc *ringacc;
  
  	u32 features;

@@ -78,6 +83,7 @@ struct udma_dev {
unsigned long *tchan_map;
unsigned long *rchan_map;
unsigned long *rflow_map;
+   unsigned long *rflow_map_reserved;
  
  	struct udma_tchan *tchans;

struct udma_rchan *rchans;
@@ -535,6 +541,28 @@ static void udma_poll_completion(struct udma_chan *uc, 
dma_addr_t *paddr)
}
  }
  
+static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id)

+{
+   DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
+
+   if (id >= 0) {
+   if (test_bit(id, ud->rflow_map)) {
+   dev_err(ud->dev, "rflow%d is in use\n", id);
+   return ERR_PTR(-ENOENT);
+   }
+   } else {
+   bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved,
+ ud->rflow_cnt);
+
+   id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt);
+   if (id >= ud->rflow_cnt)
+   return ERR_PTR(-ENOENT);
+   }
+
+   __set_bit(id, ud->rflow_map);
+   return >rflows[id];
+}
+
  #define UDMA_RESERVE_RESOURCE(res)\
  static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud,   \
   int id)  \
@@ -557,7 +585,6 @@ static struct udma_##res *__udma_reserve_##res(struct 
udma_dev *ud, \
  
  UDMA_RESERVE_RESOURCE(tchan);

  UDMA_RESERVE_RESOURCE(rchan);
-UDMA_RESERVE_RESOURCE(rflow);
  
  static int udma_get_tchan(struct udma_chan *uc)

  {
@@ -1103,14 +1130,129 @@ static int udma_get_mmrs(struct udevice *dev)
return 0;
  }
  
-#define UDMA_MAX_CHANNELS	192

+static int udma_setup_resources(struct udma_dev *ud)
+{
+   struct udevice *dev = ud->dev;
+   int ch_count, i;
+   u32 cap2, cap3;
+   struct ti_sci_resource_desc *rm_desc;
+   struct ti_sci_resource *rm_res;
+   struct udma_tisci_rm *tisci_rm = >tisci_rm;
+   static const char * const range_names[] = { "ti,sci-rm-range-tchan",
+   "ti,sci-rm-range-rchan",
+   "ti,sci-rm-range-rflow" };
+
+   cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
+   cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
+
+   ud->rflow_cnt = cap3 & 0x3fff;
+   ud->tchan_cnt = cap2 & 0x1ff;
+   ud->echan_cnt = (cap2 >> 9) & 0x1ff;
+   ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+   ch_count  = ud->tchan_cnt + ud->rchan_cnt;
+
+   ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+  sizeof(unsigned long), GFP_KERNEL);
+   ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ 

Re: [U-Boot] [PATCH v4 4/5] doc: bindings: add mdio-handle property to ethernet nodes

[Grygorii Strashko]

On 14/11/2019 17:04, Alex Marginean wrote:

Adds an optional mdio-handle property which identifies a MDIO bus which can
be scanned to find the relevant PHY.  The property is ignored if phy-handle
is also present.

Signed-off-by: Alex Marginean 
---
  doc/device-tree-bindings/net/ethernet.txt | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/doc/device-tree-bindings/net/ethernet.txt 
b/doc/device-tree-bindings/net/ethernet.txt
index 3fc360523b..9f9629f8d6 100644
--- a/doc/device-tree-bindings/net/ethernet.txt
+++ b/doc/device-tree-bindings/net/ethernet.txt
@@ -9,6 +9,8 @@ The following properties are common to the Ethernet controllers:
  - max-speed: number, specifies maximum speed in Mbit/s supported by the 
device;
  - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather 
than
the maximum frame size (there's contradiction in ePAPR).
+- mdio-handle: phandle, specifies a reference to a MDIO bus to be scanned to
+  find the PHY device.  Ignored if phy-handle is also present.


Sry, but it looks redundant. The Ethernet-controller bindings
expects to use phy-handle which, in turn, allows to get MDIO node.

So, if your platform is DT based and can use DT then it's reasonable to follow 
standard binding,
which, in addition, allows to specify Ethernet PHY properties.
More over, your series does not provide user for this new property.

Personally I do not see even reasons to have 
doc/device-tree-bindings/net/ethernet.txt in u-boot
and think we should follow [1]


  - phy-mode: string, operation mode of the PHY interface; supported values are
"mii", "gmii", "sgmii", "qsgmii", "tbi", "rev-mii", "rmii", "rgmii", 
"rgmii-id",
"rgmii-rxid", "rgmii-txid", "rtbi", "smii", "xgmii"; this is now a de-facto



[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/ethernet-controller.yaml

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Re: [U-Boot] [PATCH] net: cpsw: Add NULL pointer check

[Grygorii Strashko]

On 11/11/2019 11:52, Faiz Abbas wrote:

Add null pointer check to take care of out of memory errors.

Signed-off-by: Faiz Abbas 
---
  drivers/net/ti/cpsw.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 4a990be93e..b710ae4053 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -1223,6 +1223,9 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice 
*dev)
int ret;
  
  	data = calloc(1, sizeof(struct cpsw_platform_data));

+   if (!data)
+   return -ENOMEM;
+
pdata->priv_pdata = data;
pdata->iobase = dev_read_addr(dev);
data->version = CPSW_CTRL_VERSION_2;



Reviewed-by: Grygorii Strashko 

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Re: [U-Boot] [PATCH v2 0/6] net: ti: set of fixes and improvements

[Grygorii Strashko]

Hi Joe, Tom

On 19/09/2019 11:16, Grygorii Strashko wrote:

Hi All,

This series introduces set of fixes and improvements for TI CPSW and AM654x
CPSW networking drivers.

Patch 1 - Enables support of 10Mbit link speeds for TI CPSW driver.
Patch 3 - Adds support of standard Ethernet "max-speed" DT property.
Patches 4-5 - fix mac tx internal delay for rgmii-rxid mode
Patches 2,6 - are code improvements

Changes in v2:
- fixed network init in Patch 3

v1:
  https://patchwork.ozlabs.org/cover/1159782/

Grygorii Strashko (6):
   net: ti: cpsw: enable 10Mbps link speed support in rgmii mode
   net: ti: cpsw: move parsing of dt port's parameters in separate func
   net: ti: cpsw: add support for standard eth "max-speed" dt property
   net: ti: cpsw: fix mac tx internal delay for rgmii-rxid mode
   net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid mode
   net: ti: cpsw: convert to use dev/ofnode api

  drivers/net/ti/am65-cpsw-nuss.c |   2 +-
  drivers/net/ti/cpsw.c   | 154 +---
  include/cpsw.h  |   3 +-
  3 files changed, 84 insertions(+), 75 deletions(-)



Are there any comments? can it be merged?

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Re: [U-Boot] [PATCH 0/3] arm: dts: ti: sync cpsw/mdio/phy with latest linux 1 - drop phy_id

[Grygorii Strashko]

Hi Tom, All,

On 04/09/2019 11:38, Lokesh Vutla wrote:



On 31/08/19 1:00 PM, Grygorii Strashko wrote:

Synchronize CPSW/MDIO/PHY DT nodes with latest linux - replace deprecated
phy_id property with phy-handle.


For the series:
Reviewed-by: Lokesh Vutla 



Are there anything else I need to do to have this merged?
Sry, for impatience.

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[U-Boot] [PATCH v2 6/6] net: ti: cpsw: convert to use dev/ofnode api

[Grygorii Strashko]

Conver TI CPSW driver to use dev/ofnode api.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 119 ++
 include/cpsw.h|   2 +-
 2 files changed, 51 insertions(+), 70 deletions(-)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 408983401f..4a990be93e 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -19,12 +19,9 @@
 #include 
 #include 
 #include 
-#include 
 
 #include "cpsw_mdio.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define BITMASK(bits)  (BIT(bits) - 1)
 #define NUM_DESCS  (PKTBUFSRX * 2)
 #define PKT_MIN60
@@ -860,8 +857,8 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct 
cpsw_slave *slave)
phydev->advertising = phydev->supported;
 
 #ifdef CONFIG_DM_ETH
-   if (slave->data->phy_of_handle)
-   phydev->node = offset_to_ofnode(slave->data->phy_of_handle);
+   if (ofnode_valid(slave->data->phy_of_handle))
+   phydev->node = slave->data->phy_of_handle;
 #endif
 
priv->phydev = phydev;
@@ -1049,12 +1046,6 @@ static const struct eth_ops cpsw_eth_ops = {
.stop   = cpsw_eth_stop,
 };
 
-static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
-{
-   return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL,
- false);
-}
-
 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
 phy_interface_t phy_mode)
 {
@@ -1188,39 +1179,37 @@ static int cpsw_eth_probe(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
-   int slave_index, int subnode)
+   int slave_index, ofnode subnode)
 {
-   struct cpsw_slave_data  *slave_data;
-   const void *fdt = gd->fdt_blob;
+   struct ofnode_phandle_args out_args;
+   struct cpsw_slave_data *slave_data;
const char *phy_mode;
-   int max_speed = -1;
u32 phy_id[2];
+   int ret;
 
slave_data = >slave_data[slave_index];
 
-   phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
+   phy_mode = ofnode_read_string(subnode, "phy-mode");
if (phy_mode)
-   slave_data->phy_if =
-   phy_get_interface_by_name(phy_mode);
+   slave_data->phy_if = phy_get_interface_by_name(phy_mode);
 
-   slave_data->phy_of_handle = fdtdec_lookup_phandle(fdt, subnode,
- "phy-handle");
+   ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
+NULL, 0, 0, _args);
+   if (!ret) {
+   slave_data->phy_of_handle = out_args.node;
 
-   if (data->slave_data[slave_index].phy_of_handle >= 0) {
-   slave_data->phy_addr =
-   fdtdec_get_int(fdt, slave_data->phy_of_handle,
-  "reg", -1);
+   ret = ofnode_read_s32(slave_data->phy_of_handle, "reg",
+ _data->phy_addr);
+   if (ret)
+   printf("error: phy addr not found in dt\n");
} else {
-   fdtdec_get_int_array(fdt, subnode, "phy_id",
-phy_id, 2);
-   slave_data->phy_addr = phy_id[1];
+   ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2);
+   if (ret)
+   printf("error: phy_id read failed\n");
}
 
-   slave_data->max_speed = 0;
-   max_speed = fdtdec_get_int(fdt, subnode,
-  "max-speed", max_speed);
-   if (max_speed > 0)
-   slave_data->max_speed = max_speed;
+   slave_data->max_speed = ofnode_read_s32_default(subnode,
+   "max-speed", 0);
 }
 
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
@@ -1228,17 +1217,14 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice 
*dev)
struct eth_pdata *pdata = dev_get_platdata(dev);
struct cpsw_platform_data *data;
struct gpio_desc *mode_gpios;
-   const void *fdt = gd->fdt_blob;
-   int node = dev_of_offset(dev);
-   int subnode;
int slave_index = 0;
-   int active_slave;
int num_mode_gpios;
+   ofnode subnode;
int ret;
 
data = calloc(1, sizeof(struct cpsw_platform_data));
pdata->priv_pdata = data;
-   pdata->iobase = devfdt_get_addr(dev);
+   pdata->iobase = dev_read_addr(dev);
data->version = CPSW_CTRL

[U-Boot] [PATCH v2 5/6] net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid mode

[Grygorii Strashko]

Now AM65x CPSW2G driver will disable MAC TX internal delay for PHY
interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping
default value (enabled) for MAC TX internal delay when "rgmii-rxid"
interface mode is selected.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/am65-cpsw-nuss.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index e11fbdeed3..06b0663950 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -234,11 +234,11 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv 
*priv,
break;
 
case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_RXID:
mode = AM65_GMII_SEL_MODE_RGMII;
break;
 
case PHY_INTERFACE_MODE_RGMII_ID:
-   case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
mode = AM65_GMII_SEL_MODE_RGMII;
rgmii_id = true;
-- 
2.17.1

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[U-Boot] [PATCH v2 2/6] net: ti: cpsw: move parsing of dt port's parameters in separate func

[Grygorii Strashko]

Move parsing of dt port's parameters in separate func for better code
readability.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 57 +--
 1 file changed, 33 insertions(+), 24 deletions(-)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index f0d008f0f5..533c167995 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -1179,12 +1179,40 @@ static int cpsw_eth_probe(struct udevice *dev)
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
+static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
+   int slave_index, int subnode)
+{
+   struct cpsw_slave_data  *slave_data;
+   const void *fdt = gd->fdt_blob;
+   const char *phy_mode;
+   u32 phy_id[2];
+
+   slave_data = >slave_data[slave_index];
+
+   phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
+   if (phy_mode)
+   slave_data->phy_if =
+   phy_get_interface_by_name(phy_mode);
+
+   slave_data->phy_of_handle = fdtdec_lookup_phandle(fdt, subnode,
+ "phy-handle");
+
+   if (data->slave_data[slave_index].phy_of_handle >= 0) {
+   slave_data->phy_addr =
+   fdtdec_get_int(fdt, slave_data->phy_of_handle,
+  "reg", -1);
+   } else {
+   fdtdec_get_int_array(fdt, subnode, "phy_id",
+phy_id, 2);
+   slave_data->phy_addr = phy_id[1];
+   }
+}
+
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_platdata(dev);
struct cpsw_platform_data *data;
struct gpio_desc *mode_gpios;
-   const char *phy_mode;
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int subnode;
@@ -1267,30 +1295,10 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice 
*dev)
}
 
if (!strncmp(name, "slave", 5)) {
-   u32 phy_id[2];
-
if (slave_index >= data->slaves)
continue;
-   phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
-   if (phy_mode)
-   data->slave_data[slave_index].phy_if =
-   phy_get_interface_by_name(phy_mode);
-
-   data->slave_data[slave_index].phy_of_handle =
-   fdtdec_lookup_phandle(fdt, subnode,
- "phy-handle");
-
-   if (data->slave_data[slave_index].phy_of_handle >= 0) {
-   data->slave_data[slave_index].phy_addr =
-   fdtdec_get_int(gd->fdt_blob,
-   
data->slave_data[slave_index].phy_of_handle,
-  "reg", -1);
-   } else {
-   fdtdec_get_int_array(fdt, subnode, "phy_id",
-phy_id, 2);
-   data->slave_data[slave_index].phy_addr =
-   phy_id[1];
-   }
+
+   cpsw_eth_of_parse_slave(data, slave_index, subnode);
slave_index++;
}
 
@@ -1331,7 +1339,8 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice 
*dev)
 
pdata->phy_interface = data->slave_data[active_slave].phy_if;
if (pdata->phy_interface == -1) {
-   debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+   debug("%s: Invalid PHY interface '%s'\n", __func__,
+ phy_string_for_interface(pdata->phy_interface));
return -EINVAL;
}
 
-- 
2.17.1

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[U-Boot] [PATCH v2 4/6] net: ti: cpsw: fix mac tx internal delay for rgmii-rxid mode

[Grygorii Strashko]

Now TI CPSW driver will disable MAC TX internal delay for PHY interface
mode "rgmii-rxid" which is incorrect.

Hence, fix it by keeping default value (enabled) for MAC TX internal delay
when "rgmii-rxid" interface mode is selected.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 24265360e6..408983401f 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -1072,10 +1072,10 @@ static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
break;
 
case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_RXID:
mode = AM33XX_GMII_SEL_MODE_RGMII;
break;
case PHY_INTERFACE_MODE_RGMII_ID:
-   case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
mode = AM33XX_GMII_SEL_MODE_RGMII;
rgmii_id = true;
-- 
2.17.1

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[U-Boot] [PATCH v2 3/6] net: ti: cpsw: add support for standard eth "max-speed" dt property

[Grygorii Strashko]

This patch adds support for standard Ethernet "max-speed" DT property to
allow PHY link speed limitation.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 15 +++
 include/cpsw.h|  1 +
 2 files changed, 16 insertions(+)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 533c167995..24265360e6 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -839,6 +839,7 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct 
cpsw_slave *slave)
 {
struct phy_device *phydev;
u32 supported = PHY_GBIT_FEATURES;
+   int ret;
 
phydev = phy_connect(priv->bus,
slave->data->phy_addr,
@@ -849,6 +850,13 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct 
cpsw_slave *slave)
return -1;
 
phydev->supported &= supported;
+   if (slave->data->max_speed) {
+   ret = phy_set_supported(phydev, slave->data->max_speed);
+   if (ret)
+   return ret;
+   dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
+   slave->slave_num + 1, slave->data->max_speed);
+   }
phydev->advertising = phydev->supported;
 
 #ifdef CONFIG_DM_ETH
@@ -1185,6 +1193,7 @@ static void cpsw_eth_of_parse_slave(struct 
cpsw_platform_data *data,
struct cpsw_slave_data  *slave_data;
const void *fdt = gd->fdt_blob;
const char *phy_mode;
+   int max_speed = -1;
u32 phy_id[2];
 
slave_data = >slave_data[slave_index];
@@ -1206,6 +1215,12 @@ static void cpsw_eth_of_parse_slave(struct 
cpsw_platform_data *data,
 phy_id, 2);
slave_data->phy_addr = phy_id[1];
}
+
+   slave_data->max_speed = 0;
+   max_speed = fdtdec_get_int(fdt, subnode,
+  "max-speed", max_speed);
+   if (max_speed > 0)
+   slave_data->max_speed = max_speed;
 }
 
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
diff --git a/include/cpsw.h b/include/cpsw.h
index 96ff254f98..c7532fc866 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -39,6 +39,7 @@ struct cpsw_slave_data {
int phy_addr;
int phy_if;
int phy_of_handle;
+   int max_speed;
 };
 
 enum {
-- 
2.17.1

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[U-Boot] [PATCH v2 0/6] net: ti: set of fixes and improvements

[Grygorii Strashko]

Hi All,

This series introduces set of fixes and improvements for TI CPSW and AM654x
CPSW networking drivers.

Patch 1 - Enables support of 10Mbit link speeds for TI CPSW driver.
Patch 3 - Adds support of standard Ethernet "max-speed" DT property.
Patches 4-5 - fix mac tx internal delay for rgmii-rxid mode
Patches 2,6 - are code improvements

Changes in v2:
- fixed network init in Patch 3

v1: 
 https://patchwork.ozlabs.org/cover/1159782/

Grygorii Strashko (6):
  net: ti: cpsw: enable 10Mbps link speed support in rgmii mode
  net: ti: cpsw: move parsing of dt port's parameters in separate func
  net: ti: cpsw: add support for standard eth "max-speed" dt property
  net: ti: cpsw: fix mac tx internal delay for rgmii-rxid mode
  net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid mode
  net: ti: cpsw: convert to use dev/ofnode api

 drivers/net/ti/am65-cpsw-nuss.c |   2 +-
 drivers/net/ti/cpsw.c   | 154 +---
 include/cpsw.h  |   3 +-
 3 files changed, 84 insertions(+), 75 deletions(-)

-- 
2.17.1

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[U-Boot] [PATCH v2 1/6] net: ti: cpsw: enable 10Mbps link speed support in rgmii mode

[Grygorii Strashko]

According to TRMs the 10Mbps link speed is supported in RGMII only when
CPSW2G MAC SL is configured for External Control ("in band") mode
CPSW_SL_MACCTRL.EXT_EN(18) = 1.

Hence update cpsw_slave_update_link() to follow documentation.

[1] https://patchwork.kernel.org/patch/10285239/
Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 20ddb44dd8..f0d008f0f5 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -33,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GIGABITEN  BIT(7)
 #define FULLDUPLEXEN   BIT(0)
 #define MIIEN  BIT(15)
+#define CTL_EXT_EN BIT(18)
 /* DMA Registers */
 #define CPDMA_TXCONTROL0x004
 #define CPDMA_RXCONTROL0x014
@@ -489,6 +490,8 @@ static int cpsw_slave_update_link(struct cpsw_slave *slave,
mac_control |= FULLDUPLEXEN;
if (phy->speed == 100)
mac_control |= MIIEN;
+   if (phy->speed == 10 && phy_interface_is_rgmii(phy))
+   mac_control |= CTL_EXT_EN;
}
 
if (mac_control == slave->mac_control)
-- 
2.17.1

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Re: [U-Boot] [PATCH 3/6] net: ti: cpsw: add support for standard eth "max-speed" dt property

[Grygorii Strashko]

On 09/09/2019 18:00, Grygorii Strashko wrote:

This patch adds support for standard Ethernet "max-speed" DT property to
allow PHY link speed limitation.


This patch by itself will break network boot (see below).
But with whole series issue will not be reproducible, because it's
implicitly fixed by patch 6.

I'll send v2.



Signed-off-by: Grygorii Strashko 
---
  drivers/net/ti/cpsw.c | 14 ++
  include/cpsw.h|  1 +
  2 files changed, 15 insertions(+)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 533c167995..af4db89341 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -839,6 +839,7 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct 
cpsw_slave *slave)
  {
struct phy_device *phydev;
u32 supported = PHY_GBIT_FEATURES;
+   int ret;
  
  	phydev = phy_connect(priv->bus,

slave->data->phy_addr,
@@ -849,6 +850,13 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct 
cpsw_slave *slave)
return -1;
  
  	phydev->supported &= supported;

+   if (slave->data->max_speed) {
+   ret = phy_set_supported(phydev, slave->data->max_speed);
+   if (ret)
+   return ret;
+   dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
+   slave->slave_num + 1, slave->data->max_speed);
+   }
phydev->advertising = phydev->supported;
  
  #ifdef CONFIG_DM_ETH

@@ -1185,6 +1193,7 @@ static void cpsw_eth_of_parse_slave(struct 
cpsw_platform_data *data,
struct cpsw_slave_data  *slave_data;
const void *fdt = gd->fdt_blob;
const char *phy_mode;
+   int max_speed = -1;
u32 phy_id[2];
  
  	slave_data = >slave_data[slave_index];

@@ -1206,6 +1215,11 @@ static void cpsw_eth_of_parse_slave(struct 
cpsw_platform_data *data,
 phy_id, 2);
slave_data->phy_addr = phy_id[1];
}
+


slave_data->max_speed has to be reset to 0 here.


+   max_speed = fdtdec_get_int(fdt, subnode,
+  "max-speed", max_speed);
+   if (max_speed > 0)
+   slave_data->max_speed = max_speed;
  }
  



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Re: [U-Boot] [PATCH] watchdog: omap_wdt: Fix WDT target reset when booted from emmc

[Grygorii Strashko]

On 16/09/2019 11:09, suni...@techveda.org wrote:

From: Suniel Mahesh 

AM335X based beaglebone black target gets reset by DM converted watchdog
if booted from emmc around 60sec. Fixed this by moving driver's private struct
variable initialization at different places in the driver to driver's probe.
Tested on Beaglebone Black.

Cc: Grygorii Strashko 
Fixes: 7659ea32 ("watchdog: omap_wdt: Convert watchdog driver to use DT and DM")
Reported-by: Sam Protsenko 
Signed-off-by: Suniel Mahesh 
---
  drivers/watchdog/omap_wdt.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)



Acked-by: Grygorii Strashko 

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Re: [U-Boot] OMAP watchdog timer reset on BBB

[Grygorii Strashko]

On 16/09/2019 10:05, Suniel Mahesh wrote:

Hi all,

On 14/09/19 12:55, Sam Protsenko wrote:

Hi Grygorii,

On Fri, Sep 13, 2019 at 8:58 PM Grygorii Strashko
 wrote:




On 12/09/2019 19:33, Sam Protsenko wrote:

Hi Stefan,

On Thu, Sep 12, 2019 at 5:38 PM Stefan Roese  wrote:


Hi Sam,

On 12.09.19 15:45, Sam Protsenko wrote:

Hi Suniel,

After transition to DM WDT, watchdog timer on BeagleBone Black resets
the board after 1 minute or so. I'm using this defconfig: [1]. After
disabling CONFIG_WDT and CONFIG_WATCHDOG options the board doesn't
reset. I guess it might be happening on other boards using
CONFIG_WDT_OMAP3 as well. The issue can be reproduced by stopping in
U-Boot shell (=>) and waiting for 1 minute.

Do you know by chance why it might be happening, or maybe some fix
already exists?

Thanks!

[1] https://pastebin.ubuntu.com/p/Zz5bY6cYXS/


So you have enabled the watchdog and should see something like this
upon bootup:

WDT:   Started without servicing (60s timeout)

Is this correct? Then you need to enable the U-Boot internal WDT
servicing by enabling CONFIG_WATCHDOG as well, as this will
result in the internal U-Boot servicing of the watchdog. Then
you should see this upon bootup and no reset will appear in
U-Boot:

WDT:   Started with servicing (60s timeout)



I'm seeing this ("with servicing") line, and CONFIG_WATCHDOG is
already enabled in am335x_evm_defconfig. So I think it's an issue,
which *probably* appeared when watchdog drivers were converted to
Driver Model (this defconfig is using CONFIG_WDT + CONFIG_WDT_OMAP3
options). Any clues what can be wrong?


Does this help?

It seems logic of hw_watchdog_reset() and omap3_wdt_reset() is different.
Pay attention at wdt_trgr_pattern.

It seems that
 priv->wdt_trgr_pattern = 0x1234;
need to be moved in omap3_wdt_probe()



Thanks a lot for the investigation. I'll check that once I have some spare time.


I have done some investigation and I am unable to conclude the behaviour(though 
the problem got fixed)
Here are my observations:

watchdog timer doesn't reset the board if booted via sd-card and serial.
https://paste.ubuntu.com/p/tjcPhv4FMQ/ (sd card boot)
https://pastebin.ubuntu.com/p/X4tkp4ngMK/ (serial boot)
https://pastebin.ubuntu.com/p/WvS9PZb45p/ (serial boot with print messages)

Sam was right. watchdog timer is resetting the board after conversion to DM, 
but only if we booted via emmc.
earlier for some reason I couldn't concentrate on emmc booting. "my bad".

analyzed the behaviour, the count is getting reset in the register when ever 
watchdog_reset is called but for some reason
at around < 60s, the board gets reset (this shouldn't happen...!!). please go 
through the pastebin link:
https://pastebin.ubuntu.com/p/td6c4SQmnm/ (emmc boot)

As pointed by Grygorii, I just moved priv->wdt_trgr_pattern into probe and the 
problem disappears. didn't understand how that
change made a difference. Generally as per documentation all initializations 
are to be done in probe (but still).
Why this is not happening on the other two bootmodes (sd-card and serial) ?
Can some body shed some light for this behaviour ?


It's kinda simple - non DM code defines wdt_trgr_pattern as static so it's 
initialized only once.
Your code initializes it on every reset, so violates TRM.

TRM says:
"The specific reload sequence is performed whenever the written value on the 
WDT_WTGR register differs
from its previous value. In this case, reload is executed in the same way as an 
overflow autoreload, but
without the generation of a reset pulse."



The problem seems to be fixed, I will be patching u-boot in a while. Request 
Sam if possible to check/test/deploy the change on the
board and acknowledge. (I have already tested the changeset and its fixed at my 
end)


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Re: [U-Boot] OMAP watchdog timer reset on BBB

[Grygorii Strashko]

On 12/09/2019 19:33, Sam Protsenko wrote:

Hi Stefan,

On Thu, Sep 12, 2019 at 5:38 PM Stefan Roese  wrote:


Hi Sam,

On 12.09.19 15:45, Sam Protsenko wrote:

Hi Suniel,

After transition to DM WDT, watchdog timer on BeagleBone Black resets
the board after 1 minute or so. I'm using this defconfig: [1]. After
disabling CONFIG_WDT and CONFIG_WATCHDOG options the board doesn't
reset. I guess it might be happening on other boards using
CONFIG_WDT_OMAP3 as well. The issue can be reproduced by stopping in
U-Boot shell (=>) and waiting for 1 minute.

Do you know by chance why it might be happening, or maybe some fix
already exists?

Thanks!

[1] https://pastebin.ubuntu.com/p/Zz5bY6cYXS/


So you have enabled the watchdog and should see something like this
upon bootup:

WDT:   Started without servicing (60s timeout)

Is this correct? Then you need to enable the U-Boot internal WDT
servicing by enabling CONFIG_WATCHDOG as well, as this will
result in the internal U-Boot servicing of the watchdog. Then
you should see this upon bootup and no reset will appear in
U-Boot:

WDT:   Started with servicing (60s timeout)



I'm seeing this ("with servicing") line, and CONFIG_WATCHDOG is
already enabled in am335x_evm_defconfig. So I think it's an issue,
which *probably* appeared when watchdog drivers were converted to
Driver Model (this defconfig is using CONFIG_WDT + CONFIG_WDT_OMAP3
options). Any clues what can be wrong?


Does this help?

It seems logic of hw_watchdog_reset() and omap3_wdt_reset() is different.
Pay attention at wdt_trgr_pattern.

It seems that
priv->wdt_trgr_pattern = 0x1234;
need to be moved in omap3_wdt_probe()
 


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Re: [U-Boot] OMAP watchdog timer reset on BBB

[Grygorii Strashko]

CC: Lokesh

On 12/09/2019 16:45, Sam Protsenko wrote:

Hi Suniel,

After transition to DM WDT, watchdog timer on BeagleBone Black resets
the board after 1 minute or so. I'm using this defconfig: [1]. After
disabling CONFIG_WDT and CONFIG_WATCHDOG options the board doesn't
reset. I guess it might be happening on other boards using
CONFIG_WDT_OMAP3 as well. The issue can be reproduced by stopping in
U-Boot shell (=>) and waiting for 1 minute.

Do you know by chance why it might be happening, or maybe some fix
already exists?

Thanks!

[1] https://pastebin.ubuntu.com/p/Zz5bY6cYXS/
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[U-Boot] [PATCH 6/6] net: ti: cpsw: convert to use dev/ofnode api

[Grygorii Strashko]

Conver TI CPSW driver to use dev/ofnode api.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 118 ++
 include/cpsw.h|   2 +-
 2 files changed, 51 insertions(+), 69 deletions(-)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 55edff3b8d..4a990be93e 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -19,12 +19,9 @@
 #include 
 #include 
 #include 
-#include 
 
 #include "cpsw_mdio.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define BITMASK(bits)  (BIT(bits) - 1)
 #define NUM_DESCS  (PKTBUFSRX * 2)
 #define PKT_MIN60
@@ -860,8 +857,8 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct 
cpsw_slave *slave)
phydev->advertising = phydev->supported;
 
 #ifdef CONFIG_DM_ETH
-   if (slave->data->phy_of_handle)
-   phydev->node = offset_to_ofnode(slave->data->phy_of_handle);
+   if (ofnode_valid(slave->data->phy_of_handle))
+   phydev->node = slave->data->phy_of_handle;
 #endif
 
priv->phydev = phydev;
@@ -1049,12 +1046,6 @@ static const struct eth_ops cpsw_eth_ops = {
.stop   = cpsw_eth_stop,
 };
 
-static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
-{
-   return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL,
- false);
-}
-
 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
 phy_interface_t phy_mode)
 {
@@ -1188,38 +1179,37 @@ static int cpsw_eth_probe(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
-   int slave_index, int subnode)
+   int slave_index, ofnode subnode)
 {
-   struct cpsw_slave_data  *slave_data;
-   const void *fdt = gd->fdt_blob;
+   struct ofnode_phandle_args out_args;
+   struct cpsw_slave_data *slave_data;
const char *phy_mode;
-   int max_speed = -1;
u32 phy_id[2];
+   int ret;
 
slave_data = >slave_data[slave_index];
 
-   phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
+   phy_mode = ofnode_read_string(subnode, "phy-mode");
if (phy_mode)
-   slave_data->phy_if =
-   phy_get_interface_by_name(phy_mode);
+   slave_data->phy_if = phy_get_interface_by_name(phy_mode);
 
-   slave_data->phy_of_handle = fdtdec_lookup_phandle(fdt, subnode,
- "phy-handle");
+   ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
+NULL, 0, 0, _args);
+   if (!ret) {
+   slave_data->phy_of_handle = out_args.node;
 
-   if (data->slave_data[slave_index].phy_of_handle >= 0) {
-   slave_data->phy_addr =
-   fdtdec_get_int(fdt, slave_data->phy_of_handle,
-  "reg", -1);
+   ret = ofnode_read_s32(slave_data->phy_of_handle, "reg",
+ _data->phy_addr);
+   if (ret)
+   printf("error: phy addr not found in dt\n");
} else {
-   fdtdec_get_int_array(fdt, subnode, "phy_id",
-phy_id, 2);
-   slave_data->phy_addr = phy_id[1];
+   ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2);
+   if (ret)
+   printf("error: phy_id read failed\n");
}
 
-   max_speed = fdtdec_get_int(fdt, subnode,
-  "max-speed", max_speed);
-   if (max_speed > 0)
-   slave_data->max_speed = max_speed;
+   slave_data->max_speed = ofnode_read_s32_default(subnode,
+   "max-speed", 0);
 }
 
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
@@ -1227,17 +1217,14 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice 
*dev)
struct eth_pdata *pdata = dev_get_platdata(dev);
struct cpsw_platform_data *data;
struct gpio_desc *mode_gpios;
-   const void *fdt = gd->fdt_blob;
-   int node = dev_of_offset(dev);
-   int subnode;
int slave_index = 0;
-   int active_slave;
int num_mode_gpios;
+   ofnode subnode;
int ret;
 
data = calloc(1, sizeof(struct cpsw_platform_data));
pdata->priv_pdata = data;
-   pdata->iobase = devfdt_get_addr(dev);
+   pdata->iobase = dev_read_addr(dev);
data->version = CPSW_CTRL_VERSION_2;
data->bd_r

[U-Boot] [PATCH 1/6] net: ti: cpsw: enable 10Mbps link speed support in rgmii mode

[Grygorii Strashko]

According to TRMs the 10Mbps link speed is supported in RGMII only when
CPSW2G MAC SL is configured for External Control ("in band") mode
CPSW_SL_MACCTRL.EXT_EN(18) = 1.

Hence update cpsw_slave_update_link() to follow documentation.

[1] https://patchwork.kernel.org/patch/10285239/
Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 20ddb44dd8..f0d008f0f5 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -33,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GIGABITEN  BIT(7)
 #define FULLDUPLEXEN   BIT(0)
 #define MIIEN  BIT(15)
+#define CTL_EXT_EN BIT(18)
 /* DMA Registers */
 #define CPDMA_TXCONTROL0x004
 #define CPDMA_RXCONTROL0x014
@@ -489,6 +490,8 @@ static int cpsw_slave_update_link(struct cpsw_slave *slave,
mac_control |= FULLDUPLEXEN;
if (phy->speed == 100)
mac_control |= MIIEN;
+   if (phy->speed == 10 && phy_interface_is_rgmii(phy))
+   mac_control |= CTL_EXT_EN;
}
 
if (mac_control == slave->mac_control)
-- 
2.17.1

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[U-Boot] [PATCH 3/6] net: ti: cpsw: add support for standard eth "max-speed" dt property

[Grygorii Strashko]

This patch adds support for standard Ethernet "max-speed" DT property to
allow PHY link speed limitation.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 14 ++
 include/cpsw.h|  1 +
 2 files changed, 15 insertions(+)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 533c167995..af4db89341 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -839,6 +839,7 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct 
cpsw_slave *slave)
 {
struct phy_device *phydev;
u32 supported = PHY_GBIT_FEATURES;
+   int ret;
 
phydev = phy_connect(priv->bus,
slave->data->phy_addr,
@@ -849,6 +850,13 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct 
cpsw_slave *slave)
return -1;
 
phydev->supported &= supported;
+   if (slave->data->max_speed) {
+   ret = phy_set_supported(phydev, slave->data->max_speed);
+   if (ret)
+   return ret;
+   dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
+   slave->slave_num + 1, slave->data->max_speed);
+   }
phydev->advertising = phydev->supported;
 
 #ifdef CONFIG_DM_ETH
@@ -1185,6 +1193,7 @@ static void cpsw_eth_of_parse_slave(struct 
cpsw_platform_data *data,
struct cpsw_slave_data  *slave_data;
const void *fdt = gd->fdt_blob;
const char *phy_mode;
+   int max_speed = -1;
u32 phy_id[2];
 
slave_data = >slave_data[slave_index];
@@ -1206,6 +1215,11 @@ static void cpsw_eth_of_parse_slave(struct 
cpsw_platform_data *data,
 phy_id, 2);
slave_data->phy_addr = phy_id[1];
}
+
+   max_speed = fdtdec_get_int(fdt, subnode,
+  "max-speed", max_speed);
+   if (max_speed > 0)
+   slave_data->max_speed = max_speed;
 }
 
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
diff --git a/include/cpsw.h b/include/cpsw.h
index 96ff254f98..c7532fc866 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -39,6 +39,7 @@ struct cpsw_slave_data {
int phy_addr;
int phy_if;
int phy_of_handle;
+   int max_speed;
 };
 
 enum {
-- 
2.17.1

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[U-Boot] [PATCH 5/6] net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid mode

[Grygorii Strashko]

Now AM65x CPSW2G driver will disable MAC TX internal delay for PHY
interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping
default value (enabled) for MAC TX internal delay when "rgmii-rxid"
interface mode is selected.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/am65-cpsw-nuss.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index e11fbdeed3..06b0663950 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -234,11 +234,11 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv 
*priv,
break;
 
case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_RXID:
mode = AM65_GMII_SEL_MODE_RGMII;
break;
 
case PHY_INTERFACE_MODE_RGMII_ID:
-   case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
mode = AM65_GMII_SEL_MODE_RGMII;
rgmii_id = true;
-- 
2.17.1

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[U-Boot] [PATCH 4/6] net: ti: cpsw: fix mac tx internal delay for rgmii-rxid mode

[Grygorii Strashko]

Now TI CPSW driver will disable MAC TX internal delay for PHY interface
mode "rgmii-rxid" which is incorrect.

Hence, fix it by keeping default value (enabled) for MAC TX internal delay
when "rgmii-rxid" interface mode is selected.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index af4db89341..55edff3b8d 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -1072,10 +1072,10 @@ static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
break;
 
case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_RXID:
mode = AM33XX_GMII_SEL_MODE_RGMII;
break;
case PHY_INTERFACE_MODE_RGMII_ID:
-   case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
mode = AM33XX_GMII_SEL_MODE_RGMII;
rgmii_id = true;
-- 
2.17.1

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[U-Boot] [PATCH 2/6] net: ti: cpsw: move parsing of dt port's parameters in separate func

[Grygorii Strashko]

Move parsing of dt port's parameters in separate func for better code
readability.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 57 +--
 1 file changed, 33 insertions(+), 24 deletions(-)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index f0d008f0f5..533c167995 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -1179,12 +1179,40 @@ static int cpsw_eth_probe(struct udevice *dev)
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
+static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
+   int slave_index, int subnode)
+{
+   struct cpsw_slave_data  *slave_data;
+   const void *fdt = gd->fdt_blob;
+   const char *phy_mode;
+   u32 phy_id[2];
+
+   slave_data = >slave_data[slave_index];
+
+   phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
+   if (phy_mode)
+   slave_data->phy_if =
+   phy_get_interface_by_name(phy_mode);
+
+   slave_data->phy_of_handle = fdtdec_lookup_phandle(fdt, subnode,
+ "phy-handle");
+
+   if (data->slave_data[slave_index].phy_of_handle >= 0) {
+   slave_data->phy_addr =
+   fdtdec_get_int(fdt, slave_data->phy_of_handle,
+  "reg", -1);
+   } else {
+   fdtdec_get_int_array(fdt, subnode, "phy_id",
+phy_id, 2);
+   slave_data->phy_addr = phy_id[1];
+   }
+}
+
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_platdata(dev);
struct cpsw_platform_data *data;
struct gpio_desc *mode_gpios;
-   const char *phy_mode;
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int subnode;
@@ -1267,30 +1295,10 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice 
*dev)
}
 
if (!strncmp(name, "slave", 5)) {
-   u32 phy_id[2];
-
if (slave_index >= data->slaves)
continue;
-   phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
-   if (phy_mode)
-   data->slave_data[slave_index].phy_if =
-   phy_get_interface_by_name(phy_mode);
-
-   data->slave_data[slave_index].phy_of_handle =
-   fdtdec_lookup_phandle(fdt, subnode,
- "phy-handle");
-
-   if (data->slave_data[slave_index].phy_of_handle >= 0) {
-   data->slave_data[slave_index].phy_addr =
-   fdtdec_get_int(gd->fdt_blob,
-   
data->slave_data[slave_index].phy_of_handle,
-  "reg", -1);
-   } else {
-   fdtdec_get_int_array(fdt, subnode, "phy_id",
-phy_id, 2);
-   data->slave_data[slave_index].phy_addr =
-   phy_id[1];
-   }
+
+   cpsw_eth_of_parse_slave(data, slave_index, subnode);
slave_index++;
}
 
@@ -1331,7 +1339,8 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice 
*dev)
 
pdata->phy_interface = data->slave_data[active_slave].phy_if;
if (pdata->phy_interface == -1) {
-   debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+   debug("%s: Invalid PHY interface '%s'\n", __func__,
+ phy_string_for_interface(pdata->phy_interface));
return -EINVAL;
}
 
-- 
2.17.1

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[U-Boot] [PATCH 0/6] net: ti: net: to: set of fixes and improvements

[Grygorii Strashko]

Hi All,

This series introduces set of fixes and improvements for TI CPSW and AM654x
CPSW networking drivers.

Patch 1 - Enables support of 10Mbit link speeds for TI CPSW driver.
Patch 3 - Adds support of standard Ethernet "max-speed" DT property.
Patches 4-5 - fix mac tx internal delay for rgmii-rxid mode
Patches 2,6 - are code improvements


Grygorii Strashko (6):
  net: ti: cpsw: enable 10Mbps link speed support in rgmii mode
  net: ti: cpsw: move parsing of dt port's parameters in separate func
  net: ti: cpsw: add support for standard eth "max-speed" dt property
  net: ti: cpsw: fix mac tx internal delay for rgmii-rxid mode
  net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid mode
  net: ti: cpsw: convert to use dev/ofnode api

 drivers/net/ti/am65-cpsw-nuss.c |   2 +-
 drivers/net/ti/cpsw.c   | 154 +---
 include/cpsw.h  |   3 +-
 3 files changed, 84 insertions(+), 75 deletions(-)

-- 
2.17.1

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[U-Boot] [PATCH 3/3] arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id

[Grygorii Strashko]

Synchronize CPSW/MDIO/PHY DT nodes with latest linux - replace deprecated
phy_id property with phy-handle.

Signed-off-by: Grygorii Strashko 
Cc: Lokesh Vutla 
Cc: Hannes Schmelzer 
Cc: Heiko Schocher 
Cc: Felix Brack 
Cc: Jean-Jacques Hiblot 

---
 arch/arm/dts/am335x-baltos.dts   | 14 --
 arch/arm/dts/am335x-bone-common.dtsi | 12 ++--
 arch/arm/dts/am335x-brsmarc1.dts | 12 ++--
 arch/arm/dts/am335x-brxre1.dts   | 12 ++--
 arch/arm/dts/am335x-chiliboard.dts   |  6 +-
 arch/arm/dts/am335x-draco.dts|  2 +-
 arch/arm/dts/am335x-evm.dts  | 14 +++---
 arch/arm/dts/am335x-evmsk.dts| 16 
 arch/arm/dts/am335x-icev2.dts| 12 ++--
 arch/arm/dts/am335x-igep0033.dtsi| 12 ++--
 arch/arm/dts/am335x-pxm2.dtsi| 12 ++--
 arch/arm/dts/am335x-rut.dts  |  7 +--
 arch/arm/dts/am335x-shc.dts  | 10 +-
 arch/arm/dts/am335x-sl50.dts | 13 +++--
 14 files changed, 106 insertions(+), 48 deletions(-)

diff --git a/arch/arm/dts/am335x-baltos.dts b/arch/arm/dts/am335x-baltos.dts
index f939cf6406..b3c13c9a9d 100644
--- a/arch/arm/dts/am335x-baltos.dts
+++ b/arch/arm/dts/am335x-baltos.dts
@@ -409,16 +409,26 @@
pinctrl-1 = <_mdio_sleep>;
 
status = "okay";
+
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+
+   phy1: ethernet-phy@7 {
+   reg = <7>;
+   eee-broken-100tx;
+   eee-broken-1000t;
+   };
 };
 
 _emac0 {
-   phy_id = <_mdio>, <0>;
+   phy-handle = <>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
 };
 
 _emac1 {
-   phy_id = <_mdio>, <7>;
+   phy-handle = <>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/dts/am335x-bone-common.dtsi 
b/arch/arm/dts/am335x-bone-common.dtsi
index 40a3c35ff8..5b8230e281 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -360,16 +360,12 @@
 };
 
 _emac0 {
-   phy_id = <_mdio>, <0>;
-   phy-mode = "mii";
-};
-
-_emac1 {
-   phy_id = <_mdio>, <1>;
+   phy-handle = <>;
phy-mode = "mii";
 };
 
  {
+   slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <_default>;
pinctrl-1 = <_sleep>;
@@ -381,6 +377,10 @@
pinctrl-0 = <_mdio_default>;
pinctrl-1 = <_mdio_sleep>;
status = "okay";
+
+   ethphy0: ethernet-phy@0 {
+   reg = <0>;
+   };
 };
 
  {
diff --git a/arch/arm/dts/am335x-brsmarc1.dts b/arch/arm/dts/am335x-brsmarc1.dts
index 1a7f9a5365..e1738b6dde 100644
--- a/arch/arm/dts/am335x-brsmarc1.dts
+++ b/arch/arm/dts/am335x-brsmarc1.dts
@@ -247,6 +247,14 @@
 
 _mdio {
status = "okay";
+
+   ethphy0: ethernet-phy@1 {
+   reg = <1>;
+   };
+
+   ethphy1: ethernet-phy@3 {
+   reg = <3>;
+   };
 };
 
  {
@@ -258,13 +266,13 @@
 };
 
 _emac0 {
-   phy_id = <_mdio>, <1>;
+   phy-handle = <>;
phy-mode = "rmii";
ti,ledcr = <0x0480>;
 };
 
 _emac1 {
-   phy_id = <_mdio>, <3>;
+   phy-handle = <>;
phy-mode = "rmii";
ti,ledcr = <0x0480>;
 };
diff --git a/arch/arm/dts/am335x-brxre1.dts b/arch/arm/dts/am335x-brxre1.dts
index 708407daf2..a0d046d07a 100644
--- a/arch/arm/dts/am335x-brxre1.dts
+++ b/arch/arm/dts/am335x-brxre1.dts
@@ -206,6 +206,14 @@
 
 _mdio {
status = "okay";
+
+   ethphy0: ethernet-phy@1 {
+   reg = <1>;
+   };
+
+   ethphy1: ethernet-phy@2 {
+   reg = <2>;
+   };
 };
 
  {
@@ -213,12 +221,12 @@
 };
 
 _emac0 {
-   phy_id = <_mdio>, <1>;
+   phy-handle = <>;
phy-mode = "mii";
 };
 
 _emac1 {
-   phy_id = <_mdio>, <2>;
+   phy-handle = <>;
phy-mode = "mii";
 };
 
diff --git a/arch/arm/dts/am335x-chiliboard.dts 
b/arch/arm/dts/am335x-chiliboard.dts
index 59431b2359..9c2a947aac 100644
--- a/arch/arm/dts/am335x-chiliboard.dts
+++ b/arch/arm/dts/am335x-chiliboard.dts
@@ -140,10 +140,14 @@
pinctrl-0 = <_mdio_default>;
pinctrl-1 = <_mdio_sleep>;
status = "okay";
+
+   ethphy0: ethernet-phy@0 {
+   reg = <0>;
+   };
 };
 
 _emac0 {
-   phy_id = <_mdio>, <0>;
+   phy-handle = <>;
phy-mode = "rmii";
 };
 
diff --git a/arch/arm/dts/am335x-draco.dts b/arch/arm/dts/am335x-draco.dts
index 25d0480ecd..f8faa8f7c4 100644
--- a/arch/arm/dts/am335x-draco.dts
+++ b/arch/arm/d

[U-Boot] [PATCH 2/3] arm: dts: am437x: sync cpsw/mdio/phy with latest linux - drop phy_id

[Grygorii Strashko]

Synchronize CPSW/MDIO/PHY DT nodes with latest linux - replace deprecated
phy_id property with phy-handle.

Signed-off-by: Grygorii Strashko 
Cc: Lokesh Vutla 
---
 arch/arm/dts/am437x-gp-evm.dts  |  6 +-
 arch/arm/dts/am437x-idk-evm.dts |  7 ++-
 arch/arm/dts/am437x-sk-evm.dts  | 12 ++--
 arch/arm/dts/am43x-epos-evm.dts | 12 ++--
 4 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts
index 142bfc52a1..3c500d52db 100644
--- a/arch/arm/dts/am437x-gp-evm.dts
+++ b/arch/arm/dts/am437x-gp-evm.dts
@@ -645,10 +645,14 @@
pinctrl-0 = <_mdio_default>;
pinctrl-1 = <_mdio_sleep>;
status = "okay";
+
+   ethphy0: ethernet-phy@0 {
+   reg = <0>;
+   };
 };
 
 _emac0 {
-   phy_id = <_mdio>, <0>;
+   phy-handle = <>;
phy-mode = "rgmii";
 };
 
diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts
index 19d1462d15..8f6824c198 100644
--- a/arch/arm/dts/am437x-idk-evm.dts
+++ b/arch/arm/dts/am437x-idk-evm.dts
@@ -385,6 +385,7 @@
 };
 
  {
+   slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <_default>;
pinctrl-1 = <_sleep>;
@@ -396,10 +397,14 @@
pinctrl-0 = <_mdio_default>;
pinctrl-1 = <_mdio_sleep>;
status = "okay";
+
+   ethphy0: ethernet-phy@0 {
+   reg = <0>;
+   };
 };
 
 _emac0 {
-   phy_id = <_mdio>, <0>;
+   phy-handle = <>;
phy-mode = "rgmii";
 };
 
diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts
index dc8fcde458..66a3bd1dfa 100644
--- a/arch/arm/dts/am437x-sk-evm.dts
+++ b/arch/arm/dts/am437x-sk-evm.dts
@@ -626,16 +626,24 @@
pinctrl-0 = <_mdio_default>;
pinctrl-1 = <_mdio_sleep>;
status = "okay";
+
+   ethphy0: ethernet-phy@4 {
+   reg = <4>;
+   };
+
+   ethphy1: ethernet-phy@5 {
+   reg = <5>;
+   };
 };
 
 _emac0 {
-   phy_id = <_mdio>, <4>;
+   phy-handle = <>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
 };
 
 _emac1 {
-   phy_id = <_mdio>, <5>;
+   phy-handle = <>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts
index fa4d1e3f32..65f157ed59 100644
--- a/arch/arm/dts/am43x-epos-evm.dts
+++ b/arch/arm/dts/am43x-epos-evm.dts
@@ -389,6 +389,7 @@
pinctrl-0 = <_default>;
pinctrl-1 = <_sleep>;
status = "okay";
+   slaves = <1>;
 };
 
 _mdio {
@@ -396,15 +397,14 @@
pinctrl-0 = <_mdio_default>;
pinctrl-1 = <_mdio_sleep>;
status = "okay";
-};
 
-_emac0 {
-   phy_id = <_mdio>, <16>;
-   phy-mode = "rmii";
+   ethphy0: ethernet-phy@16 {
+   reg = <16>;
+   };
 };
 
-_emac1 {
-   phy_id = <_mdio>, <1>;
+_emac0 {
+   phy-handle = <>;
phy-mode = "rmii";
 };
 
-- 
2.17.1

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[U-Boot] [PATCH 1/3] arm: dts: dra7: sync cpsw/mdio/phy with latest linux - drop phy_id

[Grygorii Strashko]

Synchronize CPSW/MDIO/PHY DT nodes with latest linux - replace deprecated
phy_id property with phy-handle.

Signed-off-by: Grygorii Strashko 
Cc: Lokesh Vutla 
---
 arch/arm/dts/am57xx-idk-common.dtsi | 14 --
 arch/arm/dts/dra7-evm.dts   | 14 --
 arch/arm/dts/dra71-evm.dts  |  4 ++--
 arch/arm/dts/dra72-evm-revc.dts |  4 ++--
 arch/arm/dts/dra72-evm.dts  |  8 +++-
 arch/arm/dts/dra76-evm.dts  |  4 ++--
 6 files changed, 37 insertions(+), 11 deletions(-)

diff --git a/arch/arm/dts/am57xx-idk-common.dtsi 
b/arch/arm/dts/am57xx-idk-common.dtsi
index fdb4e0e47c..590fb14caf 100644
--- a/arch/arm/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/dts/am57xx-idk-common.dtsi
@@ -372,17 +372,27 @@
 };
 
 _emac0 {
-   phy_id = <_mdio>, <0>;
+   phy-handle = <>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
 };
 
 _emac1 {
-   phy_id = <_mdio>, <1>;
+   phy-handle = <>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
 };
 
+_mdio {
+   ethphy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+
+   ethphy1: ethernet-phy@1 {
+   reg = <1>;
+   };
+};
+
 _phy1 {
phy-supply = <_reg>;
 };
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index aa426dabb6..43de9638e3 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -479,17 +479,27 @@
 };
 
 _emac0 {
-   phy_id = <_mdio>, <2>;
+   phy-handle = <>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
 };
 
 _emac1 {
-   phy_id = <_mdio>, <3>;
+   phy-handle = <>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
 };
 
+_mdio {
+   ethphy0: ethernet-phy@2 {
+   reg = <2>;
+   };
+
+   ethphy1: ethernet-phy@3 {
+   reg = <3>;
+   };
+};
+
  {
status = "ok";
pinctrl-names = "default", "sleep", "active";
diff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts
index 64363f75c0..9bf08294b2 100644
--- a/arch/arm/dts/dra71-evm.dts
+++ b/arch/arm/dts/dra71-evm.dts
@@ -201,13 +201,13 @@
 };
 
 _emac0 {
-   phy_id = <_mdio>, <2>;
+   phy-handle = <_0>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
 };
 
 _emac1 {
-   phy_id = <_mdio>, <3>;
+   phy-handle = <_1>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts
index bf588d0072..fafc2a4d7b 100644
--- a/arch/arm/dts/dra72-evm-revc.dts
+++ b/arch/arm/dts/dra72-evm-revc.dts
@@ -61,13 +61,13 @@
 };
 
 _emac0 {
-   phy_id = <_mdio>, <2>;
+   phy-handle = <_0>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
 };
 
 _emac1 {
-   phy_id = <_mdio>, <3>;
+   phy-handle = <_1>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index c572693b16..154b0a0ceb 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -51,10 +51,16 @@
 };
 
 _emac0 {
-   phy_id = <_mdio>, <3>;
+   phy-handle = <>;
phy-mode = "rgmii";
 };
 
+_mdio {
+   ethphy0: ethernet-phy@3 {
+   reg = <3>;
+   };
+};
+
  {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", 
"sdr104";
pinctrl-0 = <_pins_default>;
diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts
index a1f289f345..e3da17ac97 100644
--- a/arch/arm/dts/dra76-evm.dts
+++ b/arch/arm/dts/dra76-evm.dts
@@ -341,13 +341,13 @@
 };
 
 _emac0 {
-   phy_id = <_mdio>, <2>;
+   phy-handle = <_0>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
 };
 
 _emac1 {
-   phy_id = <_mdio>, <3>;
+   phy-handle = <_1>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
 };
-- 
2.17.1

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[U-Boot] [PATCH 0/3] arm: dts: ti: sync cpsw/mdio/phy with latest linux 1 - drop phy_id

[Grygorii Strashko]

Synchronize CPSW/MDIO/PHY DT nodes with latest linux - replace deprecated
phy_id property with phy-handle.

Grygorii Strashko (3):
  arm: dts: dra7: sync cpsw/mdio/phy with latest linux - drop phy_id
  arm: dts: am437x: sync cpsw/mdio/phy with latest linux - drop phy_id
  arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id

 arch/arm/dts/am335x-baltos.dts   | 14 --
 arch/arm/dts/am335x-bone-common.dtsi | 12 ++--
 arch/arm/dts/am335x-brsmarc1.dts | 12 ++--
 arch/arm/dts/am335x-brxre1.dts   | 12 ++--
 arch/arm/dts/am335x-chiliboard.dts   |  6 +-
 arch/arm/dts/am335x-draco.dts|  2 +-
 arch/arm/dts/am335x-evm.dts  | 14 +++---
 arch/arm/dts/am335x-evmsk.dts| 16 
 arch/arm/dts/am335x-icev2.dts| 12 ++--
 arch/arm/dts/am335x-igep0033.dtsi| 12 ++--
 arch/arm/dts/am335x-pxm2.dtsi| 12 ++--
 arch/arm/dts/am335x-rut.dts  |  7 +--
 arch/arm/dts/am335x-shc.dts  | 10 +-
 arch/arm/dts/am335x-sl50.dts | 13 +++--
 arch/arm/dts/am437x-gp-evm.dts   |  6 +-
 arch/arm/dts/am437x-idk-evm.dts  |  7 ++-
 arch/arm/dts/am437x-sk-evm.dts   | 12 ++--
 arch/arm/dts/am43x-epos-evm.dts  | 12 ++--
 arch/arm/dts/am57xx-idk-common.dtsi  | 14 --
 arch/arm/dts/dra7-evm.dts| 14 --
 arch/arm/dts/dra71-evm.dts   |  4 ++--
 arch/arm/dts/dra72-evm-revc.dts  |  4 ++--
 arch/arm/dts/dra72-evm.dts   |  8 +++-
 arch/arm/dts/dra76-evm.dts   |  4 ++--
 24 files changed, 170 insertions(+), 69 deletions(-)

-- 
2.17.1

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Re: [U-Boot] [PATCH] net: phy: ti: Fix clock output DT property

[Grygorii Strashko]

On 10.05.19 20:49, Trent Piepho wrote:
> The code block reading the DT property for the clock output control was
> before the phy's DT node pointer was set, so it could never work.  Move
> it after the node pointer is set.
> 
> Also store the unsigned 32-bit property into an unsigned value, not a
> signed value, as the former will cause a problem if value overflows.
> For instance, if one were to add 0x as a code to mean the clock
> output should be turned off.
> 
> Cc: Joe Hershberger 
> Cc: Janine Hagemann 
> Cc: Grygorii Strashko 
> Signed-off-by: Trent Piepho 
> ---
>  drivers/net/phy/ti.c | 16 +---
>  1 file changed, 5 insertions(+), 11 deletions(-)
> 

Reviewed-by: Grygorii Strashko  

-- 
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Re: [U-Boot] [PATCH] dma: ti: k3-udma: Do not touch RT registers before channel configuration

[Grygorii Strashko]

On 25.04.19 09:38, Vignesh Raghavendra wrote:
> From: Peter Ujfalusi 
> 
> Upcoming sysfw (2019.03) will not open the channelized firewalls during
> init, it only going to do so in response to the channel configuration
> message.
> 
> Remove the channel state checks done before the channel configuration and
> move it after the configuration for warning purposes.
> 
> Signed-off-by: Peter Ujfalusi 
> Signed-off-by: Vignesh Raghavendra 
> ---
>  drivers/dma/ti/k3-udma.c | 33 +
>  1 file changed, 9 insertions(+), 24 deletions(-)

Reviewed-by: Grygorii Strashko  

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Re: [U-Boot] [PATCH v3 2/2] net: eth-uclass: Support device tree MAC addresses

[Grygorii Strashko]

On 25.04.19 18:49, Thierry Reding wrote:
> From: Thierry Reding 
> 
> Add the standard Ethernet device tree bindings (imported from v5.0 of
> the Linux kernel) and implement support for reading the MAC address for
> Ethernet devices in the Ethernet uclass. If the "mac-address" property
> exists, the MAC address will be parsed from that. If that property does
> not exist, the "local-mac-address" property will be tried as fallback.
> 
> MAC addresses from device tree take precedence over the ones stored in
> a network interface card's ROM.
> 
> Acked-by: Joe Hershberger 
> Signed-off-by: Thierry Reding 
> ---
> Changes in v3:
> - add additional check to make sure the MAC address read from device
>   tree is a valid MAC address
> 
> Changes in v2:
> - use dev_read_u8_array_ptr()

Reviewed-by: Grygorii Strashko  

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Re: [U-Boot] [PATCH v2 2/2] net: eth-uclass: Support device tree MAC addresses

[Grygorii Strashko]

On 17.04.19 18:03, Thierry Reding wrote:
> On Wed, Apr 17, 2019 at 02:49:22PM +0300, Grygorii Strashko wrote:
>>
>>
>> On 16.04.19 19:24, Thierry Reding wrote:
>>> From: Thierry Reding 
>>>
>>> Add the standard Ethernet device tree bindings (imported from v5.0 of
>>> the Linux kernel) and implement support for reading the MAC address for
>>> Ethernet devices in the Ethernet uclass. If the "mac-address" property
>>> exists, the MAC address will be parsed from that. If that property does
>>> not exist, the "local-mac-address" property will be tried as fallback.
>>>
>>> MAC addresses from device tree take precedence over the ones stored in
>>> a network interface card's ROM.
>>>
>>> Acked-by: Joe Hershberger 
>>> Signed-off-by: Thierry Reding 
>>> ---
>>> Changes in v2:
>>> - use dev_read_u8_array_ptr()
>>>
>>>  .../devicetree/bindings/net/ethernet.txt  | 66 +++
>>>  net/eth-uclass.c  | 26 +++-
>>>  2 files changed, 89 insertions(+), 3 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/net/ethernet.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/net/ethernet.txt 
>>> b/Documentation/devicetree/bindings/net/ethernet.txt
>>> new file mode 100644
>>> index ..cfc376bc977a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/net/ethernet.txt
>>> @@ -0,0 +1,66 @@
>>> +The following properties are common to the Ethernet controllers:
>>> +
>>> +NOTE: All 'phy*' properties documented below are Ethernet specific. For the
>>> +generic PHY 'phys' property, see
>>> +Documentation/devicetree/bindings/phy/phy-bindings.txt.
>>> +
>>> +- local-mac-address: array of 6 bytes, specifies the MAC address that was
>>> +  assigned to the network device;
>>> +- mac-address: array of 6 bytes, specifies the MAC address that was last 
>>> used by
>>> +  the boot program; should be used in cases where the MAC address assigned 
>>> to
>>> +  the device by the boot program is different from the "local-mac-address"
>>> +  property;
>>> +- nvmem-cells: phandle, reference to an nvmem node for the MAC address;
>>> +- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
>>> +- max-speed: number, specifies maximum speed in Mbit/s supported by the 
>>> device;
>>> +- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather 
>>> than
>>> +  the maximum frame size (there's contradiction in the Devicetree
>>> +  Specification).
>>> +- phy-mode: string, operation mode of the PHY interface. This is now a 
>>> de-facto
>>> +  standard property; supported values are:
>>> +  * "internal"
>>> +  * "mii"
>>> +  * "gmii"
>>> +  * "sgmii"
>>> +  * "qsgmii"
>>> +  * "tbi"
>>> +  * "rev-mii"
>>> +  * "rmii"
>>> +  * "rgmii" (RX and TX delays are added by the MAC when required)
>>> +  * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, 
>>> the
>>> + MAC should not add the RX or TX delays in this case)
>>> +  * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
>>> + should not add an RX delay in this case)
>>> +  * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
>>> + should not add an TX delay in this case)
>>> +  * "rtbi"
>>> +  * "smii"
>>> +  * "xgmii"
>>> +  * "trgmii"
>>> +  * "2000base-x",
>>> +  * "2500base-x",
>>> +  * "rxaui"
>>> +  * "xaui"
>>> +  * "10gbase-kr" (10GBASE-KR, XFI, SFI)
>>> +- phy-connection-type: the same as "phy-mode" property but described in the
>>> +  Devicetree Specification;
>>> +- phy-handle: phandle, specifies a reference to a node representing a PHY
>>> +  device; this property is described in the Devicetree Specification and so
>>> +  preferred;
>>> +- phy: the same as "phy-handle" property, not recommended for new bindings.
>>> +- phy-device: the same as "phy-handle" property, not recommended for new
>>> +  bindings.
>>> +- rx

Re: [U-Boot] [PATCH v2 2/2] net: eth-uclass: Support device tree MAC addresses

[Grygorii Strashko]

On 16.04.19 19:24, Thierry Reding wrote:
> From: Thierry Reding 
> 
> Add the standard Ethernet device tree bindings (imported from v5.0 of
> the Linux kernel) and implement support for reading the MAC address for
> Ethernet devices in the Ethernet uclass. If the "mac-address" property
> exists, the MAC address will be parsed from that. If that property does
> not exist, the "local-mac-address" property will be tried as fallback.
> 
> MAC addresses from device tree take precedence over the ones stored in
> a network interface card's ROM.
> 
> Acked-by: Joe Hershberger 
> Signed-off-by: Thierry Reding 
> ---
> Changes in v2:
> - use dev_read_u8_array_ptr()
> 
>  .../devicetree/bindings/net/ethernet.txt  | 66 +++
>  net/eth-uclass.c  | 26 +++-
>  2 files changed, 89 insertions(+), 3 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/ethernet.txt
> 
> diff --git a/Documentation/devicetree/bindings/net/ethernet.txt 
> b/Documentation/devicetree/bindings/net/ethernet.txt
> new file mode 100644
> index ..cfc376bc977a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/ethernet.txt
> @@ -0,0 +1,66 @@
> +The following properties are common to the Ethernet controllers:
> +
> +NOTE: All 'phy*' properties documented below are Ethernet specific. For the
> +generic PHY 'phys' property, see
> +Documentation/devicetree/bindings/phy/phy-bindings.txt.
> +
> +- local-mac-address: array of 6 bytes, specifies the MAC address that was
> +  assigned to the network device;
> +- mac-address: array of 6 bytes, specifies the MAC address that was last 
> used by
> +  the boot program; should be used in cases where the MAC address assigned to
> +  the device by the boot program is different from the "local-mac-address"
> +  property;
> +- nvmem-cells: phandle, reference to an nvmem node for the MAC address;
> +- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
> +- max-speed: number, specifies maximum speed in Mbit/s supported by the 
> device;
> +- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather 
> than
> +  the maximum frame size (there's contradiction in the Devicetree
> +  Specification).
> +- phy-mode: string, operation mode of the PHY interface. This is now a 
> de-facto
> +  standard property; supported values are:
> +  * "internal"
> +  * "mii"
> +  * "gmii"
> +  * "sgmii"
> +  * "qsgmii"
> +  * "tbi"
> +  * "rev-mii"
> +  * "rmii"
> +  * "rgmii" (RX and TX delays are added by the MAC when required)
> +  * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the
> + MAC should not add the RX or TX delays in this case)
> +  * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
> + should not add an RX delay in this case)
> +  * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
> + should not add an TX delay in this case)
> +  * "rtbi"
> +  * "smii"
> +  * "xgmii"
> +  * "trgmii"
> +  * "2000base-x",
> +  * "2500base-x",
> +  * "rxaui"
> +  * "xaui"
> +  * "10gbase-kr" (10GBASE-KR, XFI, SFI)
> +- phy-connection-type: the same as "phy-mode" property but described in the
> +  Devicetree Specification;
> +- phy-handle: phandle, specifies a reference to a node representing a PHY
> +  device; this property is described in the Devicetree Specification and so
> +  preferred;
> +- phy: the same as "phy-handle" property, not recommended for new bindings.
> +- phy-device: the same as "phy-handle" property, not recommended for new
> +  bindings.
> +- rx-fifo-depth: the size of the controller's receive fifo in bytes. This
> +  is used for components that can have configurable receive fifo sizes,
> +  and is useful for determining certain configuration settings such as
> +  flow control thresholds.
> +- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
> +  is used for components that can have configurable fifo sizes.
> +- managed: string, specifies the PHY management type. Supported values are:
> +  "auto", "in-band-status". "auto" is the default, it usess MDIO for
> +  management if fixed-link is not specified.
> +
> +Child nodes of the Ethernet controller are typically the individual PHY 
> devices
> +connected via the MDIO bus (sometimes the MDIO bus controller is separate).
> +They are described in the phy.txt file in this same directory.
> +For non-MDIO PHY management see fixed-link.txt.
> diff --git a/net/eth-uclass.c b/net/eth-uclass.c
> index 4225aabf1fa1..c6d5ec013bd8 100644
> --- a/net/eth-uclass.c
> +++ b/net/eth-uclass.c
> @@ -455,6 +455,23 @@ static int eth_pre_unbind(struct udevice *dev)
>   return 0;
>  }
>  
> +static bool eth_dev_get_mac_address(struct udevice *dev, u8 mac[ARP_HLEN])
> +{
> + const uint8_t *p;
> +
> + p = dev_read_u8_array_ptr(dev, "mac-address", ARP_HLEN);
> + if (!p)
> + p = dev_read_u8_array_ptr(dev, "local-mac-address", ARP_HLEN);
> +
> 

Re: [U-Boot] [PATCH v2 3/7] net: netcp: add support for phy with rgmii ids

[Grygorii Strashko]

On 18.02.19 18:28, Murali Karicheri wrote:

Enhance the netcp driver to support phys that can be configured
for internal delay (rgmii-id, rgmii-rxid, rgmii-txid)

Signed-off-by: Murali Karicheri 
---
  drivers/net/ti/keystone_net.c | 22 +-
  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c
index a3ba91cc3f..defc57b29f 100644
--- a/drivers/net/ti/keystone_net.c
+++ b/drivers/net/ti/keystone_net.c
@@ -88,6 +88,7 @@ struct ks2_eth_priv {
struct mii_dev  *mdio_bus;
int phy_addr;
phy_interface_t phy_if;
+   int phy_of_handle;
int sgmii_link_type;
void*mdio_base;
struct rx_buff_desc net_rx_buffs;
@@ -588,6 +589,10 @@ static int ks2_eth_probe(struct udevice *dev)
if (priv->has_mdio) {
priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
   dev, priv->phy_if);
+#ifdef CONFIG_DM_ETH
+   if (priv->phy_of_handle)
+   dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
+#endif


Above is not correct, it has to be smth. like

#ifdef CONFIG_DM_ETH
if (priv->phy_of_handle)
phydev->node = offset_to_ofnode(priv->phy_of_handle);
#endif

see commit d4bb98170006e "drivers: net: cpsw: fix phy dt node setting"


phy_config(priv->phydev);
}
  




--
Best regards,
grygorii
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Re: [U-Boot] [PATCH v9 0/3] dma: add channels support

[Grygorii Strashko]

Hi Álvaro,

On 11/28/18 12:17 PM, Álvaro Fernández Rojas wrote:
> In order to add bcm6348-enet support, dma-uclass must be extended to support
> dma channels and reworked to operate like the other dm uclass (clk, reset...).
> 
> ===

Thank you for picking this up.
I, unfortunately, will be out unresponsive next few month due to personal 
reasons,
but hope this will be moved forward eventually.

> 
> ===
> 
> v9: Separate generic dma channels support from bmips enet support
> v8: Sync with latest u-boot.
> v7: From Grygorii Strashko:
>   - copyright fixed as suggested by Tom Rini
>   - added "Reviewed-by" tags
> v6: From Grygorii Strashko:
>   - added possibility to pass DMA driver/channel's specific data per each
>   transfer using additional parameter "metadata" in dma_send/dma_receive() 
> API.
>   For example, port number for network packets to be directed to the
>   specific port on multi port ethernet controllers.
>   - added new dma_prepare_rcv_buf() API which allows to implement zero-copy
>   DEV_TO_MEM transfer using DMA streaming channels which is usual case
>   for Networking.
>   - added dma-uclass test
>   - removed unused function dma_get_by_index_platdata()
>   - updated comments
> v5: Fix build of ti-edma3.
> v4: No changes
> v3: Introduce changes reported by Simon Glass:
>   - Improve dma-uclass.h documentation.
>   - Switch to live tree API.
> v2: Introduce changes reported by Vignesh:
>   - Respect current dma implementation.
>   - Let dma_memcpy find a compatible dma device.
> 
> Grygorii Strashko (1):
>test: dma: add dma-uclass test
> 
> Álvaro Fernández Rojas (2):
>dma: move dma_ops to dma-uclass.h
>dma: add channels support
> 
>   arch/sandbox/dts/test.dts  |   8 ++
>   configs/sandbox_defconfig  |   3 +
>   drivers/dma/Kconfig|  14 ++
>   drivers/dma/Makefile   |   1 +
>   drivers/dma/dma-uclass.c   | 183 +-
>   drivers/dma/sandbox-dma-test.c | 282 
> +
>   drivers/dma/ti-edma3.c |   2 +-
>   include/dma-uclass.h   | 128 +++
>   include/dma.h  | 282 
> +
>   test/dm/Makefile   |   1 +
>   test/dm/dma.c  | 123 ++
>   11 files changed, 997 insertions(+), 30 deletions(-)
>   create mode 100644 drivers/dma/sandbox-dma-test.c
>   create mode 100644 include/dma-uclass.h
>   create mode 100644 test/dm/dma.c
> 

-- 
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-grygorii
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[U-Boot] [PATCH v7 3/5] test: dma: add dma-uclass test

[Grygorii Strashko]

Add a sandbox DMA driver implementation (provider) and corresponding DM
test.

Reviewed-by: Tom Rini 
Signed-off-by: Grygorii Strashko 
---
 arch/sandbox/dts/test.dts  |   8 ++
 configs/sandbox_defconfig  |   3 +
 drivers/dma/Kconfig|   7 +
 drivers/dma/Makefile   |   1 +
 drivers/dma/sandbox-dma-test.c | 282 +
 test/dm/Makefile   |   1 +
 test/dm/dma.c  | 123 ++
 7 files changed, 425 insertions(+)
 create mode 100644 drivers/dma/sandbox-dma-test.c
 create mode 100644 test/dm/dma.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 57e0dd7..b721007 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -712,6 +712,14 @@
sandbox_tee {
compatible = "sandbox,tee";
};
+
+   dma: dma {
+   compatible = "sandbox,dma";
+   #dma-cells = <1>;
+
+   dmas = < 0>, < 1>, < 2>;
+   dma-names = "m2m", "tx0", "rx0";
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 2ce336f..7cdc01c 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -217,3 +217,6 @@ CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
 CONFIG_UT_ENV=y
 CONFIG_UT_OVERLAY=y
+CONFIG_DMA=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_SANDBOX_DMA=y
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index b9b85c6..8a4162e 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -19,6 +19,13 @@ config DMA_CHANNELS
  Enable channels support for DMA. Some DMA controllers have multiple
  channels which can either transfer data to/from different devices.
 
+config SANDBOX_DMA
+   bool "Enable the sandbox DMA test driver"
+   depends on DMA && DMA_CHANNELS && SANDBOX
+   help
+ Enable support for a test DMA uclass implementation. It stimulates
+ DMA transfer by simple copying data between channels.
+
 config TI_EDMA3
bool "TI EDMA3 driver"
help
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4eaef8a..aff31f9 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_DMA) += dma-uclass.o
 obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
 obj-$(CONFIG_APBH_DMA) += apbh_dma.o
 obj-$(CONFIG_FSL_DMA) += fsl_dma.o
+obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o
 obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
 obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
 obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c
new file mode 100644
index 000..b958ec4
--- /dev/null
+++ b/drivers/dma/sandbox-dma-test.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Direct Memory Access U-Class Simulation driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated 
+ *
+ * Author: Grygorii Strashko 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SANDBOX_DMA_CH_CNT 3
+#define SANDBOX_DMA_BUF_SIZE 1024
+
+struct sandbox_dma_chan {
+   struct sandbox_dma_dev *ud;
+   char name[20];
+   u32 id;
+   enum dma_direction dir;
+   bool in_use;
+   bool enabled;
+};
+
+struct sandbox_dma_dev {
+   struct device *dev;
+   u32 ch_count;
+   struct sandbox_dma_chan channels[SANDBOX_DMA_CH_CNT];
+   uchar   buf[SANDBOX_DMA_BUF_SIZE];
+   uchar   *buf_rx;
+   size_t  data_len;
+   u32 meta;
+};
+
+static int sandbox_dma_transfer(struct udevice *dev, int direction,
+   void *dst, void *src, size_t len)
+{
+   memcpy(dst, src, len);
+
+   return 0;
+}
+
+static int sandbox_dma_of_xlate(struct dma *dma,
+   struct ofnode_phandle_args *args)
+{
+   struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+   struct sandbox_dma_chan *uc;
+
+   debug("%s(dma id=%u)\n", __func__, args->args[0]);
+
+   if (args->args[0] >= SANDBOX_DMA_CH_CNT)
+   return -EINVAL;
+
+   dma->id = args->args[0];
+
+   uc = >channels[dma->id];
+
+   if (dma->id == 1)
+   uc->dir = DMA_MEM_TO_DEV;
+   else if (dma->id == 2)
+   uc->dir = DMA_DEV_TO_MEM;
+   else
+   uc->dir = DMA_MEM_TO_MEM;
+   debug("%s(dma id=%lu dir=%d)\n", __func__, dma->id, uc->dir);
+
+   return 0;
+}
+
+static int sandbox_dma_request(struct dma *dma)
+{
+   struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+   struct sandbox_dma_chan *uc;
+
+   if (dma->id >= SANDBOX_DMA_CH_CNT)
+   return -EINVAL;
+
+   uc = >channels[dma->id];
+   if (uc->in_use)
+   retur

[U-Boot] [NOT-FOR-MERGE-PATCH PATCH v7 4/5] dma: ti: add driver to K3 UDMA

[Grygorii Strashko]

From: Vignesh R 

Add support for K3 AM65x UDMA with only support pktmode MEM_TO_MEM
transfers and DEV_TO_MEM/MEM_TO_DEV through DMA channels.

Signed-off-by: Peter Ujfalusi 
Signed-off-by: Grygorii Strashko 
---
 drivers/dma/Kconfig   |2 +
 drivers/dma/Makefile  |2 +
 drivers/dma/ti/Kconfig|   14 +
 drivers/dma/ti/Makefile   |3 +
 drivers/dma/ti/k3-udma-hwdef.h|  184 
 drivers/dma/ti/k3-udma.c  | 1679 +
 include/dt-bindings/dma/k3-udma.h |   26 +
 include/linux/soc/ti/ti-udma.h|   24 +
 8 files changed, 1934 insertions(+)
 create mode 100644 drivers/dma/ti/Kconfig
 create mode 100644 drivers/dma/ti/Makefile
 create mode 100644 drivers/dma/ti/k3-udma-hwdef.h
 create mode 100644 drivers/dma/ti/k3-udma.c
 create mode 100644 include/dt-bindings/dma/k3-udma.h
 create mode 100644 include/linux/soc/ti/ti-udma.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8a4162e..306261c 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -48,4 +48,6 @@ config APBH_DMA_BURST8
 
 endif
 
+source "drivers/dma/ti/Kconfig"
+
 endmenu # menu "DMA Support"
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index aff31f9..ef2865a 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -12,3 +12,5 @@ obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o
 obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
 obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
 obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
+
+obj-y += ti/
diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig
new file mode 100644
index 000..3d54983
--- /dev/null
+++ b/drivers/dma/ti/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+if ARCH_K3
+
+config TI_K3_NAVSS_UDMA
+bool "Texas Instruments UDMA"
+depends on ARCH_K3
+select DMA
+select TI_K3_NAVSS_RINGACC
+select TI_K3_NAVSS_PSILCFG
+default n
+help
+  Support for UDMA used in K3 devices.
+endif
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
new file mode 100644
index 000..de2f9ac
--- /dev/null
+++ b/drivers/dma/ti/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_TI_K3_NAVSS_UDMA) += k3-udma.o
diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h
new file mode 100644
index 000..c88399a
--- /dev/null
+++ b/drivers/dma/ti/k3-udma-hwdef.h
@@ -0,0 +1,184 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef K3_NAVSS_UDMA_HWDEF_H_
+#define K3_NAVSS_UDMA_HWDEF_H_
+
+#define UDMA_PSIL_DST_THREAD_ID_OFFSET 0x8000
+
+/* Global registers */
+#define UDMA_REV_REG   0x0
+#define UDMA_PERF_CTL_REG  0x4
+#define UDMA_EMU_CTL_REG   0x8
+#define UDMA_PSIL_TO_REG   0x10
+#define UDMA_UTC_CTL_REG   0x1c
+#define UDMA_CAP_REG(i)(0x20 + (i * 4))
+#define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
+#define UDMA_RX_FLOW_ID_FW_STATUS_REG  0x88
+
+/* RX Flow regs */
+#define UDMA_RFLOW_RFA_REG 0x0
+#define UDMA_RFLOW_RFB_REG 0x4
+#define UDMA_RFLOW_RFC_REG 0x8
+#define UDMA_RFLOW_RFD_REG 0xc
+#define UDMA_RFLOW_RFE_REG 0x10
+#define UDMA_RFLOW_RFF_REG 0x14
+#define UDMA_RFLOW_RFG_REG 0x18
+#define UDMA_RFLOW_RFH_REG 0x1c
+
+#define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG)
+
+/* TX chan regs */
+#define UDMA_TCHAN_TCFG_REG0x0
+#define UDMA_TCHAN_TCREDIT_REG 0x4
+#define UDMA_TCHAN_TCQ_REG 0x14
+#define UDMA_TCHAN_TOES_REG(i) (0x20 + (i) * 4)
+#define UDMA_TCHAN_TEOES_REG   0x60
+#define UDMA_TCHAN_TPRI_CTRL_REG   0x64
+#define UDMA_TCHAN_THREAD_ID_REG   0x68
+#define UDMA_TCHAN_TFIFO_DEPTH_REG 0x70
+#define UDMA_TCHAN_TST_SCHED_REG   0x80
+
+/* RX chan regs */
+#define UDMA_RCHAN_RCFG_REG0x0
+#define UDMA_RCHAN_RCQ_REG 0x14
+#define UDMA_RCHAN_ROES_REG(i) (0x20 + (i) * 4)
+#define UDMA_RCHAN_REOES_REG   0x60
+#define UDMA_RCHAN_RPRI_CTRL_REG   0x64
+#define UDMA_RCHAN_THREAD_ID_REG   0x68
+#define UDMA_RCHAN_RST_SCHED_REG   0x80
+#define UDMA_RCHAN_RFLOW_RNG_REG   0xf0
+
+/* TX chan RT regs */
+#define UDMA_TCHAN_RT_CTL_REG  0x0
+#define UDMA_TCHAN_RT_SWTRIG_REG   0x8
+#define UDMA_TCHAN_RT_STDATA_REG   0x80
+
+#define UDMA_TCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4))
+#define UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG\
+   UDMA_TCHAN_RT_PEERn_REG(0)  /* PSI-L: 0x400 */
+#define UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG \
+

[U-Boot] [NOT-FOR-MERGE-PATCH PATCH v7 5/5] net: ethernet: ti: introduce am654 gigabit eth switch subsystem driver

[Grygorii Strashko]

Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
NUSS). It has two ports and provides Ethernet packet communication for the
device and can be configured as an Ethernet switch. CPSW NUSS features: the
Reduced Gigabit Media Independent Interface (RGMII), Reduced Media
Independent Interface (RMII), and the Management Data Input/Output (MDIO)
interface for physical layer device (PHY) management. The TI AM65x SoC has
integrated two-port Gigabit Ethernet Switch subsystem into device MCU
domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII
and RMII interfaces and an internal Communications Port Programming
Interface (CPPI) port (Host port 0).

Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX
channels and on RX channels operating by TI am654 NAVSS Unified DMA
Peripheral Root Complex (UDMA-P) controller.

Signed-off-by: Grygorii Strashko 
---
 drivers/net/Kconfig  |   8 +
 drivers/net/Makefile |   1 +
 drivers/net/am65-cpsw-nuss.c | 962 +++
 3 files changed, 971 insertions(+)
 create mode 100644 drivers/net/am65-cpsw-nuss.c

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index e2d5b97..3a45732 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -316,6 +316,14 @@ config SH_ETHER
help
  This driver supports the Ethernet for Renesas SH and ARM SoCs.
 
+config TI_AM65_CPSW_NUSS
+   bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver"
+   depends on ARCH_K3
+   select PHYLIB
+   help
+ This driver supports TI K3 MCU CPSW Nuss Ethernet controller
+ in Texas Instruments K3 AM65x SoCs.
+
 config XILINX_AXIEMAC
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 8e33d7a..073fb3e 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_SMC9) += smc9.o
 obj-$(CONFIG_SMC911X) += smc911x.o
 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
 obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
+obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o
 obj-$(CONFIG_ULI526X) += uli526x.o
 obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
 obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
diff --git a/drivers/net/am65-cpsw-nuss.c b/drivers/net/am65-cpsw-nuss.c
new file mode 100644
index 000..e2761c9
--- /dev/null
+++ b/drivers/net/am65-cpsw-nuss.c
@@ -0,0 +1,962 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
+ *
+ * Copyright (C) 2018, Texas Instruments, Incorporated
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define AM65_CPSW_CPSWNU_MAX_PORTS 2
+
+#define AM65_CPSW_SS_BASE  0x0
+#define AM65_CPSW_SGMII_BASE   0x100
+#define AM65_CPSW_MDIO_BASE0xf00
+#define AM65_CPSW_XGMII_BASE   0x2100
+#define AM65_CPSW_CPSW_NU_BASE 0x2
+#define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000
+
+#define AM65_CPSW_CPSW_NU_PORTS_OFFSET 0x1000
+#define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET0x330
+
+#define AM65_CPSW_MDIO_BUS_FREQ_DEF 100
+
+#define AM65_CPSW_CTL_REG  0x4
+#define AM65_CPSW_STAT_PORT_EN_REG 0x14
+#define AM65_CPSW_PTYPE_REG0x18
+
+#define AM65_CPSW_CTL_REG_P0_ENABLEBIT(2)
+#define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE BIT(13)
+#define AM65_CPSW_CTL_REG_P0_RX_PADBIT(14)
+
+#define AM65_CPSW_P0_FLOW_ID_REG   0x8
+#define AM65_CPSW_PN_RX_MAXLEN_REG 0x24
+#define AM65_CPSW_PN_REG_SA_L  0x308
+#define AM65_CPSW_PN_REG_SA_H  0x30c
+
+#define AM65_CPSW_ALE_CTL_REG  0x8
+#define AM65_CPSW_ALE_CTL_REG_ENABLE   BIT(31)
+#define AM65_CPSW_ALE_CTL_REG_RESET_TBLBIT(30)
+#define AM65_CPSW_ALE_CTL_REG_BYPASS   BIT(4)
+#define AM65_CPSW_ALE_PN_CTL_REG(x)(0x40 + (x) * 4)
+#define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD  0x3
+#define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY  BIT(11)
+
+#define AM65_CPSW_MACSL_CTL_REG0x0
+#define AM65_CPSW_MACSL_CTL_REG_IFCTL_ABIT(15)
+#define AM65_CPSW_MACSL_CTL_REG_GIGBIT(7)
+#define AM65_CPSW_MACSL_CTL_REG_GMII_ENBIT(5)
+#define AM65_CPSW_MACSL_CTL_REG_LOOPBACK   BIT(1)
+#define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEXBIT(0)
+#define AM65_CPSW_MACSL_RESET_REG  0x8
+#define AM65_CPSW_MACSL_RESET_REG_RESETBIT(0)
+#define AM65_CPSW_MACSL_STATUS_REG 0x4
+#define AM65_CPSW_MACSL_RESET_REG_PN_IDLE  BIT(31)
+#define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLEBIT(30)
+#define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLEBIT(29)
+#define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE   BIT(28)
+#define AM65_CPSW_MACSL_R

[U-Boot] [PATCH v7 0/5] dma: add channels support

[Grygorii Strashko]

Hi All,

This series is the next try to add DMA channels support for DMA controllers
which last version was posted by Álvaro Fernández Rojas [1].
i've kept version numbering.

Comparing to the original post I've added few changes:
 - added possibility to pass DMA driver/channel's specific data per each 
transfer
 using additional parameter "metadata" in dma_send/dma_receive() API.
 For example, port number for network packets to be directed to the
 specific port on multi port ethernet controllers.
 - added new dma_prepare_rcv_buf() API which allows to implement zero-copy
 DEV_TO_MEM transfer using DMA streaming channels which is usual case
 for Networking.
 - added dma-uclass test
 - removed unused function dma_get_by_index_platdata()
 - updated comments

Hence, originally DMA channels support was introduced to add support for
"bmips: add bcm6348-enet support" - that series can be easily updated following
DMA channels API changes (if still actual).

Patches 5-6 - Here I'm providing DMA and networking drivers for the new
TI AM65x SoC [2] as an illustration of DMA channels API usage only. 
Unfortunately,
those drivers are still under development so NOT-FOR-MERGE (!will not build!)
- we'd like code/bindings to be accepted in LKML first.
Full sources can be found at [3].

[1] https://patchwork.ozlabs.org/cover/881642/
[2] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
[3] g...@git.ti.com:~gragst/ti-u-boot/gragsts-ti-u-boot.git
branch: master-am6-dma-wip
===

A DMA is a feature of computer systems that allows certain hardware
subsystems to access main system memory, independent of the CPU.
DMA channels are typically generated externally to the HW module
consuming them, by an entity this API calls a DMA provider. This API
provides a standard means for drivers to enable and disable DMAs, and to
copy, send and receive data using DMA.

DMA channel API:
 dma_get_by_index()
 dma_get_by_name()
 dma_request()
 dma_free()
 dma_enable()
 dma_disable()
 dma_prepare_rcv_buf()
 dma_receive()
 dma_send()

A driver that implements UCLASS_DMA is a DMA provider. A provider will
often implement multiple separate DMAs channels, since the hardware it manages
often has this capability. dma_uclass.h describes the interface which
DMA providers must implement.

DMA consumers/clients are the HW modules driven by the DMA channels. 

DMA consumer DMA_MEM_TO_DEV (transmit) usage example (based on networking).
Note. In u-boot dma_send() is sync operation always - it'll start transfer and
will poll for it to complete:
- get/request dma channel
struct dma dma_tx;
ret = dma_get_by_name(common->dev, "tx0", _tx);
if (ret) ...

- enable dma channel
ret = dma_enable(_tx);
if (ret) ...

- dma transmit DMA_MEM_TO_DEV.
struct ti_drv_packet_data packet_data;

packet_data.opt1 = val1;
packet_data.opt2 = val2;
ret = dma_send(_tx, packet, length, _data);
if (ret) ..

DMA consumer DMA_DEV_TO_MEM (receive) usage example (based on networking).
Note. dma_receive() is sync operation always - it'll start transfer
(if required) and will poll for it to complete (or for any previously
configured dev2mem transfer to complete):
- get/request dma channel
struct dma dma_rx;
ret = dma_get_by_name(common->dev, "rx0", _rx);
if (ret) ...

- enable dma channel
ret = dma_enable(_rx);
if (ret) ...

- dma receive DMA_DEV_TO_MEM.
struct ti_drv_packet_data packet_data;

len = dma_receive(_rx, (void **)packet, _data);
if (ret < 0) ...

DMA consumer DMA_DEV_TO_MEM (receive) zero-copy usage example (based on
networking). Networking subsystem allows to configure and use few receive
buffers (dev2mem), as Networking RX DMA channels usually implemented
as streaming interface
- get/request dma channel
struct dma dma_rx;
ret = dma_get_by_name(common->dev, "rx0", _rx);
if (ret) ...

for (i = 0; i < RX_DESC_NUM; i++) {
ret = dma_prepare_rcv_buf(_rx,
  net_rx_packets[i],
  RX_BUF_SIZE);
if (ret) ...
}

- enable dma channel
ret = dma_enable(_rx);
if (ret) ...

- dma receive DMA_DEV_TO_MEM.
struct ti_drv_packet_data packet_data;
void *packet;

len = dma_receive(_rx, , _data);
if (ret < 0) ..

/* packet - points on buffer prepared by dma_prepare_rcv_buf().
   process packet*/

- return buffer back to DAM channel
ret = dma_prepare_rcv_buf(_rx,
  net_rx_packets[rx_next],
  RX_BUF_SIZE);

changes in v7:
 - copyright fixed as suggested by Tom Rini
 - added "Reviewed-by" tags

v1: http://patchwork.ozlabs.org/cover/987948/

Grygorii

[U-Boot] [PATCH v7 2/5] dma: add channels support

[Grygorii Strashko]

From: Álvaro Fernández Rojas 

This adds channels support for dma controllers that have multiple channels
which can transfer data to/from different devices (enet, usb...).

DMA channle API:
 dma_get_by_index()
 dma_get_by_name()
 dma_request()
 dma_free()
 dma_enable()
 dma_disable()
 dma_prepare_rcv_buf()
 dma_receive()
 dma_send()

Reviewed-by: Tom Rini 
Signed-off-by: Álvaro Fernández Rojas 
[grygorii.stras...@ti.com: drop unused dma_get_by_index_platdata(),
 add metadata to send/receive ops, add dma_prepare_rcv_buf(),
 minor clean up]
Signed-off-by: Grygorii Strashko 
---
 drivers/dma/Kconfig  |   7 ++
 drivers/dma/dma-uclass.c | 181 -
 include/dma-uclass.h |  91 -
 include/dma.h| 260 ++-
 4 files changed, 532 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 4ee6afa..b9b85c6 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -12,6 +12,13 @@ config DMA
  buses that is used to transfer data to and from memory.
  The uclass interface is defined in include/dma.h.
 
+config DMA_CHANNELS
+   bool "Enable DMA channels support"
+   depends on DMA
+   help
+ Enable channels support for DMA. Some DMA controllers have multiple
+ channels which can either transfer data to/from different devices.
+
 config TI_EDMA3
bool "TI EDMA3 driver"
help
diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
index 6c3506c..9c961cf 100644
--- a/drivers/dma/dma-uclass.c
+++ b/drivers/dma/dma-uclass.c
@@ -2,19 +2,192 @@
 /*
  * Direct Memory Access U-Class driver
  *
- * (C) Copyright 2015
- * Texas Instruments Incorporated, 
+ * Copyright (C) 2018 Álvaro Fernández Rojas 
+ * Copyright (C) 2015 - 2018 Texas Instruments Incorporated 
+ * Written by Mugunthan V N 
  *
  * Author: Mugunthan V N 
  */
 
 #include 
 #include 
-#include 
-#include 
+#include 
 #include 
+#include 
 #include 
 
+#ifdef CONFIG_DMA_CHANNELS
+static inline struct dma_ops *dma_dev_ops(struct udevice *dev)
+{
+   return (struct dma_ops *)dev->driver->ops;
+}
+
+# if CONFIG_IS_ENABLED(OF_CONTROL)
+static int dma_of_xlate_default(struct dma *dma,
+   struct ofnode_phandle_args *args)
+{
+   debug("%s(dma=%p)\n", __func__, dma);
+
+   if (args->args_count > 1) {
+   pr_err("Invaild args_count: %d\n", args->args_count);
+   return -EINVAL;
+   }
+
+   if (args->args_count)
+   dma->id = args->args[0];
+   else
+   dma->id = 0;
+
+   return 0;
+}
+
+int dma_get_by_index(struct udevice *dev, int index, struct dma *dma)
+{
+   int ret;
+   struct ofnode_phandle_args args;
+   struct udevice *dev_dma;
+   const struct dma_ops *ops;
+
+   debug("%s(dev=%p, index=%d, dma=%p)\n", __func__, dev, index, dma);
+
+   assert(dma);
+   dma->dev = NULL;
+
+   ret = dev_read_phandle_with_args(dev, "dmas", "#dma-cells", 0, index,
+);
+   if (ret) {
+   pr_err("%s: dev_read_phandle_with_args failed: err=%d\n",
+  __func__, ret);
+   return ret;
+   }
+
+   ret = uclass_get_device_by_ofnode(UCLASS_DMA, args.node, _dma);
+   if (ret) {
+   pr_err("%s: uclass_get_device_by_ofnode failed: err=%d\n",
+  __func__, ret);
+   return ret;
+   }
+
+   dma->dev = dev_dma;
+
+   ops = dma_dev_ops(dev_dma);
+
+   if (ops->of_xlate)
+   ret = ops->of_xlate(dma, );
+   else
+   ret = dma_of_xlate_default(dma, );
+   if (ret) {
+   pr_err("of_xlate() failed: %d\n", ret);
+   return ret;
+   }
+
+   return dma_request(dev_dma, dma);
+}
+
+int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma)
+{
+   int index;
+
+   debug("%s(dev=%p, name=%s, dma=%p)\n", __func__, dev, name, dma);
+   dma->dev = NULL;
+
+   index = dev_read_stringlist_search(dev, "dma-names", name);
+   if (index < 0) {
+   pr_err("dev_read_stringlist_search() failed: %d\n", index);
+   return index;
+   }
+
+   return dma_get_by_index(dev, index, dma);
+}
+# endif /* OF_CONTROL */
+
+int dma_request(struct udevice *dev, struct dma *dma)
+{
+   struct dma_ops *ops = dma_dev_ops(dev);
+
+   debug("%s(dev=%p, dma=%p)\n", __func__, dev, dma);
+
+   dma->dev = dev;
+
+   if (!ops->request)
+   return 0;
+
+   return ops->request(dma);
+}
+
+int dma_free(struct dma *dma)
+{
+   struct dma_ops *ops = dma_dev_ops(dma->dev);
+
+   debug("

[U-Boot] [PATCH v7 1/5] dma: move dma_ops to dma-uclass.h

[Grygorii Strashko]

From: Álvaro Fernández Rojas 

Move dma_ops to a separate header file, following other uclass
implementations. While doing so, this patch also improves dma_ops
documentation.

Reviewed-by: Tom Rini 
Reviewed-by: Simon Glass 
Signed-off-by: Álvaro Fernández Rojas 
Signed-off-by: Grygorii Strashko 
---
 drivers/dma/dma-uclass.c |  2 +-
 drivers/dma/ti-edma3.c   |  2 +-
 include/dma-uclass.h | 39 +++
 include/dma.h| 22 --
 4 files changed, 41 insertions(+), 24 deletions(-)
 create mode 100644 include/dma-uclass.h

diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
index a33f7d5..6c3506c 100644
--- a/drivers/dma/dma-uclass.c
+++ b/drivers/dma/dma-uclass.c
@@ -9,10 +9,10 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 
 int dma_get_device(u32 transfer_type, struct udevice **devp)
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
index 2131e10..7e11b13 100644
--- a/drivers/dma/ti-edma3.c
+++ b/drivers/dma/ti-edma3.c
@@ -11,7 +11,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/include/dma-uclass.h b/include/dma-uclass.h
new file mode 100644
index 000..7bec5d3
--- /dev/null
+++ b/include/dma-uclass.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas 
+ * Copyright (C) 2015 Texas Instruments Incorporated 
+ * Written by Mugunthan V N 
+ *
+ */
+
+#ifndef _DMA_UCLASS_H
+#define _DMA_UCLASS_H
+
+/* See dma.h for background documentation. */
+
+#include 
+
+/*
+ * struct dma_ops - Driver model DMA operations
+ *
+ * The uclass interface is implemented by all DMA devices which use
+ * driver model.
+ */
+struct dma_ops {
+   /**
+* transfer() - Issue a DMA transfer. The implementation must
+*   wait until the transfer is done.
+*
+* @dev: The DMA device
+* @direction: direction of data transfer (should be one from
+*   enum dma_direction)
+* @dst: The destination pointer.
+* @src: The source pointer.
+* @len: Length of the data to be copied (number of bytes).
+* @return zero on success, or -ve error code.
+*/
+   int (*transfer)(struct udevice *dev, int direction, void *dst,
+   void *src, size_t len);
+};
+
+#endif /* _DMA_UCLASS_H */
diff --git a/include/dma.h b/include/dma.h
index 50e9652..97fa0cf 100644
--- a/include/dma.h
+++ b/include/dma.h
@@ -27,28 +27,6 @@ enum dma_direction {
 #define DMA_SUPPORTS_DEV_TO_DEVBIT(3)
 
 /*
- * struct dma_ops - Driver model DMA operations
- *
- * The uclass interface is implemented by all DMA devices which use
- * driver model.
- */
-struct dma_ops {
-   /*
-* Get the current timer count
-*
-* @dev: The DMA device
-* @direction: direction of data transfer should be one from
-  enum dma_direction
-* @dst: Destination pointer
-* @src: Source pointer
-* @len: Length of the data to be copied.
-* @return: 0 if OK, -ve on error
-*/
-   int (*transfer)(struct udevice *dev, int direction, void *dst,
-   void *src, size_t len);
-};
-
-/*
  * struct dma_dev_priv - information about a device used by the uclass
  *
  * @supported: mode of transfers that DMA can support, should be
-- 
2.10.5

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[U-Boot] [PATCH v3 0/7] driver: net: ti: clean up and code optimization

[Grygorii Strashko]

This series contains set of code clean up and optimizations for TI networking 
drivers.
Patch 1 - Adds drivers/net/ti/ folder and moves all TI's networking code
 in this folder.
Patches 2,3 - keystone2 clean up
Patch 5 - introduces common TI MDIO support library as existing TI SoCs network
 HW IPs have similar MDIO implementation.
Patches 6-7 - conversation of TI CPSW and keystone_net drivers to use common
 TI MDIO support library

tested dhcp and kernel boot on:
- k2e/g/hk/l evms 
- am437x-gpevm and AM5748 IDK

changes in v3:
 - patch 5 comments applied
changes in v2:
 - patch 5 comments fixed: use wait_for_bit, snprintf, mdelay, mdio_free 

v2: https://patchwork.ozlabs.org/cover/991649/
v1: https://patchwork.ozlabs.org/cover/989449/

TODO: TODO: As per code and documentation davinci_emac.c seems also can be
re-worked to use common TI MDIO support library and network PHYs framework.
Unfortunately, I have no HW to work with.

Grygorii Strashko (7):
  driver: net: consolidate ti's code in separate folder
  configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig
  drivers: net: keystone_net: drop non dm code
  driver: net: ti: cpsw: update to use SPDX identifier
  driver: net: ti: introduce common mdio support library
  driver: net: ti: cpsw: switch to use common mdio lib
  driver: net: ti: keystone_net: switch to use common mdio lib

 arch/arm/include/asm/ti-common/keystone_net.h |  27 --
 arch/arm/mach-davinci/dp83848.c   |   2 +-
 arch/arm/mach-davinci/et1011c.c   |   2 +-
 arch/arm/mach-davinci/ksz8873.c   |   2 +-
 arch/arm/mach-davinci/lxt972.c|   2 +-
 board/ti/ks2_evm/board.c  |  53 
 board/ti/ks2_evm/board.h  |   3 -
 board/ti/ks2_evm/board_k2e.c  |  74 -
 board/ti/ks2_evm/board_k2g.c  |  18 --
 board/ti/ks2_evm/board_k2hk.c |  42 ---
 board/ti/ks2_evm/board_k2l.c  |  42 ---
 configs/k2e_evm_defconfig |   1 +
 configs/k2e_hs_evm_defconfig  |   1 +
 configs/k2g_evm_defconfig |   1 +
 configs/k2g_hs_evm_defconfig  |   1 +
 configs/k2hk_evm_defconfig|   1 +
 configs/k2hk_hs_evm_defconfig |   1 +
 configs/k2l_evm_defconfig |   1 +
 configs/k2l_hs_evm_defconfig  |   1 +
 drivers/net/Kconfig   |  13 +-
 drivers/net/Makefile  |   4 +-
 drivers/net/ti/Kconfig|  20 ++
 drivers/net/ti/Makefile   |   7 +
 drivers/net/{ => ti}/cpsw-common.c|   0
 drivers/net/{ => ti}/cpsw.c   | 146 +-
 drivers/net/ti/cpsw_mdio.c| 203 +
 drivers/net/ti/cpsw_mdio.h|  18 ++
 drivers/net/{ => ti}/davinci_emac.c   |   0
 drivers/net/{ => ti}/davinci_emac.h   |   0
 drivers/net/{ => ti}/keystone_net.c   | 401 +-
 include/configs/ti_armv7_keystone2.h  |   1 -
 31 files changed, 286 insertions(+), 802 deletions(-)
 create mode 100644 drivers/net/ti/Kconfig
 create mode 100644 drivers/net/ti/Makefile
 rename drivers/net/{ => ti}/cpsw-common.c (100%)
 rename drivers/net/{ => ti}/cpsw.c (90%)
 create mode 100644 drivers/net/ti/cpsw_mdio.c
 create mode 100644 drivers/net/ti/cpsw_mdio.h
 rename drivers/net/{ => ti}/davinci_emac.c (100%)
 rename drivers/net/{ => ti}/davinci_emac.h (100%)
 rename drivers/net/{ => ti}/keystone_net.c (68%)

-- 
2.10.5

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[U-Boot] [PATCH v3 2/7] configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig

[Grygorii Strashko]

Convert DRIVER_TI_KEYSTONE_NET to Kconfig.

Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger 
Signed-off-by: Grygorii Strashko 
---
 configs/k2e_evm_defconfig| 1 +
 configs/k2e_hs_evm_defconfig | 1 +
 configs/k2g_evm_defconfig| 1 +
 configs/k2g_hs_evm_defconfig | 1 +
 configs/k2hk_evm_defconfig   | 1 +
 configs/k2hk_hs_evm_defconfig| 1 +
 configs/k2l_evm_defconfig| 1 +
 configs/k2l_hs_evm_defconfig | 1 +
 drivers/net/ti/Kconfig   | 5 +
 include/configs/ti_armv7_keystone2.h | 1 -
 10 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index d744cb1..67b1f30 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index 87faf3d..1abda84 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -49,3 +49,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index a96029c..bc4b92b 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -60,3 +60,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 9e75500..66d8220 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -53,3 +53,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 8c7d362..f66d922 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index c8f4bbe..dd91a51 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -49,3 +49,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index dd91aa5..4f04caa 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index ac400e4..9ce23de 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -48,3 +48,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 35a6b5d..c38e273 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -13,3 +13,8 @@ config DRIVER_TI_EMAC
bool "TI Davinci EMAC"
help
   Support for davinci emac
+
+config DRIVER_TI_KEYSTONE_NET
+   bool "TI Keystone 2 Ethernet"
+   help
+  This driver supports the TI Keystone 2 Ethernet subsystem
\ No newline at end of file
diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index cc823c5..5e504f6 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -128,7 +128,6 @@
 #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE   KS2_NETCP_PDMA_TX_SND_QUEUE
 
 /* Keystone net */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
 #define CONFIG_KSNET_MAC_ID_BASE   KS2_MAC_ID_BASE_ADDR
 #define CONFIG_KSNET_NETCP_BASEKS2_NETCP_BASE
 #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
-- 
2.10.5

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[U-Boot] [PATCH v3 4/7] driver: net: ti: cpsw: update to use SPDX identifier

[Grygorii Strashko]

Update to use SPDX license identifier.

Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger 
Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 12 ++--
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 8e2a48c..fe43d14 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * CPSW Ethernet Switch Driver
  *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 #include 
-- 
2.10.5

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[U-Boot] [PATCH v3 1/7] driver: net: consolidate ti's code in separate folder

[Grygorii Strashko]

Add drivers/net/ti/ folder and move all TI's code in this folder for better
maintenance.

Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger 
Signed-off-by: Grygorii Strashko 
---
 arch/arm/mach-davinci/dp83848.c |  2 +-
 arch/arm/mach-davinci/et1011c.c |  2 +-
 arch/arm/mach-davinci/ksz8873.c |  2 +-
 arch/arm/mach-davinci/lxt972.c  |  2 +-
 drivers/net/Kconfig | 13 +
 drivers/net/Makefile|  4 +---
 drivers/net/ti/Kconfig  | 15 +++
 drivers/net/ti/Makefile |  7 +++
 drivers/net/{ => ti}/cpsw-common.c  |  0
 drivers/net/{ => ti}/cpsw.c |  0
 drivers/net/{ => ti}/davinci_emac.c |  0
 drivers/net/{ => ti}/davinci_emac.h |  0
 drivers/net/{ => ti}/keystone_net.c |  0
 13 files changed, 28 insertions(+), 19 deletions(-)
 create mode 100644 drivers/net/ti/Kconfig
 create mode 100644 drivers/net/ti/Makefile
 rename drivers/net/{ => ti}/cpsw-common.c (100%)
 rename drivers/net/{ => ti}/cpsw.c (100%)
 rename drivers/net/{ => ti}/davinci_emac.c (100%)
 rename drivers/net/{ => ti}/davinci_emac.h (100%)
 rename drivers/net/{ => ti}/keystone_net.c (100%)

diff --git a/arch/arm/mach-davinci/dp83848.c b/arch/arm/mach-davinci/dp83848.c
index 595e3ca..7115d7b 100644
--- a/arch/arm/mach-davinci/dp83848.c
+++ b/arch/arm/mach-davinci/dp83848.c
@@ -12,7 +12,7 @@
 #include 
 #include 
 #include 
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 
diff --git a/arch/arm/mach-davinci/et1011c.c b/arch/arm/mach-davinci/et1011c.c
index 3d02274..bfb7ff2 100644
--- a/arch/arm/mach-davinci/et1011c.c
+++ b/arch/arm/mach-davinci/et1011c.c
@@ -9,7 +9,7 @@
 #include 
 #include 
 #include 
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 
diff --git a/arch/arm/mach-davinci/ksz8873.c b/arch/arm/mach-davinci/ksz8873.c
index 899cff0..85b0c26 100644
--- a/arch/arm/mach-davinci/ksz8873.c
+++ b/arch/arm/mach-davinci/ksz8873.c
@@ -19,7 +19,7 @@
 #include 
 #include 
 #include 
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
 
 int ksz8873_is_phy_connected(int phy_addr)
 {
diff --git a/arch/arm/mach-davinci/lxt972.c b/arch/arm/mach-davinci/lxt972.c
index 170e4a5..b54f67d 100644
--- a/arch/arm/mach-davinci/lxt972.c
+++ b/arch/arm/mach-davinci/lxt972.c
@@ -13,7 +13,7 @@
 #include 
 #include 
 #include 
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index f1f0e2d..e904c5e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,5 +1,6 @@
 source "drivers/net/phy/Kconfig"
 source "drivers/net/pfe_eth/Kconfig"
+source "drivers/net/ti/Kconfig"
 
 config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
@@ -11,13 +12,6 @@ config DM_ETH
  This is currently implemented in net/eth-uclass.c
  Look in include/net.h for details.
 
-config DRIVER_TI_CPSW
-   bool "TI Common Platform Ethernet Switch"
-   select PHYLIB
-   help
- This driver supports the TI three port switch gigabit ethernet
- subsystem found in the TI SoCs.
-
 menuconfig NETDEVICES
bool "Network device support"
depends on NET
@@ -322,11 +316,6 @@ config SH_ETHER
help
  This driver supports the Ethernet for Renesas SH and ARM SoCs.
 
-config DRIVER_TI_EMAC
-   bool "TI Davinci EMAC"
-   help
-  Support for davinci emac
-
 config XILINX_AXIEMAC
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 48a2878..8e33d7a 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -30,7 +30,6 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o
 obj-$(CONFIG_FTMAC110) += ftmac110.o
 obj-$(CONFIG_FTMAC100) += ftmac100.o
 obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
-obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
 obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
 obj-$(CONFIG_LAN91C96) += lan91c96.o
 obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
@@ -56,9 +55,7 @@ obj-$(CONFIG_SH_ETHER) += sh_eth.o
 obj-$(CONFIG_RENESAS_RAVB) += ravb.o
 obj-$(CONFIG_SMC9) += smc9.o
 obj-$(CONFIG_SMC911X) += smc911x.o
-obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
-obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
 obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
 obj-$(CONFIG_ULI526X) += uli526x.o
 obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
@@ -73,3 +70,4 @@ obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
 obj-$(CONFIG_DWC_ETH_QOS) +

[U-Boot] [PATCH v3 7/7] driver: net: ti: keystone_net: switch to use common mdio lib

[Grygorii Strashko]

Update TI Keystone 2 driver to re-use common mdio lib.

Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger 
Signed-off-by: Grygorii Strashko 
---
 arch/arm/include/asm/ti-common/keystone_net.h |  13 ---
 drivers/net/ti/Makefile   |   2 +-
 drivers/net/ti/keystone_net.c | 118 --
 3 files changed, 18 insertions(+), 115 deletions(-)

diff --git a/arch/arm/include/asm/ti-common/keystone_net.h 
b/arch/arm/include/asm/ti-common/keystone_net.h
index bef1867..bba1048 100644
--- a/arch/arm/include/asm/ti-common/keystone_net.h
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -57,19 +57,6 @@
 /* MDIO clock output frequency */
 #define EMAC_MDIO_CLOCK_FREQ   250 /* 2.5 MHz */
 
-/* MII Status Register */
-#define MII_STATUS_REG 1
-#define MII_STATUS_LINK_MASK   0x4
-
-#define MDIO_CONTROL_IDLE  0x8000
-#define MDIO_CONTROL_ENABLE0x4000
-#define MDIO_CONTROL_FAULT_ENABLE  0x4
-#define MDIO_CONTROL_FAULT 0x8
-#define MDIO_USERACCESS0_GO0x8000
-#define MDIO_USERACCESS0_WRITE_READ0x0
-#define MDIO_USERACCESS0_WRITE_WRITE   0x4000
-#define MDIO_USERACCESS0_ACK   0x2000
-
 #define EMAC_MACCONTROL_MIIEN_ENABLE   0x20
 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE  0x1
 #define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7)
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index d2b6f20..ee3e4eb 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -4,4 +4,4 @@
 
 obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
-obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c
index 5550572..a3ba91c 100644
--- a/drivers/net/ti/keystone_net.c
+++ b/drivers/net/ti/keystone_net.c
@@ -22,6 +22,8 @@
 #include 
 #include 
 
+#include "cpsw_mdio.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
@@ -97,93 +99,20 @@ struct ks2_eth_priv {
boolhas_mdio;
 };
 
-/* MDIO */
-
-static int keystone2_mdio_reset(struct mii_dev *bus)
-{
-   u_int32_t clkdiv;
-   struct mdio_regs *adap_mdio = bus->priv;
-
-   clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
-
-   writel((clkdiv & 0x) | MDIO_CONTROL_ENABLE |
-  MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
-  _mdio->control);
-
-   while (readl(_mdio->control) & MDIO_CONTROL_IDLE)
-   ;
-
-   return 0;
-}
-
-/**
- * keystone2_mdio_read - read a PHY register via MDIO interface.
- * Blocks until operation is complete.
- */
-static int keystone2_mdio_read(struct mii_dev *bus,
-  int addr, int devad, int reg)
-{
-   int tmp;
-   struct mdio_regs *adap_mdio = bus->priv;
-
-   while (readl(_mdio->useraccess0) & MDIO_USERACCESS0_GO)
-   ;
-
-   writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
-  ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
-  _mdio->useraccess0);
-
-   /* Wait for command to complete */
-   while ((tmp = readl(_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
-   ;
-
-   if (tmp & MDIO_USERACCESS0_ACK)
-   return tmp & 0x;
-
-   return -1;
-}
-
-/**
- * keystone2_mdio_write - write to a PHY register via MDIO interface.
- * Blocks until operation is complete.
- */
-static int keystone2_mdio_write(struct mii_dev *bus,
-   int addr, int devad, int reg, u16 val)
-{
-   struct mdio_regs *adap_mdio = bus->priv;
-
-   while (readl(_mdio->useraccess0) & MDIO_USERACCESS0_GO)
-   ;
-
-   writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
-  ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
-  (val & 0x), _mdio->useraccess0);
-
-   /* Wait for command to complete */
-   while (readl(_mdio->useraccess0) & MDIO_USERACCESS0_GO)
-   ;
-
-   return 0;
-}
-
 static void  __attribute__((unused))
keystone2_eth_gigabit_enable(struct udevice *dev)
 {
struct ks2_eth_priv *priv = dev_get_priv(dev);
-   u_int16_t data;
-
-   if (priv->has_mdio) {
-   data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr,
-  MDIO_DEVAD_NONE, 0);
-   /* speed selection MSB */
-   if (!(data & (1 << 6)))
-   return;
-   }
 
/*
 * Check if link detected is giga-bit
 * If Gigabit mode detected, enable gigbit in MAC
 */
+   if (priv->has_mdio) {
+   

[U-Boot] [PATCH v3 6/7] driver: net: ti: cpsw: switch to use common mdio lib

[Grygorii Strashko]

Update TI CPSW driver to re-use common mdio lib

Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger 
Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/cpsw.c | 134 +++---
 1 file changed, 6 insertions(+), 128 deletions(-)

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index fe43d14..f5fd02e 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -21,11 +21,11 @@
 #include 
 #include 
 
+#include "cpsw_mdio.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define BITMASK(bits)  (BIT(bits) - 1)
-#define PHY_REG_MASK   0x1f
-#define PHY_ID_MASK0x1f
 #define NUM_DESCS  (PKTBUFSRX * 2)
 #define PKT_MIN60
 #define PKT_MAX(1500 + 14 + 4 + 4)
@@ -76,37 +76,8 @@ DECLARE_GLOBAL_DATA_PTR;
  * unexpected controller lock ups.  Ideally, we should never ever hit this
  * scenario in practice.
  */
-#define MDIO_TIMEOUT100 /* msecs */
 #define CPDMA_TIMEOUT  100 /* msecs */
 
-struct cpsw_mdio_regs {
-   u32 version;
-   u32 control;
-#define CONTROL_IDLE   BIT(31)
-#define CONTROL_ENABLE BIT(30)
-
-   u32 alive;
-   u32 link;
-   u32 linkintraw;
-   u32 linkintmasked;
-   u32 __reserved_0[2];
-   u32 userintraw;
-   u32 userintmasked;
-   u32 userintmaskset;
-   u32 userintmaskclr;
-   u32 __reserved_1[20];
-
-   struct {
-   u32 access;
-   u32 physel;
-#define USERACCESS_GO  BIT(31)
-#define USERACCESS_WRITE   BIT(30)
-#define USERACCESS_ACK BIT(29)
-#define USERACCESS_READ(0)
-#define USERACCESS_DATA(0x)
-   } user[0];
-};
-
 struct cpsw_regs {
u32 id_ver;
u32 control;
@@ -484,100 +455,6 @@ static inline void cpsw_ale_port_state(struct cpsw_priv 
*priv, int port,
__raw_writel(tmp, priv->ale_regs + offset);
 }
 
-static struct cpsw_mdio_regs *mdio_regs;
-
-/* wait until hardware is ready for another user access */
-static inline u32 wait_for_user_access(void)
-{
-   u32 reg = 0;
-   int timeout = MDIO_TIMEOUT;
-
-   while (timeout-- &&
-   ((reg = __raw_readl(_regs->user[0].access)) & USERACCESS_GO))
-   udelay(10);
-
-   if (timeout == -1) {
-   printf("wait_for_user_access Timeout\n");
-   return -ETIMEDOUT;
-   }
-   return reg;
-}
-
-/* wait until hardware state machine is idle */
-static inline void wait_for_idle(void)
-{
-   int timeout = MDIO_TIMEOUT;
-
-   while (timeout-- &&
-   ((__raw_readl(_regs->control) & CONTROL_IDLE) == 0))
-   udelay(10);
-
-   if (timeout == -1)
-   printf("wait_for_idle Timeout\n");
-}
-
-static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
-   int dev_addr, int phy_reg)
-{
-   int data;
-   u32 reg;
-
-   if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
-   return -EINVAL;
-
-   wait_for_user_access();
-   reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
-  (phy_id << 16));
-   __raw_writel(reg, _regs->user[0].access);
-   reg = wait_for_user_access();
-
-   data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
-   return data;
-}
-
-static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
-   int phy_reg, u16 data)
-{
-   u32 reg;
-
-   if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
-   return -EINVAL;
-
-   wait_for_user_access();
-   reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
-  (phy_id << 16) | (data & USERACCESS_DATA));
-   __raw_writel(reg, _regs->user[0].access);
-   wait_for_user_access();
-
-   return 0;
-}
-
-static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div)
-{
-   struct mii_dev *bus = mdio_alloc();
-
-   mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
-
-   /* set enable and clock divider */
-   __raw_writel(div | CONTROL_ENABLE, _regs->control);
-
-   /*
-* wait for scan logic to settle:
-* the scan time consists of (a) a large fixed component, and (b) a
-* small component that varies with the mii bus frequency.  These
-* were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
-* silicon.  Since the effect of (b) was found to be largely
-* negligible, we keep things simple here.
-*/
-   udelay(1000);
-
-   bus->read = cpsw_mdio_read;
-   bus->write = cpsw_mdio_write;
-   strcpy(bus->name, name);
-
-   mdio_register(bus);
-}
-
 /* Set a self-clearing bit in a

[U-Boot] [PATCH v3 3/7] drivers: net: keystone_net: drop non dm code

[Grygorii Strashko]

Networking support for all TI K2 boards converted to use DM model and
CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop
unused non DM K2 networking code.

Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger 
Signed-off-by: Grygorii Strashko 
---
 arch/arm/include/asm/ti-common/keystone_net.h |  14 --
 board/ti/ks2_evm/board.c  |  53 -
 board/ti/ks2_evm/board.h  |   3 -
 board/ti/ks2_evm/board_k2e.c  |  74 ---
 board/ti/ks2_evm/board_k2g.c  |  18 --
 board/ti/ks2_evm/board_k2hk.c |  42 
 board/ti/ks2_evm/board_k2l.c  |  42 
 drivers/net/ti/keystone_net.c | 287 +-
 8 files changed, 1 insertion(+), 532 deletions(-)

diff --git a/arch/arm/include/asm/ti-common/keystone_net.h 
b/arch/arm/include/asm/ti-common/keystone_net.h
index f89e043..bef1867 100644
--- a/arch/arm/include/asm/ti-common/keystone_net.h
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -242,18 +242,4 @@ struct mdio_regs {
u32 userphysel1;
 };
 
-struct eth_priv_t {
-   char int_name[32];
-   int rx_flow;
-   int phy_addr;
-   int slave_port;
-   int sgmii_link_type;
-   phy_interface_t phy_if;
-   struct phy_device *phy_dev;
-};
-
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
-void sgmii_serdes_setup_156p25mhz(void);
-void sgmii_serdes_shutdown(void);
-
 #endif  /* _KEYSTONE_NET_H_ */
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index d81c8e6..72709c0 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -66,59 +66,6 @@ int board_init(void)
return 0;
 }
 
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-#ifndef CONFIG_DM_ETH
-int get_eth_env_param(char *env_name)
-{
-   char *env;
-   int res = -1;
-
-   env = env_get(env_name);
-   if (env)
-   res = simple_strtol(env, NULL, 0);
-
-   return res;
-}
-
-int board_eth_init(bd_t *bis)
-{
-   int j;
-   int res;
-   int port_num;
-   char link_type_name[32];
-
-   if (cpu_is_k2g())
-   writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
-
-   /* By default, select PA PLL clock as PA clock source */
-#ifndef CONFIG_SOC_K2G
-   if (psc_enable_module(KS2_LPSC_PA))
-   return -1;
-#endif
-   if (psc_enable_module(KS2_LPSC_CPGMAC))
-   return -1;
-   if (psc_enable_module(KS2_LPSC_CRYPTO))
-   return -1;
-
-   if (cpu_is_k2e() || cpu_is_k2l())
-   pll_pa_clk_sel();
-
-   port_num = get_num_eth_ports();
-
-   for (j = 0; j < port_num; j++) {
-   sprintf(link_type_name, "sgmii%d_link_type", j);
-   res = get_eth_env_param(link_type_name);
-   if (res >= 0)
-   eth_priv_cfg[j].sgmii_link_type = res;
-
-   keystone2_emac_initialize(_priv_cfg[j]);
-   }
-
-   return 0;
-}
-#endif
-#endif
-
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index 250b649..d0cfbf5 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -12,8 +12,6 @@
 #include 
 #include "../common/board_detect.h"
 
-extern struct eth_priv_t eth_priv_cfg[];
-
 #if defined(CONFIG_TI_I2C_BOARD_DETECT)
 static inline int board_is_k2g_gp(void)
 {
@@ -38,7 +36,6 @@ static inline int board_is_k2g_ice(void)
 }
 #endif
 
-int get_num_eth_ports(void);
 void spl_init_keystone_plls(void);
 
 #endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index f86a836..ecd4a42 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -89,80 +89,6 @@ struct pll_init_data *get_pll_init_data(int pll)
return data;
 }
 
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
-   {
-   .int_name= "K2E_EMAC0",
-   .rx_flow = 0,
-   .phy_addr= 0,
-   .slave_port  = 1,
-   .sgmii_link_type = SGMII_LINK_MAC_PHY,
-   .phy_if  = PHY_INTERFACE_MODE_SGMII,
-   },
-   {
-   .int_name= "K2E_EMAC1",
-   .rx_flow = 8,
-   .phy_addr= 1,
-   .slave_port  = 2,
-   .sgmii_link_type = SGMII_LINK_MAC_PHY,
-   .phy_if  = PHY_INTERFACE_MODE_SGMII,
-   },
-   {
-   .int_name= "K2E_EMAC2",
-   .rx_flow = 16,
-   .phy_addr= 2,
-   .slave_port  = 3,
-   .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
-   .phy_if  = PHY_INTERFACE_MODE_SGMII,
-   },
-   {
-   .int_name= "K2E_EMAC3",
-   .rx_flow = 24,
-   

[U-Boot] [PATCH v3 5/7] driver: net: ti: introduce common mdio support library

[Grygorii Strashko]

All existing TI SoCs network HW have similar MDIO implementation, so
introduce common mdio support library which can be reused by TI networking
drivers.

Reviewed-by: Tom Rini 
Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/Makefile|   2 +-
 drivers/net/ti/cpsw_mdio.c | 203 +
 drivers/net/ti/cpsw_mdio.h |  18 
 3 files changed, 222 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/ti/cpsw_mdio.c
 create mode 100644 drivers/net/ti/cpsw_mdio.h

diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index 4ab4a27..d2b6f20 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -2,6 +2,6 @@
 #
 # Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
 
-obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
+obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c
new file mode 100644
index 000..70f547e
--- /dev/null
+++ b/drivers/net/ti/cpsw_mdio.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices.
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+struct cpsw_mdio_regs {
+   u32 version;
+   u32 control;
+#define CONTROL_IDLE   BIT(31)
+#define CONTROL_ENABLE BIT(30)
+#define CONTROL_FAULT  BIT(19)
+#define CONTROL_FAULT_ENABLE   BIT(18)
+#define CONTROL_DIV_MASK   GENMASK(15, 0)
+
+   u32 alive;
+   u32 link;
+   u32 linkintraw;
+   u32 linkintmasked;
+   u32 __reserved_0[2];
+   u32 userintraw;
+   u32 userintmasked;
+   u32 userintmaskset;
+   u32 userintmaskclr;
+   u32 __reserved_1[20];
+
+   struct {
+   u32 access;
+   u32 physel;
+#define USERACCESS_GO  BIT(31)
+#define USERACCESS_WRITE   BIT(30)
+#define USERACCESS_ACK BIT(29)
+#define USERACCESS_READ(0)
+#define USERACCESS_PHY_REG_SHIFT   (21)
+#define USERACCESS_PHY_ADDR_SHIFT  (16)
+#define USERACCESS_DATAGENMASK(15, 0)
+   } user[0];
+};
+
+#define CPSW_MDIO_DIV_DEF  0xff
+#define PHY_REG_MASK   0x1f
+#define PHY_ID_MASK0x1f
+
+/*
+ * This timeout definition is a worst-case ultra defensive measure against
+ * unexpected controller lock ups.  Ideally, we should never ever hit this
+ * scenario in practice.
+ */
+#define CPSW_MDIO_TIMEOUT100 /* msecs */
+
+struct cpsw_mdio {
+   struct cpsw_mdio_regs *regs;
+   struct mii_dev *bus;
+   int div;
+};
+
+/* wait until hardware is ready for another user access */
+static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio)
+{
+   return wait_for_bit_le32(>regs->user[0].access,
+USERACCESS_GO, false,
+CPSW_MDIO_TIMEOUT, false);
+}
+
+static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
+ int dev_addr, int phy_reg)
+{
+   struct cpsw_mdio *mdio = bus->priv;
+   int data, ret;
+   u32 reg;
+
+   if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+   return -EINVAL;
+
+   ret = cpsw_mdio_wait_for_user_access(mdio);
+   if (ret)
+   return ret;
+   reg = (USERACCESS_GO | USERACCESS_READ |
+  (phy_reg << USERACCESS_PHY_REG_SHIFT) |
+  (phy_id << USERACCESS_PHY_ADDR_SHIFT));
+   writel(reg, >regs->user[0].access);
+   ret = cpsw_mdio_wait_for_user_access(mdio);
+   if (ret)
+   return ret;
+
+   reg = readl(>regs->user[0].access);
+   data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
+   return data;
+}
+
+static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
+  int phy_reg, u16 data)
+{
+   struct cpsw_mdio *mdio = bus->priv;
+   u32 reg;
+   int ret;
+
+   if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+   return -EINVAL;
+
+   ret = cpsw_mdio_wait_for_user_access(mdio);
+   if (ret)
+   return ret;
+   reg = (USERACCESS_GO | USERACCESS_WRITE |
+  (phy_reg << USERACCESS_PHY_REG_SHIFT) |
+  (phy_id << USERACCESS_PHY_ADDR_SHIFT) |
+  (data & USERACCESS_DATA));
+   writel(reg, >regs->user[0].access);
+
+   return cpsw_mdio_wait_for_user_access(mdio);
+}
+
+u32 cpsw_mdio_get_alive(struct mii_dev *bus)
+{
+   struct cpsw_mdio *mdio = bus->priv;
+   u32 val;
+
+   val = readl(>regs->control);
+   return

[U-Boot] [PATCH v2 3/7] drivers: net: keystone_net: drop non dm code

[Grygorii Strashko]

Networking support for all TI K2 boards converted to use DM model and
CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop
unused non DM K2 networking code.

Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger 
Signed-off-by: Grygorii Strashko 
---
 arch/arm/include/asm/ti-common/keystone_net.h |  14 --
 board/ti/ks2_evm/board.c  |  53 -
 board/ti/ks2_evm/board.h  |   3 -
 board/ti/ks2_evm/board_k2e.c  |  74 ---
 board/ti/ks2_evm/board_k2g.c  |  18 --
 board/ti/ks2_evm/board_k2hk.c |  42 
 board/ti/ks2_evm/board_k2l.c  |  42 
 drivers/net/ti/keystone_net.c | 287 +-
 8 files changed, 1 insertion(+), 532 deletions(-)

diff --git a/arch/arm/include/asm/ti-common/keystone_net.h 
b/arch/arm/include/asm/ti-common/keystone_net.h
index f89e043..bef1867 100644
--- a/arch/arm/include/asm/ti-common/keystone_net.h
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -242,18 +242,4 @@ struct mdio_regs {
u32 userphysel1;
 };
 
-struct eth_priv_t {
-   char int_name[32];
-   int rx_flow;
-   int phy_addr;
-   int slave_port;
-   int sgmii_link_type;
-   phy_interface_t phy_if;
-   struct phy_device *phy_dev;
-};
-
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
-void sgmii_serdes_setup_156p25mhz(void);
-void sgmii_serdes_shutdown(void);
-
 #endif  /* _KEYSTONE_NET_H_ */
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index d81c8e6..72709c0 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -66,59 +66,6 @@ int board_init(void)
return 0;
 }
 
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-#ifndef CONFIG_DM_ETH
-int get_eth_env_param(char *env_name)
-{
-   char *env;
-   int res = -1;
-
-   env = env_get(env_name);
-   if (env)
-   res = simple_strtol(env, NULL, 0);
-
-   return res;
-}
-
-int board_eth_init(bd_t *bis)
-{
-   int j;
-   int res;
-   int port_num;
-   char link_type_name[32];
-
-   if (cpu_is_k2g())
-   writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
-
-   /* By default, select PA PLL clock as PA clock source */
-#ifndef CONFIG_SOC_K2G
-   if (psc_enable_module(KS2_LPSC_PA))
-   return -1;
-#endif
-   if (psc_enable_module(KS2_LPSC_CPGMAC))
-   return -1;
-   if (psc_enable_module(KS2_LPSC_CRYPTO))
-   return -1;
-
-   if (cpu_is_k2e() || cpu_is_k2l())
-   pll_pa_clk_sel();
-
-   port_num = get_num_eth_ports();
-
-   for (j = 0; j < port_num; j++) {
-   sprintf(link_type_name, "sgmii%d_link_type", j);
-   res = get_eth_env_param(link_type_name);
-   if (res >= 0)
-   eth_priv_cfg[j].sgmii_link_type = res;
-
-   keystone2_emac_initialize(_priv_cfg[j]);
-   }
-
-   return 0;
-}
-#endif
-#endif
-
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index 250b649..d0cfbf5 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -12,8 +12,6 @@
 #include 
 #include "../common/board_detect.h"
 
-extern struct eth_priv_t eth_priv_cfg[];
-
 #if defined(CONFIG_TI_I2C_BOARD_DETECT)
 static inline int board_is_k2g_gp(void)
 {
@@ -38,7 +36,6 @@ static inline int board_is_k2g_ice(void)
 }
 #endif
 
-int get_num_eth_ports(void);
 void spl_init_keystone_plls(void);
 
 #endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index f86a836..ecd4a42 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -89,80 +89,6 @@ struct pll_init_data *get_pll_init_data(int pll)
return data;
 }
 
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
-   {
-   .int_name= "K2E_EMAC0",
-   .rx_flow = 0,
-   .phy_addr= 0,
-   .slave_port  = 1,
-   .sgmii_link_type = SGMII_LINK_MAC_PHY,
-   .phy_if  = PHY_INTERFACE_MODE_SGMII,
-   },
-   {
-   .int_name= "K2E_EMAC1",
-   .rx_flow = 8,
-   .phy_addr= 1,
-   .slave_port  = 2,
-   .sgmii_link_type = SGMII_LINK_MAC_PHY,
-   .phy_if  = PHY_INTERFACE_MODE_SGMII,
-   },
-   {
-   .int_name= "K2E_EMAC2",
-   .rx_flow = 16,
-   .phy_addr= 2,
-   .slave_port  = 3,
-   .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
-   .phy_if  = PHY_INTERFACE_MODE_SGMII,
-   },
-   {
-   .int_name= "K2E_EMAC3",
-   .rx_flow = 24,
-   

[U-Boot] [PATCH v2 5/7] driver: net: ti: introduce common mdio support library

[Grygorii Strashko]

All existing TI SoCs network HW have similar MDIO implementation, so
introduce common mdio support library which can be reused by TI networking
drivers.

Reviewed-by: Tom Rini 
Signed-off-by: Grygorii Strashko 
---
 drivers/net/ti/Makefile|   2 +-
 drivers/net/ti/cpsw_mdio.c | 201 +
 drivers/net/ti/cpsw_mdio.h |  18 
 3 files changed, 220 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/ti/cpsw_mdio.c
 create mode 100644 drivers/net/ti/cpsw_mdio.h

diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index 4ab4a27..d2b6f20 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -2,6 +2,6 @@
 #
 # Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
 
-obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
+obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c
new file mode 100644
index 000..f4211b7
--- /dev/null
+++ b/drivers/net/ti/cpsw_mdio.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices.
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+struct cpsw_mdio_regs {
+   u32 version;
+   u32 control;
+#define CONTROL_IDLE   BIT(31)
+#define CONTROL_ENABLE BIT(30)
+#define CONTROL_FAULT  BIT(19)
+#define CONTROL_FAULT_ENABLE   BIT(18)
+#define CONTROL_DIV_MASK   GENMASK(15, 0)
+
+   u32 alive;
+   u32 link;
+   u32 linkintraw;
+   u32 linkintmasked;
+   u32 __reserved_0[2];
+   u32 userintraw;
+   u32 userintmasked;
+   u32 userintmaskset;
+   u32 userintmaskclr;
+   u32 __reserved_1[20];
+
+   struct {
+   u32 access;
+   u32 physel;
+#define USERACCESS_GO  BIT(31)
+#define USERACCESS_WRITE   BIT(30)
+#define USERACCESS_ACK BIT(29)
+#define USERACCESS_READ(0)
+#define USERACCESS_PHY_REG_SHIFT   (21)
+#define USERACCESS_PHY_ADDR_SHIFT  (16)
+#define USERACCESS_DATAGENMASK(15, 0)
+   } user[0];
+};
+
+#define CPSW_MDIO_DIV_DEF  0xff
+#define PHY_REG_MASK   0x1f
+#define PHY_ID_MASK0x1f
+
+/*
+ * This timeout definition is a worst-case ultra defensive measure against
+ * unexpected controller lock ups.  Ideally, we should never ever hit this
+ * scenario in practice.
+ */
+#define CPSW_MDIO_TIMEOUT100 /* msecs */
+
+struct cpsw_mdio {
+   struct cpsw_mdio_regs *regs;
+   struct mii_dev *bus;
+   int div;
+};
+
+/* wait until hardware is ready for another user access */
+static inline u32 cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio)
+{
+   int ret;
+
+   ret = wait_for_bit_le32(>regs->user[0].access,
+   USERACCESS_GO, false, CPSW_MDIO_TIMEOUT, false);
+   if (ret)
+   return ret;
+
+   return readl(>regs->user[0].access);
+}
+
+static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
+ int dev_addr, int phy_reg)
+{
+   struct cpsw_mdio *mdio = bus->priv;
+   int data;
+   u32 reg;
+
+   if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+   return -EINVAL;
+
+   cpsw_mdio_wait_for_user_access(mdio);
+   reg = (USERACCESS_GO | USERACCESS_READ |
+  (phy_reg << USERACCESS_PHY_REG_SHIFT) |
+  (phy_id << USERACCESS_PHY_ADDR_SHIFT));
+   writel(reg, >regs->user[0].access);
+   reg = cpsw_mdio_wait_for_user_access(mdio);
+
+   data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
+   return data;
+}
+
+static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
+  int phy_reg, u16 data)
+{
+   struct cpsw_mdio *mdio = bus->priv;
+   u32 reg;
+
+   if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+   return -EINVAL;
+
+   cpsw_mdio_wait_for_user_access(mdio);
+   reg = (USERACCESS_GO | USERACCESS_WRITE |
+  (phy_reg << USERACCESS_PHY_REG_SHIFT) |
+  (phy_id << USERACCESS_PHY_ADDR_SHIFT) |
+  (data & USERACCESS_DATA));
+   writel(reg, >regs->user[0].access);
+   cpsw_mdio_wait_for_user_access(mdio);
+
+   return 0;
+}
+
+u32 cpsw_mdio_get_alive(struct mii_dev *bus)
+{
+   struct cpsw_mdio *mdio = bus->priv;
+   u32 val;
+
+   val = readl(>regs->control);
+   return val & GENMASK(15, 0);
+}
+
+struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base,
+  u32 bus_f

[U-Boot] [PATCH v2 2/7] configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig

[Grygorii Strashko]

Convert DRIVER_TI_KEYSTONE_NET to Kconfig.

Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger 
Signed-off-by: Grygorii Strashko 
---
 configs/k2e_evm_defconfig| 1 +
 configs/k2e_hs_evm_defconfig | 1 +
 configs/k2g_evm_defconfig| 1 +
 configs/k2g_hs_evm_defconfig | 1 +
 configs/k2hk_evm_defconfig   | 1 +
 configs/k2hk_hs_evm_defconfig| 1 +
 configs/k2l_evm_defconfig| 1 +
 configs/k2l_hs_evm_defconfig | 1 +
 drivers/net/ti/Kconfig   | 5 +
 include/configs/ti_armv7_keystone2.h | 1 -
 10 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index d744cb1..67b1f30 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index 87faf3d..1abda84 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -49,3 +49,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index a96029c..bc4b92b 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -60,3 +60,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 9e75500..66d8220 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -53,3 +53,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 8c7d362..f66d922 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index c8f4bbe..dd91a51 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -49,3 +49,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index dd91aa5..4f04caa 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index ac400e4..9ce23de 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -48,3 +48,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 35a6b5d..c38e273 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -13,3 +13,8 @@ config DRIVER_TI_EMAC
bool "TI Davinci EMAC"
help
   Support for davinci emac
+
+config DRIVER_TI_KEYSTONE_NET
+   bool "TI Keystone 2 Ethernet"
+   help
+  This driver supports the TI Keystone 2 Ethernet subsystem
\ No newline at end of file
diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index cc823c5..5e504f6 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -128,7 +128,6 @@
 #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE   KS2_NETCP_PDMA_TX_SND_QUEUE
 
 /* Keystone net */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
 #define CONFIG_KSNET_MAC_ID_BASE   KS2_MAC_ID_BASE_ADDR
 #define CONFIG_KSNET_NETCP_BASEKS2_NETCP_BASE
 #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
-- 
2.10.5

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[U-Boot] [PATCH v2 0/7] driver: net: ti: clean up and code optimization

[Grygorii Strashko]

This series contains set of code clean up and optimizations for TI networking 
drivers.
Patch 1 - Adds drivers/net/ti/ folder and moves all TI's networking code
 in this folder.
Patches 2,3 - keystone2 clean up
Patch 5 - introduces common TI MDIO support library as existing TI SoCs network
 HW IPs have similar MDIO implementation.
Patches 6-7 - conversation of TI CPSW and keystone_net drivers to use common
 TI MDIO support library

tested dhcp and kernel boot on:
- k2e/g/hk/l evms 
- am437x-gpevm and AM5748 IDK

changes in v2:
 - patch 5 comments fixed: use wait_for_bit, snprintf, mdelay, mdio_free 

TODO: TODO: As per code and documentation davinci_emac.c seems also can be
re-worked to use common TI MDIO support library and network PHYs framework.
Unfortunately, I have no HW to work with.

Grygorii Strashko (7):
  driver: net: consolidate ti's code in separate folder
  configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig
  drivers: net: keystone_net: drop non dm code
  driver: net: ti: cpsw: update to use SPDX identifier
  driver: net: ti: introduce common mdio support library
  driver: net: ti: cpsw: switch to use common mdio lib
  driver: net: ti: keystone_net: switch to use common mdio lib

 arch/arm/include/asm/ti-common/keystone_net.h |  27 --
 arch/arm/mach-davinci/dp83848.c   |   2 +-
 arch/arm/mach-davinci/et1011c.c   |   2 +-
 arch/arm/mach-davinci/ksz8873.c   |   2 +-
 arch/arm/mach-davinci/lxt972.c|   2 +-
 board/ti/ks2_evm/board.c  |  53 
 board/ti/ks2_evm/board.h  |   3 -
 board/ti/ks2_evm/board_k2e.c  |  74 -
 board/ti/ks2_evm/board_k2g.c  |  18 --
 board/ti/ks2_evm/board_k2hk.c |  42 ---
 board/ti/ks2_evm/board_k2l.c  |  42 ---
 configs/k2e_evm_defconfig |   1 +
 configs/k2e_hs_evm_defconfig  |   1 +
 configs/k2g_evm_defconfig |   1 +
 configs/k2g_hs_evm_defconfig  |   1 +
 configs/k2hk_evm_defconfig|   1 +
 configs/k2hk_hs_evm_defconfig |   1 +
 configs/k2l_evm_defconfig |   1 +
 configs/k2l_hs_evm_defconfig  |   1 +
 drivers/net/Kconfig   |  13 +-
 drivers/net/Makefile  |   4 +-
 drivers/net/ti/Kconfig|  20 ++
 drivers/net/ti/Makefile   |   7 +
 drivers/net/{ => ti}/cpsw-common.c|   0
 drivers/net/{ => ti}/cpsw.c   | 146 +-
 drivers/net/ti/cpsw_mdio.c| 201 +
 drivers/net/ti/cpsw_mdio.h|  18 ++
 drivers/net/{ => ti}/davinci_emac.c   |   0
 drivers/net/{ => ti}/davinci_emac.h   |   0
 drivers/net/{ => ti}/keystone_net.c   | 401 +-
 include/configs/ti_armv7_keystone2.h  |   1 -
 31 files changed, 284 insertions(+), 802 deletions(-)
 create mode 100644 drivers/net/ti/Kconfig
 create mode 100644 drivers/net/ti/Makefile
 rename drivers/net/{ => ti}/cpsw-common.c (100%)
 rename drivers/net/{ => ti}/cpsw.c (90%)
 create mode 100644 drivers/net/ti/cpsw_mdio.c
 create mode 100644 drivers/net/ti/cpsw_mdio.h
 rename drivers/net/{ => ti}/davinci_emac.c (100%)
 rename drivers/net/{ => ti}/davinci_emac.h (100%)
 rename drivers/net/{ => ti}/keystone_net.c (68%)

-- 
2.10.5

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[U-Boot] [PATCH v2 7/7] driver: net: ti: keystone_net: switch to use common mdio lib

[Grygorii Strashko]

Update TI Keystone 2 driver to re-use common mdio lib.

Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger 
Signed-off-by: Grygorii Strashko 
---
 arch/arm/include/asm/ti-common/keystone_net.h |  13 ---
 drivers/net/ti/Makefile   |   2 +-
 drivers/net/ti/keystone_net.c | 118 --
 3 files changed, 18 insertions(+), 115 deletions(-)

diff --git a/arch/arm/include/asm/ti-common/keystone_net.h 
b/arch/arm/include/asm/ti-common/keystone_net.h
index bef1867..bba1048 100644
--- a/arch/arm/include/asm/ti-common/keystone_net.h
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -57,19 +57,6 @@
 /* MDIO clock output frequency */
 #define EMAC_MDIO_CLOCK_FREQ   250 /* 2.5 MHz */
 
-/* MII Status Register */
-#define MII_STATUS_REG 1
-#define MII_STATUS_LINK_MASK   0x4
-
-#define MDIO_CONTROL_IDLE  0x8000
-#define MDIO_CONTROL_ENABLE0x4000
-#define MDIO_CONTROL_FAULT_ENABLE  0x4
-#define MDIO_CONTROL_FAULT 0x8
-#define MDIO_USERACCESS0_GO0x8000
-#define MDIO_USERACCESS0_WRITE_READ0x0
-#define MDIO_USERACCESS0_WRITE_WRITE   0x4000
-#define MDIO_USERACCESS0_ACK   0x2000
-
 #define EMAC_MACCONTROL_MIIEN_ENABLE   0x20
 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE  0x1
 #define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7)
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index d2b6f20..ee3e4eb 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -4,4 +4,4 @@
 
 obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
-obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c
index 5550572..a3ba91c 100644
--- a/drivers/net/ti/keystone_net.c
+++ b/drivers/net/ti/keystone_net.c
@@ -22,6 +22,8 @@
 #include 
 #include 
 
+#include "cpsw_mdio.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
@@ -97,93 +99,20 @@ struct ks2_eth_priv {
boolhas_mdio;
 };
 
-/* MDIO */
-
-static int keystone2_mdio_reset(struct mii_dev *bus)
-{
-   u_int32_t clkdiv;
-   struct mdio_regs *adap_mdio = bus->priv;
-
-   clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
-
-   writel((clkdiv & 0x) | MDIO_CONTROL_ENABLE |
-  MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
-  _mdio->control);
-
-   while (readl(_mdio->control) & MDIO_CONTROL_IDLE)
-   ;
-
-   return 0;
-}
-
-/**
- * keystone2_mdio_read - read a PHY register via MDIO interface.
- * Blocks until operation is complete.
- */
-static int keystone2_mdio_read(struct mii_dev *bus,
-  int addr, int devad, int reg)
-{
-   int tmp;
-   struct mdio_regs *adap_mdio = bus->priv;
-
-   while (readl(_mdio->useraccess0) & MDIO_USERACCESS0_GO)
-   ;
-
-   writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
-  ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
-  _mdio->useraccess0);
-
-   /* Wait for command to complete */
-   while ((tmp = readl(_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
-   ;
-
-   if (tmp & MDIO_USERACCESS0_ACK)
-   return tmp & 0x;
-
-   return -1;
-}
-
-/**
- * keystone2_mdio_write - write to a PHY register via MDIO interface.
- * Blocks until operation is complete.
- */
-static int keystone2_mdio_write(struct mii_dev *bus,
-   int addr, int devad, int reg, u16 val)
-{
-   struct mdio_regs *adap_mdio = bus->priv;
-
-   while (readl(_mdio->useraccess0) & MDIO_USERACCESS0_GO)
-   ;
-
-   writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
-  ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
-  (val & 0x), _mdio->useraccess0);
-
-   /* Wait for command to complete */
-   while (readl(_mdio->useraccess0) & MDIO_USERACCESS0_GO)
-   ;
-
-   return 0;
-}
-
 static void  __attribute__((unused))
keystone2_eth_gigabit_enable(struct udevice *dev)
 {
struct ks2_eth_priv *priv = dev_get_priv(dev);
-   u_int16_t data;
-
-   if (priv->has_mdio) {
-   data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr,
-  MDIO_DEVAD_NONE, 0);
-   /* speed selection MSB */
-   if (!(data & (1 << 6)))
-   return;
-   }
 
/*
 * Check if link detected is giga-bit
 * If Gigabit mode detected, enable gigbit in MAC
 */
+   if (priv->has_mdio) {
+