[U-Boot] [PATCHv2 13/14] powerpc: mpc8548cds: extend the reserved length for monitor
Extend the reserved length for monitor to fix the following build error: BINMAN u-boot-with-dtb.bin Wrote map file './image.map' to show errors binman: Section '/binman': contents size 0x8 (524288) exceeds section size 0x4 (262144) Makefile:1373: recipe for target 'u-boot-with-dtb.bin' failed make: *** [u-boot-with-dtb.bin] Error 1 Signed-off-by: Hou Zhiqiang --- V2: - No change. include/configs/MPC8548CDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b37601c..4252fbe 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -289,7 +289,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv2 12/14] powerpc: dts: add default definition of CONFIG_RESET_VECTOR_ADDRESS
Add CONFIG_RESET_VECTOR_ADDRESS definition with the default value
in u-boot.dtsi to fix the build error below. In the configuration
header file of some MPC85xx boards, there is not the definition
of CONFIG_RESET_VECTOR_ADDRESS, while CONFIG_SYS_MPC85XX_NO_RESETVEC
is also not defined. In this case, it will lack of definition of
CONFIG_RESET_VECTOR_ADDRESS in u-boot.dtsi, and the address
0xfffc will be used as the boot page by default.
Error log:
DTC arch/powerpc/dts/mpc8548cds.dtb
DTC arch/powerpc/dts/mpc8548cds_36b.dtb
Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error
FATAL ERROR: Unable to parse input tree
Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:308: recipe for target 'arch/powerpc/dts/mpc8548cds.dtb'
failed
make[2]: *** [arch/powerpc/dts/mpc8548cds.dtb] Error 1
make[2]: *** Waiting for unfinished jobs
scripts/Makefile.lib:308: recipe for target
'arch/powerpc/dts/mpc8548cds_36b.dtb' failed
make[2]: *** [arch/powerpc/dts/mpc8548cds_36b.dtb] Error 1
dts/Makefile:38: recipe for target 'arch-dtbs' failed
make[1]: *** [arch-dtbs] Error 2
Makefile:1038: recipe for target 'dts/dt.dtb' failed
make: *** [dts/dt.dtb] Error 2
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi
index 213d543..9661f4d 100644
--- a/arch/powerpc/dts/u-boot.dtsi
+++ b/arch/powerpc/dts/u-boot.dtsi
@@ -24,6 +24,9 @@
#endif
};
#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffc
+#endif
powerpc-mpc85xx-bootpg-resetvec {
offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
};
--
2.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv2 06/14] powerpc: Enable device tree support for P1020RDB
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile| 2 ++
arch/powerpc/dts/e500v2_power_isa.dtsi | 26 +++
arch/powerpc/dts/p1020-post.dtsi | 27
arch/powerpc/dts/p1020.dtsi | 31
arch/powerpc/dts/p1020rdb-pc.dts | 23 +
arch/powerpc/dts/p1020rdb-pc_36b.dts | 23 +
arch/powerpc/dts/p1020rdb-pd.dts | 23 +
board/freescale/p1_p2_rdb_pc/README | 19 +
configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 ++
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 ++
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++
configs/P1020RDB-PC_36BIT_defconfig | 3 +++
configs/P1020RDB-PC_NAND_defconfig | 2 ++
configs/P1020RDB-PC_SDCARD_defconfig | 2 ++
configs/P1020RDB-PC_SPIFLASH_defconfig | 2 ++
configs/P1020RDB-PC_defconfig| 3 +++
configs/P1020RDB-PD_NAND_defconfig | 2 ++
configs/P1020RDB-PD_SDCARD_defconfig | 2 ++
configs/P1020RDB-PD_SPIFLASH_defconfig | 2 ++
configs/P1020RDB-PD_defconfig| 3 +++
20 files changed, 201 insertions(+)
create mode 100644 arch/powerpc/dts/e500v2_power_isa.dtsi
create mode 100644 arch/powerpc/dts/p1020-post.dtsi
create mode 100644 arch/powerpc/dts/p1020.dtsi
create mode 100644 arch/powerpc/dts/p1020rdb-pc.dts
create mode 100644 arch/powerpc/dts/p1020rdb-pc_36b.dts
create mode 100644 arch/powerpc/dts/p1020rdb-pd.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index f0d49aa..3a806bd 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
+dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
+dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
diff --git a/arch/powerpc/dts/e500v2_power_isa.dtsi
b/arch/powerpc/dts/e500v2_power_isa.dtsi
new file mode 100644
index 000..010e8e5
--- /dev/null
+++ b/arch/powerpc/dts/e500v2_power_isa.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e500v2 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+ cpus {
+ power-isa-version = "2.03";
+ power-isa-b;// Base
+ power-isa-e;// Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-mmc; // Memory Coherence
+ power-isa-sp; // Signal Processing Engine
+ power-isa-sp.fd;// SPE.Embedded Float Scalar Double
+ power-isa-sp.fs;// SPE.Embedded Float Scalar Single
+ power-isa-sp.fv;// SPE.Embedded Float Vector
+ mmu-type = "power-embedded";
+ };
+};
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
new file mode 100644
index 000..e1a4f50
--- /dev/null
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1020-immr", "simple-bus";
+ bus-frequency = <0x0>;
+
+ mpic: pic@4 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x4 0x4>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ big-endian;
+ single-cpu-affinity;
+ last-interrupt-source = <255>;
+ };
+};
diff --git a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi
new file mode 100644
index 000..ee2b6f4
--- /dev/null
+++ b/arch/powerpc/dts/p1020.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
[U-Boot] [PATCHv2 14/14] powerpc: Enable device tree support for MPC8548CDS
Add device tree for MPC8548CDS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/mpc8548-post.dtsi | 27 +++
arch/powerpc/dts/mpc8548.dtsi | 27 +++
arch/powerpc/dts/mpc8548cds.dts | 23 +++
arch/powerpc/dts/mpc8548cds_36b.dts | 23 +++
configs/MPC8548CDS_36BIT_defconfig | 3 +++
configs/MPC8548CDS_defconfig| 3 +++
configs/MPC8548CDS_legacy_defconfig | 3 +++
8 files changed, 110 insertions(+)
create mode 100644 arch/powerpc/dts/mpc8548-post.dtsi
create mode 100644 arch/powerpc/dts/mpc8548.dtsi
create mode 100644 arch/powerpc/dts/mpc8548cds.dts
create mode 100644 arch/powerpc/dts/mpc8548cds_36b.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 0e234cc..021c85f 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
+dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
diff --git a/arch/powerpc/dts/mpc8548-post.dtsi
b/arch/powerpc/dts/mpc8548-post.dtsi
new file mode 100644
index 000..5533a4b
--- /dev/null
+++ b/arch/powerpc/dts/mpc8548-post.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8548-immr", "simple-bus";
+ bus-frequency = <0x0>;
+
+ mpic: pic@4 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x4 0x4>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ big-endian;
+ single-cpu-affinity;
+ last-interrupt-source = <255>;
+ };
+};
diff --git a/arch/powerpc/dts/mpc8548.dtsi b/arch/powerpc/dts/mpc8548.dtsi
new file mode 100644
index 000..b24567d
--- /dev/null
+++ b/arch/powerpc/dts/mpc8548.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8548@0 {
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts
new file mode 100644
index 000..cceea34
--- /dev/null
+++ b/arch/powerpc/dts/mpc8548cds.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Device Tree Source
+ *
+ * Copyright 2006 - 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+ model = "fsl,MPC8548CDS";
+ compatible = "fsl,MPC8548CDS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ soc: soc8548@e000 {
+ ranges = <0x0 0x0 0xe000 0x10>;
+ };
+};
+
+/include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts
b/arch/powerpc/dts/mpc8548cds_36b.dts
new file mode 100644
index 000..faff35c
--- /dev/null
+++ b/arch/powerpc/dts/mpc8548cds_36b.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS (36-bit address map) Device Tree Source
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+ model = "fsl,MPC8548CDS";
+ compatible = "fsl,MPC8548CDS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ soc: soc8548@fe000 {
+ ranges = <0x0 0xf 0xe000 0x10>;
+ };
+};
+
+/include/ "mpc8548-post.dtsi"
diff --git a/configs/MPC8548CDS_36BIT_defconfig
b/configs/MPC8548CDS_36BIT_defconfig
index 672dc78..f259f19 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -1,8 +1,11
[U-Boot] [PATCHv2 08/14] powerpc: Enable device tree support for P2041RDB
Add device tree for P1041RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/e500mc_power_isa.dtsi | 33 ++
arch/powerpc/dts/p2041.dtsi| 63 ++
arch/powerpc/dts/p2041rdb.dts | 18 ++
board/freescale/p2041rdb/README| 18 ++
configs/P2041RDB_NAND_defconfig| 3 ++
configs/P2041RDB_SDCARD_defconfig | 3 ++
configs/P2041RDB_SPIFLASH_defconfig| 3 ++
configs/P2041RDB_defconfig | 3 ++
9 files changed, 145 insertions(+)
create mode 100644 arch/powerpc/dts/e500mc_power_isa.dtsi
create mode 100644 arch/powerpc/dts/p2041.dtsi
create mode 100644 arch/powerpc/dts/p2041rdb.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index bee1e2d..3123249 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
+dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
diff --git a/arch/powerpc/dts/e500mc_power_isa.dtsi
b/arch/powerpc/dts/e500mc_power_isa.dtsi
new file mode 100644
index 000..e486ae5
--- /dev/null
+++ b/arch/powerpc/dts/e500mc_power_isa.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e500mc Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+ cpus {
+ power-isa-version = "2.06";
+ power-isa-b;// Base
+ power-isa-e;// Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-ds; // Decorated Storage
+ power-isa-e.ed; // Embedded.Enhanced Debug
+ power-isa-e.pd; // Embedded.External PID
+ power-isa-e.hv; // Embedded.Hypervisor
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-e.pc; // Embedded.Processor Control
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-exp; // External Proxy
+ power-isa-fp; // Floating Point
+ power-isa-fp.r; // Floating Point.Record
+ power-isa-mmc; // Memory Coherence
+ power-isa-scpm; // Store Conditional Page Mobility
+ power-isa-wt; // Wait
+ fsl,eref-deo; // Data Cache Extended Operations
+ mmu-type = "power-embedded";
+ };
+};
diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
new file mode 100644
index 000..9aa0422
--- /dev/null
+++ b/arch/powerpc/dts/p2041.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+ compatible = "fsl,P2041";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e500mc@0 {
+ device_type = "cpu";
+ reg = <0>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu1: PowerPC,e500mc@1 {
+ device_type = "cpu";
+ reg = <1>;
+ fsl,portid-mapping = <0x4000>;
+ };
+ cpu2: PowerPC,e500mc@2 {
+ device_type = "cpu";
+ reg = <2>;
+ fsl,portid-mapping = <0x2000>;
+ };
+ cpu3: PowerPC,e500mc@3 {
+ device_type = "cpu";
+ reg = <3>;
+ fsl,portid-mapping = <0x1000>;
+ };
+ };
+
+ soc: soc@ffe00 {
+ ranges = <0x 0xf 0xfe00 0x100>;
+ reg = <0xf 0xfe00 0 0x1000>;
+ #address-cells = <1>;
+ #si
[U-Boot] [PATCHv2 09/14] powerpc: Enable device tree support for P3041DS
Add device tree for P3041DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/p3041.dtsi| 63 ++
arch/powerpc/dts/p3041ds.dts | 18 +++
configs/P3041DS_NAND_defconfig | 3 ++
configs/P3041DS_SDCARD_defconfig | 3 ++
configs/P3041DS_SPIFLASH_defconfig | 3 ++
configs/P3041DS_defconfig | 3 ++
7 files changed, 94 insertions(+)
create mode 100644 arch/powerpc/dts/p3041.dtsi
create mode 100644 arch/powerpc/dts/p3041ds.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 3123249..fe2d4e4 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -4,6 +4,7 @@ dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb
p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
+dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
new file mode 100644
index 000..7d5c713
--- /dev/null
+++ b/arch/powerpc/dts/p3041.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P3041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2010 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+ compatible = "fsl,P3041";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e500mc@0 {
+ device_type = "cpu";
+ reg = <0>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu1: PowerPC,e500mc@1 {
+ device_type = "cpu";
+ reg = <1>;
+ fsl,portid-mapping = <0x4000>;
+ };
+ cpu2: PowerPC,e500mc@2 {
+ device_type = "cpu";
+ reg = <2>;
+ fsl,portid-mapping = <0x2000>;
+ };
+ cpu3: PowerPC,e500mc@3 {
+ device_type = "cpu";
+ reg = <3>;
+ fsl,portid-mapping = <0x1000>;
+ };
+ };
+
+ soc: soc@ffe00 {
+ ranges = <0x 0xf 0xfe00 0x100>;
+ reg = <0xf 0xfe00 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@4 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x4 0x4>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts
new file mode 100644
index 000..c30bf7a
--- /dev/null
+++ b/arch/powerpc/dts/p3041ds.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P3041DS Device Tree Source
+ *
+ * Copyright 2010 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p3041.dtsi"
+
+/ {
+ model = "fsl,P3041DS";
+ compatible = "fsl,P3041DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+};
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 81ce703..b315840 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -1,7 +1,10 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF4
CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P3041DS=y
+CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
+CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 7392948..50dee40 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -1,7 +1,10 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF4
CONFIG_MPC85xx=y
+CONFIG_MPC85XX_
[U-Boot] [PATCHv2 05/14] powerpc: Enable device tree support for T1042D4RDB
Add device tree for T1042D4RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/t1042d4rdb.dts | 17 ++
arch/powerpc/dts/t104x.dtsi | 62 +++
board/freescale/t104xrdb/README | 19 +++
configs/T1042D4RDB_NAND_defconfig | 2 ++
configs/T1042D4RDB_SDCARD_defconfig | 2 ++
configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++
configs/T1042D4RDB_defconfig | 3 ++
8 files changed, 108 insertions(+)
create mode 100644 arch/powerpc/dts/t1042d4rdb.dts
create mode 100644 arch/powerpc/dts/t104x.dtsi
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index b7acba5..f0d49aa 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
+dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts
new file mode 100644
index 000..16a8ed4
--- /dev/null
+++ b/arch/powerpc/dts/t1042d4rdb.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T1042D4RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t104x.dtsi"
+
+/ {
+ model = "fsl,T1042D4RDB";
+ compatible = "fsl,T1042D4RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+};
diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
new file mode 100644
index 000..ff0da93
--- /dev/null
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T104X Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ #cooling-cells = <2>;
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ #cooling-cells = <2>;
+ };
+ cpu2: PowerPC,e5500@2 {
+ device_type = "cpu";
+ reg = <2>;
+ #cooling-cells = <2>;
+ };
+ cpu3: PowerPC,e5500@3 {
+ device_type = "cpu";
+ reg = <3>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ soc: soc@ffe00 {
+ ranges = <0x 0xf 0xfe00 0x100>;
+ reg = <0xf 0xfe00 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@4 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x4 0x4>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+};
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
index 98b3f63..09cb98e 100644
--- a/board/freescale/t104xrdb/README
+++ b/board/freescale/t104xrdb/README
@@ -365,3 +365,22 @@ to
2. SPI does not support flush so remove flush from pbl, make changes in
tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
with 0x091380c0
+
+Device tree support and how to enable it for different configs
+--
+Device tree support is available for t1042d4rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if
required)
+2. CONFIG
[U-Boot] [PATCHv2 11/14] powerpc: Enable device tree support for P5040DS
Add device tree for P5040DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/p5040.dtsi| 62 ++
arch/powerpc/dts/p5040ds.dts | 18 +++
configs/P5040DS_NAND_defconfig | 3 ++
configs/P5040DS_SDCARD_defconfig | 3 ++
configs/P5040DS_SPIFLASH_defconfig | 3 ++
configs/P5040DS_defconfig | 3 ++
7 files changed, 93 insertions(+)
create mode 100644 arch/powerpc/dts/p5040.dtsi
create mode 100644 arch/powerpc/dts/p5040ds.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index ffd929c..0e234cc 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -6,6 +6,7 @@ dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb
p2020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
+dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
new file mode 100644
index 000..b6f6c5d
--- /dev/null
+++ b/arch/powerpc/dts/p5040.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P5040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ fsl,portid-mapping = <0x4000>;
+ };
+ cpu2: PowerPC,e5500@2 {
+ device_type = "cpu";
+ reg = <2>;
+ fsl,portid-mapping = <0x2000>;
+ };
+ cpu3: PowerPC,e5500@3 {
+ device_type = "cpu";
+ reg = <3>;
+ fsl,portid-mapping = <0x1000>;
+ };
+ };
+
+ soc: soc@ffe00 {
+ ranges = <0x 0xf 0xfe00 0x100>;
+ reg = <0xf 0xfe00 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@4 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x4 0x4>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts
new file mode 100644
index 000..723d31d
--- /dev/null
+++ b/arch/powerpc/dts/p5040ds.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P5040DS Device Tree Source
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p5040.dtsi"
+
+/ {
+ model = "fsl,P5040DS";
+ compatible = "fsl,P5040DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+};
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index b2c61d7..cbccb4c 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -1,7 +1,10 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF4
CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P5040DS=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
+CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index dbff8f7..cdefb2d 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -1,7 +1,10 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF4
CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P5040DS=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
[U-Boot] [PATCHv2 07/14] powerpc: Enable device tree support for P2020RDB
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile| 1 +
arch/powerpc/dts/p2020-post.dtsi | 27
arch/powerpc/dts/p2020.dtsi | 31
arch/powerpc/dts/p2020rdb-pc.dts | 23 +
arch/powerpc/dts/p2020rdb-pc_36b.dts | 23 +
board/freescale/p1_p2_rdb_pc/README | 2 +-
configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 ++
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 ++
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++
configs/P2020RDB-PC_36BIT_defconfig | 3 +++
configs/P2020RDB-PC_NAND_defconfig | 2 ++
configs/P2020RDB-PC_SDCARD_defconfig | 2 ++
configs/P2020RDB-PC_SPIFLASH_defconfig | 2 ++
configs/P2020RDB-PC_defconfig| 3 +++
14 files changed, 124 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/dts/p2020-post.dtsi
create mode 100644 arch/powerpc/dts/p2020.dtsi
create mode 100644 arch/powerpc/dts/p2020rdb-pc.dts
create mode 100644 arch/powerpc/dts/p2020rdb-pc_36b.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 3a806bd..bee1e2d 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
+dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
new file mode 100644
index 000..f20d1fa
--- /dev/null
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p2020-immr", "simple-bus";
+ bus-frequency = <0x0>;
+
+ mpic: pic@4 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x4 0x4>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ big-endian;
+ single-cpu-affinity;
+ last-interrupt-source = <255>;
+ };
+};
diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi
new file mode 100644
index 000..7c4c206
--- /dev/null
+++ b/arch/powerpc/dts/p2020.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,P2020@0 {
+ device_type = "cpu";
+ reg = <0>;
+ };
+ cpu1: PowerPC,P2020@1 {
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
new file mode 100644
index 000..4800b76
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020RDB-PC Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p2020.dtsi"
+
+/ {
+ model = "fsl,P2020RDB-PC";
+ compatible = "fsl,P2020RDB-PC";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ soc: soc@ffe0 {
+ ranges = <0x0 0x0 0xffe0 0x10>;
+ };
+};
+
+/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
b/arch/powerpc/dts/p2020rdb-pc_36b.dts
new file mode 100644
index 000..8323b90
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020RDB-PC (36-bit address map) Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+
[U-Boot] [PATCHv2 03/14] powerpc: Enable device tree support for T4240RDB
Add device tree for T4240RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/t4240.dtsi | 102 ++
arch/powerpc/dts/t4240rdb.dts | 17 +++
configs/T4240RDB_SDCARD_defconfig | 2 +
configs/T4240RDB_defconfig| 3 ++
5 files changed, 125 insertions(+)
create mode 100644 arch/powerpc/dts/t4240.dtsi
create mode 100644 arch/powerpc/dts/t4240rdb.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 388a4b2..9002393 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
+dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
new file mode 100644
index 000..4d8fc71
--- /dev/null
+++ b/arch/powerpc/dts/t4240.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T4240 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e6500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e6500@0 {
+ device_type = "cpu";
+ reg = <0 1>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu1: PowerPC,e6500@2 {
+ device_type = "cpu";
+ reg = <2 3>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu2: PowerPC,e6500@4 {
+ device_type = "cpu";
+ reg = <4 5>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu3: PowerPC,e6500@6 {
+ device_type = "cpu";
+ reg = <6 7>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu4: PowerPC,e6500@8 {
+ device_type = "cpu";
+ reg = <8 9>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu5: PowerPC,e6500@10 {
+ device_type = "cpu";
+ reg = <10 11>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu6: PowerPC,e6500@12 {
+ device_type = "cpu";
+ reg = <12 13>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu7: PowerPC,e6500@14 {
+ device_type = "cpu";
+ reg = <14 15>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu8: PowerPC,e6500@16 {
+ device_type = "cpu";
+ reg = <16 17>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu9: PowerPC,e6500@18 {
+ device_type = "cpu";
+ reg = <18 19>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu10: PowerPC,e6500@20 {
+ device_type = "cpu";
+ reg = <20 21>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu11: PowerPC,e6500@22 {
+ device_type = "cpu";
+ reg = <22 23>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ };
+
+ soc: soc@ffe00 {
+ ranges = <0x 0xf 0xfe00 0x100>;
+ reg = <0xf 0xfe00 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@4 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x4 0x4>;
+ compatible = "fsl,mpic";
+ device_type = "op
[U-Boot] [PATCHv2 10/14] powerpc: Enable device tree support for P4080DS
Add device tree for P4080DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/p4080.dtsi| 83 ++
arch/powerpc/dts/p4080ds.dts | 18 +
configs/P4080DS_SDCARD_defconfig | 3 ++
configs/P4080DS_SPIFLASH_defconfig | 3 ++
configs/P4080DS_defconfig | 3 ++
6 files changed, 111 insertions(+)
create mode 100644 arch/powerpc/dts/p4080.dtsi
create mode 100644 arch/powerpc/dts/p4080ds.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index fe2d4e4..ffd929c 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -5,6 +5,7 @@ dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
+dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
new file mode 100644
index 000..7c8dbae
--- /dev/null
+++ b/arch/powerpc/dts/p4080.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+ compatible = "fsl,P4080";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e500mc@0 {
+ device_type = "cpu";
+ reg = <0>;
+ fsl,portid-mapping = <0x8000>;
+ };
+ cpu1: PowerPC,e500mc@1 {
+ device_type = "cpu";
+ reg = <1>;
+ fsl,portid-mapping = <0x4000>;
+ };
+ cpu2: PowerPC,e500mc@2 {
+ device_type = "cpu";
+ reg = <2>;
+ fsl,portid-mapping = <0x2000>;
+ };
+ cpu3: PowerPC,e500mc@3 {
+ device_type = "cpu";
+ reg = <3>;
+ fsl,portid-mapping = <0x1000>;
+ };
+ cpu4: PowerPC,e500mc@4 {
+ device_type = "cpu";
+ reg = <4>;
+ fsl,portid-mapping = <0x0800>;
+ };
+ cpu5: PowerPC,e500mc@5 {
+ device_type = "cpu";
+ reg = <5>;
+ fsl,portid-mapping = <0x0400>;
+ };
+ cpu6: PowerPC,e500mc@6 {
+ device_type = "cpu";
+ reg = <6>;
+ fsl,portid-mapping = <0x0200>;
+ };
+ cpu7: PowerPC,e500mc@7 {
+ device_type = "cpu";
+ reg = <7>;
+ fsl,portid-mapping = <0x0100>;
+ };
+ };
+
+ soc: soc@ffe00 {
+ ranges = <0x 0xf 0xfe00 0x100>;
+ reg = <0xf 0xfe00 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@4 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x4 0x4>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts
new file mode 100644
index 000..15a0f66
--- /dev/null
+++ b/arch/powerpc/dts/p4080ds.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P4080DS Device Tree Source
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p4080.dtsi"
+
+/ {
+ model = "fsl,P4080DS";
+ compatible = "fsl,P4080DS";
+ #address-cells = <2>;
+
[U-Boot] [PATCHv2 04/14] powerpc: Enable device tree support for T1024RDB
Add device tree for T1024RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/e5500_power_isa.dtsi | 34 +++
arch/powerpc/dts/t1024rdb.dts | 17
arch/powerpc/dts/t102x.dtsi | 52 +++
board/freescale/t102xrdb/README | 19 +
configs/T1024RDB_NAND_defconfig | 2 ++
configs/T1024RDB_SDCARD_defconfig | 2 ++
configs/T1024RDB_SPIFLASH_defconfig | 2 ++
configs/T1024RDB_defconfig| 3 ++
9 files changed, 132 insertions(+)
create mode 100644 arch/powerpc/dts/e5500_power_isa.dtsi
create mode 100644 arch/powerpc/dts/t1024rdb.dts
create mode 100644 arch/powerpc/dts/t102x.dtsi
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 9002393..b7acba5 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
+dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
diff --git a/arch/powerpc/dts/e5500_power_isa.dtsi
b/arch/powerpc/dts/e5500_power_isa.dtsi
new file mode 100644
index 000..0a0943b
--- /dev/null
+++ b/arch/powerpc/dts/e5500_power_isa.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e5500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+ cpus {
+ power-isa-version = "2.06";
+ power-isa-b;// Base
+ power-isa-e;// Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-ds; // Decorated Storage
+ power-isa-e.ed; // Embedded.Enhanced Debug
+ power-isa-e.pd; // Embedded.External PID
+ power-isa-e.hv; // Embedded.Hypervisor
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-e.pc; // Embedded.Processor Control
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-exp; // External Proxy
+ power-isa-fp; // Floating Point
+ power-isa-fp.r; // Floating Point.Record
+ power-isa-mmc; // Memory Coherence
+ power-isa-scpm; // Store Conditional Page Mobility
+ power-isa-wt; // Wait
+ power-isa-64; // 64-bit
+ fsl,eref-deo; // Data Cache Extended Operations
+ mmu-type = "power-embedded";
+ };
+};
diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts
new file mode 100644
index 000..19a6652
--- /dev/null
+++ b/arch/powerpc/dts/t1024rdb.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T1024RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t102x.dtsi"
+
+/ {
+ model = "fsl,T1024RDB";
+ compatible = "fsl,T1024RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+};
diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi
new file mode 100644
index 000..2393e31
--- /dev/null
+++ b/arch/powerpc/dts/t102x.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T102X Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ #cooling-cells = <2>;
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ soc: soc@ffe00 {
+ ranges = <0x 0xf 0xfe00 0x100>;
+ reg = <0xf 0xfe00 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ de
[U-Boot] [PATCHv2 02/14] powerpc: Enable device tree support for T2080RDB
Add device tree for T2080RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/t2080rdb.dts | 17 +
board/freescale/t208xrdb/README | 19 +++
configs/T2080RDB_NAND_defconfig | 2 ++
configs/T2080RDB_SDCARD_defconfig | 2 ++
configs/T2080RDB_SPIFLASH_defconfig | 2 ++
configs/T2080RDB_defconfig | 3 +++
7 files changed, 46 insertions(+)
create mode 100644 arch/powerpc/dts/t2080rdb.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 6a28f80..388a4b2 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
+dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts
new file mode 100644
index 000..49c1765
--- /dev/null
+++ b/arch/powerpc/dts/t2080rdb.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T2080RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t2080.dtsi"
+
+/ {
+ model = "fsl,T2080RDB";
+ compatible = "fsl,T2080RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <>;
+};
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
index 42b2b92..9e4b28f 100644
--- a/board/freescale/t208xrdb/README
+++ b/board/freescale/t208xrdb/README
@@ -262,3 +262,22 @@ How to update the ucode of Freescale FMAN
For more details, please refer to T2080PCIe-RDB User Guide and access
website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+
+Device tree support and how to enable it for different configs
+--
+Device tree support is available for t2080rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if
required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+ CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 1bb90f3..7eb7058 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -10,10 +10,12 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_CONTROL=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/T2080RDB_SDCARD_defconfig
b/configs/T2080RDB_SDCARD_defconfig
index 1a7070c..9ea6698 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -11,6 +11,8 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
diff --git a/configs/T2080RDB_SPIFLASH_defconfig
b/configs/T2080RDB_SPIFLASH_defconfig
index ceb0230..988897b 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -13,6 +13,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index e782ba0..3f7e282 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -2,9 +2,11 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF4
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_CONTROL=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
@@ -26,6 +28,7 @@ CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe800.nor,nand0=fff80.flash,spi0=spife11.1"
CONFIG_MTDPARTS_DEFAULT=&quo
[U-Boot] [PATCHv2 01/14] powerpc: mpc85xx: Add device tree support option for PBL boot image
The current Makefile always use u-boot.bin to generate PBL boot image (u-boot.pbl), this patch changes it to use u-boot-with-dtb.bin to support device tree when CONFIG_OF_SEPARATE is enabled. Signed-off-by: Hou Zhiqiang --- V2: - New patch. Makefile | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 059978b..a70a0d0 100644 --- a/Makefile +++ b/Makefile @@ -1247,8 +1247,14 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage +ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) +UBOOT_BIN := u-boot-with-dtb.bin +else +UBOOT_BIN := u-boot.bin +endif + u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \ - $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE + $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,$(UBOOT_BIN)) FORCE $(call if_changed,mkimage) $(BOARD_SIZE_CHECK) -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv2 00/14] powerpc: Enable device tree support
This patch is to enable device tree support for the Freescale PowerPC platforms below. Hou Zhiqiang (14): powerpc: mpc85xx: Add device tree support option for PBL boot image powerpc: Enable device tree support for T2080RDB powerpc: Enable device tree support for T4240RDB powerpc: Enable device tree support for T1024RDB powerpc: Enable device tree support for T1042D4RDB powerpc: Enable device tree support for P1020RDB powerpc: Enable device tree support for P2020RDB powerpc: Enable device tree support for P2041RDB powerpc: Enable device tree support for P3041DS powerpc: Enable device tree support for P4080DS powerpc: Enable device tree support for P5040DS powerpc: dts: add default definition of CONFIG_RESET_VECTOR_ADDRESS powerpc: mpc8548cds: extend the reserved length for monitor powerpc: Enable device tree support for MPC8548CDS Makefile | 8 ++- arch/powerpc/dts/Makefile| 12 arch/powerpc/dts/e500mc_power_isa.dtsi | 33 + arch/powerpc/dts/e500v2_power_isa.dtsi | 26 +++ arch/powerpc/dts/e5500_power_isa.dtsi| 34 + arch/powerpc/dts/mpc8548-post.dtsi | 27 +++ arch/powerpc/dts/mpc8548.dtsi| 27 +++ arch/powerpc/dts/mpc8548cds.dts | 23 ++ arch/powerpc/dts/mpc8548cds_36b.dts | 23 ++ arch/powerpc/dts/p1020-post.dtsi | 27 +++ arch/powerpc/dts/p1020.dtsi | 31 arch/powerpc/dts/p1020rdb-pc.dts | 23 ++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 23 ++ arch/powerpc/dts/p1020rdb-pd.dts | 23 ++ arch/powerpc/dts/p2020-post.dtsi | 27 +++ arch/powerpc/dts/p2020.dtsi | 31 arch/powerpc/dts/p2020rdb-pc.dts | 23 ++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 23 ++ arch/powerpc/dts/p2041.dtsi | 63 + arch/powerpc/dts/p2041rdb.dts| 18 + arch/powerpc/dts/p3041.dtsi | 63 + arch/powerpc/dts/p3041ds.dts | 18 + arch/powerpc/dts/p4080.dtsi | 83 ++ arch/powerpc/dts/p4080ds.dts | 18 + arch/powerpc/dts/p5040.dtsi | 62 arch/powerpc/dts/p5040ds.dts | 18 + arch/powerpc/dts/t1024rdb.dts| 17 + arch/powerpc/dts/t102x.dtsi | 52 ++ arch/powerpc/dts/t1042d4rdb.dts | 17 + arch/powerpc/dts/t104x.dtsi | 62 arch/powerpc/dts/t2080rdb.dts| 17 + arch/powerpc/dts/t4240.dtsi | 102 +++ arch/powerpc/dts/t4240rdb.dts| 17 + arch/powerpc/dts/u-boot.dtsi | 3 + board/freescale/p1_p2_rdb_pc/README | 19 + board/freescale/p2041rdb/README | 18 + board/freescale/t102xrdb/README | 19 + board/freescale/t104xrdb/README | 19 + board/freescale/t208xrdb/README | 19 + configs/MPC8548CDS_36BIT_defconfig | 3 + configs/MPC8548CDS_defconfig | 3 + configs/MPC8548CDS_legacy_defconfig | 3 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 + configs/P1020RDB-PC_36BIT_defconfig | 3 + configs/P1020RDB-PC_NAND_defconfig | 2 + configs/P1020RDB-PC_SDCARD_defconfig | 2 + configs/P1020RDB-PC_SPIFLASH_defconfig | 2 + configs/P1020RDB-PC_defconfig| 3 + configs/P1020RDB-PD_NAND_defconfig | 2 + configs/P1020RDB-PD_SDCARD_defconfig | 2 + configs/P1020RDB-PD_SPIFLASH_defconfig | 2 + configs/P1020RDB-PD_defconfig| 3 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 + configs/P2020RDB-PC_36BIT_defconfig | 3 + configs/P2020RDB-PC_NAND_defconfig | 2 + configs/P2020RDB-PC_SDCARD_defconfig | 2 + configs/P2020RDB-PC_SPIFLASH_defconfig | 2 + configs/P2020RDB-PC_defconfig| 3 + configs/P2041RDB_NAND_defconfig | 3 + configs/P2041RDB_SDCARD_defconfig| 3 + configs/P2041RDB_SPIFLASH_defconfig | 3 + configs/P2041RDB_defconfig | 3 + configs/P3041DS_NAND_defconfig | 3 + configs/P3041DS_SDCARD_defconfig | 3 + configs/P3041DS_SPIFLASH_defconfig | 3 + configs/P3041DS_defconfig| 3 + configs/P4080DS_SDCARD_defconfig | 3 + configs
[U-Boot] [PATCH] dm: pci: Change to config device according to Header Type
The configuration space layouts of normal device, bridge and
CardBus bridge are distinct, and it is indicated by Header
Type instead of Class Code. So change it to config device
according to Header Type.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pci_auto.c | 60 +++---
1 file changed, 32 insertions(+), 28 deletions(-)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 1a3bf70..06621d5 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -311,6 +311,7 @@ int dm_pciauto_config_device(struct udevice *dev)
struct pci_region *pci_io;
unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
unsigned short class;
+ u8 header_type;
bool enum_only = false;
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
@@ -325,9 +326,33 @@ int dm_pciauto_config_device(struct udevice *dev)
pci_io = ctlr_hose->pci_io;
dm_pci_read_config16(dev, PCI_CLASS_DEVICE, );
+ dm_pci_read_config8(dev, PCI_HEADER_TYPE, _type);
+
+ switch (header_type & 0x7f) {
+ case PCI_HEADER_TYPE_BRIDGE:
+ if (class == PCI_CLASS_BRIDGE_OTHER) {
+#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
+ debug("PCI Autoconfig: Skipping bridge device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+ break;
+#endif
+#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
+ !defined(CONFIG_TARGET_CADDY2)
+ /*
+* The host/PCI bridge 1 seems broken in 8349 - it
+* presents itself as 'PCI_CLASS_BRIDGE_OTHER' and
+* appears as an _agent_ device claiming resources
+* io/mem/irq.. we only allow for the PIMMR window
+* to be allocated (BAR0 - 1MB size)
+*/
+ debug("PCI Autoconfig: Broken bridge found, only
minimal config\n");
+ dm_pciauto_setup_device(dev, 0, hose->pci_mem,
+ hose->pci_prefetch,
+ hose->pci_io, enum_only);
+ break;
+#endif
+ }
- switch (class) {
- case PCI_CLASS_BRIDGE_PCI:
debug("PCI Autoconfig: Found P2P bridge, device %d\n",
PCI_DEV(dm_pci_get_bdf(dev)));
@@ -340,7 +365,7 @@ int dm_pciauto_config_device(struct udevice *dev)
sub_bus = (unsigned int)n;
break;
- case PCI_CLASS_BRIDGE_CARDBUS:
+ case PCI_HEADER_TYPE_CARDBUS:
/*
* just do a minimal setup of the bridge,
* let the OS take care of the rest
@@ -353,35 +378,14 @@ int dm_pciauto_config_device(struct udevice *dev)
break;
-#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
- case PCI_CLASS_BRIDGE_OTHER:
- debug("PCI Autoconfig: Skipping bridge device %d\n",
- PCI_DEV(dm_pci_get_bdf(dev)));
- break;
-#endif
-#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
- !defined(CONFIG_TARGET_CADDY2)
- case PCI_CLASS_BRIDGE_OTHER:
- /*
-* The host/PCI bridge 1 seems broken in 8349 - it presents
-* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
-* device claiming resources io/mem/irq.. we only allow for
-* the PIMMR window to be allocated (BAR0 - 1MB size)
-*/
- debug("PCI Autoconfig: Broken bridge found, only minimal
config\n");
- dm_pciauto_setup_device(dev, 0, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io,
+ case PCI_HEADER_TYPE_NORMAL:
+ dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
enum_only);
break;
-#endif
-
- case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
- debug("PCI AutoConfig: Found PowerPC device\n");
- /* fall through */
default:
- dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
- enum_only);
+ printf("Unknown header type %02x, ignoring device\n",
+ header_type);
break;
}
--
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[U-Boot] [PATCH 31/47] configs: P2041RDB: Enable PCIe driver
Enable the DM PCIe driver in P2041RDB defconfig. Signed-off-by: Hou Zhiqiang --- configs/P2041RDB_NAND_defconfig | 4 configs/P2041RDB_SDCARD_defconfig | 4 configs/P2041RDB_SPIFLASH_defconfig | 4 configs/P2041RDB_defconfig | 4 4 files changed, 16 insertions(+) diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 73baf49..43434aa 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index d75f8b1..8d0efa4 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 925f0cd..eadb35b 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 1923b7a..8208907 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 40/47] P5040: dts: Added PCIe DT nodes
P5040 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/p5040.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
index b6f6c5d..8ab123d 100644
--- a/arch/powerpc/dts/p5040.dtsi
+++ b/arch/powerpc/dts/p5040.dtsi
@@ -59,4 +59,40 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe20 {
+ compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe20 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf800 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf801 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf802 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x4000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
--
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[U-Boot] [PATCH 43/47] powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected
Disable legacy PCI and PCIe fixup when CONFIG_DM_PCI is selected.
Signed-off-by: Hou Zhiqiang
---
board/freescale/common/cds_pci_ft.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cds_pci_ft.c
b/board/freescale/common/cds_pci_ft.c
index 3ff2fa4..fb2e5c7 100644
--- a/board/freescale/common/cds_pci_ft.c
+++ b/board/freescale/common/cds_pci_ft.c
@@ -9,6 +9,7 @@
#include "cadmus.h"
#if defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
static void cds_pci_fixup(void *blob)
{
int node;
@@ -61,11 +62,12 @@ static void cds_pci_fixup(void *blob)
}
}
}
+#endif
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
ft_pci_setup(blob, bd);
cds_pci_fixup(blob);
#endif
--
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[U-Boot] [PATCH 32/47] dm: pcie_fsl: Add P3041 PCIe support
Add compatible string for P3041 PCIe.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 61f08e7..a4e0cd1 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -629,6 +629,7 @@ static struct fsl_pcie_data t2080_data = {
static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)_p2_data },
{ .compatible = "fsl,pcie-p2041", .data = (ulong)_data },
+ { .compatible = "fsl,pcie-p3041", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t102x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t104x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)_data },
--
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[U-Boot] [PATCH 20/47] powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally
Compile the legacy PCIe initialization reoutines for P1020,
P1021, P1024, P1025 and P2020 RDB boards only when DM_PCI
is not enabled.
Signed-off-by: Hou Zhiqiang
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 4b151e8..5982a91 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -277,7 +277,7 @@ int checkboard(void)
return 0;
}
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -443,7 +443,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if !defined(CONFIG_DM_PCI)
FT_FSL_PCI_SETUP;
+#endif
#ifdef CONFIG_QE
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
--
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[U-Boot] [PATCH 24/47] configs: P1020RDB: Enable PCIe driver
Enable the DM PCIe driver in P1020RDB defconfig. Signed-off-by: Hou Zhiqiang --- configs/P1020RDB-PC_36BIT_NAND_defconfig | 4 configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 4 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 4 configs/P1020RDB-PC_36BIT_defconfig | 4 configs/P1020RDB-PC_NAND_defconfig | 4 configs/P1020RDB-PC_SDCARD_defconfig | 4 configs/P1020RDB-PC_SPIFLASH_defconfig | 4 configs/P1020RDB-PC_defconfig| 4 configs/P1020RDB-PD_NAND_defconfig | 4 configs/P1020RDB-PD_SDCARD_defconfig | 4 configs/P1020RDB-PD_SPIFLASH_defconfig | 4 configs/P1020RDB-PD_defconfig| 4 12 files changed, 48 insertions(+) diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 8fce49d..557fb49 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -55,6 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 80a4a0a..28ec227 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -52,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index ee565d4..84b88ae 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -53,6 +53,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 7d7c55f..fea964d 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -42,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index b729089..62199b9 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -54,6 +54,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 4622efd..f10e4fa 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -51,6 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 9cd897f..bacae37 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -52,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 595ff5f..0a6f974 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index b45122d..2c41054 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index c559879..7f0c7d4 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -55,6 +55,10
[U-Boot] [PATCH 07/47] powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang --- include/configs/T4240RDB.h | 35 +++ 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index a818f0c..8cdc17c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -63,7 +63,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -178,44 +177,48 @@ /* controller 1, direct to uli, tgtid 3, Base address 2 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x8000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xcull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 -#define CONFIG_SYS_PCIE1_IO_BUS0x #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc2000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 -#define CONFIG_SYS_PCIE2_IO_BUS0x #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc4000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 -#define CONFIG_SYS_PCIE3_IO_BUS0x #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc6000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x2000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS0x #define CONFIG_SYS_PCIE4_IO_PHYS 0xff803ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS0x +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS0x +#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS0x +#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS0x +#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 12/47] powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040
Remove the macro CONFIG_ARCH_T1040 from the T102xRDB.h and the PCIE4 related macros, as there are only 3 PCIe controllers on T102x SoCs. Signed-off-by: Hou Zhiqiang --- include/configs/T102xRDB.h | 24 1 file changed, 24 deletions(-) diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index cce65f5..3715e25 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -500,9 +500,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#ifdef CONFIG_ARCH_T1040 -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#endif #define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_PCI_INDIRECT_BRIDGE @@ -571,27 +568,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ #endif -/* controller 4, Base address 203000, to be removed */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc3000ull -#else -#define CONFIG_SYS_PCIE4_MEM_BUS 0xb000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb000 -#endif -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x1000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf803 -#define CONFIG_SYS_PCIE4_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff803ull -#else -#define CONFIG_SYS_PCIE4_IO_PHYS 0xf803 -#endif -#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ -#endif - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/47] dm: pcie_fsl: Add T4240 PCIe support
Add compatible string for T4240 PCIe.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index e13e5a6..961d8e3 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -616,6 +616,7 @@ static struct fsl_pcie_data t2080_data = {
static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-t2080", .data = (ulong)_data },
+ { .compatible = "fsl,pcie-t4240", .data = (ulong)_data },
{ }
};
--
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[U-Boot] [PATCH 15/47] powerpc: T104xRDB: Compile legacy PCIe routines conditionally
Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang
---
board/freescale/t104xrdb/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
index 9fd6659..6b666ba 100644
--- a/board/freescale/t104xrdb/pci.c
+++ b/board/freescale/t104xrdb/pci.c
@@ -11,6 +11,7 @@
#include
#include
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
+#endif
--
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[U-Boot] [PATCH 29/47] P2041: dts: Added PCIe DT nodes
P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/p2041.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
index 9aa0422..55f7adc 100644
--- a/arch/powerpc/dts/p2041.dtsi
+++ b/arch/powerpc/dts/p2041.dtsi
@@ -60,4 +60,40 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe20 {
+ compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe20 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf800 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf801 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf802 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x4000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
--
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[U-Boot] [PATCH 16/47] dm: pcie_fsl: Add T104x PCIe support
Add compatible string for T104x PCIe.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 25df84d..c4b4ace 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -616,6 +616,7 @@ static struct fsl_pcie_data t2080_data = {
static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-t102x", .data = (ulong)_data },
+ { .compatible = "fsl,pcie-t104x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t4240", .data = (ulong)_data },
{ }
--
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[U-Boot] [PATCH 39/47] dm: pcie_fsl: Add P5040 PCIe support
Add compatible string for P5040 PCIe.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index f61e39e..1411b1f 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -631,6 +631,7 @@ static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-p2041", .data = (ulong)_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)_data },
{ .compatible = "fsl,pcie-p4080", .data = (ulong)_data },
+ { .compatible = "fsl,pcie-p5040", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t102x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t104x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)_data },
--
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[U-Boot] [PATCH 19/47] configs: T1042D4RDB: Enable PCIe driver
Enable the DM PCIe driver in T1042D4RDB defconfig. Signed-off-by: Hou Zhiqiang --- configs/T1042D4RDB_NAND_defconfig | 4 configs/T1042D4RDB_SDCARD_defconfig | 4 configs/T1042D4RDB_SPIFLASH_defconfig | 4 configs/T1042D4RDB_defconfig | 4 4 files changed, 16 insertions(+) diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 2edd3b3..e51124b 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index f5a8613..fa9b3e3 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 945740a..fdec9a2 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 3be988c..86c0a7f 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 45/47] MPC8548: dts: Added PCIe DT node
MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/mpc8548-post.dtsi | 9 +
arch/powerpc/dts/mpc8548cds.dts | 6 ++
arch/powerpc/dts/mpc8548cds_36b.dts | 6 ++
3 files changed, 21 insertions(+)
diff --git a/arch/powerpc/dts/mpc8548-post.dtsi
b/arch/powerpc/dts/mpc8548-post.dtsi
index 5533a4b..2206f2d 100644
--- a/arch/powerpc/dts/mpc8548-post.dtsi
+++ b/arch/powerpc/dts/mpc8548-post.dtsi
@@ -25,3 +25,12 @@
last-interrupt-source = <255>;
};
};
+
+ {
+ compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts
index cceea34..3b927bd 100644
--- a/arch/powerpc/dts/mpc8548cds.dts
+++ b/arch/powerpc/dts/mpc8548cds.dts
@@ -18,6 +18,12 @@
soc: soc8548@e000 {
ranges = <0x0 0x0 0xe000 0x10>;
};
+
+ pcie: pcie@e000a000 {
+ reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0x0 0xe300 0x0
0x0010 /* downstream I/O */
+ 0x0200 0x0 0xa000 0x0 0xa000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
/include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts
b/arch/powerpc/dts/mpc8548cds_36b.dts
index faff35c..98d7c24 100644
--- a/arch/powerpc/dts/mpc8548cds_36b.dts
+++ b/arch/powerpc/dts/mpc8548cds_36b.dts
@@ -18,6 +18,12 @@
soc: soc8548@fe000 {
ranges = <0x0 0xf 0xe000 0x10>;
};
+
+ pcie: pcie@fe000a000 {
+ reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0xf 0xe300 0x0
0x0010 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
/include/ "mpc8548-post.dtsi"
--
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[U-Boot] [PATCH 47/47] configs: MPC8548CDS: Enable PCIe driver
Enable the DM PCIe driver in MPC8548CDS defconfig. Signed-off-by: Hou Zhiqiang --- configs/MPC8548CDS_36BIT_defconfig | 4 configs/MPC8548CDS_defconfig| 4 configs/MPC8548CDS_legacy_defconfig | 4 3 files changed, 12 insertions(+) diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index f259f19..102716b 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -26,6 +26,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 72239da..9cccb60 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index f2420c3..782f827 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang --- include/configs/P2041RDB.h | 55 +- 1 file changed, 15 insertions(+), 40 deletions(-) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b433308..ba670d7 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -37,7 +37,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_SYS_SRIO @@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* controller 1, direct to uli, tgtid 3, Base address 2 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x8000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xcull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x8000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 -#define CONFIG_SYS_PCIE1_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf800 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc2000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 -#define CONFIG_SYS_PCIE2_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf801 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc4000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 -#define CONFIG_SYS_PCIE3_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf802 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS10 @@ -489,7 +449,22 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS0x +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS0x +#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS0x +#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/p2020-post.dtsi | 30 ++
arch/powerpc/dts/p2020rdb-pc.dts | 17 +
arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +
3 files changed, 64 insertions(+)
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index f20d1fa..f696f35 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -25,3 +25,33 @@
last-interrupt-source = <255>;
};
};
+
+/* PCIe controller base address 0x8000 */
+ {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0x9000 */
+ {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+ {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 4800b76..08befd4 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -18,6 +18,23 @@
soc: soc@ffe0 {
ranges = <0x0 0x0 0xffe0 0x10>;
};
+
+ pci2: pcie@ffe08000 {
+ reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
+ status = "disabled";
+ };
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0x0 0xffc1 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xa000 0x0 0xa000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0x0 0xffc0 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0x8000 0x0 0x8000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 8323b90..04b2519 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -18,6 +18,23 @@
soc: soc@fffe0 {
ranges = <0x0 0xf 0xffe0 0x10>;
};
+
+ pci2: pcie@fffe08000 {
+ reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */
+ status = "disabled";
+ };
+
+ pci1: pcie@fffe09000 {
+ reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0xf 0xffc1 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xc000 0xc 0x2000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@fffe0a000 {
+ reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0xf 0xffc0 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0x8000 0xc 0x 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
/include/ "p2020-post.dtsi"
--
2.9.5
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[U-Boot] [PATCH 04/47] powerpc: T4RDB: Compile legacy PCIe routines conditionally
Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang
---
board/freescale/t4rdb/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
index 4100370..7d670e1 100644
--- a/board/freescale/t4rdb/pci.c
+++ b/board/freescale/t4rdb/pci.c
@@ -11,6 +11,7 @@
#include
#include
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
+#endif
--
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[U-Boot] [PATCH 21/47] dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs
Add compatible string for PCIe of P1020, P1021, P1024, P1025
and P2020 SoCs.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index c4b4ace..c8b8e3b 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -608,6 +608,12 @@ static const struct dm_pci_ops fsl_pcie_ops = {
.write_config = fsl_pcie_write_config,
};
+static struct fsl_pcie_data p1_p2_data = {
+ .block_offset = 0xa000,
+ .block_offset_mask = 0x,
+ .stride = 0x1000,
+};
+
static struct fsl_pcie_data t2080_data = {
.block_offset = 0x24,
.block_offset_mask = 0x3f,
@@ -615,6 +621,7 @@ static struct fsl_pcie_data t2080_data = {
};
static const struct udevice_id fsl_pcie_ids[] = {
+ { .compatible = "fsl,pcie-p1_p2", .data = (ulong)_p2_data },
{ .compatible = "fsl,pcie-t102x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t104x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)_data },
--
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[U-Boot] [PATCH 38/47] configs: P4080DS: Enable PCIe driver
Enable the DM PCIe driver in P4080DS defconfig. Signed-off-by: Hou Zhiqiang --- configs/P4080DS_SDCARD_defconfig | 4 configs/P4080DS_SPIFLASH_defconfig | 4 configs/P4080DS_defconfig | 4 3 files changed, 12 insertions(+) diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 0aaf09a..5e5b30c 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 3a91df2..29560f3 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index d89d69f..aa42a0b 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 44/47] dm: pcie_fsl: Add MPC8548 PCIe support
Add compatible string for MPC8548 PCIe.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 1411b1f..112f3b9 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -627,6 +627,7 @@ static struct fsl_pcie_data t2080_data = {
};
static const struct udevice_id fsl_pcie_ids[] = {
+ { .compatible = "fsl,pcie-mpc8548", .data = (ulong)_p2_data },
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)_p2_data },
{ .compatible = "fsl,pcie-p2041", .data = (ulong)_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)_data },
--
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[U-Boot] [PATCH 46/47] powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang --- include/configs/MPC8548CDS.h | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4252fbe..4809bbd 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -18,8 +18,6 @@ #define CONFIG_PCI1/* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #undef CONFIG_PCI2 -#define CONFIG_FSL_PCI_INIT1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -343,24 +341,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_IO_SIZE0x0010 /* 1M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc2000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xe300 -#define CONFIG_SYS_PCIE1_IO_BUS0x #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS0xfe300ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xe300 #endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0010 /* 1M */ #endif /* @@ -386,6 +378,20 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 +#define CONFIG_SYS_PCIE1_NAME "Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS0x +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0010 /* 1M */ +#endif + #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 41/47] configs: P5040DS: Enable PCIe driver
Enable the DM PCIe driver in P5040DS defconfig. Signed-off-by: Hou Zhiqiang --- configs/P5040DS_NAND_defconfig | 4 configs/P5040DS_SDCARD_defconfig | 4 configs/P5040DS_SPIFLASH_defconfig | 4 configs/P5040DS_defconfig | 4 4 files changed, 16 insertions(+) diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index cbccb4c..bab7561 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -42,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index cdefb2d..517708a 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index c636b16..cb019f2 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 6572ff1..31a8fca 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 36/47] dm: pcie_fsl: Add P4080 PCIe support
Add compatible string for P4080 PCIe.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index a4e0cd1..f61e39e 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -630,6 +630,7 @@ static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)_p2_data },
{ .compatible = "fsl,pcie-p2041", .data = (ulong)_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)_data },
+ { .compatible = "fsl,pcie-p4080", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t102x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t104x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)_data },
--
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[U-Boot] [PATCH 11/47] t102x: dts: Added PCIe DT nodes
T102x integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/t102x.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi
index 2393e31..c49fd21 100644
--- a/arch/powerpc/dts/t102x.dtsi
+++ b/arch/powerpc/dts/t102x.dtsi
@@ -49,4 +49,40 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe24 {
+ compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe24 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf800 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0
0x1000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe25 {
+ compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe25 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf801 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x1000 0x0
0x1000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe26 {
+ compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe26 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf802 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x1000>; /* non-prefetchable memory */
+ };
};
--
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[U-Boot] [PATCH 27/47] powerpc: p_corenet: Compile legacy PCIe routines conditionally
Compile the legacy PCIe initialization reoutines for P2041RDB,
P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is
not enabled.
Signed-off-by: Hou Zhiqiang
---
board/freescale/common/p_corenet/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/common/p_corenet/pci.c
b/board/freescale/common/p_corenet/pci.c
index a2df928..a6abe66 100644
--- a/board/freescale/common/p_corenet/pci.c
+++ b/board/freescale/common/p_corenet/pci.c
@@ -11,6 +11,7 @@
#include
#include
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
+#endif
--
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[U-Boot] [PATCH 35/47] configs: P3041DS: Enable PCIe driver
Enable the DM PCIe driver in P3041DS defconfig. Signed-off-by: Hou Zhiqiang --- configs/P3041DS_NAND_defconfig | 4 configs/P3041DS_SDCARD_defconfig | 4 configs/P3041DS_SPIFLASH_defconfig | 4 configs/P3041DS_defconfig | 4 4 files changed, 16 insertions(+) diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index b315840..87958db 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 50dee40..90a0efe 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 984ff5f..7682877 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 5728cbb..ce9289f 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 23/47] powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled for P1020, P1021, P1024, P1025 and P2020 RDB boards. Signed-off-by: Hou Zhiqiang --- include/configs/p1_p2_rdb_pc.h | 36 +++- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index b1367a9..d3fb3da 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -215,8 +215,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -580,44 +578,56 @@ */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc2000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa000 #endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc1 -#define CONFIG_SYS_PCIE2_IO_BUS0x #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc1ull #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc1 #endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x8000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xcull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x8000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc0 -#define CONFIG_SYS_PCIE1_IO_BUS0x #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc0ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc0 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc000 +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS0x +#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ + +#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS0x #define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver
Enable the DM PCIe driver in T2080RDB defconfig. Signed-off-by: Hou Zhiqiang --- configs/T2080RDB_NAND_defconfig | 4 configs/T2080RDB_SDCARD_defconfig | 4 configs/T2080RDB_SPIFLASH_defconfig | 4 configs/T2080RDB_defconfig | 4 4 files changed, 16 insertions(+) diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 7eb7058..30ec72b 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 9ea6698..22c2e05 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -56,6 +56,10 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 988897b..e70fa0d 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 3f7e282..b620349 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -45,6 +45,10 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang --- include/configs/corenet_ds.h | 63 +--- 1 file changed, 19 insertions(+), 44 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f974291..07844c1 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -362,68 +361,25 @@ /* controller 1, direct to uli, tgtid 3, Base address 2 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x8000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xcull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x8000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 -#define CONFIG_SYS_PCIE1_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf800 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc2000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 -#define CONFIG_SYS_PCIE2_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf801 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc4000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 -#define CONFIG_SYS_PCIE3_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf802 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc6000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x2000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS0x #define CONFIG_SYS_PCIE4_IO_PHYS 0xff803ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS10 @@ -505,7 +461,26 @@ #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS0x +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS0x +#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS0x +#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS0x +#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 42/47] powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally
Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang
---
board/freescale/mpc8548cds/mpc8548cds.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c
b/board/freescale/mpc8548cds/mpc8548cds.c
index 7d819d8..2799b5b 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -164,7 +164,7 @@ void lbc_sdram_init(void)
#endif /* enable SDRAM init */
}
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it.
*/
@@ -189,6 +189,7 @@ static struct pci_config_table
pci_mpc85xxcds_config_table[] = {
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -268,6 +269,7 @@ void pci_init_board(void)
fsl_pcie_init_board(first_free_busno);
}
+#endif
void configure_rgmii(void)
{
@@ -349,7 +351,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
-#if defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
void ft_pci_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
--
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[U-Boot] [PATCH 17/47] t104x: dts: Added PCIe DT nodes
T104x integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/t104x.dtsi | 48 +
1 file changed, 48 insertions(+)
diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
index ff0da93..5998967 100644
--- a/arch/powerpc/dts/t104x.dtsi
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -59,4 +59,52 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe24 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe24 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf800 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0
0x1000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe25 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe25 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf801 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x1000 0x0
0x1000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe26 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe26 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf802 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x1000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe27 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe27 0x0 0x1000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf803 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x3000 0x0
0x1000>; /* non-prefetchable memory */
+ };
};
--
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[U-Boot] [PATCH 33/47] P3041: dts: Added PCIe DT nodes
P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/p3041.dtsi | 48 +
1 file changed, 48 insertions(+)
diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
index 7d5c713..197896d 100644
--- a/arch/powerpc/dts/p3041.dtsi
+++ b/arch/powerpc/dts/p3041.dtsi
@@ -60,4 +60,52 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe20 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe20 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf800 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf801 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf802 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x4000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe203000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf803 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x6000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
--
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[U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang --- include/configs/T102xRDB.h | 54 +- 1 file changed, 15 insertions(+), 39 deletions(-) diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 3715e25..4fb1709 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 2 */ #ifdef CONFIG_PCIE1 #defineCONFIG_SYS_PCIE1_MEM_VIRT 0x8000 -#ifdef CONFIG_PHYS_64BIT -#defineCONFIG_SYS_PCIE1_MEM_BUS0xe000 #defineCONFIG_SYS_PCIE1_MEM_PHYS 0xcull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x8000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 -#define CONFIG_SYS_PCIE1_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf800 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x9000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc1000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x9000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x9000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 -#define CONFIG_SYS_PCIE2_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf801 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc2000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 -#define CONFIG_SYS_PCIE3_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf802 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS0x +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS0x +#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS0x #define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 28/47] dm: pcie_fsl: Add P2041 PCIe support
Add compatible string for P2041 PCIe.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index c8b8e3b..61f08e7 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -614,6 +614,12 @@ static struct fsl_pcie_data p1_p2_data = {
.stride = 0x1000,
};
+static struct fsl_pcie_data p2041_data = {
+ .block_offset = 0x20,
+ .block_offset_mask = 0x3f,
+ .stride = 0x1000,
+};
+
static struct fsl_pcie_data t2080_data = {
.block_offset = 0x24,
.block_offset_mask = 0x3f,
@@ -622,6 +628,7 @@ static struct fsl_pcie_data t2080_data = {
static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)_p2_data },
+ { .compatible = "fsl,pcie-p2041", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t102x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t104x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)_data },
--
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[U-Boot] [PATCH 26/47] configs: P2020RDB: Enable PCIe driver
Enable the DM PCIe driver in P2020RDB defconfig. Signed-off-by: Hou Zhiqiang --- configs/P2020RDB-PC_36BIT_NAND_defconfig | 4 configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 4 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 4 configs/P2020RDB-PC_36BIT_defconfig | 4 configs/P2020RDB-PC_NAND_defconfig | 4 configs/P2020RDB-PC_SDCARD_defconfig | 4 configs/P2020RDB-PC_SPIFLASH_defconfig | 4 configs/P2020RDB-PC_defconfig| 4 8 files changed, 32 insertions(+) diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index d8c04e2..a51a34c 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 7c45996..9c97b3d 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 5372d98..fee83e5 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 79f4f3c..bb5c6bd 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -47,6 +47,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 2f91691..610bd96 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index a5cee06..46d430c 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index a2f9d87..f3eb66e 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 4000459..b94c67e 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 09/47] powerpc: T102xRDB: Compile legacy PCIe routines conditionally
Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang
---
board/freescale/t102xrdb/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
index 161b8cb..adc128d 100644
--- a/board/freescale/t102xrdb/pci.c
+++ b/board/freescale/t102xrdb/pci.c
@@ -11,6 +11,7 @@
#include
#include
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
+#endif
--
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[U-Boot] [PATCH 18/47] powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang --- include/configs/T104xRDB.h | 38 -- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 470f60a..5d9dd10 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -151,13 +151,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -530,51 +528,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* controller 1, direct to uli, tgtid 3, Base address 2 */ #ifdef CONFIG_PCIE1 #defineCONFIG_SYS_PCIE1_MEM_VIRT 0x8000 -#defineCONFIG_SYS_PCIE1_MEM_BUS0xe000 #defineCONFIG_SYS_PCIE1_MEM_PHYS 0xcull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 -#define CONFIG_SYS_PCIE1_IO_BUS0x #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x9000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc1000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 -#define CONFIG_SYS_PCIE2_IO_BUS0x #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc2000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 -#define CONFIG_SYS_PCIE3_IO_BUS0x #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc3000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf803 -#define CONFIG_SYS_PCIE4_IO_BUS0x #define CONFIG_SYS_PCIE4_IO_PHYS 0xff803ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ #endif +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS0x +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS0x +#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS0x +#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS0x +#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 37/47] P4080: dts: Added PCIe DT nodes
P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/p4080.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
index 7c8dbae..ab76680 100644
--- a/arch/powerpc/dts/p4080.dtsi
+++ b/arch/powerpc/dts/p4080.dtsi
@@ -80,4 +80,40 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe20 {
+ compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe20 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf800 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf801 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf802 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x4000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
--
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[U-Boot] [PATCH 14/47] configs: T1024RDB: Enable PCIe driver
Enable the DM PCIe driver in T1024RDB defconfig. Signed-off-by: Hou Zhiqiang --- configs/T1024RDB_NAND_defconfig | 4 configs/T1024RDB_SDCARD_defconfig | 4 configs/T1024RDB_SPIFLASH_defconfig | 4 configs/T1024RDB_defconfig | 4 4 files changed, 16 insertions(+) diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 30acd0e..faea7d2 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 7569e4e..bce2fc3 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 470674b..55f80f8 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 146551d..f8b3227 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -48,6 +48,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 08/47] configs: T4240RDB: Enable PCIe driver
Enable the DM PCIe driver in T4240RDB defconfig. Signed-off-by: Hou Zhiqiang --- configs/T4240RDB_SDCARD_defconfig | 4 configs/T4240RDB_defconfig| 4 2 files changed, 8 insertions(+) diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index a70c237..cce4872 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -50,6 +50,10 @@ CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index d4ce176..bdadfa8 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -39,6 +39,10 @@ CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/47] t4240: dts: Added PCIe DT nodes
T4240 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/t4240.dtsi | 48 +
1 file changed, 48 insertions(+)
diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
index 4d8fc71..fc34974 100644
--- a/arch/powerpc/dts/t4240.dtsi
+++ b/arch/powerpc/dts/t4240.dtsi
@@ -99,4 +99,52 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe24 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe24 0x0 0x4000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf800 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe25 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe25 0x0 0x4000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf801 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe26 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe26 0x0 0x4000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf802 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x4000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe27 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe27 0x0 0x4000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x0100 0x0 0x 0xf 0xf803 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x6000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
--
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[U-Boot] [PATCH 10/47] dm: pcie_fsl: Add T102x PCIe support
Add compatible string for T102x PCIe.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 961d8e3..25df84d 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -615,6 +615,7 @@ static struct fsl_pcie_data t2080_data = {
};
static const struct udevice_id fsl_pcie_ids[] = {
+ { .compatible = "fsl,pcie-t102x", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)_data },
{ .compatible = "fsl,pcie-t4240", .data = (ulong)_data },
{ }
--
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[U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/dts/p1020-post.dtsi | 20
arch/powerpc/dts/p1020rdb-pc.dts | 12
arch/powerpc/dts/p1020rdb-pc_36b.dts | 12
arch/powerpc/dts/p1020rdb-pd.dts | 12
4 files changed, 56 insertions(+)
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index e1a4f50..1e5e678 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -25,3 +25,23 @@
last-interrupt-source = <255>;
};
};
+
+/* PCIe controller base address 0x9000 */
+ {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+ {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index fd68b8b..7ebaa61 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -18,6 +18,18 @@
soc: soc@ffe0 {
ranges = <0x0 0x0 0xffe0 0x10>;
};
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0x0 0xffc1 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xa000 0x0 0xa000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0x0 0xffc0 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0x8000 0x0 0x8000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts
b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index a23d031..c0e5ef4 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -18,6 +18,18 @@
soc: soc@fffe0 {
ranges = <0x0 0xf 0xffe0 0x10>;
};
+
+ pci1: pcie@fffe09000 {
+ reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0xf 0xffc1 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xc000 0xc 0x2000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@fffe0a000 {
+ reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0xf 0xffc0 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0x8000 0xc 0x 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 81f25a3..21174a0 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -18,6 +18,18 @@
soc: soc@ffe0 {
ranges = <0x0 0x0 0xffe0 0x10>;
};
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0x0 0xffc1 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0xa000 0x0 0xa000 0x0
0x2000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x0100 0x0 0x 0x0 0xffc0 0x0
0x0001 /* downstream I/O */
+ 0x0200 0x0 0x8000 0x0 0x8000 0x0
0x2000>; /* non-prefetchable memory */
+ };
};
/include/ "p1020-post.dtsi"
--
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[U-Boot] [PATCH 01/47] powerpc: T208xRDB: Compile legacy PCIe routines conditionally
Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang
---
board/freescale/t208xrdb/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c
index 161b8cb..adc128d 100644
--- a/board/freescale/t208xrdb/pci.c
+++ b/board/freescale/t208xrdb/pci.c
@@ -11,6 +11,7 @@
#include
#include
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
+#endif
--
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[U-Boot] [PATCH 02/47] powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang --- include/configs/T208xRDB.h | 36 +++- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 1a5a93e..b1ae050 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -439,49 +439,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 2 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x8000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xcull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 -#define CONFIG_SYS_PCIE1_IO_BUS0x #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc2000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 -#define CONFIG_SYS_PCIE2_IO_BUS0x #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc3000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 -#define CONFIG_SYS_PCIE3_IO_BUS0x #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc4000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x1000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS0x #define CONFIG_SYS_PCIE4_IO_PHYS 0xff803ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS0x +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS0x +#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS0x +#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x1000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS0x +#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 00/47] powerpc: Enable PCIe DM drvier for some platforms
Enable PCIe DM driver for some PowerPC platforms which has supported device tree. Depends on the following 2 series: http://patchwork.ozlabs.org/project/uboot/list/?series=120960 http://patchwork.ozlabs.org/project/uboot/list/?series=115008 Hou Zhiqiang (47): powerpc: T208xRDB: Compile legacy PCIe routines conditionally powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T2080RDB: Enable PCIe driver powerpc: T4RDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T4240 PCIe support t4240: dts: Added PCIe DT nodes powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T4240RDB: Enable PCIe driver powerpc: T102xRDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T102x PCIe support t102x: dts: Added PCIe DT nodes powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040 powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T1024RDB: Enable PCIe driver powerpc: T104xRDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T104x PCIe support t104x: dts: Added PCIe DT nodes powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T1042D4RDB: Enable PCIe driver powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs P1020: dts: Added PCIe DT nodes powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled configs: P1020RDB: Enable PCIe driver P2020: dts: Added PCIe DT nodes configs: P2020RDB: Enable PCIe driver powerpc: p_corenet: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add P2041 PCIe support P2041: dts: Added PCIe DT nodes powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled configs: P2041RDB: Enable PCIe driver dm: pcie_fsl: Add P3041 PCIe support P3041: dts: Added PCIe DT nodes powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled configs: P3041DS: Enable PCIe driver dm: pcie_fsl: Add P4080 PCIe support P4080: dts: Added PCIe DT nodes configs: P4080DS: Enable PCIe driver dm: pcie_fsl: Add P5040 PCIe support P5040: dts: Added PCIe DT nodes configs: P5040DS: Enable PCIe driver powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected dm: pcie_fsl: Add MPC8548 PCIe support MPC8548: dts: Added PCIe DT node powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled configs: MPC8548CDS: Enable PCIe driver arch/powerpc/dts/mpc8548-post.dtsi | 9 arch/powerpc/dts/mpc8548cds.dts | 6 +++ arch/powerpc/dts/mpc8548cds_36b.dts | 6 +++ arch/powerpc/dts/p1020-post.dtsi | 20 +++ arch/powerpc/dts/p1020rdb-pc.dts | 12 + arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 + arch/powerpc/dts/p1020rdb-pd.dts | 12 + arch/powerpc/dts/p2020-post.dtsi | 30 +++ arch/powerpc/dts/p2020rdb-pc.dts | 17 ++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 ++ arch/powerpc/dts/p2041.dtsi | 36 + arch/powerpc/dts/p3041.dtsi | 48 + arch/powerpc/dts/p4080.dtsi | 36 + arch/powerpc/dts/p5040.dtsi | 36 + arch/powerpc/dts/t102x.dtsi | 36 + arch/powerpc/dts/t104x.dtsi | 48 + arch/powerpc/dts/t4240.dtsi | 48 + board/freescale/common/cds_pci_ft.c | 4 +- board/freescale/common/p_corenet/pci.c | 2 + board/freescale/mpc8548cds/mpc8548cds.c | 6 ++- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 +- board/freescale/t102xrdb/pci.c | 2 + board/freescale/t104xrdb/pci.c | 2 + board/freescale/t208xrdb/pci.c | 2 + board/freescale/t4rdb/pci.c | 2 + configs/MPC8548CDS_36BIT_defconfig | 4 ++ configs/MPC8548CDS_defconfig | 4 ++ configs/MPC8548CDS_legacy_defconfig | 4 ++ configs/P1020RDB-PC_36BIT_NAND_defconfig | 4 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 4 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++ configs/P1020RDB-PC_36BIT_defconfig | 4 ++ configs/P1020RDB-PC_NAND_defconfig | 4 ++ configs/P1020RDB-PC_SDCARD_defconfig | 4 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 4 ++ configs/P1020RDB-PC_defconfig| 4 ++ configs/P1020RDB-PD_NAND_defconfig | 4 ++ configs/P1020RDB-PD_SDCARD_defconfig | 4 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 4 ++ configs/P1020RDB-PD_defconfig| 4 ++ configs/P2020RDB-PC_36BIT_NAND_defconfig | 4 ++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 4 ++ configs/P2020RDB
[U-Boot] [PATCH 3/3] dm: pcie_fsl: Fix the calculation of controller index
The PCIe controller register address in CCSR is different
on various platforms, the current code erroneously use
the hardcoded address (0xffe24) and stride (0x1)
to calculate the controller's index.
Fix it by adding the related info to the driver data
structure.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 14 --
drivers/pci/pcie_fsl.h | 7 +++
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 7a7da1f..e13e5a6 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -580,6 +580,7 @@ static int fsl_pcie_probe(struct udevice *dev)
static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
{
struct fsl_pcie *pcie = dev_get_priv(dev);
+ struct fsl_pcie_data *info;
int ret;
pcie->regs = dev_remap_addr(dev);
@@ -594,7 +595,10 @@ static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
return ret;
}
- pcie->idx = (dev_read_addr(dev) - 0xffe24) / 0x1;
+ info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
+ pcie->info = info;
+ pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
+ info->block_offset) / info->stride;
return 0;
}
@@ -604,8 +608,14 @@ static const struct dm_pci_ops fsl_pcie_ops = {
.write_config = fsl_pcie_write_config,
};
+static struct fsl_pcie_data t2080_data = {
+ .block_offset = 0x24,
+ .block_offset_mask = 0x3f,
+ .stride = 0x1,
+};
+
static const struct udevice_id fsl_pcie_ids[] = {
- { .compatible = "fsl,pcie-t2080" },
+ { .compatible = "fsl,pcie-t2080", .data = (ulong)_data },
{ }
};
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index a872921..8335c62 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -50,6 +50,12 @@
#define P4080_SERDES_ADDR 0
#endif
+struct fsl_pcie_data {
+ u32 block_offset; /* Offset from CCSR of 1st controller */
+ u32 block_offset_mask; /* Mask out the CCSR base */
+ u32 stride; /* Offset stride between controllers */
+};
+
struct fsl_pcie {
int idx;
struct udevice *bus;
@@ -59,6 +65,7 @@ struct fsl_pcie {
bool mode; /* RC mode flag */
bool enabled; /* Enable status */
struct list_head list;
+ struct fsl_pcie_data *info;
};
extern struct list_head fsl_pcie_list;
--
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[U-Boot] [PATCH 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
In the workaround of P4080 erratum A003, it uses the macro
CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
register address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is
defined as following:
#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
This is valid on P4080, but on non-corenet platforms, such
as MPC8548, there is not definition of
CONFIG_SYS_FSL_CORENET_SERDES_OFFSET, then on these platforms
the following build error will come up:
drivers/pci/pcie_fsl.c: In function 'fsl_pcie_init_port':
./arch/powerpc/include/asm/immap_85xx.h:3000:21: error:
'CONFIG_SYS_FSL_CORENET_SERDES_OFFSET' undeclared (first use
in this function); did you mean 'CONFIG_SYS_FSL_CORENET_SERDES_ADDR'?
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
^~~~
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 2 +-
drivers/pci/pcie_fsl.h | 6 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index bfb207e..999e9c9 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -445,7 +445,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
!fsl_pcie_link_up(pcie)) {
serdes_corenet_t *srds_regs;
- srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ srds_regs = (void *)P4080_SERDES_ADDR;
val_32 = in_be32(_regs->srdspccr0);
if ((val_32 >> 28) == 3) {
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index ce2b1af..e09099b 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -41,6 +41,12 @@
#define LTSSM_L0_REV3 0x11
#define LTSSM_L0 0x16
+#ifdef ARCH_P4080
+#define P4080_SERDES_ADDR CONFIG_SYS_FSL_CORENET_SERDES_ADDR
+#else
+#define P4080_SERDES_ADDR 0
+#endif
+
struct fsl_pcie {
int idx;
struct udevice *bus;
--
2.9.5
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[U-Boot] [PATCH 2/3] dm: pcie_fsl: Fix the Class Code fixup function
The Class Code fixup method was changed from PCIe block
revision 3.0, the current fixup is only valid for the
revision 3.0 and the later ones.
This patch is to add the Class Code fixup for the block
revision < 3.0.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 17 +
drivers/pci/pcie_fsl.h | 3 +++
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 999e9c9..7a7da1f 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -503,12 +503,21 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
ccsr_fsl_pci_t *regs = pcie->regs;
u32 val;
- setbits_be32(>dbi_ro_wr_en, 0x01);
- fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, );
+ if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+ setbits_be32(>dbi_ro_wr_en, 0x01);
+ fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, );
+ val &= 0xff;
+ val |= PCI_CLASS_BRIDGE_PCI << 16;
+ fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
+ clrbits_be32(>dbi_ro_wr_en, 0x01);
+
+ return 0;
+ }
+
+ fsl_pcie_hose_read_config_dword(pcie, CSR_CLASSCODE, );
val &= 0xff;
val |= PCI_CLASS_BRIDGE_PCI << 16;
- fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
- clrbits_be32(>dbi_ro_wr_en, 0x01);
+ fsl_pcie_hose_write_config_dword(pcie, CSR_CLASSCODE, val);
return 0;
}
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index e09099b..a872921 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -10,6 +10,9 @@
#ifndef _PCIE_FSL_H_
#define _PCIE_FSL_H_
+/* GPEX CSR */
+#define CSR_CLASSCODE 0x474
+
#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
#define FSL_PCIE_CAP_ID0x70
#else
--
2.9.5
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[U-Boot] [PATCH 0/3] dm: pcie_fsl: Fix some issues
The current driver is not working on some PowerPC T-series, P-series and MPC85xx platforms due to the difference in PCIe IP revisions and the various integration on different platforms. This patch set fixes these issues. Hou Zhiqiang (3): dm: pcie_fsl: Fix workaround of P4080 erratum A003 dm: pcie_fsl: Fix the Class Code fixup function dm: pcie_fsl: Fix the calculation of controller index drivers/pci/pcie_fsl.c | 33 ++--- drivers/pci/pcie_fsl.h | 16 2 files changed, 42 insertions(+), 7 deletions(-) -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 2/2] armv8: fsl-layerscape: Make DDR non secure in MMU tables
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: 2015年12月3日 0:00
> To: Hou Zhiqiang-B48286; U-Boot Mailing List
> Cc: Pan Lijun-B44306; Hu Mingkai-B21284; Sharma Bhupesh-B45370; Gong
> Qianyu-B52263; Tom Rini; Li Yang-Leo-R58472; Albert Aribaud; Kushwaha
> Prabhakar-B32579; Wang Huan-B18965
> Subject: Re: [PATCH v6 2/2] armv8: fsl-layerscape: Make DDR non secure in
> MMU tables
>
>
>
> On 12/01/2015 10:38 PM, Hou Zhiqiang-B48286 wrote:
>
>
>
> >>/* Invalidate all table entries */
> >>memset(level0_table, 0, PGTABLE_SIZE); @@ -269,6 +344,22 @@ static
> >> inline void final_mmu_setup(void)
> >> _mmu_table[i]);
> >>}
> >>}
> >> + /* Set the secure memory to secure in MMU */ #ifdef
> >> +CONFIG_SYS_MEM_RESERVE_SECURE
> >> + if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { #ifdef
> >> +CONFIG_FSL_LSCH3
> >> + level2_table_secure = level2_table1 + 512; #elif
> >> +defined(CONFIG_FSL_LSCH2)
> >> + level2_table_secure = level2_table2 + 512; #endif
> >> + /* update tlb pointer */
> >> + gd->arch.tlb_addr = gd->secure_ram & ~0x3;
> >
> > The memory reserved for mmu table was lost? If it's better to record it
> and use for non-sec mmu table?
>
> That can be arranged.
>
> >
> > If this func is called from non-secure state, for example EL2, the
> secure memory cannot be accessed and the PMD_SECT_NS bit should be
> cleared.
>
> We need to setup secure memory at EL3 to have secure memory to begin with.
> But you have a point here. Will look into it.
>
Yes, this func is called at EL3 for now, it is a assumption for this func.
I mean we'd better make it a API that can be invoked at both EL3 and EL2
to setup the MMU table. And do you know if the EL1 should be taken into
account in u-boot?
Thanks,
Zhiqiang
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Re: [U-Boot] [PATCH v6 2/2] armv8: fsl-layerscape: Make DDR non secure in MMU tables
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: 2015年12月3日 11:05
> To: Hou Zhiqiang-B48286; U-Boot Mailing List
> Cc: Pan Lijun-B44306; Hu Mingkai-B21284; Sharma Bhupesh-B45370; Gong
> Qianyu-B52263; Tom Rini; Li Yang-Leo-R58472; Albert Aribaud; Kushwaha
> Prabhakar-B32579; Wang Huan-B18965
> Subject: Re: [PATCH v6 2/2] armv8: fsl-layerscape: Make DDR non secure in
> MMU tables
>
>
>
> On 12/02/2015 06:48 PM, Hou Zhiqiang-B48286 wrote:
> >
> >
> >> -Original Message-
> >> From: York Sun [mailto:york...@freescale.com]
> >> Sent: 2015年12月3日 0:00
> >> To: Hou Zhiqiang-B48286; U-Boot Mailing List
> >> Cc: Pan Lijun-B44306; Hu Mingkai-B21284; Sharma Bhupesh-B45370; Gong
> >> Qianyu-B52263; Tom Rini; Li Yang-Leo-R58472; Albert Aribaud; Kushwaha
> >> Prabhakar-B32579; Wang Huan-B18965
> >> Subject: Re: [PATCH v6 2/2] armv8: fsl-layerscape: Make DDR non
> >> secure in MMU tables
> >>
> >>
> >>
> >> On 12/01/2015 10:38 PM, Hou Zhiqiang-B48286 wrote:
> >>
> >>
> >>
> >>>> /* Invalidate all table entries */
> >>>> memset(level0_table, 0, PGTABLE_SIZE); @@ -269,6 +344,22 @@
> >>>> static inline void final_mmu_setup(void)
> >>>> _mmu_table[i]);
> >>>> }
> >>>> }
> >>>> +/* Set the secure memory to secure in MMU */ #ifdef
> >>>> +CONFIG_SYS_MEM_RESERVE_SECURE
> >>>> +if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { #ifdef
> >>>> +CONFIG_FSL_LSCH3
> >>>> +level2_table_secure = level2_table1 + 512; #elif
> >>>> +defined(CONFIG_FSL_LSCH2)
> >>>> +level2_table_secure = level2_table2 + 512; #endif
> >>>> +/* update tlb pointer */
> >>>> +gd->arch.tlb_addr = gd->secure_ram & ~0x3;
> >>>
> >>> The memory reserved for mmu table was lost? If it's better to record
> >>> it
> >> and use for non-sec mmu table?
> >>
> >> That can be arranged.
> >>
> >>>
> >>> If this func is called from non-secure state, for example EL2, the
> >> secure memory cannot be accessed and the PMD_SECT_NS bit should be
> >> cleared.
> >>
> >> We need to setup secure memory at EL3 to have secure memory to begin
> with.
> >> But you have a point here. Will look into it.
> >>
> >
> > Yes, this func is called at EL3 for now, it is a assumption for this
> func.
> > I mean we'd better make it a API that can be invoked at both EL3 and
> > EL2 to setup the MMU table. And do you know if the EL1 should be taken
> > into account in u-boot?
>
> We don't need to differentiate this function for EL2 or EL1 if we ever
> need to run at. The only difference is EL3 can handle secure access. So
> adding a detection of exception level before setting secure bit will
> suffice.
ok.
Thanks,
Zhiqiang
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Re: [U-Boot] [PATCH v6 2/2] armv8: fsl-layerscape: Make DDR non secure in MMU tables
Hi York,
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: 2015年11月19日 2:02
> To: U-Boot Mailing List
> Cc: Sun York-R58495; Pan Lijun-B44306; Hu Mingkai-B21284; Sharma Bhupesh-
> B45370; Gong Qianyu-B52263; Tom Rini; Li Yang-Leo-R58472; Albert Aribaud;
> Hou Zhiqiang-B48286; Kushwaha Prabhakar-B32579; Wang Huan-B18965
> Subject: [PATCH v6 2/2] armv8: fsl-layerscape: Make DDR non secure in MMU
> tables
>
> DDR has been set as secure in MMU tables. Non-secure master such as SDHC
> DMA cannot access data correctly. Mixing secure and non- secure MMU
> entries requirs the MMU tables themselves in secure memory. This patch
> moves MMU tables into a secure DDR area.
>
> Early MMU tables are changed to set DDR as non-secure. A new table is
> added into final MMU tables so secure memory can have 2MB granuality.
>
> gd->secure_ram tracks the location of this secure memory. For
> ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
> banks. gd->secure_ram needs to be maintained before using. This
> maintenance is board-specific, depending on the SoC and memory bank of
> the secure memory falls into.
>
> Signed-off-by: York Sun <york...@freescale.com>
>
> fixup
> ---
>
> Changes in v6:
> Move cmd_bdinfo change to 1st patch in this set
> Rearrange #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
>
> Changes in v5:
> Put ifdef where gd->secure_ram is used
>
> Changes in v4:
> Drop RFC from patch prefix
> Drop excessive mmu table for secure ram for early MMU
> Update commit message accordingly
> Mark QBMan cacheable portal memory non-secure
>
> Changes in v3:
> Replace CONFIG_FSL_PPA_RESERVED_DRAM_SIZE with
> CONFIG_SYS_MEM_RESERVE_SECURE
> Sanity check gd->secure_ram before using
> Define CONFIG_SYS_MEM_RESERVE_SECURE in SoC header file
> Include ls1043ardb
> Modified commit message.
>
> Changes in v2:
> Move gd->arch.secure_ram to gd->secure_ram.
> Change the calculation of gd->secure_ram accordingly.
> Chnage commit message slightly accordingly.
>
> Changes in v1: None
>
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 111
> +++--
> arch/arm/include/asm/arch-fsl-layerscape/config.h |6 ++
> arch/arm/include/asm/arch-fsl-layerscape/cpu.h| 14 ++-
> board/freescale/ls1043ardb/ddr.c |4 +
> board/freescale/ls2085a/ddr.c | 15 +++
> board/freescale/ls2085aqds/ddr.c | 15 +++
> board/freescale/ls2085ardb/ddr.c | 15 +++
> 7 files changed, 165 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 9d1c70f..501feb3 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -206,11 +206,65 @@ static inline void early_mmu_setup(void)
> set_sctlr(get_sctlr() | CR_M);
> }
>
> +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
> +/*
> + * Called from final mmu setup. The phys_addr is new, non-existing
> + * address. A new sub table is created @level2_table_secure to cover
> + * size of CONFIG_SYS_MEM_RESERVE_SECURE memory.
> + */
> +static inline int final_secure_ddr(u64 *level0_table,
> +u64 *level2_table_secure,
> +phys_addr_t phys_addr)
> +{
> + int ret = -EINVAL;
> + struct table_info table = {};
> + struct sys_mmu_table ddr_entry = {
> + 0, 0, BLOCK_SIZE_L1, MT_NORMAL,
> + PMD_SECT_OUTER_SHARE | PMD_SECT_NS
> + };
> + u64 index;
> +
> + /* Need to create a new table */
> + ddr_entry.virt_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
> + ddr_entry.phys_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
> + ret = find_table(_entry, , level0_table);
> + if (ret)
> + return ret;
> + index = (ddr_entry.virt_addr - table.table_base) >>
> SECTION_SHIFT_L1;
> + set_pgtable_table(table.ptr, index, level2_table_secure);
> + table.ptr = level2_table_secure;
> + table.table_base = ddr_entry.virt_addr;
> + table.entry_size = BLOCK_SIZE_L2;
> + ret = set_block_entry(_entry, );
> + if (ret) {
> + printf("MMU error: could not fill non-secure ddr block
> entries\n");
> + return ret;
> + }
> + ddr_entry.virt_addr = phys_addr;
> + ddr_entry.phys_addr = phys_addr;
> + ddr_entry.size = CONFIG_SYS_MEM_RESERVE_SECURE;
> + ddr_entry.attribute = PMD_SECT_OUTER_SHARE;
> + ret = find_table(_entry, , level0_table);
> + if (ret) {
Re: [U-Boot] [Patch V7 04/18] net/fm/eth: Use mb() to be compatible for both ARM and PowerPC
> -Original Message- > From: Wood Scott-B07421 > Sent: 2015年10月23日 7:11 > To: Gong Qianyu-B52263 > Cc: u-boot@lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou > Zhiqiang-B48286; Xie Shaohui-B21989; Song Wenbin-B53747; Wood Scott- > B07421; Kushwaha Prabhakar-B32579; Wang Huan-B18965 > Subject: Re: [Patch V7 04/18] net/fm/eth: Use mb() to be compatible for > both ARM and PowerPC > > On Thu, 2015-10-22 at 18:46 +0800, Gong Qianyu wrote: > > From: Shaohui Xie <shaohui@freescale.com> > > > > Use mb() instead of sync() to be compatible for both ARM and PowerPC. > > > > Signed-off-by: Shaohui Xie <shaohui@freescale.com> > > Signed-off-by: Mingkai Hu <mingkai...@freescale.com> > > Signed-off-by: Gong Qianyu <qianyu.g...@freescale.com> > > --- > > V7: > > - No change. > > V6: > > - No change. > > V5: > > - No change. > > V4: > > - No change. > > V3: > > - New patch. Separated from patch 'net: Move some header files to > include/' > > > > drivers/net/fm/eth.c | 14 +++--- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index > > 368d554..ad02c66 100644 > > --- a/drivers/net/fm/eth.c > > +++ b/drivers/net/fm/eth.c > > @@ -371,7 +371,7 @@ static void > > fmc_tx_port_graceful_stop_enable(struct > > fm_eth *fm_eth) > > pram = fm_eth->tx_pram; > > /* graceful stop transmission of frames */ > > setbits_be32(>mode, PRAM_MODE_GRACEFUL_STOP); > > - sync(); > > + mb(); > > } > > > > static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth) > > @@ -381,7 +381,7 @@ static void > > fmc_tx_port_graceful_stop_disable(struct > > fm_eth *fm_eth) > > pram = fm_eth->tx_pram; > > /* re-enable transmission of frames */ > > clrbits_be32(>mode, PRAM_MODE_GRACEFUL_STOP); > > - sync(); > > + mb(); > > } > > Why is it needed at all? The I/O accessors should include the necessary > barriers. The I/O accessors of powerpc does include the barrier, but it absents from ARMs'. Thanks, Zhiqiang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V6 11/18] armv8/fsl_lsch3: Change arch to fsl-layerscape
> -Original Message- > From: Gong Qianyu [mailto:b52...@rhuath.am.freescale.net] > Sent: 2015年10月19日 19:59 > To: u-boot@lists.denx.de > Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui- > B21989; Song Wenbin-B53747; Wood Scott-B07421; Kushwaha Prabhakar-B32579; > Wang Huan-B18965; Gong Qianyu-B52263 > Subject: [Patch V6 11/18] armv8/fsl_lsch3: Change arch to fsl-layerscape > > From: Mingkai Hu <mingkai...@freescale.com> > > There are two LS series processors are built on ARMv8 Layersacpe > architecture currently, LS2085A and LS1043A. They are based on > ARMv8 core although use different chassis, so create fsl-layerscape > to refactor the common code for the LS series processors which also > paves the way for adding LS1043A platform. > > Signed-off-by: Mingkai Hu <mingkai...@freescale.com> > Signed-off-by: Gong Qianyu <qianyu.g...@freescale.com> Qianyu, you lost my Signed-off. Thanks, Zhqiang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V6 01/18] armv7/ls1021a: move ns_access to common file
> -Original Message- > From: Gong Qianyu [mailto:b52...@rhuath.am.freescale.net] > Sent: 2015年10月19日 19:59 > To: u-boot@lists.denx.de > Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui- > B21989; Song Wenbin-B53747; Wood Scott-B07421; Kushwaha Prabhakar-B32579; > Wang Huan-B18965; Gong Qianyu-B52263 > Subject: [Patch V6 01/18] armv7/ls1021a: move ns_access to common file > > From: Mingkai Hu <mingkai...@freescale.com> > > Config Security Level Register is different between different SoCs, so > put the CSL register definition into the arch specific directory. > > Signed-off-by: Mingkai Hu <mingkai...@freescale.com> > Signed-off-by: Gong Qianyu <qianyu.g...@freescale.com> Qianyu, you lost my Signed-off. Thanks, Zhqiang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2015年9月18日 2:14
> To: Gong Qianyu-B52263
> Cc: u-boot@lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> B07421
> Subject: Re: [Patch v2 08/16] net/fm: fix compile warnings for 64-bit
> platform
>
> On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > This patch fixes such compile warnings:
> >
> > drivers/net/fm/eth.c: In function 'fm_eth_recv':
> > drivers/net/fm/eth.c:549:11: warning: cast to pointer from integer of
> > different size [-Wint-to-pointer-cast]
> > data = (u8 *)in_be32(>buf_ptr_lo);
> > drivers/net/fm/fm.c: In function 'fm_muram_alloc':
> > drivers/net/fm/fm.c:52:9: warning: cast to pointer from integer of
> > different size [-Wint-to-pointer-cast]
> > memset((void *)ret, 0, size);
> > drivers/net/fm/fm.c: In function 'fm_init_muram':
> > drivers/net/fm/fm.c:59:13: warning: cast from pointer to integer of
> > different size [-Wpointer-to-int-cast]
> > u32 base = (u32)reg;
> >
> > Just make the cast explicit for them.
> >
> > Signed-off-by: Gong Qianyu <qianyu.g...@freescale.com>
> > ---
> > drivers/net/fm/eth.c | 31 ---
> > drivers/net/fm/fm.c | 4 ++--
> > 2 files changed, 18 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index
> > 12eb9b8..6ef0afb 100644
> > --- a/drivers/net/fm/eth.c
> > +++ b/drivers/net/fm/eth.c
> > @@ -120,12 +120,12 @@ static int tgec_is_fibre(struct eth_device *dev)
> >
> > static u16 muram_readw(u16 *addr)
> > {
> > - u32 base = (u32)addr & ~0x3;
> > + ulong base = (ulong)addr & ~0x3;
>
> This will still truncate the address at 32 bits. It needs to be ~0x3UL.
>
>
> > u32 val32 = in_be32((u32 *)base);
> > int byte_pos;
> > u16 ret;
> >
> > - byte_pos = (u32)addr & 0x3;
> > + byte_pos = (ulong)addr & 0x3;
> > if (byte_pos)
> > ret = (u16)(val32 & 0x);
> > else
> > @@ -136,12 +136,12 @@ static u16 muram_readw(u16 *addr)
> >
> > static void muram_writew(u16 *addr, u16 val) {
> > - u32 base = (u32)addr & ~0x3;
> > + ulong base = (ulong)addr & ~0x3;
> > u32 org32 = in_be32((u32 *)base);
> > u32 val32;
> > int byte_pos;
> >
> > - byte_pos = (u32)addr & 0x3;
> > + byte_pos = (ulong)addr & 0x3;
> > if (byte_pos)
> > val32 = (org32 & 0x) | val;
> > else
> > @@ -217,12 +217,12 @@ static int fm_eth_rx_port_parameter_init(struct
> > fm_eth *fm_eth)
> > int i;
> >
> > /* alloc global parameter ram at MURAM */
> > - pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth-
> >fm_index,
> > - FM_PRAM_SIZE, FM_PRAM_ALIGN);
> > + pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
> > + fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN);
>
> Make fm_muram_alloc() return a pointer instead. If muram were >= 4 GiB
> the above would fail.
>
The muram is a region included in CCSR.
So does we take muram >= 4GiB into account make sense?
> > fm_eth->rx_pram = pram;
> >
> > /* parameter page offset to MURAM */
> > - pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
> > + pram_page_offset = (u32)(ulong)pram -
> > + fm_muram_base(fm_eth->fm_index);
>
> Get rid of the u32 cast -- again, if the muram base were above >= 4 GiB
> this would fail because you're dropping the high bits before the
> subtraction rather than after.
>
> >
> > /* enable global mode- snooping data buffers and BDs */
> > out_be32(>mode, PRAM_MODE_GLOBAL); @@ -258,7 +258,8 @@
> > static int fm_eth_rx_port_parameter_init(struct fm_eth
> > *fm_eth)
> > muram_writew(>status, RxBD_EMPTY);
> > muram_writew(>len, 0);
> > muram_writew(>buf_ptr_hi, 0);
> > - out_be32(>buf_ptr_lo, (u32)rx_buf_pool + i *
> MAX_RXBUF_LEN);
> > + out_be32(>buf_ptr_lo, (u32)(ulong)rx_buf_pool +
> > + i *
> > + MAX_RXBUF_LEN);
> > rxbd++;
>
> Use virt_to_phys() and lower_32_bits(). Is there a "hi" register to
> handle the upper 32 bits?
>
> Likewise elsewhere. Don't just apply the minimum bandage to get rid of
> the warning. Make the code actually be 64-bit clean.
>
Thanks,
Zhiqiang
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Re: [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2015年9月25日 10:34
> To: Hou Zhiqiang-B48286
> Cc: Gong Qianyu-B52263; u-boot@lists.denx.de; Hu Mingkai-B21284; Sun
> York-R58495; Song Wenbin-B53747; Xie Shaohui-B21989
> Subject: Re: [Patch v2 08/16] net/fm: fix compile warnings for 64-bit
> platform
>
> On Thu, 2015-09-24 at 21:22 -0500, Hou Zhiqiang-B48286 wrote:
> >
> > > -Original Message-
> > > From: Wood Scott-B07421
> > > Sent: 2015年9月18日 2:14
> > > To: Gong Qianyu-B52263
> > > Cc: u-boot@lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> > > Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> > > B07421
> > > Subject: Re: [Patch v2 08/16] net/fm: fix compile warnings for
> > > 64-bit platform
> > >
> > > On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > > > This patch fixes such compile warnings:
> > > >
> > > > drivers/net/fm/eth.c: In function 'fm_eth_recv':
> > > > drivers/net/fm/eth.c:549:11: warning: cast to pointer from integer
> > > > of different size [-Wint-to-pointer-cast]
> > > > data = (u8 *)in_be32(>buf_ptr_lo);
> > > > drivers/net/fm/fm.c: In function 'fm_muram_alloc':
> > > > drivers/net/fm/fm.c:52:9: warning: cast to pointer from integer of
> > > > different size [-Wint-to-pointer-cast]
> > > > memset((void *)ret, 0, size);
> > > > drivers/net/fm/fm.c: In function 'fm_init_muram':
> > > > drivers/net/fm/fm.c:59:13: warning: cast from pointer to integer
> > > > of different size [-Wpointer-to-int-cast]
> > > > u32 base = (u32)reg;
> > > >
> > > > Just make the cast explicit for them.
> > > >
> > > > Signed-off-by: Gong Qianyu <qianyu.g...@freescale.com>
> > > > ---
> > > > drivers/net/fm/eth.c | 31 ---
> > > > drivers/net/fm/fm.c | 4 ++--
> > > > 2 files changed, 18 insertions(+), 17 deletions(-)
> > > >
> > > > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index
> > > > 12eb9b8..6ef0afb 100644
> > > > --- a/drivers/net/fm/eth.c
> > > > +++ b/drivers/net/fm/eth.c
> > > > @@ -120,12 +120,12 @@ static int tgec_is_fibre(struct eth_device
> > > > *dev)
> > > >
> > > > static u16 muram_readw(u16 *addr) {
> > > > - u32 base = (u32)addr & ~0x3;
> > > > + ulong base = (ulong)addr & ~0x3;
> > >
> > > This will still truncate the address at 32 bits. It needs to be
> ~0x3UL.
> > >
> > >
> > > > u32 val32 = in_be32((u32 *)base);
> > > > int byte_pos;
> > > > u16 ret;
> > > >
> > > > - byte_pos = (u32)addr & 0x3;
> > > > + byte_pos = (ulong)addr & 0x3;
> > > > if (byte_pos)
> > > > ret = (u16)(val32 & 0x);
> > > > else
> > > > @@ -136,12 +136,12 @@ static u16 muram_readw(u16 *addr)
> > > >
> > > > static void muram_writew(u16 *addr, u16 val) {
> > > > - u32 base = (u32)addr & ~0x3;
> > > > + ulong base = (ulong)addr & ~0x3;
> > > > u32 org32 = in_be32((u32 *)base);
> > > > u32 val32;
> > > > int byte_pos;
> > > >
> > > > - byte_pos = (u32)addr & 0x3;
> > > > + byte_pos = (ulong)addr & 0x3;
> > > > if (byte_pos)
> > > > val32 = (org32 & 0x) | val;
> > > > else
> > > > @@ -217,12 +217,12 @@ static int
> > > > fm_eth_rx_port_parameter_init(struct
> > > > fm_eth *fm_eth)
> > > > int i;
> > > >
> > > > /* alloc global parameter ram at MURAM */
> > > > - pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth-
> > > > fm_index,
> > > > - FM_PRAM_SIZE, FM_PRAM_ALIGN);
> > > > + pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
> > > > + fm_eth->fm_index, FM_PRAM_SIZE,
> > > > + FM_PRAM_ALIGN);
> > >
> > > Make fm_muram_alloc() return a pointer instead. If muram were >= 4
> > > GiB the above would fail.
> > >
> >
> > The muram is a region included in CCSR.
> > So does we take muram >= 4GiB into account make sense?
>
> The fact that currently, we run U-Boot as 32-bit on platforms where CCSR
> is
> >= 4GiB is not a good excuse to be sloppy with types.
>
ok.
Thanks,
Zhiqiang
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Re: [U-Boot] [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
Hello Jagannadha and Siva,
Do you have any idea for if there should be a shift upon the flash size?
If yes, why there isn't one when initializing the BAR read/write commands?
-Original Message-
From: Hou Zhiqiang-B48286
Sent: 2015年8月14日 18:02
To: 'Siva Durga Prasad Paladugu'; u-boot@lists.denx.de;
jt...@openedev.com; 'jaga...@xilinx.com'
Cc: Sun York-R58495; Hu Mingkai-B21284; nofooter
Subject: RE: [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
Hi Jagannadha,
See Siva's comments inline and For the DUAL spi flash memories, do you
have any comment?
-Original Message-
From: Siva Durga Prasad Paladugu
[mailto:siva.durga.palad...@xilinx.com]
Sent: 2015年8月14日 12:55
To: Hou Zhiqiang-B48286; u-boot@lists.denx.de; jt...@openedev.com
Cc: Sun York-R58495; Hu Mingkai-B21284; nofooter
Subject: RE: [PATCH V6] sf: Turn SPI flash chip into 3-Byte address
mode
Hi Zhiqiang,
-Original Message-
From: Zhiqiang Hou [mailto:b48...@freescale.com]
Sent: Wednesday, August 12, 2015 11:48 AM
To: u-boot@lists.denx.de; jt...@openedev.com
Cc: york...@freescale.com; mingkai...@freescale.com; Siva Durga
Prasad Paladugu; Hou Zhiqiang
Subject: [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
From: Hou Zhiqiang b48...@freescale.com
For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte
address mode, and only the 3-Byte address mode is supported in
U-Boot
so far.
So, reset the SPI flash to 3-Byte address mode in probe to ensure
the SPI flash work correctly, because it may has been set to 4-Byte
address mode after warm boot.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
Tested on T1042RDB board.
V6:
Add the spi_release_bus.
V5:
1. Removed #ifdef for STMICRO.
2. Add support for Spansion chips (16MiB) switch to 3-Byte
address
mode.
V4:
Split the the patch to 2 patches for clear FSR and SPI flash
address mode.
V3:
Generate the patch based on the latest tree git://git.denx.de/u-
boot.git.
V2:
Add the operation of enter 3 Byte address mode in probe.
V1:
Based on git://git.denx.de/u-boot.git.
drivers/mtd/spi/sf_internal.h | 7 +++
drivers/mtd/spi/sf_ops.c | 40
drivers/mtd/spi/sf_probe.c| 10 ++
3 files changed, 57 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 1de1dac..9519bd8 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -75,6 +75,10 @@ enum {
#define CMD_FLAG_STATUS 0x70
#define CMD_CLEAR_FLAG_STATUS0x50
+/* Used for Micron, Macronix and Winbond flashes */
+#define CMD_ENTER_4B_ADDR 0xB7
+#define CMD_EXIT_4B_ADDR0xE9
+
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_ARRAY_FAST 0x0b
@@ -231,6 +235,9 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash
*flash,
u32 offset,
size_t len, void *data);
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash,
+ int enable, u8 idcode0);
+
#ifdef CONFIG_SPI_FLASH_MTD
int spi_flash_mtd_register(struct spi_flash *flash); void
spi_flash_mtd_unregister(void); diff --git
a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index
deebcab..de30c55 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,46 @@ int spi_flash_cmd_write_config(struct spi_flash
*flash,
u8 wc) } #endif
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash,
+ int enable, u8 idcode0) {
+ int ret;
+ u8 cmd, bar;
+ bool need_wren = false;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: unable to claim SPI bus\n);
+ return ret;
+ }
+
+ switch (idcode0) {
+ case SPI_FLASH_CFI_MFR_STMICRO:
+ /* Some Micron need WREN command; all will accept it */
+ need_wren = true;
+ case SPI_FLASH_CFI_MFR_MACRONIX:
+ case SPI_FLASH_CFI_MFR_WINBOND:
+ if (need_wren)
+ spi_flash_cmd_write_enable(flash);
+
+ cmd = enable ? CMD_ENTER_4B_ADDR :
CMD_EXIT_4B_ADDR;
+ ret = spi_flash_cmd(flash-spi, cmd, NULL, 0);
+ if (need_wren)
+ spi_flash_cmd_write_disable(flash);
+
+ break;
+ default:
+ /* Spansion style */
+ bar = enable 7;
+ cmd = CMD_BANKADDR_BRWR;
+ ret = spi_flash_cmd_write(flash-spi, cmd, 1, bar, 1
Re: [U-Boot] [PATCH 0/6] sf: BAR/wait_ready logic updates
Hello Jagan, -Original Message- From: Jagan Teki [mailto:jt...@openedev.com] Sent: 2015年8月16日 16:50 To: u-boot@lists.denx.de; Hou Zhiqiang-B48286; Sun York-R58495 Cc: Jagan Teki Subject: Re: [PATCH 0/6] sf: BAR/wait_ready logic updates Hi Zhiqiang, On 16 August 2015 at 14:16, Jagan Teki jt...@openedev.com wrote: Hi Michal/Siva, On 16 August 2015 at 14:13, Jagan Teki jt...@openedev.com wrote: BAR and spi_flash_cmd_wait_ready are updated to make more module to add new status checks. Jagan Teki (6): spi: zynq_spi: Remove unneeded headers sf: Return proper bank_sel, if flash-bank_curr == bank_sel sf: Make BAR discovery, as spi_flash_read_bar sf: Optimize BAR write code sf: Make flash-flags use for generic usage sf: Update spi_flash_cmd_wait_ready Add your clear status register support on-top this, and let me know for any inputs. Sorry, I'm not in this context. What do you mean by 'Add your clear status register support on-top this'? Generate the patch base on the latest base? Pls- test BAR/wait_ready for all supported spi-nor flash. drivers/mtd/spi/sf_internal.h | 5 ++ drivers/mtd/spi/sf_ops.c | 153 + - drivers/mtd/spi/sf_probe.c| 64 +++--- drivers/spi/zynq_spi.c| 6 +- include/spi_flash.h | 6 +- 5 files changed, 121 insertions(+), 113 deletions(-) -- 1.9.1 Thanks, Zhiqiang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
Hi Jagannadha,
See Siva's comments inline and For the DUAL spi flash memories, do you have any
comment?
-Original Message-
From: Siva Durga Prasad Paladugu [mailto:siva.durga.palad...@xilinx.com]
Sent: 2015年8月14日 12:55
To: Hou Zhiqiang-B48286; u-boot@lists.denx.de; jt...@openedev.com
Cc: Sun York-R58495; Hu Mingkai-B21284; nofooter
Subject: RE: [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
Hi Zhiqiang,
-Original Message-
From: Zhiqiang Hou [mailto:b48...@freescale.com]
Sent: Wednesday, August 12, 2015 11:48 AM
To: u-boot@lists.denx.de; jt...@openedev.com
Cc: york...@freescale.com; mingkai...@freescale.com; Siva Durga Prasad
Paladugu; Hou Zhiqiang
Subject: [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
From: Hou Zhiqiang b48...@freescale.com
For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte
address mode, and only the 3-Byte address mode is supported in U-Boot
so far.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the
SPI flash work correctly, because it may has been set to 4-Byte
address mode after warm boot.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
Tested on T1042RDB board.
V6:
Add the spi_release_bus.
V5:
1. Removed #ifdef for STMICRO.
2. Add support for Spansion chips (16MiB) switch to 3-Byte address
mode.
V4:
Split the the patch to 2 patches for clear FSR and SPI flash
address mode.
V3:
Generate the patch based on the latest tree git://git.denx.de/u-
boot.git.
V2:
Add the operation of enter 3 Byte address mode in probe.
V1:
Based on git://git.denx.de/u-boot.git.
drivers/mtd/spi/sf_internal.h | 7 +++
drivers/mtd/spi/sf_ops.c | 40
drivers/mtd/spi/sf_probe.c| 10 ++
3 files changed, 57 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 1de1dac..9519bd8 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -75,6 +75,10 @@ enum {
#define CMD_FLAG_STATUS 0x70
#define CMD_CLEAR_FLAG_STATUS0x50
+/* Used for Micron, Macronix and Winbond flashes */
+#define CMD_ENTER_4B_ADDR 0xB7
+#define CMD_EXIT_4B_ADDR0xE9
+
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_ARRAY_FAST 0x0b
@@ -231,6 +235,9 @@ int spi_flash_read_common(struct spi_flash *flash,
const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash,
u32 offset,
size_t len, void *data);
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash,
+ int enable, u8 idcode0);
+
#ifdef CONFIG_SPI_FLASH_MTD
int spi_flash_mtd_register(struct spi_flash *flash); void
spi_flash_mtd_unregister(void); diff --git a/drivers/mtd/spi/sf_ops.c
b/drivers/mtd/spi/sf_ops.c index deebcab..de30c55 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,46 @@ int spi_flash_cmd_write_config(struct spi_flash
*flash,
u8 wc) } #endif
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash,
+ int enable, u8 idcode0) {
+ int ret;
+ u8 cmd, bar;
+ bool need_wren = false;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: unable to claim SPI bus\n);
+ return ret;
+ }
+
+ switch (idcode0) {
+ case SPI_FLASH_CFI_MFR_STMICRO:
+ /* Some Micron need WREN command; all will accept it */
+ need_wren = true;
+ case SPI_FLASH_CFI_MFR_MACRONIX:
+ case SPI_FLASH_CFI_MFR_WINBOND:
+ if (need_wren)
+ spi_flash_cmd_write_enable(flash);
+
+ cmd = enable ? CMD_ENTER_4B_ADDR :
CMD_EXIT_4B_ADDR;
+ ret = spi_flash_cmd(flash-spi, cmd, NULL, 0);
+ if (need_wren)
+ spi_flash_cmd_write_disable(flash);
+
+ break;
+ default:
+ /* Spansion style */
+ bar = enable 7;
+ cmd = CMD_BANKADDR_BRWR;
+ ret = spi_flash_cmd_write(flash-spi, cmd, 1, bar, 1);
+ }
+
+ spi_release_bus(flash-spi);
+
+ return ret;
+}
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8
bank_sel) { diff --git a/drivers/mtd/spi/sf_probe.c
b/drivers/mtd/spi/sf_probe.c index e0283dc..3b204f8 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -170,6 +170,16 @@ static int spi_flash_validate_params(struct
spi_slave *spi, u8 *idcode,
flash-page_size = flash-shift;
flash-sector_size = params-sector_size flash-shift;
flash-size = flash-sector_size * params-nr_sectors
flash-shift
Re: [U-Boot] [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
-Original Message-
From: Siva Durga Prasad Paladugu [mailto:siva.durga.palad...@xilinx.com]
Sent: 2015年8月13日 17:18
To: Hou Zhiqiang-B48286; u-boot@lists.denx.de; jt...@openedev.com
Cc: Sun York-R58495; Hu Mingkai-B21284; nofooter
Subject: RE: [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
Hi Zhejiang/Jagan,
I think it would be good to extend this further to support 4-byte
addressing in u-boot also.
This would be based on the driver, We can get the data that whether the
controller supports 4-byte or not from the driver level(through slave
struct) and enable 4 byte addressing here based on that.
That is a long way, and I don't think it is necessary for U-Boot. The U-Boot
work well using BAR to address more than 16MiB flash.
This patch focus on the address mode issue when warm boot up base on the BAR
address mode.
Let me know your thoughts on this.
Regards,
Siva
-Original Message-
From: Zhejiang Hou [mailto:b48...@freescale.com]
Sent: Wednesday, August 12, 2015 11:48 AM
To: u-boot@lists.denx.de; jt...@openedev.com
Cc: york...@freescale.com; mingkai...@freescale.com; Siva Durga Prasad
Paladugu; Hou Zhiqiang
Subject: [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
From: Hou Zhiqiang b48...@freescale.com
For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte
address mode, and only the 3-Byte address mode is supported in U-Boot
so far.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the
SPI flash work correctly, because it may has been set to 4-Byte
address mode after warm boot.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
Tested on T1042RDB board.
V6:
Add the spi_release_bus.
V5:
1. Removed #ifdef for STMICRO.
2. Add support for Spansion chips (16MiB) switch to 3-Byte address
mode.
V4:
Split the the patch to 2 patches for clear FSR and SPI flash
address mode.
V3:
Generate the patch based on the latest tree git://git.denx.de/u-
boot.git.
V2:
Add the operation of enter 3 Byte address mode in probe.
V1:
Based on git://git.denx.de/u-boot.git.
drivers/mtd/spi/sf_internal.h | 7 +++
drivers/mtd/spi/sf_ops.c | 40
drivers/mtd/spi/sf_probe.c| 10 ++
3 files changed, 57 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 1de1dac..9519bd8 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -75,6 +75,10 @@ enum {
#define CMD_FLAG_STATUS 0x70
#define CMD_CLEAR_FLAG_STATUS0x50
+/* Used for Micron, Macronix and Winbond flashes */
+#define CMD_ENTER_4B_ADDR 0xB7
+#define CMD_EXIT_4B_ADDR0xE9
+
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_ARRAY_FAST 0x0b
@@ -231,6 +235,9 @@ int spi_flash_read_common(struct spi_flash *flash,
const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash,
u32 offset,
size_t len, void *data);
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash,
+ int enable, u8 idcode0);
+
#ifdef CONFIG_SPI_FLASH_MTD
int spi_flash_mtd_register(struct spi_flash *flash); void
spi_flash_mtd_unregister(void); diff --git a/drivers/mtd/spi/sf_ops.c
b/drivers/mtd/spi/sf_ops.c index deebcab..de30c55 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,46 @@ int spi_flash_cmd_write_config(struct spi_flash
*flash,
u8 wc) } #endif
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash,
+ int enable, u8 idcode0) {
+ int ret;
+ u8 cmd, bar;
+ bool need_wren = false;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: unable to claim SPI bus\n);
+ return ret;
+ }
+
+ switch (idcode0) {
+ case SPI_FLASH_CFI_MFR_STMICRO:
+ /* Some Micron need WREN command; all will accept it */
+ need_wren = true;
+ case SPI_FLASH_CFI_MFR_MACRONIX:
+ case SPI_FLASH_CFI_MFR_WINBOND:
+ if (need_wren)
+ spi_flash_cmd_write_enable(flash);
+
+ cmd = enable ? CMD_ENTER_4B_ADDR :
CMD_EXIT_4B_ADDR;
+ ret = spi_flash_cmd(flash-spi, cmd, NULL, 0);
+ if (need_wren)
+ spi_flash_cmd_write_disable(flash);
+
+ break;
+ default:
+ /* Spansion style */
+ bar = enable 7;
+ cmd = CMD_BANKADDR_BRWR;
+ ret = spi_flash_cmd_write(flash-spi, cmd, 1, bar, 1);
+ }
+
+ spi_release_bus(flash-spi);
+
+ return ret;
+}
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash
Re: [U-Boot] [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
Hello all, As Siva said the 4-Byte support should be splited to another thread. And this patch focus on the BAR addressing mode base on the current u-boot, the aim is make the spi flash work upon warm boot, specifically when boot from SPI flash, without correcting the address mode, it will crash when kernel set the spi flash to 4-Byte address mode. -Original Message- From: Siva Durga Prasad Paladugu [mailto:siva.durga.palad...@xilinx.com] Sent: 2015年8月13日 20:48 To: Jagan Teki Cc: Stefan Roese; Hou Zhiqiang-B48286; u-boot@lists.denx.de; nofooter; Sun York-R58495 Subject: RE: [U-Boot] [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode B.R Zhiqiang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [V4 2/2] sf: Turn SPI flash into 3-Byte address mode on Micron chips
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: 2015年8月11日 1:10
To: Hou Zhiqiang-B48286
Cc: u-boot@lists.denx.de; Sun York-R58495
Subject: Re: [U-Boot] [V4 2/2] sf: Turn SPI flash into 3-Byte address
mode on Micron chips
On 10 August 2015 at 08:28, Hou Zhiqiang b48...@freescale.com wrote:
Hi Jagan,
Do you have any feedback?
-Original Message-
From: Zhiqiang Hou [mailto:b48...@freescale.com]
Sent: 2015年7月23日 17:54
To: u-boot@lists.denx.de; jt...@openedev.com
Cc: Sun York-R58495; Hu Mingkai-B21284; Hou Zhiqiang-B48286
Subject: [V4 2/2] sf: Turn SPI flash into 3-Byte address mode on
Micron chips
From: Hou Zhiqiang b48...@freescale.com
For more than 16MiB Micron chips, there are 3-Byte and 4-Byte address
mode, and only the 3-Byte address mode is supported in u-boot.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the
SPI flash work correctly, because it may be in 4-Byte address mode
after warm boot.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
drivers/mtd/spi/sf_internal.h | 8
drivers/mtd/spi/sf_ops.c | 24
drivers/mtd/spi/sf_probe.c| 5 +
3 files changed, 37 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 703d4a7..3d7ed24 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -75,6 +75,10 @@ enum {
#define CMD_FLAG_STATUS 0x70
#define CMD_CLEAR_FLAG_STATUS0x50
+/* Used for Macronix and Winbond flashes */
+#define CMD_ENTER_4B_ADDR 0xB7
+#define CMD_EXIT_4B_ADDR0xE9
+
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_ARRAY_FAST 0x0b
@@ -227,6 +231,10 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash
*flash, u32 offset,
size_t len, void *data);
+#if defined(CONFIG_SPI_FLASH_STMICRO) int
+spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable);
+#endif
+
#ifdef CONFIG_SPI_FLASH_MTD
int spi_flash_mtd_register(struct spi_flash *flash); void
spi_flash_mtd_unregister(void); diff --git a/drivers/mtd/spi/sf_ops.c
b/drivers/mtd/spi/sf_ops.c index cbb9f00..1ce14d1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash
*flash,
u8 wc) } #endif
+#if defined(CONFIG_SPI_FLASH_STMICRO) int
+spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable) {
+ int ret;
+ u8 cmd;
+
+ cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: unable to claim SPI bus\n);
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret 0) {
+ debug(SF: enabling write failed\n);
+ return ret;
+ }
+
+ return spi_flash_cmd(flash-spi, cmd, NULL, 0); } #endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8
bank_sel) { diff --git a/drivers/mtd/spi/sf_probe.c
b/drivers/mtd/spi/sf_probe.c index e0283dc..5ba7dde 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -231,6 +231,11 @@ static int spi_flash_validate_params(struct
spi_slave *spi, u8 *idcode, #ifdef CONFIG_SPI_FLASH_STMICRO
if (params-flags E_FSR)
flash-poll_cmd = CMD_FLAG_STATUS;
+
+ if (flash-size SPI_FLASH_16MB_BOUN) {
+ if (spi_flash_cmd_4B_addr_switch(flash, 0) 0)
+ debug(SF: enter 3B address mode failed\n);
+ }
Don't add STMICRO specific macro, add something like 1. define a macro
CONFIG_SF_EN4B 2. probe check for size 16MiB, and try to set the 4byte
addressing.
Thanks for your suggestions and Patch version 5 has been pushed to upstream.
In patch version 5:
Removed the STMICRO specific macro and add Spansion chips address mode switch
support.
Force the chips (16MiB) switch to 3-Byte address mode in probe, due to the
4-Byte
Mode isn't supported so far in U-Boot, so didn't define a macro CONFIG_SF_EN4B,
and read/write 16MiB chips by the extend address register.
#endif
/* Configure the BAR - discover bank cmds and read current bank
*/
--
2.1.0.27.g96db324
thanks!
--
Jagan | openedev.
Thanks,
Zhiqiang
___
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U-Boot@lists.denx.de
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Re: [U-Boot] [V4 1/2] sf: Add clear flag status register operation on Micron chips
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: 2015年8月11日 1:06
To: Hou Zhiqiang-B48286
Cc: u-boot@lists.denx.de; Hu Mingkai-B21284
Subject: Re: [U-Boot] [V4 1/2] sf: Add clear flag status register
operation on Micron chips
On 23 July 2015 at 15:24, Zhiqiang Hou b48...@freescale.com wrote:
From: Hou Zhiqiang b48...@freescale.com
Add clear flag status register operation that was required by Micron
SPI flash chips after reading the flag status register to check if the
erase and program operations complete or an error occur.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
Signed-off-by: Mingkai.Hu mingkai...@freescale.com
---
drivers/mtd/spi/sf_internal.h | 9 +
drivers/mtd/spi/sf_ops.c | 40 ---
-
2 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 9fb5557..703d4a7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -73,6 +73,7 @@ enum {
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+#define CMD_CLEAR_FLAG_STATUS 0x50
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
@@ -96,6 +97,8 @@ enum {
#define STATUS_QEB_WINSPAN (1 1)
#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
+#define STATUS_PROT(1 1)
+#define STATUS_ERASE (1 5)
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
@@ -182,6 +185,12 @@ static inline int
spi_flash_cmd_write_disable(struct spi_flash *flash)
return spi_flash_cmd(flash-spi, CMD_WRITE_DISABLE, NULL, 0);
}
+/* Clear flag status register */
+static inline int spi_flash_cmd_clear_flag_status(struct spi_slave
+*spi) {
+ return spi_flash_cmd(spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); }
+
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index
38592f5..cbb9f00 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -160,6 +160,7 @@ static int spi_flash_poll_status(struct spi_slave
*spi, unsigned long timeout,
unsigned long timebase;
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ int out_of_time = 1;
u8 status;
u8 check_status = 0x0;
@@ -182,22 +183,45 @@ static int spi_flash_poll_status(struct spi_slave
*spi, unsigned long timeout,
WATCHDOG_RESET();
ret = spi_xfer(spi, 8, NULL, status, 0);
- if (ret)
+ if (ret) {
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
return -1;
+ }
- if ((status poll_bit) == check_status)
+ if ((status poll_bit) == check_status) {
+ out_of_time = 0;
break;
+ }
} while (get_timer(timebase) timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
- if ((status poll_bit) == check_status)
- return 0;
+ if (out_of_time) {
+ /* Timed out */
+ debug(SF: time out!\n);
+ if (cmd == CMD_FLAG_STATUS) {
+ if (spi_flash_cmd_clear_flag_status(spi) 0)
+ debug(SF: clear flag status failed\n);
+ }
+ ret = -1;
+ }
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ else if (cmd == CMD_FLAG_STATUS) {
+ if (!(status (STATUS_PROT | STATUS_ERASE))) {
+ ret = 0;
+ } else {
+ debug(SF: flag status error);
+ ret = -1;
+ }
Don't add any #ifdef for STMICRO, as this clear status only require when
FSR used, so try to do that when ever FSR does.
Something like here:
/* read */
spi_xfer for FSR and then CFSR
/* status */
spi_xfer for FSR and then CFSR
Let me know if you need any inputs.
Thanks for your suggestions!
In patch v5, removed the #ifdef and clear the FSR only when there is any error
Bit has been set.
- /* Timed out */
- debug(SF: time out!\n);
- return -1;
+ if (spi_flash_cmd_clear_flag_status(spi) 0) {
+ debug(SF: clear flag status failed\n);
+ ret = -1;
+ }
+ }
+#endif
+ return ret;
}
int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long
timeout) @@ -252,7 +276,7 @@ int spi_flash_write_common
Re: [U-Boot] [PATCH V5 2/2] sf: Turn SPI flash chip into 3-Byte address mode
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: 2015年8月11日 19:45
To: Hou Zhiqiang-B48286
Cc: u-boot@lists.denx.de; Siva Durga Prasad Paladugu; Sun York-R58495
Subject: Re: [U-Boot] [PATCH V5 2/2] sf: Turn SPI flash chip into 3-Byte
address mode
On 11 August 2015 at 16:25, Zhiqiang Hou b48...@freescale.com wrote:
From: Hou Zhiqiang b48...@freescale.com
For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte
address mode, and only the 3-Byte address mode is supported in U-Boot
so far.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the
SPI flash work correctly, because it may has been set to 4-Byte
address mode after warm boot.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
Tested on T1042RDB board.
V5:
1. Removed #ifdef for STMICRO.
2. Add support for Spansion chips (16MiB) switch to 3-Byte address
mode.
V4:
Split the the patch to 2 patches for clear FSR and SPI flash
address mode.
V3:
Generate the patch based on the latest tree git://git.denx.de/u-
boot.git.
V2:
Add the operation of enter 3 Byte address mode in probe.
V1:
Based on git://git.denx.de/u-boot.git.
drivers/mtd/spi/sf_internal.h | 7 +++
drivers/mtd/spi/sf_ops.c | 36
drivers/mtd/spi/sf_probe.c| 10 ++
3 files changed, 53 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 1de1dac..9519bd8 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -75,6 +75,10 @@ enum {
#define CMD_FLAG_STATUS0x70
#define CMD_CLEAR_FLAG_STATUS 0x50
+/* Used for Micron, Macronix and Winbond flashes */
+#defineCMD_ENTER_4B_ADDR 0xB7
+#defineCMD_EXIT_4B_ADDR0xE9
+
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
#define CMD_READ_ARRAY_FAST0x0b
@@ -231,6 +235,9 @@ int spi_flash_read_common(struct spi_flash *flash,
const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
size_t len, void *data);
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash,
+ int enable, u8 idcode0);
+
#ifdef CONFIG_SPI_FLASH_MTD
int spi_flash_mtd_register(struct spi_flash *flash); void
spi_flash_mtd_unregister(void); diff --git a/drivers/mtd/spi/sf_ops.c
b/drivers/mtd/spi/sf_ops.c index deebcab..ace1156 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,42 @@ int spi_flash_cmd_write_config(struct spi_flash
*flash, u8 wc) } #endif
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash,
+ int enable, u8 idcode0) {
+ int ret;
+ u8 cmd, bar;
+ bool need_wren = false;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: unable to claim SPI bus\n);
+ return ret;
+ }
+
+ switch (idcode0) {
+ case SPI_FLASH_CFI_MFR_STMICRO:
+ /* Some Micron need WREN command; all will accept it */
+ need_wren = true;
+ case SPI_FLASH_CFI_MFR_MACRONIX:
+ case SPI_FLASH_CFI_MFR_WINBOND:
+ if (need_wren)
+ spi_flash_cmd_write_enable(flash);
+
+ cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR;
+ ret = spi_flash_cmd(flash-spi, cmd, NULL, 0);
+ if (need_wren)
+ spi_flash_cmd_write_disable(flash);
+
+ return ret;
+ default:
+ /* Spansion style */
+ bar = enable 7;
+ cmd = CMD_BANKADDR_BRWR;
+ return spi_flash_cmd_write(flash-spi, cmd, 1, bar,
1);
+ }
+}
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8
bank_sel) { diff --git a/drivers/mtd/spi/sf_probe.c
b/drivers/mtd/spi/sf_probe.c index e0283dc..3b204f8 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -170,6 +170,16 @@ static int spi_flash_validate_params(struct
spi_slave *spi, u8 *idcode,
flash-page_size = flash-shift;
flash-sector_size = params-sector_size flash-shift;
flash-size = flash-sector_size * params-nr_sectors
flash-shift;
+
+ /*
+* So far, the 4-byte address mode haven't been supported in U-
Boot,
+* and make sure the chip ( 16MiB) in default 3-byte address
mode,
+* in case of warm bootup, the chip was set to 4-byte mode in
kernel.
+*/
+ if (flash-size SPI_FLASH_16MB_BOUN) {
+ if (spi_flash_cmd_4B_addr_switch(flash, false,
idcode[0]) 0)
+ debug(SF: enter 3B address mode failed\n
Re: [U-Boot] [V4 1/2] sf: Add clear flag status register operation on Micron chips
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: 2015年8月7日 16:22
To: Hou Zhiqiang-B48286
Cc: u-boot@lists.denx.de; Hu Mingkai-B21284
Subject: Re: [U-Boot] [V4 1/2] sf: Add clear flag status register
operation on Micron chips
On 23 July 2015 at 15:24, Zhiqiang Hou b48...@freescale.com wrote:
From: Hou Zhiqiang b48...@freescale.com
Add clear flag status register operation that was required by Micron
SPI flash chips after reading the flag status register to check if the
erase and program operations complete or an error occur.
Flag status requires N25Q512 + parts, so clear flag status we need add
only in this scenario is that true?
Yes, so the clear FSR operation will work only if the chip supports FSR.
And if the chip supports FSR, it will support both read and clear FSR.
So there is a condition branch if (cmd == CMD_FLAG_STATUS).
Signed-off-by: Hou Zhiqiang b48...@freescale.com
Signed-off-by: Mingkai.Hu mingkai...@freescale.com
---
drivers/mtd/spi/sf_internal.h | 9 +
drivers/mtd/spi/sf_ops.c | 40 ---
-
2 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 9fb5557..703d4a7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -73,6 +73,7 @@ enum {
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+#define CMD_CLEAR_FLAG_STATUS 0x50
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
@@ -96,6 +97,8 @@ enum {
#define STATUS_QEB_WINSPAN (1 1)
#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
+#define STATUS_PROT(1 1)
+#define STATUS_ERASE (1 5)
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
@@ -182,6 +185,12 @@ static inline int
spi_flash_cmd_write_disable(struct spi_flash *flash)
return spi_flash_cmd(flash-spi, CMD_WRITE_DISABLE, NULL, 0);
}
+/* Clear flag status register */
+static inline int spi_flash_cmd_clear_flag_status(struct spi_slave
+*spi) {
+ return spi_flash_cmd(spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); }
+
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index
38592f5..cbb9f00 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -160,6 +160,7 @@ static int spi_flash_poll_status(struct spi_slave
*spi, unsigned long timeout,
unsigned long timebase;
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ int out_of_time = 1;
u8 status;
u8 check_status = 0x0;
@@ -182,22 +183,45 @@ static int spi_flash_poll_status(struct spi_slave
*spi, unsigned long timeout,
WATCHDOG_RESET();
ret = spi_xfer(spi, 8, NULL, status, 0);
- if (ret)
+ if (ret) {
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
return -1;
+ }
- if ((status poll_bit) == check_status)
+ if ((status poll_bit) == check_status) {
+ out_of_time = 0;
break;
+ }
} while (get_timer(timebase) timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
- if ((status poll_bit) == check_status)
- return 0;
+ if (out_of_time) {
+ /* Timed out */
+ debug(SF: time out!\n);
+ if (cmd == CMD_FLAG_STATUS) {
+ if (spi_flash_cmd_clear_flag_status(spi) 0)
+ debug(SF: clear flag status failed\n);
+ }
+ ret = -1;
+ }
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ else if (cmd == CMD_FLAG_STATUS) {
+ if (!(status (STATUS_PROT | STATUS_ERASE))) {
+ ret = 0;
+ } else {
+ debug(SF: flag status error);
+ ret = -1;
+ }
- /* Timed out */
- debug(SF: time out!\n);
- return -1;
+ if (spi_flash_cmd_clear_flag_status(spi) 0) {
+ debug(SF: clear flag status failed\n);
+ ret = -1;
+ }
+ }
+#endif
+ return ret;
}
int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long
timeout) @@ -252,7 +276,7 @@ int spi_flash_write_common(struct
spi_flash *flash, const u8 *cmd,
ret = spi_flash_cmd_wait_ready(flash
Re: [U-Boot] [V4 2/2] sf: Turn SPI flash into 3-Byte address mode on Micron chips
Hi Jagan,
Do you have any feedback?
-Original Message-
From: Zhiqiang Hou [mailto:b48...@freescale.com]
Sent: 2015年7月23日 17:54
To: u-boot@lists.denx.de; jt...@openedev.com
Cc: Sun York-R58495; Hu Mingkai-B21284; Hou Zhiqiang-B48286
Subject: [V4 2/2] sf: Turn SPI flash into 3-Byte address mode on Micron
chips
From: Hou Zhiqiang b48...@freescale.com
For more than 16MiB Micron chips, there are 3-Byte and 4-Byte address
mode, and only the 3-Byte address mode is supported in u-boot.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the SPI
flash work correctly, because it may be in 4-Byte address mode after warm
boot.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
drivers/mtd/spi/sf_internal.h | 8
drivers/mtd/spi/sf_ops.c | 24
drivers/mtd/spi/sf_probe.c| 5 +
3 files changed, 37 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 703d4a7..3d7ed24 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -75,6 +75,10 @@ enum {
#define CMD_FLAG_STATUS 0x70
#define CMD_CLEAR_FLAG_STATUS0x50
+/* Used for Macronix and Winbond flashes */
+#define CMD_ENTER_4B_ADDR 0xB7
+#define CMD_EXIT_4B_ADDR0xE9
+
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_ARRAY_FAST 0x0b
@@ -227,6 +231,10 @@ int spi_flash_read_common(struct spi_flash *flash,
const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
size_t len, void *data);
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable);
+#endif
+
#ifdef CONFIG_SPI_FLASH_MTD
int spi_flash_mtd_register(struct spi_flash *flash); void
spi_flash_mtd_unregister(void); diff --git a/drivers/mtd/spi/sf_ops.c
b/drivers/mtd/spi/sf_ops.c index cbb9f00..1ce14d1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash,
u8 wc) } #endif
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable) {
+ int ret;
+ u8 cmd;
+
+ cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: unable to claim SPI bus\n);
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret 0) {
+ debug(SF: enabling write failed\n);
+ return ret;
+ }
+
+ return spi_flash_cmd(flash-spi, cmd, NULL, 0); } #endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8
bank_sel) { diff --git a/drivers/mtd/spi/sf_probe.c
b/drivers/mtd/spi/sf_probe.c index e0283dc..5ba7dde 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -231,6 +231,11 @@ static int spi_flash_validate_params(struct
spi_slave *spi, u8 *idcode, #ifdef CONFIG_SPI_FLASH_STMICRO
if (params-flags E_FSR)
flash-poll_cmd = CMD_FLAG_STATUS;
+
+ if (flash-size SPI_FLASH_16MB_BOUN) {
+ if (spi_flash_cmd_4B_addr_switch(flash, 0) 0)
+ debug(SF: enter 3B address mode failed\n);
+ }
#endif
/* Configure the BAR - discover bank cmds and read current bank */
--
2.1.0.27.g96db324
Thanks,
Zhiqiang
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Re: [U-Boot] [V4 1/2] sf: Add clear flag status register operation on Micron chips
Hi Jagan,
Do you have any feedback?
-Original Message-
From: Zhiqiang Hou [mailto:b48...@freescale.com]
Sent: 2015年7月23日 17:54
To: u-boot@lists.denx.de; jt...@openedev.com
Cc: Sun York-R58495; Hu Mingkai-B21284; Hou Zhiqiang-B48286; Hu Mingkai-
B21284
Subject: [V4 1/2] sf: Add clear flag status register operation on Micron
chips
From: Hou Zhiqiang b48...@freescale.com
Add clear flag status register operation that was required by Micron SPI
flash chips after reading the flag status register to check if the erase
and program operations complete or an error occur.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
Signed-off-by: Mingkai.Hu mingkai...@freescale.com
---
drivers/mtd/spi/sf_internal.h | 9 +
drivers/mtd/spi/sf_ops.c | 40 -
---
2 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 9fb5557..703d4a7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -73,6 +73,7 @@ enum {
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG 0x35
#define CMD_FLAG_STATUS 0x70
+#define CMD_CLEAR_FLAG_STATUS0x50
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
@@ -96,6 +97,8 @@ enum {
#define STATUS_QEB_WINSPAN (1 1)
#define STATUS_QEB_MXIC (1 6)
#define STATUS_PEC (1 7)
+#define STATUS_PROT (1 1)
+#define STATUS_ERASE (1 5)
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
@@ -182,6 +185,12 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
return spi_flash_cmd(flash-spi, CMD_WRITE_DISABLE, NULL, 0); }
+/* Clear flag status register */
+static inline int spi_flash_cmd_clear_flag_status(struct spi_slave
+*spi) {
+ return spi_flash_cmd(spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); }
+
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index
38592f5..cbb9f00 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -160,6 +160,7 @@ static int spi_flash_poll_status(struct spi_slave
*spi, unsigned long timeout,
unsigned long timebase;
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ int out_of_time = 1;
u8 status;
u8 check_status = 0x0;
@@ -182,22 +183,45 @@ static int spi_flash_poll_status(struct spi_slave
*spi, unsigned long timeout,
WATCHDOG_RESET();
ret = spi_xfer(spi, 8, NULL, status, 0);
- if (ret)
+ if (ret) {
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
return -1;
+ }
- if ((status poll_bit) == check_status)
+ if ((status poll_bit) == check_status) {
+ out_of_time = 0;
break;
+ }
} while (get_timer(timebase) timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
- if ((status poll_bit) == check_status)
- return 0;
+ if (out_of_time) {
+ /* Timed out */
+ debug(SF: time out!\n);
+ if (cmd == CMD_FLAG_STATUS) {
+ if (spi_flash_cmd_clear_flag_status(spi) 0)
+ debug(SF: clear flag status failed\n);
+ }
+ ret = -1;
+ }
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ else if (cmd == CMD_FLAG_STATUS) {
+ if (!(status (STATUS_PROT | STATUS_ERASE))) {
+ ret = 0;
+ } else {
+ debug(SF: flag status error);
+ ret = -1;
+ }
- /* Timed out */
- debug(SF: time out!\n);
- return -1;
+ if (spi_flash_cmd_clear_flag_status(spi) 0) {
+ debug(SF: clear flag status failed\n);
+ ret = -1;
+ }
+ }
+#endif
+ return ret;
}
int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long
timeout) @@ -252,7 +276,7 @@ int spi_flash_write_common(struct spi_flash
*flash, const u8 *cmd,
ret = spi_flash_cmd_wait_ready(flash, timeout);
if (ret 0) {
- debug(SF: write %s timed out\n,
+ debug(SF: write %s failed\n,
timeout == SPI_FLASH_PROG_TIMEOUT ?
program : page erase);
return ret;
--
2.1.0.27.g96db324
Thanks,
Zhiqiang
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Re: [U-Boot] [PATCH V3] sf: Add support for flag status register on Micron chips
Hi Jagan,
Tested the latest source code, after running the 'reboot' command, the sf
commands executed incorrectly due to the reboot process is a warm boot,
during the process system will keep the power supply, so the SPI flash
will keep the 4-byte address mode, which was modified by kernel. But
this address mode isn't supported by u-boot.
Two points should be cleared:
1. I saw the patch polling both the SR and FSR, but it doesn't check
the error bits, and according to Mircon datasheet n25q512a, the error
bits must be cleared through the CLEAR FLAG STATUS REGISTER command.
2. the address mode should be reset to 3-byte mode, upon the warm boot,
if the address mode has been changed to 4-byte mode, sf commands will
execute incorrectly.
Per the two points above, I will split this patch to two patches.
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: 2015年6月19日 16:21
To: Hou Zhiqiang-B48286
Cc: u-boot@lists.denx.de; Sun York-R58495; Hu Mingkai-B21284
Subject: Re: [PATCH V3] sf: Add support for flag status register on
Micron chips
I think you may missed my comment on v2 [1] Just check with master.
If something not works well, will review the same.
[1] https://patchwork.ozlabs.org/patch/469961/
On 25 May 2015 at 09:03, Hou Zhiqiang b48...@freescale.com wrote:
Hi Jagan,
So much long time no comment, could you please apply this patch?
Thanks,
Zhiqiang
-Original Message-
From: Zhiqiang Hou [mailto:b48...@freescale.com]
Sent: 2015年5月11日 16:35
To: u-boot@lists.denx.de; jt...@openedev.com
Cc: Sun York-R58495; Hu Mingkai-B21284; Hou Zhiqiang-B48286; Hu
Mingkai-
B21284
Subject: [PATCH V3] sf: Add support for flag status register on
Micron chips
From: Hou Zhiqiang b48...@freescale.com
Enter 3 Byte address mode at first, because it may change to 4 Byte
address mode in kernel driver and not reset to 3 Byte address mode
after reboot.
Add clear flag status register operation that some Micron SPI flash
chips required after reading the flag status register to check some
operations completion.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
Signed-off-by: Mingkai.Hu mingkai...@freescale.com
---
V3:
Generate the patch based on the latest tree git://git.denx.de/u-
boot.git.
V2:
Add the operation of enter 3 Byte address mode in probe.
V1:
Based on git://git.denx.de/u-boot.git.
Also can be applied to git://www.denx.de/git/u-boot-mpc85xx.git.
Tested on board T2080QDS and T2080RDB.
drivers/mtd/spi/sf_internal.h | 17
drivers/mtd/spi/sf_ops.c | 64
+--
drivers/mtd/spi/sf_probe.c| 5
3 files changed, 78 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 4158e13..24a693e 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -73,6 +73,11 @@ enum {
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG 0x35
#define CMD_FLAG_STATUS 0x70
+#define CMD_CLEAR_FLAG_STATUS0x50
+
+/* Used for Macronix and Winbond flashes */
+#define CMD_ENTER_4B_ADDR 0xB7
+#define CMD_EXIT_4B_ADDR0xE9
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
@@ -96,6 +101,8 @@ enum {
#define STATUS_QEB_WINSPAN (1 1)
#define STATUS_QEB_MXIC (1 6)
#define STATUS_PEC (1 7)
+#define STATUS_PROT (1 1)
+#define STATUS_ERASE (1 5)
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
@@ -182,6 +189,12 @@ static inline int
spi_flash_cmd_write_disable(struct
spi_flash *flash)
return spi_flash_cmd(flash-spi, CMD_WRITE_DISABLE, NULL, 0);
}
+/* Clear flag status register */
+static inline int spi_flash_cmd_clear_flag_status(struct spi_slave
+*spi) {
+ return spi_flash_cmd(spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); }
+
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
@@ -218,4 +231,8 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash
*flash, u32 offset,
size_t len, void *data);
+#if defined(CONFIG_SPI_FLASH_STMICRO) int
+spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable);
+#endif
+
#endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index
38592f5..1ce14d1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash
*flash,
u8 wc) } #endif
+#if defined(CONFIG_SPI_FLASH_STMICRO) int
+spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable
Re: [U-Boot] [PATCH V3] sf: Add support for flag status register on Micron chips
Hi Jagan,
So much long time no comment, could you please apply this patch?
Thanks,
Zhiqiang
-Original Message-
From: Zhiqiang Hou [mailto:b48...@freescale.com]
Sent: 2015年5月11日 16:35
To: u-boot@lists.denx.de; jt...@openedev.com
Cc: Sun York-R58495; Hu Mingkai-B21284; Hou Zhiqiang-B48286; Hu Mingkai-
B21284
Subject: [PATCH V3] sf: Add support for flag status register on Micron
chips
From: Hou Zhiqiang b48...@freescale.com
Enter 3 Byte address mode at first, because it may change to 4 Byte
address mode in kernel driver and not reset to 3 Byte address mode after
reboot.
Add clear flag status register operation that some Micron SPI flash chips
required after reading the flag status register to check some operations
completion.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
Signed-off-by: Mingkai.Hu mingkai...@freescale.com
---
V3:
Generate the patch based on the latest tree git://git.denx.de/u-boot.git.
V2:
Add the operation of enter 3 Byte address mode in probe.
V1:
Based on git://git.denx.de/u-boot.git.
Also can be applied to git://www.denx.de/git/u-boot-mpc85xx.git.
Tested on board T2080QDS and T2080RDB.
drivers/mtd/spi/sf_internal.h | 17
drivers/mtd/spi/sf_ops.c | 64
+--
drivers/mtd/spi/sf_probe.c| 5
3 files changed, 78 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h index 4158e13..24a693e 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -73,6 +73,11 @@ enum {
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG 0x35
#define CMD_FLAG_STATUS 0x70
+#define CMD_CLEAR_FLAG_STATUS0x50
+
+/* Used for Macronix and Winbond flashes */
+#define CMD_ENTER_4B_ADDR 0xB7
+#define CMD_EXIT_4B_ADDR0xE9
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
@@ -96,6 +101,8 @@ enum {
#define STATUS_QEB_WINSPAN (1 1)
#define STATUS_QEB_MXIC (1 6)
#define STATUS_PEC (1 7)
+#define STATUS_PROT (1 1)
+#define STATUS_ERASE (1 5)
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
@@ -182,6 +189,12 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
return spi_flash_cmd(flash-spi, CMD_WRITE_DISABLE, NULL, 0); }
+/* Clear flag status register */
+static inline int spi_flash_cmd_clear_flag_status(struct spi_slave
+*spi) {
+ return spi_flash_cmd(spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); }
+
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
@@ -218,4 +231,8 @@ int spi_flash_read_common(struct spi_flash *flash,
const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
size_t len, void *data);
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable);
+#endif
+
#endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index
38592f5..1ce14d1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash,
u8 wc) } #endif
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable) {
+ int ret;
+ u8 cmd;
+
+ cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: unable to claim SPI bus\n);
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret 0) {
+ debug(SF: enabling write failed\n);
+ return ret;
+ }
+
+ return spi_flash_cmd(flash-spi, cmd, NULL, 0); } #endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8
bank_sel) { @@ -160,6 +184,7 @@ static int spi_flash_poll_status(struct
spi_slave *spi, unsigned long timeout,
unsigned long timebase;
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ int out_of_time = 1;
u8 status;
u8 check_status = 0x0;
@@ -182,22 +207,45 @@ static int spi_flash_poll_status(struct spi_slave
*spi, unsigned long timeout,
WATCHDOG_RESET();
ret = spi_xfer(spi, 8, NULL, status, 0);
- if (ret)
+ if (ret) {
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
return -1;
+ }
- if ((status poll_bit) == check_status)
+ if ((status poll_bit) == check_status) {
+ out_of_time = 0;
break
[U-Boot] [PATCH V2] sf: Add support for flag status register on Micron chips
Enter 3 Byte address mode at first, because it may change to 4 Byte
address mode in kernel driver and not reset to 3 Byte address mode
after reboot.
Add clear flag status register operation that some Micron SPI flash
chips required after reading the flag status register to check some
operations completion.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
Signed-off-by: Mingkai.Hu mingkai...@freescale.com
---
V1:
Based on git://git.denx.de/u-boot.git.
Also can be applied to git://www.denx.de/git/u-boot-mpc85xx.git.
Tested on board T2080QDS and T2080RDB.
V2:
Add the operation of enter 3 Byte address mode in probe.
drivers/mtd/spi/sf_internal.h | 17
drivers/mtd/spi/sf_ops.c | 64 +--
drivers/mtd/spi/sf_probe.c| 5
3 files changed, 78 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 19d4914..49e5a2c 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -36,6 +36,11 @@
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+#define CMD_CLEAR_FLAG_STATUS 0x50
+
+/* Used for Macronix and Winbond flashes */
+#defineCMD_ENTER_4B_ADDR 0xB7
+#defineCMD_EXIT_4B_ADDR0xE9
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
@@ -59,6 +64,8 @@
#define STATUS_QEB_WINSPAN (1 1)
#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
+#define STATUS_PROT(1 1)
+#define STATUS_ERASE (1 5)
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
#define STATUS_SRWD(1 7) /* SR write protect */
@@ -124,6 +131,12 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
return spi_flash_cmd(flash-spi, CMD_WRITE_DISABLE, NULL, 0);
}
+/* Clear flag status register */
+static inline int spi_flash_cmd_clear_flag_status(struct spi_flash *flash)
+{
+ return spi_flash_cmd(flash-spi, CMD_CLEAR_FLAG_STATUS, NULL, 0);
+}
+
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
@@ -160,4 +173,8 @@ int spi_flash_read_common(struct spi_flash *flash, const u8
*cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data);
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable);
+#endif
+
#endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 85cf22d..8a532b8 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8
wc)
}
#endif
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable)
+{
+ int ret;
+ u8 cmd;
+
+ cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: unable to claim SPI bus\n);
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret 0) {
+ debug(SF: enabling write failed\n);
+ return ret;
+ }
+
+ return spi_flash_cmd(flash-spi, cmd, NULL, 0);
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
@@ -160,6 +184,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
unsigned long timebase;
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ int out_of_time = 1;
u8 status;
u8 check_status = 0x0;
u8 poll_bit = STATUS_WIP;
@@ -186,22 +211,45 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
WATCHDOG_RESET();
ret = spi_xfer(spi, 8, NULL, status, 0);
- if (ret)
+ if (ret) {
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
return -1;
+ }
- if ((status poll_bit) == check_status)
+ if ((status poll_bit) == check_status) {
+ out_of_time = 0;
break;
+ }
} while (get_timer(timebase) timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
- if ((status poll_bit) == check_status)
- return 0;
+ if (out_of_time) {
+ /* Timed out */
+ debug(SF: time out!\n);
+ if (cmd == CMD_FLAG_STATUS) {
+ if (spi_flash_cmd_clear_flag_status(flash) 0)
+ debug(SF: clear flag status failed\n);
+ }
+ ret
[U-Boot] [PATCH] powerpc/t104xrdb: Enable SPI flash Extend address support
Enable the Extend address to support SPI flash more than 16MB. Signed-off-by: Hou Zhiqiang b48...@freescale.com --- Based on git://git.denx.de/u-boot.git. Also can be applied to git://www.denx.de/git/u-boot-mpc85xx.git. Tested on board T1040RDB. include/configs/T104xRDB.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 0ee0ff2..d4c6f58 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -503,6 +503,7 @@ #define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 1000 #define CONFIG_SF_DEFAULT_MODE 0 -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sf: Add support for flag status register on Micron chips
Add clear flag status register operation that some Micron SPI flash
chips required after reading the flag status register to check some
operations completion.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
Based on git://git.denx.de/u-boot.git.
It also can be applied to git://www.denx.de/git/u-boot-mpc85xx.git.
Tested on board T2080QDS and T2080RDB.
drivers/mtd/spi/sf_internal.h | 9 +
drivers/mtd/spi/sf_ops.c | 36
2 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 6bcd522..162dd87 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -36,6 +36,7 @@
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+#define CMD_CLEAR_FLAG_STATUS 0x50
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
@@ -59,6 +60,8 @@
#define STATUS_QEB_WINSPAN (1 1)
#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
+#define STATUS_PROT(1 1)
+#define STATUS_ERASE (1 5)
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
@@ -120,6 +123,12 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
return spi_flash_cmd(flash-spi, CMD_WRITE_DISABLE, NULL, 0);
}
+/* Clear flag status register */
+static inline int spi_flash_cmd_clear_flag_status(struct spi_flash *flash)
+{
+ return spi_flash_cmd(flash-spi, CMD_CLEAR_FLAG_STATUS, NULL, 0);
+}
+
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 85cf22d..08ff1df 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -160,6 +160,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
unsigned long timebase;
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ int out_of_time = 1;
u8 status;
u8 check_status = 0x0;
u8 poll_bit = STATUS_WIP;
@@ -186,22 +187,41 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
WATCHDOG_RESET();
ret = spi_xfer(spi, 8, NULL, status, 0);
- if (ret)
+ if (ret) {
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
return -1;
+ }
- if ((status poll_bit) == check_status)
+ if ((status poll_bit) == check_status) {
+ out_of_time = 0;
break;
+ }
} while (get_timer(timebase) timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
- if ((status poll_bit) == check_status)
- return 0;
+ if (out_of_time) {
+ /* Timed out */
+ debug(SF: time out!\n);
+ ret = -1;
+ }
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ else if (cmd == CMD_FLAG_STATUS) {
+ if (!(status (STATUS_PROT | STATUS_ERASE))) {
+ ret = 0;
+ } else {
+ debug(SF: flag status error);
+ ret = -1;
+ }
- /* Timed out */
- debug(SF: time out!\n);
- return -1;
+ if (spi_flash_cmd_clear_flag_status(flash) 0) {
+ debug(SF: clear flag status failed\n);
+ ret = -1;
+ }
+ }
+#endif
+ return ret;
}
int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
@@ -234,7 +254,7 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
ret = spi_flash_cmd_wait_ready(flash, timeout);
if (ret 0) {
- debug(SF: write %s timed out\n,
+ debug(SF: write %s failed\n,
timeout == SPI_FLASH_PROG_TIMEOUT ?
program : page erase);
return ret;
--
1.8.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/espi: remove 80us delay to improve transfer performance
Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
drivers/spi/fsl_espi.c | 138 +
1 file changed, 106 insertions(+), 32 deletions(-)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 7c84582..ae0fe58 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -15,8 +15,10 @@
struct fsl_spi_slave {
struct spi_slave slave;
+ ccsr_espi_t *espi;
unsigned intdiv16;
unsigned intpm;
+ int tx_timeout;
unsigned intmode;
size_t cmd_len;
u8 cmd_buf[16];
@@ -25,11 +27,17 @@ struct fsl_spi_slave {
};
#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
+#define US_PER_SECOND 100UL
#define ESPI_MAX_CS_NUM4
+#define ESPI_FIFO_WIDTH_BIT32
#define ESPI_EV_RNE(1 9)
#define ESPI_EV_TNF(1 8)
+#define ESPI_EV_DON(1 14)
+#define ESPI_EV_TXE(1 15)
+#define ESPI_EV_RFCNT_SHIFT24
+#define ESPI_EV_RFCNT_MASK (0x3f ESPI_EV_RFCNT_SHIFT)
#define ESPI_MODE_EN (1 31) /* Enable interface */
#define ESPI_MODE_TXTHR(x) ((x) 8) /* Tx FIFO threshold */
@@ -61,6 +69,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
struct fsl_spi_slave *fsl;
sys_info_t sysinfo;
unsigned long spibrg = 0;
+ unsigned long spi_freq = 0;
unsigned char pm = 0;
if (!spi_cs_is_valid(bus, cs))
@@ -70,6 +79,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
if (!fsl)
return NULL;
+ fsl-espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
fsl-mode = mode;
fsl-max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
@@ -91,6 +101,15 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
pm--;
fsl-pm = pm;
+ if (fsl-div16)
+ spi_freq = spibrg / ((pm + 1) * 2 * 16);
+ else
+ spi_freq = spibrg / ((pm + 1) * 2);
+
+ /* set tx_timeout to 10 times of one espi FIFO entry go out */
+ fsl-tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
+ * 10), spi_freq);
+
return fsl-slave;
}
@@ -108,7 +127,7 @@ void spi_init(void)
int spi_claim_bus(struct spi_slave *slave)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ ccsr_espi_t *espi = fsl-espi;
unsigned char pm = fsl-pm;
unsigned int cs = slave-cs;
unsigned int mode = fsl-mode;
@@ -161,24 +180,86 @@ void spi_release_bus(struct spi_slave *slave)
}
+static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
+{
+ ccsr_espi_t *espi = fsl-espi;
+ unsigned int tmpdout, event;
+ int tmp_tx_timeout;
+
+ if (dout)
+ tmpdout = *(u32 *)dout;
+ else
+ tmpdout = 0;
+
+ out_be32(espi-tx, tmpdout);
+ out_be32(espi-event, ESPI_EV_TNF);
+ debug(***spi_xfer:...%08x written\n, tmpdout);
+
+ tmp_tx_timeout = fsl-tx_timeout;
+ /* Wait for eSPI transmit to go out */
+ while (tmp_tx_timeout--) {
+ event = in_be32(espi-event);
+ if (event ESPI_EV_DON || event ESPI_EV_TXE) {
+ out_be32(espi-event, ESPI_EV_TXE);
+ break;
+ }
+ udelay(1);
+ }
+
+ if (tmp_tx_timeout 0)
+ debug(***spi_xfer:...Tx timeout! event = %08x\n, event);
+}
+
+static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int
bytes)
+{
+ ccsr_espi_t *espi = fsl-espi;
+ unsigned int tmpdin, rx_times;
+ unsigned char *buf, *p_cursor;
+
+ if (bytes = 0)
+ return 0;
+
+ rx_times = DIV_ROUND_UP(bytes, 4);
+ buf = (unsigned char *)malloc(4 * rx_times);
+ if (!buf) {
+ debug(SF: Failed to malloc memory.\n);
+ return -1;
+ }
+ p_cursor = buf;
+ while (rx_times--) {
+ tmpdin = in_be32(espi-rx);
+ debug(***spi_xfer:...%08x readed\n, tmpdin);
+ *(u32 *)p_cursor = tmpdin;
+ p_cursor += 4;
+ }
+
+ if (din)
+ memcpy(din, buf, bytes);
+
+ free(buf);
+ out_be32(espi-event, ESPI_EV_RNE);
+
+ return bytes;
+}
+
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void
*data_out,
void *data_in, unsigned long flags)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
- unsigned int tmpdout, tmpdin, event;
+ ccsr_espi_t *espi = fsl-espi;
+ unsigned int
