Re: [U-Boot] [PATCH 2/2] Create the S5PC100 SoC header under the include/asm-arm/arch-s5pc100
Dear Dirk, Ah, I was busy yesterday. Well, I can write the message now. I wonder if there is any patch missing here? Is it correct that this series stops after 2 patches? Shouldn't there be at least something added to board directory? And I miss a config file to be able to compile this stuff. Ok. I have a patch. It's a board specific file. But, It's not ready to send yet. It's working on. So, I update the SoC Header patches first to be reviewed to maintainers or countributors. Is it available? or not? I was not sure whether it was right or not. As soon as possible, I'll update Board patch for SMDKC100. Perhaps, It'll be next weeks, and I will re-update any other my fixed patches. - new S5PC100 #0, 1, 2. Thanks to keep watching :) Best Regards, riverful ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] I wonder --- in the patch file generated by the git-format-patch
Dear Wolfgang Denk, I have a question about git-format-patch usage. I generated the patch using git-format-patch. The my usage is the following : 1. pull latest git repo. 2. change the code 3. # git commit -a -s 4. insert commit any other things. 5. # git-format-patch -1 So, I get patch. But, this patch's form is different with you said. First of all, the all comments is on the ---. But, you said all comments must belong below the --- like this messages. : http://lists.denx.de/pipermail/u-boot/2009-June/053535.html It's different. What did I lose anything during the patching progress?? Can you tell me what is wrong?? Thanks to read. Best Regards, riverful ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] move L2 cache enable/disable function to cache.c in the omap3 SoC directory
CC: Dirk Behme dirk.be...@googlemail.com
Signed-off-by: HeungJun, Kim riverful@samsung.com
---
The omap3 L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c. Because, it must be CortexA8 ARCH generic
code below the cpu/arm_cortexa8.
This patches fixes the First issue in the following
http://lists.denx.de/pipermail/u-boot/2009-May/053433.html
The Second issue is fixed by
http://lists.denx.de/pipermail/u-boot/2009-May/053490.html
cpu/arm_cortexa8/cpu.c | 70 ++---
cpu/arm_cortexa8/omap3/Makefile |2 +-
cpu/arm_cortexa8/omap3/board.c |5 +-
cpu/arm_cortexa8/omap3/cache.c | 96 +++
include/asm-arm/cache.h | 31 +
5 files changed, 135 insertions(+), 69 deletions(-)
create mode 100644 cpu/arm_cortexa8/omap3/cache.c
create mode 100644 include/asm-arm/cache.h
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..4675812 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -33,17 +33,13 @@
#include common.h
#include command.h
-#include asm/arch/sys_proto.h
#include asm/system.h
+#include asm/cache.h
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif
-#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
-#endif
-
static void cache_flush(void);
int cpu_init(void)
@@ -80,7 +76,7 @@ int cleanup_before_linux(void)
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
- l2cache_disable();
+ l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
@@ -89,72 +85,14 @@ int cleanup_before_linux(void)
asm(mcr p15, 0, %0, c7, c10, 4: :r(i));
#ifndef CONFIG_L2_OFF
- l2cache_enable();
+ l2_cache_enable();
#endif
return 0;
}
-void l2cache_enable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(orr r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-
-}
-
-void l2cache_disable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(bic %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(bic r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-}
-
static void cache_flush(void)
{
asm (mcr p15, 0, %0, c7, c5, 0: :r (0));
}
+
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index b96b3dd..f83036b 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
-COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o
+COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..439ea6a 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -36,6 +36,7 @@
#include
[U-Boot] [PATCH 1/2] Create the S5PC100 SoC code under the cpu/arm_cortesa8/
Signed-off-by: HeungJun, Kim riverful@samsung.com --- This patch is the new processor - S5PC100's SoC code headers. This patch consists of 2 files. The First file is to create the new SoC code related with S5PC100 application processor. It's located in ther cpu/arm_cortesa8/s5pc100. The Second file is to create the new SoC header related with S5PC100 application processor. It's located in ther include/asm-arm/s5pc100. This file is the First. cpu/arm_cortexa8/s5pc100/Makefile | 48 +++ cpu/arm_cortexa8/s5pc100/config.mk| 36 ++ cpu/arm_cortexa8/s5pc100/cpu_init.S | 196 + cpu/arm_cortexa8/s5pc100/interrupts.c | 218 + cpu/arm_cortexa8/s5pc100/speed.c | 159 5 files changed, 657 insertions(+), 0 deletions(-) create mode 100644 cpu/arm_cortexa8/s5pc100/Makefile create mode 100644 cpu/arm_cortexa8/s5pc100/config.mk create mode 100644 cpu/arm_cortexa8/s5pc100/cpu_init.S create mode 100644 cpu/arm_cortexa8/s5pc100/interrupts.c create mode 100644 cpu/arm_cortexa8/s5pc100/speed.c diff --git a/cpu/arm_cortexa8/s5pc100/Makefile b/cpu/arm_cortexa8/s5pc100/Makefile new file mode 100644 index 000..4688533 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc100/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).a + +COBJS-y= interrupts.o +COBJS-$(CONFIG_S5PC100)+= cpu_init.o speed.o + +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all:$(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/cpu/arm_cortexa8/s5pc100/config.mk b/cpu/arm_cortexa8/s5pc100/config.mk new file mode 100644 index 000..e05d7ae --- /dev/null +++ b/cpu/arm_cortexa8/s5pc100/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, g...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +# Make ARMv5 to allow more compilers to work, even though its v6. +PLATFORM_CPPFLAGS += -march=armv5t +# = +# +# Supply options according to compiler version +# +# = +PLATFORM_CPPFLAGS +=$(call cc-option) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\ + $(call cc-option,-malignment-traps,)) diff --git a/cpu/arm_cortexa8/s5pc100/cpu_init.S b/cpu/arm_cortexa8/s5pc100/cpu_init.S new file mode 100644 index 000..4510049 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc100/cpu_init.S @@ -0,0 +1,196 @@ +/* + * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx + * + * Copyright (C) 2008 + * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de + + * Copyright (C) 2009 + * Inki Dae, SAMSUNG Electronics, inki@samsung.com + * Heungjun Kim,
[U-Boot] [PATCH 2/2] Create the S5PC100 SoC header under the include/asm-arm/arch-s5pc100
Signed-off-by: HeungJun, Kim riverful@samsung.com --- This patch is the new processor - S5PC100's SoC code headers. This patch consists of 2 files. The First file is to create the new SoC code related with S5PC100 application processor. It's located in ther cpu/arm_cortesa8/s5pc100. The Second file is to create the new SoC header related with S5PC100 application processor. It's located in ther include/asm-arm/s5pc100. This file is the Second. include/asm-arm/arch-s5pc100/clock.h | 137 +++ include/asm-arm/arch-s5pc100/cpu.h | 292 +++ include/asm-arm/arch-s5pc100/gpio.h | 580 ++ include/asm-arm/arch-s5pc100/hardware.h | 63 include/asm-arm/arch-s5pc100/sys_proto.h | 25 ++ include/asm-arm/arch-s5pc100/uart.h | 94 + include/asm-arm/arch-s5pc100/watchdog.h | 39 ++ 7 files changed, 1230 insertions(+), 0 deletions(-) create mode 100644 include/asm-arm/arch-s5pc100/clock.h create mode 100644 include/asm-arm/arch-s5pc100/cpu.h create mode 100644 include/asm-arm/arch-s5pc100/gpio.h create mode 100644 include/asm-arm/arch-s5pc100/hardware.h create mode 100644 include/asm-arm/arch-s5pc100/sys_proto.h create mode 100644 include/asm-arm/arch-s5pc100/uart.h create mode 100644 include/asm-arm/arch-s5pc100/watchdog.h diff --git a/include/asm-arm/arch-s5pc100/clock.h b/include/asm-arm/arch-s5pc100/clock.h new file mode 100644 index 000..c703eec --- /dev/null +++ b/include/asm-arm/arch-s5pc100/clock.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2009 + * Inki Dae, SAMSUNG Electronics, inki@samsung.com + * Heungjun Kim, SAMSUNG Electronics, riverful@samsung.com + * Minkyu Kang, SAMSUNG Electronics, mk7.k...@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Clock control + */ +#define S5P_CLKREG(x) (S5P_PA_CLK + (x)) + +/* Clock Register */ +#define S5P_APLL_LOCK S5P_CLKREG(0x0) +#define S5P_MPLL_LOCK S5P_CLKREG(0x4) +#define S5P_EPLL_LOCK S5P_CLKREG(0x8) +#define S5P_HPLL_LOCK S5P_CLKREG(0xc) + +#define S5P_APLL_CON S5P_CLKREG(0x100) +#define S5P_MPLL_CON S5P_CLKREG(0x104) +#define S5P_EPLL_CON S5P_CLKREG(0x108) +#define S5P_HPLL_CON S5P_CLKREG(0x10c) + +#define S5P_CLK_SRC0 S5P_CLKREG(0x200) +#define S5P_CLK_SRC1 S5P_CLKREG(0x204) +#define S5P_CLK_SRC2 S5P_CLKREG(0x208) +#define S5P_CLK_SRC3 S5P_CLKREG(0x20c) + +#define S5P_CLK_DIV0 S5P_CLKREG(0x300) +#define S5P_CLK_DIV1 S5P_CLKREG(0x304) +#define S5P_CLK_DIV2 S5P_CLKREG(0x308) +#define S5P_CLK_DIV3 S5P_CLKREG(0x30c) +#define S5P_CLK_DIV4 S5P_CLKREG(0x310) + +#define S5P_CLK_OUTS5P_CLKREG(0x400) + +#define S5P_CLK_GATE_D00 S5P_CLKREG(0x500) +#define S5P_CLK_GATE_D01 S5P_CLKREG(0x504) +#define S5P_CLK_GATE_D02 S5P_CLKREG(0x508) +#define S5P_CLK_GATE_D10 S5P_CLKREG(0x520) +#define S5P_CLK_GATE_D11 S5P_CLKREG(0x524) +#define S5P_CLK_GATE_D12 S5P_CLKREG(0x528) +#define S5P_CLK_GATE_D13 S5P_CLKREG(0x530) +#define S5P_CLK_GATE_D14 S5P_CLKREG(0x534) +#define S5P_CLK_GATE_D20 S5P_CLKREG(0x540) +#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x560) +#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x564) + +/* + * Clock control - Others + */ +#define S5P_OTHERS_REG_BASE(x) (S5P_PA_CLK_OTHERS + (x)) +#define S5P_OTHERS_BASES5P_OTHERS_REG_BASE(0x0) +#define S5P_SW_RST S5P_OTHERS_REG_BASE(0x0) +#define S5P_ONENAND_RSTS5P_OTHERS_REG_BASE(0x8) +#define S5P_GENERAL_CTRL S5P_OTHERS_REG_BASE(0x100) +#define S5P_GENERAL_STATUS S5P_OTHERS_REG_BASE(0x104) +#define S5P_MEM_SYS_CFGS5P_OTHERS_REG_BASE(0x200) +#define S5P_CAM_MUX_SELS5P_OTHERS_REG_BASE(0x300) +#define S5P_MIXER_OUT_SEL S5P_OTHERS_REG_BASE(0x304) +#define S5P_LPMP3_MODE_SEL S5P_OTHERS_REG_BASE(0x308) +#define S5P_MIPI_PHY_CON0 S5P_OTHERS_REG_BASE(0x400) +#define S5P_MIPI_PHY_CON1 S5P_OTHERS_REG_BASE(0x414) +#define
[U-Boot] [PATCH]
Dear Jean,
I made new patch about L2 cane enable/disable function.
The related thread is here.
http://www.mail-archive.com/u-boot@lists.denx.de/msg14744.html
I fixed title issue apart header.
Thanks to read :)
Best Regards,
riverful
=
omap3 L2 cache enable/disable function moved from cpu/arm_cortexa8/cpu.c
to cpu/arm_cortexa8/omap3/. for generic SoC supports.
Signed-off-by: HeungJun, Kim riverful@samsung.com
---
cpu/arm_cortexa8/cpu.c | 68 +-
cpu/arm_cortexa8/omap3/Makefile|2 +-
cpu/arm_cortexa8/omap3/board.c |5 +-
cpu/arm_cortexa8/omap3/cache.c | 99
include/asm-arm/arch-omap3/sys_proto.h |1 -
include/asm-arm/cache.h| 37
6 files changed, 143 insertions(+), 69 deletions(-)
create mode 100644 cpu/arm_cortexa8/omap3/cache.c
create mode 100644 include/asm-arm/cache.h
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..96f42a9 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -35,15 +35,12 @@
#include command.h
#include asm/arch/sys_proto.h
#include asm/system.h
+#include asm/cache.h
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif
-#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
-#endif
-
static void cache_flush(void);
int cpu_init(void)
@@ -80,7 +77,7 @@ int cleanup_before_linux(void)
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
- l2cache_disable();
+ l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
@@ -89,71 +86,12 @@ int cleanup_before_linux(void)
asm(mcr p15, 0, %0, c7, c10, 4: :r(i));
#ifndef CONFIG_L2_OFF
- l2cache_enable();
+ l2_cache_enable();
#endif
return 0;
}
-void l2cache_enable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(orr r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-
-}
-
-void l2cache_disable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(bic %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(bic r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-}
-
static void cache_flush(void)
{
asm (mcr p15, 0, %0, c7, c5, 0: :r (0));
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index b96b3dd..f83036b 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
-COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o
+COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..439ea6a 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -36,6 +36,7 @@
#include asm/io.h
#include
[U-Boot] [PATCH] omap3 L2-cache enable/disable function to omap3 dependent code
Dear Jean,
I miss mail title sorry. :)
=
Dear Jean,
I made new patch about L2 cane enable/disable function.
The related thread is here.
http://www.mail-archive.com/u-boot@lists.denx.de/msg14744.html
I fixed title issue apart header.
Thanks to read :)
Best Regards,
riverful
=
omap3 L2 cache enable/disable function moved from cpu/arm_cortexa8/cpu.c
to cpu/arm_cortexa8/omap3/. for generic SoC supports.
Signed-off-by: HeungJun, Kim riverful@samsung.com
---
cpu/arm_cortexa8/cpu.c | 68 +-
cpu/arm_cortexa8/omap3/Makefile|2 +-
cpu/arm_cortexa8/omap3/board.c |5 +-
cpu/arm_cortexa8/omap3/cache.c | 99
include/asm-arm/arch-omap3/sys_proto.h |1 -
include/asm-arm/cache.h| 37
6 files changed, 143 insertions(+), 69 deletions(-)
create mode 100644 cpu/arm_cortexa8/omap3/cache.c
create mode 100644 include/asm-arm/cache.h
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..96f42a9 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -35,15 +35,12 @@
#include command.h
#include asm/arch/sys_proto.h
#include asm/system.h
+#include asm/cache.h
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif
-#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
-#endif
-
static void cache_flush(void);
int cpu_init(void)
@@ -80,7 +77,7 @@ int cleanup_before_linux(void)
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
- l2cache_disable();
+ l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
@@ -89,71 +86,12 @@ int cleanup_before_linux(void)
asm(mcr p15, 0, %0, c7, c10, 4: :r(i));
#ifndef CONFIG_L2_OFF
- l2cache_enable();
+ l2_cache_enable();
#endif
return 0;
}
-void l2cache_enable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(orr r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-
-}
-
-void l2cache_disable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(bic %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(bic r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-}
-
static void cache_flush(void)
{
asm (mcr p15, 0, %0, c7, c5, 0: :r (0));
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index b96b3dd..f83036b 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
-COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o
+COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..439ea6a 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@
Re: [U-Boot] [PATCH] ARM Cortex A8: Move OMAP3 specific reset handler to OMAP3 code
Dear Jean Dirk, Jean's opinion seems that file naming func naming must match for soruce maintaining, definitely I agree with that. Moreover it's a very first time to implement the new arm_cortexa8 code for u-boot source. So, the matching works is needed. On the other hand, Dirk's opinion seems that it dosen't make sense in this case, if there is many files when the developer make the code. I think that too, especially when the code is a little simple like the boot code. The u-boot's architecture SoC directory tree is already brilliant, so it's alright we just look at this directories what arch SoC ever we develop. So, my opinions is re-using the files seems to be right in this case. the Dirk's patch code is not difficult to understand use. After the code polluted cause of not-matching the file func naming, I believe that the developers seem be able to fix this issue easily, like my case. BTW, when am I able to re-update my new patch?? I wanna do that :) Best Regards, riverful 2009/6/1 Dirk Behme dirk.be...@googlemail.com: Dear Jean-Christophe, Jean-Christophe PLAGNIOL-VILLARD wrote: On 09:30 Sat 30 May , Dirk Behme wrote: Reset is SoC specific and not ARM Cortex A8 generic. Move it from generic code to OMAP3 SoC specific file. CC: Kim, Heung Jun river...@gmail.com Signed-off-by: Dirk Behme dirk.be...@googlemail.com --- This patches fixes the second issue found by riverful in http://lists.denx.de/pipermail/u-boot/2009-May/053433.html The first issue is fixed by http://lists.denx.de/pipermail/u-boot/2009-May/053444.html cpu/arm_cortexa8/omap3/lowlevel_init.S | 12 cpu/arm_cortexa8/start.S | 14 -- 2 files changed, 12 insertions(+), 14 deletions(-) Index: u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S === --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/lowlevel_init.S +++ u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S @@ -181,6 +181,18 @@ lowlevel_init: /* back to arch calling code */ mov pc, lr +.global reset_cpu +reset_cpu: + ldr r1, rstctl @ get addr for global reset + @ reg + mov r3, #0x2 @ full reset pll + mpu + str r3, [r1] @ force reset + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl: + .word PRM_RSTCTRL + please move this to reset.S other wise fine Most probably your idea is that each file should only contain functionality which fits 100% (120%?) what the file name implies (?). While from general point of view this is correct, it makes no sense to create new files again and again just to follow this rule. We already created a cache.c on your request, now you request a new file reset.S for ~5 assembly lines. This new file would contain more comments (e.g. GPL header) than useful code. So while in general case having file names reflecting more or less the functionality in these files, in this case it doesn't make sense. It doesn't make sense to pollute the source tree with a new file containing ~5 assembly lines just to make your rules apply. For such small code, re-using existing file is the better way to go. So NACK in this case. Best regards Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] The omap3 L2 cache enable/disable function to omap3 dependent code
CC: Dirk Behme dirk.be...@googlemail.com
Signed-off-by: HeungJun, Kim riverful@samsung.com
---
The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c.
This patches fixes the First issue in the following
http://lists.denx.de/pipermail/u-boot/2009-May/053433.html
The Second issue is fixed by
http://lists.denx.de/pipermail/u-boot/2009-May/053490.html
cpu/arm_cortexa8/cpu.c | 68 +-
cpu/arm_cortexa8/omap3/Makefile|2 +-
cpu/arm_cortexa8/omap3/board.c |5 +-
cpu/arm_cortexa8/omap3/cache.c | 99
include/asm-arm/arch-omap3/sys_proto.h |1 -
include/asm-arm/cache.h| 37
6 files changed, 143 insertions(+), 69 deletions(-)
create mode 100644 cpu/arm_cortexa8/omap3/cache.c
create mode 100644 include/asm-arm/cache.h
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..96f42a9 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -35,15 +35,12 @@
#include command.h
#include asm/arch/sys_proto.h
#include asm/system.h
+#include asm/cache.h
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif
-#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
-#endif
-
static void cache_flush(void);
int cpu_init(void)
@@ -80,7 +77,7 @@ int cleanup_before_linux(void)
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
- l2cache_disable();
+ l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
@@ -89,71 +86,12 @@ int cleanup_before_linux(void)
asm(mcr p15, 0, %0, c7, c10, 4: :r(i));
#ifndef CONFIG_L2_OFF
- l2cache_enable();
+ l2_cache_enable();
#endif
return 0;
}
-void l2cache_enable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(orr r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-
-}
-
-void l2cache_disable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(bic %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(bic r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-}
-
static void cache_flush(void)
{
asm (mcr p15, 0, %0, c7, c5, 0: :r (0));
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index b96b3dd..f83036b 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
-COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o
+COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..439ea6a 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -36,6 +36,7 @@
#include asm/io.h
#include asm/arch/sys_proto.h
#include
[U-Boot] [PATCH] The omap3 L2 cache enable/disable function to omap3 dependent code
CC: Dirk Behme dirk.be...@googlemail.com
Signed-off-by: HeungJun, Kim riverful@samsung.com
---
The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c.
This patches fixes the First issue in the following
http://lists.denx.de/pipermail/u-boot/2009-May/053433.html
The Second issue is fixed by
http://lists.denx.de/pipermail/u-boot/2009-May/053490.html
cpu/arm_cortexa8/cpu.c | 68 +-
cpu/arm_cortexa8/omap3/Makefile|2 +-
cpu/arm_cortexa8/omap3/board.c |5 +-
cpu/arm_cortexa8/omap3/cache.c | 99
include/asm-arm/arch-omap3/sys_proto.h |1 -
include/asm-arm/cache.h| 37
6 files changed, 143 insertions(+), 69 deletions(-)
create mode 100644 cpu/arm_cortexa8/omap3/cache.c
create mode 100644 include/asm-arm/cache.h
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..96f42a9 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -35,15 +35,12 @@
#include command.h
#include asm/arch/sys_proto.h
#include asm/system.h
+#include asm/cache.h
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif
-#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
-#endif
-
static void cache_flush(void);
int cpu_init(void)
@@ -80,7 +77,7 @@ int cleanup_before_linux(void)
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
- l2cache_disable();
+ l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
@@ -89,71 +86,12 @@ int cleanup_before_linux(void)
asm(mcr p15, 0, %0, c7, c10, 4: :r(i));
#ifndef CONFIG_L2_OFF
- l2cache_enable();
+ l2_cache_enable();
#endif
return 0;
}
-void l2cache_enable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(orr r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-
-}
-
-void l2cache_disable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(bic %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(bic r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-}
-
static void cache_flush(void)
{
asm (mcr p15, 0, %0, c7, c5, 0: :r (0));
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index b96b3dd..f83036b 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
-COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o
+COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..439ea6a 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -36,6 +36,7 @@
#include asm/io.h
#include asm/arch/sys_proto.h
Re: [U-Boot] [PATCH] The omap3 L2 cache enable/disable function to omap3 dependent code
Dear Wolfgang,
I fixed the deficiencies like the following :
http://lists.denx.de/pipermail/u-boot/2009-June/053534.html
And, I use git-format-patch.
One more thing,
I wanted to tell that this is the exact time in the unmatch-naming case,
by the following thread. :
http://lists.denx.de/pipermail/u-boot/2009-June/053533.html
It's my fault that u don't understand my words :)
BTW, Very thanks to review.
Best Regards,
riverful
2009/6/1 Kim, Heung Jun river...@gmail.com:
CC: Dirk Behme dirk.be...@googlemail.com
Signed-off-by: HeungJun, Kim riverful@samsung.com
---
The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c.
This patches fixes the First issue in the following
http://lists.denx.de/pipermail/u-boot/2009-May/053433.html
The Second issue is fixed by
http://lists.denx.de/pipermail/u-boot/2009-May/053490.html
cpu/arm_cortexa8/cpu.c | 68 +-
cpu/arm_cortexa8/omap3/Makefile | 2 +-
cpu/arm_cortexa8/omap3/board.c | 5 +-
cpu/arm_cortexa8/omap3/cache.c | 99
include/asm-arm/arch-omap3/sys_proto.h | 1 -
include/asm-arm/cache.h | 37
6 files changed, 143 insertions(+), 69 deletions(-)
create mode 100644 cpu/arm_cortexa8/omap3/cache.c
create mode 100644 include/asm-arm/cache.h
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..96f42a9 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -35,15 +35,12 @@
#include command.h
#include asm/arch/sys_proto.h
#include asm/system.h
+#include asm/cache.h
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif
-#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
-#endif
-
static void cache_flush(void);
int cpu_init(void)
@@ -80,7 +77,7 @@ int cleanup_before_linux(void)
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
- l2cache_disable();
+ l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
@@ -89,71 +86,12 @@ int cleanup_before_linux(void)
asm(mcr p15, 0, %0, c7, c10, 4: :r(i));
#ifndef CONFIG_L2_OFF
- l2cache_enable();
+ l2_cache_enable();
#endif
return 0;
}
-void l2cache_enable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(orr r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-
-}
-
-void l2cache_disable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(bic %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(bic r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-}
-
static void cache_flush(void)
{
asm (mcr p15, 0, %0, c7, c5, 0: :r (0));
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index b96b3dd..f83036b 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3
Re: [U-Boot] [PATCH] The cache flush using coprocessor must be in lib_arm/cache-cp15.c
Thanks to point. Dirk. And call me riverful next time, plz :) Kim mentioned that he shuffles around the code due to compile errors while adding his new code. So we have to see if we can stay with the current implementation or have to change something. Yes. I shuffles around a little now. Kim: What compile errors do you get for cache_flush()? Could you check if you really don't need it? Why don't you get compile errors if you move it from cpu/arm_cortexa8/cpu.c to lib_arm/cache-cp15.c? The compile errors are two. 1. First error occured cause of omap3 dependent definition CPU_3XX_ES20. cpu.c:99: warning: function declaration isn't a prototype cpu.c: In function 'l2cache_enable': cpu.c:104: warning: implicit declaration of function 'get_cpu_rev' cpu.c:104: error: 'CPU_3XX_ES20' undeclared (first use in this function) cpu.c:104: error: (Each undeclared identifier is reported only once cpu.c:104: error: for each function it appears in.) cpu.c: At top level: cpu.c:129: warning: function declaration isn't a prototype cpu.c: In function 'l2cache_disable': cpu.c:134: error: 'CPU_3XX_ES20' undeclared (first use in this function) make[1]: *** [cpu.o] Error 1 2. After upper error was resolved, linking error occured. The definition PRM_RSTCTRL is also omap3 dependent. It is used in the cpu/arm_cortexa8/start.S, and defined in the include/asm-arm/arch-omap3/cpu.h /arm_cortexa8/s5pc100/libs5pc100.a lib_arm/libarm.a fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a fs/yaffs2/libyaffs2.a fs/ubifs/libubifs.a net/libnet.a disk/libdisk.a drivers/bios_emulator/libatibiosemu.a drivers/block/libblock.a drivers/dma/libdma.a drivers/fpga/libfpga.a drivers/gpio/libgpio.a drivers/hwmon/libhwmon.a drivers/i2c/libi2c.a drivers/input/libinput.a drivers/misc/libmisc.a drivers/mmc/libmmc.a drivers/mtd/libmtd.a drivers/mtd/nand/libnand.a drivers/mtd/nand_legacy/libnand_legacy.a drivers/mtd/onenand/libonenand.a drivers/mtd/ubi/libubi.a drivers/mtd/spi/libspi_flash.a drivers/net/libnet.a drivers/net/phy/libphy.a drivers/net/sk98lin/libsk98lin.a drivers/pci/libpci.a drivers/pcmcia/libpcmcia.a drivers/spi/libspi.a drivers/rtc/librtc.a drivers/serial/libserial.a drivers/twserial/libtws.a drivers/usb/gadget/libusb_gadget.a drivers/usb/host/libusb_host.a drivers/usb/musb/libusb_musb.a drivers/video/libvideo.a drivers/watchdog/libwatchdog.a common/libcommon.a libfdt/libfdt.a api/libapi.a post/libpost.a board/samsung/tickertape/libtickertape.a --end-group -L /opt/toolchains/arm-2007q3/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.1 -lgcc \ -Map u-boot.map -o u-boot cpu/arm_cortexa8/start.o: In function `rstctl': /ubuntu/archive/s5pc100/u-boot-arm/cpu/arm_cortexa8/start.S:514: undefined reference to `PRM_RSTCTRL' Thanks one more. Best regards, HeungJun, Kim(riverful) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Move L2-cache enable/disable function to soc dependent code
The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c.
Signed-off-by: HeungJun, Kim riverful@samsung.com
---
cpu/arm_cortexa8/cpu.c | 65 +
cpu/arm_cortexa8/omap3/Makefile|2 +-
cpu/arm_cortexa8/omap3/board.c |4 +-
cpu/arm_cortexa8/omap3/cache.c | 99
include/asm-arm/arch-omap3/sys_proto.h |2 +
5 files changed, 107 insertions(+), 65 deletions(-)
create mode 100644 cpu/arm_cortexa8/omap3/cache.c
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..209bbd0 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
+void l2_cache_disable(void);
#endif
static void cache_flush(void);
@@ -80,7 +80,7 @@ int cleanup_before_linux(void)
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
- l2cache_disable();
+ l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
@@ -89,71 +89,12 @@ int cleanup_before_linux(void)
asm(mcr p15, 0, %0, c7, c10, 4: :r(i));
#ifndef CONFIG_L2_OFF
- l2cache_enable();
+ l2_cache_enable();
#endif
return 0;
}
-void l2cache_enable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(orr r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-
-}
-
-void l2cache_disable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(bic %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(bic r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-}
-
static void cache_flush(void)
{
asm (mcr p15, 0, %0, c7, c5, 0: :r (0));
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index b96b3dd..f83036b 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
-COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o
+COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..26cb436 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -206,9 +206,9 @@ void s_init(void)
#endif
#ifdef CONFIG_L2_OFF
- l2cache_disable();
+ l2_cache_disable();
#else
- l2cache_enable();
+ l2_cache_enable();
#endif
/*
* Writing to AuxCR in U-boot using SMI for GP DEV
diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c
new file mode 100644
index 000..d195046
--- /dev/null
+++ b/cpu/arm_cortexa8/omap3/cache.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2009
+ * Samsung Electornics, HeungJun Kim
[U-Boot] [PATCH] change cpu.c under cpu/arm_cortexa8 dir to common code.
The cpu.c under cpu/arm_cortexa8 has a dependency of omap3.
The part of cache in cpu.c is moved in the omap3/board.c,
because the functions about controlling cache seems to be different with a lot
of processors.
Signed-off-by: root r...@riverbuntu.(none)
---
cpu/arm_cortexa8/cpu.c | 55 +
cpu/arm_cortexa8/omap3/board.c | 68
include/asm-arm/arch-omap3/sys_proto.h |3 +
3 files changed, 74 insertions(+), 52 deletions(-)
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..046a89e 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -97,64 +97,15 @@ int cleanup_before_linux(void)
void l2cache_enable()
{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(orr r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-
+ board_l2cache_enable();
}
void l2cache_disable()
{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(bic %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
-* GP Device ROM code API usage here
-* r12 = AUXCR Write function and r0 value
-*/
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(bic r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
+ board_l2cache_disable();
}
static void cache_flush(void)
{
- asm (mcr p15, 0, %0, c7, c5, 0: :r (0));
+ board_cache_flush();
}
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..a594fc9 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -52,6 +52,74 @@ static inline void delay(unsigned long loops)
}
/**
+ * Routine: board_l2cache_enable() / disable() / flush()
+ * Description: cache enable / disable / flush
+ */
+void board_l2cache_enable()
+{
+ unsigned long i;
+ volatile unsigned int j;
+
+ /* ES2 onwards we can disable/enable L2 ourselves */
+ if (get_cpu_rev() = CPU_3XX_ES20) {
+ __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
+ __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
+ __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
+ } else {
+ /* Save r0, r12 and restore them after usage */
+ __asm__ __volatile__(mov %0, r12:=r(j));
+ __asm__ __volatile__(mov %0, r0:=r(i));
+
+ /*
+* GP Device ROM code API usage here
+* r12 = AUXCR Write function and r0 value
+*/
+ __asm__ __volatile__(mov r12, #0x3);
+ __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
+ __asm__ __volatile__(orr r0, r0, #0x2);
+ /* SMI instruction to call ROM Code API */
+ __asm__ __volatile__(.word 0xE1600070);
+ __asm__ __volatile__(mov r0, %0:=r(i));
+ __asm__ __volatile__(mov r12, %0:=r(j));
+ }
+
+}
+
+void board_l2cache_disable()
+{
+ unsigned long i;
+ volatile unsigned int j;
+
+
Re: [U-Boot] [PATCH] change cpu.c under cpu/arm_cortexa8 dir to common code.
Sorry about wrong Signed-off-by.
Signed-off-by: riverful.kim riverful@samsung.com
Regards,
Kim, HeungJun
2009/5/27 Kim, Heung Jun river...@gmail.com:
The cpu.c under cpu/arm_cortexa8 has a dependency of omap3.
The part of cache in cpu.c is moved in the omap3/board.c,
because the functions about controlling cache seems to be different with a lot
of processors.
Signed-off-by: root r...@riverbuntu.(none)
---
cpu/arm_cortexa8/cpu.c | 55 +
cpu/arm_cortexa8/omap3/board.c | 68
include/asm-arm/arch-omap3/sys_proto.h | 3 +
3 files changed, 74 insertions(+), 52 deletions(-)
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..046a89e 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -97,64 +97,15 @@ int cleanup_before_linux(void)
void l2cache_enable()
{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(orr r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
-
+ board_l2cache_enable();
}
void l2cache_disable()
{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() = CPU_3XX_ES20) {
- __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
- __asm__ __volatile__(bic %0, %0, #0x2:=r(i));
- __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__(mov %0, r12:=r(j));
- __asm__ __volatile__(mov %0, r0:=r(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__(mov r12, #0x3);
- __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
- __asm__ __volatile__(bic r0, r0, #0x2);
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(.word 0xE1600070);
- __asm__ __volatile__(mov r0, %0:=r(i));
- __asm__ __volatile__(mov r12, %0:=r(j));
- }
+ board_l2cache_disable();
}
static void cache_flush(void)
{
- asm (mcr p15, 0, %0, c7, c5, 0: :r (0));
+ board_cache_flush();
}
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..a594fc9 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -52,6 +52,74 @@ static inline void delay(unsigned long loops)
}
/**
+ * Routine: board_l2cache_enable() / disable() / flush()
+ * Description: cache enable / disable / flush
+
*/
+void board_l2cache_enable()
+{
+ unsigned long i;
+ volatile unsigned int j;
+
+ /* ES2 onwards we can disable/enable L2 ourselves */
+ if (get_cpu_rev() = CPU_3XX_ES20) {
+ __asm__ __volatile__(mrc p15, 0, %0, c1, c0, 1:=r(i));
+ __asm__ __volatile__(orr %0, %0, #0x2:=r(i));
+ __asm__ __volatile__(mcr p15, 0, %0, c1, c0, 1:=r(i));
+ } else {
+ /* Save r0, r12 and restore them after usage */
+ __asm__ __volatile__(mov %0, r12:=r(j));
+ __asm__ __volatile__(mov %0, r0:=r(i));
+
+ /*
+ * GP Device ROM code API usage here
+ * r12 = AUXCR Write function and r0 value
+ */
+ __asm__ __volatile__(mov r12, #0x3);
+ __asm__ __volatile__(mrc p15, 0, r0, c1, c0, 1);
+ __asm__ __volatile__(orr r0, r0, #0x2);
+ /* SMI instruction to call ROM Code API
