Dear Wolfgang, I fixed the deficiencies like the following : http://lists.denx.de/pipermail/u-boot/2009-June/053534.html
And, I use git-format-patch. One more thing, I wanted to tell that this is the exact time in the unmatch-naming case, by the following thread. : http://lists.denx.de/pipermail/u-boot/2009-June/053533.html It's my fault that u don't understand my words :) BTW, Very thanks to review. Best Regards, riverful 2009/6/1 Kim, Heung Jun <[email protected]>: > CC: Dirk Behme <[email protected]> > Signed-off-by: HeungJun, Kim <[email protected]> > > --- > > The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved > to cpu/arm_cortexa8/omap3/cache.c. > > This patches fixes the First issue in the following > > http://lists.denx.de/pipermail/u-boot/2009-May/053433.html > > The Second issue is fixed by > > http://lists.denx.de/pipermail/u-boot/2009-May/053490.html > > cpu/arm_cortexa8/cpu.c | 68 +--------------------- > cpu/arm_cortexa8/omap3/Makefile | 2 +- > cpu/arm_cortexa8/omap3/board.c | 5 +- > cpu/arm_cortexa8/omap3/cache.c | 99 > ++++++++++++++++++++++++++++++++ > include/asm-arm/arch-omap3/sys_proto.h | 1 - > include/asm-arm/cache.h | 37 ++++++++++++ > 6 files changed, 143 insertions(+), 69 deletions(-) > create mode 100644 cpu/arm_cortexa8/omap3/cache.c > create mode 100644 include/asm-arm/cache.h > > diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c > index 3e1780b..96f42a9 100644 > --- a/cpu/arm_cortexa8/cpu.c > +++ b/cpu/arm_cortexa8/cpu.c > @@ -35,15 +35,12 @@ > #include <command.h> > #include <asm/arch/sys_proto.h> > #include <asm/system.h> > +#include <asm/cache.h> > > #ifdef CONFIG_USE_IRQ > DECLARE_GLOBAL_DATA_PTR; > #endif > > -#ifndef CONFIG_L2_OFF > -void l2cache_disable(void); > -#endif > - > static void cache_flush(void); > > int cpu_init(void) > @@ -80,7 +77,7 @@ int cleanup_before_linux(void) > > #ifndef CONFIG_L2_OFF > /* turn off L2 cache */ > - l2cache_disable(); > + l2_cache_disable(); > /* invalidate L2 cache also */ > v7_flush_dcache_all(get_device_type()); > #endif > @@ -89,71 +86,12 @@ int cleanup_before_linux(void) > asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); > > #ifndef CONFIG_L2_OFF > - l2cache_enable(); > + l2_cache_enable(); > #endif > > return 0; > } > > -void l2cache_enable() > -{ > - unsigned long i; > - volatile unsigned int j; > - > - /* ES2 onwards we can disable/enable L2 ourselves */ > - if (get_cpu_rev() >= CPU_3XX_ES20) { > - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); > - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); > - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); > - } else { > - /* Save r0, r12 and restore them after usage */ > - __asm__ __volatile__("mov %0, r12":"=r"(j)); > - __asm__ __volatile__("mov %0, r0":"=r"(i)); > - > - /* > - * GP Device ROM code API usage here > - * r12 = AUXCR Write function and r0 value > - */ > - __asm__ __volatile__("mov r12, #0x3"); > - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); > - __asm__ __volatile__("orr r0, r0, #0x2"); > - /* SMI instruction to call ROM Code API */ > - __asm__ __volatile__(".word 0xE1600070"); > - __asm__ __volatile__("mov r0, %0":"=r"(i)); > - __asm__ __volatile__("mov r12, %0":"=r"(j)); > - } > - > -} > - > -void l2cache_disable() > -{ > - unsigned long i; > - volatile unsigned int j; > - > - /* ES2 onwards we can disable/enable L2 ourselves */ > - if (get_cpu_rev() >= CPU_3XX_ES20) { > - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); > - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); > - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); > - } else { > - /* Save r0, r12 and restore them after usage */ > - __asm__ __volatile__("mov %0, r12":"=r"(j)); > - __asm__ __volatile__("mov %0, r0":"=r"(i)); > - > - /* > - * GP Device ROM code API usage here > - * r12 = AUXCR Write function and r0 value > - */ > - __asm__ __volatile__("mov r12, #0x3"); > - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); > - __asm__ __volatile__("bic r0, r0, #0x2"); > - /* SMI instruction to call ROM Code API */ > - __asm__ __volatile__(".word 0xE1600070"); > - __asm__ __volatile__("mov r0, %0":"=r"(i)); > - __asm__ __volatile__("mov r12, %0":"=r"(j)); > - } > -} > - > static void cache_flush(void) > { > asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); > diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile > index b96b3dd..f83036b 100644 > --- a/cpu/arm_cortexa8/omap3/Makefile > +++ b/cpu/arm_cortexa8/omap3/Makefile > @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk > LIB = $(obj)lib$(SOC).a > > SOBJS := lowlevel_init.o > -COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o > +COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o > > SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c > index 51d5cf6..439ea6a 100644 > --- a/cpu/arm_cortexa8/omap3/board.c > +++ b/cpu/arm_cortexa8/omap3/board.c > @@ -36,6 +36,7 @@ > #include <asm/io.h> > #include <asm/arch/sys_proto.h> > #include <asm/arch/mem.h> > +#include <asm/cache.h> > > extern omap3_sysinfo sysinfo; > > @@ -206,9 +207,9 @@ void s_init(void) > #endif > > #ifdef CONFIG_L2_OFF > - l2cache_disable(); > + l2_cache_disable(); > #else > - l2cache_enable(); > + l2_cache_enable(); > #endif > /* > * Writing to AuxCR in U-boot using SMI for GP DEV > diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c > new file mode 100644 > index 0000000..4b3e64a > --- /dev/null > +++ b/cpu/arm_cortexa8/omap3/cache.c > @@ -0,0 +1,99 @@ > +/* > + * (C) Copyright 2009 > + * Samsung Electornics, HeungJun Kim <[email protected]> > + * > + * (C) Copyright 2008 Texas Insturments > + * > + * (C) Copyright 2002 > + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> > + * Marius Groeger <[email protected]> > + * > + * (C) Copyright 2002 > + * Gary Jennejohn, DENX Software Engineering, <[email protected]> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +/* > + * L2 cache specific code > + */ > + > +#include <common.h> > +#include <command.h> > +#include <asm/cache.h> > + > +void l2_cache_enable() > +{ > + unsigned long i; > + volatile unsigned int j; > + > + /* ES2 onwards we can disable/enable L2 ourselves */ > + if (get_cpu_rev() >= CPU_3XX_ES20) { > + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); > + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); > + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); > + } else { > + /* Save r0, r12 and restore them after usage */ > + __asm__ __volatile__("mov %0, r12":"=r"(j)); > + __asm__ __volatile__("mov %0, r0":"=r"(i)); > + > + /* > + * GP Device ROM code API usage here > + * r12 = AUXCR Write function and r0 value > + */ > + __asm__ __volatile__("mov r12, #0x3"); > + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); > + __asm__ __volatile__("orr r0, r0, #0x2"); > + /* SMI instruction to call ROM Code API */ > + __asm__ __volatile__(".word 0xE1600070"); > + __asm__ __volatile__("mov r0, %0":"=r"(i)); > + __asm__ __volatile__("mov r12, %0":"=r"(j)); > + } > + > +} > + > +void l2_cache_disable() > +{ > + unsigned long i; > + volatile unsigned int j; > + > + /* ES2 onwards we can disable/enable L2 ourselves */ > + if (get_cpu_rev() >= CPU_3XX_ES20) { > + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); > + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); > + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); > + } else { > + /* Save r0, r12 and restore them after usage */ > + __asm__ __volatile__("mov %0, r12":"=r"(j)); > + __asm__ __volatile__("mov %0, r0":"=r"(i)); > + > + /* > + * GP Device ROM code API usage here > + * r12 = AUXCR Write function and r0 value > + */ > + __asm__ __volatile__("mov r12, #0x3"); > + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); > + __asm__ __volatile__("bic r0, r0, #0x2"); > + /* SMI instruction to call ROM Code API */ > + __asm__ __volatile__(".word 0xE1600070"); > + __asm__ __volatile__("mov r0, %0":"=r"(i)); > + __asm__ __volatile__("mov r12, %0":"=r"(j)); > + } > +} > + > diff --git a/include/asm-arm/arch-omap3/sys_proto.h > b/include/asm-arm/arch-omap3/sys_proto.h > index 7361d08..9314c7c 100644 > --- a/include/asm-arm/arch-omap3/sys_proto.h > +++ b/include/asm-arm/arch-omap3/sys_proto.h > @@ -50,7 +50,6 @@ u32 is_running_in_sdram(void); > u32 is_running_in_sram(void); > u32 is_running_in_flash(void); > u32 get_device_type(void); > -void l2cache_enable(void); > void secureworld_exit(void); > void setup_auxcr(void); > void try_unlock_memory(void); > diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h > new file mode 100644 > index 0000000..38ecd6b > --- /dev/null > +++ b/include/asm-arm/cache.h > @@ -0,0 +1,37 @@ > +/* > + * (C) Copyright 2008 Texas Insturments > + * > + * (C) Copyright 2002 > + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> > + * Marius Groeger <[email protected]> > + * > + * (C) Copyright 2002 > + * Gary Jennejohn, DENX Software Engineering, <[email protected]> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef _L2_CACHE_H_ > +#define _L2_CACHE_H_ > + > +void l2_cache_disable(); > +void l2_cache_enable(); > + > +#endif > + > -- > 1.5.6.3 > _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
