Re: [PATCH] riscv: fix the wrong swap value register

[Lukas Auer]

On Fri, 2020-11-13 at 20:47 +0900, Brad Kim wrote:

> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
> 
> Signed-off-by: Brad Kim 
> ---
>  arch/riscv/cpu/start.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Thanks for catching this issue!

Reviewed-by: Lukas Auer 

[PATCH] Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL"

[Lukas Auer]

The commit was added as a workaround required in QEMU when using BBL as
the supervisor binary interface (SBI) for Linux. We are now using
OpenSBI to provide the SBI, the workaround is therefore not required
anymore and can be removed.

This reverts commit 897206c5cc5c6ac0dc2ab851044e42baada3785b.

Signed-off-by: Lukas Auer 
---

 board/emulation/qemu-riscv/Kconfig  |  1 -
 board/emulation/qemu-riscv/qemu-riscv.c | 39 -
 2 files changed, 40 deletions(-)

diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 7ce12018e7..ad99b08b44 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -43,7 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_EXT4
imply CMD_FAT
imply BOARD_LATE_INIT
-   imply OF_BOARD_SETUP
imply SIFIVE_SERIAL
imply SMP
imply PCI
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c 
b/board/emulation/qemu-riscv/qemu-riscv.c
index cbce5ffe6e..c3f96988b1 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -52,45 +52,6 @@ int board_late_init(void)
return 0;
 }
 
-/*
- * QEMU specifies the location of Linux (supplied with the -kernel argument)
- * in the device tree using the riscv,kernel-start and riscv,kernel-end
- * properties. We currently rely on the SBI implementation of BBL to run
- * Linux and therefore embed Linux as payload in BBL. This causes an issue,
- * because BBL detects the kernel properties in the device tree and ignores
- * the Linux payload as a result. To work around this issue, we clear the
- * kernel properties before booting Linux.
- *
- * This workaround can be removed, once we do not require BBL for its SBI
- * implementation anymore.
- */
-int ft_board_setup(void *blob, bd_t *bd)
-{
-   int chosen_offset, ret;
-
-   chosen_offset = fdt_path_offset(blob, "/chosen");
-   if (chosen_offset < 0)
-   return 0;
-
-#ifdef CONFIG_ARCH_RV64I
-   ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-start", 0);
-#else
-   ret = fdt_setprop_u32(blob, chosen_offset, "riscv,kernel-start", 0);
-#endif
-   if (ret)
-   return ret;
-
-#ifdef CONFIG_ARCH_RV64I
-   ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-end", 0);
-#else
-   ret = fdt_setprop_u32(blob, chosen_offset, "riscv,kernel-end", 0);
-#endif
-   if (ret)
-   return ret;
-
-   return 0;
-}
-
 #ifdef CONFIG_SPL
 u32 spl_boot_device(void)
 {
-- 
2.25.2

Re: [PATCH 2/2] riscv: Avoid calling sbi_clear_ipi()

[Lukas Auer]

On Fri, 2020-03-06 at 00:44 -0800, Bin Meng wrote:
> There is no need for S-mode U-Boot to call sbi_clear_ipi() as it
> can be cleared directly from S-mode. This saves some cycles.
> 
> Signed-off-by: Bin Meng 
> ---
> 
>  arch/riscv/lib/sbi_ipi.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 

Reviewed-by: Lukas Auer 

Re: [PATCH 1/2] riscv: Fix sbi_remote_sfence_vma{,_asid}

[Lukas Auer]

On Fri, 2020-03-06 at 00:44 -0800, Bin Meng wrote:
> Currently sbi_remote_sfence_vma{,_asid} does not pass their arguments
> to SBI at all, which is semantically incorrect.
> 
> This keeps in sync with Linux kernel commit:
>   a21344dfc6ad: fix sbi_remote_sfence_vma{,_asid}
> 
> Signed-off-by: Bin Meng 
> ---
> 
>  arch/riscv/include/asm/sbi.h | 19 ---
>  1 file changed, 12 insertions(+), 7 deletions(-)
> 

Reviewed-by: Lukas Auer 

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

[Lukas Auer]

On Tue, 2020-03-03 at 16:57 -0500, Sean Anderson wrote:
> On 3/3/20 4:53 PM, Lukas Auer wrote:
> > On Mon, 2020-03-02 at 18:43 -0500, Sean Anderson wrote:
> > > On 3/2/20 6:17 PM, Lukas Auer wrote:
> > > > Don't move this. It is intended to be run before the IPI is cleared.
> > > 
> > > Hm, ok. I think I moved it to after because of the 'if (!smp_function)'
> > > check, but those two don't really need to be done together.
> > > 
> > 
> > Thanks! We had problems with code corruption in some situations,
> > because some secondary harts entered OpenSBI after the main hart while
> > OpenSBI expected all harts to be running OpenSBI by that time. Moving
> > this code block was part of the fix for this situation, see [1].
> > 
> > [1]: 
> > https://gitlab.denx.de/u-boot/u-boot/commit/90ae28143700bae4edd23930a7772899ad259058
> 
> Ah, this makes a lot more sense why it was located where it was.
> 
> > > > >   /*
> > > > >* Clear the IPI to acknowledge the request before jumping to 
> > > > > the
> > > > >* requested function.
> > > > >*/
> > > > >   ret = riscv_clear_ipi(hart);
> > > > >   if (ret) {
> > > > > - pr_err("Cannot clear IPI of hart %ld\n", hart);
> > > > > + pr_err("Cannot clear IPI of hart %ld (error %d)\n", 
> > > > > hart, ret);
> > > > >   return;
> > > > >   }
> > > > >  
> > > > > + __smp_mb();
> > > > > +
> > > > > + smp_function = (void (*)(ulong, ulong, 
> > > > > ulong))gd->arch.ipi[hart].addr;
> > > > > + /*
> > > > > +  * There may be an IPI raised before u-boot begins execution, 
> > > > > so check
> > > > > +  * to ensure we actually have a function to call.
> > > > > +  */
> > > > > + if (!smp_function)
> > > > > + return;
> > > > > + log_debug("hart = %lu func = %p\n", hart, smp_function);
> > > > 
> > > > The log messages might be corrupted if multiple harts are calling the
> > > > log function here. I have not looked into the details so this might not
> > > > be an issue. In that case it is fine to keep, otherwise please remove
> > > > it.
> > > 
> > > I ran into this problem a lot when debugging. I ended up implementing a
> > > spinlock around puts/putc. I agree it's probably better to remove this,
> > > but I worry that concurrency bugs will become much harder to track down
> > > without some kind of feedback. (This same criticism applies to the log
> > > message above as well).
> > > 
> > 
> > Especially with your changes, I hope we already have or will soon reach
> > a code robustness level where we won't have too many concurrency bugs
> > in the future. :)
> > Let's remove it for now until the logging backend can handle this
> > cleanly.
> 
> Ok. Should the error message above ("Cannot clear IPI of hart...") also
> be removed? I found it tended to corrupt the log output if it was ever
> triggered.
> 

Even though it's not ideal, we should keep it for now. Otherwise we
don't have a way to get notified about the error.

Thanks,
Lukas

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

[Lukas Auer]

On Mon, 2020-03-02 at 18:43 -0500, Sean Anderson wrote:
> On 3/2/20 6:17 PM, Lukas Auer wrote:
> > On Fri, 2020-02-28 at 16:05 -0500, Sean Anderson wrote:
> > 
> > > The IPI code could have race conditions in several places.
> > > * Several harts could race on the value of gd->arch->clint/plic
> > > * Non-boot harts could race with the main hart on the DM subsystem In
> > >   addition, if an IPI was pending when U-Boot started, it would cause the
> > >   IPI handler to jump to address 0.
> > > 
> > > To address these problems, a new function riscv_init_ipi is introduced. It
> > > is called once during arch_cpu_init_dm. Before this point, no riscv_*_ipi
> > > functions may be called. Access is synchronized by gd->arch->ipi_ready.
> > > 
> > > Signed-off-by: Sean Anderson 
> > > ---
> > > 
> > > Changes in v5:
> > > - New
> > > 
> > >  arch/riscv/cpu/cpu.c |  9 
> > >  arch/riscv/include/asm/global_data.h |  1 +
> > >  arch/riscv/include/asm/smp.h | 43 ++
> > >  arch/riscv/lib/andes_plic.c  | 34 +-
> > >  arch/riscv/lib/sbi_ipi.c |  5 ++
> > >  arch/riscv/lib/sifive_clint.c| 33 +-
> > >  arch/riscv/lib/smp.c | 68 
> > >  7 files changed, 101 insertions(+), 92 deletions(-)
> > > 
> > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > index e457f6acbf..a971ec8694 100644
> > > --- a/arch/riscv/cpu/cpu.c
> > > +++ b/arch/riscv/cpu/cpu.c
> > > @@ -96,6 +96,15 @@ int arch_cpu_init_dm(void)
> > >   csr_write(CSR_SATP, 0);
> > >   }
> > >  
> > > +#ifdef CONFIG_SMP
> > > + ret = riscv_init_ipi();
> > > + if (ret)
> > > + return ret;
> > > +
> > > + /* Atomically set a flag enabling IPI handling */
> > > + WRITE_ONCE(gd->arch.ipi_ready, 1);
> > > +#endif
> > > +
> > >   return 0;
> > >  }
> > >  
> > > diff --git a/arch/riscv/include/asm/global_data.h 
> > > b/arch/riscv/include/asm/global_data.h
> > > index 7276d9763f..b24f8fd2a7 100644
> > > --- a/arch/riscv/include/asm/global_data.h
> > > +++ b/arch/riscv/include/asm/global_data.h
> > > @@ -28,6 +28,7 @@ struct arch_global_data {
> > >  #endif
> > >  #ifdef CONFIG_SMP
> > >   struct ipi_data ipi[CONFIG_NR_CPUS];
> > > + long ipi_ready; /* Set after riscv_init_ipi is called */
> > >  #endif
> > >  #ifndef CONFIG_XIP
> > >   ulong available_harts;
> > > diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
> > > index 74de92ed13..1b428856b2 100644
> > > --- a/arch/riscv/include/asm/smp.h
> > > +++ b/arch/riscv/include/asm/smp.h
> > > @@ -51,4 +51,47 @@ void handle_ipi(ulong hart);
> > >   */
> > >  int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
> > >  
> > > +/**
> > > + * riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
> > > + *
> > > + * Platform code must provide this function. This function is called 
> > > once after
> > > + * the cpu driver is initialized. No other riscv_*_ipi() calls will be 
> > > made
> > > + * before this function is called.
> > > + *
> > > + * @return 0 if OK, -ve on error
> > > + */
> > > +int riscv_init_ipi(void);
> > > +
> > > +/**
> > > + * riscv_send_ipi() - Send inter-processor interrupt (IPI)
> > > + *
> > > + * Platform code must provide this function.
> > > + *
> > > + * @hart: Hart ID of receiving hart
> > > + * @return 0 if OK, -ve on error
> > > + */
> > > +int riscv_send_ipi(int hart);
> > > +
> > > +/**
> > > + * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
> > > + *
> > > + * Platform code must provide this function.
> > > + *
> > > + * @hart: Hart ID of hart to be cleared
> > > + * @return 0 if OK, -ve on error
> > > + */
> > > +int riscv_clear_ipi(int hart);
> > > +
> > > +/**
> > > + * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
> > > + *
> > > + * Platform code must provide this function.
> > > + *
> > > + * @hart: Hart ID of hart to be checked
> > > + * @pending: Pointer to va

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

[Lukas Auer]

On Fri, 2020-02-28 at 16:05 -0500, Sean Anderson wrote:

> The IPI code could have race conditions in several places.
> * Several harts could race on the value of gd->arch->clint/plic
> * Non-boot harts could race with the main hart on the DM subsystem In
>   addition, if an IPI was pending when U-Boot started, it would cause the
>   IPI handler to jump to address 0.
> 
> To address these problems, a new function riscv_init_ipi is introduced. It
> is called once during arch_cpu_init_dm. Before this point, no riscv_*_ipi
> functions may be called. Access is synchronized by gd->arch->ipi_ready.
> 
> Signed-off-by: Sean Anderson 
> ---
> 
> Changes in v5:
> - New
> 
>  arch/riscv/cpu/cpu.c |  9 
>  arch/riscv/include/asm/global_data.h |  1 +
>  arch/riscv/include/asm/smp.h | 43 ++
>  arch/riscv/lib/andes_plic.c  | 34 +-
>  arch/riscv/lib/sbi_ipi.c |  5 ++
>  arch/riscv/lib/sifive_clint.c| 33 +-
>  arch/riscv/lib/smp.c | 68 
>  7 files changed, 101 insertions(+), 92 deletions(-)
> 
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index e457f6acbf..a971ec8694 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -96,6 +96,15 @@ int arch_cpu_init_dm(void)
>   csr_write(CSR_SATP, 0);
>   }
>  
> +#ifdef CONFIG_SMP
> + ret = riscv_init_ipi();
> + if (ret)
> + return ret;
> +
> + /* Atomically set a flag enabling IPI handling */
> + WRITE_ONCE(gd->arch.ipi_ready, 1);
> +#endif
> +
>   return 0;
>  }
>  
> diff --git a/arch/riscv/include/asm/global_data.h 
> b/arch/riscv/include/asm/global_data.h
> index 7276d9763f..b24f8fd2a7 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -28,6 +28,7 @@ struct arch_global_data {
>  #endif
>  #ifdef CONFIG_SMP
>   struct ipi_data ipi[CONFIG_NR_CPUS];
> + long ipi_ready; /* Set after riscv_init_ipi is called */
>  #endif
>  #ifndef CONFIG_XIP
>   ulong available_harts;
> diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
> index 74de92ed13..1b428856b2 100644
> --- a/arch/riscv/include/asm/smp.h
> +++ b/arch/riscv/include/asm/smp.h
> @@ -51,4 +51,47 @@ void handle_ipi(ulong hart);
>   */
>  int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
>  
> +/**
> + * riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
> + *
> + * Platform code must provide this function. This function is called once 
> after
> + * the cpu driver is initialized. No other riscv_*_ipi() calls will be made
> + * before this function is called.
> + *
> + * @return 0 if OK, -ve on error
> + */
> +int riscv_init_ipi(void);
> +
> +/**
> + * riscv_send_ipi() - Send inter-processor interrupt (IPI)
> + *
> + * Platform code must provide this function.
> + *
> + * @hart: Hart ID of receiving hart
> + * @return 0 if OK, -ve on error
> + */
> +int riscv_send_ipi(int hart);
> +
> +/**
> + * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
> + *
> + * Platform code must provide this function.
> + *
> + * @hart: Hart ID of hart to be cleared
> + * @return 0 if OK, -ve on error
> + */
> +int riscv_clear_ipi(int hart);
> +
> +/**
> + * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
> + *
> + * Platform code must provide this function.
> + *
> + * @hart: Hart ID of hart to be checked
> + * @pending: Pointer to variable with result of the check,
> + *   1 if IPI is pending, 0 otherwise
> + * @return 0 if OK, -ve on error
> + */
> +int riscv_get_ipi(int hart, int *pending);
> +
>  #endif
> diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> index 20529ab3eb..8484f76386 100644
> --- a/arch/riscv/lib/andes_plic.c
> +++ b/arch/riscv/lib/andes_plic.c
> @@ -30,20 +30,6 @@
>  #define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
>  
>  DECLARE_GLOBAL_DATA_PTR;
> -static int init_plic(void);
> -
> -#define PLIC_BASE_GET(void)  \
> - do {\
> - long *ret;  \
> - \
> - if (!gd->arch.plic) {   \
> - ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
> - if (IS_ERR(ret))\
> - return PTR_ERR(ret);\
> - gd->arch.plic = ret;\
> - init_plic();\
> - }   \
> - } while (0)
>  
>  static int enable_ipi(int hart)
>  {
> @@ -93,13 +79,21 @@ static int init_plic(void)
>   return -ENODEV;
>  }
>  
> +int 

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

[Lukas Auer]

On Mon, 2020-03-02 at 10:43 -0500, Sean Anderson wrote:

> On 3/2/20 4:08 AM, Rick Chen wrote:
> > Hi Sean
> > 
> > > The IPI code could have race conditions in several places.
> > > * Several harts could race on the value of gd->arch->clint/plic
> > > * Non-boot harts could race with the main hart on the DM subsystem In
> > >   addition, if an IPI was pending when U-Boot started, it would cause the
> > >   IPI handler to jump to address 0.
> > > 
> > > To address these problems, a new function riscv_init_ipi is introduced. It
> > > is called once during arch_cpu_init_dm. Before this point, no riscv_*_ipi
> > > functions may be called. Access is synchronized by gd->arch->ipi_ready.
> > > 
> > > Signed-off-by: Sean Anderson 
> > > ---
> > > 
> > > Changes in v5:
> > > - New
> > > 
> > >  arch/riscv/cpu/cpu.c |  9 
> > >  arch/riscv/include/asm/global_data.h |  1 +
> > >  arch/riscv/include/asm/smp.h | 43 ++
> > >  arch/riscv/lib/andes_plic.c  | 34 +-
> > >  arch/riscv/lib/sbi_ipi.c |  5 ++
> > >  arch/riscv/lib/sifive_clint.c| 33 +-
> > >  arch/riscv/lib/smp.c | 68 
> > >  7 files changed, 101 insertions(+), 92 deletions(-)
> > > 
> > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > index e457f6acbf..a971ec8694 100644
> > > --- a/arch/riscv/cpu/cpu.c
> > > +++ b/arch/riscv/cpu/cpu.c
> > > @@ -96,6 +96,15 @@ int arch_cpu_init_dm(void)
> > > csr_write(CSR_SATP, 0);
> > > }
> > > 
> > > +#ifdef CONFIG_SMP
> > > +   ret = riscv_init_ipi();
> > > +   if (ret)
> > > +   return ret;
> > > +
> > > +   /* Atomically set a flag enabling IPI handling */
> > > +   WRITE_ONCE(gd->arch.ipi_ready, 1);
> > 
> > I think it shall not have race condition here.
> > Can you explain more detail why there will occur race condition ?
> > 
> > Hi Lukas
> > 
> > Do you have any comments ?
> > 
> > Thanks
> > Rick
> 
> On the K210, there may already be an IPI pending when U-Boot starts.
> (Perhaps the prior stage sends an IPI but does not clear it). As soon as
> interrupts are enabled, the hart then tries to call riscv_clear_ipi().
> Because the clint/plic has not yet been enabled, the clear_ipi function
> will try and bind/probe the device. This can have really nasty effects, since
> the boot hart is *also* trying to bind/probe devices.
> 
> In addition, a hart could end up trying to probe the clint/plic because
> it could receive the IPI before (from its perspective) gd->arch.clint
> (or plic) gets initialized.
> 

We did not have a problem with pending IPIs on other platforms. It
should suffice to clear SSIP / MSIP before enabling the interrupts.

> Aside from the above, I think the macro approach is a bit confusing,
> since it's unclear at first glance what function will be initializing
> the clint/plic. Given U-Boot's otherwise completely SMP-unsafe design, I
> think it's better to be explicit and conservative in these areas.
> 

I agree, the patch makes this more clear and helps make the code more
robust.

Thanks,
Lukas

Re: [PATCH v2 07/11] riscv: Add initial Sipeed Maix support

[Lukas Auer]

On Sun, 2020-01-26 at 20:09 -0500, Sean Anderson wrote:
> On 1/26/20 5:17 PM, Lukas Auer wrote:
> > Hi Sean,
> > 
> > 
> > On Wed, 2020-01-15 at 18:04 -0500, Sean Anderson wrote:
> > > The Sipeed Maix series is a collection of boards built around the RISC-V
> > > Kendryte K210 processor. This processor contains several peripherals to
> > > accelerate neural network processing and other "ai" tasks. This includes 
> > > a "KPU"
> > > neural network processor, an audio processor supporting beamforming 
> > > reception,
> > > and a digital video port supporting capture and output at VGA resolution. 
> > > Other
> > > peripherals include 8M of sram (accessible with and without caching);
> > > remappable pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a 
> > > DMA
> > > controller; and I2C, I2S, and SPI controllers. Maix peripherals vary, but
> > > include spi flash; on-board usb-serial bridges; ports for cameras, 
> > > displays, and
> > > sd cards; and ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 
> > > (bitm) is
> > > supported, but the boards are fairly similar.
> > > 
> > > Documentation for Maix boards is located at 
> > > <http://dl.sipeed.com/MAIX/HDK/>;;.
> > > Documentation for the Kendryte K210 is located at
> > > <https://kendryte.com/downloads/>;;. However, hardware details are rather 
> > > lacking,
> > > so most technical reference has been taken from the standalone sdk 
> > > located at
> > > <https://github.com/kendryte/kendryte-standalone-sdk>;;.
> > > 
> > > Signed-off-by: Sean Anderson 
> > 
> > This patch should be the last in the patch series, because it requires
> > all other patches in the series.
> 
> Ok, will reorder it for v3.
> 
> > > ---
> > > Changes for v2:
> > >   Select CONFIG_SYS_RISCV_NOCOUNTER.
> > >   Imply CONFIG_CLK_K210.
> > >   Remove spurious references to CONFIG_ARCH_K210.
> > >   Remove many configs from defconfig where the defaults were fine.
> > >   Add a few "not set" lines to suppress unneeded defaults.
> > >   Reduce pre-reloc malloc space, now that clocks initialization happens
> > >   later.
> > >   
> > >  arch/riscv/Kconfig |  4 ++
> > >  board/sipeed/maix/Kconfig  | 41 +
> > >  board/sipeed/maix/MAINTAINERS  | 13 +
> > >  board/sipeed/maix/Makefile |  5 ++
> > >  board/sipeed/maix/maix.c   |  9 +++
> > >  configs/sipeed_maix_bitm_defconfig | 93 ++
> > >  include/configs/sipeed-maix.h  | 19 ++
> > >  7 files changed, 184 insertions(+)
> > >  create mode 100644 board/sipeed/maix/Kconfig
> > >  create mode 100644 board/sipeed/maix/MAINTAINERS
> > >  create mode 100644 board/sipeed/maix/Makefile
> > >  create mode 100644 board/sipeed/maix/maix.c
> > >  create mode 100644 configs/sipeed_maix_bitm_defconfig
> > >  create mode 100644 include/configs/sipeed-maix.h
> > > 
> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > index 4f8c62dcff..4c62b8dd77 100644
> > > --- a/arch/riscv/Kconfig
> > > +++ b/arch/riscv/Kconfig
> > > @@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
> > >  config TARGET_SIFIVE_FU540
> > >   bool "Support SiFive FU540 Board"
> > >  
> > > +config TARGET_SIPEED_MAIX
> > > + bool "Support Sipeed Maix Board"
> > > +
> > >  endchoice
> > >  
> > >  config SYS_ICACHE_OFF
> > > @@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
> > >  source "board/emulation/qemu-riscv/Kconfig"
> > >  source "board/microchip/mpfs_icicle/Kconfig"
> > >  source "board/sifive/fu540/Kconfig"
> > > +source "board/sipeed/maix/Kconfig"
> > >  
> > >  # platform-specific options below
> > >  source "arch/riscv/cpu/ax25/Kconfig"
> > > diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
> > > new file mode 100644
> > > index 00..9259eb34aa
> > > --- /dev/null
> > > +++ b/board/sipeed/maix/Kconfig
> > > @@ -0,0 +1,41 @@
> > > +# SPDX-License-Identifier: GPL-2.0+
> > > +# Copyright (C) 2019 Sean Anderson 
> > > +
> > > +if TARGET_SIPEED_MAIX
> > > +
> > > +config SYS_BOARD
&g

Re: [PATCH v2 05/11] riscv: Add option to disable writes to mcounteren

[Lukas Auer]

On Sun, 2020-01-26 at 17:24 -0500, Sean Anderson wrote:
> On 1/26/20 5:09 PM, Lukas Auer wrote:
> > + Bin, Anup, Atish
> > 
> > 
> > On Wed, 2020-01-15 at 17:53 -0500, Sean Anderson wrote:
> > > On the kendryte k210, writes to mcounteren result in an illegal 
> > > instruction
> > > exception.
> > > 
> > > Signed-off-by: Sean Anderson 
> > > ---
> > > Changes for v2:
> > >  Moved forward in the patch series
> > > 
> > >  arch/riscv/Kconfig   | 3 +++
> > >  arch/riscv/cpu/cpu.c | 2 ++
> > >  2 files changed, 5 insertions(+)
> > > 
> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > index 9a7b0334c2..4f8c62dcff 100644
> > > --- a/arch/riscv/Kconfig
> > > +++ b/arch/riscv/Kconfig
> > > @@ -226,6 +226,9 @@ config XIP
> > > from a NOR flash memory without copying the code to ram.
> > > Say yes here if U-Boot boots from flash directly.
> > >  
> > > +config SYS_RISCV_NOCOUNTER
> > > + bool "Disable accesses to the mcounteren CSR"
> > > +
> > 
> > Can you rename this to something like RISCV_PRIV_1_9_1?
> > 
> > The k210 implements version 1.9.1 of the privileged spec (if I remember
> > correctly). The mcounteren CSR doesn't exist in that version and
> > therefore triggers the illegal instruction exception. By renaming the
> > config entry, it is clearer why the CSR is missing and is therefore not
> > accessed.
> 
> Thanks, I was not aware that the k210 was following a different spec
> when I made the change. For v3 I can add this functionality back using
> the old counter CSRs.
> 
> > I am not too familiar with the changes between the versions of the
> > spec. Are there other parts of the code we need to adapt?
> 
> From reading the changelog, most of the changes seem related to virtual
> memory, which doesn't apply to u-boot.
> 

Ok, great. Thanks for checking!

Regards,
Lukas

Re: [PATCH] riscv: Try to get cpu frequency from device tree

[Lukas Auer]

On Sun, 2020-01-26 at 13:20 -0500, Sean Anderson wrote:
> On 1/26/20 11:34 AM, Lukas Auer wrote:
> > Hi Sean,
> > Usually, ret is used as a variable name here. I think it would actually
> > make the code a bit nicer to read here, because the clock rate is not
> > read from variable err.
> 
> Hm, I chose err instead of ret since that variable is never the return
> value of the function. I can change that for v2 if you'd like.
> 

Makes sense. I think it's fine to keep it as is.

> > But that's just nit-picking. The patch looks good otherwise!
> > 
> > Reviewed-by: Lukas Auer 
> 
> 

Re: [PATCH v2 03/11] riscv: Add headers for asm/global_data.h

[Lukas Auer]

On Sun, 2020-01-26 at 17:12 -0500, Sean Anderson wrote:
> On 1/26/20 5:04 PM, Lukas Auer wrote:
> > asm/u-boot.h is usually included with common.h. ulong is defined in
> > linux/types.h (also included in common.h). It should be sufficient to
> > include common.h in your source files.
> > 
> > Thanks,
> > Lukas
> 
> So shouldn't asm/u-boot.h include common.h? Or is that header implicitly
> assumed to be included with every source file? Is that documented
> anywhere? To me, the "default" assumption is that any header should be
> able to be included anywhere and to pull in all of its own dependencies.
> 

You are right, it is not entirely correct like this. I think common.h
is assumed to always be included. Unfortunately, I don't know if this
is documented anywhere.

Thanks,
Lukas

Re: [PATCH v2 07/11] riscv: Add initial Sipeed Maix support

[Lukas Auer]

Hi Sean,


On Wed, 2020-01-15 at 18:04 -0500, Sean Anderson wrote:
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a 
> "KPU"
> neural network processor, an audio processor supporting beamforming reception,
> and a digital video port supporting capture and output at VGA resolution. 
> Other
> peripherals include 8M of sram (accessible with and without caching);
> remappable pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA
> controller; and I2C, I2S, and SPI controllers. Maix peripherals vary, but
> include spi flash; on-board usb-serial bridges; ports for cameras, displays, 
> and
> sd cards; and ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is
> supported, but the boards are fairly similar.
> 
> Documentation for Maix boards is located at ;.
> Documentation for the Kendryte K210 is located at
> ;. However, hardware details are rather 
> lacking,
> so most technical reference has been taken from the standalone sdk located at
> ;.
> 
> Signed-off-by: Sean Anderson 

This patch should be the last in the patch series, because it requires
all other patches in the series.

> ---
> Changes for v2:
>   Select CONFIG_SYS_RISCV_NOCOUNTER.
>   Imply CONFIG_CLK_K210.
>   Remove spurious references to CONFIG_ARCH_K210.
>   Remove many configs from defconfig where the defaults were fine.
>   Add a few "not set" lines to suppress unneeded defaults.
>   Reduce pre-reloc malloc space, now that clocks initialization happens
>   later.
>   
>  arch/riscv/Kconfig |  4 ++
>  board/sipeed/maix/Kconfig  | 41 +
>  board/sipeed/maix/MAINTAINERS  | 13 +
>  board/sipeed/maix/Makefile |  5 ++
>  board/sipeed/maix/maix.c   |  9 +++
>  configs/sipeed_maix_bitm_defconfig | 93 ++
>  include/configs/sipeed-maix.h  | 19 ++
>  7 files changed, 184 insertions(+)
>  create mode 100644 board/sipeed/maix/Kconfig
>  create mode 100644 board/sipeed/maix/MAINTAINERS
>  create mode 100644 board/sipeed/maix/Makefile
>  create mode 100644 board/sipeed/maix/maix.c
>  create mode 100644 configs/sipeed_maix_bitm_defconfig
>  create mode 100644 include/configs/sipeed-maix.h
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 4f8c62dcff..4c62b8dd77 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
>  config TARGET_SIFIVE_FU540
>   bool "Support SiFive FU540 Board"
>  
> +config TARGET_SIPEED_MAIX
> + bool "Support Sipeed Maix Board"
> +
>  endchoice
>  
>  config SYS_ICACHE_OFF
> @@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
>  source "board/emulation/qemu-riscv/Kconfig"
>  source "board/microchip/mpfs_icicle/Kconfig"
>  source "board/sifive/fu540/Kconfig"
> +source "board/sipeed/maix/Kconfig"
>  
>  # platform-specific options below
>  source "arch/riscv/cpu/ax25/Kconfig"
> diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
> new file mode 100644
> index 00..9259eb34aa
> --- /dev/null
> +++ b/board/sipeed/maix/Kconfig
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright (C) 2019 Sean Anderson 
> +
> +if TARGET_SIPEED_MAIX
> +
> +config SYS_BOARD
> + default "maix"
> +
> +config SYS_VENDOR
> + default "sipeed"
> +
> +config SYS_CPU
> + default "generic"
> +
> +config SYS_CONFIG_NAME
> + default "sipeed-maix"
> +
> +config SYS_TEXT_BASE
> + default 0x8000
> +
> +config NR_CPUS
> + default 2
> +
> +config NR_DRAM_BANKS
> + default 2
> +
> +config BOARD_SPECIFIC_OPTIONS
> + def_bool y
> + select GENERIC_RISCV
> + select DM_SERIAL
> + select SIFIVE_SERIAL
> + select ARCH_DEFAULT_RV64I
> + select ENV_IS_NOWHERE

ENV_IS_NOWHERE is automatically selected if no other environment
provider is available, so no need to include it here.
Also, why are you not using the SD card to store the environment?

> + select SYS_RISCV_NOCOUNTER
> + imply SIFIVE_CLINT
> + imply SPI
> + imply DM_GPIO
> + imply CMD_GPIO
> + imply SYS_NS16550
> + imply SYS_MALLOC_F
> +endif
> diff --git a/board/sipeed/maix/MAINTAINERS b/board/sipeed/maix/MAINTAINERS
> new file mode 100644
> index 00..217de45970
> --- /dev/null
> +++ b/board/sipeed/maix/MAINTAINERS
> @@ -0,0 +1,13 @@
> +Sipeed Maix BOARD
> +M:   Sean Anderson 
> +S:   Maintained
> +F:   arch/riscv/dts/k210.dtsi
> +F:   arch/riscv/dts/k210-maix-bit.dts
> +F:   arch/riscv/include/asm/k210_sysctl.h
> +F:   arch/riscv/lib/k210_sysctl.c
> +F:   board/sipeed/maix/
> +F:   configs/sipeed_maix_defconfig
> +F:   drivers/clk/kendryte/
> +F:   include/configs/sipeed-maix.h
> +F:   

Re: [PATCH v2 05/11] riscv: Add option to disable writes to mcounteren

[Lukas Auer]

+ Bin, Anup, Atish


On Wed, 2020-01-15 at 17:53 -0500, Sean Anderson wrote:
> On the kendryte k210, writes to mcounteren result in an illegal instruction
> exception.
> 
> Signed-off-by: Sean Anderson 
> ---
> Changes for v2:
>  Moved forward in the patch series
> 
>  arch/riscv/Kconfig   | 3 +++
>  arch/riscv/cpu/cpu.c | 2 ++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 9a7b0334c2..4f8c62dcff 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -226,6 +226,9 @@ config XIP
> from a NOR flash memory without copying the code to ram.
> Say yes here if U-Boot boots from flash directly.
>  
> +config SYS_RISCV_NOCOUNTER
> + bool "Disable accesses to the mcounteren CSR"
> +

Can you rename this to something like RISCV_PRIV_1_9_1?

The k210 implements version 1.9.1 of the privileged spec (if I remember
correctly). The mcounteren CSR doesn't exist in that version and
therefore triggers the illegal instruction exception. By renaming the
config entry, it is clearer why the CSR is missing and is therefore not
accessed.
I am not too familiar with the changes between the versions of the
spec. Are there other parts of the code we need to adapt?

Thanks,
Lukas

>  config STACK_SIZE_SHIFT
>   int
>   default 14
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index e457f6acbf..df9eae663c 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -89,7 +89,9 @@ int arch_cpu_init_dm(void)
>* Enable perf counters for cycle, time,
>* and instret counters only
>*/
> +#ifndef CONFIG_SYS_RISCV_NOCOUNTER
>   csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
> +#endif
>  
>   /* Disable paging */
>   if (supports_extension('s'))

Re: [PATCH v2 06/11] riscv: Fix incorrect cpu frequency on RV64

[Lukas Auer]

On Wed, 2020-01-15 at 17:55 -0500, Sean Anderson wrote:

> The riscv_cpu_get_info function does not always zero-out cpu_freq. This can
> cause spurious higher frequencies.
> 
> Signed-off-by Sean Anderson 
> ---
> Changes for v2:
>   New.
> 
>  drivers/cpu/riscv_cpu.c | 2 ++
>  1 file changed, 2 insertions(+)
> 

Reviewed-by: Lukas Auer 

Re: [PATCH v2 03/11] riscv: Add headers for asm/global_data.h

[Lukas Auer]

Hi Sean,


On Wed, 2020-01-15 at 17:50 -0500, Sean Anderson wrote:
> This header depended on bd_t and ulong, but did not include the appropriate
> headers.
> 
> Signed-off-by: Sean Anderson 
> ---
>  arch/riscv/include/asm/global_data.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/global_data.h 
> b/arch/riscv/include/asm/global_data.h
> index b74bd7e738..4f0c12b402 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -11,6 +11,8 @@
>  #define __ASM_GBL_DATA_H
>  
>  #include 
> +#include 
> +#include 
>  

asm/u-boot.h is usually included with common.h. ulong is defined in
linux/types.h (also included in common.h). It should be sufficient to
include common.h in your source files.

Thanks,
Lukas

Re: [PATCH] riscv: Try to get cpu frequency from device tree

[Lukas Auer]

Hi Sean,

On Fri, 2020-01-17 at 14:51 -0500, Sean Anderson wrote:
> Instead of always using the "clock-frequency" property to determine cpu
> frequency, try using a clock in "clocks" if it exists.
> 
> Signed-off-by Sean Anderson 
> ---
> This patch depends on <https://patchwork.ozlabs.org/patch/1223933/>;.
> 
>  drivers/cpu/riscv_cpu.c | 16 +++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
> index 1e32bb5678..280c9de376 100644
> --- a/drivers/cpu/riscv_cpu.c
> +++ b/drivers/cpu/riscv_cpu.c
> @@ -3,6 +3,7 @@
>   * Copyright (C) 2018, Bin Meng 
>   */
>  
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -27,11 +28,24 @@ static int riscv_cpu_get_desc(struct udevice *dev, char 
> *buf, int size)
>  
>  static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
>  {
> + int err;
> + struct clk clk;
>   const char *mmu;
>  
>   /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */
>   info->cpu_freq = 0;
> - dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
> +
> + /* First try getting the frequency from the assigned clock */
> + err = clk_get_by_index(dev, 0, );

Usually, ret is used as a variable name here. I think it would actually
make the code a bit nicer to read here, because the clock rate is not
read from variable err.

But that's just nit-picking. The patch looks good otherwise!

Reviewed-by: Lukas Auer 

> + if (!err) {
> + err = clk_get_rate();
> + if (!IS_ERR_VALUE(err))
> + info->cpu_freq = err;
> + clk_free();
> + }
> +
> + if (!info->cpu_freq)
> + dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
>  
>   mmu = dev_read_string(dev, "mmu-type");
>   if (!mmu)

Re: [PATCH 3/3] riscv: sifive: fu540: add SPL configuration

[Lukas Auer]

On Tue, 2020-01-14 at 23:12 -0600, Troy Benjegerdes wrote:
> > On Jan 13, 2020, at 4:31 PM, Lukas Auer  wrote:
> > 
> > +Troy
> > 
> > On Mon, 2020-01-13 at 14:32 +, Pragnesh Patel wrote:
> > > > > > +#include 
> > > > > > +
> > > > > > +u32 DENALI_PHY_DATA[1215] = {
> > > > > > +   DENALI_PHY_00_DATA, DENALI_PHY_01_DATA,
> > > > > DENALI_PHY_02_DATA,
> > > > > > +   DENALI_PHY_03_DATA, DENALI_PHY_04_DATA,
> > > > > DENALI_PHY_05_DATA,
> > > > > > +   DENALI_PHY_06_DATA, DENALI_PHY_07_DATA,
> > > > > DENALI_PHY_08_DATA,
> > > > > 
> > > > > Can this handle to write separate driver for ram like drivers/ram ?
> > > 
> > > We can add DM driver for RAM later. Right now, I want to get U-boot SPL 
> > > running for FU540.
> > 
> > Troy was working on a DM RAM driver that, from a first glance, already
> > looked good [1]. What is the status of the driver, can it be used here?
> > 
> > [1]: 
> > https://github.com/sifive/u-boot/blob/sandbox/drivers/ram/sifive/sdram_denali.c
> 
> It was unfortunately only a first attempt, and I never got it working.
> 
> I am hoping that someone else has time to pick it up and complete the work.
> 

Ah ok, that would have been great. It is already a very good start and
seems to be close to being complete. Perhaps it is just a matter of
debugging the code.

At the moment the driver is hard to find. It might therefore be a good
idea to post it somewhere for discussion, though I am not sure what the
best way / place of doing that is.

> Are there any other SoCs we know of besides RockChip that use this
> controller and have some sort of open boot firmware and/or U-boot support?
> 

I am not aware of any, but also don't have a good overview of what's
available.

Re: [PATCH 3/3] riscv: sifive: fu540: add SPL configuration

[Lukas Auer]

+Troy

On Mon, 2020-01-13 at 14:32 +, Pragnesh Patel wrote:
> > > > +#include 
> > > > +
> > > > +u32 DENALI_PHY_DATA[1215] = {
> > > > +   DENALI_PHY_00_DATA, DENALI_PHY_01_DATA,
> > > DENALI_PHY_02_DATA,
> > > > +   DENALI_PHY_03_DATA, DENALI_PHY_04_DATA,
> > > DENALI_PHY_05_DATA,
> > > > +   DENALI_PHY_06_DATA, DENALI_PHY_07_DATA,
> > > DENALI_PHY_08_DATA,
> > > 
> > > Can this handle to write separate driver for ram like drivers/ram ?
> 
> We can add DM driver for RAM later. Right now, I want to get U-boot SPL 
> running for FU540.

Troy was working on a DM RAM driver that, from a first glance, already
looked good [1]. What is the status of the driver, can it be used here?

[1]: 
https://github.com/sifive/u-boot/blob/sandbox/drivers/ram/sifive/sdram_denali.c

[PATCH v2 0/4] Fixes for RISC-V U-Boot SPL / OpenSBI boot flow

[Lukas Auer]

Rick's recent patch series, which adds support for U-Boot SPL to the
Andes platform, brought several problems of the current U-Boot SPL boot
flow on RISC-V to light. Discussion on the relevant parts starts at [1].

The problem showed itself in the form of code corruption. At start,
OpenSBI relocates itself to its link address. This allows it to be
loaded independently of the link address. In the case that the link
address ranges of U-Boot SPL and OpenSBI overlap, code corruption occurs
if the relocation starts while some harts are still running U-Boot SPL.
This series prevents this problem by specifying the hart that performs
the relocation and then making sure that it is the last hart to enter
OpenSBI, allowing relocation to be completed safely. A recent version of
OpenSBI is required for the changes to work.

This patch series resolves the problems associated with the use case of
overlapping link address ranges. However, it is still recommended to
select non-overlapping ranges for U-Boot SPL and OpenSBI.

[1]: https://lists.denx.de/pipermail/u-boot/2019-November/389385.html

Changes in v2:
- Use the pending register instead of the claim register in the Andes
PLIC implementation

Lukas Auer (4):
  spl: opensbi: specify main hart as preferred boot hart
  riscv: add functions for reading the IPI status
  riscv: add option to wait for ack from secondary harts in smp
functions
  spl: opensbi: wait for ack from secondary harts before entering
OpenSBI

 arch/riscv/cpu/start.S|  2 ++
 arch/riscv/include/asm/smp.h  |  3 ++-
 arch/riscv/lib/andes_plic.c   | 11 +
 arch/riscv/lib/bootm.c|  2 +-
 arch/riscv/lib/sbi_ipi.c  | 11 +
 arch/riscv/lib/sifive_clint.c |  9 
 arch/riscv/lib/smp.c  | 43 +++
 arch/riscv/lib/spl.c  |  2 +-
 common/spl/spl_opensbi.c  | 13 ++-
 include/opensbi.h | 18 ++-
 10 files changed, 100 insertions(+), 14 deletions(-)

-- 
2.21.0

[PATCH v2 3/4] riscv: add option to wait for ack from secondary harts in smp functions

[Lukas Auer]

Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.

As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.

Signed-off-by: Lukas Auer 
Reviewed-by: Rick Chen 
Tested-by: Rick Chen 
Reviewed-by: Anup Patel 
---

Changes in v2: None

 arch/riscv/cpu/start.S   |  2 ++
 arch/riscv/include/asm/smp.h |  3 ++-
 arch/riscv/lib/bootm.c   |  2 +-
 arch/riscv/lib/smp.c | 31 ++-
 arch/riscv/lib/spl.c |  2 +-
 common/spl/spl_opensbi.c |  2 +-
 6 files changed, 29 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 0a2ce6d691..60631638dd 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -197,6 +197,7 @@ spl_secondary_hart_stack_gd_setup:
la  a0, secondary_hart_relocate
mv  a1, s0
mv  a2, s0
+   mv  a3, zero
jal smp_call_function
 
/* hang if relocation of secondary harts has failed */
@@ -337,6 +338,7 @@ relocate_secondary_harts:
 
mv  a1, s2
mv  a2, s3
+   mv  a3, zero
jal smp_call_function
 
/* hang if relocation of secondary harts has failed */
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index bc863fdbaf..74de92ed13 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -46,8 +46,9 @@ void handle_ipi(ulong hart);
  * @addr: Address of function
  * @arg0: First argument of function
  * @arg1: Second argument of function
+ * @wait: Wait for harts to acknowledge request
  * @return 0 if OK, -ve on error
  */
-int smp_call_function(ulong addr, ulong arg0, ulong arg1);
+int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
 
 #endif
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index efbd3e23e7..e96137a50c 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -99,7 +99,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
 #ifdef CONFIG_SMP
ret = smp_call_function(images->ep,
-   (ulong)images->ft_addr, 0);
+   (ulong)images->ft_addr, 0, 0);
if (ret)
hang();
 #endif
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 188a7e34bd..17adb35730 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -44,11 +44,11 @@ extern int riscv_clear_ipi(int hart);
  */
 extern int riscv_get_ipi(int hart, int *pending);
 
-static int send_ipi_many(struct ipi_data *ipi)
+static int send_ipi_many(struct ipi_data *ipi, int wait)
 {
ofnode node, cpus;
u32 reg;
-   int ret;
+   int ret, pending;
 
cpus = ofnode_path("/cpus");
if (!ofnode_valid(cpus)) {
@@ -91,6 +91,15 @@ static int send_ipi_many(struct ipi_data *ipi)
pr_err("Cannot send IPI to hart %d\n", reg);
return ret;
}
+
+   if (wait) {
+   pending = 1;
+   while (pending) {
+   ret = riscv_get_ipi(reg, );
+   if (ret)
+   return ret;
+   }
+   }
}
 
return 0;
@@ -104,21 +113,25 @@ void handle_ipi(ulong hart)
if (hart >= CONFIG_NR_CPUS)
return;
 
+   __smp_mb();
+
+   smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
+   invalidate_icache_all();
+
+   /*
+* Clear the IPI to acknowledge the request before jumping to the
+* requested function.
+*/
ret = riscv_clear_ipi(hart);
if (ret) {
pr_err("Cannot clear IPI of hart %ld\n", hart);
return;
}
 
-   __smp_mb();
-
-   smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
-   invalidate_icache_all();
-
smp_function(hart, gd->arch.ipi[hart].arg0, gd->arch.ipi[hart].arg1);
 }
 
-int smp_call_function(ulong addr, ulong arg0, ulong arg1)
+int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait)
 {
int ret = 0;
struct ipi_data ipi;
@@ -127,7 +140,7 @@ int smp_call_fun

[PATCH v2 4/4] spl: opensbi: wait for ack from secondary harts before entering OpenSBI

[Lukas Auer]

At the start, OpenSBI relocates itself to its link address. If the link
address ranges of U-Boot SPL and OpenSBI overlap, the relocation can
lead to code corruption if a hart is still running U-Boot SPL during
relocation. To avoid this problem, the main hart is specified as the
preferred boot hart to perform the relocation. This fixes the code
corruption problems based on the assumption that since the main hart
schedules the secondary harts to enter OpenSBI, it will be the last to
enter OpenSBI. However it was reported that this assumption is not
always correct.

To make sure the assumption always holds true, wait for all secondary
harts to acknowledge the call-function request before entering OpenSBI
on the main hart.

Reported-by: Rick Chen 
Signed-off-by: Lukas Auer 
Reviewed-by: Rick Chen 
Tested-by: Rick Chen 
Reviewed-by: Anup Patel 
---

Changes in v2: None

 common/spl/spl_opensbi.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 58bf2468ce..6404373eca 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -76,9 +76,19 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image)
invalidate_icache_all();
 
 #ifdef CONFIG_SMP
+   /*
+* Start OpenSBI on all secondary harts and wait for acknowledgment.
+*
+* OpenSBI first relocates itself to its link address. This is done by
+* the main hart. To make sure no hart is still running U-Boot SPL
+* during relocation, we wait for all secondary harts to acknowledge
+* the call-function request before entering OpenSBI on the main hart.
+* Otherwise, code corruption can occur if the link address ranges of
+* U-Boot SPL and OpenSBI overlap.
+*/
ret = smp_call_function((ulong)spl_image->entry_point,
(ulong)spl_image->fdt_addr,
-   (ulong)_info, 0);
+   (ulong)_info, 1);
if (ret)
hang();
 #endif
-- 
2.21.0

[PATCH v2 2/4] riscv: add functions for reading the IPI status

[Lukas Auer]

Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).

Signed-off-by: Lukas Auer 
---

Changes in v2:
- Use the pending register instead of the claim register in the Andes
PLIC implementation

 arch/riscv/lib/andes_plic.c   | 11 +++
 arch/riscv/lib/sbi_ipi.c  | 11 +++
 arch/riscv/lib/sifive_clint.c |  9 +
 arch/riscv/lib/smp.c  | 12 
 4 files changed, 43 insertions(+)

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 28568e4e2b..42bda9b759 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -114,6 +114,17 @@ int riscv_clear_ipi(int hart)
return 0;
 }
 
+int riscv_get_ipi(int hart, int *pending)
+{
+   PLIC_BASE_GET();
+
+   *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
+gd->arch.boot_hart));
+   *pending = !!(*pending & SEND_IPI_TO_HART(hart));
+
+   return 0;
+}
+
 static const struct udevice_id andes_plic_ids[] = {
{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
{ }
diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
index 170346da68..9a698ce74e 100644
--- a/arch/riscv/lib/sbi_ipi.c
+++ b/arch/riscv/lib/sbi_ipi.c
@@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart)
 
return 0;
 }
+
+int riscv_get_ipi(int hart, int *pending)
+{
+   /*
+* The SBI does not support reading the IPI status. We always return 0
+* to indicate that no IPI is pending.
+*/
+   *pending = 0;
+
+   return 0;
+}
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index d24e0d585b..d7899d16d7 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart)
return 0;
 }
 
+int riscv_get_ipi(int hart, int *pending)
+{
+   CLINT_BASE_GET();
+
+   *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
+
+   return 0;
+}
+
 static const struct udevice_id sifive_clint_ids[] = {
{ .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
{ }
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 705437862a..188a7e34bd 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -32,6 +32,18 @@ extern int riscv_send_ipi(int hart);
  */
 extern int riscv_clear_ipi(int hart);
 
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ *   1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+extern int riscv_get_ipi(int hart, int *pending);
+
 static int send_ipi_many(struct ipi_data *ipi)
 {
ofnode node, cpus;
-- 
2.21.0

[PATCH v2 1/4] spl: opensbi: specify main hart as preferred boot hart

[Lukas Auer]

OpenSBI uses a relocation lottery to determine the hart to relocate
OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart
schedules the secondary harts to enter OpenSBI before doing so itself.
One of the secondary harts will therefore always be the winner of the
relocation lottery. This is problematic if the link address ranges of
OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore
overwrite U-Boot SPL while some harts may still run it, leading to code
corruption.

Avoid this problem by specifying the main hart as the preferred boot
hart to perform the OpenSBI relocation. The main hart will be the last
hart to enter OpenSBI, relocation can therefore occur safely.

The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC
info structure. The header file include/opensbi.h is synchronized with
include/sbi/fw_dynamic.h from the OpenSBI project to update the info
structure. The header file is recent as of commit
7a13beb21326 ("firmware: Add preferred boot HART field in struct
fw_dynamic_info").

Reported-by: Rick Chen 
Suggested-by: Anup Patel 
Signed-off-by: Lukas Auer 
Reviewed-by: Rick Chen 
Tested-by: Rick Chen 
Reviewed-by: Anup Patel 
---

Changes in v2: None

 common/spl/spl_opensbi.c |  1 +
 include/opensbi.h| 18 +-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 2345f949f0..fed41b1e66 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -70,6 +70,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image)
opensbi_info.next_addr = uboot_entry;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = SBI_SCRATCH_NO_BOOT_PRINTS;
+   opensbi_info.boot_hart = gd->arch.boot_hart;
 
opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point;
invalidate_icache_all();
diff --git a/include/opensbi.h b/include/opensbi.h
index 9f1d62e7dd..d812cc8ccd 100644
--- a/include/opensbi.h
+++ b/include/opensbi.h
@@ -11,7 +11,7 @@
 #define FW_DYNAMIC_INFO_MAGIC_VALUE0x4942534f
 
 /** Maximum supported info version */
-#define FW_DYNAMIC_INFO_VERSION0x1
+#define FW_DYNAMIC_INFO_VERSION0x2
 
 /** Possible next mode values */
 #define FW_DYNAMIC_INFO_NEXT_MODE_U0x0
@@ -35,6 +35,22 @@ struct fw_dynamic_info {
unsigned long next_mode;
/** Options for OpenSBI library */
unsigned long options;
+   /**
+* Preferred boot HART id
+*
+* It is possible that the previous booting stage uses same link
+* address as the FW_DYNAMIC firmware. In this case, the relocation
+* lottery mechanism can potentially overwrite the previous booting
+* stage while other HARTs are still running in the previous booting
+* stage leading to boot-time crash. To avoid this boot-time crash,
+* the previous booting stage can specify last HART that will jump
+* to the FW_DYNAMIC firmware as the preferred boot HART.
+*
+* To avoid specifying a preferred boot HART, the previous booting
+* stage can set it to -1UL which will force the FW_DYNAMIC firmware
+* to use the relocation lottery mechanism.
+*/
+   unsigned long boot_hart;
 } __packed;
 
 #endif
-- 
2.21.0

[PATCH 1/4] spl: opensbi: specify main hart as preferred boot hart

[Lukas Auer]

OpenSBI uses a relocation lottery to determine the hart to relocate
OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart
schedules the secondary harts to enter OpenSBI before doing so itself.
One of the secondary harts will therefore always be the winner of the
relocation lottery. This is problematic if the link address ranges of
OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore
overwrite U-Boot SPL while some harts may still run it, leading to code
corruption.

Avoid this problem by specifying the main hart as the preferred boot
hart to perform the OpenSBI relocation. The main hart will be the last
hart to enter OpenSBI, relocation can therefore occur safely.

The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC
info structure. The header file include/opensbi.h is synchronized with
include/sbi/fw_dynamic.h from the OpenSBI project to update the info
structure. The header file is recent as of commit
7a13beb21326 ("firmware: Add preferred boot HART field in struct
fw_dynamic_info").

Reported-by: Rick Chen 
Suggested-by: Anup Patel 
Signed-off-by: Lukas Auer 
---

 common/spl/spl_opensbi.c |  1 +
 include/opensbi.h| 18 +-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index a6b4480ed2..79ee7edcf9 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -69,6 +69,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image)
opensbi_info.next_addr = uboot_entry;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = SBI_SCRATCH_NO_BOOT_PRINTS;
+   opensbi_info.boot_hart = gd->arch.boot_hart;
 
opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point;
invalidate_icache_all();
diff --git a/include/opensbi.h b/include/opensbi.h
index 9f1d62e7dd..d812cc8ccd 100644
--- a/include/opensbi.h
+++ b/include/opensbi.h
@@ -11,7 +11,7 @@
 #define FW_DYNAMIC_INFO_MAGIC_VALUE0x4942534f
 
 /** Maximum supported info version */
-#define FW_DYNAMIC_INFO_VERSION0x1
+#define FW_DYNAMIC_INFO_VERSION0x2
 
 /** Possible next mode values */
 #define FW_DYNAMIC_INFO_NEXT_MODE_U0x0
@@ -35,6 +35,22 @@ struct fw_dynamic_info {
unsigned long next_mode;
/** Options for OpenSBI library */
unsigned long options;
+   /**
+* Preferred boot HART id
+*
+* It is possible that the previous booting stage uses same link
+* address as the FW_DYNAMIC firmware. In this case, the relocation
+* lottery mechanism can potentially overwrite the previous booting
+* stage while other HARTs are still running in the previous booting
+* stage leading to boot-time crash. To avoid this boot-time crash,
+* the previous booting stage can specify last HART that will jump
+* to the FW_DYNAMIC firmware as the preferred boot HART.
+*
+* To avoid specifying a preferred boot HART, the previous booting
+* stage can set it to -1UL which will force the FW_DYNAMIC firmware
+* to use the relocation lottery mechanism.
+*/
+   unsigned long boot_hart;
 } __packed;
 
 #endif
-- 
2.21.0

[PATCH 2/4] riscv: add functions for reading the IPI status

[Lukas Auer]

Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).

Signed-off-by: Lukas Auer 
---
I do not have access to the datasheet of the Andes PLIC. The
riscv_clear_ipi() implementation seems to read the IPI status from the
claim register before writing back the results to clear them. Based on
this, I also used the claim register. Rick, please let me know if that
is ok or if I should use the pending register instead.

 arch/riscv/lib/andes_plic.c   |  9 +
 arch/riscv/lib/sbi_ipi.c  | 11 +++
 arch/riscv/lib/sifive_clint.c |  9 +
 arch/riscv/lib/smp.c  | 12 
 4 files changed, 41 insertions(+)

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 28568e4e2b..731ac3a148 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -114,6 +114,15 @@ int riscv_clear_ipi(int hart)
return 0;
 }
 
+int riscv_get_ipi(int hart, int *pending)
+{
+   PLIC_BASE_GET();
+
+   *pending = !!readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+
+   return 0;
+}
+
 static const struct udevice_id andes_plic_ids[] = {
{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
{ }
diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
index 170346da68..9a698ce74e 100644
--- a/arch/riscv/lib/sbi_ipi.c
+++ b/arch/riscv/lib/sbi_ipi.c
@@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart)
 
return 0;
 }
+
+int riscv_get_ipi(int hart, int *pending)
+{
+   /*
+* The SBI does not support reading the IPI status. We always return 0
+* to indicate that no IPI is pending.
+*/
+   *pending = 0;
+
+   return 0;
+}
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index d24e0d585b..d7899d16d7 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart)
return 0;
 }
 
+int riscv_get_ipi(int hart, int *pending)
+{
+   CLINT_BASE_GET();
+
+   *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
+
+   return 0;
+}
+
 static const struct udevice_id sifive_clint_ids[] = {
{ .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
{ }
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index cc66f15567..6ff0de4b74 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -31,6 +31,18 @@ extern int riscv_send_ipi(int hart);
  */
 extern int riscv_clear_ipi(int hart);
 
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ *   1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+extern int riscv_get_ipi(int hart, int *pending);
+
 static int send_ipi_many(struct ipi_data *ipi)
 {
ofnode node, cpus;
-- 
2.21.0

[PATCH 0/4] Fixes for RISC-V U-Boot SPL / OpenSBI boot flow

[Lukas Auer]

Rick's recent patch series, which adds support for U-Boot SPL to the
Andes platform, brought several problems of the current U-Boot SPL boot
flow on RISC-V to light. Discussion on the relevant parts starts at [1].

The problem showed itself in the form of code corruption. At start,
OpenSBI relocates itself to its link address. This allows it to be
loaded independently of the link address. In the case that the link
address ranges of U-Boot SPL and OpenSBI overlap, code corruption occurs
if the relocation starts while some harts are still running U-Boot SPL.
This series prevents this problem by specifying the hart that performs
the relocation and then making sure that it is the last hart to enter
OpenSBI, allowing relocation to be completed safely. A recent version of
OpenSBI is required for the changes to work.

This patch series resolves the problems associated with the use case of
overlapping link address ranges. However, it is still recommended to
select non-overlapping ranges for U-Boot SPL and OpenSBI.

[1]: https://lists.denx.de/pipermail/u-boot/2019-November/389385.html


Lukas Auer (4):
  spl: opensbi: specify main hart as preferred boot hart
  riscv: add functions for reading the IPI status
  riscv: add option to wait for ack from secondary harts in smp
functions
  spl: opensbi: wait for ack from secondary harts before entering
OpenSBI

 arch/riscv/cpu/start.S|  2 ++
 arch/riscv/include/asm/smp.h  |  3 ++-
 arch/riscv/lib/andes_plic.c   |  9 
 arch/riscv/lib/bootm.c|  2 +-
 arch/riscv/lib/sbi_ipi.c  | 11 +
 arch/riscv/lib/sifive_clint.c |  9 
 arch/riscv/lib/smp.c  | 43 +++
 arch/riscv/lib/spl.c  |  2 +-
 common/spl/spl_opensbi.c  | 13 ++-
 include/opensbi.h | 18 ++-
 10 files changed, 98 insertions(+), 14 deletions(-)

-- 
2.21.0

[PATCH 4/4] spl: opensbi: wait for ack from secondary harts before entering OpenSBI

[Lukas Auer]

At the start, OpenSBI relocates itself to its link address. If the link
address ranges of U-Boot SPL and OpenSBI overlap, the relocation can
lead to code corruption if a hart is still running U-Boot SPL during
relocation. To avoid this problem, the main hart is specified as the
preferred boot hart to perform the relocation. This fixes the code
corruption problems based on the assumption that since the main hart
schedules the secondary harts to enter OpenSBI, it will be the last to
enter OpenSBI. However it was reported that this assumption is not
always correct.

To make sure the assumption always holds true, wait for all secondary
harts to acknowledge the call-function request before entering OpenSBI
on the main hart.

Reported-by: Rick Chen 
Signed-off-by: Lukas Auer 
---

 common/spl/spl_opensbi.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 91a411a3db..5ea59d423f 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -75,9 +75,19 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image)
invalidate_icache_all();
 
 #ifdef CONFIG_SMP
+   /*
+* Start OpenSBI on all secondary harts and wait for acknowledgment.
+*
+* OpenSBI first relocates itself to its link address. This is done by
+* the main hart. To make sure no hart is still running U-Boot SPL
+* during relocation, we wait for all secondary harts to acknowledge
+* the call-function request before entering OpenSBI on the main hart.
+* Otherwise, code corruption can occur if the link address ranges of
+* U-Boot SPL and OpenSBI overlap.
+*/
ret = smp_call_function((ulong)spl_image->entry_point,
(ulong)spl_image->fdt_addr,
-   (ulong)_info, 0);
+   (ulong)_info, 1);
if (ret)
hang();
 #endif
-- 
2.21.0

[PATCH 3/4] riscv: add option to wait for ack from secondary harts in smp functions

[Lukas Auer]

Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.

As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.

Signed-off-by: Lukas Auer 
---

 arch/riscv/cpu/start.S   |  2 ++
 arch/riscv/include/asm/smp.h |  3 ++-
 arch/riscv/lib/bootm.c   |  2 +-
 arch/riscv/lib/smp.c | 31 ++-
 arch/riscv/lib/spl.c |  2 +-
 common/spl/spl_opensbi.c |  2 +-
 6 files changed, 29 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 0a2ce6d691..60631638dd 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -197,6 +197,7 @@ spl_secondary_hart_stack_gd_setup:
la  a0, secondary_hart_relocate
mv  a1, s0
mv  a2, s0
+   mv  a3, zero
jal smp_call_function
 
/* hang if relocation of secondary harts has failed */
@@ -337,6 +338,7 @@ relocate_secondary_harts:
 
mv  a1, s2
mv  a2, s3
+   mv  a3, zero
jal smp_call_function
 
/* hang if relocation of secondary harts has failed */
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index bc863fdbaf..74de92ed13 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -46,8 +46,9 @@ void handle_ipi(ulong hart);
  * @addr: Address of function
  * @arg0: First argument of function
  * @arg1: Second argument of function
+ * @wait: Wait for harts to acknowledge request
  * @return 0 if OK, -ve on error
  */
-int smp_call_function(ulong addr, ulong arg0, ulong arg1);
+int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
 
 #endif
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index efbd3e23e7..e96137a50c 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -99,7 +99,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
 #ifdef CONFIG_SMP
ret = smp_call_function(images->ep,
-   (ulong)images->ft_addr, 0);
+   (ulong)images->ft_addr, 0, 0);
if (ret)
hang();
 #endif
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 6ff0de4b74..d575e904c2 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -43,11 +43,11 @@ extern int riscv_clear_ipi(int hart);
  */
 extern int riscv_get_ipi(int hart, int *pending);
 
-static int send_ipi_many(struct ipi_data *ipi)
+static int send_ipi_many(struct ipi_data *ipi, int wait)
 {
ofnode node, cpus;
u32 reg;
-   int ret;
+   int ret, pending;
 
cpus = ofnode_path("/cpus");
if (!ofnode_valid(cpus)) {
@@ -90,6 +90,15 @@ static int send_ipi_many(struct ipi_data *ipi)
pr_err("Cannot send IPI to hart %d\n", reg);
return ret;
}
+
+   if (wait) {
+   pending = 1;
+   while (pending) {
+   ret = riscv_get_ipi(reg, );
+   if (ret)
+   return ret;
+   }
+   }
}
 
return 0;
@@ -103,21 +112,25 @@ void handle_ipi(ulong hart)
if (hart >= CONFIG_NR_CPUS)
return;
 
+   __smp_mb();
+
+   smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
+   invalidate_icache_all();
+
+   /*
+* Clear the IPI to acknowledge the request before jumping to the
+* requested function.
+*/
ret = riscv_clear_ipi(hart);
if (ret) {
pr_err("Cannot clear IPI of hart %ld\n", hart);
return;
}
 
-   __smp_mb();
-
-   smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
-   invalidate_icache_all();
-
smp_function(hart, gd->arch.ipi[hart].arg0, gd->arch.ipi[hart].arg1);
 }
 
-int smp_call_function(ulong addr, ulong arg0, ulong arg1)
+int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait)
 {
int ret = 0;
struct ipi_data ipi;
@@ -126,7 +139,7 @@ int smp_call_function(ulong addr, ulong arg0, ulong arg1)
ipi.arg0 = arg0;
ipi.arg1 = arg1;
 

[U-Boot] [PATCH] riscv: increase stack size to avoid a stack overflow during distro boot

[Lukas Auer]

This fixes a problem, where booting Linux using distro boot will
sometimes lead to an invalid instruction exception on the main hart. The
secondary harts are not affected and boot Linux successfully. The root
cause of this problem is a stack overflow on the main hart.

With distro boot, the current default stack size of 8KiB on RISC-V is
not sufficient and will cause a stack overflow. The stacks are allocated
sequentially. In the case of a stack overflow the stack of the main hart
can reach into that of another hart and be corrupted.

The stack overflow previously did not cause any problems, because only
stack frames, which are not used anymore since the hart enters Linux,
were corrupted. Starting with GCC 9, the stack usage has decreased. Now,
only the most recent stack frame overflows into the stack of a secondary
hart and is corrupted. The illegal instruction exception is caused by
the secondary hart overwriting the return address in the stack frame of
the main hart with an address that does not include valid code.

Increase the default stack size of each hart to 16KiB to avoid this
problem.

Reported-by: Aurelien Jarno 
Signed-off-by: Lukas Auer 
Tested-by: David Abdurachmanov 
Tested-by: Aurelien Jarno 
---

 arch/riscv/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 01975d7c60..85e15ebffa 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -224,7 +224,7 @@ config XIP
 
 config STACK_SIZE_SHIFT
int
-   default 13
+   default 14
 
 config SPL_LDSCRIPT
default "arch/riscv/cpu/u-boot-spl.lds"
-- 
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[U-Boot] [RESEND PATCH v4 06/11] riscv: add SPL support

[Lukas Auer]

U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
jumping to the image and via OpenSBI firmware. In the first case, both
U-Boot SPL and proper must be compiled to run in the same privilege
mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
mode and U-Boot proper for supervisor mode.

To be able to use SPL, boards have to provide a supported SPL boot
device.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/Kconfig   |  6 +++
 arch/riscv/Kconfig |  3 ++
 arch/riscv/cpu/generic/Kconfig |  3 ++
 arch/riscv/cpu/start.S | 23 +-
 arch/riscv/cpu/u-boot-spl.lds  | 82 ++
 arch/riscv/include/asm/spl.h   | 31 +
 arch/riscv/lib/Makefile|  1 +
 arch/riscv/lib/spl.c   | 48 
 8 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100644 arch/riscv/lib/spl.c

diff --git a/arch/Kconfig b/arch/Kconfig
index e510e971b4..f4ada57909 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -76,6 +76,12 @@ config RISCV
imply MTD
imply TIMER
imply CMD_DM
+   imply SPL_DM
+   imply SPL_OF_CONTROL
+   imply SPL_LIBCOMMON_SUPPORT
+   imply SPL_LIBGENERIC_SUPPORT
+   imply SPL_SERIAL_SUPPORT
+   imply SPL_TIMER
 
 config SANDBOX
bool "Sandbox"
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b8d01ba8e1..01975d7c60 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -226,4 +226,7 @@ config STACK_SIZE_SHIFT
int
default 13
 
+config SPL_LDSCRIPT
+   default "arch/riscv/cpu/u-boot-spl.lds"
+
 endmenu
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index b7552f539f..b2cb155d6d 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -10,3 +10,6 @@ config GENERIC_RISCV
imply RISCV_TIMER
imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply CMD_CPU
+   imply SPL_CPU_SUPPORT
+   imply SPL_OPENSBI
+   imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index e82ee9e365..66c603906d 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -75,7 +75,11 @@ _start:
  */
 call_board_init_f:
li  t0, -16
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+   li  t1, CONFIG_SPL_STACK
+#else
li  t1, CONFIG_SYS_INIT_SP_ADDR
+#endif
and sp, t1, t0  /* force 16 byte alignment */
 
 call_board_init_f_0:
@@ -159,7 +163,24 @@ wait_for_gd_init:
 
mv  a0, zero/* a0 <-- boot_flags = 0 */
la  t5, board_init_f
-   jr  t5  /* jump to board_init_f() */
+   jalrt5  /* jump to board_init_f() */
+
+#ifdef CONFIG_SPL_BUILD
+spl_clear_bss:
+   la  t0, __bss_start
+   la  t1, __bss_end
+   beq t0, t1, spl_call_board_init_r
+
+spl_clear_bss_loop:
+   SREGzero, 0(t0)
+   addit0, t0, REGBYTES
+   bne t0, t1, spl_clear_bss_loop
+
+spl_call_board_init_r:
+   mv  a0, zero
+   mv  a1, zero
+   jal board_init_r
+#endif
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
new file mode 100644
index 00..32255d58de
--- /dev/null
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/riscv/cpu/u-boot.lds, which is
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ *
+ * and arch/mips/cpu/u-boot-spl.lds.
+ */
+MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+   LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+   . = ALIGN(4);
+   .text : {
+   arch/riscv/cpu/start.o  (.text)
+   *(.text*)
+   } > .spl_mem
+
+   . = ALIGN(4);
+   .rodata : {
+   *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+   } > .spl_mem
+
+   . = ALIGN(4);
+   .data : {
+   *(.data*)
+   } > .spl_mem
+   . = ALIGN(4);
+
+   .got : {
+   __got_start = .;
+   *(.got.plt) *(.got)
+   __got_end = .;
+   } > .spl_mem
+
+   . = ALIGN(4);
+
+   .u_boot_list : {
+   KEEP(*(SORT(.u_boot_list*)));
+   } > .spl_mem
+
+   . = ALIGN(4);
+
+   .binman_sym_table : {
+   __binman_sym_start = .;
+   KEEP(*(SORT(.binman_sym*)));
+ 

[U-Boot] [RESEND PATCH v4 11/11] doc: update QEMU RISC-V documentation

[Lukas Auer]

The available defconfigs for RISC-V QEMU have changed. We now have
configurations to compile U-Boot to run in supervisor mode and for
U-Boot SPL. Update the QEMU RISC-V documentation to reflect these
changes.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3:
- Add note on minimum version of OpenSBI

Changes in v2:
- Rebase on master and format documentation as reStructuredText

 doc/board/emulation/qemu-riscv.rst | 60 +-
 1 file changed, 59 insertions(+), 1 deletion(-)

diff --git a/doc/board/emulation/qemu-riscv.rst 
b/doc/board/emulation/qemu-riscv.rst
index 214833496b..fe7505e201 100644
--- a/doc/board/emulation/qemu-riscv.rst
+++ b/doc/board/emulation/qemu-riscv.rst
@@ -6,7 +6,8 @@ QEMU RISC-V
 
 QEMU for RISC-V supports a special 'virt' machine designed for emulation and
 virtualization purposes. This document describes how to run U-Boot under it.
-Both 32-bit 64-bit targets are supported.
+Both 32-bit and 64-bit targets are supported, running in either machine or
+supervisor mode.
 
 The QEMU virt machine models a generic RISC-V virtual machine with support for
 the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
@@ -28,6 +29,11 @@ Set the CROSS_COMPILE environment variable as usual, and run:
 make qemu-riscv64_defconfig
 make
 
+This will compile U-Boot for machine mode. To build supervisor mode binaries,
+use the configurations qemu-riscv32_smode_defconfig and
+qemu-riscv64_smode_defconfig instead. Note that U-Boot running in supervisor
+mode requires a supervisor binary interface (SBI), such as RISC-V OpenSBI.
+
 Running U-Boot
 --
 The minimal QEMU command line to get U-Boot up and running is:
@@ -46,4 +52,56 @@ parameter. For example, '-m 2G' creates 2GiB memory for the 
target,
 and the memory node in the embedded DTB created by QEMU reflects
 the new setting.
 
+For instructions on how to run U-Boot in supervisor mode on QEMU
+with OpenSBI, see the documentation available with OpenSBI:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
 These have been tested in QEMU 3.0.0.
+
+Running U-Boot SPL
+--
+In the default SPL configuration, U-Boot SPL starts in machine mode. U-Boot
+proper and OpenSBI (FW_DYNAMIC firmware) are bundled as FIT image and made
+available to U-Boot SPL. Both are then loaded by U-Boot SPL and the location
+of U-Boot proper is passed to OpenSBI. After initialization, U-Boot proper is
+started in supervisor mode by OpenSBI.
+
+OpenSBI must be compiled before compiling U-Boot. Version 0.4 and higher is
+supported by U-Boot. Clone the OpenSBI repository and run the following 
command.
+
+.. code-block:: console
+
+git clone https://github.com/riscv/opensbi.git
+cd opensbi
+make PLATFORM=qemu/virt
+
+See the OpenSBI documentation for full details:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
+To make the FW_DYNAMIC binary 
(build/platform/qemu/virt/firmware/fw_dynamic.bin)
+available to U-Boot, either copy it into the U-Boot root directory or specify
+its location with the OPENSBI environment variable. Afterwards, compile U-Boot
+with the following commands.
+
+- For 32-bit RISC-V::
+
+make qemu-riscv32_spl_defconfig
+make
+
+- For 64-bit RISC-V::
+
+make qemu-riscv64_spl_defconfig
+make
+
+The minimal QEMU commands to run U-Boot SPL in both 32-bit and 64-bit
+configurations are:
+
+- For 32-bit RISC-V::
+
+qemu-system-riscv32 -nographic -machine virt -kernel spl/u-boot-spl \
+-device loader,file=u-boot.itb,addr=0x8020
+
+- For 64-bit RISC-V::
+
+qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
+-device loader,file=u-boot.itb,addr=0x8020
-- 
2.21.0

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[U-Boot] [RESEND PATCH v4 09/11] riscv: set default FIT generator script and build target for SPL builds

[Lukas Auer]

Now that we have a generic FIT generator script for RISC-V, set it as
the default. To also build the FIT image by default, set the default
build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Kconfig b/Kconfig
index d2eb744e70..a78dd59a79 100644
--- a/Kconfig
+++ b/Kconfig
@@ -250,7 +250,8 @@ config BUILD_TARGET
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
-   default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI)
+   default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || \
+   ARCH_SUNXI || RISCV)
default "u-boot.kwb" if KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
help
@@ -463,6 +464,7 @@ config SPL_FIT_GENERATOR
depends on SPL_FIT
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && 
ARCH_ROCKCHIP
+   default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
  Specifies a (platform specific) script file to generate the FIT
  source file used to build the U-Boot FIT image file. This gets
-- 
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[U-Boot] [RESEND PATCH v4 08/11] riscv: add a generic FIT generator script

[Lukas Auer]

Add a generic FIT generator script for RISC-V to generate images
containing U-Boot, OpenSBI FW_DYNAMIC firmware, and optionally one or
more device trees. The location of the OpenSBI firmware binary can be
specified with the OPENSBI environment variable. By default, it is
assumed to be "fw_dynamic.bin", located in the U-Boot top-level. Device
trees are passed as arguments to the generator script. A separate
configuration entry is created for each device tree.

The load addresses of U-Boot and OpenSBI are parsed from the U-Boot
configuration. They can be overwritten with the UBOOT_LOAD_ADDR and
OPENSBI_LOAD_ADDR environment variables.

The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh)
and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator
scripts.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/riscv/lib/mkimage_fit_opensbi.sh | 100 ++
 1 file changed, 100 insertions(+)
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh

diff --git a/arch/riscv/lib/mkimage_fit_opensbi.sh 
b/arch/riscv/lib/mkimage_fit_opensbi.sh
new file mode 100755
index 00..d6f95e5bfd
--- /dev/null
+++ b/arch/riscv/lib/mkimage_fit_opensbi.sh
@@ -0,0 +1,100 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for RISC-V boards with OpenSBI
+# and, optionally, multiple device trees (given on the command line).
+#
+# usage: $0 [ [&2
+   OPENSBI=/dev/null
+fi
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+   description = "Configuration to load OpenSBI before U-Boot";
+
+   images {
+   uboot {
+   description = "U-Boot";
+   data = /incbin/("u-boot-nodtb.bin");
+   type = "standalone";
+   os = "U-Boot";
+   arch = "riscv";
+   compression = "none";
+   load = <$UBOOT_LOAD_ADDR>;
+   };
+   opensbi {
+   description = "RISC-V OpenSBI";
+   data = /incbin/("$OPENSBI");
+   type = "firmware";
+   os = "opensbi";
+   arch = "riscv";
+   compression = "none";
+   load = <$OPENSBI_LOAD_ADDR>;
+   entry = <$OPENSBI_LOAD_ADDR>;
+   };
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+   cat << __FDT_IMAGE_EOF
+   fdt_$cnt {
+   description = "$(basename $dtname .dtb)";
+   data = /incbin/("$dtname");
+   type = "flat_dt";
+   compression = "none";
+   };
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+   };
+   configurations {
+   default = "config_1";
+
+__CONF_HEADER_EOF
+
+if [ $# -eq 0 ]; then
+cat << __CONF_SECTION_EOF
+   config_1 {
+   description = "U-Boot FIT";
+   firmware = "opensbi";
+   loadables = "uboot";
+   };
+__CONF_SECTION_EOF
+else
+cnt=1
+for dtname in $*
+do
+cat << __CONF_SECTION_EOF
+   config_$cnt {
+   description = "$(basename $dtname .dtb)";
+   firmware = "opensbi";
+   loadables = "uboot";
+   fdt = "fdt_$cnt";
+   };
+__CONF_SECTION_EOF
+cnt=$((cnt+1))
+done
+fi
+
+cat << __ITS_EOF
+   };
+};
+__ITS_EOF
-- 
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[U-Boot] [RESEND PATCH v4 05/11] spl: support booting via RISC-V OpenSBI

[Lukas Auer]

RISC-V OpenSBI is an open-source implementation of the RISC-V Supervisor
Binary Interface (SBI) specification. It is required by Linux and U-Boot
running in supervisor mode. This patch adds support for booting via the
OpenSBI FW_DYNAMIC firmware. It supports OpenSBI version 0.4 and higher.

In this configuration, U-Boot SPL starts in machine mode. After loading
OpenSBI and U-Boot proper, it will start OpenSBI. All necessary
parameters are generated by U-Boot SPL and are passed to OpenSBI. U-Boot
proper is started in supervisor mode by OpenSBI. Support for OpenSBI is
enabled with CONFIG_SPL_OPENSBI. An additional configuration entry,
CONFIG_SPL_OPENSBI_LOAD_ADDR, is used to specify the load address of the
OpenSBI firmware binary. It is not used directly in U-Boot and instead
is intended to make the value available to scripts such as FIT
configuration generators.

The header file include/opensbi.h is based on header files from the
OpenSBI project. They are recent, as of commit bae54f764570 ("firmware:
Add fw_dynamic firmware").

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3:
- Update commit message to include minimum version of OpenSBI

Changes in v2: None

 common/image.c   |  1 +
 common/spl/Kconfig   | 17 
 common/spl/Makefile  |  1 +
 common/spl/spl.c |  6 +++
 common/spl/spl_opensbi.c | 85 
 include/image.h  |  1 +
 include/opensbi.h| 40 +++
 include/spl.h|  5 +++
 8 files changed, 156 insertions(+)
 create mode 100644 common/spl/spl_opensbi.c
 create mode 100644 include/opensbi.h

diff --git a/common/image.c b/common/image.c
index 84e859a30f..645584b5ba 100644
--- a/common/image.c
+++ b/common/image.c
@@ -132,6 +132,7 @@ static const table_entry_t uimage_os[] = {
 #if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC)
{   IH_OS_OPENRTOS, "openrtos", "OpenRTOS", },
 #endif
+   {   IH_OS_OPENSBI,  "opensbi",  "RISC-V OpenSBI",   },
 
{   -1, "", "", },
 };
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 630491699c..a819387cab 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1146,6 +1146,23 @@ config SPL_OPTEE
  OP-TEE is an open source Trusted OS  which is loaded by SPL.
  More detail at: https://github.com/OP-TEE/optee_os
 
+config SPL_OPENSBI
+   bool "Support RISC-V OpenSBI"
+   depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE
+   help
+ OpenSBI is an open-source implementation of the RISC-V Supervisor 
Binary
+ Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC
+ firmware. It is loaded and started by U-Boot SPL.
+
+ More details are available at https://github.com/riscv/opensbi and
+ https://github.com/riscv/riscv-sbi-doc
+
+config SPL_OPENSBI_LOAD_ADDR
+   hex "OpenSBI load address"
+   depends on SPL_OPENSBI
+   help
+ Load address of the OpenSBI binary.
+
 config TPL
bool
depends on SUPPORT_TPL
diff --git a/common/spl/Makefile b/common/spl/Makefile
index d28de692dd..5ce6f4ae48 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
 obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
+obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o
 obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
 obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
 obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 2c696f2a79..8c9415bedf 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -659,6 +659,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
(void *)spl_image.entry_point);
break;
 #endif
+#if CONFIG_IS_ENABLED(OPENSBI)
+   case IH_OS_OPENSBI:
+   debug("Jumping to U-Boot via RISC-V OpenSBI\n");
+   spl_invoke_opensbi(_image);
+   break;
+#endif
 #ifdef CONFIG_SPL_OS_BOOT
case IH_OS_LINUX:
debug("Jumping to Linux\n");
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
new file mode 100644
index 00..a6b4480ed2
--- /dev/null
+++ b/common/spl/spl_opensbi.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer 
+ *
+ * Based on common/spl/spl_atf.c
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct fw_dynamic_info opensbi_info;
+
+static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+{

[U-Boot] [RESEND PATCH v4 07/11] riscv: support SPL stack and global data relocation

[Lukas Auer]

To support relocation of the stack and global data on RISC-V, the
secondary harts must be notified of the change using IPIs. We can reuse
the hart relocation code for this purpose. It uses global data to store
the new stack pointer and global data pointer for the secondary harts.
This means that we cannot update the global data pointer of the main
hart in spl_relocate_stack_gd(), because the secondary harts have not
yet been relocated at this point. It is updated after the secondary
harts have been notified.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/riscv/cpu/start.S | 35 ++-
 common/spl/spl.c   |  2 +-
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 66c603906d..b15209d623 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -169,13 +169,46 @@ wait_for_gd_init:
 spl_clear_bss:
la  t0, __bss_start
la  t1, __bss_end
-   beq t0, t1, spl_call_board_init_r
+   beq t0, t1, spl_stack_gd_setup
 
 spl_clear_bss_loop:
SREGzero, 0(t0)
addit0, t0, REGBYTES
bne t0, t1, spl_clear_bss_loop
 
+spl_stack_gd_setup:
+   jal spl_relocate_stack_gd
+
+   /* skip setup if we did not relocate */
+   beqza0, spl_call_board_init_r
+   mv  s0, a0
+
+   /* setup stack on main hart */
+#ifdef CONFIG_SMP
+   /* tp: hart id */
+   sllit0, tp, CONFIG_STACK_SIZE_SHIFT
+   sub sp, s0, t0
+#else
+   mv  sp, s0
+#endif
+
+   /* set new stack and global data pointer on secondary harts */
+spl_secondary_hart_stack_gd_setup:
+   la  a0, secondary_hart_relocate
+   mv  a1, s0
+   mv  a2, s0
+   jal smp_call_function
+
+   /* hang if relocation of secondary harts has failed */
+   beqza0, 1f
+   mv  a1, a0
+   la  a0, secondary_harts_relocation_error
+   jal printf
+   jal hang
+
+   /* set new global data pointer on main hart */
+1: mv  gp, s0
+
 spl_call_board_init_r:
mv  a0, zero
mv  a1, zero
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 8c9415bedf..082fa2bd94 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -781,7 +781,7 @@ ulong spl_relocate_stack_gd(void)
 #if CONFIG_IS_ENABLED(DM)
dm_fixup_for_gd_move(new_gd);
 #endif
-#if !defined(CONFIG_ARM)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_RISCV)
gd = new_gd;
 #endif
return ptr;
-- 
2.21.0

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[U-Boot] [RESEND PATCH v4 10/11] riscv: qemu: add SPL configuration

[Lukas Auer]

Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
configurations are meant to help the development of SPL on RISC-V.

The configurations enable RAM as the only SPL boot device. Images must
be loaded at address 0x8020. In the default boot flow, U-Boot SPL
starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
then started in supervisor mode by OpenSBI.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3:
- Rebase on u-boot/master

Changes in v2: None

 board/emulation/qemu-riscv/Kconfig  | 10 ++
 board/emulation/qemu-riscv/MAINTAINERS  |  2 ++
 board/emulation/qemu-riscv/qemu-riscv.c | 17 +
 configs/qemu-riscv32_spl_defconfig  | 11 +++
 configs/qemu-riscv64_spl_defconfig  | 12 
 include/configs/qemu-riscv.h| 14 ++
 6 files changed, 66 insertions(+)
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig

diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 6cc7c31dc6..1928d6dda0 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -13,13 +13,21 @@ config SYS_CONFIG_NAME
default "qemu-riscv"
 
 config SYS_TEXT_BASE
+   default 0x8120 if SPL
default 0x8000 if !RISCV_SMODE
default 0x8020 if RISCV_SMODE && ARCH_RV64I
default 0x8040 if RISCV_SMODE && ARCH_RV32I
 
+config SPL_TEXT_BASE
+   default 0x8000
+
+config SPL_OPENSBI_LOAD_ADDR
+   default 0x8100
+
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+   select SUPPORT_SPL
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
@@ -43,5 +51,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_PCI
imply E1000
imply NVME
+   imply SPL_RAM_SUPPORT
+   imply SPL_RAM_DEVICE
 
 endif
diff --git a/board/emulation/qemu-riscv/MAINTAINERS 
b/board/emulation/qemu-riscv/MAINTAINERS
index c701c83d77..78969ed6bd 100644
--- a/board/emulation/qemu-riscv/MAINTAINERS
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -5,5 +5,7 @@ F:  board/emulation/qemu-riscv/
 F: include/configs/qemu-riscv.h
 F: configs/qemu-riscv32_defconfig
 F: configs/qemu-riscv32_smode_defconfig
+F: configs/qemu-riscv32_spl_defconfig
 F: configs/qemu-riscv64_defconfig
 F: configs/qemu-riscv64_smode_defconfig
+F: configs/qemu-riscv64_spl_defconfig
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c 
b/board/emulation/qemu-riscv/qemu-riscv.c
index 49e304f7eb..37d48d04f2 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -88,3 +89,19 @@ int ft_board_setup(void *blob, bd_t *bd)
 
return 0;
 }
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+   /* RISC-V QEMU only supports RAM as SPL boot device */
+   return BOOT_DEVICE_RAM;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   /* boot using first FIT config */
+   return 0;
+}
+#endif
diff --git a/configs/qemu-riscv32_spl_defconfig 
b/configs/qemu-riscv32_spl_defconfig
new file mode 100644
index 00..78e755b36a
--- /dev/null
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_spl_defconfig 
b/configs/qemu-riscv64_spl_defconfig
new file mode 100644
index 00..a3f5e29d58
--- /dev/null
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -0,0 +1,12 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index ecea1d4765..fa9b9af934 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -8,6 +8,18 @@
 
 #include 
 
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE0x0010
+#define CONFIG_SPL_BSS_START_ADDR  0x8400
+#define CONFIG_SPL_BSS_MAX_SIZE0x0010
+#define CONFIG_SYS_SPL_MALLOC_START0x8410
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS0x8020
+
+#endif
+
 #de

[U-Boot] [RESEND PATCH v4 04/11] riscv: add run mode configuration for SPL

[Lukas Auer]

U-Boot SPL can be run in a different privilege mode from U-Boot proper.
Add new configuration entries for SPL to allow the run mode to be
configured independently of U-Boot proper.

Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
configuration symbols to also cover the SPL equivalents. Ensure that
files compatible with only one privilege mode are not included in builds
targeting an incompatible privilege mode.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3:
- Rebase on u-boot-riscv/master

Changes in v2: None

 arch/riscv/Kconfig| 33 ++-
 arch/riscv/cpu/ax25/Kconfig   |  6 +++---
 arch/riscv/cpu/cpu.c  |  6 +++---
 arch/riscv/cpu/generic/Kconfig|  2 +-
 arch/riscv/cpu/start.S|  6 +++---
 arch/riscv/include/asm/encoding.h |  2 +-
 arch/riscv/lib/Makefile   |  7 +--
 7 files changed, 44 insertions(+), 18 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8cfc7d0faa..b8d01ba8e1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,6 +113,23 @@ config RISCV_SMODE
 
 endchoice
 
+choice
+   prompt "SPL Run Mode"
+   default SPL_RISCV_MMODE
+   depends on SPL
+
+config SPL_RISCV_MMODE
+   bool "Machine"
+   help
+ Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+   bool "Supervisor"
+   help
+ Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
 config RISCV_ISA_C
bool "Emit compressed instructions"
default y
@@ -132,34 +149,40 @@ config 64BIT
 
 config SIFIVE_CLINT
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
 config ANDES_PLIC
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The Andes PLIC block holds memory-mapped claim and pending registers
  associated with software interrupt.
 
 config ANDES_PLMT
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The Andes PLMT block holds memory-mapped mtime register
  associated with timer tick.
 
 config RISCV_RDTIME
bool
-   default y if RISCV_SMODE
+   default y if RISCV_SMODE || SPL_RISCV_SMODE
help
  The provides the riscv_get_time() API that is implemented using the
  standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -189,7 +212,7 @@ config NR_CPUS
 
 config SBI_IPI
bool
-   default y if RISCV_SMODE
+   default y if RISCV_SMODE || SPL_RISCV_SMODE
depends on SMP
 
 config XIP
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e692..f4b59cb71d 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,8 +4,8 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
-   imply ANDES_PLIC if RISCV_MMODE
-   imply ANDES_PLMT if RISCV_MMODE
+   imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+   imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
help
  Run U-Boot on AndeStar V5 platforms and use some specific features
  which are provided by Andes Technology AndeStar V5 families.
@@ -14,7 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
help
  Provide Andes Technology AndeStar V5 families specific cache support.
 
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 5ca185745e..e457f6acbf 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -46,13 +46,13 @@ static inline bool supports_extension(char ext)
 
return false;
 #else  /* !CONFIG_CPU */
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
return csr_read(CSR_MISA) & (1 << (ext - 'a'));
-#else  /* !CONFIG_RISCV_MMODE */
+#else  /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
return false;
-#endif /* CONFIG_RISCV_MMODE */
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
 #endif /*

[U-Boot] [RESEND PATCH v4 03/11] spl: fit: use U-Boot device tree when FIT image has no device tree

[Lukas Auer]

As part of the SPL FIT boot flow, the device tree is appended to U-Boot
proper. The device tree is used to record information on the loadables
to make them available to the SPL framework and U-Boot proper. Depending
on the U-Boot device tree provider, the FIT image might not include a
device tree. Information on the loadables is missing in this case.

When booting via firmware bundled with the FIT image, U-Boot SPL loads
the firmware binary and U-Boot proper before starting the firmware. The
firmware, in turn, is responsible for starting U-Boot proper.
Information on the memory location of the U-Boot proper loadable must be
available to the SPL framework so that it can be passed to the firmware
binary. To support this use case when no device tree is found in the FIT
image, fall back to the U-Boot device tree in this situation.

At the same time, update the comment to remove the note that the
destination address must be aligned to ARCH_DMA_MINALIGN. Alignment is
only required as an intermediate step when reading external data. This
is automatically handled by spl_fit_append_fdt(). After reading the
external data, it is copied to the specified address, which does not
have to be aligned to ARCH_DMA_MINALIGN.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 common/spl/spl_fit.c | 37 -
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 2e2e09eafb..b3e3ccd5a2 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -12,6 +12,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_BOOTM_LEN
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)
 #endif
@@ -279,25 +281,34 @@ static int spl_fit_append_fdt(struct spl_image_info 
*spl_image,
  void *fit, int images, ulong base_offset)
 {
struct spl_image_info image_info;
-   int node, ret;
+   int node, ret = 0;
+
+   /*
+* Use the address following the image as target address for the
+* device tree.
+*/
+   image_info.load_addr = spl_image->load_addr + spl_image->size;
 
/* Figure out which device tree the board wants to use */
node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
if (node < 0) {
debug("%s: cannot find FDT node\n", __func__);
-   return node;
-   }
-
-   /*
-* Read the device tree and place it after the image.
-* Align the destination address to ARCH_DMA_MINALIGN.
-*/
-   image_info.load_addr = spl_image->load_addr + spl_image->size;
-   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
-_info);
 
-   if (ret < 0)
-   return ret;
+   /*
+* U-Boot did not find a device tree inside the FIT image. Use
+* the U-Boot device tree instead.
+*/
+   if (gd->fdt_blob)
+   memcpy((void *)image_info.load_addr, gd->fdt_blob,
+  fdt_totalsize(gd->fdt_blob));
+   else
+   return node;
+   } else {
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+_info);
+   if (ret < 0)
+   return ret;
+   }
 
/* Make the load-address of the FDT available for the SPL framework */
spl_image->fdt_addr = (void *)image_info.load_addr;
-- 
2.21.0

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[U-Boot] [RESEND PATCH v4 02/11] Makefile: support building SPL FIT images without device trees

[Lukas Auer]

When building a U-Boot FIT image, the device trees specified by the
board are unconditionally built for inclusion in the FIT image. However,
not all device tree providers, such as CONFIG_OF_PRIOR_STAGE, require a
device tree to be built and bundled with the U-Boot binary. They rely on
other mechanisms to provide the device tree to U-Boot. Compilation on
boards with these device tree providers fails, because they do not
specify a device tree.

Change the makefile rules to conditionally build the device trees if
CONFIG_OF_SEPARATE, CONFIG_OF_EMBED, or CONFIG_OF_HOSTFILE is selected
as device tree provider.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4:
- Also build the device tree if CONFIG_OF_HOSTFILE is selected,
otherwise sandbox_spl is broken

Changes in v3: None
Changes in v2: None

 Makefile | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 3b0864ae8e..cf85e8c949 100644
--- a/Makefile
+++ b/Makefile
@@ -1257,7 +1257,9 @@ MKIMAGEFLAGS_u-boot.pbl = -n 
$(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
-   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin 
dts/dt.dtb,u-boot.bin) FORCE
+   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
+   $(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+   ,u-boot.bin) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
 
@@ -1267,7 +1269,9 @@ else
 MKIMAGEFLAGS_u-boot.itb = -E
 endif
 
-u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+u-boot.itb: u-boot-nodtb.bin \
+   $(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+   $(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK)
 
-- 
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[U-Boot] [RESEND PATCH v4 00/11] SPL support for RISC-V

[Lukas Auer]

This series adds support for SPL to RISC-V U-Boot. Images can be booted
via OpenSBI (FW_DYNAMIC firmware) or by directly jumping to them. In the
former case, OpenSBI and U-Boot proper are bundled as a FIT image and
made available to U-Boot SPL. Currently, only the QEMU board enables
U-Boot SPL with a dedicated configuration. It uses RAM as SPL boot
device.

On many RISC-V CPUs, the device tree is provided to U-Boot by the
first stage bootloader. This requires changes to U-Boot SPL (patches 1,
2 and 3), which modify the behavior on other boards as well.

To test this series, OpenSBI has to be compiled first. The
fw_dynamic.bin binary must be copied into the U-Boot root directory.
Alternatively, the location of the binary can be specified with the
OPENSBI environment variable. U-Boot can then be build as normal using
the configuration qemu-riscv64_spl_defconfig for 64-bit builds or
qemu-riscv32_spl_defconfig for 32-bit builds. The outputs from the build
process are the U-Boot SPL binary (spl/u-boot-spl.bin) and the U-Boot
FIT image (u-boot.itb) containing U-Boot proper and OpenSBI.

U-Boot can be run in QEMU with the following command.

qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
-device loader,file=u-boot.itb,addr=0x8020

Changes in v4:
- Also build the device tree if CONFIG_OF_HOSTFILE is selected,
otherwise sandbox_spl is broken

Changes in v3:
- Rebase on u-boot-riscv/master
- Update commit message to include minimum version of OpenSBI
- Rebase on u-boot/master
- Add note on minimum version of OpenSBI

Changes in v2:
- Rebase on master and format documentation as reStructuredText

Lukas Auer (11):
  fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL
  Makefile: support building SPL FIT images without device trees
  spl: fit: use U-Boot device tree when FIT image has no device tree
  riscv: add run mode configuration for SPL
  spl: support booting via RISC-V OpenSBI
  riscv: add SPL support
  riscv: support SPL stack and global data relocation
  riscv: add a generic FIT generator script
  riscv: set default FIT generator script and build target for SPL
builds
  riscv: qemu: add SPL configuration
  doc: update QEMU RISC-V documentation

 Kconfig |   4 +-
 Makefile|   8 +-
 arch/Kconfig|   6 ++
 arch/riscv/Kconfig  |  36 +++--
 arch/riscv/cpu/ax25/Kconfig |   6 +-
 arch/riscv/cpu/cpu.c|   6 +-
 arch/riscv/cpu/generic/Kconfig  |   5 +-
 arch/riscv/cpu/start.S  |  62 ++-
 arch/riscv/cpu/u-boot-spl.lds   |  82 +++
 arch/riscv/include/asm/encoding.h   |   2 +-
 arch/riscv/include/asm/spl.h|  31 
 arch/riscv/lib/Makefile |   8 +-
 arch/riscv/lib/mkimage_fit_opensbi.sh   | 100 
 arch/riscv/lib/spl.c|  48 
 board/emulation/qemu-riscv/Kconfig  |  10 +++
 board/emulation/qemu-riscv/MAINTAINERS  |   2 +
 board/emulation/qemu-riscv/qemu-riscv.c |  17 
 common/image.c  |   1 +
 common/spl/Kconfig  |  17 
 common/spl/Makefile |   1 +
 common/spl/spl.c|   8 +-
 common/spl/spl_fit.c|  37 ++---
 common/spl/spl_opensbi.c|  85 
 configs/qemu-riscv32_spl_defconfig  |  11 +++
 configs/qemu-riscv64_spl_defconfig  |  12 +++
 doc/board/emulation/qemu-riscv.rst  |  60 +-
 include/configs/qemu-riscv.h|  14 
 include/fdtdec.h|   2 +-
 include/image.h |   1 +
 include/opensbi.h   |  40 ++
 include/spl.h   |   5 ++
 lib/fdtdec.c|   6 +-
 32 files changed, 691 insertions(+), 42 deletions(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
 create mode 100644 arch/riscv/lib/spl.c
 create mode 100644 common/spl/spl_opensbi.c
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig
 create mode 100644 include/opensbi.h

-- 
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[U-Boot] [RESEND PATCH v4 01/11] fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL

[Lukas Auer]

The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being
used in U-Boot SPL. Change the logic to also make it available in U-Boot
SPL.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/fdtdec.h | 2 +-
 lib/fdtdec.c | 6 ++
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index e6c22dd5cd..635f53083b 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -54,7 +54,7 @@ struct bd_info;
 #define SPL_BUILD  0
 #endif
 
-#if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
+#ifdef CONFIG_OF_PRIOR_STAGE
 extern phys_addr_t prior_stage_fdt_address;
 #endif
 
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index ef5e54875c..74525c84e7 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1535,16 +1535,14 @@ int fdtdec_setup(void)
puts("Failed to read control FDT\n");
return -1;
}
+# elif defined(CONFIG_OF_PRIOR_STAGE)
+   gd->fdt_blob = (void *)prior_stage_fdt_address;
 # endif
 # ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
-#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
-   gd->fdt_blob = (void *)prior_stage_fdt_address;
-#  else
gd->fdt_blob = map_sysmem
(env_get_ulong("fdtcontroladdr", 16,
   (unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
-#  endif
 # endif
 
 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
-- 
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[U-Boot] [PATCH v4 02/11] Makefile: support building SPL FIT images without device trees

[Lukas Auer]

When building a U-Boot FIT image, the device trees specified by the
board are unconditionally built for inclusion in the FIT image. However,
not all device tree providers, such as CONFIG_OF_PRIOR_STAGE, require a
device tree to be built and bundled with the U-Boot binary. They rely on
other mechanisms to provide the device tree to U-Boot. Compilation on
boards with these device tree providers fails, because they do not
specify a device tree.

Change the makefile rules to conditionally build the device trees if
CONFIG_OF_SEPARATE, CONFIG_OF_EMBED, or CONFIG_OF_HOSTFILE is selected
as device tree provider.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v4:
- Also build the device tree if CONFIG_OF_HOSTFILE is selected,
otherwise this breaks sandbox_spl

Changes in v3: None
Changes in v2: None

 Makefile | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 3b0864ae8e..cf85e8c949 100644
--- a/Makefile
+++ b/Makefile
@@ -1257,7 +1257,9 @@ MKIMAGEFLAGS_u-boot.pbl = -n 
$(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
-   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin 
dts/dt.dtb,u-boot.bin) FORCE
+   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
+   $(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+   ,u-boot.bin) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
 
@@ -1267,7 +1269,9 @@ else
 MKIMAGEFLAGS_u-boot.itb = -E
 endif
 
-u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+u-boot.itb: u-boot-nodtb.bin \
+   $(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+   $(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK)
 
-- 
2.21.0

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[U-Boot] [PATCH v3 05/11] spl: support booting via RISC-V OpenSBI

[Lukas Auer]

RISC-V OpenSBI is an open-source implementation of the RISC-V Supervisor
Binary Interface (SBI) specification. It is required by Linux and U-Boot
running in supervisor mode. This patch adds support for booting via the
OpenSBI FW_DYNAMIC firmware. It supports OpenSBI version 0.4 and higher.

In this configuration, U-Boot SPL starts in machine mode. After loading
OpenSBI and U-Boot proper, it will start OpenSBI. All necessary
parameters are generated by U-Boot SPL and are passed to OpenSBI. U-Boot
proper is started in supervisor mode by OpenSBI. Support for OpenSBI is
enabled with CONFIG_SPL_OPENSBI. An additional configuration entry,
CONFIG_SPL_OPENSBI_LOAD_ADDR, is used to specify the load address of the
OpenSBI firmware binary. It is not used directly in U-Boot and instead
is intended to make the value available to scripts such as FIT
configuration generators.

The header file include/opensbi.h is based on header files from the
OpenSBI project. They are recent, as of commit bae54f764570 ("firmware:
Add fw_dynamic firmware").

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3:
- Update commit message to include minimum version of OpenSBI

Changes in v2: None

 common/image.c   |  1 +
 common/spl/Kconfig   | 17 
 common/spl/Makefile  |  1 +
 common/spl/spl.c |  6 +++
 common/spl/spl_opensbi.c | 85 
 include/image.h  |  1 +
 include/opensbi.h| 40 +++
 include/spl.h|  5 +++
 8 files changed, 156 insertions(+)
 create mode 100644 common/spl/spl_opensbi.c
 create mode 100644 include/opensbi.h

diff --git a/common/image.c b/common/image.c
index 495883185d..df5d174cd7 100644
--- a/common/image.c
+++ b/common/image.c
@@ -131,6 +131,7 @@ static const table_entry_t uimage_os[] = {
 #if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC)
{   IH_OS_OPENRTOS, "openrtos", "OpenRTOS", },
 #endif
+   {   IH_OS_OPENSBI,  "opensbi",  "RISC-V OpenSBI",   },
 
{   -1, "", "", },
 };
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 54154b93c9..d9a1e3af89 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1127,6 +1127,23 @@ config SPL_OPTEE
  OP-TEE is an open source Trusted OS  which is loaded by SPL.
  More detail at: https://github.com/OP-TEE/optee_os
 
+config SPL_OPENSBI
+   bool "Support RISC-V OpenSBI"
+   depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE
+   help
+ OpenSBI is an open-source implementation of the RISC-V Supervisor 
Binary
+ Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC
+ firmware. It is loaded and started by U-Boot SPL.
+
+ More details are available at https://github.com/riscv/opensbi and
+ https://github.com/riscv/riscv-sbi-doc
+
+config SPL_OPENSBI_LOAD_ADDR
+   hex "OpenSBI load address"
+   depends on SPL_OPENSBI
+   help
+ Load address of the OpenSBI binary.
+
 config TPL
bool
depends on SUPPORT_TPL
diff --git a/common/spl/Makefile b/common/spl/Makefile
index d28de692dd..5ce6f4ae48 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
 obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
+obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o
 obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
 obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
 obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index c182705b3f..133b179675 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -659,6 +659,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
(void *)spl_image.entry_point);
break;
 #endif
+#if CONFIG_IS_ENABLED(OPENSBI)
+   case IH_OS_OPENSBI:
+   debug("Jumping to U-Boot via RISC-V OpenSBI\n");
+   spl_invoke_opensbi(_image);
+   break;
+#endif
 #ifdef CONFIG_SPL_OS_BOOT
case IH_OS_LINUX:
debug("Jumping to Linux\n");
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
new file mode 100644
index 00..a6b4480ed2
--- /dev/null
+++ b/common/spl/spl_opensbi.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer 
+ *
+ * Based on common/spl/spl_atf.c
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct fw_dynamic_info opensbi_info;
+
+static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+{

[U-Boot] [PATCH v3 00/11] SPL support for RISC-V

[Lukas Auer]

This series adds support for SPL to RISC-V U-Boot. Images can be booted
via OpenSBI (FW_DYNAMIC firmware) or by directly jumping to them. In the
former case, OpenSBI and U-Boot proper are bundled as a FIT image and
made available to U-Boot SPL. Currently, only the QEMU board enables
U-Boot SPL with a dedicated configuration. It uses RAM as SPL boot
device.

On many RISC-V CPUs, the device tree is provided to U-Boot by the
first stage bootloader. This requires changes to U-Boot SPL (patches 1,
2 and 3), which modify the behavior on other boards as well.

To test this series, OpenSBI has to be compiled first. The
fw_dynamic.bin binary must be copied into the U-Boot root directory.
Alternatively, the location of the binary can be specified with the
OPENSBI environment variable. U-Boot can then be build as normal using
the configuration qemu-riscv64_spl_defconfig for 64-bit builds or
qemu-riscv32_spl_defconfig for 32-bit builds. The outputs from the build
process are the U-Boot SPL binary (spl/u-boot-spl.bin) and the U-Boot
FIT image (u-boot.itb) containing U-Boot proper and OpenSBI.

U-Boot can be run in QEMU with the following command.

qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
-device loader,file=u-boot.itb,addr=0x8020

Changes in v3:
- Rebase on u-boot-riscv/master
- Update commit message to include minimum version of OpenSBI
- Rebase on u-boot/master
- Add note on minimum version of OpenSBI

Changes in v2:
- Rebase on master and format documentation as reStructuredText

Lukas Auer (11):
  fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL
  Makefile: support building SPL FIT images without device trees
  spl: fit: use U-Boot device tree when FIT image has no device tree
  riscv: add run mode configuration for SPL
  spl: support booting via RISC-V OpenSBI
  riscv: add SPL support
  riscv: support SPL stack and global data relocation
  riscv: add a generic FIT generator script
  riscv: set default FIT generator script and build target for SPL
builds
  riscv: qemu: add SPL configuration
  doc: update QEMU RISC-V documentation

 Kconfig |   4 +-
 Makefile|   8 +-
 arch/Kconfig|   6 ++
 arch/riscv/Kconfig  |  36 +++--
 arch/riscv/cpu/ax25/Kconfig |   6 +-
 arch/riscv/cpu/cpu.c|   6 +-
 arch/riscv/cpu/generic/Kconfig  |   5 +-
 arch/riscv/cpu/start.S  |  62 ++-
 arch/riscv/cpu/u-boot-spl.lds   |  82 +++
 arch/riscv/include/asm/encoding.h   |   2 +-
 arch/riscv/include/asm/spl.h|  31 
 arch/riscv/lib/Makefile |   8 +-
 arch/riscv/lib/mkimage_fit_opensbi.sh   | 100 
 arch/riscv/lib/spl.c|  48 
 board/emulation/qemu-riscv/Kconfig  |  10 +++
 board/emulation/qemu-riscv/MAINTAINERS  |   2 +
 board/emulation/qemu-riscv/qemu-riscv.c |  17 
 common/image.c  |   1 +
 common/spl/Kconfig  |  17 
 common/spl/Makefile |   1 +
 common/spl/spl.c|   8 +-
 common/spl/spl_fit.c|  37 ++---
 common/spl/spl_opensbi.c|  85 
 configs/qemu-riscv32_spl_defconfig  |  11 +++
 configs/qemu-riscv64_spl_defconfig  |  12 +++
 doc/board/emulation/qemu-riscv.rst  |  60 +-
 include/configs/qemu-riscv.h|  14 
 include/fdtdec.h|   2 +-
 include/image.h |   1 +
 include/opensbi.h   |  40 ++
 include/spl.h   |   5 ++
 lib/fdtdec.c|   6 +-
 32 files changed, 691 insertions(+), 42 deletions(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
 create mode 100644 arch/riscv/lib/spl.c
 create mode 100644 common/spl/spl_opensbi.c
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig
 create mode 100644 include/opensbi.h

-- 
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[U-Boot] [PATCH v3 04/11] riscv: add run mode configuration for SPL

[Lukas Auer]

U-Boot SPL can be run in a different privilege mode from U-Boot proper.
Add new configuration entries for SPL to allow the run mode to be
configured independently of U-Boot proper.

Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
configuration symbols to also cover the SPL equivalents. Ensure that
files compatible with only one privilege mode are not included in builds
targeting an incompatible privilege mode.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3:
- Rebase on u-boot-riscv/master

Changes in v2: None

 arch/riscv/Kconfig| 33 ++-
 arch/riscv/cpu/ax25/Kconfig   |  6 +++---
 arch/riscv/cpu/cpu.c  |  6 +++---
 arch/riscv/cpu/generic/Kconfig|  2 +-
 arch/riscv/cpu/start.S|  6 +++---
 arch/riscv/include/asm/encoding.h |  2 +-
 arch/riscv/lib/Makefile   |  7 +--
 7 files changed, 44 insertions(+), 18 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8cfc7d0faa..b8d01ba8e1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,6 +113,23 @@ config RISCV_SMODE
 
 endchoice
 
+choice
+   prompt "SPL Run Mode"
+   default SPL_RISCV_MMODE
+   depends on SPL
+
+config SPL_RISCV_MMODE
+   bool "Machine"
+   help
+ Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+   bool "Supervisor"
+   help
+ Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
 config RISCV_ISA_C
bool "Emit compressed instructions"
default y
@@ -132,34 +149,40 @@ config 64BIT
 
 config SIFIVE_CLINT
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
 config ANDES_PLIC
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The Andes PLIC block holds memory-mapped claim and pending registers
  associated with software interrupt.
 
 config ANDES_PLMT
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The Andes PLMT block holds memory-mapped mtime register
  associated with timer tick.
 
 config RISCV_RDTIME
bool
-   default y if RISCV_SMODE
+   default y if RISCV_SMODE || SPL_RISCV_SMODE
help
  The provides the riscv_get_time() API that is implemented using the
  standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -189,7 +212,7 @@ config NR_CPUS
 
 config SBI_IPI
bool
-   default y if RISCV_SMODE
+   default y if RISCV_SMODE || SPL_RISCV_SMODE
depends on SMP
 
 config XIP
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e692..f4b59cb71d 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,8 +4,8 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
-   imply ANDES_PLIC if RISCV_MMODE
-   imply ANDES_PLMT if RISCV_MMODE
+   imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+   imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
help
  Run U-Boot on AndeStar V5 platforms and use some specific features
  which are provided by Andes Technology AndeStar V5 families.
@@ -14,7 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
help
  Provide Andes Technology AndeStar V5 families specific cache support.
 
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 5ca185745e..e457f6acbf 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -46,13 +46,13 @@ static inline bool supports_extension(char ext)
 
return false;
 #else  /* !CONFIG_CPU */
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
return csr_read(CSR_MISA) & (1 << (ext - 'a'));
-#else  /* !CONFIG_RISCV_MMODE */
+#else  /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
return false;
-#endif /* CONFIG_RISCV_MMODE */
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
 #endif /* CONFIG_CPU */
 

[U-Boot] [PATCH v3 06/11] riscv: add SPL support

[Lukas Auer]

U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
jumping to the image and via OpenSBI firmware. In the first case, both
U-Boot SPL and proper must be compiled to run in the same privilege
mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
mode and U-Boot proper for supervisor mode.

To be able to use SPL, boards have to provide a supported SPL boot
device.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3: None
Changes in v2: None

 arch/Kconfig   |  6 +++
 arch/riscv/Kconfig |  3 ++
 arch/riscv/cpu/generic/Kconfig |  3 ++
 arch/riscv/cpu/start.S | 23 +-
 arch/riscv/cpu/u-boot-spl.lds  | 82 ++
 arch/riscv/include/asm/spl.h   | 31 +
 arch/riscv/lib/Makefile|  1 +
 arch/riscv/lib/spl.c   | 48 
 8 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100644 arch/riscv/lib/spl.c

diff --git a/arch/Kconfig b/arch/Kconfig
index 949eb28dfa..8350d9b1ea 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -76,6 +76,12 @@ config RISCV
imply MTD
imply TIMER
imply CMD_DM
+   imply SPL_DM
+   imply SPL_OF_CONTROL
+   imply SPL_LIBCOMMON_SUPPORT
+   imply SPL_LIBGENERIC_SUPPORT
+   imply SPL_SERIAL_SUPPORT
+   imply SPL_TIMER
 
 config SANDBOX
bool "Sandbox"
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b8d01ba8e1..01975d7c60 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -226,4 +226,7 @@ config STACK_SIZE_SHIFT
int
default 13
 
+config SPL_LDSCRIPT
+   default "arch/riscv/cpu/u-boot-spl.lds"
+
 endmenu
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index b7552f539f..b2cb155d6d 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -10,3 +10,6 @@ config GENERIC_RISCV
imply RISCV_TIMER
imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply CMD_CPU
+   imply SPL_CPU_SUPPORT
+   imply SPL_OPENSBI
+   imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index e82ee9e365..66c603906d 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -75,7 +75,11 @@ _start:
  */
 call_board_init_f:
li  t0, -16
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+   li  t1, CONFIG_SPL_STACK
+#else
li  t1, CONFIG_SYS_INIT_SP_ADDR
+#endif
and sp, t1, t0  /* force 16 byte alignment */
 
 call_board_init_f_0:
@@ -159,7 +163,24 @@ wait_for_gd_init:
 
mv  a0, zero/* a0 <-- boot_flags = 0 */
la  t5, board_init_f
-   jr  t5  /* jump to board_init_f() */
+   jalrt5  /* jump to board_init_f() */
+
+#ifdef CONFIG_SPL_BUILD
+spl_clear_bss:
+   la  t0, __bss_start
+   la  t1, __bss_end
+   beq t0, t1, spl_call_board_init_r
+
+spl_clear_bss_loop:
+   SREGzero, 0(t0)
+   addit0, t0, REGBYTES
+   bne t0, t1, spl_clear_bss_loop
+
+spl_call_board_init_r:
+   mv  a0, zero
+   mv  a1, zero
+   jal board_init_r
+#endif
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
new file mode 100644
index 00..32255d58de
--- /dev/null
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/riscv/cpu/u-boot.lds, which is
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ *
+ * and arch/mips/cpu/u-boot-spl.lds.
+ */
+MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+   LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+   . = ALIGN(4);
+   .text : {
+   arch/riscv/cpu/start.o  (.text)
+   *(.text*)
+   } > .spl_mem
+
+   . = ALIGN(4);
+   .rodata : {
+   *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+   } > .spl_mem
+
+   . = ALIGN(4);
+   .data : {
+   *(.data*)
+   } > .spl_mem
+   . = ALIGN(4);
+
+   .got : {
+   __got_start = .;
+   *(.got.plt) *(.got)
+   __got_end = .;
+   } > .spl_mem
+
+   . = ALIGN(4);
+
+   .u_boot_list : {
+   KEEP(*(SORT(.u_boot_list*)));
+   } > .spl_mem
+
+   . = ALIGN(4);
+
+   .binman_sym_table : {
+   __binman_sym_start = .;
+   KEEP(*(SORT(.binman_sym*)));
+   __binman

[U-Boot] [PATCH v3 09/11] riscv: set default FIT generator script and build target for SPL builds

[Lukas Auer]

Now that we have a generic FIT generator script for RISC-V, set it as
the default. To also build the FIT image by default, set the default
build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3: None
Changes in v2: None

 Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Kconfig b/Kconfig
index d2eb744e70..a78dd59a79 100644
--- a/Kconfig
+++ b/Kconfig
@@ -250,7 +250,8 @@ config BUILD_TARGET
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
-   default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI)
+   default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || \
+   ARCH_SUNXI || RISCV)
default "u-boot.kwb" if KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
help
@@ -463,6 +464,7 @@ config SPL_FIT_GENERATOR
depends on SPL_FIT
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && 
ARCH_ROCKCHIP
+   default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
  Specifies a (platform specific) script file to generate the FIT
  source file used to build the U-Boot FIT image file. This gets
-- 
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[U-Boot] [PATCH v3 08/11] riscv: add a generic FIT generator script

[Lukas Auer]

Add a generic FIT generator script for RISC-V to generate images
containing U-Boot, OpenSBI FW_DYNAMIC firmware, and optionally one or
more device trees. The location of the OpenSBI firmware binary can be
specified with the OPENSBI environment variable. By default, it is
assumed to be "fw_dynamic.bin", located in the U-Boot top-level. Device
trees are passed as arguments to the generator script. A separate
configuration entry is created for each device tree.

The load addresses of U-Boot and OpenSBI are parsed from the U-Boot
configuration. They can be overwritten with the UBOOT_LOAD_ADDR and
OPENSBI_LOAD_ADDR environment variables.

The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh)
and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator
scripts.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3: None
Changes in v2: None

 arch/riscv/lib/mkimage_fit_opensbi.sh | 100 ++
 1 file changed, 100 insertions(+)
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh

diff --git a/arch/riscv/lib/mkimage_fit_opensbi.sh 
b/arch/riscv/lib/mkimage_fit_opensbi.sh
new file mode 100755
index 00..d6f95e5bfd
--- /dev/null
+++ b/arch/riscv/lib/mkimage_fit_opensbi.sh
@@ -0,0 +1,100 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for RISC-V boards with OpenSBI
+# and, optionally, multiple device trees (given on the command line).
+#
+# usage: $0 [ [&2
+   OPENSBI=/dev/null
+fi
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+   description = "Configuration to load OpenSBI before U-Boot";
+
+   images {
+   uboot {
+   description = "U-Boot";
+   data = /incbin/("u-boot-nodtb.bin");
+   type = "standalone";
+   os = "U-Boot";
+   arch = "riscv";
+   compression = "none";
+   load = <$UBOOT_LOAD_ADDR>;
+   };
+   opensbi {
+   description = "RISC-V OpenSBI";
+   data = /incbin/("$OPENSBI");
+   type = "firmware";
+   os = "opensbi";
+   arch = "riscv";
+   compression = "none";
+   load = <$OPENSBI_LOAD_ADDR>;
+   entry = <$OPENSBI_LOAD_ADDR>;
+   };
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+   cat << __FDT_IMAGE_EOF
+   fdt_$cnt {
+   description = "$(basename $dtname .dtb)";
+   data = /incbin/("$dtname");
+   type = "flat_dt";
+   compression = "none";
+   };
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+   };
+   configurations {
+   default = "config_1";
+
+__CONF_HEADER_EOF
+
+if [ $# -eq 0 ]; then
+cat << __CONF_SECTION_EOF
+   config_1 {
+   description = "U-Boot FIT";
+   firmware = "opensbi";
+   loadables = "uboot";
+   };
+__CONF_SECTION_EOF
+else
+cnt=1
+for dtname in $*
+do
+cat << __CONF_SECTION_EOF
+   config_$cnt {
+   description = "$(basename $dtname .dtb)";
+   firmware = "opensbi";
+   loadables = "uboot";
+   fdt = "fdt_$cnt";
+   };
+__CONF_SECTION_EOF
+cnt=$((cnt+1))
+done
+fi
+
+cat << __ITS_EOF
+   };
+};
+__ITS_EOF
-- 
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[U-Boot] [PATCH v3 03/11] spl: fit: use U-Boot device tree when FIT image has no device tree

[Lukas Auer]

As part of the SPL FIT boot flow, the device tree is appended to U-Boot
proper. The device tree is used to record information on the loadables
to make them available to the SPL framework and U-Boot proper. Depending
on the U-Boot device tree provider, the FIT image might not include a
device tree. Information on the loadables is missing in this case.

When booting via firmware bundled with the FIT image, U-Boot SPL loads
the firmware binary and U-Boot proper before starting the firmware. The
firmware, in turn, is responsible for starting U-Boot proper.
Information on the memory location of the U-Boot proper loadable must be
available to the SPL framework so that it can be passed to the firmware
binary. To support this use case when no device tree is found in the FIT
image, fall back to the U-Boot device tree in this situation.

At the same time, update the comment to remove the note that the
destination address must be aligned to ARCH_DMA_MINALIGN. Alignment is
only required as an intermediate step when reading external data. This
is automatically handled by spl_fit_append_fdt(). After reading the
external data, it is copied to the specified address, which does not
have to be aligned to ARCH_DMA_MINALIGN.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3: None
Changes in v2: None

 common/spl/spl_fit.c | 37 -
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 969f7775c1..0bfb91d686 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -11,6 +11,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_BOOTM_LEN
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)
 #endif
@@ -278,25 +280,34 @@ static int spl_fit_append_fdt(struct spl_image_info 
*spl_image,
  void *fit, int images, ulong base_offset)
 {
struct spl_image_info image_info;
-   int node, ret;
+   int node, ret = 0;
+
+   /*
+* Use the address following the image as target address for the
+* device tree.
+*/
+   image_info.load_addr = spl_image->load_addr + spl_image->size;
 
/* Figure out which device tree the board wants to use */
node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
if (node < 0) {
debug("%s: cannot find FDT node\n", __func__);
-   return node;
-   }
-
-   /*
-* Read the device tree and place it after the image.
-* Align the destination address to ARCH_DMA_MINALIGN.
-*/
-   image_info.load_addr = spl_image->load_addr + spl_image->size;
-   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
-_info);
 
-   if (ret < 0)
-   return ret;
+   /*
+* U-Boot did not find a device tree inside the FIT image. Use
+* the U-Boot device tree instead.
+*/
+   if (gd->fdt_blob)
+   memcpy((void *)image_info.load_addr, gd->fdt_blob,
+  fdt_totalsize(gd->fdt_blob));
+   else
+   return node;
+   } else {
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+_info);
+   if (ret < 0)
+   return ret;
+   }
 
/* Make the load-address of the FDT available for the SPL framework */
spl_image->fdt_addr = (void *)image_info.load_addr;
-- 
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[U-Boot] [PATCH v3 02/11] Makefile: support building SPL FIT images without device trees

[Lukas Auer]

When building a U-Boot FIT image, the device trees specified by the
board are unconditionally built for inclusion in the FIT image. However,
not all device tree providers, such as CONFIG_OF_PRIOR_STAGE, require a
device tree to be built and bundled with the U-Boot binary. They rely on
other mechanisms to provide the device tree to U-Boot. Compilation on
boards with these device tree providers fails, because they do not
specify a device tree.

Change the makefile rules to conditionally build the device trees if
either CONFIG_OF_SEPARATE or CONFIG_OF_EMBED is selected as device tree
provider.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3: None
Changes in v2: None

 Makefile | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 8513db94e3..b2f857f890 100644
--- a/Makefile
+++ b/Makefile
@@ -1257,7 +1257,9 @@ MKIMAGEFLAGS_u-boot.pbl = -n 
$(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
-   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin 
dts/dt.dtb,u-boot.bin) FORCE
+   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
+   $(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED),dts/dt.dtb) \
+   ,u-boot.bin) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
 
@@ -1267,7 +1269,9 @@ else
 MKIMAGEFLAGS_u-boot.itb = -E
 endif
 
-u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+u-boot.itb: u-boot-nodtb.bin \
+   $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED),dts/dt.dtb) \
+   $(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK)
 
-- 
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[U-Boot] [PATCH v3 11/11] doc: update QEMU RISC-V documentation

[Lukas Auer]

The available defconfigs for RISC-V QEMU have changed. We now have
configurations to compile U-Boot to run in supervisor mode and for
U-Boot SPL. Update the QEMU RISC-V documentation to reflect these
changes.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3:
- Add note on minimum version of OpenSBI

Changes in v2:
- Rebase on master and format documentation as reStructuredText

 doc/board/emulation/qemu-riscv.rst | 60 +-
 1 file changed, 59 insertions(+), 1 deletion(-)

diff --git a/doc/board/emulation/qemu-riscv.rst 
b/doc/board/emulation/qemu-riscv.rst
index 214833496b..fe7505e201 100644
--- a/doc/board/emulation/qemu-riscv.rst
+++ b/doc/board/emulation/qemu-riscv.rst
@@ -6,7 +6,8 @@ QEMU RISC-V
 
 QEMU for RISC-V supports a special 'virt' machine designed for emulation and
 virtualization purposes. This document describes how to run U-Boot under it.
-Both 32-bit 64-bit targets are supported.
+Both 32-bit and 64-bit targets are supported, running in either machine or
+supervisor mode.
 
 The QEMU virt machine models a generic RISC-V virtual machine with support for
 the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
@@ -28,6 +29,11 @@ Set the CROSS_COMPILE environment variable as usual, and run:
 make qemu-riscv64_defconfig
 make
 
+This will compile U-Boot for machine mode. To build supervisor mode binaries,
+use the configurations qemu-riscv32_smode_defconfig and
+qemu-riscv64_smode_defconfig instead. Note that U-Boot running in supervisor
+mode requires a supervisor binary interface (SBI), such as RISC-V OpenSBI.
+
 Running U-Boot
 --
 The minimal QEMU command line to get U-Boot up and running is:
@@ -46,4 +52,56 @@ parameter. For example, '-m 2G' creates 2GiB memory for the 
target,
 and the memory node in the embedded DTB created by QEMU reflects
 the new setting.
 
+For instructions on how to run U-Boot in supervisor mode on QEMU
+with OpenSBI, see the documentation available with OpenSBI:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
 These have been tested in QEMU 3.0.0.
+
+Running U-Boot SPL
+--
+In the default SPL configuration, U-Boot SPL starts in machine mode. U-Boot
+proper and OpenSBI (FW_DYNAMIC firmware) are bundled as FIT image and made
+available to U-Boot SPL. Both are then loaded by U-Boot SPL and the location
+of U-Boot proper is passed to OpenSBI. After initialization, U-Boot proper is
+started in supervisor mode by OpenSBI.
+
+OpenSBI must be compiled before compiling U-Boot. Version 0.4 and higher is
+supported by U-Boot. Clone the OpenSBI repository and run the following 
command.
+
+.. code-block:: console
+
+git clone https://github.com/riscv/opensbi.git
+cd opensbi
+make PLATFORM=qemu/virt
+
+See the OpenSBI documentation for full details:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
+To make the FW_DYNAMIC binary 
(build/platform/qemu/virt/firmware/fw_dynamic.bin)
+available to U-Boot, either copy it into the U-Boot root directory or specify
+its location with the OPENSBI environment variable. Afterwards, compile U-Boot
+with the following commands.
+
+- For 32-bit RISC-V::
+
+make qemu-riscv32_spl_defconfig
+make
+
+- For 64-bit RISC-V::
+
+make qemu-riscv64_spl_defconfig
+make
+
+The minimal QEMU commands to run U-Boot SPL in both 32-bit and 64-bit
+configurations are:
+
+- For 32-bit RISC-V::
+
+qemu-system-riscv32 -nographic -machine virt -kernel spl/u-boot-spl \
+-device loader,file=u-boot.itb,addr=0x8020
+
+- For 64-bit RISC-V::
+
+qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
+-device loader,file=u-boot.itb,addr=0x8020
-- 
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[U-Boot] [PATCH v3 10/11] riscv: qemu: add SPL configuration

[Lukas Auer]

Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
configurations are meant to help the development of SPL on RISC-V.

The configurations enable RAM as the only SPL boot device. Images must
be loaded at address 0x8020. In the default boot flow, U-Boot SPL
starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
then started in supervisor mode by OpenSBI.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3:
- Rebase on u-boot/master

Changes in v2: None

 board/emulation/qemu-riscv/Kconfig  | 10 ++
 board/emulation/qemu-riscv/MAINTAINERS  |  2 ++
 board/emulation/qemu-riscv/qemu-riscv.c | 17 +
 configs/qemu-riscv32_spl_defconfig  | 11 +++
 configs/qemu-riscv64_spl_defconfig  | 12 
 include/configs/qemu-riscv.h| 14 ++
 6 files changed, 66 insertions(+)
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig

diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 6cc7c31dc6..1928d6dda0 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -13,13 +13,21 @@ config SYS_CONFIG_NAME
default "qemu-riscv"
 
 config SYS_TEXT_BASE
+   default 0x8120 if SPL
default 0x8000 if !RISCV_SMODE
default 0x8020 if RISCV_SMODE && ARCH_RV64I
default 0x8040 if RISCV_SMODE && ARCH_RV32I
 
+config SPL_TEXT_BASE
+   default 0x8000
+
+config SPL_OPENSBI_LOAD_ADDR
+   default 0x8100
+
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+   select SUPPORT_SPL
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
@@ -43,5 +51,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_PCI
imply E1000
imply NVME
+   imply SPL_RAM_SUPPORT
+   imply SPL_RAM_DEVICE
 
 endif
diff --git a/board/emulation/qemu-riscv/MAINTAINERS 
b/board/emulation/qemu-riscv/MAINTAINERS
index c701c83d77..78969ed6bd 100644
--- a/board/emulation/qemu-riscv/MAINTAINERS
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -5,5 +5,7 @@ F:  board/emulation/qemu-riscv/
 F: include/configs/qemu-riscv.h
 F: configs/qemu-riscv32_defconfig
 F: configs/qemu-riscv32_smode_defconfig
+F: configs/qemu-riscv32_spl_defconfig
 F: configs/qemu-riscv64_defconfig
 F: configs/qemu-riscv64_smode_defconfig
+F: configs/qemu-riscv64_spl_defconfig
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c 
b/board/emulation/qemu-riscv/qemu-riscv.c
index d6167aaef1..e04bd3001c 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -87,3 +88,19 @@ int ft_board_setup(void *blob, bd_t *bd)
 
return 0;
 }
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+   /* RISC-V QEMU only supports RAM as SPL boot device */
+   return BOOT_DEVICE_RAM;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   /* boot using first FIT config */
+   return 0;
+}
+#endif
diff --git a/configs/qemu-riscv32_spl_defconfig 
b/configs/qemu-riscv32_spl_defconfig
new file mode 100644
index 00..78e755b36a
--- /dev/null
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_spl_defconfig 
b/configs/qemu-riscv64_spl_defconfig
new file mode 100644
index 00..a3f5e29d58
--- /dev/null
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -0,0 +1,12 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index ecea1d4765..fa9b9af934 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -8,6 +8,18 @@
 
 #include 
 
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE0x0010
+#define CONFIG_SPL_BSS_START_ADDR  0x8400
+#define CONFIG_SPL_BSS_MAX_SIZE0x0010
+#define CONFIG_SYS_SPL_MALLOC_START0x8410
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS0x8020
+
+#endif
+
 #define CONFIG_SYS_SDRA

[U-Boot] [PATCH v3 01/11] fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL

[Lukas Auer]

The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being
used in U-Boot SPL. Change the logic to also make it available in U-Boot
SPL.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3: None
Changes in v2: None

 include/fdtdec.h | 2 +-
 lib/fdtdec.c | 6 ++
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index e6c22dd5cd..635f53083b 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -54,7 +54,7 @@ struct bd_info;
 #define SPL_BUILD  0
 #endif
 
-#if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
+#ifdef CONFIG_OF_PRIOR_STAGE
 extern phys_addr_t prior_stage_fdt_address;
 #endif
 
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 3ee786b579..569ffd5987 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1533,16 +1533,14 @@ int fdtdec_setup(void)
puts("Failed to read control FDT\n");
return -1;
}
+# elif defined(CONFIG_OF_PRIOR_STAGE)
+   gd->fdt_blob = (void *)prior_stage_fdt_address;
 # endif
 # ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
-#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
-   gd->fdt_blob = (void *)prior_stage_fdt_address;
-#  else
gd->fdt_blob = map_sysmem
(env_get_ulong("fdtcontroladdr", 16,
   (unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
-#  endif
 # endif
 
 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
-- 
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[U-Boot] [PATCH v3 07/11] riscv: support SPL stack and global data relocation

[Lukas Auer]

To support relocation of the stack and global data on RISC-V, the
secondary harts must be notified of the change using IPIs. We can reuse
the hart relocation code for this purpose. It uses global data to store
the new stack pointer and global data pointer for the secondary harts.
This means that we cannot update the global data pointer of the main
hart in spl_relocate_stack_gd(), because the secondary harts have not
yet been relocated at this point. It is updated after the secondary
harts have been notified.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Anup Patel 
---

Changes in v3: None
Changes in v2: None

 arch/riscv/cpu/start.S | 35 ++-
 common/spl/spl.c   |  2 +-
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 66c603906d..b15209d623 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -169,13 +169,46 @@ wait_for_gd_init:
 spl_clear_bss:
la  t0, __bss_start
la  t1, __bss_end
-   beq t0, t1, spl_call_board_init_r
+   beq t0, t1, spl_stack_gd_setup
 
 spl_clear_bss_loop:
SREGzero, 0(t0)
addit0, t0, REGBYTES
bne t0, t1, spl_clear_bss_loop
 
+spl_stack_gd_setup:
+   jal spl_relocate_stack_gd
+
+   /* skip setup if we did not relocate */
+   beqza0, spl_call_board_init_r
+   mv  s0, a0
+
+   /* setup stack on main hart */
+#ifdef CONFIG_SMP
+   /* tp: hart id */
+   sllit0, tp, CONFIG_STACK_SIZE_SHIFT
+   sub sp, s0, t0
+#else
+   mv  sp, s0
+#endif
+
+   /* set new stack and global data pointer on secondary harts */
+spl_secondary_hart_stack_gd_setup:
+   la  a0, secondary_hart_relocate
+   mv  a1, s0
+   mv  a2, s0
+   jal smp_call_function
+
+   /* hang if relocation of secondary harts has failed */
+   beqza0, 1f
+   mv  a1, a0
+   la  a0, secondary_harts_relocation_error
+   jal printf
+   jal hang
+
+   /* set new global data pointer on main hart */
+1: mv  gp, s0
+
 spl_call_board_init_r:
mv  a0, zero
mv  a1, zero
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 133b179675..ea7f01baaf 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -756,7 +756,7 @@ ulong spl_relocate_stack_gd(void)
 #if CONFIG_IS_ENABLED(DM)
dm_fixup_for_gd_move(new_gd);
 #endif
-#if !defined(CONFIG_ARM)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_RISCV)
gd = new_gd;
 #endif
return ptr;
-- 
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[U-Boot] [PATCH v2 05/11] spl: support booting via RISC-V OpenSBI

[Lukas Auer]

RISC-V OpenSBI is an open-source implementation of the RISC-V Supervisor
Binary Interface (SBI) specification. It is required by Linux and U-Boot
running in supervisor mode. This patch adds support for booting via the
OpenSBI FW_DYNAMIC firmware.

In this configuration, U-Boot SPL starts in machine mode. After loading
OpenSBI and U-Boot proper, it will start OpenSBI. All necessary
parameters are generated by U-Boot SPL and passed to OpenSBI. U-Boot
proper is started in supervisor mode by OpenSBI. Support for OpenSBI is
enabled with CONFIG_SPL_OPENSBI. An additional configuration entry,
CONFIG_SPL_OPENSBI_LOAD_ADDR, is used to specify the load address of the
OpenSBI firmware binary. It is not used directly in U-Boot and instead
is intended to make the value available to scripts such as FIT
configuration generators.

The header file include/opensbi.h is based on header files from the
OpenSBI project. They are recent, as of commit bae54f764570 ("firmware:
Add fw_dynamic firmware").

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 common/image.c   |  1 +
 common/spl/Kconfig   | 17 
 common/spl/Makefile  |  1 +
 common/spl/spl.c |  6 +++
 common/spl/spl_opensbi.c | 85 
 include/image.h  |  1 +
 include/opensbi.h| 40 +++
 include/spl.h|  5 +++
 8 files changed, 156 insertions(+)
 create mode 100644 common/spl/spl_opensbi.c
 create mode 100644 include/opensbi.h

diff --git a/common/image.c b/common/image.c
index 9f9538fac2..7c7353a989 100644
--- a/common/image.c
+++ b/common/image.c
@@ -125,6 +125,7 @@ static const table_entry_t uimage_os[] = {
 #if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC)
{   IH_OS_OPENRTOS, "openrtos", "OpenRTOS", },
 #endif
+   {   IH_OS_OPENSBI,  "opensbi",  "RISC-V OpenSBI",   },
 
{   -1, "", "", },
 };
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 5d6da5db89..939c8517cd 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1126,6 +1126,23 @@ config SPL_OPTEE
  OP-TEE is an open source Trusted OS  which is loaded by SPL.
  More detail at: https://github.com/OP-TEE/optee_os
 
+config SPL_OPENSBI
+   bool "Support RISC-V OpenSBI"
+   depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE
+   help
+ OpenSBI is an open-source implementation of the RISC-V Supervisor 
Binary
+ Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC
+ firmware. It is loaded and started by U-Boot SPL.
+
+ More details are available at https://github.com/riscv/opensbi and
+ https://github.com/riscv/riscv-sbi-doc
+
+config SPL_OPENSBI_LOAD_ADDR
+   hex "OpenSBI load address"
+   depends on SPL_OPENSBI
+   help
+ Load address of the OpenSBI binary.
+
 config TPL
bool
depends on SUPPORT_TPL
diff --git a/common/spl/Makefile b/common/spl/Makefile
index d28de692dd..5ce6f4ae48 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
 obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
+obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o
 obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
 obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
 obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index d5e3f680f4..1ed4741bdc 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -659,6 +659,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
(void *)spl_image.entry_point);
break;
 #endif
+#if CONFIG_IS_ENABLED(OPENSBI)
+   case IH_OS_OPENSBI:
+   debug("Jumping to U-Boot via RISC-V OpenSBI\n");
+   spl_invoke_opensbi(_image);
+   break;
+#endif
 #ifdef CONFIG_SPL_OS_BOOT
case IH_OS_LINUX:
debug("Jumping to Linux\n");
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
new file mode 100644
index 00..a6b4480ed2
--- /dev/null
+++ b/common/spl/spl_opensbi.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer 
+ *
+ * Based on common/spl/spl_atf.c
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct fw_dynamic_info opensbi_info;
+
+static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+{
+   int fit_images_node, node;
+   const char *fit_os;
+
+   fit_images_node = fdt_path_offset(blob, "/fit-images");
+   if (fit_images_node < 0)
+ 

[U-Boot] [PATCH v2 00/11] SPL support for RISC-V

[Lukas Auer]

This series adds support for SPL to RISC-V U-Boot. Images can be booted
via OpenSBI (FW_DYNAMIC firmware) or by directly jumping to them. In the
former case, OpenSBI and U-Boot proper are bundled as a FIT image and
made available to U-Boot SPL. Currently, only the QEMU board enables
U-Boot SPL with a dedicated configuration. It uses RAM as SPL boot
device.

On many RISC-V CPUs, the device tree is provided to U-Boot by the
first stage bootloader. This requires changes to U-Boot SPL (patches 1,
2 and 3), which modify the behavior on other boards as well.

To test this series, OpenSBI has to be compiled first. The
fw_dynamic.bin binary must be copied into the U-Boot root directory.
Alternatively, the location of the binary can be specified with the
OPENSBI environment variable. U-Boot can then be build as normal using
the configuration qemu-riscv64_spl_defconfig for 64-bit builds or
qemu-riscv32_spl_defconfig for 32-bit builds. The outputs from the build
process are the U-Boot SPL binary (spl/u-boot-spl.bin) and the U-Boot
FIT image (u-boot.itb) containing U-Boot proper and OpenSBI.

U-Boot can be run in QEMU with the following command.

qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
-device loader,file=u-boot.itb,addr=0x8020

Changes in v2:
- Rebase on master and format documentation as reStructuredText

Lukas Auer (11):
  fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL
  Makefile: support building SPL FIT images without device trees
  spl: fit: use U-Boot device tree when FIT image has no device tree
  riscv: add run mode configuration for SPL
  spl: support booting via RISC-V OpenSBI
  riscv: add SPL support
  riscv: support SPL stack and global data relocation
  riscv: add a generic FIT generator script
  riscv: set default FIT generator script and build target for SPL
builds
  riscv: qemu: add SPL configuration
  doc: update QEMU RISC-V documentation

 Kconfig |   4 +-
 Makefile|   8 +-
 arch/Kconfig|   6 ++
 arch/riscv/Kconfig  |  36 +++--
 arch/riscv/cpu/ax25/Kconfig |   6 +-
 arch/riscv/cpu/cpu.c|   6 +-
 arch/riscv/cpu/generic/Kconfig  |   5 +-
 arch/riscv/cpu/start.S  |  62 ++-
 arch/riscv/cpu/u-boot-spl.lds   |  82 +++
 arch/riscv/include/asm/encoding.h   |   2 +-
 arch/riscv/include/asm/spl.h|  31 
 arch/riscv/lib/Makefile |   8 +-
 arch/riscv/lib/mkimage_fit_opensbi.sh   | 100 
 arch/riscv/lib/spl.c|  48 
 board/emulation/qemu-riscv/Kconfig  |  10 +++
 board/emulation/qemu-riscv/MAINTAINERS  |   2 +
 board/emulation/qemu-riscv/qemu-riscv.c |  17 
 common/image.c  |   1 +
 common/spl/Kconfig  |  17 
 common/spl/Makefile |   1 +
 common/spl/spl.c|   8 +-
 common/spl/spl_fit.c|  37 ++---
 common/spl/spl_opensbi.c|  85 
 configs/qemu-riscv32_spl_defconfig  |  11 +++
 configs/qemu-riscv64_spl_defconfig  |  12 +++
 doc/board/emulation/qemu-riscv.rst  |  60 +-
 include/configs/qemu-riscv.h|  14 
 include/fdtdec.h|   2 +-
 include/image.h |   1 +
 include/opensbi.h   |  40 ++
 include/spl.h   |   5 ++
 lib/fdtdec.c|   6 +-
 32 files changed, 691 insertions(+), 42 deletions(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
 create mode 100644 arch/riscv/lib/spl.c
 create mode 100644 common/spl/spl_opensbi.c
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig
 create mode 100644 include/opensbi.h

-- 
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[U-Boot] [PATCH v2 08/11] riscv: add a generic FIT generator script

[Lukas Auer]

Add a generic FIT generator script for RISC-V to generate images
containing U-Boot, OpenSBI FW_DYNAMIC firmware, and optionally one or
more device trees. The location of the OpenSBI firmware binary can be
specified with the OPENSBI environment variable. By default, it is
assumed to be "fw_dynamic.bin" and located in the U-Boot top-level.
Device trees are passed as arguments to the generator script. A separate
configuration entry is created for each device tree.

The load addresses of U-Boot and OpenSBI are parsed from the U-Boot
configuration. They can be overwritten with the UBOOT_LOAD_ADDR and
OPENSBI_LOAD_ADDR environment variables.

The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh)
and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator
scripts.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 arch/riscv/lib/mkimage_fit_opensbi.sh | 100 ++
 1 file changed, 100 insertions(+)
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh

diff --git a/arch/riscv/lib/mkimage_fit_opensbi.sh 
b/arch/riscv/lib/mkimage_fit_opensbi.sh
new file mode 100755
index 00..d6f95e5bfd
--- /dev/null
+++ b/arch/riscv/lib/mkimage_fit_opensbi.sh
@@ -0,0 +1,100 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for RISC-V boards with OpenSBI
+# and, optionally, multiple device trees (given on the command line).
+#
+# usage: $0 [ [&2
+   OPENSBI=/dev/null
+fi
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+   description = "Configuration to load OpenSBI before U-Boot";
+
+   images {
+   uboot {
+   description = "U-Boot";
+   data = /incbin/("u-boot-nodtb.bin");
+   type = "standalone";
+   os = "U-Boot";
+   arch = "riscv";
+   compression = "none";
+   load = <$UBOOT_LOAD_ADDR>;
+   };
+   opensbi {
+   description = "RISC-V OpenSBI";
+   data = /incbin/("$OPENSBI");
+   type = "firmware";
+   os = "opensbi";
+   arch = "riscv";
+   compression = "none";
+   load = <$OPENSBI_LOAD_ADDR>;
+   entry = <$OPENSBI_LOAD_ADDR>;
+   };
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+   cat << __FDT_IMAGE_EOF
+   fdt_$cnt {
+   description = "$(basename $dtname .dtb)";
+   data = /incbin/("$dtname");
+   type = "flat_dt";
+   compression = "none";
+   };
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+   };
+   configurations {
+   default = "config_1";
+
+__CONF_HEADER_EOF
+
+if [ $# -eq 0 ]; then
+cat << __CONF_SECTION_EOF
+   config_1 {
+   description = "U-Boot FIT";
+   firmware = "opensbi";
+   loadables = "uboot";
+   };
+__CONF_SECTION_EOF
+else
+cnt=1
+for dtname in $*
+do
+cat << __CONF_SECTION_EOF
+   config_$cnt {
+   description = "$(basename $dtname .dtb)";
+   firmware = "opensbi";
+   loadables = "uboot";
+   fdt = "fdt_$cnt";
+   };
+__CONF_SECTION_EOF
+cnt=$((cnt+1))
+done
+fi
+
+cat << __ITS_EOF
+   };
+};
+__ITS_EOF
-- 
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[U-Boot] [PATCH v2 03/11] spl: fit: use U-Boot device tree when FIT image has no device tree

[Lukas Auer]

As part of the SPL FIT boot flow, the device tree is appended to U-Boot
proper. The device tree is used to record information on the loadables
to make them available to the SPL framework and U-Boot proper. Depending
on the U-Boot device tree provider, the FIT image might not include a
device tree. Information on the loadables is missing in this case.

When booting via firmware bundled with the FIT image, U-Boot SPL loads
the firmware binary and U-Boot proper before starting the firmware. The
firmware, in turn, is responsible for starting U-Boot proper.
Information on the memory location of the U-Boot proper loadable must be
available to the SPL framework so that it can be passed to the firmware
binary. To support this use case when no device tree is found in the FIT
image, fall back to the U-Boot device tree in this situation.

At the same time, update the comment to remove the note that the
destination address must be aligned to ARCH_DMA_MINALIGN. Alignment is
only required as an intermediate step when reading external data. This
is automatically handled by spl_fit_append_fdt(). After reading the
external data, it is copied to the specified address, which does not
have to be aligned to ARCH_DMA_MINALIGN.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 common/spl/spl_fit.c | 37 -
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 969f7775c1..0bfb91d686 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -11,6 +11,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_BOOTM_LEN
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)
 #endif
@@ -278,25 +280,34 @@ static int spl_fit_append_fdt(struct spl_image_info 
*spl_image,
  void *fit, int images, ulong base_offset)
 {
struct spl_image_info image_info;
-   int node, ret;
+   int node, ret = 0;
+
+   /*
+* Use the address following the image as target address for the
+* device tree.
+*/
+   image_info.load_addr = spl_image->load_addr + spl_image->size;
 
/* Figure out which device tree the board wants to use */
node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
if (node < 0) {
debug("%s: cannot find FDT node\n", __func__);
-   return node;
-   }
-
-   /*
-* Read the device tree and place it after the image.
-* Align the destination address to ARCH_DMA_MINALIGN.
-*/
-   image_info.load_addr = spl_image->load_addr + spl_image->size;
-   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
-_info);
 
-   if (ret < 0)
-   return ret;
+   /*
+* U-Boot did not find a device tree inside the FIT image. Use
+* the U-Boot device tree instead.
+*/
+   if (gd->fdt_blob)
+   memcpy((void *)image_info.load_addr, gd->fdt_blob,
+  fdt_totalsize(gd->fdt_blob));
+   else
+   return node;
+   } else {
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+_info);
+   if (ret < 0)
+   return ret;
+   }
 
/* Make the load-address of the FDT available for the SPL framework */
spl_image->fdt_addr = (void *)image_info.load_addr;
-- 
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[U-Boot] [PATCH v2 11/11] doc: update QEMU RISC-V documentation

[Lukas Auer]

The available defconfigs for RISC-V QEMU have changed. We now have
configurations to compile U-Boot to run in supervisor mode and for
U-Boot SPL. Update the QEMU RISC-V documentation to reflect these
changes.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2:
- Rebase on master and format documentation as reStructuredText

 doc/board/emulation/qemu-riscv.rst | 60 +-
 1 file changed, 59 insertions(+), 1 deletion(-)

diff --git a/doc/board/emulation/qemu-riscv.rst 
b/doc/board/emulation/qemu-riscv.rst
index 214833496b..9472a6f812 100644
--- a/doc/board/emulation/qemu-riscv.rst
+++ b/doc/board/emulation/qemu-riscv.rst
@@ -6,7 +6,8 @@ QEMU RISC-V
 
 QEMU for RISC-V supports a special 'virt' machine designed for emulation and
 virtualization purposes. This document describes how to run U-Boot under it.
-Both 32-bit 64-bit targets are supported.
+Both 32-bit and 64-bit targets are supported, running in either machine or
+supervisor mode.
 
 The QEMU virt machine models a generic RISC-V virtual machine with support for
 the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
@@ -28,6 +29,11 @@ Set the CROSS_COMPILE environment variable as usual, and run:
 make qemu-riscv64_defconfig
 make
 
+This will compile U-Boot for machine mode. To build supervisor mode binaries,
+use the configurations qemu-riscv32_smode_defconfig and
+qemu-riscv64_smode_defconfig instead. Note that U-Boot running in supervisor
+mode requires a supervisor binary interface (SBI), such as RISC-V OpenSBI.
+
 Running U-Boot
 --
 The minimal QEMU command line to get U-Boot up and running is:
@@ -46,4 +52,56 @@ parameter. For example, '-m 2G' creates 2GiB memory for the 
target,
 and the memory node in the embedded DTB created by QEMU reflects
 the new setting.
 
+For instructions on how to run U-Boot in supervisor mode on QEMU
+with OpenSBI, see the documentation available with OpenSBI:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
 These have been tested in QEMU 3.0.0.
+
+Running U-Boot SPL
+--
+In the default SPL configuration, U-Boot SPL starts in machine mode. U-Boot
+proper and OpenSBI (FW_DYNAMIC firmware) are bundled as FIT image and made
+available to U-Boot SPL. Both are then loaded by U-Boot SPL and the location
+of U-Boot proper is passed to OpenSBI. After initialization, U-Boot proper is
+started in supervisor mode by OpenSBI.
+
+OpenSBI must be compiled before compiling U-Boot. Clone the OpenSBI repository
+and run the following command.
+
+.. code-block:: console
+
+git clone https://github.com/riscv/opensbi.git
+cd opensbi
+make PLATFORM=qemu/virt
+
+See the OpenSBI documentation for full details:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
+To make the FW_DYNAMIC binary 
(build/platform/qemu/virt/firmware/fw_dynamic.bin)
+available to U-Boot, either copy it into the U-Boot root directory or specify
+its location with the OPENSBI environment variable. Afterwards, compile U-Boot
+with the following commands.
+
+- For 32-bit RISC-V::
+
+make qemu-riscv32_spl_defconfig
+make
+
+- For 64-bit RISC-V::
+
+make qemu-riscv64_spl_defconfig
+make
+
+The minimal QEMU commands to run U-Boot SPL in both 32-bit and 64-bit
+configurations are:
+
+- For 32-bit RISC-V::
+
+qemu-system-riscv32 -nographic -machine virt -kernel spl/u-boot-spl \
+-device loader,file=u-boot.itb,addr=0x8020
+
+- For 64-bit RISC-V::
+
+qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
+-device loader,file=u-boot.itb,addr=0x8020
-- 
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[U-Boot] [PATCH v2 10/11] riscv: qemu: add SPL configuration

[Lukas Auer]

Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
configurations are meant to help the development of SPL on RISC-V.

The configurations enable RAM as the only SPL boot device. Images must
be loaded at address 0x8020. In the default boot flow, U-Boot SPL
starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
then started in supervisor mode by OpenSBI.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 board/emulation/qemu-riscv/Kconfig  | 10 ++
 board/emulation/qemu-riscv/MAINTAINERS  |  2 ++
 board/emulation/qemu-riscv/qemu-riscv.c | 17 +
 configs/qemu-riscv32_spl_defconfig  | 11 +++
 configs/qemu-riscv64_spl_defconfig  | 12 
 include/configs/qemu-riscv.h| 14 ++
 6 files changed, 66 insertions(+)
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig

diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 6cc7c31dc6..1928d6dda0 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -13,13 +13,21 @@ config SYS_CONFIG_NAME
default "qemu-riscv"
 
 config SYS_TEXT_BASE
+   default 0x8120 if SPL
default 0x8000 if !RISCV_SMODE
default 0x8020 if RISCV_SMODE && ARCH_RV64I
default 0x8040 if RISCV_SMODE && ARCH_RV32I
 
+config SPL_TEXT_BASE
+   default 0x8000
+
+config SPL_OPENSBI_LOAD_ADDR
+   default 0x8100
+
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+   select SUPPORT_SPL
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
@@ -43,5 +51,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_PCI
imply E1000
imply NVME
+   imply SPL_RAM_SUPPORT
+   imply SPL_RAM_DEVICE
 
 endif
diff --git a/board/emulation/qemu-riscv/MAINTAINERS 
b/board/emulation/qemu-riscv/MAINTAINERS
index c701c83d77..78969ed6bd 100644
--- a/board/emulation/qemu-riscv/MAINTAINERS
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -5,5 +5,7 @@ F:  board/emulation/qemu-riscv/
 F: include/configs/qemu-riscv.h
 F: configs/qemu-riscv32_defconfig
 F: configs/qemu-riscv32_smode_defconfig
+F: configs/qemu-riscv32_spl_defconfig
 F: configs/qemu-riscv64_defconfig
 F: configs/qemu-riscv64_smode_defconfig
+F: configs/qemu-riscv64_spl_defconfig
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c 
b/board/emulation/qemu-riscv/qemu-riscv.c
index d6167aaef1..e04bd3001c 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -87,3 +88,19 @@ int ft_board_setup(void *blob, bd_t *bd)
 
return 0;
 }
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+   /* RISC-V QEMU only supports RAM as SPL boot device */
+   return BOOT_DEVICE_RAM;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   /* boot using first FIT config */
+   return 0;
+}
+#endif
diff --git a/configs/qemu-riscv32_spl_defconfig 
b/configs/qemu-riscv32_spl_defconfig
new file mode 100644
index 00..78e755b36a
--- /dev/null
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_spl_defconfig 
b/configs/qemu-riscv64_spl_defconfig
new file mode 100644
index 00..a3f5e29d58
--- /dev/null
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -0,0 +1,12 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index df22f780b0..69aa82d36a 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -8,6 +8,18 @@
 
 #include 
 
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE0x0010
+#define CONFIG_SPL_BSS_START_ADDR  0x8400
+#define CONFIG_SPL_BSS_MAX_SIZE0x0010
+#define CONFIG_SYS_SPL_MALLOC_START0x8410
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS0x8020
+
+#endif
+
 #define CONFIG_SYS_SDRAM_BASE  0x8000
 #define CONFIG_SYS_INIT_SP_ADDR

[U-Boot] [PATCH v2 04/11] riscv: add run mode configuration for SPL

[Lukas Auer]

U-Boot SPL can be run in a different privilege mode from U-Boot proper.
Add new configuration entries for SPL to allow the run mode to be
configured independently of U-Boot proper.

Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
configuration symbols to also cover the SPL equivalents. Ensure that
files compatible with only one privilege mode are not included in builds
targeting an incompatible privilege mode.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 arch/riscv/Kconfig| 33 ++-
 arch/riscv/cpu/ax25/Kconfig   |  6 +++---
 arch/riscv/cpu/cpu.c  |  6 +++---
 arch/riscv/cpu/generic/Kconfig|  2 +-
 arch/riscv/cpu/start.S|  6 +++---
 arch/riscv/include/asm/encoding.h |  2 +-
 arch/riscv/lib/Makefile   |  7 +--
 7 files changed, 44 insertions(+), 18 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8cfc7d0faa..b8d01ba8e1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,6 +113,23 @@ config RISCV_SMODE
 
 endchoice
 
+choice
+   prompt "SPL Run Mode"
+   default SPL_RISCV_MMODE
+   depends on SPL
+
+config SPL_RISCV_MMODE
+   bool "Machine"
+   help
+ Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+   bool "Supervisor"
+   help
+ Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
 config RISCV_ISA_C
bool "Emit compressed instructions"
default y
@@ -132,34 +149,40 @@ config 64BIT
 
 config SIFIVE_CLINT
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
 config ANDES_PLIC
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The Andes PLIC block holds memory-mapped claim and pending registers
  associated with software interrupt.
 
 config ANDES_PLMT
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The Andes PLMT block holds memory-mapped mtime register
  associated with timer tick.
 
 config RISCV_RDTIME
bool
-   default y if RISCV_SMODE
+   default y if RISCV_SMODE || SPL_RISCV_SMODE
help
  The provides the riscv_get_time() API that is implemented using the
  standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -189,7 +212,7 @@ config NR_CPUS
 
 config SBI_IPI
bool
-   default y if RISCV_SMODE
+   default y if RISCV_SMODE || SPL_RISCV_SMODE
depends on SMP
 
 config XIP
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e692..f4b59cb71d 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,8 +4,8 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
-   imply ANDES_PLIC if RISCV_MMODE
-   imply ANDES_PLMT if RISCV_MMODE
+   imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+   imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
help
  Run U-Boot on AndeStar V5 platforms and use some specific features
  which are provided by Andes Technology AndeStar V5 families.
@@ -14,7 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
help
  Provide Andes Technology AndeStar V5 families specific cache support.
 
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e9a8b437ed..ecf682c290 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -47,13 +47,13 @@ static inline bool supports_extension(char ext)
 
return false;
 #else  /* !CONFIG_CPU */
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
return csr_read(misa) & (1 << (ext - 'a'));
-#else  /* !CONFIG_RISCV_MMODE */
+#else  /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
return false;
-#endif /* CONFIG_RISCV_MMODE */
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
 #endif /* CONFIG_CPU */
 }
 
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfi

[U-Boot] [PATCH v2 07/11] riscv: support SPL stack and global data relocation

[Lukas Auer]

To support relocation of the stack and global data on RISC-V, the
secondary harts must be notified of the change using IPIs. We can reuse
the hart relocation code for this purpose. It uses global data to store
the new stack pointer and global data pointer for the secondary harts.
This means that we cannot update the global data pointer of the main
hart in spl_relocate_stack_gd(), because the secondary harts have not
yet been relocated at this point. It is updated after the secondary
harts have been notified.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 arch/riscv/cpu/start.S | 35 ++-
 common/spl/spl.c   |  2 +-
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index e053197645..e8c65c887a 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -170,13 +170,46 @@ wait_for_gd_init:
 spl_clear_bss:
la  t0, __bss_start
la  t1, __bss_end
-   beq t0, t1, spl_call_board_init_r
+   beq t0, t1, spl_stack_gd_setup
 
 spl_clear_bss_loop:
SREGzero, 0(t0)
addit0, t0, REGBYTES
bne t0, t1, spl_clear_bss_loop
 
+spl_stack_gd_setup:
+   jal spl_relocate_stack_gd
+
+   /* skip setup if we did not relocate */
+   beqza0, spl_call_board_init_r
+   mv  s0, a0
+
+   /* setup stack on main hart */
+#ifdef CONFIG_SMP
+   /* tp: hart id */
+   sllit0, tp, CONFIG_STACK_SIZE_SHIFT
+   sub sp, s0, t0
+#else
+   mv  sp, s0
+#endif
+
+   /* set new stack and global data pointer on secondary harts */
+spl_secondary_hart_stack_gd_setup:
+   la  a0, secondary_hart_relocate
+   mv  a1, s0
+   mv  a2, s0
+   jal smp_call_function
+
+   /* hang if relocation of secondary harts has failed */
+   beqza0, 1f
+   mv  a1, a0
+   la  a0, secondary_harts_relocation_error
+   jal printf
+   jal hang
+
+   /* set new global data pointer on main hart */
+1: mv  gp, s0
+
 spl_call_board_init_r:
mv  a0, zero
mv  a1, zero
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 1ed4741bdc..834f39908b 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -756,7 +756,7 @@ ulong spl_relocate_stack_gd(void)
 #if CONFIG_IS_ENABLED(DM)
dm_fixup_for_gd_move(new_gd);
 #endif
-#if !defined(CONFIG_ARM)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_RISCV)
gd = new_gd;
 #endif
return ptr;
-- 
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[U-Boot] [PATCH v2 09/11] riscv: set default FIT generator script and build target for SPL builds

[Lukas Auer]

Now that we have a generic FIT generator script for RISC-V, set it as
the default. To also build the FIT image by default, set the default
build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Kconfig b/Kconfig
index d2eb744e70..a78dd59a79 100644
--- a/Kconfig
+++ b/Kconfig
@@ -250,7 +250,8 @@ config BUILD_TARGET
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
-   default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI)
+   default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || \
+   ARCH_SUNXI || RISCV)
default "u-boot.kwb" if KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
help
@@ -463,6 +464,7 @@ config SPL_FIT_GENERATOR
depends on SPL_FIT
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && 
ARCH_ROCKCHIP
+   default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
  Specifies a (platform specific) script file to generate the FIT
  source file used to build the U-Boot FIT image file. This gets
-- 
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[U-Boot] [PATCH v2 06/11] riscv: add SPL support

[Lukas Auer]

U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
jumping to the image and via OpenSBI firmware. In the first case, both
U-Boot SPL and proper must be compiled to run in the same privilege
mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
mode and U-Boot proper for supervisor mode.

To be able to use SPL, boards have to provide a supported SPL boot
device.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 arch/Kconfig   |  6 +++
 arch/riscv/Kconfig |  3 ++
 arch/riscv/cpu/generic/Kconfig |  3 ++
 arch/riscv/cpu/start.S | 23 +-
 arch/riscv/cpu/u-boot-spl.lds  | 82 ++
 arch/riscv/include/asm/spl.h   | 31 +
 arch/riscv/lib/Makefile|  1 +
 arch/riscv/lib/spl.c   | 48 
 8 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100644 arch/riscv/lib/spl.c

diff --git a/arch/Kconfig b/arch/Kconfig
index 949eb28dfa..8350d9b1ea 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -76,6 +76,12 @@ config RISCV
imply MTD
imply TIMER
imply CMD_DM
+   imply SPL_DM
+   imply SPL_OF_CONTROL
+   imply SPL_LIBCOMMON_SUPPORT
+   imply SPL_LIBGENERIC_SUPPORT
+   imply SPL_SERIAL_SUPPORT
+   imply SPL_TIMER
 
 config SANDBOX
bool "Sandbox"
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b8d01ba8e1..01975d7c60 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -226,4 +226,7 @@ config STACK_SIZE_SHIFT
int
default 13
 
+config SPL_LDSCRIPT
+   default "arch/riscv/cpu/u-boot-spl.lds"
+
 endmenu
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index b7552f539f..b2cb155d6d 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -10,3 +10,6 @@ config GENERIC_RISCV
imply RISCV_TIMER
imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply CMD_CPU
+   imply SPL_CPU_SUPPORT
+   imply SPL_OPENSBI
+   imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 08b9812c4d..e053197645 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -76,7 +76,11 @@ _start:
  */
 call_board_init_f:
li  t0, -16
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+   li  t1, CONFIG_SPL_STACK
+#else
li  t1, CONFIG_SYS_INIT_SP_ADDR
+#endif
and sp, t1, t0  /* force 16 byte alignment */
 
 call_board_init_f_0:
@@ -160,7 +164,24 @@ wait_for_gd_init:
 
mv  a0, zero/* a0 <-- boot_flags = 0 */
la  t5, board_init_f
-   jr  t5  /* jump to board_init_f() */
+   jalrt5  /* jump to board_init_f() */
+
+#ifdef CONFIG_SPL_BUILD
+spl_clear_bss:
+   la  t0, __bss_start
+   la  t1, __bss_end
+   beq t0, t1, spl_call_board_init_r
+
+spl_clear_bss_loop:
+   SREGzero, 0(t0)
+   addit0, t0, REGBYTES
+   bne t0, t1, spl_clear_bss_loop
+
+spl_call_board_init_r:
+   mv  a0, zero
+   mv  a1, zero
+   jal board_init_r
+#endif
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
new file mode 100644
index 00..32255d58de
--- /dev/null
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/riscv/cpu/u-boot.lds, which is
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ *
+ * and arch/mips/cpu/u-boot-spl.lds.
+ */
+MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+   LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+   . = ALIGN(4);
+   .text : {
+   arch/riscv/cpu/start.o  (.text)
+   *(.text*)
+   } > .spl_mem
+
+   . = ALIGN(4);
+   .rodata : {
+   *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+   } > .spl_mem
+
+   . = ALIGN(4);
+   .data : {
+   *(.data*)
+   } > .spl_mem
+   . = ALIGN(4);
+
+   .got : {
+   __got_start = .;
+   *(.got.plt) *(.got)
+   __got_end = .;
+   } > .spl_mem
+
+   . = ALIGN(4);
+
+   .u_boot_list : {
+   KEEP(*(SORT(.u_boot_list*)));
+   } > .spl_mem
+
+   . = ALIGN(4);
+
+   .binman_sym_table : {
+   __binman_sym_start = .;
+   KEEP(*(SORT(.binman_sym*)));
+   __binman_sym_end = .;
+   } > .spl_mem

[U-Boot] [PATCH v2 02/11] Makefile: support building SPL FIT images without device trees

[Lukas Auer]

When building a U-Boot FIT image, the device trees specified by the
board are unconditionally built for inclusion in the FIT image. However,
not all device tree providers, such as CONFIG_OF_PRIOR_STAGE, require a
device tree to be built and bundled with the U-Boot binary. They rely on
other mechanisms to provide the device tree to U-Boot. Compilation on
boards with these device tree providers fails, because they do not
specify a device tree.

Change the makefile rules to conditionally build the device trees if
either CONFIG_OF_SEPARATE or CONFIG_OF_EMBED is selected as device tree
provider.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 Makefile | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 704579bec1..84678b2c47 100644
--- a/Makefile
+++ b/Makefile
@@ -1263,7 +1263,9 @@ MKIMAGEFLAGS_u-boot.pbl = -n 
$(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
-   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin 
dts/dt.dtb,u-boot.bin) FORCE
+   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
+   $(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED),dts/dt.dtb) \
+   ,u-boot.bin) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
 
@@ -1273,7 +1275,9 @@ else
 MKIMAGEFLAGS_u-boot.itb = -E
 endif
 
-u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+u-boot.itb: u-boot-nodtb.bin \
+   $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED),dts/dt.dtb) \
+   $(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK)
 
-- 
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[U-Boot] [PATCH v2 01/11] fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL

[Lukas Auer]

The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being
used in U-Boot SPL. Change the logic to also make it available in U-Boot
SPL.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2: None

 include/fdtdec.h | 2 +-
 lib/fdtdec.c | 6 ++
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index e6c22dd5cd..635f53083b 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -54,7 +54,7 @@ struct bd_info;
 #define SPL_BUILD  0
 #endif
 
-#if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
+#ifdef CONFIG_OF_PRIOR_STAGE
 extern phys_addr_t prior_stage_fdt_address;
 #endif
 
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 3ee786b579..569ffd5987 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1533,16 +1533,14 @@ int fdtdec_setup(void)
puts("Failed to read control FDT\n");
return -1;
}
+# elif defined(CONFIG_OF_PRIOR_STAGE)
+   gd->fdt_blob = (void *)prior_stage_fdt_address;
 # endif
 # ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
-#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
-   gd->fdt_blob = (void *)prior_stage_fdt_address;
-#  else
gd->fdt_blob = map_sysmem
(env_get_ulong("fdtcontroladdr", 16,
   (unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
-#  endif
 # endif
 
 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
-- 
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[U-Boot] [RFC PATCH 05/11] spl: support booting via RISC-V OpenSBI

[Lukas Auer]

RISC-V OpenSBI is an open-source implementation of the RISC-V Supervisor
Binary Interface (SBI) specification. It is required by Linux and U-Boot
running in supervisor mode. This patch adds support for booting via the
OpenSBI FW_DYNAMIC firmware.

In this configuration, U-Boot SPL starts in machine mode. After loading
OpenSBI and U-Boot proper, it will start OpenSBI. All necessary
parameters are generated by U-Boot SPL and passed to OpenSBI. U-Boot
proper is started in supervisor mode by OpenSBI. Support for OpenSBI is
enabled with CONFIG_SPL_OPENSBI. An additional configuration entry,
CONFIG_SPL_OPENSBI_LOAD_ADDR, is used to specify the load address of the
OpenSBI firmware binary. It is not used directly in U-Boot and instead
is intended to make the value available to scripts such as FIT
configuration generators.

The header file include/opensbi.h is based on header files from the
OpenSBI project. They are recent, as of commit bae54f764570 ("firmware:
Add fw_dynamic firmware").

Signed-off-by: Lukas Auer 
---

 common/image.c   |  1 +
 common/spl/Kconfig   | 17 
 common/spl/Makefile  |  1 +
 common/spl/spl.c |  6 +++
 common/spl/spl_opensbi.c | 85 
 include/image.h  |  1 +
 include/opensbi.h| 40 +++
 include/spl.h|  5 +++
 8 files changed, 156 insertions(+)
 create mode 100644 common/spl/spl_opensbi.c
 create mode 100644 include/opensbi.h

diff --git a/common/image.c b/common/image.c
index 9f9538fac2..7c7353a989 100644
--- a/common/image.c
+++ b/common/image.c
@@ -125,6 +125,7 @@ static const table_entry_t uimage_os[] = {
 #if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC)
{   IH_OS_OPENRTOS, "openrtos", "OpenRTOS", },
 #endif
+   {   IH_OS_OPENSBI,  "opensbi",  "RISC-V OpenSBI",   },
 
{   -1, "", "", },
 };
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 5978fb2934..9043f7b7ec 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1112,6 +1112,23 @@ config SPL_OPTEE
  OP-TEE is an open source Trusted OS  which is loaded by SPL.
  More detail at: https://github.com/OP-TEE/optee_os
 
+config SPL_OPENSBI
+   bool "Support RISC-V OpenSBI"
+   depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE
+   help
+ OpenSBI is an open-source implementation of the RISC-V Supervisor 
Binary
+ Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC
+ firmware. It is loaded and started by U-Boot SPL.
+
+ More details are available at https://github.com/riscv/opensbi and
+ https://github.com/riscv/riscv-sbi-doc
+
+config SPL_OPENSBI_LOAD_ADDR
+   hex "OpenSBI load address"
+   depends on SPL_OPENSBI
+   help
+ Load address of the OpenSBI binary.
+
 config TPL
bool
depends on SUPPORT_TPL
diff --git a/common/spl/Makefile b/common/spl/Makefile
index d28de692dd..5ce6f4ae48 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
 obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
+obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o
 obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
 obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
 obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index d5e3f680f4..1ed4741bdc 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -659,6 +659,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
(void *)spl_image.entry_point);
break;
 #endif
+#if CONFIG_IS_ENABLED(OPENSBI)
+   case IH_OS_OPENSBI:
+   debug("Jumping to U-Boot via RISC-V OpenSBI\n");
+   spl_invoke_opensbi(_image);
+   break;
+#endif
 #ifdef CONFIG_SPL_OS_BOOT
case IH_OS_LINUX:
debug("Jumping to Linux\n");
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
new file mode 100644
index 00..a6b4480ed2
--- /dev/null
+++ b/common/spl/spl_opensbi.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer 
+ *
+ * Based on common/spl/spl_atf.c
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct fw_dynamic_info opensbi_info;
+
+static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+{
+   int fit_images_node, node;
+   const char *fit_os;
+
+   fit_images_node = fdt_path_offset(blob, "/fit-images");
+   if (fit_images_node < 0)
+   return -ENODEV;
+
+   fdt_for_e

[U-Boot] [RFC PATCH 00/11] SPL support for RISC-V

[Lukas Auer]

This series adds support for SPL to RISC-V U-Boot. Images can be booted
via OpenSBI (FW_DYNAMIC firmware) or by directly jumping to them. In the
former case, OpenSBI and U-Boot proper are bundled as a FIT image and
made available to U-Boot SPL. Currently, only the QEMU board enables
U-Boot SPL with a dedicated configuration. It uses RAM as SPL boot
device.

On many RISC-V CPUs, the device tree is provided to U-Boot by the
first stage bootloader. This requires changes to U-Boot SPL (patches 1,
2 and 3), which modify the behavior on other boards as well. To get
feedback on this, I am therefore sending this series as RFC first.

To test this series, OpenSBI has to be compiled first. The
fw_dynamic.bin binary must be copied into the U-Boot root directory.
Alternatively, the location of the binary can be specified with the
OPENSBI environment variable. U-Boot can then be build as normal using
the configuration qemu-riscv64_spl_defconfig for 64-bit builds or
qemu-riscv32_spl_defconfig for 32-bit builds. The outputs from the build
process are the U-Boot SPL binary (spl/u-boot-spl.bin) and the U-Boot
FIT image (u-boot.itb) containing U-Boot proper and OpenSBI.

U-Boot can be run in QEMU with the following command.

qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
-device loader,file=u-boot.itb,addr=0x8020


Lukas Auer (11):
  fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL
  Makefile: support building SPL FIT images without device trees
  spl: fit: use U-Boot device tree when FIT image has no device tree
  riscv: add run mode configuration for SPL
  spl: support booting via RISC-V OpenSBI
  riscv: add SPL support
  riscv: support SPL stack and global data relocation
  riscv: add a generic FIT generator script
  riscv: set default FIT generator script and build target for SPL
builds
  riscv: qemu: add SPL configuration
  doc: update QEMU RISC-V documentation

 Kconfig |   4 +-
 Makefile|   8 +-
 arch/Kconfig|   6 ++
 arch/riscv/Kconfig  |  36 +++--
 arch/riscv/cpu/ax25/Kconfig |   6 +-
 arch/riscv/cpu/cpu.c|   6 +-
 arch/riscv/cpu/generic/Kconfig  |   5 +-
 arch/riscv/cpu/start.S  |  62 ++-
 arch/riscv/cpu/u-boot-spl.lds   |  82 +++
 arch/riscv/include/asm/encoding.h   |   2 +-
 arch/riscv/include/asm/spl.h|  31 
 arch/riscv/lib/Makefile |   8 +-
 arch/riscv/lib/mkimage_fit_opensbi.sh   | 100 
 arch/riscv/lib/spl.c|  48 
 board/emulation/qemu-riscv/Kconfig  |  10 +++
 board/emulation/qemu-riscv/MAINTAINERS  |   2 +
 board/emulation/qemu-riscv/qemu-riscv.c |  17 
 common/image.c  |   1 +
 common/spl/Kconfig  |  17 
 common/spl/Makefile |   1 +
 common/spl/spl.c|   8 +-
 common/spl/spl_fit.c|  37 ++---
 common/spl/spl_opensbi.c|  85 
 configs/qemu-riscv32_spl_defconfig  |  11 +++
 configs/qemu-riscv64_spl_defconfig  |  12 +++
 doc/README.qemu-riscv   |  56 -
 include/configs/qemu-riscv.h|  14 
 include/fdtdec.h|   2 +-
 include/image.h |   1 +
 include/opensbi.h   |  40 ++
 include/spl.h   |   5 ++
 lib/fdtdec.c|   6 +-
 32 files changed, 687 insertions(+), 42 deletions(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
 create mode 100644 arch/riscv/lib/spl.c
 create mode 100644 common/spl/spl_opensbi.c
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig
 create mode 100644 include/opensbi.h

-- 
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[U-Boot] [RFC PATCH 11/11] doc: update QEMU RISC-V documentation

[Lukas Auer]

The available defconfigs for RISC-V QEMU have changed. We now have
configurations to compile U-Boot to run in supervisor mode and for
U-Boot SPL. Update the QEMU RISC-V documentation to reflect these
changes.

Signed-off-by: Lukas Auer 
---

 doc/README.qemu-riscv | 56 ++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/doc/README.qemu-riscv b/doc/README.qemu-riscv
index e2e4804917..5688084d36 100644
--- a/doc/README.qemu-riscv
+++ b/doc/README.qemu-riscv
@@ -7,7 +7,8 @@ U-Boot on QEMU's 'virt' machine on RISC-V
 
 QEMU for RISC-V supports a special 'virt' machine designed for emulation and
 virtualization purposes. This document describes how to run U-Boot under it.
-Both 32-bit 64-bit targets are supported.
+Both 32-bit and 64-bit targets are supported, running in either machine or
+supervisor mode.
 
 The QEMU virt machine models a generic RISC-V virtual machine with support for
 the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
@@ -27,6 +28,11 @@ Set the CROSS_COMPILE environment variable as usual, and run:
 make qemu-riscv64_defconfig
 make
 
+This will compile U-Boot for machine mode. To build supervisor mode binaries,
+use the configurations qemu-riscv32_smode_defconfig and
+qemu-riscv64_smode_defconfig instead. Note that U-Boot running in supervisor
+mode requires a supervisor binary interface (SBI), such as RISC-V OpenSBI.
+
 Running U-Boot
 --
 The minimal QEMU command line to get U-Boot up and running is:
@@ -43,4 +49,52 @@ parameter. For example, '-m 2G' creates 2GiB memory for the 
target,
 and the memory node in the embedded DTB created by QEMU reflects
 the new setting.
 
+For instructions on how to run U-Boot in supervisor mode on QEMU
+with OpenSBI, see the documentation available with OpenSBI:
+
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
 These have been tested in QEMU 3.0.0.
+
+Running U-Boot SPL
+--
+In the default SPL configuration, U-Boot SPL starts in machine mode. U-Boot
+proper and OpenSBI (FW_DYNAMIC firmware) are bundled as FIT image and made
+available to U-Boot SPL. Both are then loaded by U-Boot SPL and the location
+of U-Boot proper is passed to OpenSBI. After initialization, U-Boot proper is
+started in supervisor mode by OpenSBI.
+
+OpenSBI must be compiled before compiling U-Boot. Clone the OpenSBI repository
+and run the following command.
+
+git clone https://github.com/riscv/opensbi.git
+cd opensbi
+make PLATFORM=qemu/virt
+
+See the OpenSBI documentation for full details:
+
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
+To make the FW_DYNAMIC binary 
(build/platform/qemu/virt/firmware/fw_dynamic.bin)
+available to U-Boot, either copy it into the U-Boot root directory or specify
+its location with the OPENSBI environment variable. Afterwards, compile U-Boot
+with the following commands.
+
+- For 32-bit RISC-V:
+make qemu-riscv32_spl_defconfig
+make
+
+- For 64-bit RISC-V:
+make qemu-riscv64_spl_defconfig
+make
+
+The minimal QEMU commands to run U-Boot SPL in both 32-bit and 64-bit
+configurations are:
+
+- For 32-bit RISC-V:
+qemu-system-riscv32 -nographic -machine virt -kernel spl/u-boot-spl \
+-device loader,file=u-boot.itb,addr=0x8020
+
+- For 64-bit RISC-V:
+qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
+-device loader,file=u-boot.itb,addr=0x8020
-- 
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[U-Boot] [RFC PATCH 09/11] riscv: set default FIT generator script and build target for SPL builds

[Lukas Auer]

Now that we have a generic FIT generator script for RISC-V, set it as
the default. To also build the FIT image by default, set the default
build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled.

Signed-off-by: Lukas Auer 
---

 Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Kconfig b/Kconfig
index d2eb744e70..a78dd59a79 100644
--- a/Kconfig
+++ b/Kconfig
@@ -250,7 +250,8 @@ config BUILD_TARGET
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
-   default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI)
+   default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || \
+   ARCH_SUNXI || RISCV)
default "u-boot.kwb" if KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
help
@@ -463,6 +464,7 @@ config SPL_FIT_GENERATOR
depends on SPL_FIT
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && 
ARCH_ROCKCHIP
+   default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
  Specifies a (platform specific) script file to generate the FIT
  source file used to build the U-Boot FIT image file. This gets
-- 
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[U-Boot] [RFC PATCH 10/11] riscv: qemu: add SPL configuration

[Lukas Auer]

Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
configurations are meant to help the development of SPL on RISC-V.

The configurations enable RAM as the only SPL boot device. Images must
be loaded at address 0x8020. In the default boot flow, U-Boot SPL
starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
then started in supervisor mode by OpenSBI.

Signed-off-by: Lukas Auer 
---

 board/emulation/qemu-riscv/Kconfig  | 10 ++
 board/emulation/qemu-riscv/MAINTAINERS  |  2 ++
 board/emulation/qemu-riscv/qemu-riscv.c | 17 +
 configs/qemu-riscv32_spl_defconfig  | 11 +++
 configs/qemu-riscv64_spl_defconfig  | 12 
 include/configs/qemu-riscv.h| 14 ++
 6 files changed, 66 insertions(+)
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig

diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 6cc7c31dc6..1928d6dda0 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -13,13 +13,21 @@ config SYS_CONFIG_NAME
default "qemu-riscv"
 
 config SYS_TEXT_BASE
+   default 0x8120 if SPL
default 0x8000 if !RISCV_SMODE
default 0x8020 if RISCV_SMODE && ARCH_RV64I
default 0x8040 if RISCV_SMODE && ARCH_RV32I
 
+config SPL_TEXT_BASE
+   default 0x8000
+
+config SPL_OPENSBI_LOAD_ADDR
+   default 0x8100
+
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+   select SUPPORT_SPL
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
@@ -43,5 +51,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_PCI
imply E1000
imply NVME
+   imply SPL_RAM_SUPPORT
+   imply SPL_RAM_DEVICE
 
 endif
diff --git a/board/emulation/qemu-riscv/MAINTAINERS 
b/board/emulation/qemu-riscv/MAINTAINERS
index c701c83d77..78969ed6bd 100644
--- a/board/emulation/qemu-riscv/MAINTAINERS
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -5,5 +5,7 @@ F:  board/emulation/qemu-riscv/
 F: include/configs/qemu-riscv.h
 F: configs/qemu-riscv32_defconfig
 F: configs/qemu-riscv32_smode_defconfig
+F: configs/qemu-riscv32_spl_defconfig
 F: configs/qemu-riscv64_defconfig
 F: configs/qemu-riscv64_smode_defconfig
+F: configs/qemu-riscv64_spl_defconfig
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c 
b/board/emulation/qemu-riscv/qemu-riscv.c
index d6167aaef1..e04bd3001c 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -87,3 +88,19 @@ int ft_board_setup(void *blob, bd_t *bd)
 
return 0;
 }
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+   /* RISC-V QEMU only supports RAM as SPL boot device */
+   return BOOT_DEVICE_RAM;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   /* boot using first FIT config */
+   return 0;
+}
+#endif
diff --git a/configs/qemu-riscv32_spl_defconfig 
b/configs/qemu-riscv32_spl_defconfig
new file mode 100644
index 00..78e755b36a
--- /dev/null
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_spl_defconfig 
b/configs/qemu-riscv64_spl_defconfig
new file mode 100644
index 00..a3f5e29d58
--- /dev/null
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -0,0 +1,12 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index df22f780b0..69aa82d36a 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -8,6 +8,18 @@
 
 #include 
 
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE0x0010
+#define CONFIG_SPL_BSS_START_ADDR  0x8400
+#define CONFIG_SPL_BSS_MAX_SIZE0x0010
+#define CONFIG_SYS_SPL_MALLOC_START0x8410
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS0x8020
+
+#endif
+
 #define CONFIG_SYS_SDRAM_BASE  0x8000
 #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + SZ_2M)
 
@@ -22,6 +34,7 @@
 /* Envir

[U-Boot] [RFC PATCH 08/11] riscv: add a generic FIT generator script

[Lukas Auer]

Add a generic FIT generator script for RISC-V to generate images
containing U-Boot, OpenSBI FW_DYNAMIC firmware, and optionally one or
more device trees. The location of the OpenSBI firmware binary can be
specified with the OPENSBI environment variable. By default, it is
assumed to be "fw_dynamic.bin" and located in the U-Boot top-level.
Device trees are passed as arguments to the generator script. A separate
configuration entry is created for each device tree.

The load addresses of U-Boot and OpenSBI are parsed from the U-Boot
configuration. They can be overwritten with the UBOOT_LOAD_ADDR and
OPENSBI_LOAD_ADDR environment variables.

The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh)
and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator
scripts.

Signed-off-by: Lukas Auer 
---

 arch/riscv/lib/mkimage_fit_opensbi.sh | 100 ++
 1 file changed, 100 insertions(+)
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh

diff --git a/arch/riscv/lib/mkimage_fit_opensbi.sh 
b/arch/riscv/lib/mkimage_fit_opensbi.sh
new file mode 100755
index 00..d6f95e5bfd
--- /dev/null
+++ b/arch/riscv/lib/mkimage_fit_opensbi.sh
@@ -0,0 +1,100 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for RISC-V boards with OpenSBI
+# and, optionally, multiple device trees (given on the command line).
+#
+# usage: $0 [ [&2
+   OPENSBI=/dev/null
+fi
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+   description = "Configuration to load OpenSBI before U-Boot";
+
+   images {
+   uboot {
+   description = "U-Boot";
+   data = /incbin/("u-boot-nodtb.bin");
+   type = "standalone";
+   os = "U-Boot";
+   arch = "riscv";
+   compression = "none";
+   load = <$UBOOT_LOAD_ADDR>;
+   };
+   opensbi {
+   description = "RISC-V OpenSBI";
+   data = /incbin/("$OPENSBI");
+   type = "firmware";
+   os = "opensbi";
+   arch = "riscv";
+   compression = "none";
+   load = <$OPENSBI_LOAD_ADDR>;
+   entry = <$OPENSBI_LOAD_ADDR>;
+   };
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+   cat << __FDT_IMAGE_EOF
+   fdt_$cnt {
+   description = "$(basename $dtname .dtb)";
+   data = /incbin/("$dtname");
+   type = "flat_dt";
+   compression = "none";
+   };
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+   };
+   configurations {
+   default = "config_1";
+
+__CONF_HEADER_EOF
+
+if [ $# -eq 0 ]; then
+cat << __CONF_SECTION_EOF
+   config_1 {
+   description = "U-Boot FIT";
+   firmware = "opensbi";
+   loadables = "uboot";
+   };
+__CONF_SECTION_EOF
+else
+cnt=1
+for dtname in $*
+do
+cat << __CONF_SECTION_EOF
+   config_$cnt {
+   description = "$(basename $dtname .dtb)";
+   firmware = "opensbi";
+   loadables = "uboot";
+   fdt = "fdt_$cnt";
+   };
+__CONF_SECTION_EOF
+cnt=$((cnt+1))
+done
+fi
+
+cat << __ITS_EOF
+   };
+};
+__ITS_EOF
-- 
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[U-Boot] [RFC PATCH 07/11] riscv: support SPL stack and global data relocation

[Lukas Auer]

To support relocation of the stack and global data on RISC-V, the
secondary harts must be notified of the change using IPIs. We can reuse
the hart relocation code for this purpose. It uses global data to store
the new stack pointer and global data pointer for the secondary harts.
This means that we cannot update the global data pointer of the main
hart in spl_relocate_stack_gd(), because the secondary harts have not
yet been relocated at this point. It is updated after the secondary
harts have been notified.

Signed-off-by: Lukas Auer 
---

 arch/riscv/cpu/start.S | 35 ++-
 common/spl/spl.c   |  2 +-
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index e053197645..e8c65c887a 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -170,13 +170,46 @@ wait_for_gd_init:
 spl_clear_bss:
la  t0, __bss_start
la  t1, __bss_end
-   beq t0, t1, spl_call_board_init_r
+   beq t0, t1, spl_stack_gd_setup
 
 spl_clear_bss_loop:
SREGzero, 0(t0)
addit0, t0, REGBYTES
bne t0, t1, spl_clear_bss_loop
 
+spl_stack_gd_setup:
+   jal spl_relocate_stack_gd
+
+   /* skip setup if we did not relocate */
+   beqza0, spl_call_board_init_r
+   mv  s0, a0
+
+   /* setup stack on main hart */
+#ifdef CONFIG_SMP
+   /* tp: hart id */
+   sllit0, tp, CONFIG_STACK_SIZE_SHIFT
+   sub sp, s0, t0
+#else
+   mv  sp, s0
+#endif
+
+   /* set new stack and global data pointer on secondary harts */
+spl_secondary_hart_stack_gd_setup:
+   la  a0, secondary_hart_relocate
+   mv  a1, s0
+   mv  a2, s0
+   jal smp_call_function
+
+   /* hang if relocation of secondary harts has failed */
+   beqza0, 1f
+   mv  a1, a0
+   la  a0, secondary_harts_relocation_error
+   jal printf
+   jal hang
+
+   /* set new global data pointer on main hart */
+1: mv  gp, s0
+
 spl_call_board_init_r:
mv  a0, zero
mv  a1, zero
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 1ed4741bdc..834f39908b 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -756,7 +756,7 @@ ulong spl_relocate_stack_gd(void)
 #if CONFIG_IS_ENABLED(DM)
dm_fixup_for_gd_move(new_gd);
 #endif
-#if !defined(CONFIG_ARM)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_RISCV)
gd = new_gd;
 #endif
return ptr;
-- 
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[U-Boot] [RFC PATCH 06/11] riscv: add SPL support

[Lukas Auer]

U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
jumping to the image and via OpenSBI firmware. In the first case, both
U-Boot SPL and proper must be compiled to run in the same privilege
mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
mode and U-Boot proper for supervisor mode.

To be able to use SPL, boards have to provide a supported SPL boot
device.

Signed-off-by: Lukas Auer 
---

 arch/Kconfig   |  6 +++
 arch/riscv/Kconfig |  3 ++
 arch/riscv/cpu/generic/Kconfig |  3 ++
 arch/riscv/cpu/start.S | 23 +-
 arch/riscv/cpu/u-boot-spl.lds  | 82 ++
 arch/riscv/include/asm/spl.h   | 31 +
 arch/riscv/lib/Makefile|  1 +
 arch/riscv/lib/spl.c   | 48 
 8 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100644 arch/riscv/lib/spl.c

diff --git a/arch/Kconfig b/arch/Kconfig
index a946af816f..5462c9b933 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -76,6 +76,12 @@ config RISCV
imply MTD
imply TIMER
imply CMD_DM
+   imply SPL_DM
+   imply SPL_OF_CONTROL
+   imply SPL_LIBCOMMON_SUPPORT
+   imply SPL_LIBGENERIC_SUPPORT
+   imply SPL_SERIAL_SUPPORT
+   imply SPL_TIMER
 
 config SANDBOX
bool "Sandbox"
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b8d01ba8e1..01975d7c60 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -226,4 +226,7 @@ config STACK_SIZE_SHIFT
int
default 13
 
+config SPL_LDSCRIPT
+   default "arch/riscv/cpu/u-boot-spl.lds"
+
 endmenu
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index b7552f539f..b2cb155d6d 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -10,3 +10,6 @@ config GENERIC_RISCV
imply RISCV_TIMER
imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply CMD_CPU
+   imply SPL_CPU_SUPPORT
+   imply SPL_OPENSBI
+   imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 08b9812c4d..e053197645 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -76,7 +76,11 @@ _start:
  */
 call_board_init_f:
li  t0, -16
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+   li  t1, CONFIG_SPL_STACK
+#else
li  t1, CONFIG_SYS_INIT_SP_ADDR
+#endif
and sp, t1, t0  /* force 16 byte alignment */
 
 call_board_init_f_0:
@@ -160,7 +164,24 @@ wait_for_gd_init:
 
mv  a0, zero/* a0 <-- boot_flags = 0 */
la  t5, board_init_f
-   jr  t5  /* jump to board_init_f() */
+   jalrt5  /* jump to board_init_f() */
+
+#ifdef CONFIG_SPL_BUILD
+spl_clear_bss:
+   la  t0, __bss_start
+   la  t1, __bss_end
+   beq t0, t1, spl_call_board_init_r
+
+spl_clear_bss_loop:
+   SREGzero, 0(t0)
+   addit0, t0, REGBYTES
+   bne t0, t1, spl_clear_bss_loop
+
+spl_call_board_init_r:
+   mv  a0, zero
+   mv  a1, zero
+   jal board_init_r
+#endif
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
new file mode 100644
index 00..32255d58de
--- /dev/null
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/riscv/cpu/u-boot.lds, which is
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ *
+ * and arch/mips/cpu/u-boot-spl.lds.
+ */
+MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+   LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+   . = ALIGN(4);
+   .text : {
+   arch/riscv/cpu/start.o  (.text)
+   *(.text*)
+   } > .spl_mem
+
+   . = ALIGN(4);
+   .rodata : {
+   *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+   } > .spl_mem
+
+   . = ALIGN(4);
+   .data : {
+   *(.data*)
+   } > .spl_mem
+   . = ALIGN(4);
+
+   .got : {
+   __got_start = .;
+   *(.got.plt) *(.got)
+   __got_end = .;
+   } > .spl_mem
+
+   . = ALIGN(4);
+
+   .u_boot_list : {
+   KEEP(*(SORT(.u_boot_list*)));
+   } > .spl_mem
+
+   . = ALIGN(4);
+
+   .binman_sym_table : {
+   __binman_sym_start = .;
+   KEEP(*(SORT(.binman_sym*)));
+   __binman_sym_end = .;
+   } > .spl_mem
+
+   . = ALIGN(4);
+
+   /DISCARD/ : { *(.rela.pl

[U-Boot] [RFC PATCH 04/11] riscv: add run mode configuration for SPL

[Lukas Auer]

U-Boot SPL can be run in a different privilege mode from U-Boot proper.
Add new configuration entries for SPL to allow the run mode to be
configured independently of U-Boot proper.

Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
configuration symbols to also cover the SPL equivalents. Ensure that
files compatible with only one privilege mode are not included in builds
targeting an incompatible privilege mode.

Signed-off-by: Lukas Auer 
---

 arch/riscv/Kconfig| 33 ++-
 arch/riscv/cpu/ax25/Kconfig   |  6 +++---
 arch/riscv/cpu/cpu.c  |  6 +++---
 arch/riscv/cpu/generic/Kconfig|  2 +-
 arch/riscv/cpu/start.S|  6 +++---
 arch/riscv/include/asm/encoding.h |  2 +-
 arch/riscv/lib/Makefile   |  7 +--
 7 files changed, 44 insertions(+), 18 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8cfc7d0faa..b8d01ba8e1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,6 +113,23 @@ config RISCV_SMODE
 
 endchoice
 
+choice
+   prompt "SPL Run Mode"
+   default SPL_RISCV_MMODE
+   depends on SPL
+
+config SPL_RISCV_MMODE
+   bool "Machine"
+   help
+ Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+   bool "Supervisor"
+   help
+ Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
 config RISCV_ISA_C
bool "Emit compressed instructions"
default y
@@ -132,34 +149,40 @@ config 64BIT
 
 config SIFIVE_CLINT
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
 config ANDES_PLIC
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The Andes PLIC block holds memory-mapped claim and pending registers
  associated with software interrupt.
 
 config ANDES_PLMT
bool
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+   select SPL_REGMAP if SPL
+   select SPL_SYSCON if SPL
help
  The Andes PLMT block holds memory-mapped mtime register
  associated with timer tick.
 
 config RISCV_RDTIME
bool
-   default y if RISCV_SMODE
+   default y if RISCV_SMODE || SPL_RISCV_SMODE
help
  The provides the riscv_get_time() API that is implemented using the
  standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -189,7 +212,7 @@ config NR_CPUS
 
 config SBI_IPI
bool
-   default y if RISCV_SMODE
+   default y if RISCV_SMODE || SPL_RISCV_SMODE
depends on SMP
 
 config XIP
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e692..f4b59cb71d 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,8 +4,8 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
-   imply ANDES_PLIC if RISCV_MMODE
-   imply ANDES_PLMT if RISCV_MMODE
+   imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+   imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
help
  Run U-Boot on AndeStar V5 platforms and use some specific features
  which are provided by Andes Technology AndeStar V5 families.
@@ -14,7 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
-   depends on RISCV_MMODE
+   depends on RISCV_MMODE || SPL_RISCV_MMODE
help
  Provide Andes Technology AndeStar V5 families specific cache support.
 
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e9a8b437ed..ecf682c290 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -47,13 +47,13 @@ static inline bool supports_extension(char ext)
 
return false;
 #else  /* !CONFIG_CPU */
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
return csr_read(misa) & (1 << (ext - 'a'));
-#else  /* !CONFIG_RISCV_MMODE */
+#else  /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
return false;
-#endif /* CONFIG_RISCV_MMODE */
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
 #endif /* CONFIG_CPU */
 }
 
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index 1d6ab5032d..b7552f539f 100644
--- a/arch/riscv

[U-Boot] [RFC PATCH 03/11] spl: fit: use U-Boot device tree when FIT image has no device tree

[Lukas Auer]

As part of the SPL FIT boot flow, the device tree is appended to U-Boot
proper. The device tree is used to record information on the loadables
to make them available to the SPL framework and U-Boot proper. Depending
on the U-Boot device tree provider, the FIT image might not include a
device tree. Information on the loadables is missing in this case.

When booting via firmware bundled with the FIT image, U-Boot SPL loads
the firmware binary and U-Boot proper before starting the firmware. The
firmware, in turn, is responsible for starting U-Boot proper.
Information on the memory location of the U-Boot proper loadable must be
available to the SPL framework so that it can be passed to the firmware
binary. To support this use case when no device tree is found in the FIT
image, fall back to the U-Boot device tree in this situation.

At the same time, update the comment to remove the note that the
destination address must be aligned to ARCH_DMA_MINALIGN. Alignment is
only required as an intermediate step when reading external data. This
is automatically handled by spl_fit_append_fdt(). After reading the
external data, it is copied to the specified address, which does not
have to be aligned to ARCH_DMA_MINALIGN.

Signed-off-by: Lukas Auer 
---

 common/spl/spl_fit.c | 37 -
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 969f7775c1..0bfb91d686 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -11,6 +11,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_BOOTM_LEN
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)
 #endif
@@ -278,25 +280,34 @@ static int spl_fit_append_fdt(struct spl_image_info 
*spl_image,
  void *fit, int images, ulong base_offset)
 {
struct spl_image_info image_info;
-   int node, ret;
+   int node, ret = 0;
+
+   /*
+* Use the address following the image as target address for the
+* device tree.
+*/
+   image_info.load_addr = spl_image->load_addr + spl_image->size;
 
/* Figure out which device tree the board wants to use */
node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
if (node < 0) {
debug("%s: cannot find FDT node\n", __func__);
-   return node;
-   }
-
-   /*
-* Read the device tree and place it after the image.
-* Align the destination address to ARCH_DMA_MINALIGN.
-*/
-   image_info.load_addr = spl_image->load_addr + spl_image->size;
-   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
-_info);
 
-   if (ret < 0)
-   return ret;
+   /*
+* U-Boot did not find a device tree inside the FIT image. Use
+* the U-Boot device tree instead.
+*/
+   if (gd->fdt_blob)
+   memcpy((void *)image_info.load_addr, gd->fdt_blob,
+  fdt_totalsize(gd->fdt_blob));
+   else
+   return node;
+   } else {
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+_info);
+   if (ret < 0)
+   return ret;
+   }
 
/* Make the load-address of the FDT available for the SPL framework */
spl_image->fdt_addr = (void *)image_info.load_addr;
-- 
2.21.0

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[U-Boot] [RFC PATCH 02/11] Makefile: support building SPL FIT images without device trees

[Lukas Auer]

When building a U-Boot FIT image, the device trees specified by the
board are unconditionally built for inclusion in the FIT image. However,
not all device tree providers, such as CONFIG_OF_PRIOR_STAGE, require a
device tree to be built and bundled with the U-Boot binary. They rely on
other mechanisms to provide the device tree to U-Boot. Compilation on
boards with these device tree providers fails, because they do not
specify a device tree.

Change the makefile rules to conditionally build the device trees if
either CONFIG_OF_SEPARATE or CONFIG_OF_EMBED is selected as device tree
provider.

Signed-off-by: Lukas Auer 
---

 Makefile | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 73fdf70cdd..23f4a73b7a 100644
--- a/Makefile
+++ b/Makefile
@@ -1263,7 +1263,9 @@ MKIMAGEFLAGS_u-boot.pbl = -n 
$(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
-   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin 
dts/dt.dtb,u-boot.bin) FORCE
+   $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
+   $(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED),dts/dt.dtb) \
+   ,u-boot.bin) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
 
@@ -1273,7 +1275,9 @@ else
 MKIMAGEFLAGS_u-boot.itb = -E
 endif
 
-u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+u-boot.itb: u-boot-nodtb.bin \
+   $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED),dts/dt.dtb) \
+   $(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK)
 
-- 
2.21.0

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[U-Boot] [RFC PATCH 01/11] fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL

[Lukas Auer]

The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being
used in U-Boot SPL. Change the logic to also make it available in U-Boot
SPL.

Signed-off-by: Lukas Auer 
---

 include/fdtdec.h | 2 +-
 lib/fdtdec.c | 6 ++
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index e6c22dd5cd..635f53083b 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -54,7 +54,7 @@ struct bd_info;
 #define SPL_BUILD  0
 #endif
 
-#if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
+#ifdef CONFIG_OF_PRIOR_STAGE
 extern phys_addr_t prior_stage_fdt_address;
 #endif
 
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 3ee786b579..569ffd5987 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1533,16 +1533,14 @@ int fdtdec_setup(void)
puts("Failed to read control FDT\n");
return -1;
}
+# elif defined(CONFIG_OF_PRIOR_STAGE)
+   gd->fdt_blob = (void *)prior_stage_fdt_address;
 # endif
 # ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
-#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
-   gd->fdt_blob = (void *)prior_stage_fdt_address;
-#  else
gd->fdt_blob = map_sysmem
(env_get_ulong("fdtcontroladdr", 16,
   (unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
-#  endif
 # endif
 
 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
-- 
2.21.0

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[U-Boot] [PATCH] simple-bus: add DM_FLAG_PRE_RELOC flag to simple-bus driver

[Lukas Auer]

Boards such as qemu-riscv, which receive their device tree at runtime,
for example from QEMU or firmware, are unable to add the appropriate
device tree properties to make devices available pre relocation.
Instead, they must rely on the DM_FLAG_PRE_RELOC flag to be set for the
required drivers.

Add the DM_FLAG_PRE_RELOC flag to the simple-bus driver to make devices
under it with drivers that have set the flag as well available pre
relocation for these boards.

Signed-off-by: Lukas Auer 
---

 drivers/core/simple-bus.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c
index e16d8a9ff4..7fc23ef82d 100644
--- a/drivers/core/simple-bus.c
+++ b/drivers/core/simple-bus.c
@@ -60,4 +60,5 @@ U_BOOT_DRIVER(simple_bus_drv) = {
.name   = "generic_simple_bus",
.id = UCLASS_SIMPLE_BUS,
.of_match = generic_simple_bus_ids,
+   .flags  = DM_FLAG_PRE_RELOC,
 };
-- 
2.20.1

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[U-Boot] [PATCH v3 09/11] riscv: hang if relocation of secondary harts fails

[Lukas Auer]

Print an error message and hang if smp_call_function() returns an error,
indicating that relocation of the secondary harts has failed.

Signed-off-by: Lukas Auer 
---

Changes in v3:
- New patch to hang if relocation of secondary harts fails

Changes in v2: None

 arch/riscv/cpu/start.S | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 5ac899b141..a4433fbd6b 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -33,6 +33,10 @@
 #define SYM_SIZE   0x18
 #endif
 
+.section .data
+secondary_harts_relocation_error:
+   .ascii "Relocation of secondary harts has failed, error %d\n"
+
 .section .text
 .globl _start
 _start:
@@ -274,8 +278,15 @@ relocate_secondary_harts:
mv  a2, s3
jal smp_call_function
 
+   /* hang if relocation of secondary harts has failed */
+   beqza0, 1f
+   mv  a1, a0
+   la  a0, secondary_harts_relocation_error
+   jal printf
+   jal hang
+
/* restore relocation offset */
-   mv  t6, s5
+1: mv  t6, s5
 #endif
 
 /*
-- 
2.20.1

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[U-Boot] [PATCH v3 07/11] riscv: boot images passed to bootm on all harts

[Lukas Auer]

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 arch/riscv/lib/bootm.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index f36b8702ef..efbd3e23e7 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -81,6 +82,9 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
void (*kernel)(ulong hart, void *dtb);
int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+#ifdef CONFIG_SMP
+   int ret;
+#endif
 
kernel = (void (*)(ulong, void *))images->ep;
 
@@ -92,8 +96,15 @@ static void boot_jump_linux(bootm_headers_t *images, int 
flag)
announce_and_cleanup(fake);
 
if (!fake) {
-   if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+   if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+#ifdef CONFIG_SMP
+   ret = smp_call_function(images->ep,
+   (ulong)images->ft_addr, 0);
+   if (ret)
+   hang();
+#endif
kernel(gd->arch.boot_hart, images->ft_addr);
+   }
}
 }
 
-- 
2.20.1

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[U-Boot] [PATCH v3 08/11] riscv: do not rely on hart ID passed by previous boot stage

[Lukas Auer]

RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
the previous boot stage. Machine mode firmware such as BBL and OpenSBI
do this when starting their payload (U-Boot) in supervisor mode. If
U-Boot is running in machine mode, this task must be handled by the boot
ROM. Explicitly populate register a0 with the hart ID from the mhartid
CSR to avoid possible problems on RISC-V processors with a boot ROM that
does not handle this task.

Suggested-by: Rick Chen 
Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Atish Patra 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Rick Chen 
Tested-by: Rick Chen 
---

Changes in v3: None
Changes in v2:
- New patch to populate register a0 with the hart ID from the mhartid
CSR in machine-mode

 arch/riscv/cpu/start.S | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index f55b8cbc37..5ac899b141 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -36,6 +36,10 @@
 .section .text
 .globl _start
 _start:
+#ifdef CONFIG_RISCV_MMODE
+   csrra0, mhartid
+#endif
+
/* save hart id and dtb pointer */
mv  tp, a0
mv  s1, a1
-- 
2.20.1

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[U-Boot] [PATCH v3 10/11] riscv: fu540: enable SMP

[Lukas Auer]

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
---

Changes in v3: None
Changes in v2:
- New patch to enable SMP on the SiFive FU540, which was previously sent
independently

 board/sifive/fu540/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 6be3d88144..f46437901d 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -38,5 +38,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply PHY_LIB
imply PHY_MSCC
imply SIFIVE_SERIAL
+   imply SMP
 
 endif
-- 
2.20.1

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[U-Boot] [PATCH v3 11/11] riscv: qemu: enable SMP

[Lukas Auer]

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 board/emulation/qemu-riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 88d07d568e..cf057e7de6 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -34,5 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply BOARD_LATE_INIT
imply OF_BOARD_SETUP
imply SIFIVE_SERIAL
+   imply SMP
 
 endif
-- 
2.20.1

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[U-Boot] [PATCH v3 03/11] riscv: implement IPI platform functions using SBI

[Lukas Auer]

The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.

This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
Reviewed-by: Atish Patra 
Tested-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 arch/riscv/Kconfig   |  5 +
 arch/riscv/lib/Makefile  |  1 +
 arch/riscv/lib/sbi_ipi.c | 25 +
 3 files changed, 31 insertions(+)
 create mode 100644 arch/riscv/lib/sbi_ipi.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4d7a115569..9da609b33b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -139,4 +139,9 @@ config NR_CPUS
  Stack memory is pre-allocated. U-Boot must therefore know the
  maximum number of CPUs that may be present.
 
+config SBI_IPI
+   bool
+   default y if RISCV_SMODE
+   depends on SMP
+
 endmenu
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 19370f9749..35dbf643e4 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-y  += interrupts.o
 obj-y  += reset.o
+obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 obj-y   += setjmp.o
 obj-$(CONFIG_SMP) += smp.o
 
diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
new file mode 100644
index 00..170346da68
--- /dev/null
+++ b/arch/riscv/lib/sbi_ipi.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer 
+ */
+
+#include 
+#include 
+
+int riscv_send_ipi(int hart)
+{
+   ulong mask;
+
+   mask = 1UL << hart;
+   sbi_send_ipi();
+
+   return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+   sbi_clear_ipi();
+
+   return 0;
+}
-- 
2.20.1

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[U-Boot] [PATCH v3 05/11] riscv: save hart ID in register tp instead of s0

[Lukas Auer]

The hart ID passed by the previous boot stage is currently stored in
register s0. If we divert the control flow inside a function, which is
required as part of multi-hart support, the function epilog may not be
called, clobbering register s0. Save the hart ID in the unallocatable
register tp instead to protect the hart ID.

Signed-off-by: Lukas Auer 
---

Changes in v3:
- New patch to save the hart ID in register tp instead of s0

Changes in v2: None

 arch/riscv/cpu/start.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a30f6f7194..bcc0ff696d 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -36,7 +36,7 @@
 .globl _start
 _start:
/* save hart id and dtb pointer */
-   mv  s0, a0
+   mv  tp, a0
mv  s1, a1
 
la  t0, trap_entry
@@ -64,7 +64,7 @@ call_board_init_f_0:
jal board_init_f_init_reserve
 
/* save the boot hart id to global_data */
-   SREGs0, GD_BOOT_HART(gp)
+   SREGtp, GD_BOOT_HART(gp)
 
/* Enable cache */
jal icache_enable
-- 
2.20.1

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[U-Boot] [PATCH v3 06/11] riscv: add support for multi-hart systems

[Lukas Auer]

On RISC-V, all harts boot independently. To be able to run on a
multi-hart system, U-Boot must be extended with the functionality to
manage all harts in the system. All harts entering U-Boot are registered
in the available_harts mask stored in global data. A hart lottery system
as used in the Linux kernel selects the hart U-Boot runs on. All other
harts are halted. U-Boot can delegate functions to them using
smp_call_function().

Every hart has a valid pointer to the global data structure and a 8KiB
stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT.

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v3:
- Adjust patch to use the new location of the hart ID (register tp)

Changes in v2:
- Implement hart lottery to pick main hart to run U-Boot
- Remove CONFIG_MAIN_HART as it is not required anymore
- Register available harts in the available_harts mask

 arch/riscv/Kconfig   |   4 ++
 arch/riscv/cpu/cpu.c |   9 ++-
 arch/riscv/cpu/start.S   | 134 ++-
 arch/riscv/include/asm/csr.h |   1 +
 arch/riscv/lib/asm-offsets.c |   1 +
 5 files changed, 147 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 9da609b33b..3a4470daf3 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -144,4 +144,8 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
 
+config STACK_SIZE_SHIFT
+   int
+   default 13
+
 endmenu
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e662140427..c32de8a4c3 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -12,10 +12,17 @@
 #include 
 
 /*
- * prior_stage_fdt_address must be stored in the data section since it is used
+ * The variables here must be stored in the data section since they are used
  * before the bss section is available.
  */
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+u32 hart_lottery __attribute__((section(".data"))) = 0;
+
+/*
+ * The main hart running U-Boot has acquired available_harts_lock until it has
+ * finished initialization of global data.
+ */
+u32 available_harts_lock = 1;
 
 static inline bool supports_extension(char ext)
 {
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bcc0ff696d..f55b8cbc37 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -45,6 +46,23 @@ _start:
/* mask all interrupts */
csrwMODE_PREFIX(ie), zero
 
+#ifdef CONFIG_SMP
+   /* check if hart is within range */
+   /* tp: hart id */
+   li  t0, CONFIG_NR_CPUS
+   bge tp, t0, hart_out_of_bounds_loop
+#endif
+
+#ifdef CONFIG_SMP
+   /* set xSIE bit to receive IPIs */
+#ifdef CONFIG_RISCV_MMODE
+   li  t0, MIE_MSIE
+#else
+   li  t0, SIE_SSIE
+#endif
+   csrsMODE_PREFIX(ie), t0
+#endif
+
 /*
  * Set stackpointer in internal/ex RAM to call board_init_f
  */
@@ -56,7 +74,30 @@ call_board_init_f:
 call_board_init_f_0:
mv  a0, sp
jal board_init_f_alloc_reserve
+
+   /*
+* Set global data pointer here for all harts, uninitialized at this
+* point.
+*/
+   mv  gp, a0
+
+   /* setup stack */
+#ifdef CONFIG_SMP
+   /* tp: hart id */
+   sllit0, tp, CONFIG_STACK_SIZE_SHIFT
+   sub sp, a0, t0
+#else
mv  sp, a0
+#endif
+
+   /*
+* Pick hart to initialize global data and run U-Boot. The other harts
+* wait for initialization to complete.
+*/
+   la  t0, hart_lottery
+   li  s2, 1
+   amoswap.w s2, t1, 0(t0)
+   bnezs2, wait_for_gd_init
 
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
@@ -66,6 +107,33 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
 
+   la  t0, available_harts_lock
+   fence   rw, w
+   amoswap.w zero, zero, 0(t0)
+
+wait_for_gd_init:
+   la  t0, available_harts_lock
+   li  t1, 1
+1: amoswap.w t1, t1, 0(t0)
+   fence   r, rw
+   bnezt1, 1b
+
+   /* register available harts in the available_harts mask */
+   li  t1, 1
+   sll t1, t1, tp
+   LREGt2, GD_AVAILABLE_HARTS(gp)
+   or  t2, t2, t1
+   SREGt2, GD_AVAILABLE_HARTS(gp)
+
+   fence   rw, w
+   amoswap.w zero, zero, 0(t0)
+
+   /*
+* Continue on hart lottery winner, others branch to
+* secondary_hart_loop.
+*/
+   bnezs2, secondary_hart_loop
+
/* Enable cache */
jal icache_enable
jal dcache_enable
@@ -95,7 +163,14 @@ relocate_code:
  *Set up the stack
  */
 stack_setup:
+#ifdef CONFIG_SMP
+   /* tp: hart id */
+   sllit0, tp, CONFIG_STACK_SIZE_SHIFT
+   sub  

[U-Boot] [PATCH v3 02/11] riscv: import the supervisor binary interface header file

[Lukas Auer]

Import the supervisor binary interface (SBI) header file from Linux
(arch/riscv/include/asm/sbi.h). The last change to it was in commit
6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI").

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
Reviewed-by: Atish Patra 
---

Changes in v3: None
Changes in v2: None

 arch/riscv/include/asm/sbi.h | 94 
 1 file changed, 94 insertions(+)
 create mode 100644 arch/riscv/include/asm/sbi.h

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
new file mode 100644
index 00..ced57defdd
--- /dev/null
+++ b/arch/riscv/include/asm/sbi.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ *
+ * Taken from Linux arch/riscv/include/asm/sbi.h
+ */
+
+#ifndef _ASM_RISCV_SBI_H
+#define _ASM_RISCV_SBI_H
+
+#include 
+
+#define SBI_SET_TIMER 0
+#define SBI_CONSOLE_PUTCHAR 1
+#define SBI_CONSOLE_GETCHAR 2
+#define SBI_CLEAR_IPI 3
+#define SBI_SEND_IPI 4
+#define SBI_REMOTE_FENCE_I 5
+#define SBI_REMOTE_SFENCE_VMA 6
+#define SBI_REMOTE_SFENCE_VMA_ASID 7
+#define SBI_SHUTDOWN 8
+
+#define SBI_CALL(which, arg0, arg1, arg2) ({   \
+   register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);   \
+   register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);   \
+   register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);   \
+   register uintptr_t a7 asm ("a7") = (uintptr_t)(which);  \
+   asm volatile ("ecall"   \
+ : "+r" (a0)   \
+ : "r" (a1), "r" (a2), "r" (a7)\
+ : "memory");  \
+   a0; \
+})
+
+/* Lazy implementations until SBI is finalized */
+#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
+#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
+#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
+
+static inline void sbi_console_putchar(int ch)
+{
+   SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
+}
+
+static inline int sbi_console_getchar(void)
+{
+   return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
+}
+
+static inline void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+   SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
+#else
+   SBI_CALL_1(SBI_SET_TIMER, stime_value);
+#endif
+}
+
+static inline void sbi_shutdown(void)
+{
+   SBI_CALL_0(SBI_SHUTDOWN);
+}
+
+static inline void sbi_clear_ipi(void)
+{
+   SBI_CALL_0(SBI_CLEAR_IPI);
+}
+
+static inline void sbi_send_ipi(const unsigned long *hart_mask)
+{
+   SBI_CALL_1(SBI_SEND_IPI, hart_mask);
+}
+
+static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+   SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+unsigned long start,
+unsigned long size)
+{
+   SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid)
+{
+   SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask);
+}
+
+#endif
-- 
2.20.1

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[U-Boot] [PATCH v3 04/11] riscv: delay initialization of caches and debug UART

[Lukas Auer]

Move the initialization of the caches and the debug UART until after
board_init_f_init_reserve. This is in preparation for SMP support, where
code prior to this point will be executed by all harts. This ensures
that initialization will only be performed once on the main hart running
U-Boot.

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 arch/riscv/cpu/start.S | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 81ea52b170..a30f6f7194 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -45,10 +45,6 @@ _start:
/* mask all interrupts */
csrwMODE_PREFIX(ie), zero
 
-   /* Enable cache */
-   jal icache_enable
-   jal dcache_enable
-
 /*
  * Set stackpointer in internal/ex RAM to call board_init_f
  */
@@ -57,10 +53,6 @@ call_board_init_f:
li  t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0  /* force 16 byte alignment */
 
-#ifdef CONFIG_DEBUG_UART
-   jal debug_uart_init
-#endif
-
 call_board_init_f_0:
mv  a0, sp
jal board_init_f_alloc_reserve
@@ -74,6 +66,14 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGs0, GD_BOOT_HART(gp)
 
+   /* Enable cache */
+   jal icache_enable
+   jal dcache_enable
+
+#ifdef CONFIG_DEBUG_UART
+   jal debug_uart_init
+#endif
+
mv  a0, zero/* a0 <-- boot_flags = 0 */
la  t5, board_init_f
jr  t5  /* jump to board_init_f() */
-- 
2.20.1

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[U-Boot] [PATCH v3 00/11] SMP support for RISC-V

[Lukas Auer]

This patch series adds SMP support for RISC-V to U-Boot. It allows
U-Boot to run on multi-hart systems (hart is the RISC-V terminology for
hardware thread). Images passed to bootm will be started on all harts.
The bootm command is currently the only one that will boot images on all
harts, bootefi is not yet supported.

The patches have been successfully tested on both QEMU (machine and
supervisor mode) and the HiFive Unleashed board (supervisor mode), using
BBL and OpenSBI.
Mainline QEMU requires two patches [1, 2] to run in this configuration.
Patch [1] has been dropped and will be replaced with a U-Boot patch.

[1]: https://patchwork.ozlabs.org/patch/1039493/
[2]: https://patchwork.ozlabs.org/patch/1039082/

Changes in v3:
- Print error if riscv_send_ipi() fails
- Adjust error message for failures of riscv_clear_ipi() to match error
message for failures of riscv_send_ipi()
- New patch to save the hart ID in register tp instead of s0
- Adjust patch to use the new location of the hart ID (register tp)
- New patch to hang if relocation of secondary harts fails

Changes in v2:
- Remove unneeded quotes from NR_CPUS Kconfig entry
- Move memory barrier from send_ipi_many() to handle_ipi()
- Add check in send_ipi_many so that IPIs are only sent to available
harts as indicated by the available_harts mask
- Implement hart lottery to pick main hart to run U-Boot
- Remove CONFIG_MAIN_HART as it is not required anymore
- Register available harts in the available_harts mask
- New patch to populate register a0 with the hart ID from the mhartid
CSR in machine-mode
- New patch to enable SMP on the SiFive FU540, which was previously sent
independently

Lukas Auer (11):
  riscv: add infrastructure for calling functions on other harts
  riscv: import the supervisor binary interface header file
  riscv: implement IPI platform functions using SBI
  riscv: delay initialization of caches and debug UART
  riscv: save hart ID in register tp instead of s0
  riscv: add support for multi-hart systems
  riscv: boot images passed to bootm on all harts
  riscv: do not rely on hart ID passed by previous boot stage
  riscv: hang if relocation of secondary harts fails
  riscv: fu540: enable SMP
  riscv: qemu: enable SMP

 arch/riscv/Kconfig   |  28 +
 arch/riscv/cpu/cpu.c |   9 +-
 arch/riscv/cpu/start.S   | 167 +--
 arch/riscv/include/asm/csr.h |   1 +
 arch/riscv/include/asm/global_data.h |   6 +
 arch/riscv/include/asm/sbi.h |  94 +++
 arch/riscv/include/asm/smp.h |  53 +
 arch/riscv/lib/Makefile  |   2 +
 arch/riscv/lib/asm-offsets.c |   1 +
 arch/riscv/lib/bootm.c   |  13 ++-
 arch/riscv/lib/sbi_ipi.c |  25 
 arch/riscv/lib/smp.c | 118 +++
 board/emulation/qemu-riscv/Kconfig   |   1 +
 board/sifive/fu540/Kconfig   |   1 +
 14 files changed, 507 insertions(+), 12 deletions(-)
 create mode 100644 arch/riscv/include/asm/sbi.h
 create mode 100644 arch/riscv/include/asm/smp.h
 create mode 100644 arch/riscv/lib/sbi_ipi.c
 create mode 100644 arch/riscv/lib/smp.c

-- 
2.20.1

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[U-Boot] [PATCH v3 01/11] riscv: add infrastructure for calling functions on other harts

[Lukas Auer]

Harts on RISC-V boot independently, U-Boot is responsible for managing
them. Functions are called on other harts with smp_call_function(),
which sends inter-processor interrupts (IPIs) to all other available
harts. Available harts are those marked as available in the device tree
and present in the available_harts mask stored in global data. The
available_harts mask is used to register all harts that have entered
U-Boot. Functions are specified with their address and two function
arguments (argument 2 and 3). The first function argument is always the
hart ID of the hart calling the function. On the other harts, the IPI
interrupt handler handle_ipi() must be called on software interrupts to
handle the request and call the specified function.

Functions are stored in the ipi_data data structure. Every hart has its
own data structure in global data. While this is not required at the
moment (all harts are expected to boot Linux), this does allow future
expansion, where other harts may be used for monitoring or other tasks.

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v3:
- Print error if riscv_send_ipi() fails
- Adjust error message for failures of riscv_clear_ipi() to match error
message for failures of riscv_send_ipi()

Changes in v2:
- Remove unneeded quotes from NR_CPUS Kconfig entry
- Move memory barrier from send_ipi_many() to handle_ipi()
- Add check in send_ipi_many so that IPIs are only sent to available
harts as indicated by the available_harts mask

 arch/riscv/Kconfig   |  19 +
 arch/riscv/include/asm/global_data.h |   6 ++
 arch/riscv/include/asm/smp.h |  53 
 arch/riscv/lib/Makefile  |   1 +
 arch/riscv/lib/smp.c | 118 +++
 5 files changed, 197 insertions(+)
 create mode 100644 arch/riscv/include/asm/smp.h
 create mode 100644 arch/riscv/lib/smp.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 36512a8995..4d7a115569 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -120,4 +120,23 @@ config RISCV_RDTIME
 config SYS_MALLOC_F_LEN
default 0x1000
 
+config SMP
+   bool "Symmetric Multi-Processing"
+   help
+ This enables support for systems with more than one CPU. If
+ you say N here, U-Boot will run on single and multiprocessor
+ machines, but will use only one CPU of a multiprocessor
+ machine. If you say Y here, U-Boot will run on many, but not
+ all, single processor machines.
+
+config NR_CPUS
+   int "Maximum number of CPUs (2-32)"
+   range 2 32
+   depends on SMP
+   default 8
+   help
+ On multiprocessor machines, U-Boot sets up a stack for each CPU.
+ Stack memory is pre-allocated. U-Boot must therefore know the
+ maximum number of CPUs that may be present.
+
 endmenu
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index a3a342c6e1..80e3165e39 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -10,12 +10,18 @@
 #ifndef__ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
 
+#include 
+
 /* Architecture-specific global data */
 struct arch_global_data {
long boot_hart; /* boot hart id */
 #ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint;/* clint base address */
 #endif
+#ifdef CONFIG_SMP
+   struct ipi_data ipi[CONFIG_NR_CPUS];
+#endif
+   ulong available_harts;
 };
 
 #include 
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
new file mode 100644
index 00..bc863fdbaf
--- /dev/null
+++ b/arch/riscv/include/asm/smp.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer 
+ */
+
+#ifndef _ASM_RISCV_SMP_H
+#define _ASM_RISCV_SMP_H
+
+/**
+ * struct ipi_data - Inter-processor interrupt (IPI) data structure
+ *
+ * IPIs are used for SMP support to communicate to other harts what function to
+ * call. Functions are in the form
+ * void (*addr)(ulong hart, ulong arg0, ulong arg1).
+ *
+ * The function address and the two arguments, arg0 and arg1, are stored in the
+ * IPI data structure. The hart ID is inserted by the hart handling the IPI and
+ * calling the function.
+ *
+ * @addr: Address of function
+ * @arg0: First argument of function
+ * @arg1: Second argument of function
+ */
+struct ipi_data {
+   ulong addr;
+   ulong arg0;
+   ulong arg1;
+};
+
+/**
+ * handle_ipi() - interrupt handler for software interrupts
+ *
+ * The IPI interrupt handler must be called to handle software interrupts. It
+ * calls the function specified in the hart's IPI data structure.
+ *
+ * @hart: Hart ID of the current hart
+ */
+void handle_ipi(ulong hart);
+
+/**
+ * smp_call_function() - Call a function on all other harts
+ *
+ * Send IPIs with the specified function call to all harts.
+ 

[U-Boot] [PATCH v2 6/9] riscv: boot images passed to bootm on all harts

[Lukas Auer]

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/riscv/lib/bootm.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index f36b8702ef..efbd3e23e7 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -81,6 +82,9 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
void (*kernel)(ulong hart, void *dtb);
int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+#ifdef CONFIG_SMP
+   int ret;
+#endif
 
kernel = (void (*)(ulong, void *))images->ep;
 
@@ -92,8 +96,15 @@ static void boot_jump_linux(bootm_headers_t *images, int 
flag)
announce_and_cleanup(fake);
 
if (!fake) {
-   if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+   if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+#ifdef CONFIG_SMP
+   ret = smp_call_function(images->ep,
+   (ulong)images->ft_addr, 0);
+   if (ret)
+   hang();
+#endif
kernel(gd->arch.boot_hart, images->ft_addr);
+   }
}
 }
 
-- 
2.20.1

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[U-Boot] [PATCH v2 8/9] riscv: fu540: enable SMP

[Lukas Auer]

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
---

Changes in v2:
- New patch to enable SMP on the SiFive FU540, which was previously sent
independently

 board/sifive/fu540/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 6be3d88144..f46437901d 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -38,5 +38,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply PHY_LIB
imply PHY_MSCC
imply SIFIVE_SERIAL
+   imply SMP
 
 endif
-- 
2.20.1

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[U-Boot] [PATCH v2 7/9] riscv: do not rely on hart ID passed by previous boot stage

[Lukas Auer]

RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
the previous boot stage. Machine mode firmware such as BBL and OpenSBI
do this when starting their payload (U-Boot) in supervisor mode. If
U-Boot is running in machine mode, this task must be handled by the boot
ROM. Explicitly populate register a0 with the hart ID from the mhartid
CSR to avoid possible problems on RISC-V processors with a boot ROM that
does not handle this task.

Suggested-by: Rick Chen 
Signed-off-by: Lukas Auer 
---

Changes in v2:
- New patch to populate register a0 with the hart ID from the mhartid
CSR in machine-mode

 arch/riscv/cpu/start.S | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 79b753847c..d4daa6e0bf 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -36,6 +36,10 @@
 .section .text
 .globl _start
 _start:
+#ifdef CONFIG_RISCV_MMODE
+   csrra0, mhartid
+#endif
+
/* save hart id and dtb pointer */
mv  s0, a0
mv  s1, a1
-- 
2.20.1

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[U-Boot] [PATCH v2 3/9] riscv: implement IPI platform functions using SBI

[Lukas Auer]

The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.

This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/riscv/Kconfig   |  5 +
 arch/riscv/lib/Makefile  |  1 +
 arch/riscv/lib/sbi_ipi.c | 25 +
 3 files changed, 31 insertions(+)
 create mode 100644 arch/riscv/lib/sbi_ipi.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4d7a115569..9da609b33b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -139,4 +139,9 @@ config NR_CPUS
  Stack memory is pre-allocated. U-Boot must therefore know the
  maximum number of CPUs that may be present.
 
+config SBI_IPI
+   bool
+   default y if RISCV_SMODE
+   depends on SMP
+
 endmenu
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 19370f9749..35dbf643e4 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-y  += interrupts.o
 obj-y  += reset.o
+obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 obj-y   += setjmp.o
 obj-$(CONFIG_SMP) += smp.o
 
diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
new file mode 100644
index 00..170346da68
--- /dev/null
+++ b/arch/riscv/lib/sbi_ipi.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer 
+ */
+
+#include 
+#include 
+
+int riscv_send_ipi(int hart)
+{
+   ulong mask;
+
+   mask = 1UL << hart;
+   sbi_send_ipi();
+
+   return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+   sbi_clear_ipi();
+
+   return 0;
+}
-- 
2.20.1

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[U-Boot] [PATCH v2 9/9] riscv: qemu: enable SMP

[Lukas Auer]

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 board/emulation/qemu-riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 88d07d568e..cf057e7de6 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -34,5 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply BOARD_LATE_INIT
imply OF_BOARD_SETUP
imply SIFIVE_SERIAL
+   imply SMP
 
 endif
-- 
2.20.1

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[U-Boot] [PATCH v2 5/9] riscv: add support for multi-hart systems

[Lukas Auer]

On RISC-V, all harts boot independently. To be able to run on a
multi-hart system, U-Boot must be extended with the functionality to
manage all harts in the system. All harts entering U-Boot are registered
in the available_harts mask stored in global data. A hart lottery system
as used in the Linux kernel selects the hart U-Boot runs on. All other
harts are halted. U-Boot can delegate functions to them using
smp_call_function().

Every hart has a valid pointer to the global data structure and a 8KiB
stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT.

Signed-off-by: Lukas Auer 
---

Changes in v2:
- Implement hart lottery to pick main hart to run U-Boot
- Remove CONFIG_MAIN_HART as it is not required anymore
- Register available harts in the available_harts mask

 arch/riscv/Kconfig   |   4 ++
 arch/riscv/cpu/cpu.c |   9 ++-
 arch/riscv/cpu/start.S   | 134 ++-
 arch/riscv/include/asm/csr.h |   1 +
 arch/riscv/lib/asm-offsets.c |   1 +
 5 files changed, 147 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 9da609b33b..3a4470daf3 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -144,4 +144,8 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
 
+config STACK_SIZE_SHIFT
+   int
+   default 13
+
 endmenu
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e662140427..c32de8a4c3 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -12,10 +12,17 @@
 #include 
 
 /*
- * prior_stage_fdt_address must be stored in the data section since it is used
+ * The variables here must be stored in the data section since they are used
  * before the bss section is available.
  */
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+u32 hart_lottery __attribute__((section(".data"))) = 0;
+
+/*
+ * The main hart running U-Boot has acquired available_harts_lock until it has
+ * finished initialization of global data.
+ */
+u32 available_harts_lock = 1;
 
 static inline bool supports_extension(char ext)
 {
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a30f6f7194..79b753847c 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -45,6 +46,23 @@ _start:
/* mask all interrupts */
csrwMODE_PREFIX(ie), zero
 
+#ifdef CONFIG_SMP
+   /* check if hart is within range */
+   /* s0: hart id */
+   li  t0, CONFIG_NR_CPUS
+   bge s0, t0, hart_out_of_bounds_loop
+#endif
+
+#ifdef CONFIG_SMP
+   /* set xSIE bit to receive IPIs */
+#ifdef CONFIG_RISCV_MMODE
+   li  t0, MIE_MSIE
+#else
+   li  t0, SIE_SSIE
+#endif
+   csrsMODE_PREFIX(ie), t0
+#endif
+
 /*
  * Set stackpointer in internal/ex RAM to call board_init_f
  */
@@ -56,7 +74,30 @@ call_board_init_f:
 call_board_init_f_0:
mv  a0, sp
jal board_init_f_alloc_reserve
+
+   /*
+* Set global data pointer here for all harts, uninitialized at this
+* point.
+*/
+   mv  gp, a0
+
+   /* setup stack */
+#ifdef CONFIG_SMP
+   /* s0: hart id */
+   sllit0, s0, CONFIG_STACK_SIZE_SHIFT
+   sub sp, a0, t0
+#else
mv  sp, a0
+#endif
+
+   /*
+* Pick hart to initialize global data and run U-Boot. The other harts
+* wait for initialization to complete.
+*/
+   la  t0, hart_lottery
+   li  s2, 1
+   amoswap.w s2, t1, 0(t0)
+   bnezs2, wait_for_gd_init
 
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
@@ -66,6 +107,33 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGs0, GD_BOOT_HART(gp)
 
+   la  t0, available_harts_lock
+   fence   rw, w
+   amoswap.w zero, zero, 0(t0)
+
+wait_for_gd_init:
+   la  t0, available_harts_lock
+   li  t1, 1
+1: amoswap.w t1, t1, 0(t0)
+   fence   r, rw
+   bnezt1, 1b
+
+   /* register available harts in the available_harts mask */
+   li  t1, 1
+   sll t1, t1, s0
+   LREGt2, GD_AVAILABLE_HARTS(gp)
+   or  t2, t2, t1
+   SREGt2, GD_AVAILABLE_HARTS(gp)
+
+   fence   rw, w
+   amoswap.w zero, zero, 0(t0)
+
+   /*
+* Continue on hart lottery winner, others branch to
+* secondary_hart_loop.
+*/
+   bnezs2, secondary_hart_loop
+
/* Enable cache */
jal icache_enable
jal dcache_enable
@@ -95,7 +163,14 @@ relocate_code:
  *Set up the stack
  */
 stack_setup:
+#ifdef CONFIG_SMP
+   /* s0: hart id */
+   sllit0, s0, CONFIG_STACK_SIZE_SHIFT
+   sub sp, s2, t0
+#else
mv  sp, s2
+#endif
+
la  t0, _start
sub t6, s4, t0  /* t6 <- relocation offset */

[U-Boot] [PATCH v2 2/9] riscv: import the supervisor binary interface header file

[Lukas Auer]

Import the supervisor binary interface (SBI) header file from Linux
(arch/riscv/include/asm/sbi.h). The last change to it was in commit
6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI").

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/riscv/include/asm/sbi.h | 94 
 1 file changed, 94 insertions(+)
 create mode 100644 arch/riscv/include/asm/sbi.h

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
new file mode 100644
index 00..ced57defdd
--- /dev/null
+++ b/arch/riscv/include/asm/sbi.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ *
+ * Taken from Linux arch/riscv/include/asm/sbi.h
+ */
+
+#ifndef _ASM_RISCV_SBI_H
+#define _ASM_RISCV_SBI_H
+
+#include 
+
+#define SBI_SET_TIMER 0
+#define SBI_CONSOLE_PUTCHAR 1
+#define SBI_CONSOLE_GETCHAR 2
+#define SBI_CLEAR_IPI 3
+#define SBI_SEND_IPI 4
+#define SBI_REMOTE_FENCE_I 5
+#define SBI_REMOTE_SFENCE_VMA 6
+#define SBI_REMOTE_SFENCE_VMA_ASID 7
+#define SBI_SHUTDOWN 8
+
+#define SBI_CALL(which, arg0, arg1, arg2) ({   \
+   register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);   \
+   register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);   \
+   register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);   \
+   register uintptr_t a7 asm ("a7") = (uintptr_t)(which);  \
+   asm volatile ("ecall"   \
+ : "+r" (a0)   \
+ : "r" (a1), "r" (a2), "r" (a7)\
+ : "memory");  \
+   a0; \
+})
+
+/* Lazy implementations until SBI is finalized */
+#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
+#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
+#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
+
+static inline void sbi_console_putchar(int ch)
+{
+   SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
+}
+
+static inline int sbi_console_getchar(void)
+{
+   return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
+}
+
+static inline void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+   SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
+#else
+   SBI_CALL_1(SBI_SET_TIMER, stime_value);
+#endif
+}
+
+static inline void sbi_shutdown(void)
+{
+   SBI_CALL_0(SBI_SHUTDOWN);
+}
+
+static inline void sbi_clear_ipi(void)
+{
+   SBI_CALL_0(SBI_CLEAR_IPI);
+}
+
+static inline void sbi_send_ipi(const unsigned long *hart_mask)
+{
+   SBI_CALL_1(SBI_SEND_IPI, hart_mask);
+}
+
+static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+   SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+unsigned long start,
+unsigned long size)
+{
+   SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid)
+{
+   SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask);
+}
+
+#endif
-- 
2.20.1

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[U-Boot] [PATCH v2 4/9] riscv: delay initialization of caches and debug UART

[Lukas Auer]

Move the initialization of the caches and the debug UART until after
board_init_f_init_reserve. This is in preparation for SMP support, where
code prior to this point will be executed by all harts. This ensures
that initialization will only be performed once for the main hart
running U-Boot.

Signed-off-by: Lukas Auer 
Reviewed-by: Anup Patel 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/riscv/cpu/start.S | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 81ea52b170..a30f6f7194 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -45,10 +45,6 @@ _start:
/* mask all interrupts */
csrwMODE_PREFIX(ie), zero
 
-   /* Enable cache */
-   jal icache_enable
-   jal dcache_enable
-
 /*
  * Set stackpointer in internal/ex RAM to call board_init_f
  */
@@ -57,10 +53,6 @@ call_board_init_f:
li  t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0  /* force 16 byte alignment */
 
-#ifdef CONFIG_DEBUG_UART
-   jal debug_uart_init
-#endif
-
 call_board_init_f_0:
mv  a0, sp
jal board_init_f_alloc_reserve
@@ -74,6 +66,14 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGs0, GD_BOOT_HART(gp)
 
+   /* Enable cache */
+   jal icache_enable
+   jal dcache_enable
+
+#ifdef CONFIG_DEBUG_UART
+   jal debug_uart_init
+#endif
+
mv  a0, zero/* a0 <-- boot_flags = 0 */
la  t5, board_init_f
jr  t5  /* jump to board_init_f() */
-- 
2.20.1

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