Re: [PATCH v2] board: rockchip: add ArmSoM Sige7 Rk3588 board

[Quentin Schulz]

Hi Jianfeng,

On 5/27/24 10:57 AM, Jianfeng Liu wrote:

Hi all,

However... it seems we'll likely need to also cherry-pick patches for
the GPU (should probably be straightforward as nothing would be using
the GPU anyway in U-Boot) and the USBDP PHY... but this one we would
need to update all -u-boot.dtsi for rk3588(s) boards that have it
already to make it use the new label/DT, make sure that the driver still
works... etc. Maybe not a small feat, but someone will have to do it at
some point anyway :)

Kernel v6.10-rc1 is released and now u-boot is not synced to v6.9.


It is, please use the "next" branch.


What about syncing with this procedure:
1, Sync upstream dts to v6.9 with command update-dts-subtree.sh pull.
2, Cherrypick all commits of rk3588s.dtsi from v6.10-rc1.
3, Cherrypick all commits of rk3588*.dts* from v6.10-rc1, which will
include dts of new board armsom-sige7.
4, Add armsom-sige7 to u-boot.



You should be able to do 2,3,4 yourself now I believe?

Cheers,
Quentin

Re: [PATCH 2/2] rockchip: rk3588-edgeble: Add USB OTG support

[Quentin Schulz]

Hi Jagan,

On 5/27/24 10:57 AM, Jagan Teki wrote:

On Mon, 27 May 2024 at 14:17, Quentin Schulz  wrote:


Hi Jagan,

On 5/27/24 8:39 AM, Jagan Teki wrote:

Add support for USB OTG with UMS to program eMMC.

Add it for Edgeble NCM6A, NCM6B.

Signed-off-by: Jagan Teki 
---
   .../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi| 18 ++
   .../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi| 18 ++
   configs/neu6a-io-rk3588_defconfig  |  9 +
   configs/neu6b-io-rk3588_defconfig  |  9 +
   4 files changed, 54 insertions(+)

diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi 
b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index 88f3f7eee2..534d9f8a2c 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -15,3 +15,21 @@
   bus-width = <4>;
   status = "okay";
   };
+
+ {
+ status = "okay";
+};
+
+_otg {
+ status = "okay";
+};
+
+_phy0 {
+ status = "okay";
+};
+
+_host0_xhci {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi 
b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
index 289578803e..b3d17a60ce 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -15,3 +15,21 @@
   bus-width = <4>;
   status = "okay";
   };
+
+ {
+ status = "okay";
+};
+
+_otg {
+ status = "okay";
+};
+
+_phy0 {
+ status = "okay";
+};
+
+_host0_xhci {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ status = "okay";
+};


I don't see those patches in v6.10-rc1. Have you sent those to upstream
already? I assume we should cherry-pick patches in dts/upstream instead
of piling stuff up in u-boot.dtsis. This should also bring the patches
in rk3588(s).dtsi to add the missing bits for USB support we currently
have in rk3588*-u-boot.dtsi?


These are -u-boot.dtsi and nothing to do with dts/upstream and can be
removed or reconfigured once we sync the DT from Linux.



This answer seems to suggest there are no patches in the kernel yet. Do 
you not want working USB in Linux? Is something broken in Linux?


I think we're also aiming at only having U-Boot specific stuff in 
-u-boot.dtsi wherever we have OF_UPSTREAM enabled, and enabling USB 
doesn't seem to be typically the thing that should be U-Boot specific? I 
know that we have most rk3588/rk3588s boards with those nodes defined 
already, but they predates the move to OF_UPSTREAM.


As far as I remember, we've always asked people to upstream DT stuff 
they could upstream first and then import them in -u-boot.dtsi later, 
except for things that are U-Boot specific (e.g. different 
representation at a given point in time between U-Boot and kernel, or 
simple support in U-Boot but nothing in kernel yet). We could be a bit 
more aggressive with this policy now that we have dts/upstream as well. 
Ultimately this is up to Kever/Tom to decide where we want to go with 
this and how strict we want the policy to be.


Cheers,
Quentin

Re: [PATCH 2/2] rockchip: rk3588-edgeble: Add USB OTG support

[Quentin Schulz]

Hi Jagan,

On 5/27/24 8:39 AM, Jagan Teki wrote:

Add support for USB OTG with UMS to program eMMC.

Add it for Edgeble NCM6A, NCM6B.

Signed-off-by: Jagan Teki 
---
  .../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi| 18 ++
  .../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi| 18 ++
  configs/neu6a-io-rk3588_defconfig  |  9 +
  configs/neu6b-io-rk3588_defconfig  |  9 +
  4 files changed, 54 insertions(+)

diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi 
b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index 88f3f7eee2..534d9f8a2c 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -15,3 +15,21 @@
bus-width = <4>;
status = "okay";
  };
+
+ {
+   status = "okay";
+};
+
+_otg {
+   status = "okay";
+};
+
+_phy0 {
+   status = "okay";
+};
+
+_host0_xhci {
+   dr_mode = "peripheral";
+   maximum-speed = "high-speed";
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi 
b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
index 289578803e..b3d17a60ce 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -15,3 +15,21 @@
bus-width = <4>;
status = "okay";
  };
+
+ {
+   status = "okay";
+};
+
+_otg {
+   status = "okay";
+};
+
+_phy0 {
+   status = "okay";
+};
+
+_host0_xhci {
+   dr_mode = "peripheral";
+   maximum-speed = "high-speed";
+   status = "okay";
+};


I don't see those patches in v6.10-rc1. Have you sent those to upstream 
already? I assume we should cherry-pick patches in dts/upstream instead 
of piling stuff up in u-boot.dtsis. This should also bring the patches 
in rk3588(s).dtsi to add the missing bits for USB support we currently 
have in rk3588*-u-boot.dtsi?


Cheers,
Quentin

Re: [PATCH 1/2] arm64: dts: rockchip: Fix spl-boot-order for edgeble-ncm6b

[Quentin Schulz]

Hi Jagan,

On 5/27/24 8:39 AM, Jagan Teki wrote:

Edgeble NCM6B SoM has built-in eMMC so make sdhci has first boot
priority.

Fix it for NCM6A, NCM6B SoM.

Signed-off-by: Jagan Teki 
---
  arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi |  6 +-
  arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 11 ++-
  2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi 
b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index dd0058262b..88f3f7eee2 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -6,12 +6,8 @@
  #include "rk3588-u-boot.dtsi"
  
  / {

-   aliases {
-   mmc0 = 
-   };
-
chosen {
-   u-boot,spl-boot-order = 
+   u-boot,spl-boot-order = "same-as-spl", , 
};
  };
  
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi

index a45b3f5e86..289578803e 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -6,11 +6,12 @@
  #include "rk3588j-u-boot.dtsi"
  
  / {

-   aliases {
-   mmc0 = 
-   };
-
chosen {
-   u-boot,spl-boot-order = 
+   u-boot,spl-boot-order = "same-as-spl", , 
};
  };
+
+ {
+   bus-width = <4>;
+   status = "okay";
+};


The sdmmc parts are already part of 
dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts, are you 
sure this is actually needed?


Cheers,
Quentin

[PATCH 3/3] rockchip: theobroma: update URLs to point to CHERRY website

[Quentin Schulz]

From: Quentin Schulz 

Most of the current URLs should be redirected but some aren't already,
so let's anticipate more IT hiccups by migrating to new URLs.

Signed-off-by: Quentin Schulz 
---
 board/theobroma-systems/jaguar_rk3588/MAINTAINERS | 4 ++--
 board/theobroma-systems/puma_rk3399/MAINTAINERS   | 4 ++--
 board/theobroma-systems/ringneck_px30/MAINTAINERS | 3 ++-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS 
b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
index d14edadefe2..ab7051b427f 100644
--- a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
+++ b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
@@ -9,5 +9,5 @@ F:  doc/board/theobroma-systems/
 F: include/configs/jaguar_rk3588.h
 F: arch/arm/dts/rk3588-jaguar*
 F: configs/jaguar-rk3588_defconfig
-W: https://theobroma-systems.com/product/jaguar-sbc-rk3588/
-T: git git://git.theobroma-systems.com/jaguar-u-boot.git
+W: https://embedded.cherry.de/product/jaguar-sbc-rk3588/
+T: git git://git.embedded.cherry.de/jaguar-u-boot.git
diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS 
b/board/theobroma-systems/puma_rk3399/MAINTAINERS
index 2b409f16963..2536e348887 100644
--- a/board/theobroma-systems/puma_rk3399/MAINTAINERS
+++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS
@@ -8,5 +8,5 @@ F:  doc/board/theobroma-systems
 F: include/configs/puma_rk3399.h
 F: arch/arm/dts/rk3399-puma*
 F: configs/puma-rk3399_defconfig
-W: https://www.theobroma-systems.com/rk3399-q7/tech-specs
-T: git git://git.theobroma-systems.com/puma-u-boot.git
+W: https://embedded.cherry.de/product/puma-som-rk3399-q7/
+T: git git://git.embedded.cherry.de/puma-u-boot.git
diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS 
b/board/theobroma-systems/ringneck_px30/MAINTAINERS
index bf4bc452823..2aff91f4207 100644
--- a/board/theobroma-systems/ringneck_px30/MAINTAINERS
+++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS
@@ -8,4 +8,5 @@ F:  doc/board/theobroma-systems/
 F: include/configs/ringneck_px30.h
 F: arch/arm/dts/px30-ringneck*
 F: configs/ringneck-px30_defconfig
-W: https://theobroma-systems.com/product/ringneck-som-px30-uq7/
+W: https://embedded.cherry.de/product/ringneck-som-px30-uq7/
+T: git git://git.embedded.cherry.de/ringneck-u-boot.git

-- 
2.45.1

[PATCH 0/3] fix URL and mails for Theobroma now CHERRY Embedded Solutions

[Quentin Schulz]

To prevent some IT hiccups in the future, let's just migrate important
URLs and the mail addresses to ones people "should" be using right now.

This should be unnecessary but let's play it safe.

See
https://embedded.cherry.de/theobroma-systems-is-now-officially-part-of-cherry-se/
for the press release.

Signed-off-by: Quentin Schulz 
---
Quentin Schulz (3):
  .mailmap: redirect Philipp Tomsich Theobroma address to Vrull
  migrate Theobroma Systems mail addresses to CHERRY Embedded Solutions
  rockchip: theobroma: update URLs to point to CHERRY website

 .mailmap  | 5 +
 board/hardkernel/odroid_go2/MAINTAINERS   | 2 +-
 board/theobroma-systems/jaguar_rk3588/MAINTAINERS | 8 
 board/theobroma-systems/lion_rk3368/MAINTAINERS   | 4 ++--
 board/theobroma-systems/puma_rk3399/MAINTAINERS   | 8 
 board/theobroma-systems/ringneck_px30/MAINTAINERS | 7 ---
 6 files changed, 20 insertions(+), 14 deletions(-)
---
base-commit: 377e91c162ab09ec20f96f966f380cb55c590edd
change-id: 20240524-tsd-to-cherry-8f9e69a89607

Best regards,
-- 
Quentin Schulz 

[PATCH 2/3] migrate Theobroma Systems mail addresses to CHERRY Embedded Solutions

[Quentin Schulz]

From: Quentin Schulz 

See
https://embedded.cherry.de/theobroma-systems-is-now-officially-part-of-cherry-se/

While the mail addresses on the theobroma-systems.com domain should be
redirect to cherry.de, let's anticipate IT hiccups and avoid important
mails not reaching us by swapping the domain name wherever appropriate
for the newer one.

Christoph Mueller isn't working at ~Theobroma~ CHERRY Embedded Solutions
anymore, but I don't know his new mail address so mails destined to him
will keep bouncing.

Cc: Heiko Stuebner  

Cc: Jakob Unterwurzacher 
Cc: Klaus Goger 
Signed-off-by: Quentin Schulz 
---
 .mailmap  | 4 
 board/hardkernel/odroid_go2/MAINTAINERS   | 2 +-
 board/theobroma-systems/jaguar_rk3588/MAINTAINERS | 4 ++--
 board/theobroma-systems/lion_rk3368/MAINTAINERS   | 4 ++--
 board/theobroma-systems/puma_rk3399/MAINTAINERS   | 4 ++--
 board/theobroma-systems/ringneck_px30/MAINTAINERS | 4 ++--
 6 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/.mailmap b/.mailmap
index e530949a308..952e1dac4b2 100644
--- a/.mailmap
+++ b/.mailmap
@@ -42,6 +42,7 @@ Eugen Hristev  

 Fabio Estevam 
 Harini Katakam  
 Harsha  
+Heiko Stuebner  

 Heinrich Schuchardt  
 Heinrich Schuchardt  xypron.g...@gmx.de 

 Ibai Erkiaga  
@@ -53,12 +54,14 @@ Jagan Teki 
 Jagan Teki 
 Jagan Teki 
 Jagan Teki 
+Jakob Unterwurzacher  

 Jay Buddhabhatti  
 Jernej Skrabec  
 John Linn  
 Jyotheeswar Reddy Mutthareddyvari  

 Jyotheeswar Reddy Mutthareddyvari  

 Kalyani Akula  
+Klaus Goger  
 Masahisa Kojima  
 Love Kumar  
 Lukasz Majewski 
@@ -92,6 +95,7 @@ Philipp Tomsich  
 
 Prabhakar Kushwaha 
 Punnaiah Choudary Kalluri  

+Quentin Schulz  

 Radhey Shyam Pandey  

 Rajeshwari Shinde 
 Raju Kumar Pothuraju  

diff --git a/board/hardkernel/odroid_go2/MAINTAINERS 
b/board/hardkernel/odroid_go2/MAINTAINERS
index 4d4c6e8fef6..9e83bc9452c 100644
--- a/board/hardkernel/odroid_go2/MAINTAINERS
+++ b/board/hardkernel/odroid_go2/MAINTAINERS
@@ -1,5 +1,5 @@
 GO2
-M:  Heiko Stuebner 
+M:  Heiko Stuebner 
 S:  Maintained
 F:  board/hardkernel/odroid_go2/
 F:  include/configs/odroid_go2.h
diff --git a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS 
b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
index 28fae4b479f..d14edadefe2 100644
--- a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
+++ b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
@@ -1,6 +1,6 @@
 JAGUAR-RK3588 (SBC-RK3588-AMR Single Board Computer)
-M: Klaus Goger 
-M: Quentin Schulz 
+M: Klaus Goger 
+M: Quentin Schulz 
 M: Heiko Stuebner 
 S: Maintained
 F: board/theobroma-systems/jaguar_rk3588
diff --git a/board/theobroma-systems/lion_rk3368/MAINTAINERS 
b/board/theobroma-systems/lion_rk3368/MAINTAINERS
index a5b4cb31b4a..ed35fee6468 100644
--- a/board/theobroma-systems/lion_rk3368/MAINTAINERS
+++ b/board/theobroma-systems/lion_rk3368/MAINTAINERS
@@ -1,6 +1,6 @@
 LION-RK3368 (RK3368-uQ7 system-on-module)
-M: Quentin Schulz 
-M: Klaus Goger 
+M: Quentin Schulz 
+M: Klaus Goger 
 S: Maintained
 F: board/theobroma-systems/lion_rk3368
 F: include/configs/lion_rk3368.h
diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS 
b/board/theobroma-systems/puma_rk3399/MAINTAINERS
index 7e84a5be262..2b409f16963 100644
--- a/board/theobroma-systems/puma_rk3399/MAINTAINERS
+++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS
@@ -1,6 +1,6 @@
 PUMA-RK3399
-M: Quentin Schulz 
-M: Klaus Goger 
+M: Quentin Schulz 
+M: Klaus Goger 
 S: Maintained
 F: board/theobroma-systems/puma_rk3399
 F: board/theobroma-systems/common
diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS 
b/board/theobroma-systems/ringneck_px30/MAINTAINERS
index 97baf334d02..bf4bc452823 100644
--- a/board/theobroma-systems/ringneck_px30/MAINTAINERS
+++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS
@@ -1,6 +1,6 @@
 RINGNECK-PX30
-M: Quentin Schulz 
-M: Klaus Goger 
+M: Quentin Schulz 
+M: Klaus Goger 
 S: Maintained
 F: board/theobroma-systems/ringneck_px30
 F: board/theobroma-systems/common

-- 
2.45.1

[PATCH 1/3] .mailmap: redirect Philipp Tomsich Theobroma address to Vrull

[Quentin Schulz]

From: Quentin Schulz 

The Theobroma address bounces as Philipp is not working there anymore,
so let's update with the one that seems to be working right now.

Cc: Philipp Tomsich 
Signed-off-by: Quentin Schulz 
---
 .mailmap | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.mailmap b/.mailmap
index 8049856d41c..e530949a308 100644
--- a/.mailmap
+++ b/.mailmap
@@ -88,6 +88,7 @@ This contributor prefers not to receive mails 
  
 Patrick Delaunay  
 Paul Burton  
+Philipp Tomsich  

 Piyush Mehta  
 Prabhakar Kushwaha 
 Punnaiah Choudary Kalluri  


-- 
2.45.1

[PATCH next 5/5] power: rk8xx: properly print all supported PMICs name

[Quentin Schulz]

From: Quentin Schulz 

The ID of the PMIC is stored in the 2 16b registers but the only part
that matters right now is the 3 MSB, which make the 3 digits (in hex) of
the part number.

Right now, only RK808 was properly displayed, with this all currently
supported PMICs should display the proper part number.

Tested on RK806 (RK3588 Jaguar), RK808 (RK3399 Puma) and RK809 (PX30
Ringneck).

Signed-off-by: Quentin Schulz 
---
 drivers/power/pmic/rk8xx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 12ff26a0855..fe85fb13543 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -277,10 +277,10 @@ static int rk8xx_probe(struct udevice *dev)
return ret;
 
priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
-   show_variant = priv->variant;
+   /* All currently supported PMICs store the variant in the 3 MSB */
+   show_variant = priv->variant >> 4;
switch (priv->variant) {
case RK808_ID:
-   show_variant = 0x808;   /* RK808 hardware ID is 0 */
break;
case RK805_ID:
case RK816_ID:

-- 
2.45.1

[PATCH next 4/5] rockchip: px30-ringneck: Update SPL_PAD_TO Kconfig option

[Quentin Schulz]

From: Quentin Schulz 

On px30-ringneck the FIT payload is located at sector 0x200 compared to
the more Rockchip common sector 0x4000 offset:
SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200

Because FIT payload is located at sector 0x200 and the TPL+SPL is
located at sector 64, the combined size of TPL+SPL cannot take up more
than 224KiB:
(0x200 - 64) x 512 = 0x38000 (224 KiB)

Adjust SPL_PAD_TO to match the used 0x200 sector offset.

While at it, update the px30-ringneck-u-boot.dtsi to remove the now
unnecessary override of simple-bin:fit:offset since SPL_PAD_TO matches
with the current formula.

Signed-off-by: Quentin Schulz 
---
 arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi | 8 
 configs/ringneck-px30_defconfig   | 2 +-
 2 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi 
b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
index e04766ad09c..29ea2763636 100644
--- a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
+++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
@@ -15,14 +15,6 @@
};
 };
 
- {
-   simple-bin {
-   fit {
-   offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 
64) * 512)>;
-   };
-   };
-};
-
 _clk {
bootph-all;
 };
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index dedf35d4347..a22d25e0089 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x2
-CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_PAD_TO=0x38000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set

-- 
2.45.1

[PATCH next 3/5] rockchip: rk3399-puma: remove unnecessary simple-bin:fit:offset override

[Quentin Schulz]

From: Quentin Schulz 

Since commit 6007b69d544e ("rockchip: rk3399-puma: Update SPL_PAD_TO
Kconfig option"), SPL_PAD_TO matches
(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512 and the default
value for simple-bin:fit:offset in rockchip-u-boot.dtsi is
SPL_PAD_TO, so let's remove this override.

Signed-off-by: Quentin Schulz 
---
 arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 6 --
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi 
b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
index 5a9bd320ec4..55895d0dd19 100644
--- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
@@ -33,12 +33,6 @@
 };
 
  {
-   simple-bin {
-   fit {
-   offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 
64) * 512)>;
-   };
-   };
-
 #ifdef CONFIG_ROCKCHIP_SPI_IMAGE
simple-bin-spi {
fit {

-- 
2.45.1

[PATCH next 2/5] rockchip: rk3399-puma: remove default value from defconfig

[Quentin Schulz]

From: Quentin Schulz 

CONFIG_ENV_OFFSET already defaults to 0x3F8000, however it is stored in
lowercase hexdigits instead of uppercase like in the defconfig.

No change in behavior intended.

Signed-off-by: Quentin Schulz 
---
 configs/puma-rk3399_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 34a0b575991..42819102d70 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=2000
 CONFIG_ENV_SIZE=0x3000
-CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-puma-haikou"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y

-- 
2.45.1

[PATCH next 1/5] rockchip: jaguar-rk3588: use default env size for Rockchip on MMC

[Quentin Schulz]

From: Quentin Schulz 

The default env size is 0x8000 when building for Rockchip SoCs with
support for environment stored in MMC.

Jaguar hasn't entered mass production just yet, so it's a breaking
change we can afford in the name of consistency.

Signed-off-by: Quentin Schulz 
---
 configs/jaguar-rk3588_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index b69cf4cd057..36bf34d97c8 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
 CONFIG_SF_DEFAULT_SPEED=2400
 CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_ENV_SIZE=0x1f000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-jaguar"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0

-- 
2.45.1

[PATCH next 0/5] rockchip: display PMIC variant properly + misc fixes for Theobroma boards

[Quentin Schulz]

This fixes how the Rockchip PMIC variant is shown for all but RK808 by
stripping the LSB.

Also fix the size of the environment on Jaguar to match the default
(smaller) size.

Fix SPL_PAD_TO on Ringneck.

Remove duplicated default value of ENV_OFFSET in puma defconfig.

Remove unnecessary override of the fit offset in u-boot dtsi for Puma
and Ringneck.

Signed-off-by: Quentin Schulz 
---
Quentin Schulz (5):
  rockchip: jaguar-rk3588: use default env size for Rockchip on MMC
  rockchip: rk3399-puma: remove default value from defconfig
  rockchip: rk3399-puma: remove unnecessary simple-bin:fit:offset override
  rockchip: px30-ringneck: Update SPL_PAD_TO Kconfig option
  power: rk8xx: properly print all supported PMICs name

 arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi | 8 
 arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi   | 6 --
 configs/jaguar-rk3588_defconfig   | 1 -
 configs/puma-rk3399_defconfig | 1 -
 configs/ringneck-px30_defconfig   | 2 +-
 drivers/power/pmic/rk8xx.c| 4 ++--
 6 files changed, 3 insertions(+), 19 deletions(-)
---
base-commit: 8887ffb625f65475fd6619f8b05fb7a5a12b016b
change-id: 20240524-misc-tsd-e08551c01c8a

Best regards,
-- 
Quentin Schulz 

[PATCH next v2 8/8] rockchip: px30/rk3326: migrate to OF_UPSTREAM

[Quentin Schulz]

From: Quentin Schulz 

Migrate PX30/RK3326 boards that exists in Linux v6.8 to use OF_UPSTREAM.

firefly-px30 is not migrated to OF_UPSTREAM because there's no Device
Tree in the Linux kernel.

Differences between U-Boot's Odroid-Go2 and Linux's are now moved to the
-u-boot.dtsi, though I have a gut feeling that the existing cru
overrides aren't necessary (anymore?).

The U-Boot GPIO led-0 is on GPIO0_C1 but such is the pin of PWM3 which
is used for Linux's PWM led-2 so keep Linux's.

I also doubt vcc_cam is actually used, though the Odroid-Go2 Black
Edition uses this dcdc regulator for WiFi, so let's just move it to the
-u-boot.dtsi to play it safe.

Signed-off-by: Quentin Schulz 
---
 arch/arm/dts/Makefile  |   8 -
 arch/arm/dts/px30-engicam-common.dtsi  | 129 -
 arch/arm/dts/px30-engicam-ctouch2.dtsi |  30 -
 arch/arm/dts/px30-engicam-edimm2.2.dtsi|  66 ---
 .../dts/px30-engicam-px30-core-ctouch2-of10.dts|  77 ---
 arch/arm/dts/px30-engicam-px30-core-ctouch2.dts|  22 -
 arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts   |  43 --
 arch/arm/dts/px30-engicam-px30-core.dtsi   | 241 
 arch/arm/dts/px30-evb.dts  | 634 
 arch/arm/dts/px30-ringneck-haikou.dts  | 232 
 arch/arm/dts/px30-ringneck.dtsi| 382 
 arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi |  15 +
 arch/arm/dts/rk3326-odroid-go2.dts | 642 -
 arch/arm/mach-rockchip/Kconfig |   1 +
 configs/evb-px30_defconfig |   2 +-
 configs/firefly-px30_defconfig |   1 +
 configs/odroid-go2_defconfig   |   2 +-
 configs/px30-core-ctouch2-of10-px30_defconfig  |   2 +-
 configs/px30-core-ctouch2-px30_defconfig   |   2 +-
 configs/px30-core-edimm2.2-px30_defconfig  |   2 +-
 configs/ringneck-px30_defconfig|   2 +-
 21 files changed, 23 insertions(+), 2512 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f7032f1e175..198bc41223d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -53,14 +53,6 @@ dtb-$(CONFIG_MACH_S900) += \
 dtb-$(CONFIG_MACH_S700) += \
s700-cubieboard7.dtb
 
-dtb-$(CONFIG_ROCKCHIP_PX30) += \
-   px30-evb.dtb \
-   px30-firefly.dtb \
-   px30-engicam-px30-core-ctouch2.dtb \
-   px30-engicam-px30-core-ctouch2-of10.dtb \
-   px30-engicam-px30-core-edimm2.2.dtb \
-   rk3326-odroid-go2.dtb
-
 dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
 
diff --git a/arch/arm/dts/px30-engicam-common.dtsi 
b/arch/arm/dts/px30-engicam-common.dtsi
deleted file mode 100644
index 3429e124d95..000
--- a/arch/arm/dts/px30-engicam-common.dtsi
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/ {
-   aliases {
-   mmc1 = 
-   mmc2 = 
-   };
-
-   vcc5v0_sys: vcc5v0-sys {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc5v0_sys";  /* +5V */
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <500>;
-   regulator-max-microvolt = <500>;
-   };
-
-   sdio_pwrseq: sdio-pwrseq {
-   compatible = "mmc-pwrseq-simple";
-   clocks = <>;
-   clock-names = "ext_clock";
-   post-power-on-delay-ms = <80>;
-   pinctrl-names = "default";
-   pinctrl-0 = <_enable_h>;
-   };
-
-   vcc3v3_btreg: vcc3v3-btreg {
-   compatible = "regulator-gpio";
-   enable-active-high;
-   pinctrl-names = "default";
-   pinctrl-0 = <_enable_h>;
-   regulator-name = "btreg-gpio-supply";
-   regulator-min-microvolt = <330>;
-   regulator-max-microvolt = <330>;
-   regulator-always-on;
-   states = <330 0x0>;
-   };
-
-   vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc3v3_rf_aux_mod";
-   regulator-min-microvolt = <330>;
-   regulator-max-microvolt = <330>;
-   regulator-always-on;
-   regulator-boot-on;
-   vin-supply = <_sys>;
-   };
-
-   xin32k: xin32k {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <32768>;
-   clock-output-n

[PATCH next v2 7/8] rockchip: evb-px30: make UART5 the debug UART

[Quentin Schulz]

From: Quentin Schulz 

In the Device Tree, UART5 is the system UART, but in the defconfig it
currently is UART2. Let's sync the two by making the defconfig use UART5
as well.

Reviewed-by: Kever Yang 
Signed-off-by: Quentin Schulz 
---
 configs/evb-px30_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index a5833ad6d09..abe545625a5 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -10,7 +10,7 @@ CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_EVB_PX30=y
 # CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_DEBUG_UART_BASE=0xFF16
+CONFIG_DEBUG_UART_BASE=0xff178000
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y

-- 
2.45.1

[PATCH next v2 6/8] rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB

[Quentin Schulz]

From: Quentin Schulz 

In order to be able to properly mux UART on PX30 EVB, the pinmux needs
to be done at runtime, so let's not remove the pinctrl nodes from the
SPL DTB.

Reviewed-by: Kever Yang 
Signed-off-by: Quentin Schulz 
---
 configs/evb-px30_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 50ce1d7a9f3..a5833ad6d09 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -51,7 +51,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent 
assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_REGMAP=y

-- 
2.45.1

[PATCH next v2 5/8] rockchip: px30: make UART pinmux accessible to TPL/SPL DTB

[Quentin Schulz]

From: Quentin Schulz 

This adds the default pinmux for UART2 and UART5 to the TPL/SPL DTB (if
not removed through the CONFIG_OF_SPL_REMOVE_PROPS symbol) as those two
controllers are always made available to all boards.

Reviewed-by: Kever Yang 
Signed-off-by: Quentin Schulz 
---
 arch/arm/dts/px30-u-boot.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 046da022ffe..59fa9f43a97 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -33,11 +33,27 @@
bootph-all;
 };
 
+_xfer {
+   bootph-all;
+};
+
  {
clock-frequency = <2400>;
bootph-all;
 };
 
+_cts {
+   bootph-all;
+};
+
+_rts {
+   bootph-all;
+};
+
+_xfer {
+   bootph-all;
+};
+
  {
bootph-all;
 

-- 
2.45.1

[PATCH next v2 4/8] rockchip: px30-core-*: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Reviewed-by: Kever Yang 
Signed-off-by: Quentin Schulz 
---
 configs/px30-core-ctouch2-of10-px30_defconfig | 18 +++---
 configs/px30-core-ctouch2-px30_defconfig  | 18 +++---
 configs/px30-core-edimm2.2-px30_defconfig | 18 +++---
 3 files changed, 9 insertions(+), 45 deletions(-)

diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig 
b/configs/px30-core-ctouch2-of10-px30_defconfig
index 87a39e115df..dd005f20ff8 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
diff --git a/configs/px30-core-ctouch2-px30_defconfig 
b/configs/px30-core-ctouch2-px30_defconfig
index 7162c117beb..f6559fbae3a 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
diff --git a/configs/px30-core-edimm2.2-px30_defconfig 
b/configs/px30-core-edimm2.2-px30_defconfig
index 1182f60358f..a099e9378c9 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TP

[PATCH next v2 3/8] rockchip: odroid-go2: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Tested-by: Heiko Stuebner 
Reviewed-by: Kever Yang 
Signed-off-by: Quentin Schulz 
---
 configs/odroid-go2_defconfig | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 3c1abb83ed9..f4c9b02e12f 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -2,29 +2,17 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_ODROID_GO2=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -44,11 +32,11 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set

-- 
2.45.1

[PATCH next v2 2/8] rockchip: firefly-px30: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Reviewed-by: Kever Yang 
Signed-off-by: Quentin Schulz 
---
 configs/firefly-px30_defconfig | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 0a14b393667..063e4211fb7 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-firefly"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_EVB_PX30=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set

-- 
2.45.1

[PATCH next v2 0/8] rockchip: px30: migrate to common bss and stack addresses and OF_UPSTREAM

[Quentin Schulz]

Following up on migrating PX30 Ringneck to the new common bss and stack
addresses as done in
https://lore.kernel.org/u-boot/20240523-px30-2024-07-rc-v2-0-e46782d55...@cherry.de/T/#t
let's migrate all other px30 boards to this new memory layout so that it
aligns with other Rockchip SoCs (TPL excluded).

This also migrates all (but firefly-px30) PX30-based boards to use
OF_UPSTREAM. firefly-px30 doesn't have an upstream kernel device tree so
it is left untouched.
All but Odroid-Go2 were straightforward to migrate.

While at it, also fix a few issues related to UART on the PX30 Mini EVB
I could test.

This was boot tested on PX30 Ringneck and PX30 Mini EVB, U-Boot CLI and
Linux kernel userspace are reached.

This is based on next + 
https://lore.kernel.org/u-boot/20240523-px30-2024-07-rc-v2-0-e46782d55...@cherry.de/T/#t

To: Kever Yang 
To: Tom Rini 
To: Heiko Stuebner 
To: Jagan Teki 
To: Suniel Mahesh 
To: Simon Glass 
To: Philipp Tomsich 
To: Quentin Schulz 
To: Klaus Goger 
Cc: u-boot@lists.denx.de
Signed-off-by: Quentin Schulz 

Changes in v2:
- remove px30-base and ringneck patches, they were sent for master
- migrate boards to OF_UPSTREAM
- Link to v1: 
https://lore.kernel.org/r/20240521-px30-2024-07-rc-v1-0-62109c84d...@cherry.de

independently: 
https://lore.kernel.org/u-boot/20240523-px30-2024-07-rc-v2-0-e46782d55...@cherry.de/T/#t
---
Quentin Schulz (8):
  rockchip: evb-px30: Use common bss and stack addresses
  rockchip: firefly-px30: Use common bss and stack addresses
  rockchip: odroid-go2: Use common bss and stack addresses
  rockchip: px30-core-*: Use common bss and stack addresses
  rockchip: px30: make UART pinmux accessible to TPL/SPL DTB
  rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB
  rockchip: evb-px30: make UART5 the debug UART
  rockchip: px30/rk3326: migrate to OF_UPSTREAM

 arch/arm/dts/Makefile  |   8 -
 arch/arm/dts/px30-engicam-common.dtsi  | 129 -
 arch/arm/dts/px30-engicam-ctouch2.dtsi |  30 -
 arch/arm/dts/px30-engicam-edimm2.2.dtsi|  66 ---
 .../dts/px30-engicam-px30-core-ctouch2-of10.dts|  77 ---
 arch/arm/dts/px30-engicam-px30-core-ctouch2.dts|  22 -
 arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts   |  43 --
 arch/arm/dts/px30-engicam-px30-core.dtsi   | 241 
 arch/arm/dts/px30-evb.dts  | 634 
 arch/arm/dts/px30-ringneck-haikou.dts  | 232 
 arch/arm/dts/px30-ringneck.dtsi| 382 
 arch/arm/dts/px30-u-boot.dtsi  |  16 +
 arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi |  15 +
 arch/arm/dts/rk3326-odroid-go2.dts | 642 -
 arch/arm/mach-rockchip/Kconfig |   1 +
 configs/evb-px30_defconfig |  24 +-
 configs/firefly-px30_defconfig |  19 +-
 configs/odroid-go2_defconfig   |  20 +-
 configs/px30-core-ctouch2-of10-px30_defconfig  |  20 +-
 configs/px30-core-ctouch2-px30_defconfig   |  20 +-
 configs/px30-core-edimm2.2-px30_defconfig  |  20 +-
 configs/ringneck-px30_defconfig|   2 +-
 22 files changed, 59 insertions(+), 2604 deletions(-)
---
base-commit: 5e9aa577480ffbb6d3d0af6b972f227e087eef49
change-id: 20240508-px30-of_upstream-18bdbae87c98

Best regards,
-- 
Quentin Schulz 

[PATCH next v2 1/8] rockchip: evb-px30: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Reviewed-by: Kever Yang 
Signed-off-by: Quentin Schulz 
---
 configs/evb-px30_defconfig | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 73a3c6120e0..50ce1d7a9f3 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -2,26 +2,14 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-evb"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_EVB_PX30=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -39,9 +27,9 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set

-- 
2.45.1

[PATCH v2 2/3] rockchip: Use common bss and stack addresses on PX30

[Quentin Schulz]

From: Quentin Schulz 

See commit 008ba0d56d00 ("rockchip: Add common default bss and stack
addresses") for memory layout. This migrates PX30 to use the new layout,
except for TPL. Indeed, PX30 is extremely limited in SRAM, so we need to
be extra careful about what goes into the TPL and how much we can
allocate there, so let's keep the current value for
TPL_SYS_MALLOC_F_LEN (already present in the PX30-specific Kconfig, from
an earlier commit).

This will allow us to use the same memory layout on one more Rockchip
SoC, which is always a nice thing. Additionally, this will make it
easier to fix U-Boot proper pre-reloc running out of memory on PX30 in a
subsequent commit.

Reviewed-by: Kever Yang 
Tested-by: Heiko Stuebner 
Signed-off-by: Quentin Schulz 
---
 arch/arm/mach-rockchip/px30/Kconfig | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/px30/Kconfig 
b/arch/arm/mach-rockchip/px30/Kconfig
index e39472604c3..dcf9eb8144b 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -68,8 +68,11 @@ config ROCKCHIP_STIMER_BASE
 config SYS_SOC
default "px30"
 
+config ROCKCHIP_COMMON_STACK_ADDR
+   default y
+
 config SYS_MALLOC_F_LEN
-   default 0x400
+   default 0x400 if !SPL_SHARES_INIT_SP_ADDR
 
 config SPL_SERIAL
default y

-- 
2.45.1

[PATCH v2 3/3] rockchip: ringneck_px30: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory and it is
thus impossible to boot into U-Boot CLI.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Reviewed-by: Kever Yang 
Tested-by: Heiko Stuebner 
Signed-off-by: Quentin Schulz 
---
 configs/ringneck-px30_defconfig | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 0df1b8a59ac..94179dca3ae 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_RINGNECK_PX30=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF03
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -41,11 +29,11 @@ CONFIG_SPL_PAD_TO=0x0
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set

-- 
2.45.1

[PATCH v2 1/3] rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level

[Quentin Schulz]

From: Quentin Schulz 

This is the kind of setting that typically doesn't need to be changed
between boards based on the same SoC, so let's make it the default in
PX30 Kconfig so we don't have to care about it in the defconfig if we
don't want to.

Reviewed-by: Heiko Stuebner 
Reviewed-by: Kever Yang 
Tested-by: Heiko Stuebner 
Signed-off-by: Quentin Schulz 
---
 arch/arm/mach-rockchip/px30/Kconfig   | 3 +++
 configs/evb-px30_defconfig| 1 -
 configs/firefly-px30_defconfig| 1 -
 configs/odroid-go2_defconfig  | 1 -
 configs/px30-core-ctouch2-of10-px30_defconfig | 1 -
 configs/px30-core-ctouch2-px30_defconfig  | 1 -
 configs/px30-core-edimm2.2-px30_defconfig | 1 -
 configs/ringneck-px30_defconfig   | 1 -
 8 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-rockchip/px30/Kconfig 
b/arch/arm/mach-rockchip/px30/Kconfig
index 23f8f430c4a..e39472604c3 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -83,6 +83,9 @@ config TPL_TEXT_BASE
 config TPL_STACK
default 0xff0e4fff
 
+config TPL_SYS_MALLOC_F_LEN
+   default 0x600
+
 config DEBUG_UART_CHANNEL
int "Mux channel to use for debug UART2/UART3"
depends on DEBUG_UART_BOARD_INIT
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 07c56a45ec0..73a3c6120e0 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -16,7 +16,6 @@ CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_EVB_PX30=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index e5377dcdf3d..0a14b393667 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_EVB_PX30=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 99d7149a44c..3c1abb83ed9 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -19,7 +19,6 @@ CONFIG_TARGET_ODROID_GO2=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig 
b/configs/px30-core-ctouch2-of10-px30_defconfig
index a2801ec7796..87a39e115df 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/px30-core-ctouch2-px30_defconfig 
b/configs/px30-core-ctouch2-px30_defconfig
index cc33e275742..7162c117beb 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/px30-core-edimm2.2-px30_defconfig 
b/configs/px30-core-edimm2.2-px30_defconfig
index 99e1b2fc7ae..1182f60358f 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 67a44eda684..0df1b8a59ac 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_RINGNECK_PX30=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

-- 
2.45.1

[PATCH v2 0/3] rockchip: ringneck-px30: migrate to common bss and stack addresses

[Quentin Schulz]

PX30 Ringneck ran out of memory in the allocation pool of U-Boot proper
pre-reloc. Something needed to be done. Jonas did migrate a few SoCs
already to this common bss+stack addresses so it made sense to follow
the same route for one additional SoC: PX30.

The migration of other PX30-based boards will happen in next branch
instead, this one however is required for Ringneck to still reach U-Boot
CLI. Odroid-Go2 reaches the CLI without the patches in v1. Unknown
status for the other boards.

@Tom/Kever, please merge this on master.

To: Simon Glass 
To: Philipp Tomsich 
To: Kever Yang 
To: Heiko Stuebner 
To: Jagan Teki 
To: Suniel Mahesh 
To: Quentin Schulz 
To: Klaus Goger 
Cc: tr...@konsulko.com
Cc: jo...@kwiboo.se
Cc: u-boot@lists.denx.de
Signed-off-by: Quentin Schulz 

Changes in v2:
- remove non-ringneck patches, they'll be for next instead
- Link to v1: 
https://lore.kernel.org/r/20240521-px30-2024-07-rc-v1-0-62109c84d...@cherry.de

---
Quentin Schulz (3):
  rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig 
level
  rockchip: Use common bss and stack addresses on PX30
  rockchip: ringneck_px30: Use common bss and stack addresses

 arch/arm/mach-rockchip/px30/Kconfig   |  8 +++-
 configs/evb-px30_defconfig|  1 -
 configs/firefly-px30_defconfig|  1 -
 configs/odroid-go2_defconfig  |  1 -
 configs/px30-core-ctouch2-of10-px30_defconfig |  1 -
 configs/px30-core-ctouch2-px30_defconfig  |  1 -
 configs/px30-core-edimm2.2-px30_defconfig |  1 -
 configs/ringneck-px30_defconfig   | 19 +++
 8 files changed, 10 insertions(+), 23 deletions(-)
---
base-commit: a7f0154c412859323396111dd0c09dbafbc153cb
change-id: 20240521-px30-2024-07-rc-7136f6241d29

Best regards,
-- 
Quentin Schulz 

Re: [PATCH 15/42] mmc: dw_mmc: Improve coding style

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:31 AM, Sam Protsenko wrote:

Fix most of checkpatch warnings and other obvious style issues.

No functional change.

Signed-off-by: Sam Protsenko 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH 14/42] mmc: dw_mmc: Use CONFIG_IS_ENABLED() to check config options

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:31 AM, Sam Protsenko wrote:

Use CONFIG_IS_ENABLED() macro to check config options as recommended by
checkpatch, instead of checking those with just #ifdef CONFIG_...

No functional change.



There are actual functional changes in here.

defined(CONFIG_DM_MMC) != CONFIG_IS_ENABLED(DM_MMC)

Currently, if one has SPL_MMC and MMC_DW_ROCKCHIP defined, it'll build 
the SPL variant of MMC_DW_ROCKCHIP but guarding only with the U-Boot 
proper symbols, meaning, essentially the SPL and proper variant of 
rockchip_dw_mmc.o are more or less identical.


I think we can argue this isn't proper and should be fixed. I think we 
need to migrate all the MMC_DW drivers to use $(SPL_TPL_) in there and 
create the symbols in Kconfig with the appropriate dependencies. We'll 
likely also need to modify a bunch of defconfigs or make 
SPL_MMC_DW_ROCKCHIP default y if MMC_DW_ROCKCHIP for example, so that we 
don't break current support (it's pretty much expected to have MMC 
support in SPL).


I may have misinterpreted this, so please let me know where I am wrong 
in my assumptions here, but this does look like more work than just this.


Cheers,
Quentin

Re: [PATCH 09/42] mmc: dw_mmc: Extract setting the DMA descriptor into a separate routine

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:31 AM, Sam Protsenko wrote:

Make dwmci_prepare_data() function easier to read by extracting the
preparation of IDMAC descriptor into a dedicated function.

No functional change.

Signed-off-by: Sam Protsenko 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH 08/42] mmc: dw_mmc: Extract DMA transfer handling code into a separate routine

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:31 AM, Sam Protsenko wrote:

Make dwmci_send_cmd() easier to read by moving the DMA transfer handling
code into a dedicated function.

No functional change.

Signed-off-by: Sam Protsenko 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH 05/42] mmc: dw_mmc: Extract FIFO init into a separate routine

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:30 AM, Sam Protsenko wrote:

Move FIFO threshold initialization into a separate function to make
dwmci_init() more readable.

No functional change.

Signed-off-by: Sam Protsenko 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH 04/42] mmc: dw_mmc: Extract waiting for data busy into a separate routine

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:30 AM, Sam Protsenko wrote:

Waiting for data busy is a logically separate operation and should be
implemented as a separate routine. Follow Linux kernel example and
extract it from dwmci_send_cmd(). This way it doesn't clutter
dwmci_send_cmd() function, and can be reused later in other cases.

No functional change.

Signed-off-by: Sam Protsenko 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH 03/42] mmc: dw_mmc: Move struct idmac to dw_mmc.c

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:30 AM, Sam Protsenko wrote:

struct idmac is only used in dw_mmc.c, so move it there from dwmmc.h to
avoid cluttering the interface in the header.

No functional change.

Signed-off-by: Sam Protsenko 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH 02/42] mmc: dw_mmc: Remove unused version field from struct dwmci_host

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:30 AM, Sam Protsenko wrote:

Nobody seems to use it, so just remove it.

No functional change.

Signed-off-by: Sam Protsenko 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH 01/42] mmc: dw_mmc: Remove common.h

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:30 AM, Sam Protsenko wrote:

common.h header is marked for removal treewide and shouldn't be used.
Remove it from DW MMC driver.

No functional change.

Signed-off-by: Sam Protsenko 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH 06/42] mmc: dw_mmc: Extract clock on/off code into a separate routine

[Quentin Schulz]

Hi Sam,

On 5/23/24 1:30 AM, Sam Protsenko wrote:

Extract clock control code into a separate routine to avoid code
duplication in dwmci_setup_bus().

No functional change.



There are some differences though.


Signed-off-by: Sam Protsenko 
---
  drivers/mmc/dw_mmc.c | 60 
  1 file changed, 33 insertions(+), 27 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index cbfb8d3b8683..40b9b034f793 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -412,11 +412,33 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd 
*cmd,
return ret;
  }
  
-static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)

+static int dwmci_control_clken(struct dwmci_host *host, bool on)
  {
-   u32 div, status;
+   const u32 val = on ? DWMCI_CLKEN_ENABLE | DWMCI_CLKEN_LOW_PWR : 0;
+   const u32 cmd_only_clk = DWMCI_CMD_PRV_DAT_WAIT | DWMCI_CMD_UPD_CLK;
int timeout = 1;
+   u32 status;
+
+   dwmci_writel(host, DWMCI_CLKENA, val);
+
+   /* Inform CIU */
+   dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_START | cmd_only_clk);
+   do {
+   status = dwmci_readl(host, DWMCI_CMD);
+   if (timeout-- < 0) {
+   debug("%s: Timeout!\n", __func__);
+   return -ETIMEDOUT;
+   }
+   } while (status & DWMCI_CMD_START);
+
+   return 0;
+}
+
+static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
+{
+   u32 div;
unsigned long sclk;
+   int ret;
  
  	if ((freq == host->clock) || (freq == 0))

return 0;
@@ -439,35 +461,19 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 
freq)
else
div = DIV_ROUND_UP(sclk, 2 * freq);
  
-	dwmci_writel(host, DWMCI_CLKENA, 0);

+   /* Disable clock */
dwmci_writel(host, DWMCI_CLKSRC, 0);
+   ret = dwmci_control_clken(host, false);


Here, CLKENA and CLKSRC are swapped. The kernel still calls CLKENA 
before CLKSRC, is this really safe? (I have no documentation so cannot 
tell). E.g., we could have CLKSRC register be a way to select the clock 
parent/source, 0 could be 24MHz crystal for example, so switching to 
this new parent before disabling the clock output would likely result in 
glitches?



+   if (ret)
+   return ret;
  
+	/* Set clock to desired speed */

dwmci_writel(host, DWMCI_CLKDIV, div);


Same here, CLKDIV is set now after the CIU is informed, is this an 
issue? We may want to set the clock speed before we enable the clock 
again. Right now it's setting the desired speed while disabled, inform 
the CIU, enable the clock, inform the CIU. This now does, disable the 
clock, inform the CIU, set the desired speed, enable the clock, inform 
the CIU. We may need to wait for the clock to stabilize before enabling 
it? Again, just making guesses, no documentation for me here :/



-   dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
-   DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
  
-	do {

-   status = dwmci_readl(host, DWMCI_CMD);
-   if (timeout-- < 0) {
-   debug("%s: Timeout!\n", __func__);
-   return -ETIMEDOUT;
-   }
-   } while (status & DWMCI_CMD_START);
-
-   dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
-   DWMCI_CLKEN_LOW_PWR);
-
-   dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
-   DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
-
-   timeout = 1;
-   do {
-   status = dwmci_readl(host, DWMCI_CMD);
-   if (timeout-- < 0) {
-   debug("%s: Timeout!\n", __func__);
-   return -ETIMEDOUT;
-   }
-   } while (status & DWMCI_CMD_START);
+   /* Enable clock */
+   ret = dwmci_control_clken(host, true);
+   if (ret)
+   return ret;
  
  	host->clock = freq;
  

Cheers,
Quentin

Re: [PATCH v2] board: rockchip: add ArmSoM Sige7 Rk3588 board

[Quentin Schulz]

Hi Jianfeng Liu,

On 5/22/24 6:58 PM, Jianfeng Liu wrote:
[...]

Note that these commits:
- e18e5e8188f2 (arm64: dts: rockchip: add USBDP phys on rk3588)
- 6fca4edb93d3 (arm64: dts: rockchip: Add rk3588 GPU node)
are not synced to u-boot, so I remove usb3 drd nodes and gpu from kernel
devicetree.
[...]> diff --git 
a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts 
b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts

new file mode 100644
index 00..c7b46536ec
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts


Sorry, I failed to explain properly what was expected.

dts/upstream should never be touched except with 
dts/update-dts-subtree.sh script.


Sadly, your board is not supported in v6.9 yet, only in the upcoming 
v6.10 :/


So we have two options, we keep the dts in arch/arm/dts/ like you used 
to do, until we merge v6.10 dts in U-Boot (probably for v2024.10?), or 
we cherry-pick the changes for your board with dts/update-dts-subtree.sh 
script, see the instructions in the docs Tom has started writing: 
https://lore.kernel.org/u-boot/20240517174930.1028063-2-tr...@konsulko.com/. 
I would very much like to see someone starting to look into the second 
option :)


However... it seems we'll likely need to also cherry-pick patches for 
the GPU (should probably be straightforward as nothing would be using 
the GPU anyway in U-Boot) and the USBDP PHY... but this one we would 
need to update all -u-boot.dtsi for rk3588(s) boards that have it 
already to make it use the new label/DT, make sure that the driver still 
works... etc. Maybe not a small feat, but someone will have to do it at 
some point anyway :)


You'd be the first one to do this cherry-picking into dts/upstream, so 
it'd be really interesting to us if you could provide feedback on what 
is unclear/not working, etc... so we can update the documentation or fix 
tools if they were to be insufficient.


Looking forward to your next patch,
Cheers,
Quentin

Re: [PATCH RESEND] clk: rockchip: rk3588: Set SPLL frequency during SPL stage

[Quentin Schulz]

Hi Heiko,

On 5/22/24 4:18 PM, Heiko Stübner wrote:

Hi Quentin,

Am Mittwoch, 22. Mai 2024, 15:59:24 CEST schrieb Quentin Schulz:

On 5/22/24 2:15 PM, Heiko Stuebner wrote:

[...]

I'm also a bit wary of defining SPLL (and for that matter also V0PLL to
PPLL) with offsets relative to a different base than CRU (SBUSCRU for
SPLL for example) while all the others seem to have offsets relative to
CRU, c.f. RK3588_B0_PLL_CON(x). Specifically, it seems we are calling
rockchip_pll_set_rate with priv->cru which is the base of CRU. I am now
not entirely sure anything from V0PLL to PPLL is actually working since
we use offsets relative to some xCRU but call the function with the
CRU_BASE.



I checked again and they are actually using proper offsets.

All in CRU are using CRU_BASE, others all add the offset of their base, 
e.g. RK3588_PHP_CRU_BASE for PPLL, RK3588_BIGCORE0_CRU_BASE for B0PLL, 
RK3588_BIGCORE1_CRU_BASE for B1PLL, RK3588_DSU_CRU_BASE for LPLL.



So... wondering if we shouldn't have:

#define RK3588_SBUSCRU_BASE0x18000
#define RK3588_SBUSCRU_SPLL_CON(x) ((x) * 4 + 0x220 + RK3588_SBUSCRU_BASE)

and then in the probe of the scru driver, use CRU_BASE as the base,
otherwise we're doing some mixing and I don't like that too much. Or


At least for the SPLL we're calling

ret = rockchip_pll_set_rate(_pll_clks[SPLL],
(void *)BUSSCRU_BASE, SPLL, SPLL_HZ);

so no mention of priv->cru there at all and the pll-function internally
only hand down that iomem pointer. The scru-clock driver also is
very specific to the SPL, as it the whole thing will be inaccessible
after TF-A has run.

Doing some janky maths on top of a different base definitly sounds
a lot worse than just having a comment above the PLL definition
stating that it belongs to the SBUSCRU ;-) .



The thing is, everything in that array actually uses CRU_BASE as base, 
so for consistency-sake... doing the janky maths makes sense to me :)


Up to you, at the very least please have the comment.




What about making this handled the same way as other clocks in SCRU,
without actually using the table? Or... Have another table just for SCRU
in SPL and migrate existing clocks to use rockchip_pll_set_rate with
that new table?


The rk3588-pll getter/setter relies on the pll id to do even more special-
case handling. See all the pll_id == x checks in clk-pll.c, hence the PLL-id
is sort of global over the whole set of PLLs



Yeah... an enum for that would have been nice as well. Still nothing for 
this patch :)


Cheers,
Quentin

Re: [PATCH RESEND] clk: rockchip: rk3588: Set SPLL frequency during SPL stage

[Quentin Schulz]

Hi Heiko,

On 5/22/24 2:15 PM, Heiko Stuebner wrote:

From: Heiko Stuebner 

All parts expect the SPLL to run at 702MHz. In U-Boot it's the SPLL_HZ
declaring this rate and in the kernel it's a fixed clock definition.

While everything is expecting 702MHz, the SPLL is not running that
frequency when coming from the bootrom though, instead it's running
at 351MHz and the vendor-u-boot just sets it to the expected frequency.

The SPLL itself is located inside the secure-BUSCRU and in theory
accessible as an SCMI clock, though this requires an unknown amount
of cooperation from trusted-firmware to set at a later stage, though
during the SPL stage we can still access the relevant CRU directly.

The SPLL is for example necessary for the DSI controllers to produce
output.

As the SPLL is "just" another rk3588 pll, just set the desired rate
directly during the SPL stage.

Tested on rk3588-rock5b and rk3588-tiger by reading back the PLL rate
and also observing working DSI output with this change.

Fixes: 6737771600d4 ("rockchip: rk3588: Add support for sdmmc clocks in SPL")
Suggested-by: Andy Yan 
Signed-off-by: Heiko Stuebner 
Cc: Jonas Karlman 
---
Resend, because I forgot the u-boot list

  .../include/asm/arch-rockchip/cru_rk3588.h|  1 +
  drivers/clk/rockchip/clk_rk3588.c | 26 ---
  2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index a4507e5fdd7..85b4da0bc2c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -29,6 +29,7 @@ enum rk3588_pll_id {
V0PLL,
AUPLL,
PPLL,
+   SPLL,
PLL_COUNT,
  };
  
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c

index 4c611a39049..5384b3213f5 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -37,6 +37,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
RK3588_PLL_RATE(78600, 1, 131, 2, 0),
RK3588_PLL_RATE(74250, 4, 495, 2, 0),
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+   RK3588_PLL_RATE(70200, 3, 351, 2, 0),
RK3588_PLL_RATE(6, 2, 200, 2, 0),
RK3588_PLL_RATE(59400, 2, 198, 2, 0),
RK3588_PLL_RATE(2, 3, 400, 4, 0),
@@ -65,6 +66,11 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = {
 RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
 RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
+#ifdef CONFIG_SPL_BUILD
+   /* SBUSCRU MODE_CON has the same register offset as the main MODE_CON */
+   [SPLL] = PLL(pll_rk3588, 0, RK3588_PLL_CON(136),
+RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),


FYI, it seems the rk3588 clock driver doesn't lock the PLL with the 
lock_shift member, so 15 here is useless. Maybe we should switch 
RK3588_PLLCON6_LOCK_STATUS to (1 << lock_shift) there for it to make 
sense. Anyway, nothing specific to your patch.


RK3588_PLL_CON(136) is unreadable :/ Though I understand where it's 
coming from as we have the same issue from V0PLL to PPLL. Can't we have 
something a bit more proper here, e.g.


#define RK3588_SBUSCRU_SPLL_CON(x) ((x) * 4 + 0x220)

and then use RK3588_SBUSCRU_SPLL_CON(0) here?

I'm also a bit wary of defining SPLL (and for that matter also V0PLL to 
PPLL) with offsets relative to a different base than CRU (SBUSCRU for 
SPLL for example) while all the others seem to have offsets relative to 
CRU, c.f. RK3588_B0_PLL_CON(x). Specifically, it seems we are calling 
rockchip_pll_set_rate with priv->cru which is the base of CRU. I am now 
not entirely sure anything from V0PLL to PPLL is actually working since 
we use offsets relative to some xCRU but call the function with the 
CRU_BASE.


So... wondering if we shouldn't have:

#define RK3588_SBUSCRU_BASE0x18000
#define RK3588_SBUSCRU_SPLL_CON(x) ((x) * 4 + 0x220 + RK3588_SBUSCRU_BASE)

and then in the probe of the scru driver, use CRU_BASE as the base, 
otherwise we're doing some mixing and I don't like that too much. Or 
What about making this handled the same way as other clocks in SCRU, 
without actually using the table? Or... Have another table just for SCRU 
in SPL and migrate existing clocks to use rockchip_pll_set_rate with 
that new table?



+#endif
  };
  
  #ifndef CONFIG_SPL_BUILD

@@ -2044,6 +2050,7 @@ U_BOOT_DRIVER(rockchip_rk3588_cru) = {
  
  #ifdef CONFIG_SPL_BUILD

  #define SCRU_BASE 0xfd7d
+#define BUSSCRU_BASE   0xfd7d8000


Can you please rename to SBUSCRU_BASE to match the TRM?

Cheers,
Quentin

Re: [PATCH 00/10] rockchip: px30: migrate to common bss and stack addresses + UART fixes for evb-px30

[Quentin Schulz]

Hi Tom,

On 5/21/24 8:04 PM, Tom Rini wrote:

On Tue, May 21, 2024 at 07:39:53PM +0200, Quentin Schulz wrote:

PX30 Ringneck ran out of memory in the allocation pool of U-Boot proper
pre-reloc. Something needed to be done. Jonas did migrate a few SoCs
already to this common bss+stack addresses so it made sense to follow
the same route for one additional SoC: PX30.

While at it, also fix a few issues related to UART on the PX30 Mini EVB
I could test.

Boot (to U-Boot CLI) tested on PX30 Ringneck and PX30 Mini-EVB.

Thanks to Jonas for hinting where to look at.

Signed-off-by: Quentin Schulz 
---
Quentin Schulz (10):
   rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig 
level
   rockchip: Use common bss and stack addresses on PX30
   rockchip: ringneck_px30: Use common bss and stack addresses
   rockchip: evb-px30: Use common bss and stack addresses
   rockchip: firefly-px30: Use common bss and stack addresses
   rockchip: odroid-go2: Use common bss and stack addresses
   rockchip: px30-core-*: Use common bss and stack addresses
   rockchip: px30: make UART pinmux accessible to TPL/SPL DTB
   rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB
   rockchip: evb-px30: make UART5 the debug UART

  arch/arm/dts/px30-u-boot.dtsi | 16 
  arch/arm/mach-rockchip/px30/Kconfig   |  8 +++-
  configs/evb-px30_defconfig| 23 +--
  configs/firefly-px30_defconfig| 19 +++
  configs/odroid-go2_defconfig  | 19 +++
  configs/px30-core-ctouch2-of10-px30_defconfig | 19 +++
  configs/px30-core-ctouch2-px30_defconfig  | 19 +++
  configs/px30-core-edimm2.2-px30_defconfig | 19 +++
  configs/ringneck-px30_defconfig   | 19 +++
  9 files changed, 46 insertions(+), 115 deletions(-)
---
base-commit: a7f0154c412859323396111dd0c09dbafbc153cb
change-id: 20240521-px30-2024-07-rc-7136f6241d29


As I assume we want to fix the platforms for v2024.07, is this the level
of config changes everyone is comfortable with on the platforms? Or
should we just go with the minimum for release and the rest to -next?



I can tell you that Ringneck doesn't work anymore on v2024.07-rc, but 
the PX30 Mini EVB was still reaching U-Boot CLI without the changes. I 
don't know about the other boards.


So I could split this into two series, one for master, one for next.

I could suggest: patch 1 to 3 in master, the rest in next. Patch 1 is 
just moving things around. Patch 2 is doing nothing if nobody uses 
ROCKCHIP_COMMON_STACK_ADDR and SPL_SHARES_INIT_SP_ADDR (which is the 
case for px30 boards). Patch 3 is for fixing Ringneck, which I know is 
broken.


Heiko having access to the Odroid Go2, maybe he could test without my 
patches and see if it reaches the CLI to know if we should pull it in 
for master as well.


Does this make sense?

Thanks,
Quentin

[PATCH 10/10] rockchip: evb-px30: make UART5 the debug UART

[Quentin Schulz]

From: Quentin Schulz 

In the Device Tree, UART5 is the system UART, but in the defconfig it
currently is UART2. Let's sync the two by making the defconfig use UART5
as well.

Signed-off-by: Quentin Schulz 
---
 configs/evb-px30_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index a5833ad6d09..abe545625a5 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -10,7 +10,7 @@ CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_EVB_PX30=y
 # CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_DEBUG_UART_BASE=0xFF16
+CONFIG_DEBUG_UART_BASE=0xff178000
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y

-- 
2.45.1

[PATCH 09/10] rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB

[Quentin Schulz]

From: Quentin Schulz 

In order to be able to properly mux UART on PX30 EVB, the pinmux needs
to be done at runtime, so let's not remove the pinctrl nodes from the
SPL DTB.

Signed-off-by: Quentin Schulz 
---
 configs/evb-px30_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 50ce1d7a9f3..a5833ad6d09 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -51,7 +51,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent 
assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_REGMAP=y

-- 
2.45.1

[PATCH 08/10] rockchip: px30: make UART pinmux accessible to TPL/SPL DTB

[Quentin Schulz]

From: Quentin Schulz 

This adds the default pinmux for UART2 and UART5 to the TPL/SPL DTB (if
not removed through the CONFIG_OF_SPL_REMOVE_PROPS symbol) as those two
controllers are always made available to all boards.

Signed-off-by: Quentin Schulz 
---
 arch/arm/dts/px30-u-boot.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 046da022ffe..59fa9f43a97 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -33,11 +33,27 @@
bootph-all;
 };
 
+_xfer {
+   bootph-all;
+};
+
  {
clock-frequency = <2400>;
bootph-all;
 };
 
+_cts {
+   bootph-all;
+};
+
+_rts {
+   bootph-all;
+};
+
+_xfer {
+   bootph-all;
+};
+
  {
bootph-all;
 

-- 
2.45.1

[PATCH 07/10] rockchip: px30-core-*: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Signed-off-by: Quentin Schulz 
---
 configs/px30-core-ctouch2-of10-px30_defconfig | 18 +++---
 configs/px30-core-ctouch2-px30_defconfig  | 18 +++---
 configs/px30-core-edimm2.2-px30_defconfig | 18 +++---
 3 files changed, 9 insertions(+), 45 deletions(-)

diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig 
b/configs/px30-core-ctouch2-of10-px30_defconfig
index 87a39e115df..dd005f20ff8 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
diff --git a/configs/px30-core-ctouch2-px30_defconfig 
b/configs/px30-core-ctouch2-px30_defconfig
index 7162c117beb..f6559fbae3a 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
diff --git a/configs/px30-core-edimm2.2-px30_defconfig 
b/configs/px30-core-edimm2.2-px30_defconfig
index 1182f60358f..a099e9378c9 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not 

[PATCH 06/10] rockchip: odroid-go2: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Signed-off-by: Quentin Schulz 
---
 configs/odroid-go2_defconfig | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 3c1abb83ed9..f4c9b02e12f 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -2,29 +2,17 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_ODROID_GO2=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -44,11 +32,11 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set

-- 
2.45.1

[PATCH 05/10] rockchip: firefly-px30: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Signed-off-by: Quentin Schulz 
---
 configs/firefly-px30_defconfig | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 0a14b393667..063e4211fb7 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-firefly"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_EVB_PX30=y
 CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set

-- 
2.45.1

[PATCH 04/10] rockchip: evb-px30: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Signed-off-by: Quentin Schulz 
---
 configs/evb-px30_defconfig | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 73a3c6120e0..50ce1d7a9f3 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -2,26 +2,14 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-evb"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_EVB_PX30=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF16
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -39,9 +27,9 @@ CONFIG_SPL_MAX_SIZE=0x2
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set

-- 
2.45.1

[PATCH 03/10] rockchip: ringneck_px30: Use common bss and stack addresses

[Quentin Schulz]

From: Quentin Schulz 

U-Boot proper pre-reloc is currently running out of memory and it is
thus impossible to boot into U-Boot CLI.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Signed-off-by: Quentin Schulz 
---
 configs/ringneck-px30_defconfig | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 0df1b8a59ac..94179dca3ae 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -2,27 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40
 CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou"
-CONFIG_SPL_TEXT_BASE=0x
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_RINGNECK_PX30=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x60
-CONFIG_SPL_STACK=0x40
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF03
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -41,11 +29,11 @@ CONFIG_SPL_PAD_TO=0x0
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set

-- 
2.45.1

[PATCH 02/10] rockchip: Use common bss and stack addresses on PX30

[Quentin Schulz]

From: Quentin Schulz 

See commit 008ba0d56d00 ("rockchip: Add common default bss and stack
addresses") for memory layout. This migrates PX30 to use the new layout,
except for TPL. Indeed, PX30 is extremely limited in SRAM, so we need to
be extra careful about what goes into the TPL and how much we can
allocate there, so let's keep the current value for
TPL_SYS_MALLOC_F_LEN (already present in the PX30-specific Kconfig, from
an earlier commit).

This will allow us to use the same memory layout on one more Rockchip
SoC, which is always a nice thing. Additionally, this will make it
easier to fix U-Boot proper pre-reloc running out of memory on PX30 in a
subsequent commit.

Signed-off-by: Quentin Schulz 
---
 arch/arm/mach-rockchip/px30/Kconfig | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/px30/Kconfig 
b/arch/arm/mach-rockchip/px30/Kconfig
index e39472604c3..dcf9eb8144b 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -68,8 +68,11 @@ config ROCKCHIP_STIMER_BASE
 config SYS_SOC
default "px30"
 
+config ROCKCHIP_COMMON_STACK_ADDR
+   default y
+
 config SYS_MALLOC_F_LEN
-   default 0x400
+   default 0x400 if !SPL_SHARES_INIT_SP_ADDR
 
 config SPL_SERIAL
default y

-- 
2.45.1

[PATCH 01/10] rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level

[Quentin Schulz]

From: Quentin Schulz 

This is the kind of setting that typically doesn't need to be changed
between boards based on the same SoC, so let's make it the default in
PX30 Kconfig so we don't have to care about it in the defconfig if we
don't want to.

Signed-off-by: Quentin Schulz 
---
 arch/arm/mach-rockchip/px30/Kconfig   | 3 +++
 configs/evb-px30_defconfig| 1 -
 configs/firefly-px30_defconfig| 1 -
 configs/odroid-go2_defconfig  | 1 -
 configs/px30-core-ctouch2-of10-px30_defconfig | 1 -
 configs/px30-core-ctouch2-px30_defconfig  | 1 -
 configs/px30-core-edimm2.2-px30_defconfig | 1 -
 configs/ringneck-px30_defconfig   | 1 -
 8 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-rockchip/px30/Kconfig 
b/arch/arm/mach-rockchip/px30/Kconfig
index 23f8f430c4a..e39472604c3 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -83,6 +83,9 @@ config TPL_TEXT_BASE
 config TPL_STACK
default 0xff0e4fff
 
+config TPL_SYS_MALLOC_F_LEN
+   default 0x600
+
 config DEBUG_UART_CHANNEL
int "Mux channel to use for debug UART2/UART3"
depends on DEBUG_UART_BOARD_INIT
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 07c56a45ec0..73a3c6120e0 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -16,7 +16,6 @@ CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_EVB_PX30=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index e5377dcdf3d..0a14b393667 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_EVB_PX30=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 99d7149a44c..3c1abb83ed9 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -19,7 +19,6 @@ CONFIG_TARGET_ODROID_GO2=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig 
b/configs/px30-core-ctouch2-of10-px30_defconfig
index a2801ec7796..87a39e115df 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/px30-core-ctouch2-px30_defconfig 
b/configs/px30-core-ctouch2-px30_defconfig
index cc33e275742..7162c117beb 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/px30-core-edimm2.2-px30_defconfig 
b/configs/px30-core-edimm2.2-px30_defconfig
index 99e1b2fc7ae..1182f60358f 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 67a44eda684..0df1b8a59ac 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_RINGNECK_PX30=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_SPL_STACK=0x40
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

-- 
2.45.1

[PATCH 00/10] rockchip: px30: migrate to common bss and stack addresses + UART fixes for evb-px30

[Quentin Schulz]

PX30 Ringneck ran out of memory in the allocation pool of U-Boot proper
pre-reloc. Something needed to be done. Jonas did migrate a few SoCs
already to this common bss+stack addresses so it made sense to follow
the same route for one additional SoC: PX30.

While at it, also fix a few issues related to UART on the PX30 Mini EVB
I could test.

Boot (to U-Boot CLI) tested on PX30 Ringneck and PX30 Mini-EVB.

Thanks to Jonas for hinting where to look at.

Signed-off-by: Quentin Schulz 
---
Quentin Schulz (10):
  rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig 
level
  rockchip: Use common bss and stack addresses on PX30
  rockchip: ringneck_px30: Use common bss and stack addresses
  rockchip: evb-px30: Use common bss and stack addresses
  rockchip: firefly-px30: Use common bss and stack addresses
  rockchip: odroid-go2: Use common bss and stack addresses
  rockchip: px30-core-*: Use common bss and stack addresses
  rockchip: px30: make UART pinmux accessible to TPL/SPL DTB
  rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB
  rockchip: evb-px30: make UART5 the debug UART

 arch/arm/dts/px30-u-boot.dtsi | 16 
 arch/arm/mach-rockchip/px30/Kconfig   |  8 +++-
 configs/evb-px30_defconfig| 23 +--
 configs/firefly-px30_defconfig| 19 +++
 configs/odroid-go2_defconfig  | 19 +++
 configs/px30-core-ctouch2-of10-px30_defconfig | 19 +++
 configs/px30-core-ctouch2-px30_defconfig  | 19 +++
 configs/px30-core-edimm2.2-px30_defconfig | 19 +++
 configs/ringneck-px30_defconfig   | 19 +++
 9 files changed, 46 insertions(+), 115 deletions(-)
---
base-commit: a7f0154c412859323396111dd0c09dbafbc153cb
change-id: 20240521-px30-2024-07-rc-7136f6241d29

Best regards,
-- 
Quentin Schulz 

Re: [ANN] U-Boot v2024.07-rc3 released

[quentin . schulz]

Hi Jonas,

On 5/21/24 1:57 PM, Jonas Karlman  wrote:

Hi Quentin,

On 2024-05-21 11:53, Quentin Schulz wrote:
> Hi all,
>
> On 5/20/24 6:06 PM, Tom Rini wrote:
>> Hey all,
>>
>> It's release day and here is -rc3. At this point, I think we're firmly
>> on "bug fix and documentation" ground moving forward for changes to
>> v2024.07 and the next branch is open and ready for use and pull
>> requests.
>>
>> In terms of a changelog,
>> git log --merges v2024.07-rc2..v2024.07-rc3
>> contains what I've pulled but as always, better PR messages and tags
>> will provide better results here.
>>
>> I hope to remain on schedule and that means the rest of the rcs every
>> other Monday, and with final release on Monday, July 1st, 2024. Thanks
>> all!
>>
>
> Just to let you know that Rockchip PX30 support is broken since
> 
https://source.denx.de/u-boot/u-boot/-/commit/1d01440b3f14f6648cd672da619489f635cb209c
> (at the very least on Ringneck, haven't tested on PX30 Mini-EVB yet).
>
> U-Boot proper pre-reloc seems to be running out of memory and we cannot
> reach U-Boot CLI anymore.
>
> I hope I'll have time to look into this before v2024.07 is released but
> cannot promise anything.

On Rockchip platform all DRAM is available at U-Boot proper pre-reloc,
so there is no need to limit SYS_MALLOC_F_LEN to a small amount.

Ringneck seem to use 8 KiB for pre-reloc malloc() pool, please try with
a 64 KiB pool, same as rk3308/rk3328/rk3399/rk356x/rk3588 all now use.

   CONFIG_SYS_MALLOC_F_LEN=0x1



This made it work, thanks for the hint.


malloc() pool size used by TPL/SPL should still work:

   CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
   CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000

Also check the "Early malloc usage" from bdinfo cmd, should show how
much memory was actually allocated at pre-reloc, from a rk3308 board:

   Early malloc usage: 2060 / 1



"""
=> bdinfo
boot_params = 0x
DRAM bank   = 0x
-> start= 0x0020
-> size = 0x7fe0
flashstart  = 0x
flashsize   = 0x
flashoffset = 0x
baudrate= 115200 bps
relocaddr   = 0x7ff53000
reloc off   = 0x7fd53000
Build   = 64-bit
current eth = ethernet@ff36
ethaddr = f6:3c:b5:0d:0a:13
IP addr = 
fdt_blob= 0x7df43bd0
new_fdt = 0x7df43bd0
fdt_size= 0xc1e0
lmb_dump_all:
memory.cnt = 0x1 / max = 0x10
memory[0]   [0x20-0x7fff], 0x7fe0 bytes flags: 0
reserved.cnt = 0x1 / max = 0x10
reserved[0] [0x7df3f580-0x7fff], 0x020c0a80 bytes flags: 0
devicetree  = separate
serial addr = 0xff03
width  = 0x0004
shift  = 0x0002
offset = 0x
clock  = 0x016e3600
arch_number = 0x
TLB addr= 0x7fff
irq_sp  = 0x7df43bc0
sp start= 0x7df43bc0
Early malloc usage: 2250 / 1
"""

The default on PX30 for SYS_MALLOC_F_LEN is 0x400 (both from 
arch/arm/mach-rockchip/px30/Kconfig and Kconfig).

The default for SPL_SYS_MALLOC_F_LEN is SYS_MALLOC_F_LEN.

The default for TPL_SYS_MALLOC_F_LEN is SPL_SYS_MALLOC_F_LEN.

I suggest we change the default SYS_MALLOC_F_LEN to be 0x2 then, on PX30.

Since we have forced TPL support on PX30, we can keep SPL_SYS_MALLOC_F_LEN is 
SYS_MALLOC_F_LEN, because we necessarily have DRAM support in SPL so we are 
much less limited in allocation.

Since all PX30 boards have 0x600 for TPL_SYS_MALLOC_F_LEN I suggest to make 
this the default as well?

Anything against this?

I'm also a bit confused as to why we need to specify the size of the allocation 
pool pre-relocation? Why is this important?

Thanks a lot for the hint, I can now work on migrating PX30 to OF_UPSTREAM :)

Cheers,
Quentin

Re: [ANN] U-Boot v2024.07-rc3 released

[Quentin Schulz]

Hi all,

On 5/20/24 6:06 PM, Tom Rini wrote:

Hey all,

It's release day and here is -rc3. At this point, I think we're firmly
on "bug fix and documentation" ground moving forward for changes to
v2024.07 and the next branch is open and ready for use and pull
requests.

In terms of a changelog,
git log --merges v2024.07-rc2..v2024.07-rc3
contains what I've pulled but as always, better PR messages and tags
will provide better results here.

I hope to remain on schedule and that means the rest of the rcs every
other Monday, and with final release on Monday, July 1st, 2024. Thanks
all!



Just to let you know that Rockchip PX30 support is broken since 
https://source.denx.de/u-boot/u-boot/-/commit/1d01440b3f14f6648cd672da619489f635cb209c 
(at the very least on Ringneck, haven't tested on PX30 Mini-EVB yet).


U-Boot proper pre-reloc seems to be running out of memory and we cannot 
reach U-Boot CLI anymore.


I hope I'll have time to look into this before v2024.07 is released but 
cannot promise anything.


Cheers,
Quentin

Re: [v3 2/2] doc: process.rst: Document device tree resync rules

[Quentin Schulz]

Hi Tom,

On 5/17/24 7:49 PM, Tom Rini wrote:

Document the logic of when we do a full resync of the device trees used
by OF_UPSTREAM as well as that cherry-picking is allowed as needed.

Signed-off-by: Tom Rini 
---
Changes in v3:
- Actually commit the changes I intended for v2

Changes in v2:
- Address Quentin's feedback

Cc: Heinrich Schuchardt 
Cc: Quentin Schulz 
---
  doc/develop/devicetree/control.rst |  9 ++---
  doc/develop/process.rst| 13 +
  2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/doc/develop/devicetree/control.rst 
b/doc/develop/devicetree/control.rst
index 4cc1457d4ea8..ca4fb0b5b10f 100644
--- a/doc/develop/devicetree/control.rst
+++ b/doc/develop/devicetree/control.rst
@@ -113,9 +113,12 @@ SoC being used via Kconfig and set 
`DEFAULT_DEVICE_TREE=/` when
  prompted by Kconfig.
  
  However, if `dts/upstream/` hasn't yet received devicetree source file for your

-newly added board support then you can add corresponding devicetree source file
-as `arch//dts/.dts`. To select that add `# CONFIG_OF_UPSTREAM is 
not
-set` and set `DEFAULT_DEVICE_TREE=` when prompted by Kconfig.
+newly added board support then one option is that you can add the corresponding
+devicetree source file as `arch//dts/.dts`. To select that add `#
+CONFIG_OF_UPSTREAM is not set` and set `DEFAULT_DEVICE_TREE=` when


I don't like the wording here because it implies we should modify the 
defconfig by hand, which nobody should ever do.


I could suggest:
"""
To do that, unselect `OF_UPSTREAM` and set `DEFAULT_DEVICE_TREE=` 
through a Kconfig tool (e.g. `menuconfig`).

"""

In any case, this is wording is not added in this patch, so I guess we 
could fix it in another patch as well, making this remark not a "blocker".



+prompted by Kconfig. Another option is that you can use use the "pick" option 
of
+`dts/update-dts-subtree.sh` mentioned above to bring in the commits that you
+need.
  
  This should include your CPU or SoC's devicetree file. On top of that any U-Boot

  specific tweaks (see: :ref:`dttweaks`) can be made for your board.
diff --git a/doc/develop/process.rst b/doc/develop/process.rst
index a66540a698c1..0542b3fc1245 100644
--- a/doc/develop/process.rst
+++ b/doc/develop/process.rst
@@ -108,6 +108,19 @@ Differences to the Linux Development Process
In U-Boot, ``"-rc1"`` will only be released after all (or at least most of
the) patches that were submitted during the merge window have been applied.
  
+Resyncing of the device tree subtree

+
+
+As explained in :doc:`devicetree/control` some platforms make use of device 
tree
+files which come from a git subtree that mirrors the Linux Kernel sources
+itself. For our purposes, we only track releases and not release candidates for
+merging in our tree. These merges follow the normal merge window rules.
+
+In the case of specific changes, such as bug fixes or new platform support,
+these can be "cherry-picked" and are subject to the normal merge rules. For
+example, a bug fix can come in later in the window but a full re-sync only
+happens within the merge window itself.
+


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [v3 1/2] doc: process.rst: Use subsubheading for "Phases of the Development Process"

[Quentin Schulz]

Hi Tom,

On 5/17/24 7:49 PM, Tom Rini wrote:

These sections which talk about the different phases of the development
process should be using the subsubheading identifier.

Signed-off-by: Tom Rini 
---
Changes in v3:
None

Changes in v2:
None

Cc: Heinrich Schuchardt 
---
  doc/develop/process.rst | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/doc/develop/process.rst b/doc/develop/process.rst
index 92477d05dd85..a66540a698c1 100644
--- a/doc/develop/process.rst
+++ b/doc/develop/process.rst
@@ -34,7 +34,7 @@ It is followed by a *Stabilization Period*.
  The end of a Release Cycle is marked by the release of a new U-Boot version.
  
  Merge Window

-
+
  
  The Merge Window is the period when new patches get submitted (and hopefully

  accepted) for inclusion into U-Boot mainline. This period lasts for 21 days (3
@@ -44,7 +44,7 @@ This is the only time when new code (like support for new 
processors or new
  boards, or other new features or reorganization of code) is accepted.
  
  Twilight Time

--
+^
  
  Usually patches do not get accepted as they are - the peer review that takes

  place will usually require changes and resubmissions of the patches before 
they
@@ -65,13 +65,13 @@ the Merge Window does not preclude patches that were 
already posted from being
  merged for the upcoming release.
  
  Stabilization Period

-
+
  
  During the Stabilization Period only patches containing bug fixes get

  applied.
  
  Corner Cases

-
+
  
  Sometimes it is not clear if a patch contains a bug fix or not.

  For example, changes that remove dead code, unused macros etc. or


Wondering if we shouldn't put:

Differences to the Linux Development Process

section under the "Phases of the development process" section as well?

Otherwise,

Reviewed-by: Quentin Schulz 

Thanks!
Quentin

Re: [PATCH 2/2] doc: process.rst: Document device tree resync rules

[Quentin Schulz]

Hi Tom,

On 5/16/24 10:34 PM, Tom Rini wrote:

Document the logic of when we do a full resync of the device trees used
by OF_UPSTREAM as well as that cherry-picking is allowed as needed.

Signed-off-by: Tom Rini 
---
Cc: Heinrich Schuchardt 
---
  doc/develop/process.rst | 13 +
  1 file changed, 13 insertions(+)

diff --git a/doc/develop/process.rst b/doc/develop/process.rst
index a66540a698c1..0542b3fc1245 100644
--- a/doc/develop/process.rst
+++ b/doc/develop/process.rst
@@ -108,6 +108,19 @@ Differences to the Linux Development Process
In U-Boot, ``"-rc1"`` will only be released after all (or at least most of
the) patches that were submitted during the merge window have been applied.
  
+Resyncing of the device tree subtree

+
+
+As explained in :doc:`devicetree/control` some platforms make use of device 
tree
+files which come from a git subtree that mirrors the Linux Kernel sources
+itself. For our purposes, we only track releases and not release candidates for
+merging in our tree. These merges follow the normal merge window rules.
+
+In the case of specific changes, such as bug fixes or new platform support,
+these can be "cherry-picked" and are subject to the normal merge rules. For
+example, a bug fix can come in later in the window but a full re-sync only
+happens within the merge window itself.
+


Can we provide an example on how to cherry-pick those changes with a 
command line?


Additionally, in doc/develop/devicetree/control.rst we say:

"""
However, if `dts/upstream/` hasn't yet received devicetree source file 
for your newly added board support then you can add corresponding 
devicetree source file as `arch//dts/.dts`. To select that 
add `# CONFIG_OF_UPSTREAM is not set` and set 
`DEFAULT_DEVICE_TREE=` when prompted by Kconfig.

"""

But now we have a second option, cherry-picking upstream changes 
instead, so I assume we should document it there as well (or 
cross-reference?).


Looks good to me otherwise, thanks for clarifying this new process.

Cheers,
Quentin

Re: [PATCH v1 5/9] arm: rockchip: Enable display cpuinfo to be build with SPL_BUILD

[Quentin Schulz]

Hi Anand,

On 5/16/24 10:59 AM, Anand Moon wrote:

Changes help enable CONFIG_DISPLAY_CPUINFO to build with SPL_BUILD for
SoC RK356x and RK3588.
 > Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
  arch/arm/mach-rockchip/Makefile | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c07bdaee4c..6722e7c9ea 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -25,7 +25,7 @@ obj-y += boot_mode.o
  obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
  endif
  
-ifeq ($(CONFIG_TPL_BUILD),)

+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)


If I'm not mistaken, this is a way for disabling building cpu-info.o if 
either in TPL or SPL build mode (therefore only compiling for proper 
build mode).


I think it'd make more sense to convert CONFIG_DISPLAY_CPUINFO into 
three symbols, e.g. CONFIG_TPL_DISPLAY_CPUINFO, CONFIG_SPL_DISPLAY_INFO 
and then use


"""
obj-$(CONFIG_$(TPL_SPL_)DISPLAY_CPUINFO) += cpu-info.o
"""

Also... considering the mail I sent to your first patch in this patch 
series, if we migrate to using sysreset driver to print the reset 
reason, we wouldn't need this file anymore so we could remove it and not 
have to care about this.


Cheers,
Quentin

Re: [PATCH v1 1/9] rockchip: RK3328: Read the reset cause from clock reset unit for RK3328 SoC

[Quentin Schulz]

Hi Anand,

On 5/16/24 10:59 AM, Anand Moon wrote:

Read the reset cause from clock reset unit for RK3328 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
  arch/arm/mach-rockchip/cpu-info.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index 14c7331e1a..fce4bd7541 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -8,12 +8,17 @@
  #include 
  #include 
  #include 
+#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
+#include 
+#endif
  #include 
  #include 
  
  char *get_reset_cause(void)

  {
-   struct rockchip_cru *cru = rockchip_get_cru();
+#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
+   struct rk3328_cru *cru = rockchip_get_cru();
+#endif


NACK.

If I only apply this patch, it breaks support for rk3288 and rk3399 (the 
ones which have a rockchip_cru struct).


Do:

"""

#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
struct rk3328_cru *cru = rockchip_get_cru();
#else
struct rockchip_cru *cru = rockchip_get_cru();
#endif
"""

instead to keep the current support and add stuff.

However, I very much don't like this. There's no need for cpuinfo.c to 
become SoC-specific.


I would recommend to move get_reset_cause() in some file that is SoC 
specific, and out of the DISPLAY_CPUINFO ifdef since it may be useful 
outside of this very specific print_cpuinfo function (c.f. the rk3399 
firefly board).


Yes there's a bit of code duplication then, BUT, nothing guarantees us 
the reset reason will always be stored in that glb_rst_st register and 
moreover, RK3588 already has more reasons that currently supported, and 
this prevents us from expanding it.


You can have a

"""
__weak char *get_reset_cause(void)
{
return "could not get reset cause";
}
"""
in replacement and let SoC-specific files expand it by overriding it.

And to think even further than that, maybe we should actually expand 
drivers/sysreset/sysreset_rockchip.c to support more SoCs.


Then we could get the status via get_status callback from sysreset_ops in

https://elixir.bootlin.com/u-boot/latest/source/common/board_f.c#L904

and remove this cpu-info.c file from the arch/arm/mach-rockchip.

Reporting the SoC could be done with a CPU UCLASS (c.f. what's done for 
IMX8 already), from 
https://elixir.bootlin.com/u-boot/latest/source/common/board_f.c#L176.


This honestly makes more sense to me.

Cheers,
Quentin

Re: [PATCH v1 9/9] rockchip: RK3588: Enable display cpuinfo support on all boards

[Quentin Schulz]

Hi Anand,

On 5/16/24 12:12 PM, Anand Moon wrote:

Hi Quentin

On Thu, 16 May 2024 at 14:52, Quentin Schulz  wrote:


Hi Anand,

This is patch 9/9 but somehow I didn't receive any other patch, nor did
the mailing list? c.f.
https://lists.denx.de/pipermail/u-boot/2024-May/thread.html and
https://lore.kernel.org/u-boot/. Are you registered on the ML?



Thanks for your  review comments.

Something went wrong with git sendmail,
Your message have not reached my email client (gmail)



A mail server rejected the mail to edgeble.ai domain (both you and 
Jagan) /me shrugs.



On 5/16/24 10:59 AM, Anand Moon wrote:

Imply DISPLAY_CPUINFO Kconfig options to support on all RK3588s and
RK3588 boards, Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
   arch/arm/mach-rockchip/Kconfig   | 1 +
   configs/coolpi-4b-rk3588s_defconfig  | 1 -
   configs/coolpi-cm5-evb-rk3588_defconfig  | 1 -
   configs/evb-rk3588_defconfig | 1 -
   configs/generic-rk3588_defconfig | 1 -
   configs/jaguar-rk3588_defconfig  | 1 -
   configs/nanopc-t6-rk3588_defconfig   | 1 -
   configs/neu6a-io-rk3588_defconfig| 1 -
   configs/neu6b-io-rk3588_defconfig| 1 -
   configs/orangepi-5-plus-rk3588_defconfig | 1 -
   configs/orangepi-5-rk3588s_defconfig | 1 -
   configs/quartzpro64-rk3588_defconfig | 1 -
   configs/rock5a-rk3588s_defconfig | 1 -
   configs/rock5b-rk3588_defconfig  | 1 -
   configs/toybrick-rk3588_defconfig| 1 -
   configs/turing-rk1-rk3588_defconfig  | 1 -
   16 files changed, 1 insertion(+), 15 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 2e9c71138e..1b5cc34f99 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -366,6 +366,7 @@ config ROCKCHIP_RK3588
   imply SCMI_FIRMWARE
   imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
   imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+ imply DISPLAY_CPUINFO


This is unnecessary, it's already defaulting to y if building for ARM
boards: https://elixir.bootlin.com/u-boot/latest/source/common/Kconfig#L596


See below...

I also don't think this is SO useful that we need to enable it on all
rk3588 boards? But also, doesn't hurt, so... whatever I guess :) ?

While looking at the code, I think we can remove the ifdef in
https://elixir.bootlin.com/u-boot/latest/source/arch/arm/mach-rockchip/cpu-info.c#L47
because this file is anyway only compiled when CONFIG_DISPLAY_CPUINFO is
set, c.f.


Oops I missed this changes, my bad
I will dop my changes over here.


https://elixir.bootlin.com/u-boot/latest/source/arch/arm/mach-rockchip/Makefile#L30


On Rockchip SoC CONFIG_DISPLAY_CPUINFO is been disable on most of the
configs files.

-# CONFIG_DISPLAY_CPUINFO is not set

My changes are related to determine the reset cause of the board and
display the results.
its only enable on selected SoC hence I have to used this logic.



It's enabled for all Aarch64/Aarch32 SoCs by default. People explicitly 
disabled them in their own defconfig, either because the first person 
who added a board based on rk3588 didn't know or didn't care and 
everybody just copied it as a base, or because they don't care about 
it/don't want it.


In any case, you only need to change the defconfigs, nothing else.


U-Boot 2024.07-rc2-00397-g0370324feb-dirty (May 16 2024 - 13:11:14 +0530)

SoC: Rockchip rk3568
Reset cause: POR <---
Model: Radxa ROCK3 Model A
DRAM:  8 GiB (effective 7.7 GiB)
PMIC:  RK8090 (on=0x40, off=0x00)
Core:  344 devices, 31 uclasses,
 >> which also means...


https://elixir.bootlin.com/u-boot/latest/source/arch/arm/include/asm/arch-rockchip/cru.h#L35
should probably be ifdef'ed

which means...

https://elixir.bootlin.com/u-boot/latest/source/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c#L64
should probably also be ifdef'ed (but the config is enabled already
(well... it wouldn't compile otherwsie), so I guess this is fine?).


This code changes will not affect this feature by default its enable
on RK3399 boards.



Yes, but if you disable it, it won't compile anymore. (I'm not asking 
you to fix anything I've reported here though).


Cheers,
Quentin

Re: [PATCH v1 9/9] rockchip: RK3588: Enable display cpuinfo support on all boards

[Quentin Schulz]

Hi Anand,

This is patch 9/9 but somehow I didn't receive any other patch, nor did 
the mailing list? c.f. 
https://lists.denx.de/pipermail/u-boot/2024-May/thread.html and 
https://lore.kernel.org/u-boot/. Are you registered on the ML?


On 5/16/24 10:59 AM, Anand Moon wrote:

Imply DISPLAY_CPUINFO Kconfig options to support on all RK3588s and
RK3588 boards, Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
  arch/arm/mach-rockchip/Kconfig   | 1 +
  configs/coolpi-4b-rk3588s_defconfig  | 1 -
  configs/coolpi-cm5-evb-rk3588_defconfig  | 1 -
  configs/evb-rk3588_defconfig | 1 -
  configs/generic-rk3588_defconfig | 1 -
  configs/jaguar-rk3588_defconfig  | 1 -
  configs/nanopc-t6-rk3588_defconfig   | 1 -
  configs/neu6a-io-rk3588_defconfig| 1 -
  configs/neu6b-io-rk3588_defconfig| 1 -
  configs/orangepi-5-plus-rk3588_defconfig | 1 -
  configs/orangepi-5-rk3588s_defconfig | 1 -
  configs/quartzpro64-rk3588_defconfig | 1 -
  configs/rock5a-rk3588s_defconfig | 1 -
  configs/rock5b-rk3588_defconfig  | 1 -
  configs/toybrick-rk3588_defconfig| 1 -
  configs/turing-rk1-rk3588_defconfig  | 1 -
  16 files changed, 1 insertion(+), 15 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 2e9c71138e..1b5cc34f99 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -366,6 +366,7 @@ config ROCKCHIP_RK3588
imply SCMI_FIRMWARE
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+   imply DISPLAY_CPUINFO


This is unnecessary, it's already defaulting to y if building for ARM 
boards: https://elixir.bootlin.com/u-boot/latest/source/common/Kconfig#L596


I also don't think this is SO useful that we need to enable it on all 
rk3588 boards? But also, doesn't hurt, so... whatever I guess :) ?


While looking at the code, I think we can remove the ifdef in 
https://elixir.bootlin.com/u-boot/latest/source/arch/arm/mach-rockchip/cpu-info.c#L47 
because this file is anyway only compiled when CONFIG_DISPLAY_CPUINFO is 
set, c.f. 
https://elixir.bootlin.com/u-boot/latest/source/arch/arm/mach-rockchip/Makefile#L30


which also means...

https://elixir.bootlin.com/u-boot/latest/source/arch/arm/include/asm/arch-rockchip/cru.h#L35 
should probably be ifdef'ed


which means...

https://elixir.bootlin.com/u-boot/latest/source/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c#L64 
should probably also be ifdef'ed (but the config is enabled already 
(well... it wouldn't compile otherwsie), so I guess this is fine?).


Cheers,
Quentin

Re: [PATCH v3] rockchip: rv1126: Migrate to OF_UPSTREAM

[Quentin Schulz]

Hi Anand,

On 5/13/24 2:07 PM, Anand Moon wrote:

[You don't often get email from an...@edgeble.ai. Learn why this is important 
at https://aka.ms/LearnAboutSenderIdentification ]

Hi Quentin,

On Mon, 13 May 2024 at 16:10, Quentin Schulz  wrote:


Hi Anand,

On 5/11/24 6:12 PM, Anand Moon wrote:

[You don't often get email from an...@edgeble.ai. Learn why this is important 
at https://aka.ms/LearnAboutSenderIdentification ]

Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.

Following targets is migrated to use OF_UPSTREAM:

- rv1126-edgeble-neu2 : Board is an industrial form factor
  IO board.
- sonoff-ihost-rv1126 : Gateway device designed to provide a
  Smart Home Hub.

Cc: Tim Lunn 
Cc: Jagan Teki 
Reviewed-By: Tim Lunn 
Tested-By: Tim Lunn 
Reviewed-by: Kever Yang 
Signed-off-by: Anand Moon 


Doesn't match the mail address sending this patch :)


Earlier I sent this patch with my email ID,
Since I am testing these new boards,
I will use this edgable.ai email ID for source code changes to boards.
if needed I could send this with From: Anand Moon 



Up to you, it is just particularly odd that there's only one letter 
difference between those two mail addresses, which very much looks like 
a typo:

edgeble.ai and
edgable.ai

But if this was on purpose, nothing against it :)

(I made a similar typo in a kernel patch recently, hence why I brought 
this up :) )


Cheers,
Quentin

Re: [PATCH v3] rockchip: rv1126: Migrate to OF_UPSTREAM

[Quentin Schulz]

Hi Anand,

On 5/11/24 6:12 PM, Anand Moon wrote:

[You don't often get email from an...@edgeble.ai. Learn why this is important 
at https://aka.ms/LearnAboutSenderIdentification ]

Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.

Following targets is migrated to use OF_UPSTREAM:

- rv1126-edgeble-neu2 : Board is an industrial form factor
 IO board.
- sonoff-ihost-rv1126 : Gateway device designed to provide a
 Smart Home Hub.

Cc: Tim Lunn 
Cc: Jagan Teki 
Reviewed-By: Tim Lunn 
Tested-By: Tim Lunn 
Reviewed-by: Kever Yang 
Signed-off-by: Anand Moon 


Doesn't match the mail address sending this patch :)

Cheers,
Quentin

Re: [PATCH v2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module

[Quentin Schulz]

Hi Kever,

On 5/8/24 4:42 AM, Kever Yang wrote:

Hi Quentin,

     Could you please update this patch with OF_UPSTREAM support?



No, I cannot yet :/

Tiger is only available in Linux kernel v6.9-rcX and dts/ in U-Boot is 
currently at v6.8.


What are we supposed to do for this then?

Would bumping dts/ to an -rc tag be ok for U-Boot? After all, those are 
rc and not "stable" branches. Do we need to wait for the actual kernel 
release before bumping dts/ (so wait for up to 2 months before 
supporting a board in U-Boot)? Should we have an intermediate solution 
where we use the "old" model (NOT OF_UPSTREAM) until we bump dts/ to the 
latest kernel release and the DTS is available through OF_UPSTREAM?


Cheers,
Quentin

Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock

[Quentin Schulz]

Hi Jonas,

On 5/6/24 5:17 PM, Jonas Karlman wrote:

Hi Quentin,

On 2024-05-06 13:07, Quentin Schulz wrote:

Hi Jonas,

On 5/1/24 6:22 PM, Jonas Karlman wrote:

rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
SCLK_PCIEPHY_REF clock.

The existing enable/disable ops for SCLK_PCIEPHY_REF currently force
use of 24 MHz parent and rate.

Add improved support for setting parent and rate of the pciephy refclk
to driver to better support assign-clock props for pciephy refclk in DT.

This limited implementation only support setting 24 or 100 MHz rate,
and expect npll and clk_pciephy_ref100m divider to use default values.

Signed-off-by: Jonas Karlman 
---
v2: Implement partial instead of dummy support for SCLK_PCIEPHY_REF
---
   drivers/clk/rockchip/clk_rk3399.c | 59 +--
   1 file changed, 57 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 5934771b4096..0b3223611a32 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -926,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru 
*cru, uint hz)
return rk3399_saradc_get_clk(cru);
   }
   
+static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)

+{
+   if (readl(>clksel_con[18]) & BIT(10))
+   return 100 * MHz;
+   else
+   return OSC_HZ;


Could avoid the else since all if blocks return, no other logic than the
one matching the else can reach that part of the code.

Therefore:

"""
if (readl(>clksel_con[18]) & BIT(10))
  return 100 * MHz;

return OSC_HZ;
"""

works just as well.


I was considering above format at first, but chose to align return
statements for some reason.

I can change to this format in a v3, if needed :-)



Just a matter of taste :)



Could also be

"""
return (readl(>clksel_con[18]) & BIT(10)) ? 100 * MHz : OSC_HZ;
"""

[...]

+static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
+   struct clk *parent)
+{
+   struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+   const char *clock_output_name;
+   int ret;
+
+   if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
+   rk_setreg(>cru->clksel_con[18], BIT(10));
+   return 0;
+   }
+
+   ret = dev_read_string_index(parent->dev, "clock-output-names",
+   parent->id, _output_name);


Are you sure this works?


It should work for the clk reference I tested, <>, where the id
will be 0, it should also work for e.g. < 1>, id will be 1.

And if a / clk is referenced those nodes do not have the
clock-output-names prop, so ret should be -EINVAL (or -ENODATA).



Considering that parent->id seems to store unique ids, like 167 for
SCLK_PCIEPHY_REF100M, I doubt we should be using it for
dev_read_string_index

As per documentation:

"""
/**
   * dev_read_string_index() - obtain an indexed string from a string list
   *
   * @dev: device to examine
   * @propname: name of the property containing the string list
   * @index: index of the string to return
   * @outp: return location for the string
   *
   * Return:
   *   length of string, if found or -ve error value if not found
   */
int dev_read_string_index(const struct udevice *dev, const char *propname,
  int index, const char **outp);
"""

So index here means the (index+1)'th string in the list of strings under
the "propname" DT property, I doubt we have properties with 167+ strings
in them?


I would expect the function to return -EINVAL or -ENODATA if it is called
with an out-of-bounds index value.



-ENODATA it seems. -EINVAL if the property doesn't exist.



I realize that rk3399_gmac_set_parent also uses this, so I'm a bit
puzzled right now...

Don't you want to use

dev_read_stringlist_search(parent->dev, "clock-output-names", "xin24m")

instead?


I think the implementation is correct and is what other rk clk drivers
do for gmac set parent ops.

Using dev_read_stringlist_search() could possible match a name for
"wrong" clock, e.g:

clk_ref: clock {
#clock-cells = <1>;
clock-output-names = "xin32k", "xin24m";
};

here only <_ref 1> should match and not <_ref 0>.



Ah well, one more brain fart :) I somehow mixed things up and was 
thinking about the values in clocks/assigned-clocks in one node needing 
to match the offset in clock-names of that same node, which made no 
sense. But we're talking about different things here :)


I guess it's just a matter of taste between the implementation in your 
patch and the inverted logic which tries to find xin24m in 
clock-output-n

Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock

[Quentin Schulz]

Hi Jonas,

On 5/1/24 6:22 PM, Jonas Karlman wrote:

rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
SCLK_PCIEPHY_REF clock.

The existing enable/disable ops for SCLK_PCIEPHY_REF currently force
use of 24 MHz parent and rate.

Add improved support for setting parent and rate of the pciephy refclk
to driver to better support assign-clock props for pciephy refclk in DT.

This limited implementation only support setting 24 or 100 MHz rate,
and expect npll and clk_pciephy_ref100m divider to use default values.

Signed-off-by: Jonas Karlman 
---
v2: Implement partial instead of dummy support for SCLK_PCIEPHY_REF
---
  drivers/clk/rockchip/clk_rk3399.c | 59 +--
  1 file changed, 57 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 5934771b4096..0b3223611a32 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -926,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru 
*cru, uint hz)
return rk3399_saradc_get_clk(cru);
  }
  
+static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)

+{
+   if (readl(>clksel_con[18]) & BIT(10))
+   return 100 * MHz;
+   else
+   return OSC_HZ;


Could avoid the else since all if blocks return, no other logic than the 
one matching the else can reach that part of the code.


Therefore:

"""
if (readl(>clksel_con[18]) & BIT(10))
return 100 * MHz;

return OSC_HZ;
"""

works just as well.

Could also be

"""
return (readl(>clksel_con[18]) & BIT(10)) ? 100 * MHz : OSC_HZ;
"""

[...]

+static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
+   struct clk *parent)
+{
+   struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+   const char *clock_output_name;
+   int ret;
+
+   if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
+   rk_setreg(>cru->clksel_con[18], BIT(10));
+   return 0;
+   }
+
+   ret = dev_read_string_index(parent->dev, "clock-output-names",
+   parent->id, _output_name);


Are you sure this works?

Considering that parent->id seems to store unique ids, like 167 for 
SCLK_PCIEPHY_REF100M, I doubt we should be using it for 
dev_read_string_index


As per documentation:

"""
/**
 * dev_read_string_index() - obtain an indexed string from a string list
 *
 * @dev: device to examine
 * @propname: name of the property containing the string list
 * @index: index of the string to return
 * @outp: return location for the string
 *
 * Return:
 *   length of string, if found or -ve error value if not found
 */
int dev_read_string_index(const struct udevice *dev, const char *propname,
  int index, const char **outp);
"""

So index here means the (index+1)'th string in the list of strings under 
the "propname" DT property, I doubt we have properties with 167+ strings 
in them?


I realize that rk3399_gmac_set_parent also uses this, so I'm a bit 
puzzled right now...


Don't you want to use

dev_read_stringlist_search(parent->dev, "clock-output-names", "xin24m")

instead?

The rest looks good to me.

Cheers,
Quentin

Re: [PATCH] board: rockchip: add ArmSoM Sige7 Rk3588 board

[Quentin Schulz]

Hi Jianfeng Liu,

On 5/4/24 7:05 PM, Jianfeng Liu wrote:

[You don't often get email from liujianfeng1...@gmail.com. Learn why this is 
important at https://aka.ms/LearnAboutSenderIdentification ]

ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by
ArmSoM.

There are two variants depending on the DRAM size : 8G and 16G.

Specification:

 Rockchip Rk3588 SoC
 4x ARM Cortex-A76, 4x ARM Cortex-A55
 8/16GB memory LPDDR4x
 Mali G610MC4 GPU
 2x MIPI CSI 2 multiple lanes connector
 64GB/128GB on board eMMC
 uSD slot
 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C
 1x HDMI 2.1 output
 2x 2.5 Gbps Ethernet port
 40-pin IO header including UART, SPI and I2C
 USB PD over USB Type-C
 Size: 92mm x 62mm

Kernel commit:
81c828a67c78 (arm64: dts: rockchip: Add ArmSom Sige7 board)

Note that these commits:
- e18e5e8188f2 (arm64: dts: rockchip: add USBDP phys on rk3588)
- 6fca4edb93d3 (arm64: dts: rockchip: Add rk3588 GPU node)
are not synced to u-boot, so I remove usb3 drd nodes and gpu from kernel
devicetree.

Signed-off-by: Jianfeng Liu 
---

  MAINTAINERS  |   1 +
  arch/arm/dts/Makefile|   1 +
  arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi |  31 +
  arch/arm/dts/rk3588-armsom-sige7.dts | 691 +++
  arch/arm/mach-rockchip/rk3588/Kconfig|  26 +
  board/armsom/sige7-rk3588/Kconfig|  12 +
  board/armsom/sige7-rk3588/MAINTAINERS|   8 +
  configs/sige7-rk3588_defconfig   | 104 +++
  doc/board/rockchip/rockchip.rst  |   1 +
  include/configs/sige7-rk3588.h   |  15 +
  10 files changed, 890 insertions(+)
  create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
  create mode 100644 arch/arm/dts/rk3588-armsom-sige7.dts
  create mode 100644 board/armsom/sige7-rk3588/Kconfig
  create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS
  create mode 100644 configs/sige7-rk3588_defconfig
  create mode 100644 include/configs/sige7-rk3588.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 7a3b4d3712..52367bf38c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -532,6 +532,7 @@ F:  arch/arm/dts/rv11*
  F: arch/arm/include/asm/arch-rockchip/
  F: arch/arm/mach-rockchip/
  F: board/amarula/vyasa-rk3288/
+F: board/armsom/sige7-rk3588/


Can you order this alphabetically please?


  F: board/anbernic/rgxx3_rk3566/
  F: board/chipspark/popmetal_rk3288
  F: board/engicam/px30_core/
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c9f1b25ad6..040238dede 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
 rk3568-rock-3a.dtb

  dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+   rk3588-armsom-sige7.dtb \
 rk3588s-coolpi-4b.dtb \
 rk3588-coolpi-cm5-evb.dtb \
 rk3588-edgeble-neu6a-io.dtb \
diff --git a/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi 
b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
new file mode 100644
index 00..b9196ba5f5
--- /dev/null
+++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 ArmSoM Technology Co., Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+ {
+   cap-mmc-highspeed;


I think this isn't supported in U-Boot on RK35xx devices just yet? We 
force everything to be HS200+ anyway if I remember correctly.



+   mmc-hs200-1_8v;
+};
+
+ {
+   status = "okay";
+};
+
+_otg {
+   status = "okay";
+};
+
+_phy1 {
+   status = "okay";
+};
+
+_phy1_u3 {
+   status = "okay";
+};
+
+_host1_xhci {
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-armsom-sige7.dts 
b/arch/arm/dts/rk3588-armsom-sige7.dts
new file mode 100644
index 00..c7b46536ec
--- /dev/null
+++ b/arch/arm/dts/rk3588-armsom-sige7.dts
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include 
+#include 
+#include "rk3588.dtsi"
+
+/ {
+   model = "ArmSoM Sige7";
+   compatible = "armsom,sige7", "rockchip,rk3588";
+
+   aliases {
+   mmc0 = 
+   mmc1 = 
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   analog-sound {
+   compatible = "audio-graph-card";
+   dais = <_8ch_p0>;
+   label = "rk3588-es8316";
+   hp-det-gpio = < RK_PD5 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_detect>;
+   routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+   widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = 

Re: [PATCH v3] configs: rk3588-turing-rk1: disable SPI flash by default

[Quentin Schulz]

Hi Sam,

On 5/2/24 10:07 PM, Sam Edwards wrote:

While the Turing RK1 board has a pad on the PCB for SPI flash, it is
not populated at the factory: supporting SPI flash boot is a user
modification, not an out-of-the-box feature. The defconfig for this
board should therefore not be enabling the SPI flash image nor SPI
support in the SPL, as it causes confusion among downstream users as to
whether the SPI image needs to be distributed.

Fixes: 153ac950a599 ("board: rockchip: Add the Turing RK1 SoM")
Suggested-by: Florian Klink 
Signed-off-by: Sam Edwards 
Acked-by: Joshua Riek 
Reviewed-by: Jonas Karlman 


Reviewed=by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH V2] board: rockchip: Add Indiedroid Nova

[Quentin Schulz]

Hi Chris,

On 5/2/24 8:57 PM, Chris Morgan wrote:

From: Chris Morgan 

The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.

Specifications:

 Rockchip RK3588S SoC
 4x ARM Cortex-A76, 4x ARM Cortex-A55
 4/8/16GB memory LPDDR4x
 Mali G610MC4 GPU
 Optional eMMC
 2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
 1x MIPI-CSI Port (4-lane or 2x 2-lane)
 1x MIPI-DSI 4-lane connector
 1x Micro HDMI 2.1 output, 1x DP 1.4 output
 Gigabit Ethernet
 Realtek RTL8821CS WiFi
 4 pin debug UART connector
 40 pin GPIO header
 Size: 85mm x 56mm (Raspberry Pi Form Factor)

Kernel commit:
3900160e164b ("arm64: dts: rockchip: Add Indiedroid Nova board")

Signed-off-by: Chris Morgan 
---

Changes since V1:
  - Refactored to use the upstream Linux device tree now that that is
an option.


Lucky you, I still have to wait for a bump of the upstream dts repo 
"copy" to be able to use this for Tiger (will be in v6.9, so not too 
long to wait for anymore :) ).



  - Added board to doc/board/rockchip/rockchip.rst.

---
  arch/arm/mach-rockchip/rk3588/Kconfig | 10 
  board/indiedroid/nova/Kconfig | 12 +
  board/indiedroid/nova/MAINTAINERS |  6 +++
  configs/nova-rk3588s_defconfig| 70 +++
  doc/board/rockchip/rockchip.rst   |  1 +
  include/configs/nova-rk3588s.h| 15 ++
  6 files changed, 114 insertions(+)
  create mode 100644 board/indiedroid/nova/Kconfig
  create mode 100644 board/indiedroid/nova/MAINTAINERS
  create mode 100644 configs/nova-rk3588s_defconfig
  create mode 100644 include/configs/nova-rk3588s.h

diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig 
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 39049ab35a..820e979abb 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -78,6 +78,15 @@ config TARGET_NANOPCT6_RK3588
  Power: 5.5*2.1mm DC Jack, 12VDC input
  Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
  
+config TARGET_NOVA_RK3588

+   bool "Indiedroid Nova RK3588"
+   select BOARD_LATE_INIT
+   help
+ Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
+ It comes in configurations from 4GB of RAM to 16GB of RAM,
+ includes socket for eMMC storage, an SDMMC slot, and a 40-pin
+ GPIO header for expansion.
+
  config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
@@ -223,6 +232,7 @@ config TEXT_BASE
  
  source "board/edgeble/neural-compute-module-6/Kconfig"

  source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/indiedroid/nova/Kconfig"
  source "board/pine64/quartzpro64-rk3588/Kconfig"
  source "board/turing/turing-rk1-rk3588/Kconfig"
  source "board/radxa/rock5a-rk3588s/Kconfig"
diff --git a/board/indiedroid/nova/Kconfig b/board/indiedroid/nova/Kconfig
new file mode 100644
index 00..271d15a0ed
--- /dev/null
+++ b/board/indiedroid/nova/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NOVA_RK3588
+
+config SYS_BOARD
+   default "nova-rk3588s"
+
+config SYS_VENDOR
+   default "indiedroid"
+
+config SYS_CONFIG_NAME
+   default "nova-rk3588s"
+
+endif
diff --git a/board/indiedroid/nova/MAINTAINERS 
b/board/indiedroid/nova/MAINTAINERS
new file mode 100644
index 00..9c56d01bf0
--- /dev/null
+++ b/board/indiedroid/nova/MAINTAINERS
@@ -0,0 +1,6 @@
+INDIEDROID-NOVA-RK3588
+M: Chris Morgan 
+S: Maintained
+F: board/indiedroid/nova
+F: include/configs/nova-rk3588s.h
+F: configs/indiedroid-nova-rk3588_defconfig


Typo here, missing an s after rk3588 :)

Looking good to me otherwise.

Cheers,
Quentin

Re: [PATCH] rockchip: Correct UUID for root partitions

[Quentin Schulz]

Hi Chris,

On 4/26/24 5:33 PM, Chris Morgan wrote:

From: Chris Morgan 

For root partitions, the UUID should still be random but the partition
type uuid should either be b921b045-1df0-41c3-af44-4c6f280d3fae for
aarch64 or 69dad710-2ce4-4e3c-b16c-21a1d49abed3 for aarch32. Correct
the attribute so it is the partition type that is hard coded and not
the partition unique identifier.

Note that in order for "type" to be used the config option
CONFIG_PARTITION_TYPE_GUID must be enabled. If this option is not
enabled then the type is ignored and instead the partition type
remains the generic ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 for a
Linux data partition.

Fixes: 42ec247e6988 ("rockchip: use UUID for root partitions")
Signed-off-by: Chris Morgan 
---
  include/configs/rockchip-common.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/rockchip-common.h 
b/include/configs/rockchip-common.h
index 9121bba373..f620579248 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -26,7 +26,7 @@
"name=loader2,start=8MB,size=4MB,uuid=${uuid_gpt_loader2};" \
"name=trust,size=4M,uuid=${uuid_gpt_atf};" \
"name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \
-   "name=rootfs,size=-,uuid="ROOT_UUID
+   "name=rootfs,size=-,uuid=${uuid_gpt_rootfs},type="ROOT_UUID


I would recommend to rename ROOT_UUID to ROOT_GUID also, since it's what 
it is, c.f. 
https://en.wikipedia.org/wiki/GUID_Partition_Table#Partition_type_GUIDs


BTW, it seems that type is optional, so maybe we could afford to just 
remove the whole thing? I don't see anything else defining that type 
parameter?


c.f. https://elixir.bootlin.com/u-boot/latest/source/cmd/gpt.c#L536

Also, this code is guarded by CONFIG_PARTITION_TYPE_GUID which seems to 
only be enabled for RK3399 and no other SoC or Rockchip board... so not 
sure it's *THAT* useful (or if it is, are we missing out on enabling on 
other boards/SoCs).


Additionally, I cannot find anything setting uuid_gpt_rootfs environment 
variable anywhere. I'm a bit lost to be honest. Are we maybe randomly 
generating this uuid at runtime? (RANDOM_UUID is implied by CMD_GPT 
after all so it isn't too much of a stretch).


Cheers,
Quentin

Re: [PATCH] binman: Fix typo in mkimage etype description

[Quentin Schulz]

Hi Marek,

On 4/26/24 12:54 AM, Marek Vasut wrote:

Fix a typo, no functional change.

Signed-off-by: Marek Vasut 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH v4 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588

[Quentin Schulz]

Hi Kever,

On 4/26/24 09:41, Kever Yang wrote:

Hi Quentin,

On 2024/4/25 18:46, Quentin Schulz wrote:

From: Quentin Schulz 

Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
more than 16GB of RAM. In the event that neither SoC is used or the
ROCKCHIP_TPL stage is not used, fall back to existing logic.

The logic handles creating memory holes from reserved memory areas
defined in mem_map data struct in SoC C files, but only if the DRAM area
overlaps with one reserved memory area.

Since mem_map data struct is used, it should be rather straightforward
to add support for other SoCs if needed.

The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1
(e08e32143dd).

Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as
well, but the DDR_MEM tag seems to be pretty much stable (though BL31
seems to be reserving only 1MB for itself at the moment).

u32 for ATAGS is used because it simplifies the pointer arithmetic and
it's expected that ATAGS are always below the 4GB limit allowed by u32.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 


This breaks rv1126 build which is non ARM64 platform, I can fix it and 
apply it directly.




Thanks!

Cheers,
Quentin

[PATCH v4 11/11] rockchip: rk356x: use DRAM banks from ATAGS

[Quentin Schulz]

From: Quentin Schulz 

RK356x-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 configs/anbernic-rgxx3-rk3566_defconfig   | 1 -
 configs/bpi-r2-pro-rk3568_defconfig   | 1 -
 configs/evb-rk3568_defconfig  | 1 -
 configs/generic-rk3568_defconfig  | 1 -
 configs/lubancat-2-rk3568_defconfig   | 1 -
 configs/nanopi-r5c-rk3568_defconfig   | 1 -
 configs/nanopi-r5s-rk3568_defconfig   | 1 -
 configs/odroid-m1-rk3568_defconfig| 1 -
 configs/pinetab2-rk3566_defconfig | 1 -
 configs/quartz64-a-rk3566_defconfig   | 1 -
 configs/quartz64-b-rk3566_defconfig   | 1 -
 configs/radxa-cm3-io-rk3566_defconfig | 1 -
 configs/radxa-e25-rk3568_defconfig| 1 -
 configs/rock-3a-rk3568_defconfig  | 1 -
 configs/soquartz-blade-rk3566_defconfig   | 1 -
 configs/soquartz-cm4-rk3566_defconfig | 1 -
 configs/soquartz-model-a-rk3566_defconfig | 1 -
 17 files changed, 17 deletions(-)

diff --git a/configs/anbernic-rgxx3-rk3566_defconfig 
b/configs/anbernic-rgxx3-rk3566_defconfig
index c8c9238f96f..aa3809e00c1 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
diff --git a/configs/bpi-r2-pro-rk3568_defconfig 
b/configs/bpi-r2-pro-rk3568_defconfig
index 5cc95241ba4..0f85dc63c55 100644
--- a/configs/bpi-r2-pro-rk3568_defconfig
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 6e8061f5f48..f2f429d33c4 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index e7d5e55bbfd..8f4a6259a27 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/lubancat-2-rk3568_defconfig 
b/configs/lubancat-2-rk3568_defconfig
index 1c50a0ccbe6..ea67b6a7286 100644
--- a/configs/lubancat-2-rk3568_defconfig
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/nanopi-r5c-rk3568_defconfig 
b/configs/nanopi-r5c-rk3568_defconfig
index 0f1a9461a0c..00743b7f926 100644
--- a/configs/nanopi-r5c-rk3568_defconfig
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/nanopi-r5s-rk3568_defconfig 
b/configs/nanopi-r5s-rk3568_defconfig
index 4ebf0cc9ee8..91e3a19dea6 100644
--- a/configs/nanopi-r5s-rk3568_defconfig
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/odroid-m1-rk3568_defconfig 
b/configs/odroid-m1-rk3568_defconfig
index b5ed9e4bc98..e749f9af9d2 100644
--- a/configs/odroid-m1-rk3568_defconfig
+++ b/configs/odroid-m1-rk3568_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_SF_DEFAULT_SPEED=2400
 CONFIG_SF_DEFAULT_MODE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1"
diff --git a/configs/

[PATCH v4 10/11] rockchip: rk3588: use DRAM banks from ATAGS

[Quentin Schulz]

From: Quentin Schulz 

RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 configs/jaguar-rk3588_defconfig   | 1 -
 configs/neu6a-io-rk3588_defconfig | 1 -
 configs/neu6b-io-rk3588_defconfig | 1 -
 3 files changed, 3 deletions(-)

diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index 3233b75cee9..f29505ea150 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_SF_DEFAULT_SPEED=2400
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_ENV_SIZE=0x1f000
diff --git a/configs/neu6a-io-rk3588_defconfig 
b/configs/neu6a-io-rk3588_defconfig
index 307a540f424..2b939e6795f 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/neu6b-io-rk3588_defconfig 
b/configs/neu6b-io-rk3588_defconfig
index 9ef2bb21fff..d0fa0dca7ac 100644
--- a/configs/neu6b-io-rk3588_defconfig
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_SERIAL=y

-- 
2.44.0

[PATCH v4 09/11] rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS

[Quentin Schulz]

From: Quentin Schulz 

RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.

Similarly, because the turing-rk1-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 board/turing/turing-rk1-rk3588/Makefile|  6 
 board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c | 39 --
 configs/turing-rk1-rk3588_defconfig|  2 --
 3 files changed, 47 deletions(-)

diff --git a/board/turing/turing-rk1-rk3588/Makefile 
b/board/turing/turing-rk1-rk3588/Makefile
deleted file mode 100644
index a979d8023aa..000
--- a/board/turing/turing-rk1-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += turing-rk1-rk3588.o
diff --git a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c 
b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
deleted file mode 100644
index e2338a2a35a..000
--- a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include 
-#include 
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-   struct fdt_memory gap1 = {
-   .start = 0x3fc00,
-   .end = 0x3fc4f,
-   };
-   struct fdt_memory gap2 = {
-   .start = 0x3fff0,
-   .end = 0x3,
-   };
-   unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-   unsigned int ret;
-
-   /*
-* Inject the reserved-memory nodes into the DTS
-*/
-   ret = fdtdec_add_reserved_memory(new_blob, "gap1", ,  NULL, 0,
-NULL, flags);
-   if (ret)
-   return ret;
-
-   return fdtdec_add_reserved_memory(new_blob, "gap2", ,  NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-   return turing_rk1_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/turing-rk1-rk3588_defconfig 
b/configs/turing-rk1-rk3588_defconfig
index e18ced72178..49d62410ca0 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_SF_DEFAULT_SPEED=2400
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y

-- 
2.44.0

[PATCH v4 08/11] rockchip: toybrick_rk3588: use DRAM banks from ATAGS

[Quentin Schulz]

From: Quentin Schulz 

RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.

Similarly, because the toybrick_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 board/rockchip/toybrick_rk3588/Makefile  |  6 
 board/rockchip/toybrick_rk3588/toybrick-rk3588.c | 39 
 configs/toybrick-rk3588_defconfig|  2 --
 3 files changed, 47 deletions(-)

diff --git a/board/rockchip/toybrick_rk3588/Makefile 
b/board/rockchip/toybrick_rk3588/Makefile
deleted file mode 100644
index 75d4d9438f7..000
--- a/board/rockchip/toybrick_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += toybrick-rk3588.o
diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c 
b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
deleted file mode 100644
index e3217f70b50..000
--- a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
- */
-
-#include 
-#include 
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-   struct fdt_memory gap1 = {
-   .start = 0x3fc00,
-   .end = 0x3fc4f,
-   };
-   struct fdt_memory gap2 = {
-   .start = 0x3fff0,
-   .end = 0x3,
-   };
-   unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-   int ret;
-
-   /*
-* Inject the reserved-memory nodes into the DTS
-*/
-   ret = fdtdec_add_reserved_memory(new_blob, "gap1", ,  NULL, 0,
-NULL, flags);
-   if (ret)
-   return ret;
-
-   return fdtdec_add_reserved_memory(new_blob, "gap2", ,  NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-   return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/toybrick-rk3588_defconfig 
b/configs/toybrick-rk3588_defconfig
index 6ee92e94313..675e7d89e12 100644
--- a/configs/toybrick-rk3588_defconfig
+++ b/configs/toybrick-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y

-- 
2.44.0

[PATCH v4 07/11] rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS

[Quentin Schulz]

From: Quentin Schulz 

RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.

Similarly, because the evb_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

All defconfigs using the CONFIG_TARGET_EVB_RK3588 are updated at once
since they are impacted by this change.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 board/rockchip/evb_rk3588/Makefile   |  6 -
 board/rockchip/evb_rk3588/evb-rk3588.c   | 39 
 configs/coolpi-4b-rk3588s_defconfig  |  2 --
 configs/coolpi-cm5-evb-rk3588_defconfig  |  2 --
 configs/evb-rk3588_defconfig |  2 --
 configs/generic-rk3588_defconfig |  2 --
 configs/orangepi-5-plus-rk3588_defconfig |  2 --
 configs/orangepi-5-rk3588s_defconfig |  2 --
 8 files changed, 57 deletions(-)

diff --git a/board/rockchip/evb_rk3588/Makefile 
b/board/rockchip/evb_rk3588/Makefile
deleted file mode 100644
index 240d2ec597e..000
--- a/board/rockchip/evb_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += evb-rk3588.o
diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c 
b/board/rockchip/evb_rk3588/evb-rk3588.c
deleted file mode 100644
index caf94d8d29c..000
--- a/board/rockchip/evb_rk3588/evb-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include 
-#include 
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-   struct fdt_memory gap1 = {
-   .start = 0x3fc00,
-   .end = 0x3fc4f,
-   };
-   struct fdt_memory gap2 = {
-   .start = 0x3fff0,
-   .end = 0x3,
-   };
-   unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-   unsigned int ret;
-
-   /*
-* Inject the reserved-memory nodes into the DTS
-*/
-   ret = fdtdec_add_reserved_memory(new_blob, "gap1", ,  NULL, 0,
-NULL, flags);
-   if (ret)
-   return ret;
-
-   return fdtdec_add_reserved_memory(new_blob, "gap2", ,  NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-   return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/coolpi-4b-rk3588s_defconfig 
b/configs/coolpi-4b-rk3588s_defconfig
index a0fe3708344..2608bb67679 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_SF_DEFAULT_SPEED=2400
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig 
b/configs/coolpi-cm5-evb-rk3588_defconfig
index fc17660da2a..c5bb7a42957 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_SF_DEFAULT_SPEED=2400
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index c8db04c076e..187cf26a5c9 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FI

[PATCH v4 06/11] rockchip: rock5b-rk3588: use DRAM banks from ATAGS

[Quentin Schulz]

From: Quentin Schulz 

RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.

Similarly, because the rock5b-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 board/radxa/rock5b-rk3588/Makefile|  6 -
 board/radxa/rock5b-rk3588/rock5b-rk3588.c | 39 ---
 configs/rock5b-rk3588_defconfig   |  2 --
 3 files changed, 47 deletions(-)

diff --git a/board/radxa/rock5b-rk3588/Makefile 
b/board/radxa/rock5b-rk3588/Makefile
deleted file mode 100644
index 95d813596da..000
--- a/board/radxa/rock5b-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2022 Collabora Ltd.
-#
-
-obj-y += rock5b-rk3588.o
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c 
b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
deleted file mode 100644
index 5c3b52b9489..000
--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include 
-#include 
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5b_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-   struct fdt_memory gap1 = {
-   .start = 0x3fc00,
-   .end = 0x3fc4f,
-   };
-   struct fdt_memory gap2 = {
-   .start = 0x3fff0,
-   .end = 0x3,
-   };
-   unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-   unsigned int ret;
-
-   /*
-* Inject the reserved-memory nodes into the DTS
-*/
-   ret = fdtdec_add_reserved_memory(new_blob, "gap1", ,  NULL, 0,
-NULL, flags);
-   if (ret)
-   return ret;
-
-   return fdtdec_add_reserved_memory(new_blob, "gap2", ,  NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-   return rock5b_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index ac4f1ebb4c1..ea8e3593572 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_SF_DEFAULT_SPEED=2400
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y

-- 
2.44.0

[PATCH v4 05/11] rockchip: rock5a-rk3588s: use DRAM banks from ATAGS

[Quentin Schulz]

From: Quentin Schulz 

RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.

Similarly, because the rock5a-rk3588s.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 board/radxa/rock5a-rk3588s/Makefile |  6 -
 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 -
 configs/rock5a-rk3588s_defconfig|  2 --
 3 files changed, 47 deletions(-)

diff --git a/board/radxa/rock5a-rk3588s/Makefile 
b/board/radxa/rock5a-rk3588s/Makefile
deleted file mode 100644
index 48dd5124550..000
--- a/board/radxa/rock5a-rk3588s/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Collabora Ltd.
-#
-
-obj-y += rock5a-rk3588s.o
diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c 
b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
deleted file mode 100644
index 2d7a8c07dc5..000
--- a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include 
-#include 
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5a_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-   struct fdt_memory gap1 = {
-   .start = 0x3fc00,
-   .end = 0x3fc4f,
-   };
-   struct fdt_memory gap2 = {
-   .start = 0x3fff0,
-   .end = 0x3,
-   };
-   unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-   unsigned int ret;
-
-   /*
-* Inject the reserved-memory nodes into the DTS
-*/
-   ret = fdtdec_add_reserved_memory(new_blob, "gap1", ,  NULL, 0,
-NULL, flags);
-   if (ret)
-   return ret;
-
-   return fdtdec_add_reserved_memory(new_blob, "gap2", ,  NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-   return rock5a_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index ebe2d4a2d81..01df911d9dc 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y

-- 
2.44.0

[PATCH v4 04/11] rockchip: quartzpro64-rk3588: use DRAM banks from ATAGS

[Quentin Schulz]

From: Quentin Schulz 

RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.

Similarly, because the quartzpro64-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 board/pine64/quartzpro64-rk3588/Makefile   |  3 --
 .../pine64/quartzpro64-rk3588/quartzpro64-rk3588.c | 39 --
 configs/quartzpro64-rk3588_defconfig   |  2 --
 3 files changed, 44 deletions(-)

diff --git a/board/pine64/quartzpro64-rk3588/Makefile 
b/board/pine64/quartzpro64-rk3588/Makefile
deleted file mode 100644
index 47819d9be93..000
--- a/board/pine64/quartzpro64-rk3588/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += quartzpro64-rk3588.o
diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c 
b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
deleted file mode 100644
index bda804a89e2..000
--- a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2023 Google, Inc
- */
-
-#include 
-#include 
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-   struct fdt_memory gap1 = {
-   .start = 0x3fc00,
-   .end = 0x3fc4f,
-   };
-   struct fdt_memory gap2 = {
-   .start = 0x3fff0,
-   .end = 0x3,
-   };
-   unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-   unsigned int ret;
-
-   /*
-* Inject the reserved-memory nodes into the DTS
-*/
-   ret = fdtdec_add_reserved_memory(new_blob, "gap1", ,  NULL, 0,
-NULL, flags);
-   if (ret)
-   return ret;
-
-   return fdtdec_add_reserved_memory(new_blob, "gap2", ,  NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-   return quartzpro64_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/quartzpro64-rk3588_defconfig 
b/configs/quartzpro64-rk3588_defconfig
index b2a66d3f2db..e398c7c2c0e 100644
--- a/configs/quartzpro64-rk3588_defconfig
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_SERIAL=y
@@ -19,7 +18,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y

-- 
2.44.0

[PATCH v4 03/11] rockchip: nanopc-t6-rk3588: use DRAM banks from ATAGS

[Quentin Schulz]

From: Quentin Schulz 

RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.

Similarly, because the nanopc-t6-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 board/friendlyelec/nanopc-t6-rk3588/Makefile   |  6 
 .../nanopc-t6-rk3588/nanopc-t6-rk3588.c| 39 --
 configs/nanopc-t6-rk3588_defconfig |  2 --
 3 files changed, 47 deletions(-)

diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile 
b/board/friendlyelec/nanopc-t6-rk3588/Makefile
deleted file mode 100644
index c1c49b19708..000
--- a/board/friendlyelec/nanopc-t6-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += nanopc-t6-rk3588.o
diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c 
b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
deleted file mode 100644
index 99bbef964e0..000
--- a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include 
-#include 
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int nanopc_t6_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-   struct fdt_memory gap1 = {
-   .start = 0x3fc00,
-   .end = 0x3fc4f,
-   };
-   struct fdt_memory gap2 = {
-   .start = 0x3fff0,
-   .end = 0x3,
-   };
-   unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-   unsigned int ret;
-
-   /*
-* Inject the reserved-memory nodes into the DTS
-*/
-   ret = fdtdec_add_reserved_memory(new_blob, "gap1", ,  NULL, 0,
-NULL, flags);
-   if (ret)
-   return ret;
-
-   return fdtdec_add_reserved_memory(new_blob, "gap2", ,  NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-   return nanopc_t6_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/nanopc-t6-rk3588_defconfig 
b/configs/nanopc-t6-rk3588_defconfig
index 5c7bc0b7196..738dda026b0 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_SF_DEFAULT_SPEED=2400
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y

-- 
2.44.0

[PATCH v4 02/11] rockchip: NR_DRAM_BANKS now defaults to 10 when Rockchip TPL blob is used

[Quentin Schulz]

From: Quentin Schulz 

When Rockchip TPL blob is used, the memory areas that can be used for
DRAM is gotten from ATAGS passed through the DRAM at a specific address.

The DDR_MEM tag contains at most 10 areas, so we should default to 10 if
Rockchip TPL blob is used. Note that it is technically possible we need
more if one of those 10 areas overlaps with reserved memory area,
forcing us to split it in two. But a default doesn't need to handle all
cases, only most.

Signed-off-by: Quentin Schulz 
---
 arch/arm/mach-rockchip/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 4f22d9bde9f..644f7997a29 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -574,6 +574,9 @@ config ROCKCHIP_COMMON_STACK_ADDR
imply TPL_SYS_MALLOC_F if TPL
imply TPL_SYS_MALLOC_SIMPLE if TPL
 
+config NR_DRAM_BANKS
+   default 10 if ROCKCHIP_EXTERNAL_TPL
+
 source "arch/arm/mach-rockchip/px30/Kconfig"
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 source "arch/arm/mach-rockchip/rk3066/Kconfig"

-- 
2.44.0

[PATCH v4 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588

[Quentin Schulz]

From: Quentin Schulz 

Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
more than 16GB of RAM. In the event that neither SoC is used or the
ROCKCHIP_TPL stage is not used, fall back to existing logic.

The logic handles creating memory holes from reserved memory areas
defined in mem_map data struct in SoC C files, but only if the DRAM area
overlaps with one reserved memory area.

Since mem_map data struct is used, it should be rather straightforward
to add support for other SoCs if needed.

The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1
(e08e32143dd).

Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as
well, but the DDR_MEM tag seems to be pretty much stable (though BL31
seems to be reserving only 1MB for itself at the moment).

u32 for ATAGS is used because it simplifies the pointer arithmetic and
it's expected that ATAGS are always below the 4GB limit allowed by u32.

Co-developed-by: Chris Morgan 
Signed-off-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
 arch/arm/mach-rockchip/sdram.c | 258 +
 1 file changed, 258 insertions(+)

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f5..405a998cb84 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -35,12 +36,269 @@ struct tos_parameter_t {
s64 reserve[8];
 };
 
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET   (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE)
+
+/* ATAGS memory structures */
+
+enum tag_magic {
+   ATAG_NONE,
+   ATAG_CORE = 0x54410001,
+   ATAG_SERIAL = 0x54410050,
+   ATAG_DDR_MEM = 0x54410052,
+   ATAG_MAX = 0x544100ff,
+};
+
+/*
+ * An ATAG contains the following data:
+ *  - header
+ *u32 size // sizeof(header + tag data) / sizeof(u32)
+ *u32 magic
+ *  - tag data
+ */
+
+struct tag_header {
+   u32 size;
+   u32 magic;
+} __packed;
+
+/*
+ * DDR_MEM tag bank is storing data this way:
+ *  - address0
+ *  - address1
+ *  - [...]
+ *  - addressX
+ *  - size0
+ *  - size1
+ *  - [...]
+ *  - sizeX
+ *
+ *  with X being tag_ddr_mem.count - 1.
+ */
+struct tag_ddr_mem {
+   u32 count;
+   u32 version;
+   u64 bank[20];
+   u32 flags;
+   u32 data[2];
+   u32 hash;
+} __packed;
+
+static u32 js_hash(const void *buf, u32 len)
+{
+   u32 i, hash = 0x47C6A7E6;
+
+   if (!buf || !len)
+   return hash;
+
+   for (i = 0; i < len; i++)
+   hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
+
+   return hash;
+}
+
+static int rockchip_dram_init_banksize(void)
+{
+   const struct tag_header *tag_h = NULL;
+   u32 *addr = (void *)ATAGS_PHYS_BASE;
+   struct tag_ddr_mem *ddr_info;
+   u32 calc_hash;
+   u8 i, j;
+
+   if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+   !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+   return -ENOTSUPP;
+
+   if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+   return -ENOTSUPP;
+
+   /* Find DDR_MEM tag */
+   while (addr < (u32 *)ATAGS_PHYS_END) {
+   tag_h = (const struct tag_header *)addr;
+
+   if (!tag_h->size) {
+   debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
+   return -ENODATA;
+   }
+
+   if (tag_h->magic == ATAG_DDR_MEM)
+   break;
+
+   switch (tag_h->magic) {
+   case ATAG_NONE:
+   case ATAG_CORE:
+   case ATAG_SERIAL ... ATAG_MAX:
+   addr += tag_h->size;
+   continue;
+   default:
+   debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
+ tag_h->magic, addr);
+   return -EINVAL;
+   }
+   }
+
+   if (addr >= (u32 *)ATAGS_PHYS_END ||
+   (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
+   debug("End of ATAGS, no DDR_MEM found\n");
+   return -ENODATA;
+   }
+
+   /* Data is right after the magic member of the tag_header struct */
+   ddr_info = (struct tag_ddr_mem *)(_h->magic + 1);
+   if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS) {
+   debug("Too many ATAG banks, got (%d) but max allowed (%d)\n",
+ 

[PATCH v4 00/11] rockchip: Support getting DRAM banks from TPL for rk3568 and rk3588

[Quentin Schulz]

x0004fdf882ff - 0x0004fdf88300 pattern 

[0.00]   0x0004fdf8832f - 0x0004fdf88330 pattern 

[0.00]   0x0004fdf8835f - 0x0004fdf88360 pattern 

[0.00]   0x0004fdf8838f - 0x0004fdf88390 pattern 

[0.00]   0x0004fdf883bf - 0x0004fdf883c0 pattern 

[0.00]   0x0004fdf883ef - 0x0004fdf883f0 pattern 

[0.00]   0x0004fdf8841c - 0x0004fdf88420 pattern 

[0.00]   0x0004fdf8844c - 0x0004fdf88450 pattern 

[0.00]   0x0004fdf8847c - 0x0004fdf88480 pattern 

[0.00]   0x0004fdf884ac - 0x0004fdf884b0 pattern 

[0.00]   0x0004fdf884dc - 0x0004fdf884e0 pattern 

[0.00]   0x0004fdf8850c - 0x0004fdf88510 pattern 

[0.00]   0x0004fdf8853c - 0x0004fdf88540 pattern 

[0.00]   0x0004fdf8856c - 0x0004fdf88570 pattern 

[0.00]   0x0004fdf8859c - 0x0004fdf885a0 pattern 

[0.00]   0x0004fdf885cd - 0x0004fdf885d0 pattern 

[0.00]   0x0004fdf885fd - 0x0004fdf88600 pattern 

[0.00]   0x0004fdf8862d - 0x0004fdf88630 pattern 

[0.00]   0x0004fdf8865d - 0x0004fdf88660 pattern 

[0.00]   0x0004fdf8868d - 0x0004fdf88690 pattern 


$ lsmem --output SIZE --bytes --json | jq '[.memory[].size] | add / 1024 / 1024 
/ 1024'
16
"""

I tested on Rock5B 16GB that without the memory holes and without using
this new logic, the kernel fails this memtest, so this test seems valid.

This has NOT been tested on RK356x as I don't own any.

Note that the logic for excluding DRAM memory areas from the memory
areas to consider for putting holes in DRAM banks based on mem_map
struct may conflict with SDRAM, ROM or flashes if we ever add those to
the SoC's mem_map... Something we can tackle the day we do it, it's good
enough for now.

Co-Developed-by: Chris Morgan 
Signed-off-by: Quentin Schulz 
---
Changes in v4:
- fix infinite while loop if there's no hole to create by incrementing
  the pointer in the no-match path,
- fix identification of non-DRAM memory areas in mem_map by checking for
  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE instead of
  looking for ! PTE_BLOCK_NON_SHARE since PTE_BLOCK_NON_SHARE is 0 so
  using it as a mask always makes the result the same value, regardless
  of the other operand,
- Link to v3: 
https://lore.kernel.org/r/20240415-rk35xx-dram-atags-v3-0-5bc5475b3...@theobroma-systems.com

Changes in v3:
- Split board migration to new DRAM ATAGS mechanism into separate
  commits,
- Use mem_map instead of hardcoded values for reserved memory area for
  MMIO,
- Add tag hash check to match Rockchip's downstream implementation,
- Bail from while loop as soon as a tag with no size is encountered to
  match Rockchip's downstream implementation,
- Use enum instead of constants for ATAG magic,
- Add debug messages and comments,
- Fix atags traversal by using tag size instead of checking every 16B,
- Migrate Jaguar to new mechanism,
- Default NR_DRAM_BANKS to 10 when ROCKCHIP_EXTERNAL_TPL is used so the
  default allows to use this new logic,
- Define tag_header data struct to parse the first two bytes of a tag
  more easily,
- Do not stop at CORE magic, directly look for DDR_MEM,
- Bail from while loop as soon as an unknown tag is used to match
  Rockchip's downstream implementation,
- Use phys_size_t and phys_addr_t wherever possible,

Link to v2: 
https://lore.kernel.org/u-boot/20240401181435.553351-1-macroalph...@gmail.com/
Link to v1: 
https://lore.kernel.org/u-boot/20240330050515.470025-1-macroalph...@gmail.com/

---
Quentin Schulz (11):
  rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
  rockchip: NR_DRAM_BANKS now defaults to 10 when Rockchip TPL blob is used
  rockchip: nanopc-t6-rk3588: use DRAM banks from ATAGS
  rockchip: quartzpro64-rk3588: use DRAM banks from ATAGS
  rockchip: rock5a-rk3588s: use DRAM banks from ATAGS
  rockchip: rock5b-rk3588: use DRAM banks from ATAGS
  rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS
  rockchip: toybrick_rk3588: use DRAM banks from ATAGS
  rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS
  rockchip: rk3588: use DRAM banks from ATAGS
  rockchip: rk356x: use DRAM banks from ATAGS

 arch/arm/mach-rockchip/Kconfig |   3 +
 arch/arm/mach-rockchip/sdram.c | 258 +
 board/friendlyelec/nanopc-t6-rk3588/Makefile   |   6 -
 .../nanopc-t6-rk3588/nanopc-t6-rk3588.c|  39 
 board/pine64/quartzpro64-rk3588/Mak

Re: [PATCH 2/2] armv8: generic_timer: Use event stream for udelay

[Quentin Schulz]

Hi Peter, Andre,

On 4/24/24 12:29, Andre Przywara wrote:

On Tue, 23 Apr 2024 12:55:55 +0200
Quentin Schulz  wrote:


Hi Peter,

On 4/23/24 10:10, Peter Hoyes wrote:

From: Peter Hoyes 

Polling cntpct_el0 in a tight loop for delays is inefficient.
This is particularly apparent on Arm FVPs, which do not simulate
real time, meaning that a 1s sleep can take a couple of orders
of magnitude longer to execute in wall time.

If running at EL2 or above (where CNTHCTL_EL2 is available), enable
the cntpct_el0 event stream temporarily and use wfe to implement
the delay more efficiently. The event period is chosen as a
trade-off between efficiency and the fact that Arm FVPs do not
typically simulate real time.

This is only implemented for Armv8 boards, where an architectural
timer exists.

Some mach-socfpga AArch64 boards already override __udelay to make
it always inline, so guard the functionality with a new
ARMV8_UDELAY_EVENT_STREAM Kconfig, enabled by default.

Signed-off-by: Peter Hoyes 
---
   arch/arm/cpu/armv8/Kconfig |  8 
   arch/arm/cpu/armv8/generic_timer.c | 27 +++
   arch/arm/include/asm/system.h  |  6 --
   3 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 9f0fb369f7..544c5e2d74 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -191,6 +191,14 @@ config ARMV8_EA_EL3_FIRST
  Exception handling at all exception levels for External Abort and
  SError interrupt exception are taken in EL3.
   
+config ARMV8_UDELAY_EVENT_STREAM

+   bool "Use the event stream for udelay"
+   default y if !ARCH_SOCFPGA
+   help
+ Use the event stream provided by the AArch64 architectural timer for
+ delays. This is more efficient than the default polling
+ implementation.
+
   menuconfig ARMV8_CRYPTO
bool "ARM64 Accelerated Cryptographic Algorithms"
   
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c

index 8f83372cbc..e18b5c8187 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -115,3 +115,30 @@ ulong timer_get_boot_us(void)
   
   	return val / get_tbclk();

   }
+
+#if CONFIG_IS_ENABLED(ARMV8_UDELAY_EVENT_STREAM)
+void __udelay(unsigned long usec)
+{
+   u64 target = get_ticks() + usec_to_tick(usec);
+


This can theoretically overflow, do we have any guarantee this cannot
happen in real life, like... we would need U-Boot to be running for 100
years without being powered-down/reset or something like that? Can we
document this assumption? Does this make sense?


The Arm ARM guarantees a "Roll-over time of not less than 40 years."
(Armv8 ARM 0487K.a D12.1.2 "The system counter").
So that's not the 100 years you are asking for, but I guess still good
enough?



I guess it is, since it is also stored in a u64 and is reset to 0 upon 
start-up according to the ARM. I also assume nobody is going to add a 
udelay of years in their code :) (and if they do, they would probably 
figure out something's wrong before it reaches the final products :) ).


Thanks all for the pointers to reference manuals and current 
implementations.


Cheers,
Quentin

Re: [PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588

[Quentin Schulz]

Hi Jonas,

On 4/24/24 00:40, Jonas Karlman wrote:

Hi Quentin,

On 2024-04-15 16:16, Quentin Schulz wrote:

From: Quentin Schulz 

[...]


+   if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {


This check does not seem to work because PTE_BLOCK_NON_SHARE evaluates
to 0. Because of this the logic to split the 0-8 GiB bank reported on
rk3568 is never split in two.



Oof, that's a bit oversight, thanks for the catch.

Can you test the following please?

"""
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 5b1ff1e5495..0492f9b9f41 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -196,7 +196,23 @@ static int rockchip_dram_init_banksize(void)
const phys_size_t rsrv_size = tmp_mem_map->size;
const phys_addr_t rsrv_end = rsrv_start + rsrv_size;

-   if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {
+   /*
+* DRAM memories are expected by Arm to be marked as
+* Normal Write-back cacheable, Inner shareable[1], so
+* let's filter on that to put holes in non-DRAM areas.
+*
+			 * [1] 
https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes

+*/
+   const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE;
+   /*
+* (AttrIndx | SH) in Lower Attributes of Block
+* Descriptor[2].
+			 * [2] 
https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64

+*/
+   const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9, 
8);
+
+   if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
tmp_mem_map++;
continue;
}
"""

The DRAM mem_map entry for Rockchip devices seems to have those 
attributes and no other non-DRAM entry seems to have 
PTE_BLOCK_MEMTYPE(MT_NORMAL).


We may have an issue in the future if we also want to mark SRAM, ROM or 
flash 
(https://developer.arm.com/documentation/102376/0200/Normal-memory) 
because it's likely those would also match the same attributes but we 
would need to put holes for those so that they aren't thought to be 
DRAM, but I guess we can tackle this the day this happens :)


Thanks again for the catch, let me know if this helps and makes sense 
and I'll send a v4 for it.


Cheers,
Quentin

Re: [PATCH 2/2] armv8: generic_timer: Use event stream for udelay

[Quentin Schulz]

Hi Peter,

On 4/23/24 10:10, Peter Hoyes wrote:

From: Peter Hoyes 

Polling cntpct_el0 in a tight loop for delays is inefficient.
This is particularly apparent on Arm FVPs, which do not simulate
real time, meaning that a 1s sleep can take a couple of orders
of magnitude longer to execute in wall time.

If running at EL2 or above (where CNTHCTL_EL2 is available), enable
the cntpct_el0 event stream temporarily and use wfe to implement
the delay more efficiently. The event period is chosen as a
trade-off between efficiency and the fact that Arm FVPs do not
typically simulate real time.

This is only implemented for Armv8 boards, where an architectural
timer exists.

Some mach-socfpga AArch64 boards already override __udelay to make
it always inline, so guard the functionality with a new
ARMV8_UDELAY_EVENT_STREAM Kconfig, enabled by default.

Signed-off-by: Peter Hoyes 
---
  arch/arm/cpu/armv8/Kconfig |  8 
  arch/arm/cpu/armv8/generic_timer.c | 27 +++
  arch/arm/include/asm/system.h  |  6 --
  3 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 9f0fb369f7..544c5e2d74 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -191,6 +191,14 @@ config ARMV8_EA_EL3_FIRST
  Exception handling at all exception levels for External Abort and
  SError interrupt exception are taken in EL3.
  
+config ARMV8_UDELAY_EVENT_STREAM

+   bool "Use the event stream for udelay"
+   default y if !ARCH_SOCFPGA
+   help
+ Use the event stream provided by the AArch64 architectural timer for
+ delays. This is more efficient than the default polling
+ implementation.
+
  menuconfig ARMV8_CRYPTO
bool "ARM64 Accelerated Cryptographic Algorithms"
  
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c

index 8f83372cbc..e18b5c8187 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -115,3 +115,30 @@ ulong timer_get_boot_us(void)
  
  	return val / get_tbclk();

  }
+
+#if CONFIG_IS_ENABLED(ARMV8_UDELAY_EVENT_STREAM)
+void __udelay(unsigned long usec)
+{
+   u64 target = get_ticks() + usec_to_tick(usec);
+


This can theoretically overflow, do we have any guarantee this cannot 
happen in real life, like... we would need U-Boot to be running for 100 
years without being powered-down/reset or something like that? Can we 
document this assumption? Does this make sense?



+   /* At EL2 or above, use the event stream to avoid polling CNTPCT_EL0 so 
often */
+   if (current_el() >= 2) {
+   u32 cnthctl_val;
+   const u8 event_period = 0x7;
+
+   asm volatile("mrs %0, cnthctl_el2" : "=r" (cnthctl_val));
+   asm volatile("msr cnthctl_el2, %0" : : "r"
+   (cnthctl_val | CNTHCTL_EL2_EVNT_EN | 
CNTHCTL_EL2_EVNT_I(event_period)));
+
+   while (get_ticks() + (1ULL << event_period) <= target)


This could be an overflow as well.


+   wfe();
+
+   /* Reset the event stream */
+   asm volatile("msr cnthctl_el2, %0" : : "r" (cnthctl_val));
+   }
+
+   /* Fall back to polling CNTPCT_EL0 */
+   while (get_ticks() <= target)


get_ticks() could wrap around here maybe?

Cheers,
Quentin

[PATCH v2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module

[Quentin Schulz]

From: Quentin Schulz 

The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3588.

It provides the following feature set:
 * up to 16GB LPDDR4x
 * on-module eMMC
 * SD card (on a baseboard) via edge connector
 * Gigabit Ethernet with on-module GbE PHY
 * HDMI/eDP
 * MIPI-DSI
 * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
 * HDMI input over FPC connector
 * CAN
 * USB
   - 1x USB 3.0 dual-role (direct connection)
   - 2x USB 3.0 host + 1x USB 2.0 host
 * PCIe
   - 1x PCIe 2.1 Gen3, 4 lanes
   - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
 * on-module ATtiny816 companion controller, implementing:
   - low-power RTC functionality (ISL1208 emulation)
   - fan controller (AMC6821 emulation)
  * on-module Secure Element with Global Platform 2.2.1 compliant
JavaCard environment

The support is added for Tiger on Haikou devkit, similarly to RK3399
Puma and PX30 Ringneck.

The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4.

Cc: Quentin Schulz 
Signed-off-by: Quentin Schulz 
---
This has a light dependency on
https://lore.kernel.org/u-boot/20240415-rk35xx-dram-atags-v3-0-5bc5475b3...@theobroma-systems.com/
(the Tiger defconfig can be updated to remove the dependency if required)

To: Tom Rini 
To: Klaus Goger 
To: Heiko Stuebner 
To: Simon Glass 
To: Philipp Tomsich 
To: Kever Yang 
Cc: u-boot@lists.denx.de
Signed-off-by: Quentin Schulz 

Changes in v2:
- removed uart controller muxing patch as not necessary until we get
  open-source DRAM init,
- disabled DEBUG_UART_BOARD_INIT as it's only used for muxing the UART
  controller and it's not necessary since DDR bin does this for us
  already,
- added missing uart2 mux bootph in U-Boot dtsi (though not required
  yet),
- switched to USB_DWC3_GENERIC from USB_XHCI_DWC3 as requested by Jonas,
- Link to v1: 
https://lore.kernel.org/r/20240422-tiger-v1-0-8816b070d...@theobroma-systems.com
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi   |  59 ++
 arch/arm/dts/rk3588-tiger-haikou.dts   | 266 
 arch/arm/dts/rk3588-tiger.dtsi | 690 +
 arch/arm/mach-rockchip/rk3588/Kconfig  |  31 +
 board/theobroma-systems/tiger_rk3588/Kconfig   |  16 +
 board/theobroma-systems/tiger_rk3588/MAINTAINERS   |  13 +
 board/theobroma-systems/tiger_rk3588/Makefile  |  10 +
 .../theobroma-systems/tiger_rk3588/tiger_rk3588.c  |  53 ++
 configs/tiger-rk3588_defconfig | 114 
 doc/board/rockchip/rockchip.rst|   1 +
 doc/board/theobroma-systems/index.rst  |   1 +
 doc/board/theobroma-systems/tiger_rk3588.rst   | 102 +++
 include/configs/tiger_rk3588.h |  15 +
 14 files changed, 1372 insertions(+)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..ef901642a0a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,6 +180,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb \
+   rk3588-tiger-haikou.dtb \
rk3588-turing-rk1.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RV1108) += \
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi 
b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 000..bfcefe256b0
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", , 
+   };
+};
+
+_pwrseq {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+_reset {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+ {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+ {
+   /* U-Boot currently cannot handle anything below HS200 for eMMC on 
RK3588 */
+   /delete-property/ mmc-ddr-1_8v;
+   /delete-property/ cap-mmc-highspeed;
+};
+
+/* Q7 USB P0 */
+ {
+   status = "okay";
+};
+
+_otg {
+   status = "okay";
+};
+
+_xfer {
+   bootph-all;
+};
+
+/* Q7 USB P0 */
+_phy1 {
+   status = "okay";
+};
+
+_phy1_u3 {
+   status = "okay";
+};
+
+_host1_xhci {
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-tiger-haikou.dts 
b/arch/arm/dts/rk3588-tiger-haikou.dts
new file mode 100644
index 000..d672198c6b6
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include 
+#include "rk3588-tiger.dtsi"
+
+/ {
+   model = "Theobroma Systems RK3588-Q7 SoM on Haikou devkit";
+   compati

Re: [PATCH 2/2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module

[Quentin Schulz]

Hi Jonas,

On 4/22/24 19:54, Jonas Karlman wrote:

Hi Quentin,

On 2024-04-22 18:41, Quentin Schulz wrote:

From: Quentin Schulz 

[...]

diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi 
b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 000..4259399193a
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi

[...]


Following should be added to possible fix uart2 pinctrl in SPL:

   _xfer {
bootph-all;
   };



Would only be useful once we get rid of DDR bin, but will do it now 
because I have a feeling I would forget otherwise :)


Thanks for catching this though.

[...]


[snip]


diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig
new file mode 100644
index 000..6545445bba1
--- /dev/null
+++ b/configs/tiger-rk3588_defconfig

[...]

+CONFIG_USB_XHCI_DWC3=y


Please use USB_DWC3_GENERIC instead of USB_XHCI_DWC3.



Dang, I thought I was using "the correct one".

It's very difficult to know which one to pick right now, would it be 
possible to update the help message to guide the users a bit more in 
their choice? I don't really have a clue why one is "better" than the 
other so wouldn't be able to suggest something.


Cheers,
Quentin

Re: [PATCH 1/2] rockchip: rk3588: add support for UART2 M1 and M2 in SPL

[Quentin Schulz]

Hi Kever,

On 4/23/24 03:09, Kever Yang wrote:

Hi Quentin,

On 2024/4/23 00:41, Quentin Schulz wrote:

From: Quentin Schulz 

UART2 controller is the controller in the reference design for debug
console. The default mux is M0 in that reference design. Until now, all
boards seemed to be using UART2M0 but RK3588 Tiger for example will be
using UART2M2 instead.

This feature already been supported, please use CONFIG_DEBUG_UART_BASE and
CONFIG_ROCKCHIP_UART_MUX_SEL_M to select your output channel.



CONFIG_ROCKCHIP_UART_MUX_SEL_M is only available in Rockchip's 
downstream U-Boot.


git log -p -S ROCKCHIP_UART_MUX_SEL_M

returns nothing upstream, neither does git grep.

I used the same mechanism as for PX30.

This patch will be removed though as it's not needed until we have an 
open-source DRAM init. Until then we have to rely on the DDR bin to 
setup the UART.


Cheers,
Quentin

Re: [PATCH 1/2] rockchip: rk3588: add support for UART2 M1 and M2 in SPL

[Quentin Schulz]

Hi Jonas,

On 4/22/24 19:41, Jonas Karlman wrote:

Hi Quentin,

On 2024-04-22 18:41, Quentin Schulz wrote:

From: Quentin Schulz 

UART2 controller is the controller in the reference design for debug
console. The default mux is M0 in that reference design. Until now, all
boards seemed to be using UART2M0 but RK3588 Tiger for example will be
using UART2M2 instead.

Therefore, let's add support for UART2M1 and M2 as possible muxes for
the UART2 controller used as debug console. UART2M1 support was not
tested.

The default value is M0 to match the one used currently by all devices
and the reference design.


Is this really necessary?

Use of board_debug_uart_init() should typically only be needed in TPL on
Rockchip platform, and with ROCKCHIP_TPL being used it should be enough
to use rkbin/ddrbin_tool to change uart config and just ensure correct
pinctrl is used for uart node, and that the uart node is included in SPL
for correct serial console use.



ddrbin_tool is a blob that Rockchip refuses to provide sources of. 
Running a blob on the target is one thing, requiring our users to run a 
blob on their build machine is another thing (though I document it in 
the rST).


However... I don't think we have another way around because I just 
remembered that if you have two muxes selected for the same UART 
controller, RX won't work. So while we would have UART output for U-Boot 
if Rockchip's TPL is one mux (e.g. m0, the default) and upstream U-Boot 
another one, we wouldn't be able to interact with it.


It'll be necessary the day we have an open-source DRAM init though (I 
had to do this for PX30 for example).


The issue is that since ddrbin_tool is a blob, it's not possible to use 
it in Yocto for automatically generating the appropriate ddr bin blob 
based on uart controller, mux and baudrate. So that will be my cross to 
bear.



May I suggest you try adding following to defconfig and drop this patch?

   # CONFIG_DEBUG_UART_BOARD_INIT is not set

I would expect that should result in same/working behavior without
having to add any new code.



It does work, thanks for the suggestion, will send a v2.

Cheers,
Quentin

[PATCH 2/2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module

[Quentin Schulz]

From: Quentin Schulz 

The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3588.

It provides the following feature set:
 * up to 16GB LPDDR4x
 * on-module eMMC
 * SD card (on a baseboard) via edge connector
 * Gigabit Ethernet with on-module GbE PHY
 * HDMI/eDP
 * MIPI-DSI
 * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
 * HDMI input over FPC connector
 * CAN
 * USB
   - 1x USB 3.0 dual-role (direct connection)
   - 2x USB 3.0 host + 1x USB 2.0 host
 * PCIe
   - 1x PCIe 2.1 Gen3, 4 lanes
   - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
 * on-module ATtiny816 companion controller, implementing:
   - low-power RTC functionality (ISL1208 emulation)
   - fan controller (AMC6821 emulation)
  * on-module Secure Element with Global Platform 2.2.1 compliant
JavaCard environment

The support is added for Tiger on Haikou devkit, similarly to RK3399
Puma and PX30 Ringneck.

The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4.

Cc: Quentin Schulz 
Signed-off-by: Quentin Schulz 
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi   |  54 ++
 arch/arm/dts/rk3588-tiger-haikou.dts   | 266 
 arch/arm/dts/rk3588-tiger.dtsi | 690 +
 arch/arm/mach-rockchip/rk3588/Kconfig  |  31 +
 board/theobroma-systems/tiger_rk3588/Kconfig   |  16 +
 board/theobroma-systems/tiger_rk3588/MAINTAINERS   |  13 +
 board/theobroma-systems/tiger_rk3588/Makefile  |  10 +
 .../theobroma-systems/tiger_rk3588/tiger_rk3588.c  |  53 ++
 configs/tiger-rk3588_defconfig | 114 
 doc/board/rockchip/rockchip.rst|   1 +
 doc/board/theobroma-systems/index.rst  |   1 +
 doc/board/theobroma-systems/tiger_rk3588.rst   | 102 +++
 include/configs/tiger_rk3588.h |  15 +
 14 files changed, 1367 insertions(+)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..ef901642a0a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,6 +180,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb \
+   rk3588-tiger-haikou.dtb \
rk3588-turing-rk1.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RV1108) += \
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi 
b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 000..4259399193a
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", , 
+   };
+};
+
+_pwrseq {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+_reset {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+ {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+ {
+   /* U-Boot currently cannot handle anything below HS200 for eMMC on 
RK3588 */
+   /delete-property/ mmc-ddr-1_8v;
+   /delete-property/ cap-mmc-highspeed;
+};
+
+/* Q7 USB P0 */
+ {
+   status = "okay";
+};
+
+_otg {
+   status = "okay";
+};
+
+_phy1 {
+   status = "okay";
+};
+
+_phy1_u3 {
+   status = "okay";
+};
+
+_host1_xhci {
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-tiger-haikou.dts 
b/arch/arm/dts/rk3588-tiger-haikou.dts
new file mode 100644
index 000..d672198c6b6
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include 
+#include "rk3588-tiger.dtsi"
+
+/ {
+   model = "Theobroma Systems RK3588-Q7 SoM on Haikou devkit";
+   compatible = "tsd,rk3588-tiger-haikou", "tsd,rk3588-tiger", 
"rockchip,rk3588";
+
+   aliases {
+   ethernet0 = 
+   mmc1 = 
+   };
+
+   chosen {
+   stdout-path = "serial2:115200n8";
+   };
+
+   dc_12v: dc-12v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "dc_12v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   pinctrl-names = "default";
+   pinctrl-0 = <_keys_pin>;
+
+   button-batlow-n {
+   label = "BATLOW#";
+   linux,code

[PATCH 1/2] rockchip: rk3588: add support for UART2 M1 and M2 in SPL

[Quentin Schulz]

From: Quentin Schulz 

UART2 controller is the controller in the reference design for debug
console. The default mux is M0 in that reference design. Until now, all
boards seemed to be using UART2M0 but RK3588 Tiger for example will be
using UART2M2 instead.

Therefore, let's add support for UART2M1 and M2 as possible muxes for
the UART2 controller used as debug console. UART2M1 support was not
tested.

The default value is M0 to match the one used currently by all devices
and the reference design.

Cc: Quentin Schulz 
Signed-off-by: Quentin Schulz 
---
 arch/arm/mach-rockchip/rk3588/Kconfig  | 10 ++
 arch/arm/mach-rockchip/rk3588/rk3588.c | 36 ++
 2 files changed, 46 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig 
b/arch/arm/mach-rockchip/rk3588/Kconfig
index d7e4af31f24..cacdb0459c9 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -221,6 +221,16 @@ config ROCKCHIP_COMMON_STACK_ADDR
 config TEXT_BASE
default 0x00a0
 
+config DEBUG_UART_CHANNEL
+   int "Mux channel to use for debug UART2"
+   depends on DEBUG_UART_BOARD_INIT
+   default 0
+   range 0 2
+   help
+ UART2 can use three different set of pins to route the output.
+ For using the UART for early debugging the route to use needs
+ to be declared (0, 1 or 2).
+
 source board/edgeble/neural-compute-module-6/Kconfig
 source board/friendlyelec/nanopc-t6-rk3588/Kconfig
 source board/pine64/quartzpro64-rk3588/Kconfig
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c 
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index eb65dafe3a2..e330ad6a697 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -94,9 +94,32 @@ enum {
GPIO0B6_UART2_RX_M0 = 10,
 };
 
+/* GPIO3B_IOMUX_SEL_L */
+enum {
+   GPIO3B1_SHIFT   = 4,
+   GPIO3B1_MASK= GENMASK(7, 4),
+   GPIO3B1_UART2_TX_M2 = 10,
+
+   GPIO3B2_SHIFT   = 8,
+   GPIO3B2_MASK= GENMASK(11, 8),
+   GPIO3B2_UART2_RX_M2 = 10,
+};
+
+/* GPIO4D_IOMUX_SEL_L */
+enum {
+   GPIO4D0_SHIFT   = 0,
+   GPIO4D0_MASK= GENMASK(3, 0),
+   GPIO4D0_UART2_TX_M1 = 10,
+
+   GPIO4D1_SHIFT   = 4,
+   GPIO4D1_MASK= GENMASK(7, 4),
+   GPIO4D1_UART2_RX_M1 = 10,
+};
+
 void board_debug_uart_init(void)
 {
__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void 
*)BUS_IOC_BASE;
+#if (CONFIG_DEBUG_UART_CHANNEL == 0)
static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
 
/* Refer to BUS_IOC */
@@ -110,6 +133,19 @@ void board_debug_uart_init(void)
 GPIO0B6_MASK | GPIO0B5_MASK,
 GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
 GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
+#elif (CONFIG_DEBUG_UART_CHANNEL == 1)
+   /* UART2_M1 Switch iomux */
+   rk_clrsetreg(_ioc->gpio4d_iomux_sel_l,
+GPIO4D0_MASK | GPIO4D1_MASK,
+GPIO4D0_UART2_TX_M1 << GPIO4D0_UART2_TX_M1 |
+GPIO4D1_UART2_RX_M1 << GPIO4D1_SHIFT);
+#else
+   /* UART2_M2 Switch iomux */
+   rk_clrsetreg(_ioc->gpio3b_iomux_sel_l,
+GPIO3B1_MASK | GPIO3B2_MASK,
+GPIO3B1_UART2_TX_M2 << GPIO3B1_SHIFT |
+GPIO3B2_UART2_RX_M2 << GPIO3B2_SHIFT);
+#endif /* CONFIG_DEBUG_UART_CHANNEL */
 }
 
 #ifdef CONFIG_SPL_BUILD

-- 
2.44.0

[PATCH 0/2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module

[Quentin Schulz]

The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3588.

It provides the following feature set:
 * up to 16GB LPDDR4x
 * on-module eMMC
 * SD card (on a baseboard) via edge connector
 * Gigabit Ethernet with on-module GbE PHY
 * HDMI/eDP
 * MIPI-DSI
 * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
 * HDMI input over FPC connector
 * CAN
 * USB
   - 1x USB 3.0 dual-role (direct connection)
   - 2x USB 3.0 host + 1x USB 2.0 host
 * PCIe
   - 1x PCIe 2.1 Gen3, 4 lanes
   - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
 * on-module ATtiny816 companion controller, implementing:
   - low-power RTC functionality (ISL1208 emulation)
   - fan controller (AMC6821 emulation)
  * on-module Secure Element with Global Platform 2.2.1 compliant
JavaCard environment

The support is added for Tiger on Haikou devkit, similarly to RK3399
Puma and PX30 Ringneck.

The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4.

Because Tiger doesn't use the same mux for the debug console as all
other RK3588 devices currently supported in U-Boot, an additional patch
is required to be able to interact with the device properly.

This has a light dependency on
https://lore.kernel.org/u-boot/20240415-rk35xx-dram-atags-v3-0-5bc5475b3...@theobroma-systems.com/
(the Tiger defconfig can be updated to remove the dependency if required)

Signed-off-by: Quentin Schulz 
---
Quentin Schulz (2):
  rockchip: rk3588: add support for UART2 M1 and M2 in SPL
  rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi   |  54 ++
 arch/arm/dts/rk3588-tiger-haikou.dts   | 266 
 arch/arm/dts/rk3588-tiger.dtsi | 690 +
 arch/arm/mach-rockchip/rk3588/Kconfig  |  41 ++
 arch/arm/mach-rockchip/rk3588/rk3588.c |  36 ++
 board/theobroma-systems/tiger_rk3588/Kconfig   |  16 +
 board/theobroma-systems/tiger_rk3588/MAINTAINERS   |  13 +
 board/theobroma-systems/tiger_rk3588/Makefile  |  10 +
 .../theobroma-systems/tiger_rk3588/tiger_rk3588.c  |  53 ++
 configs/tiger-rk3588_defconfig | 114 
 doc/board/rockchip/rockchip.rst|   1 +
 doc/board/theobroma-systems/index.rst  |   1 +
 doc/board/theobroma-systems/tiger_rk3588.rst   | 102 +++
 include/configs/tiger_rk3588.h |  15 +
 15 files changed, 1413 insertions(+)
---
base-commit: 5fb840ed8339cae3915ea1528a4bfa3e587540e6
change-id: 20240418-tiger-d1531308c9a0

Best regards,
-- 
Quentin Schulz 

Re: [PATCH 1/1] Makefile: don't add -Wno-maybe-uninitialized twice

[Quentin Schulz]

Hi Heinrich,

On 4/16/24 09:35, Heinrich Schuchardt wrote:

Avoid adding the same flag to KBUILD_CFLAGS twice.

Fixes: 8602d97ca2cf ("Makefile: avoid false positive -Wmaybe-uninitialized")
Signed-off-by: Heinrich Schuchardt 


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH] ram: rockchip: px30: Replace misleading log message

[Quentin Schulz]

BTW,

On 4/17/24 13:16, lukasz.czechow...@thaumatec.com wrote:

From: Lukasz Czechowski 



There is a typo in your mail address. I assume your git config 
user.email may be wrong, because your signed-off-by is correct.


Cheers,
Quentin

Re: [PATCH] ram: rockchip: px30: Replace misleading log message

[Quentin Schulz]

Hi Lukasz,

On 4/17/24 13:16, lukasz.czechow...@thaumatec.com wrote:

From: Lukasz Czechowski 

Remove the log message "out" from sdram_init function which
pollutes the console. It brings no meaningful information and
might be unwanted in case silencing the console is required.
Instead, add a debug log with a more meaningful message, printed
only if DEBUG is set. The same convention is used for other
boards, i.e. rk3399.

Signed-off-by: Lukasz Czechowski 
---
  drivers/ram/rockchip/sdram_px30.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/rockchip/sdram_px30.c 
b/drivers/ram/rockchip/sdram_px30.c
index 21498e8957..3b429973cd 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -712,7 +712,7 @@ int sdram_init(void)
  
  	sdram_print_ddr_info(_params->ch.cap_info, _params->base, 0);
  
-	printascii("out\n");

+   debug("Finish SDRAM initialization...\n");


Mmmm I don't think this is appropriate. debug() is essentially replaced 
with printf() whenever the selected log level permits. The issue is that 
printf() != printascii() and I have a feeling we use printascii 
explicitly because it is a much smaller way to print data than printf.


Additionally, we're extremely size constrained in TPL on PX30, so 
increasing the string size to print may also not be wise. If we are not 
enable to even build the TPL by defining DEBUG, this is basically dead 
code and it's as good to us as removing it entirely.


So... questions:
1) does it actually build if you set #define DEBUG 1 or whatever is 
needed for having the debug message printed? If yes, does it boot?
2) What's the size of the TPL with this change and with this 
change+DEBUG set?


What I can suggest instead is to guard all printascii (or at least the 
ones only useful for debugging) with the appropriate symbol, e.g. could 
be CONFIG_RAM_ROCKCHIP_DEBUG.


I have not tested it (only build tested on Ringneck PX30 without 
CONFIG_RAM_ROCKCHIP_DEBUG nor CONFIG_TPL_SERIAL), but here's a quick 
attempt:


"""
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index b7a6f100d41..17656e99a2f 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,7 +11,7 @@ config ROCKCHIP_PX30
select TPL_NEEDS_SEPARATE_STACK if TPL
imply SPL_SEPARATE_BSS
select SPL_SERIAL
-   select TPL_SERIAL
+   imply TPL_SERIAL
select DEBUG_UART_BOARD_INIT
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c 
b/arch/arm/mach-rockchip/px30-board-tpl.c

index 637a5e1b18b..8f56147ca7a 100644
--- a/arch/arm/mach-rockchip/px30-board-tpl.c
+++ b/arch/arm/mach-rockchip/px30-board-tpl.c
@@ -36,7 +36,7 @@ void board_init_f(ulong dummy)
 {
int ret;

-#ifdef CONFIG_DEBUG_UART
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
debug_uart_init();
/*
 * Debug UART can be used from here if required:
@@ -51,8 +51,10 @@ void board_init_f(ulong dummy)

secure_timer_init();
ret = sdram_init();
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
if (ret)
printascii("sdram_init failed\n");
+#endif

/* return to maskrom */
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index 67c63ecba04..cb59bcf0414 100644
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -16,6 +16,8 @@ if RAM_ROCKCHIP
 config RAM_ROCKCHIP_DEBUG
bool "Rockchip ram drivers debugging"
default y
+   depends on TPL_SERIAL if TPL_RAM
+   depends on SPL_SERIAL if SPL_RAM
help
  This enables debugging ram driver API's for the platforms
  based on Rockchip SoCs.
diff --git a/drivers/ram/rockchip/sdram_common.c 
b/drivers/ram/rockchip/sdram_common.c

index 60fc90d0a5c..8076cfa9aad 100644
--- a/drivers/ram/rockchip/sdram_common.c
+++ b/drivers/ram/rockchip/sdram_common.c
@@ -231,7 +231,9 @@ int sdram_detect_col(struct sdram_cap_info *cap_info,
break;
}
if (col == 8) {
+#ifdef CONFIG_RAM_ROCKCHIP_DEBUG
printascii("col error\n");
+#endif
return -1;
}

@@ -348,7 +350,9 @@ int sdram_detect_row(struct sdram_cap_info *cap_info,
break;
}
if (row == 12) {
+#ifdef CONFIG_RAM_ROCKCHIP_DEBUG
printascii("row error");
+#endif
return -1;
}

diff --git a/drivers/ram/rockchip/sdram_px30.c 
b/drivers/ram/rockchip/sdram_px30.c

index 21498e89570..607d97c268e 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -231,8 +231,10 @@ static unsigned int calculate_ddrconfig(struct 
px30_sdram_params *sdram_params)

ddrconf = i;
break;
  

Re: [PATCH v3] rockchip: px30-board-tpl: Sync ifdef guards with full TPL

[Quentin Schulz]

Hi Lukasz,

On 4/17/24 13:21, lukasz.czechow...@thaumatec.com wrote:

From: Lukasz Czechowski 

Display TPL init information message only when TPL_BANNER_PRINT
configuration entry is set. This allows to disable information
message in case logs on UART are unwanted.
Update parent ifdef condition to check also CONFIG_TPL_SERIAL
to match logic of the non-PX30 TPL implementation.

Signed-off-by: Lukasz Czechowski 



When someone gives a tag (Acked-by, Reviewed-by, Tested-by, ...) on a 
version and you send a new one, it's best to include this in the commit 
log now (above your Signed-off-by if I remember correctly) if and only 
if the content only changed a bit (like no big logic change or rewrite). 
So here, my Reviewed-by would have been nice since I gave it in the v2 
:) (please do not send a v4 for this :) )


b4 does this with `b4 trailers -u` automatically by the way :)

Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH v2] rockchip: px30-board-tpl: Use CONFIG_TPL_BANNER_PRINT flag

[Quentin Schulz]

Hi Lukasz,

I would have renamed the commit title to be something like

rockchip: px30-board-tpl: sync ifdef guards with full TPL

because CONFIG_TPL_BANNER_PRINT isn't really a flag but a Kconfig symbol 
and the effect of this patch is to not print the banner when the symbol 
is not selected.


Another option could have been (only for the v1, since you do more now):

rockchip: px30-board-tpl: print banner only if CONFIG_TPL_BANNER_PRINT

On 4/17/24 11:35, lukasz.czechow...@thaumatec.com wrote:

From: Lukasz Czechowski 

Display TPL init information message only when TPL_BANNER_PRINT
configuration entry is set. This allows to disable information
message in case logs on UART are unwanted.
Update parent ifdef condition to check also CONFIG_TPL_SERIAL
to match logic of the non-PX30 TPL implementation.

Signed-off-by: Lukasz Czechowski 
Cc: Tom Rini 
Cc: Simon Glass 
Cc: Philipp Tomsich 
Cc: Kever Yang 



Small nitpick, the Cc would make it to the git history, which isn't 
really necessary. I believe you could have those below the --- and 
git-send-email still find them.


Additionally, git send-email allows you to provide --cc and --to manually.


---
Changes for v2:
- Updated parent ifdef condition
---
  arch/arm/mach-rockchip/px30-board-tpl.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c 
b/arch/arm/mach-rockchip/px30-board-tpl.c
index 637a5e1b18..db368a7b8c 100644
--- a/arch/arm/mach-rockchip/px30-board-tpl.c
+++ b/arch/arm/mach-rockchip/px30-board-tpl.c
@@ -36,7 +36,7 @@ void board_init_f(ulong dummy)
  {
int ret;
  
-#ifdef CONFIG_DEBUG_UART

+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)


Quite interestingly, CONFIG_TPL_SERIAL cannot be disabled on PX30, maybe 
we should change arch/arm/mach-rockchip/Kconfig to use an `imply` 
instead of `select`.


Anyway, no change required on my side. Only, if there's a v3 (for the Cc 
and commit title, the Kconfig change would be a separate patch anyway).


Reviewed-by: Quentin Schulz 

Thanks,
Quentin

Re: [PATCH] rockchip: px30-board-tpl: Use CONFIG_TPL_BANNER_PRINT flag

[Quentin Schulz]

Hi Lukasz,

Please use scripts/get_maintainer.pl to set the Cc and To recipients of 
your mail to make sure it reaches the appropriate people explicitly.


$ scripts/get_maintainer.pl arch/arm/mach-rockchip/px30-board-tpl.c
Tom Rini  (maintainer:ARM)
Simon Glass  (maintainer:ARM ROCKCHIP)
Philipp Tomsich  (maintainer:ARM ROCKCHIP)
Kever Yang  (maintainer:ARM ROCKCHIP)
u-boot@lists.denx.de (open list)

(one can use scripts/get_maintainer.pl on patches instead of files, and 
it'll return whatever is needed).


Plugging `b4` here as well, because it's a pretty nice tool to use:
https://git.kernel.org/pub/scm/utils/b4/b4.git/ One can install it with 
pip. I use it for Linux kernel and U-Boot contributions for a couple of 
years now and I'm not going back to manual workflow :)


b4 prep --auto-to-cc would set everything up properly for you.

On 4/16/24 14:47, Lukasz Czechowski wrote:

Display TPL init information message only when TPL_BANNER_PRINT
configuration entry is set. This allows to disable information
message in case logs on UART are unwanted.

Signed-off-by: Lukasz Czechowski 


This matches Rockchip's non-PX30 TPL, so:

Reviewed-by: Quentin Schulz 


---
  arch/arm/mach-rockchip/px30-board-tpl.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c 
b/arch/arm/mach-rockchip/px30-board-tpl.c
index 637a5e1b18..a660816db0 100644
--- a/arch/arm/mach-rockchip/px30-board-tpl.c
+++ b/arch/arm/mach-rockchip/px30-board-tpl.c
@@ -46,7 +46,9 @@ void board_init_f(ulong dummy)
 * printhex8(0x1234);
 * printascii("string");
 */
+#if CONFIG_TPL_BANNER_PRINT
printascii("U-Boot TPL board init\n");
+#endif


I'm wondering if we shouldn't have the parent ifdef also match the logic 
of the non-PX30 TPL?


#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)

instead of

#if defined(CONFIG_DEBUG_UART)

?

Thanks,
Quentin