Re: [U-Boot] [PATCH 2/2] include:configs: Add usb device-tree fixup for all fsl platforms
> -Original Message- > From: Ramneek Mehresh > Sent: Thursday, January 28, 2016 5:45 PM > To: 'Marek Vasut' <ma...@denx.de> > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > b...@lists.denx.de; Simon Glass <s...@chromium.org> > Subject: RE: [PATCH 2/2] include:configs: Add usb device-tree fixup for all > fsl > platforms > > > > > -Original Message- > > From: Marek Vasut [mailto:ma...@denx.de] > > Sent: Thursday, January 28, 2016 5:04 PM > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup > > for all fsl platforms > > > > On Thursday, January 28, 2016 at 12:05:29 PM, Ramneek Mehresh wrote: > > > > -----Original Message- > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > Sent: Wednesday, January 27, 2016 5:13 PM > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree > > > > fixup for all fsl platforms > > > > > > > > On Wednesday, January 27, 2016 at 12:33:04 PM, Ramneek Mehresh > > wrote: > > > > > > -Original Message- > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > Sent: Wednesday, January 27, 2016 1:57 PM > > > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree > > > > > > fixup for all fsl platforms > > > > > > > > > > > > On Wednesday, January 27, 2016 at 09:26:08 AM, Ramneek > Mehresh > > > > > > > > wrote: > > > > > > > > -Original Message- > > > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > > > Sent: Wednesday, January 27, 2016 1:05 PM > > > > > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > > > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > > > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb > > > > > > > > device-tree fixup for all fsl platforms > > > > > > > > > > > > > > > > On Wednesday, January 27, 2016 at 05:30:51 AM, Ramneek > > > > > > > > Mehresh > > > > > > > > > > > > wrote: > > > > > > > > > > -Original Message----- > > > > > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > > > > > Sent: Wednesday, January 27, 2016 9:57 AM > > > > > > > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > > > > > > > Cc: Ramneek Mehresh > <ramneek.mehr...@freescale.com>; > > u- > > > > > > > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb > > > > > > > > > > device-tree fixup for all fsl platforms > > > > > > > > > > > > > > > > > > > > On Wednesday, January 27, 2016 at 05:14:00 AM, Ramneek > > > > > > > > Mehresh > > > > > > > > > > > > wrote: > > > > > > > > > > > > -Original Message- > > > > > > > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > > > > > > > Sent: Tuesday, January 26, 2016 4:58 PM > > > > > > > > > > > > To: Ramneek Mehresh > > <ramneek.mehr...@freescale.com> > > > > > > > > > > > > Cc: u-boot@lists.denx.de > > > > > > > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add
Re: [U-Boot] [PATCH 2/2] include:configs: Add usb device-tree fixup for all fsl platforms
> -Original Message- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: Thursday, January 28, 2016 5:04 PM > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > b...@lists.denx.de; Simon Glass <s...@chromium.org> > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all > fsl > platforms > > On Thursday, January 28, 2016 at 12:05:29 PM, Ramneek Mehresh wrote: > > > -Original Message- > > > From: Marek Vasut [mailto:ma...@denx.de] > > > Sent: Wednesday, January 27, 2016 5:13 PM > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup > > > for all fsl platforms > > > > > > On Wednesday, January 27, 2016 at 12:33:04 PM, Ramneek Mehresh > wrote: > > > > > -Original Message----- > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > Sent: Wednesday, January 27, 2016 1:57 PM > > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree > > > > > fixup for all fsl platforms > > > > > > > > > > On Wednesday, January 27, 2016 at 09:26:08 AM, Ramneek Mehresh > > > > > > wrote: > > > > > > > -Original Message- > > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > > Sent: Wednesday, January 27, 2016 1:05 PM > > > > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb > > > > > > > device-tree fixup for all fsl platforms > > > > > > > > > > > > > > On Wednesday, January 27, 2016 at 05:30:51 AM, Ramneek > > > > > > > Mehresh > > > > > > > > > > wrote: > > > > > > > > > -Original Message- > > > > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > > > > Sent: Wednesday, January 27, 2016 9:57 AM > > > > > > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > > > > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; > u- > > > > > > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb > > > > > > > > > device-tree fixup for all fsl platforms > > > > > > > > > > > > > > > > > > On Wednesday, January 27, 2016 at 05:14:00 AM, Ramneek > > > > > > Mehresh > > > > > > > > > > wrote: > > > > > > > > > > > -Original Message- > > > > > > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > > > > > > Sent: Tuesday, January 26, 2016 4:58 PM > > > > > > > > > > > To: Ramneek Mehresh > <ramneek.mehr...@freescale.com> > > > > > > > > > > > Cc: u-boot@lists.denx.de > > > > > > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb > > > > > > > > > > > device-tree fixup for all fsl platforms > > > > > > > > > > > > > > > > > > > > > > On Tuesday, January 26, 2016 at 12:36:58 PM, Ramneek > > > > > > Mehresh > > > > > > > > > > wrote: > > > > > > > > > > > > Add usb device-tree fixup for all relevant fsl ppc > > > > > > > > > > > > and arm platforms > > > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Ramneek Mehresh > > > > > > > > > &g
Re: [U-Boot] [PATCH 2/2] include:configs: Add usb device-tree fixup for all fsl platforms
> -Original Message- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: Wednesday, January 27, 2016 5:13 PM > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > b...@lists.denx.de; Simon Glass <s...@chromium.org> > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all > fsl > platforms > > On Wednesday, January 27, 2016 at 12:33:04 PM, Ramneek Mehresh wrote: > > > -Original Message- > > > From: Marek Vasut [mailto:ma...@denx.de] > > > Sent: Wednesday, January 27, 2016 1:57 PM > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for > > > all fsl platforms > > > > > > On Wednesday, January 27, 2016 at 09:26:08 AM, Ramneek Mehresh > wrote: > > > > > -Original Message----- > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > Sent: Wednesday, January 27, 2016 1:05 PM > > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup > > > > > for all fsl platforms > > > > > > > > > > On Wednesday, January 27, 2016 at 05:30:51 AM, Ramneek Mehresh > > > > > > wrote: > > > > > > > -Original Message- > > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > > Sent: Wednesday, January 27, 2016 9:57 AM > > > > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree > > > > > > > fixup for all fsl platforms > > > > > > > > > > > > > > On Wednesday, January 27, 2016 at 05:14:00 AM, Ramneek > Mehresh > > > > > > > > > > wrote: > > > > > > > > > -Original Message- > > > > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > > > > Sent: Tuesday, January 26, 2016 4:58 PM > > > > > > > > > To: Ramneek Mehresh <ramneek.mehr...@freescale.com> > > > > > > > > > Cc: u-boot@lists.denx.de > > > > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb > > > > > > > > > device-tree fixup for all fsl platforms > > > > > > > > > > > > > > > > > > On Tuesday, January 26, 2016 at 12:36:58 PM, Ramneek > Mehresh > > > > > > > > > > wrote: > > > > > > > > > > Add usb device-tree fixup for all relevant fsl ppc and arm > > > > > > > > > > platforms > > > > > > > > > > > > > > > > > > > > Signed-off-by: Ramneek Mehresh > > > > > > > > > > > > > > <ramneek.mehr...@freescale.com> > > > > > > > > > > > > > > > > > --- > > > > > > > > > > > > > > > > > > > > board/freescale/b4860qds/b4860qds.c | 2 +- > > > > > > > > > > board/freescale/bsc9131rdb/bsc9131rdb.c | 2 ++ > > > > > > > > > > board/freescale/bsc9132qds/bsc9132qds.c | 2 ++ > > > > > > > > > > board/freescale/corenet_ds/corenet_ds.c | 4 > > > > > > > > > > board/freescale/ls2080aqds/ls2080aqds.c | 4 > > > > > > > > > > board/freescale/ls2080ardb/ls2080ardb.c | 4 > > > > > > > > > > board/freescale/mpc8308rdb/mpc8308rdb.c | 4 > > > > > > > > > > board/freescale/mpc8315erdb/mpc8315erdb.c | 2 ++ > > > > > > > > > > board/freescale/mpc837xemds/mpc837xemds.c | 2 ++ > > > > > > &
Re: [U-Boot] [PATCH 2/2] include:configs: Add usb device-tree fixup for all fsl platforms
> -Original Message- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: Wednesday, January 27, 2016 1:05 PM > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > b...@lists.denx.de; Simon Glass <s...@chromium.org> > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all > fsl > platforms > > On Wednesday, January 27, 2016 at 05:30:51 AM, Ramneek Mehresh wrote: > > > -Original Message- > > > From: Marek Vasut [mailto:ma...@denx.de] > > > Sent: Wednesday, January 27, 2016 9:57 AM > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup > > > for all fsl platforms > > > > > > On Wednesday, January 27, 2016 at 05:14:00 AM, Ramneek Mehresh > wrote: > > > > > -Original Message- > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > Sent: Tuesday, January 26, 2016 4:58 PM > > > > > To: Ramneek Mehresh <ramneek.mehr...@freescale.com> > > > > > Cc: u-boot@lists.denx.de > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree > > > > > fixup for all fsl platforms > > > > > > > > > > On Tuesday, January 26, 2016 at 12:36:58 PM, Ramneek Mehresh > wrote: > > > > > > Add usb device-tree fixup for all relevant fsl ppc and arm > > > > > > platforms > > > > > > > > > > > > Signed-off-by: Ramneek Mehresh > > > > > > <ramneek.mehr...@freescale.com> > > > > > > > > > --- > > > > > > > > > > > > board/freescale/b4860qds/b4860qds.c | 2 +- > > > > > > board/freescale/bsc9131rdb/bsc9131rdb.c | 2 ++ > > > > > > board/freescale/bsc9132qds/bsc9132qds.c | 2 ++ > > > > > > board/freescale/corenet_ds/corenet_ds.c | 4 > > > > > > board/freescale/ls2080aqds/ls2080aqds.c | 4 > > > > > > board/freescale/ls2080ardb/ls2080ardb.c | 4 > > > > > > board/freescale/mpc8308rdb/mpc8308rdb.c | 4 > > > > > > board/freescale/mpc8315erdb/mpc8315erdb.c | 2 ++ > > > > > > board/freescale/mpc837xemds/mpc837xemds.c | 2 ++ > > > > > > board/freescale/mpc837xerdb/mpc837xerdb.c | 2 ++ > > > > > > board/freescale/mpc8536ds/mpc8536ds.c | 2 +- > > > > > > board/freescale/p1010rdb/p1010rdb.c | 2 +- > > > > > > board/freescale/p1022ds/p1022ds.c | 2 +- > > > > > > board/freescale/p1023rdb/p1023rdb.c | 2 +- > > > > > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- > > > > > > board/freescale/p1_twr/p1_twr.c | 3 +++ > > > > > > board/freescale/p2041rdb/p2041rdb.c | 2 +- > > > > > > board/freescale/t102xqds/t102xqds.c | 2 +- > > > > > > board/freescale/t102xrdb/t102xrdb.c | 3 +++ > > > > > > board/freescale/t1040qds/t1040qds.c | 2 +- > > > > > > board/freescale/t104xrdb/t104xrdb.c | 2 +- > > > > > > board/freescale/t208xqds/t208xqds.c | 3 +++ > > > > > > board/freescale/t208xrdb/t208xrdb.c | 3 +++ > > > > > > board/freescale/t4qds/t4240emu.c| 3 +++ > > > > > > board/freescale/t4qds/t4240qds.c| 3 +++ > > > > > > board/freescale/t4rdb/t4240rdb.c| 3 +++ > > > > > > include/configs/B4860QDS.h | 1 + > > > > > > include/configs/BSC9131RDB.h| 1 + > > > > > > include/configs/BSC9132QDS.h| 3 ++- > > > > > > include/configs/MPC8308RDB.h| 3 +++ > > > > > > include/configs/MPC8315ERDB.h | 1 + > > > > > > include/configs/MPC837XEMDS.h | 3 ++- > > > > > > include/configs/MPC837XERDB.h | 1 + > > > > > > include/configs/MPC8536DS.h | 1 + > > > > > > include/configs/P1010RDB.h | 1 + > > > > > > include/configs/P1022DS.h
Re: [U-Boot] [PATCH 2/2] include:configs: Add usb device-tree fixup for all fsl platforms
> -Original Message- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: Wednesday, January 27, 2016 1:57 PM > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > b...@lists.denx.de; Simon Glass <s...@chromium.org> > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all > fsl > platforms > > On Wednesday, January 27, 2016 at 09:26:08 AM, Ramneek Mehresh wrote: > > > -Original Message- > > > From: Marek Vasut [mailto:ma...@denx.de] > > > Sent: Wednesday, January 27, 2016 1:05 PM > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup > > > for all fsl platforms > > > > > > On Wednesday, January 27, 2016 at 05:30:51 AM, Ramneek Mehresh > wrote: > > > > > -Original Message----- > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > Sent: Wednesday, January 27, 2016 9:57 AM > > > > > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > > > > > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > > > > > b...@lists.denx.de; Simon Glass <s...@chromium.org> > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree > > > > > fixup for all fsl platforms > > > > > > > > > > On Wednesday, January 27, 2016 at 05:14:00 AM, Ramneek Mehresh > > > > > > wrote: > > > > > > > -Original Message- > > > > > > > From: Marek Vasut [mailto:ma...@denx.de] > > > > > > > Sent: Tuesday, January 26, 2016 4:58 PM > > > > > > > To: Ramneek Mehresh <ramneek.mehr...@freescale.com> > > > > > > > Cc: u-boot@lists.denx.de > > > > > > > Subject: Re: [PATCH 2/2] include:configs: Add usb > > > > > > > device-tree fixup for all fsl platforms > > > > > > > > > > > > > > On Tuesday, January 26, 2016 at 12:36:58 PM, Ramneek Mehresh > > > > > > wrote: > > > > > > > > Add usb device-tree fixup for all relevant fsl ppc and arm > > > > > > > > platforms > > > > > > > > > > > > > > > > Signed-off-by: Ramneek Mehresh > > > > > > > > > > <ramneek.mehr...@freescale.com> > > > > > > > > > > > > > --- > > > > > > > > > > > > > > > > board/freescale/b4860qds/b4860qds.c | 2 +- > > > > > > > > board/freescale/bsc9131rdb/bsc9131rdb.c | 2 ++ > > > > > > > > board/freescale/bsc9132qds/bsc9132qds.c | 2 ++ > > > > > > > > board/freescale/corenet_ds/corenet_ds.c | 4 > > > > > > > > board/freescale/ls2080aqds/ls2080aqds.c | 4 > > > > > > > > board/freescale/ls2080ardb/ls2080ardb.c | 4 > > > > > > > > board/freescale/mpc8308rdb/mpc8308rdb.c | 4 > > > > > > > > board/freescale/mpc8315erdb/mpc8315erdb.c | 2 ++ > > > > > > > > board/freescale/mpc837xemds/mpc837xemds.c | 2 ++ > > > > > > > > board/freescale/mpc837xerdb/mpc837xerdb.c | 2 ++ > > > > > > > > board/freescale/mpc8536ds/mpc8536ds.c | 2 +- > > > > > > > > board/freescale/p1010rdb/p1010rdb.c | 2 +- > > > > > > > > board/freescale/p1022ds/p1022ds.c | 2 +- > > > > > > > > board/freescale/p1023rdb/p1023rdb.c | 2 +- > > > > > > > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- > > > > > > > > board/freescale/p1_twr/p1_twr.c | 3 +++ > > > > > > > > board/freescale/p2041rdb/p2041rdb.c | 2 +- > > > > > > > > board/freescale/t102xqds/t102xqds.c | 2 +- > > > > > > > > board/freescale/t102xrdb/t102xrdb.c | 3 +++ > > > > > > > > board/freescale/t1040qds/t1040qds.c | 2 +- > > > > > > > > board/freescale/t104xrdb/t104xrdb.c | 2 +- > > > > > > > > board/freescale/t208xqds/t208xq
[U-Boot] [PATCH 2/2] include:configs: Add usb device-tree fixup for all fsl platforms
Add usb device-tree fixup for all relevant fsl ppc and arm platforms
Signed-off-by: Ramneek Mehresh <ramneek.mehr...@freescale.com>
---
board/freescale/b4860qds/b4860qds.c | 2 +-
board/freescale/bsc9131rdb/bsc9131rdb.c | 2 ++
board/freescale/bsc9132qds/bsc9132qds.c | 2 ++
board/freescale/corenet_ds/corenet_ds.c | 4
board/freescale/ls2080aqds/ls2080aqds.c | 4
board/freescale/ls2080ardb/ls2080ardb.c | 4
board/freescale/mpc8308rdb/mpc8308rdb.c | 4
board/freescale/mpc8315erdb/mpc8315erdb.c | 2 ++
board/freescale/mpc837xemds/mpc837xemds.c | 2 ++
board/freescale/mpc837xerdb/mpc837xerdb.c | 2 ++
board/freescale/mpc8536ds/mpc8536ds.c | 2 +-
board/freescale/p1010rdb/p1010rdb.c | 2 +-
board/freescale/p1022ds/p1022ds.c | 2 +-
board/freescale/p1023rdb/p1023rdb.c | 2 +-
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +-
board/freescale/p1_twr/p1_twr.c | 3 +++
board/freescale/p2041rdb/p2041rdb.c | 2 +-
board/freescale/t102xqds/t102xqds.c | 2 +-
board/freescale/t102xrdb/t102xrdb.c | 3 +++
board/freescale/t1040qds/t1040qds.c | 2 +-
board/freescale/t104xrdb/t104xrdb.c | 2 +-
board/freescale/t208xqds/t208xqds.c | 3 +++
board/freescale/t208xrdb/t208xrdb.c | 3 +++
board/freescale/t4qds/t4240emu.c| 3 +++
board/freescale/t4qds/t4240qds.c| 3 +++
board/freescale/t4rdb/t4240rdb.c| 3 +++
include/configs/B4860QDS.h | 1 +
include/configs/BSC9131RDB.h| 1 +
include/configs/BSC9132QDS.h| 3 ++-
include/configs/MPC8308RDB.h| 3 +++
include/configs/MPC8315ERDB.h | 1 +
include/configs/MPC837XEMDS.h | 3 ++-
include/configs/MPC837XERDB.h | 1 +
include/configs/MPC8536DS.h | 1 +
include/configs/P1010RDB.h | 1 +
include/configs/P1022DS.h | 1 +
include/configs/P1023RDB.h | 1 +
include/configs/P2041RDB.h | 1 +
include/configs/T102xQDS.h | 1 +
include/configs/T102xRDB.h | 1 +
include/configs/T1040QDS.h | 1 +
include/configs/T104xRDB.h | 1 +
include/configs/T208xQDS.h | 1 +
include/configs/T208xRDB.h | 1 +
include/configs/T4240QDS.h | 1 +
include/configs/corenet_ds.h| 1 +
include/configs/ls2080aqds.h| 1 +
include/configs/ls2080ardb.h| 1 +
include/configs/p1_p2_rdb_pc.h | 1 +
include/configs/p1_twr.h| 1 +
50 files changed, 85 insertions(+), 12 deletions(-)
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index 6a8fca6..0831cda 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -1213,7 +1213,7 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_liodn(blob);
-#ifdef CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_USB_DEVTREE_FIXUP
fdt_fixup_dr_usb(blob, bd);
#endif
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c
b/board/freescale/bsc9131rdb/bsc9131rdb.c
index 75e1142..c3be910 100644
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -73,7 +73,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
+#ifdef CONFIG_USB_DEVTREE_FIXUP
fdt_fixup_dr_usb(blob, bd);
+#endif
return 0;
}
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c
b/board/freescale/bsc9132qds/bsc9132qds.c
index 586dacc..61f96f8 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -394,7 +394,9 @@ int ft_board_setup(void *blob, bd_t *bd)
/* remove dts usb node */
fdt_del_node_compat(blob, "fsl-usb2-dr");
} else {
+#ifdef CONFIG_USB_DEVTREE_FIXUP
fdt_fixup_dr_usb(blob, bd);
+#endif
fdt_del_node_and_alias(blob, "serial2");
}
}
diff --git a/board/freescale/corenet_ds/corenet_ds.c
b/board/freescale/corenet_ds/corenet_ds.c
index 2945339..77f33c2 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -208,6 +208,10 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_liodn(blob);
+#ifdef CONFIG_USB_DEVTREE_FIXUP
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index aa256a2..6b3a15e 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.
[U-Boot] [PATCH 1/2] fsl:usb: Make fsl usb device-tree fixup arch independent
Move usb device-tree fixup from ehci drv so that it becomes
available to all ppc and arm platforms
Signed-off-by: Ramneek Mehresh <ramneek.mehr...@freescale.com>
---
board/freescale/common/Makefile | 2 +
board/freescale/common/usb.c| 203
board/freescale/corenet_ds/corenet_ds.c | 1 -
drivers/usb/host/ehci-fsl.c | 196 --
include/fdt_support.h | 4 +-
5 files changed, 207 insertions(+), 199 deletions(-)
create mode 100644 board/freescale/common/usb.c
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 51d2814..4b83303 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -64,6 +64,8 @@ obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-$(CONFIG_LS102XA_STREAM_ID)+= ls102xa_stream_id.o
+obj-$(CONFIG_USB_DEVTREE_FIXUP)+= usb.o
+
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
obj-$(CONFIG_P3041DS) += p_corenet/
diff --git a/board/freescale/common/usb.c b/board/freescale/common/usb.c
new file mode 100644
index 000..b99fa2b
--- /dev/null
+++ b/board/freescale/common/usb.c
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * Author: Ramneek Mehresh ramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * FSL board device-tree fix-up
+ */
+#include
+#include
+#include
+#include
+
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#endif
+
+static const char *fdt_usb_get_node_type(void *blob, int start_offset,
+int *node_offset)
+{
+ const char *compat_dr = "fsl-usb2-dr";
+ const char *compat_mph = "fsl-usb2-mph";
+ const char *compat_snps = "snps,dwc3";
+ const char *node_type = NULL;
+
+ *node_offset = fdt_node_offset_by_compatible(blob, start_offset,
+compat_mph);
+ if (*node_offset < 0) {
+ *node_offset = fdt_node_offset_by_compatible(blob,
+start_offset,
+compat_dr);
+ if (*node_offset < 0) {
+ *node_offset = fdt_node_offset_by_compatible(blob,
+ start_offset, compat_snps);
+ if (*node_offset < 0) {
+ printf("ERROR:could not find node:%s",
+ fdt_strerror(*node_offset));
+ } else {
+ node_type = compat_snps;
+ }
+ } else {
+ node_type = compat_dr;
+ }
+ } else {
+ node_type = compat_mph;
+ }
+
+ return node_type;
+}
+
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+ const char *phy_type, int start_offset)
+{
+ const char *prop_mode = "dr_mode";
+ const char *prop_type = "phy_type";
+ const char *node_type = NULL;
+ int node_offset;
+ int err;
+
+ node_type = fdt_usb_get_node_type(blob, start_offset, _offset);
+ if (!node_type)
+ return -1;
+
+ if (mode) {
+ err = fdt_setprop(blob, node_offset, prop_mode, mode,
+ strlen(mode) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_mode, node_type, fdt_strerror(err));
+ }
+
+ if (phy_type) {
+ err = fdt_setprop(blob, node_offset, prop_type, phy_type,
+ strlen(phy_type) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_type, node_type, fdt_strerror(err));
+ }
+
+ return node_offset;
+}
+
+static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
+int start_offset)
+{
+ int node_offset, err;
+ const char *node_type = NULL;
+
+ node_type = fdt_usb_get_node_type(blob, start_offset, _offset);
+ if (!node_type)
+ return -1;
+
+ err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
+ if (err < 0) {
+ printf("%s: ERROR: could not set %s for %s: %s.\n", __func__,
+ prop_erratum, node_type, fdt_strerror(err));
+ }
+
+ return node_offset;
+}
+
+void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+{
+ static const char * const modes[] = { &quo
Re: [U-Boot] [PATCH 2/2] include:configs: Add usb device-tree fixup for all fsl platforms
> -Original Message- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: Wednesday, January 27, 2016 9:57 AM > To: Ramneek Mehresh <ramneek.mehr...@nxp.com> > Cc: Ramneek Mehresh <ramneek.mehr...@freescale.com>; u- > b...@lists.denx.de; Simon Glass <s...@chromium.org> > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all > fsl > platforms > > On Wednesday, January 27, 2016 at 05:14:00 AM, Ramneek Mehresh wrote: > > > -Original Message- > > > From: Marek Vasut [mailto:ma...@denx.de] > > > Sent: Tuesday, January 26, 2016 4:58 PM > > > To: Ramneek Mehresh <ramneek.mehr...@freescale.com> > > > Cc: u-boot@lists.denx.de > > > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for > > > all fsl platforms > > > > > > On Tuesday, January 26, 2016 at 12:36:58 PM, Ramneek Mehresh wrote: > > > > Add usb device-tree fixup for all relevant fsl ppc and arm platforms > > > > > > > > Signed-off-by: Ramneek Mehresh > <ramneek.mehr...@freescale.com> > > > > --- > > > > > > > > board/freescale/b4860qds/b4860qds.c | 2 +- > > > > board/freescale/bsc9131rdb/bsc9131rdb.c | 2 ++ > > > > board/freescale/bsc9132qds/bsc9132qds.c | 2 ++ > > > > board/freescale/corenet_ds/corenet_ds.c | 4 > > > > board/freescale/ls2080aqds/ls2080aqds.c | 4 > > > > board/freescale/ls2080ardb/ls2080ardb.c | 4 > > > > board/freescale/mpc8308rdb/mpc8308rdb.c | 4 > > > > board/freescale/mpc8315erdb/mpc8315erdb.c | 2 ++ > > > > board/freescale/mpc837xemds/mpc837xemds.c | 2 ++ > > > > board/freescale/mpc837xerdb/mpc837xerdb.c | 2 ++ > > > > board/freescale/mpc8536ds/mpc8536ds.c | 2 +- > > > > board/freescale/p1010rdb/p1010rdb.c | 2 +- > > > > board/freescale/p1022ds/p1022ds.c | 2 +- > > > > board/freescale/p1023rdb/p1023rdb.c | 2 +- > > > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- > > > > board/freescale/p1_twr/p1_twr.c | 3 +++ > > > > board/freescale/p2041rdb/p2041rdb.c | 2 +- > > > > board/freescale/t102xqds/t102xqds.c | 2 +- > > > > board/freescale/t102xrdb/t102xrdb.c | 3 +++ > > > > board/freescale/t1040qds/t1040qds.c | 2 +- > > > > board/freescale/t104xrdb/t104xrdb.c | 2 +- > > > > board/freescale/t208xqds/t208xqds.c | 3 +++ > > > > board/freescale/t208xrdb/t208xrdb.c | 3 +++ > > > > board/freescale/t4qds/t4240emu.c| 3 +++ > > > > board/freescale/t4qds/t4240qds.c| 3 +++ > > > > board/freescale/t4rdb/t4240rdb.c| 3 +++ > > > > include/configs/B4860QDS.h | 1 + > > > > include/configs/BSC9131RDB.h| 1 + > > > > include/configs/BSC9132QDS.h| 3 ++- > > > > include/configs/MPC8308RDB.h| 3 +++ > > > > include/configs/MPC8315ERDB.h | 1 + > > > > include/configs/MPC837XEMDS.h | 3 ++- > > > > include/configs/MPC837XERDB.h | 1 + > > > > include/configs/MPC8536DS.h | 1 + > > > > include/configs/P1010RDB.h | 1 + > > > > include/configs/P1022DS.h | 1 + > > > > include/configs/P1023RDB.h | 1 + > > > > include/configs/P2041RDB.h | 1 + > > > > include/configs/T102xQDS.h | 1 + > > > > include/configs/T102xRDB.h | 1 + > > > > include/configs/T1040QDS.h | 1 + > > > > include/configs/T104xRDB.h | 1 + > > > > include/configs/T208xQDS.h | 1 + > > > > include/configs/T208xRDB.h | 1 + > > > > include/configs/T4240QDS.h | 1 + > > > > include/configs/corenet_ds.h| 1 + > > > > include/configs/ls2080aqds.h| 1 + > > > > include/configs/ls2080ardb.h| 1 + > > > > include/configs/p1_p2_rdb_pc.h | 1 + > > > > include/configs/p1_twr.h| 1 + > > > > 50 files changed, 85 insertions(+), 12 deletions(-) > > > > > > Each such new macro must be documented. What is the point of this bulk > > > rename anyway? > > > > Yes, I'll document the new MACRO defined for usb device-tree fixup. > > However, this is not bulk rename. I just modified all these files to > > include usb device-tree fixup for all fsl ppc platforms. Most of these > > platforms were already using this mechanism (some via different ways), > but > > now its consistent across them. > > Wouldn't it make more sense to make this generic then instead of patching > zillion files ? The patch set is to make this support generic, but I do need to make these platforms use this generic support in consistent way via single macro inclusion in their configs... ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] include:configs: Add usb device-tree fixup for all fsl platforms
> -Original Message- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: Tuesday, January 26, 2016 4:58 PM > To: Ramneek Mehresh <ramneek.mehr...@freescale.com> > Cc: u-boot@lists.denx.de > Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all > fsl > platforms > > On Tuesday, January 26, 2016 at 12:36:58 PM, Ramneek Mehresh wrote: > > Add usb device-tree fixup for all relevant fsl ppc and arm platforms > > > > Signed-off-by: Ramneek Mehresh <ramneek.mehr...@freescale.com> > > --- > > board/freescale/b4860qds/b4860qds.c | 2 +- > > board/freescale/bsc9131rdb/bsc9131rdb.c | 2 ++ > > board/freescale/bsc9132qds/bsc9132qds.c | 2 ++ > > board/freescale/corenet_ds/corenet_ds.c | 4 > > board/freescale/ls2080aqds/ls2080aqds.c | 4 > > board/freescale/ls2080ardb/ls2080ardb.c | 4 > > board/freescale/mpc8308rdb/mpc8308rdb.c | 4 > > board/freescale/mpc8315erdb/mpc8315erdb.c | 2 ++ > > board/freescale/mpc837xemds/mpc837xemds.c | 2 ++ > > board/freescale/mpc837xerdb/mpc837xerdb.c | 2 ++ > > board/freescale/mpc8536ds/mpc8536ds.c | 2 +- > > board/freescale/p1010rdb/p1010rdb.c | 2 +- > > board/freescale/p1022ds/p1022ds.c | 2 +- > > board/freescale/p1023rdb/p1023rdb.c | 2 +- > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- > > board/freescale/p1_twr/p1_twr.c | 3 +++ > > board/freescale/p2041rdb/p2041rdb.c | 2 +- > > board/freescale/t102xqds/t102xqds.c | 2 +- > > board/freescale/t102xrdb/t102xrdb.c | 3 +++ > > board/freescale/t1040qds/t1040qds.c | 2 +- > > board/freescale/t104xrdb/t104xrdb.c | 2 +- > > board/freescale/t208xqds/t208xqds.c | 3 +++ > > board/freescale/t208xrdb/t208xrdb.c | 3 +++ > > board/freescale/t4qds/t4240emu.c| 3 +++ > > board/freescale/t4qds/t4240qds.c| 3 +++ > > board/freescale/t4rdb/t4240rdb.c| 3 +++ > > include/configs/B4860QDS.h | 1 + > > include/configs/BSC9131RDB.h| 1 + > > include/configs/BSC9132QDS.h| 3 ++- > > include/configs/MPC8308RDB.h| 3 +++ > > include/configs/MPC8315ERDB.h | 1 + > > include/configs/MPC837XEMDS.h | 3 ++- > > include/configs/MPC837XERDB.h | 1 + > > include/configs/MPC8536DS.h | 1 + > > include/configs/P1010RDB.h | 1 + > > include/configs/P1022DS.h | 1 + > > include/configs/P1023RDB.h | 1 + > > include/configs/P2041RDB.h | 1 + > > include/configs/T102xQDS.h | 1 + > > include/configs/T102xRDB.h | 1 + > > include/configs/T1040QDS.h | 1 + > > include/configs/T104xRDB.h | 1 + > > include/configs/T208xQDS.h | 1 + > > include/configs/T208xRDB.h | 1 + > > include/configs/T4240QDS.h | 1 + > > include/configs/corenet_ds.h| 1 + > > include/configs/ls2080aqds.h| 1 + > > include/configs/ls2080ardb.h| 1 + > > include/configs/p1_p2_rdb_pc.h | 1 + > > include/configs/p1_twr.h| 1 + > > 50 files changed, 85 insertions(+), 12 deletions(-) > > Each such new macro must be documented. What is the point of this bulk > rename anyway? Yes, I'll document the new MACRO defined for usb device-tree fixup. However, this is not bulk rename. I just modified all these files to include usb device-tree fixup for all fsl ppc platforms. Most of these platforms were already using this mechanism (some via different ways), but now its consistent across them. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8] usb:xhci:exynos: Remove common dwc3 drv functions calls
Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/xhci-exynos5.c | 78
include/configs/exynos5-common.h | 1 +
2 files changed, 1 insertion(+), 78 deletions(-)
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
index a27a796..251885b 100644
--- a/drivers/usb/host/xhci-exynos5.c
+++ b/drivers/usb/host/xhci-exynos5.c
@@ -179,84 +179,6 @@ static void exynos5_usb3_phy_exit(struct exynos_usb3_phy
*phy)
set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
}
-static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
-{
- clrsetbits_le32(dwc3_reg-g_ctl,
- DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
- DWC3_GCTL_PRTCAPDIR(mode));
-}
-
-static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
-{
- /* Before Resetting PHY, put Core in Reset */
- setbits_le32(dwc3_reg-g_ctl,
- DWC3_GCTL_CORESOFTRESET);
-
- /* Assert USB3 PHY reset */
- setbits_le32(dwc3_reg-g_usb3pipectl[0],
- DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Assert USB2 PHY reset */
- setbits_le32(dwc3_reg-g_usb2phycfg,
- DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- mdelay(100);
-
- /* Clear USB3 PHY reset */
- clrbits_le32(dwc3_reg-g_usb3pipectl[0],
- DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Clear USB2 PHY reset */
- clrbits_le32(dwc3_reg-g_usb2phycfg,
- DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- /* After PHYs are stable we can take Core out of reset state */
- clrbits_le32(dwc3_reg-g_ctl,
- DWC3_GCTL_CORESOFTRESET);
-}
-
-static int dwc3_core_init(struct dwc3 *dwc3_reg)
-{
- u32 reg;
- u32 revision;
- unsigned int dwc3_hwparams1;
-
- revision = readl(dwc3_reg-g_snpsid);
- /* This should read as U3 followed by revision number */
- if ((revision DWC3_GSNPSID_MASK) != 0x5533) {
- puts(this is not a DesignWare USB3 DRD Core\n);
- return -EINVAL;
- }
-
- dwc3_core_soft_reset(dwc3_reg);
-
- dwc3_hwparams1 = readl(dwc3_reg-g_hwparams1);
-
- reg = readl(dwc3_reg-g_ctl);
- reg = ~DWC3_GCTL_SCALEDOWN_MASK;
- reg = ~DWC3_GCTL_DISSCRAMBLE;
- switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
- case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
- reg = ~DWC3_GCTL_DSBLCLKGTNG;
- break;
- default:
- debug(No power optimization available\n);
- }
-
- /*
-* WORKAROUND: DWC3 revisions 1.90a have a bug
-* where the device can fail to connect at SuperSpeed
-* and falls back to high-speed mode which causes
-* the device to enter a Connect/Disconnect loop
-*/
- if ((revision DWC3_REVISION_MASK) 0x190a)
- reg |= DWC3_GCTL_U2RSTECN;
-
- writel(reg, dwc3_reg-g_ctl);
-
- return 0;
-}
-
static int exynos_xhci_core_init(struct exynos_xhci *exynos)
{
int ret;
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 5476248..e04dec7 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -182,6 +182,7 @@
/* USB */
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
--
1.8.3.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/8] usb:xhci:keystone: Remove common dwc3 drv functions calls
Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/xhci-keystone.c | 88
include/configs/ks2_evm.h| 1 +
2 files changed, 1 insertion(+), 88 deletions(-)
diff --git a/drivers/usb/host/xhci-keystone.c b/drivers/usb/host/xhci-keystone.c
index 05d338f..924fb76 100644
--- a/drivers/usb/host/xhci-keystone.c
+++ b/drivers/usb/host/xhci-keystone.c
@@ -68,94 +68,6 @@ static void keystone_xhci_phy_unset(struct keystone_xhci_phy
*phy)
writel(val, phy-phy_clock);
}
-static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
-{
- clrsetbits_le32(dwc3_reg-g_ctl,
- DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
- DWC3_GCTL_PRTCAPDIR(mode));
-}
-
-static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
-{
- /* Before Resetting PHY, put Core in Reset */
- setbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
-
- /* Assert USB3 PHY reset */
- setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Assert USB2 PHY reset */
- setbits_le32(dwc3_reg-g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- mdelay(100);
-
- /* Clear USB3 PHY reset */
- clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Clear USB2 PHY reset */
- clrbits_le32(dwc3_reg-g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- /* After PHYs are stable we can take Core out of reset state */
- clrbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
-}
-
-static int dwc3_core_init(struct dwc3 *dwc3_reg)
-{
- u32 revision, val;
- unsigned long t_rst;
- unsigned int dwc3_hwparams1;
-
- revision = readl(dwc3_reg-g_snpsid);
- /* This should read as U3 followed by revision number */
- if ((revision DWC3_GSNPSID_MASK) != 0x5533) {
- puts(this is not a DesignWare USB3 DRD Core\n);
- return -EINVAL;
- }
-
- /* issue device SoftReset too */
- writel(DWC3_DCTL_CSFTRST, dwc3_reg-d_ctl);
-
- t_rst = get_timer(0);
- do {
- val = readl(dwc3_reg-d_ctl);
- if (!(val DWC3_DCTL_CSFTRST))
- break;
- WATCHDOG_RESET();
- } while (get_timer(t_rst) 500);
-
- if (val DWC3_DCTL_CSFTRST) {
- debug(Reset timed out\n);
- return -2;
- }
-
- dwc3_core_soft_reset(dwc3_reg);
-
- dwc3_hwparams1 = readl(dwc3_reg-g_hwparams1);
-
- val = readl(dwc3_reg-g_ctl);
- val = ~DWC3_GCTL_SCALEDOWN_MASK;
- val = ~DWC3_GCTL_DISSCRAMBLE;
- switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
- case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
- val = ~DWC3_GCTL_DSBLCLKGTNG;
- break;
- default:
- printf(No power optimization available\n);
- }
-
- /*
-* WORKAROUND: DWC3 revisions 1.90a have a bug
-* where the device can fail to connect at SuperSpeed
-* and falls back to high-speed mode which causes
-* the device to enter a Connect/Disconnect loop
-*/
- if ((revision DWC3_REVISION_MASK) 0x190a)
- val |= DWC3_GCTL_U2RSTECN;
-
- writel(val, dwc3_reg-g_ctl);
-
- return 0;
-}
-
static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
{
int ret;
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 42280ca..58730b2 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -197,6 +197,7 @@
/* USB Configuration */
#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
--
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[U-Boot] [PATCH 3/8] usb:xhci:omap: Remove common dwc3 drv functions calls
Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/xhci-omap.c | 60 --
drivers/usb/phy/omap_usb_phy.c | 18 -
include/configs/am43xx_evm.h | 1 +
include/configs/beagle_x15.h | 1 +
include/configs/dra7xx_evm.h | 1 +
5 files changed, 3 insertions(+), 78 deletions(-)
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index 912b2bd..3a55208 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -34,66 +34,6 @@ inline int __board_usb_init(int index, enum usb_init_type
init)
int board_usb_init(int index, enum usb_init_type init)
__attribute__((weak, alias(__board_usb_init)));
-static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
-{
- clrsetbits_le32(dwc3_reg-g_ctl,
- DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
- DWC3_GCTL_PRTCAPDIR(mode));
-}
-
-static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
-{
- /* Before Resetting PHY, put Core in Reset */
- setbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
-
- omap_reset_usb_phy(dwc3_reg);
-
- /* After PHYs are stable we can take Core out of reset state */
- clrbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
-}
-
-static int dwc3_core_init(struct dwc3 *dwc3_reg)
-{
- u32 reg;
- u32 revision;
- unsigned int dwc3_hwparams1;
-
- revision = readl(dwc3_reg-g_snpsid);
- /* This should read as U3 followed by revision number */
- if ((revision DWC3_GSNPSID_MASK) != 0x5533) {
- puts(this is not a DesignWare USB3 DRD Core\n);
- return -1;
- }
-
- dwc3_core_soft_reset(dwc3_reg);
-
- dwc3_hwparams1 = readl(dwc3_reg-g_hwparams1);
-
- reg = readl(dwc3_reg-g_ctl);
- reg = ~DWC3_GCTL_SCALEDOWN_MASK;
- reg = ~DWC3_GCTL_DISSCRAMBLE;
- switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
- case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
- reg = ~DWC3_GCTL_DSBLCLKGTNG;
- break;
- default:
- debug(No power optimization available\n);
- }
-
- /*
-* WORKAROUND: DWC3 revisions 1.90a have a bug
-* where the device can fail to connect at SuperSpeed
-* and falls back to high-speed mode which causes
-* the device to enter a Connect/Disconnect loop
-*/
- if ((revision DWC3_REVISION_MASK) 0x190a)
- reg |= DWC3_GCTL_U2RSTECN;
-
- writel(reg, dwc3_reg-g_ctl);
-
- return 0;
-}
-
static int omap_xhci_core_init(struct omap_xhci *omap)
{
int ret = 0;
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index 63d9301..f9069c7 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -223,24 +223,6 @@ void usb_phy_power(int on)
}
#endif /* CONFIG_AM437X_USB2PHY2_HOST */
-void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
-{
- /* Assert USB3 PHY reset */
- setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Assert USB2 PHY reset */
- setbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- mdelay(100);
-
- /* Clear USB3 PHY reset */
- clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Clear USB2 PHY reset */
- clrbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
-}
-
void omap_enable_phy(struct omap_xhci *omap)
{
#ifdef CONFIG_OMAP_USB2PHY2_HOST
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 331fdac..276aee4 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -102,6 +102,7 @@
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h
index 4aa8550..f350d79 100644
--- a/include/configs/beagle_x15.h
+++ b/include/configs/beagle_x15.h
@@ -66,6 +66,7 @@
/* USB xHCI HOST */
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index d79612b..c690795 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -173,6 +173,7 @@
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
--
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[U-Boot] [PATCH 6/8] arch:arm:fsl: Add XHCI support for LS1021A
From: ramneek mehresh ramneek.mehr...@freescale.com
Add base register address information for USB
XHCI controller on LS1021A
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index 4dc528b..c55cdef 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -35,6 +35,7 @@
#define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR +
0x011c0500)
#define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_IMMR +
0x011d0500)
#define CONFIG_SYS_DCU_ADDR(CONFIG_SYS_IMMR + 0x01ce)
+#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x0210)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index ee547fb..8e5fcdc 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -395,4 +395,14 @@ struct ccsr_cci400 {
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x1 - 0xe004];
};
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE 0x310
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A02
+
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+ CONFIG_SYS_FSL_XHCI_USB2_ADDR}
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
--
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[U-Boot] [PATCH 8/8] include:configs:ls1021aqds: Enable USB IP support
From: ramneek mehresh ramneek.mehr...@freescale.com Enable USB IP support for both EHCI and XHCI for ls1021aqds platform Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021aqds.h | 22 +- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1a41a2f..095c32b 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -424,19 +424,31 @@ unsigned long get_board_ddr_clk(void); /* * USB */ -#define CONFIG_HAS_FSL_DR_USB +/* EHCI Support - disbaled by default */ +/*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif -#ifdef CONFIG_USB_EHCI +/*XHCI Support - enabled by default*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_XHCI +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_CMD_EXT2 #endif -#endif /* * Video -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code
A lot of dwc3 code has been duplicated in various xhci drivers. Hence, to minimize this duplication, a new dwc3 file is written that provides common APIs for all other drivers. First four patches introduce dwc3 file, and necessary changes are made in other drivers for this new drv. I would request all platform/driver owners to please help me in testng these changes on their respective platforms. Last four patches are freescale layerscape la1021aqds/ ls1021atwr platform specific. Ramneek Mehresh (4): drivers:usb:dwc3: Add DWC3 controller driver support usb:xhci:exynos: Remove common dwc3 drv functions calls usb:xhci:omap: Remove common dwc3 drv functions calls usb:xhci:keystone: Remove common dwc3 drv functions calls ramneek mehresh (4): drivers:usb:fsl: Add XHCI driver support arch:arm:fsl: Add XHCI support for LS1021A include:configs:ls1021atwr: Enable USB IP support include:configs:ls1021aqds: Enable USB IP support arch/arm/include/asm/arch-ls102xa/config.h| 1 + arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 10 ++ drivers/usb/host/Makefile | 2 + drivers/usb/host/xhci-dwc3.c | 91 ++ drivers/usb/host/xhci-exynos5.c | 78 drivers/usb/host/xhci-fsl.c | 109 ++ drivers/usb/host/xhci-keystone.c | 88 - drivers/usb/host/xhci-omap.c | 60 drivers/usb/phy/omap_usb_phy.c| 18 include/configs/am43xx_evm.h | 1 + include/configs/beagle_x15.h | 1 + include/configs/dra7xx_evm.h | 1 + include/configs/exynos5-common.h | 1 + include/configs/ks2_evm.h | 1 + include/configs/ls1021aqds.h | 22 - include/configs/ls1021atwr.h | 38 include/linux/usb/dwc3.h | 6 ++ include/linux/usb/xhci-fsl.h | 54 +++ 18 files changed, 333 insertions(+), 249 deletions(-) create mode 100644 drivers/usb/host/xhci-dwc3.c create mode 100644 drivers/usb/host/xhci-fsl.c create mode 100644 include/linux/usb/xhci-fsl.h -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/8] drivers:usb:dwc3: Add DWC3 controller driver support
Add support for DWC3 XHCI controller driver
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-dwc3.c | 91
include/linux/usb/dwc3.h | 6 +++
3 files changed, 98 insertions(+)
create mode 100644 drivers/usb/host/xhci-dwc3.c
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 4d35d3e..310d979 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
new file mode 100644
index 000..67147cb
--- /dev/null
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * DWC3 controller driver
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include linux/usb/dwc3.h
+
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+ clrsetbits_le32(dwc3_reg-g_ctl,
+ DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+ DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+void dwc3_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(100);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+ /* Before Resetting PHY, put Core in Reset */
+ setbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+ /* reset USB3 phy - if required */
+ dwc3_phy_reset(dwc3_reg);
+
+ /* After PHYs are stable we can take Core out of reset state */
+ clrbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+ u32 reg;
+ u32 revision;
+ unsigned int dwc3_hwparams1;
+
+ revision = readl(dwc3_reg-g_snpsid);
+ /* This should read as U3 followed by revision number */
+ if ((revision DWC3_GSNPSID_MASK) != 0x5533) {
+ puts(this is not a DesignWare USB3 DRD Core\n);
+ return -1;
+ }
+
+ dwc3_core_soft_reset(dwc3_reg);
+
+ dwc3_hwparams1 = readl(dwc3_reg-g_hwparams1);
+
+ reg = readl(dwc3_reg-g_ctl);
+ reg = ~DWC3_GCTL_SCALEDOWN_MASK;
+ reg = ~DWC3_GCTL_DISSCRAMBLE;
+ switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+ case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+ reg = ~DWC3_GCTL_DSBLCLKGTNG;
+ break;
+ default:
+ debug(No power optimization available\n);
+ }
+
+ /*
+* WORKAROUND: DWC3 revisions 1.90a have a bug
+* where the device can fail to connect at SuperSpeed
+* and falls back to high-speed mode which causes
+* the device to enter a Connect/Disconnect loop
+*/
+ if ((revision DWC3_REVISION_MASK) 0x190a)
+ reg |= DWC3_GCTL_U2RSTECN;
+
+ writel(reg, dwc3_reg-g_ctl);
+
+ return 0;
+}
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 7edc760..ba7f314 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -191,4 +191,10 @@ struct dwc3 { /*
offset: 0xC100 */
#define DWC3_DCTL_CSFTRST (1 30)
#define DWC3_DCTL_LSFTRST (1 29)
+#ifdef CONFIG_USB_XHCI_DWC3
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
+int dwc3_core_init(struct dwc3 *dwc3_reg);
+void usb_phy_reset(struct dwc3 *dwc3_reg);
+#endif
#endif /* __DWC3_H_ */
--
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[U-Boot] [PATCH 5/8] drivers:usb:fsl: Add XHCI driver support
From: ramneek mehresh ramneek.mehr...@freescale.com
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-fsl.c | 109 +++
include/linux/usb/xhci-fsl.h | 54 +
3 files changed, 164 insertions(+)
create mode 100644 drivers/usb/host/xhci-fsl.c
create mode 100644 include/linux/usb/xhci-fsl.h
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 310d979..6cc3bbd 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644
index 000..f624c90
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include usb.h
+#include asm-generic/errno.h
+#include asm/arch-ls102xa/immap_ls102xa.h
+#include linux/compat.h
+#include linux/usb/xhci-fsl.h
+#include linux/usb/dwc3.h
+#include xhci.h
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
+
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
+{
+ int ret = 0;
+
+ ret = dwc3_core_init(fsl_xhci-dwc3_reg);
+ if (ret) {
+ debug(%s:failed to initialize core\n, __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+ /*
+* Currently fsl socs do not support PHY shutdown from
+* sw. But this support may be added in future socs.
+*/
+ return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)ctr_addr[index];
+ ctx-dwc3_reg = (struct dwc3 *)((char *)(ctx-hcd) + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = fsl_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)ctx-hcd;
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ debug(fsl-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+
+ fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 000..8eaab2c
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
+#define USB3_PHY_RX_POWERONBIT(14)
+#define USB3_PHY_TX_POWERONBIT(15)
+#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT 14
+#define
[U-Boot] [PATCH 7/8] include:configs:ls1021atwr: Enable USB IP support
From: ramneek mehresh ramneek.mehr...@freescale.com Enable USB IP support for both EHCI and XHCI for ls1021atwr platform Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021atwr.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 8ea428e..f2dca5e 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -28,6 +28,44 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* + * USB + */ + +/* + * EHCI Support - disbaled by default as + * there is no signal coming out of soc on + * this board for this controller. However, + * the silicon still has this controller, + * and anyone can use this controller by + * taking signals out on their board. + */ + +/*#define CONFIG_HAS_FSL_DR_USB*/ + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + +/* XHCI Support - enabled by default */ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_XHCI +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + +/* * Generic Timer Definitions */ #define GENERIC_TIMER_CLK 1250 -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] drivers:usb:dwc3: Add DWC3 controller driver support
Add support for DWC3 XHCI controller driver
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-dwc3.c | 74
include/linux/usb/dwc3.h | 4 +++
3 files changed, 79 insertions(+)
create mode 100644 drivers/usb/host/xhci-dwc3.c
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7658f87..c0d95cf 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
new file mode 100644
index 000..a50d81a
--- /dev/null
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * DWC3 controller driver
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include linux/usb/dwc3.h
+
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+ clrsetbits_le32(dwc3_reg-g_ctl,
+ DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+ DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+ /* Before Resetting PHY, put Core in Reset */
+ setbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+ /* reset USB3 phy - if required */
+ usb_phy_reset(dwc3_reg);
+
+ /* After PHYs are stable we can take Core out of reset state */
+ clrbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+ u32 reg;
+ u32 revision;
+ unsigned int dwc3_hwparams1;
+
+ revision = readl(dwc3_reg-g_snpsid);
+ /* This should read as U3 followed by revision number */
+ if ((revision DWC3_GSNPSID_MASK) != 0x5533) {
+ puts(this is not a DesignWare USB3 DRD Core\n);
+ return -1;
+ }
+
+ dwc3_core_soft_reset(dwc3_reg);
+
+ dwc3_hwparams1 = readl(dwc3_reg-g_hwparams1);
+
+ reg = readl(dwc3_reg-g_ctl);
+ reg = ~DWC3_GCTL_SCALEDOWN_MASK;
+ reg = ~DWC3_GCTL_DISSCRAMBLE;
+ switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+ case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+ reg = ~DWC3_GCTL_DSBLCLKGTNG;
+ break;
+ default:
+ debug(No power optimization available\n);
+ }
+
+ /*
+* WORKAROUND: DWC3 revisions 1.90a have a bug
+* where the device can fail to connect at SuperSpeed
+* and falls back to high-speed mode which causes
+* the device to enter a Connect/Disconnect loop
+*/
+ if ((revision DWC3_REVISION_MASK) 0x190a)
+ reg |= DWC3_GCTL_U2RSTECN;
+
+ writel(reg, dwc3_reg-g_ctl);
+
+ return 0;
+}
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 7edc760..c21878c 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -191,4 +191,8 @@ struct dwc3 { /*
offset: 0xC100 */
#define DWC3_DCTL_CSFTRST (1 30)
#define DWC3_DCTL_LSFTRST (1 29)
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
+int dwc3_core_init(struct dwc3 *dwc3_reg);
+void usb_phy_reset(struct dwc3 *dwc3_reg);
#endif /* __DWC3_H_ */
--
1.8.3.1
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[U-Boot] [PATCH 2/5][v3]drivers:usb:fsl: Add XHCI driver support
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v3:
- use FSL_USB_XHCI_ADDR for controller addr
- corrected multiline comment
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-fsl.c | 109 +++
include/linux/usb/xhci-fsl.h | 54 +
3 files changed, 164 insertions(+)
create mode 100644 drivers/usb/host/xhci-fsl.c
create mode 100644 include/linux/usb/xhci-fsl.h
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c0d95cf..7c94439 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644
index 000..f624c90
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include usb.h
+#include asm-generic/errno.h
+#include asm/arch-ls102xa/immap_ls102xa.h
+#include linux/compat.h
+#include linux/usb/xhci-fsl.h
+#include linux/usb/dwc3.h
+#include xhci.h
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
+
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
+{
+ int ret = 0;
+
+ ret = dwc3_core_init(fsl_xhci-dwc3_reg);
+ if (ret) {
+ debug(%s:failed to initialize core\n, __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+ /*
+* Currently fsl socs do not support PHY shutdown from
+* sw. But this support may be added in future socs.
+*/
+ return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)ctr_addr[index];
+ ctx-dwc3_reg = (struct dwc3 *)((char *)(ctx-hcd) + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = fsl_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)ctx-hcd;
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ debug(fsl-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+
+ fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 000..8eaab2c
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
+#define USB3_PHY_RX_POWERONBIT(14)
+#define USB3_PHY_TX_POWERONBIT(15)
+#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON
[U-Boot] [PATCH 3/5] arch:arm:fsl: Add XHCI support for LS1021A
Add base register address information for USB
XHCI controller on LS1021A
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index 6561ce6..f672341 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -35,6 +35,7 @@
#define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR +
0x011c0500)
#define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_IMMR +
0x011d0500)
#define CONFIG_SYS_DCU_ADDR(CONFIG_SYS_IMMR + 0x01ce)
+#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x0210)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 3a64afc..b5f570e 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -538,4 +538,14 @@ struct ccsr_cci400 {
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x1 - 0xe004];
};
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE 0x310
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A02
+
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+ CONFIG_SYS_FSL_XHCI_USB2_ADDR}
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
--
1.8.3.1
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[U-Boot] [PATCH 4/5][v3]include:configs:ls1021atwr: Enable USB IP support
Enable USB IP support for both EHCI and XHCI for ls1021atwr platform Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- Changes for v3: - corrected multiline comment - moved out xhci controller soc specific base addresse(s) to soc file include/configs/ls1021atwr.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a13876b..a96bc22 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -28,6 +28,44 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* + * USB + */ + +/* + * EHCI Support - disbaled by default as + * there is no signal coming out of soc on + * this board for this controller. However, + * the silicon still has this controller, + * and anyone can use this controller by + * taking signals out on their board. + */ + +/*#define CONFIG_HAS_FSL_DR_USB*/ + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + +/* XHCI Support - enabled by default */ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_XHCI +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + +/* * Generic Timer Definitions */ #define GENERIC_TIMER_CLK 1250 -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] include:configs:ls1021aqds: Enable USB IP support
Enable USB IP support for both EHCI and XHCI for ls1021aqds platform Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021aqds.h | 22 +- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5de416d..1aa2f94 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -423,19 +423,31 @@ unsigned long get_board_ddr_clk(void); /* * USB */ -#define CONFIG_HAS_FSL_DR_USB +/* EHCI Support - disbaled by default */ +/*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif -#ifdef CONFIG_USB_EHCI +/*XHCI Support - enabled by default*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_XHCI +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_CMD_EXT2 #endif -#endif /* * Video -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4][v2]include:configs:ls1021atwr: Enable USB IP support
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Friday, April 24, 2015 9:00 AM
To: Mehresh Ramneek-B31383
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH 3/4][v2]include:configs:ls1021atwr: Enable USB IP
support
On Thursday, April 23, 2015 at 07:03:14 PM, Ramneek Mehresh wrote:
Enable USB IP support for both EHCI and XHCI for ls1021atwr platform
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
include/configs/ls1021atwr.h | 36
include/linux/usb/xhci-fsl.h | 5 +
2 files changed, 41 insertions(+)
diff --git a/include/configs/ls1021atwr.h
b/include/configs/ls1021atwr.h index a13876b..f208638 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -28,6 +28,42 @@
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/*
+ * USB
+ */
+
+/* EHCI Support - disbaled by default as
+ * there is no signal coming out of soc on
+ * this board for this controller. However,
+ * the silicon still has this controller,
+ * and anyone can use this controller by
+ * taking signals out on their board.
+ */
Multiline comment again ;-)
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif
+
+/* XHCI Support - enabled by default */ #define
+CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) ||
+defined(CONFIG_HAS_FSL_XHCI_USB) #define CONFIG_CMD_USB
#define
+CONFIG_USB_STORAGE #define CONFIG_CMD_EXT2 #endif
+
+/*
* Generic Timer Definitions
*/
#define GENERIC_TIMER_CLK 1250
diff --git a/include/linux/usb/xhci-fsl.h
b/include/linux/usb/xhci-fsl.h index 8eaab2c..329abf7 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -46,6 +46,11 @@
#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_ENBIT(17)
+#ifdef CONFIG_LS102XA
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR
+CONFIG_SYS_LS102XA_XHCI_USB1_ADDR #define
+CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
Do you need to define this _bogus_ address at all? If so, then the driver
which depends on this is broken. Why can't you just define a list of addresses
instead ? You would be able to use ARRAY_SIZE() in the driver to determine
how many controllers there are then. This is how it would look like:
#define CONFIG_FOO_BAR_ADDRS { USB1_ADDR, USB2_ADDR, ...,
USBn_ADDR }
In the driver, there'd be:
type addrs[] = CONFIG_FOO_BAR_ADDRS;
I agree to use an array for defining list of controller addresses. However, the
no.
of controller(s) to be initialized on a particular platform is determined by
CONFIG_USB_MAX_CONTROLLER_COUNT
used in usb_init() function. This macro is defined in each platform file, and
defines the index argument passed on to
xhci_hcd_init(). There may be some platform on which we can have more than one
controller in soc, but only
one is used (exposed via external connector). Hence,
CONFIG_USB_MAX_CONTROLLER_COUNT is defined by
platform header file.
Hence, I can assign controller address on the basis of address:
struct fsl_xhci *ctx = fsl_xhci;
ctx-hcd = addrs[index];
+#endif
+
struct fsl_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
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[U-Boot] [PATCH 2/4][v2]drivers:usb:fsl: Add XHCI driver support
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-fsl.c | 107 ++
include/linux/usb/xhci-fsl.h | 54 +++
4 files changed, 168 insertions(+)
create mode 100644 drivers/usb/host/xhci-fsl.c
create mode 100644 include/linux/usb/xhci-fsl.h
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 3a64afc..9c1f1ce 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -538,4 +538,10 @@ struct ccsr_cci400 {
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x1 - 0xe004];
};
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE 0x310
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A02
+
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c0d95cf..7c94439 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644
index 000..4ffcd6a
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include usb.h
+#include asm-generic/errno.h
+#include asm/arch-ls102xa/immap_ls102xa.h
+#include linux/compat.h
+#include linux/usb/xhci-fsl.h
+#include linux/usb/dwc3.h
+#include xhci.h
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
+{
+ int ret = 0;
+
+ ret = dwc3_core_init(fsl_xhci-dwc3_reg);
+ if (ret) {
+ debug(%s:failed to initialize core\n, __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+ /* Currently fsl socs do not support PHY shutdown from
+* sw. But this support may be added in future socs.
+*/
+ return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
+ ctx-dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = fsl_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ debug(fsl-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+
+ fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 000..8eaab2c
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek
[U-Boot] [PATCH 3/4][v2]include:configs:ls1021atwr: Enable USB IP support
Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
include/configs/ls1021atwr.h | 36
include/linux/usb/xhci-fsl.h | 5 +
2 files changed, 41 insertions(+)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a13876b..f208638 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -28,6 +28,42 @@
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/*
+ * USB
+ */
+
+/* EHCI Support - disbaled by default as
+ * there is no signal coming out of soc on
+ * this board for this controller. However,
+ * the silicon still has this controller,
+ * and anyone can use this controller by
+ * taking signals out on their board.
+ */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/* XHCI Support - enabled by default */
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
* Generic Timer Definitions
*/
#define GENERIC_TIMER_CLK 1250
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 8eaab2c..329abf7 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -46,6 +46,11 @@
#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_ENBIT(17)
+#ifdef CONFIG_LS102XA
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#endif
+
struct fsl_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
--
1.8.3.1
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Re: [U-Boot] [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support
-Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Wednesday, April 22, 2015 5:18 PM To: Mehresh Ramneek-B31383 Cc: u-boot@lists.denx.de Subject: Re: [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support On Wednesday, April 22, 2015 at 08:49:42 AM, Ramneek Mehresh wrote: Enable USB IP support for both EHCI and XHCI for ls1021atwr platform Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021atwr.h | 29 + include/linux/usb/xhci-fsl.h | 5 + 2 files changed, 34 insertions(+) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a13876b..0f59b3c 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -28,6 +28,35 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* + * USB + */ +/* EHCI Support - disbaled by default */ 'disabled' +/*#define CONFIG_HAS_FSL_DR_USB*/ Why is this disabled ? EHCI is disabled because this controller is not exposed via any connector on the board. However, the silicon still has this controller, and anyone can use this controller by taking signals out on their board. XHCI can be used on the board via micro-A usb host connector [...] Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] drivers:usb:fsl: Add XHCI driver support
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Wednesday, April 22, 2015 5:17 PM
To: Mehresh Ramneek-B31383
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH 2/4] drivers:usb:fsl: Add XHCI driver support
On Wednesday, April 22, 2015 at 08:49:41 AM, Ramneek Mehresh wrote:
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Hi!
[...]
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644 index 000..9d89313
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include usb.h
+#include asm-generic/errno.h
+/*#include asm/arch/cpu.h*/
+/*#include asm/arch/sys_proto.h*/
Remove these please .
Oops, my bad, will do
+#include linux/compat.h
+#include linux/usb/xhci-fsl.h
+#include linux/usb/dwc3.h
+#include xhci.h
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+
This will do:
agreed
__weak int board_usb_init(...)
{
return 0;
}
+inline int __board_usb_init(int index, enum usb_init_type init) {
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+ __attribute__((weak, alias(__board_usb_init)));
Drop the above, just use __weak .
+void usb_phy_reset(struct dwc3 *dwc3_reg) {
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0],
+DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg,
DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0],
+DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg,
DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) {
+ int ret = 0;
+
+ ret = dwc3_core_init(fsl_xhci-dwc3_reg);
+ if (ret) {
+ debug(%s:failed to initialize core\n, __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) {
+ /* Currently fsl socs do not support PHY shutdown from
+* sw. But this support may be added in future socs */
Multiline comment should be in this form:
Will correct
/*
* foo
* bar
*/
+ return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct
+xhci_hcor
**hcor) +{
+ struct fsl_xhci *ctx = fsl_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
+ ctx-dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE +
DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = fsl_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-
cr_capbase)));
+
+ debug(fsl-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+
+ fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h
b/include/linux/usb/xhci-fsl.h new file mode 100644 index
000..1751c7a
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */ #define FSL_XHCI_BASE 0x310
+#define FSL_OCP1_SCP_BASE 0x4a084c00 #define
FSL_OTG_WRAPPER_BASE
+0x4A02
This should be in CPU-specific file I guess, not in IP-specific one.
Agreed, let me check which file can be used for this
[...]
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Re: [U-Boot] [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support
-Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Thursday, April 23, 2015 5:26 PM To: Mehresh Ramneek-B31383 Cc: u-boot@lists.denx.de Subject: Re: [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support On Thursday, April 23, 2015 at 08:51:14 AM, Ramneek Mehresh wrote: -Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Wednesday, April 22, 2015 5:18 PM To: Mehresh Ramneek-B31383 Cc: u-boot@lists.denx.de Subject: Re: [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support On Wednesday, April 22, 2015 at 08:49:42 AM, Ramneek Mehresh wrote: Enable USB IP support for both EHCI and XHCI for ls1021atwr platform Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021atwr.h | 29 + include/linux/usb/xhci-fsl.h | 5 + 2 files changed, 34 insertions(+) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a13876b..0f59b3c 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -28,6 +28,35 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* + * USB + */ +/* EHCI Support - disbaled by default */ 'disabled' +/*#define CONFIG_HAS_FSL_DR_USB*/ Why is this disabled ? EHCI is disabled because this controller is not exposed via any connector on the board. However, the silicon still has this controller, and anyone can use this controller by taking signals out on their board. XHCI can be used on the board via micro-A usb host connector Oki, please document it a bit better. The thing you just wrote would be exactly the nice piece of documentation/comment which should be in the code. Understood, will do Thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] drivers:usb:dwc3: Add DWC3 controller driver support
Add support for DWC3 XHCI controller driver
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-dwc3.c | 75
include/linux/usb/dwc3.h | 4 +++
3 files changed, 80 insertions(+)
create mode 100644 drivers/usb/host/xhci-dwc3.c
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7658f87..c0d95cf 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
new file mode 100644
index 000..c875851
--- /dev/null
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * DWC3 controller driver
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include linux/usb/dwc3.h
+
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+ clrsetbits_le32(dwc3_reg-g_ctl,
+ DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+ DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+ /* Before Resetting PHY, put Core in Reset */
+ setbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+ /* reset USB3 phy - if required */
+ usb_phy_reset(dwc3_reg);
+
+ /* After PHYs are stable we can take Core out of reset state */
+ clrbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+ u32 reg;
+ u32 revision;
+ unsigned int dwc3_hwparams1;
+
+ revision = readl(dwc3_reg-g_snpsid);
+ /* This should read as U3 followed by revision number */
+ if ((revision DWC3_GSNPSID_MASK) != 0x5533) {
+ puts(this is not a DesignWare USB3 DRD Core\n);
+ return -1;
+ }
+
+ dwc3_core_soft_reset(dwc3_reg);
+
+ dwc3_hwparams1 = readl(dwc3_reg-g_hwparams1);
+
+ reg = readl(dwc3_reg-g_ctl);
+ reg = ~DWC3_GCTL_SCALEDOWN_MASK;
+ reg = ~DWC3_GCTL_DISSCRAMBLE;
+ switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+ case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+ reg = ~DWC3_GCTL_DSBLCLKGTNG;
+ break;
+ default:
+ debug(No power optimization available\n);
+ }
+
+ /*
+* WORKAROUND: DWC3 revisions 1.90a have a bug
+* where the device can fail to connect at SuperSpeed
+* and falls back to high-speed mode which causes
+* the device to enter a Connect/Disconnect loop
+*/
+ if ((revision DWC3_REVISION_MASK) 0x190a)
+ reg |= DWC3_GCTL_U2RSTECN;
+
+ writel(reg, dwc3_reg-g_ctl);
+
+ return 0;
+}
+
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 7edc760..c21878c 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -191,4 +191,8 @@ struct dwc3 { /*
offset: 0xC100 */
#define DWC3_DCTL_CSFTRST (1 30)
#define DWC3_DCTL_LSFTRST (1 29)
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
+int dwc3_core_init(struct dwc3 *dwc3_reg);
+void usb_phy_reset(struct dwc3 *dwc3_reg);
#endif /* __DWC3_H_ */
--
1.8.3.1
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[U-Boot] [PATCH 2/4] drivers:usb:fsl: Add XHCI driver support
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-fsl.c | 110 +++
include/linux/usb/xhci-fsl.h | 58 +++
3 files changed, 169 insertions(+)
create mode 100644 drivers/usb/host/xhci-fsl.c
create mode 100644 include/linux/usb/xhci-fsl.h
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c0d95cf..7c94439 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644
index 000..9d89313
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include usb.h
+#include asm-generic/errno.h
+/*#include asm/arch/cpu.h*/
+/*#include asm/arch/sys_proto.h*/
+#include linux/compat.h
+#include linux/usb/xhci-fsl.h
+#include linux/usb/dwc3.h
+#include xhci.h
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+
+inline int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+ __attribute__((weak, alias(__board_usb_init)));
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
+{
+ int ret = 0;
+
+ ret = dwc3_core_init(fsl_xhci-dwc3_reg);
+ if (ret) {
+ debug(%s:failed to initialize core\n, __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+ /* Currently fsl socs do not support PHY shutdown from
+* sw. But this support may be added in future socs */
+ return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
+ ctx-dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = fsl_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ debug(fsl-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+
+ fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 000..1751c7a
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */
+#define FSL_XHCI_BASE 0x310
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A02
+
+#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
+#define USB3_PHY_RX_POWERONBIT(14)
+#define USB3_PHY_TX_POWERONBIT(15
[U-Boot] [PATCH 4/4] include:configs:ls1021aqds: Enable USB IP support
Enable USB IP support for both EHCI and XHCI for ls1021aqds platform Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021aqds.h | 22 +- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5de416d..1aa2f94 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -423,19 +423,31 @@ unsigned long get_board_ddr_clk(void); /* * USB */ -#define CONFIG_HAS_FSL_DR_USB +/* EHCI Support - disbaled by default */ +/*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif -#ifdef CONFIG_USB_EHCI +/*XHCI Support - enabled by default*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_XHCI +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_CMD_EXT2 #endif -#endif /* * Video -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support
Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
include/configs/ls1021atwr.h | 29 +
include/linux/usb/xhci-fsl.h | 5 +
2 files changed, 34 insertions(+)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a13876b..0f59b3c 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -28,6 +28,35 @@
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/*
+ * USB
+ */
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
* Generic Timer Definitions
*/
#define GENERIC_TIMER_CLK 1250
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 1751c7a..dc82151 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -50,6 +50,11 @@
#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_ENBIT(17)
+#ifdef CONFIG_LS102XA
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#endif
+
struct fsl_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
--
1.8.3.1
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Re: [U-Boot] Regarding patch: http://patchwork.ozlabs.org/patch/373593/
-Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Monday, April 06, 2015 8:42 PM To: Mehresh Ramneek-B31383 Cc: u-boot; s...@denx.de Subject: Re: Regarding patch: http://patchwork.ozlabs.org/patch/373593/ On Monday, April 06, 2015 at 10:58:30 AM, Ramneek Mehresh wrote: [...] The static void fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) must shut down the controller, which I don't see happening. Why? I could not locate any such requirement in IP documentation. Have contacted local IP/PHY team for the same. Waiting for response from them This is needed, so you don't start Linux with a running USB controller. xhci controller is already stopped in usb_stop-usb_lowlevel_stop-xhci_reset(). I could see CMD_RUN bit getting reset in this function before the controller is reset. So, from your previously stated requirement, controller is halted when Linux is started. Other people are shutting down PHY as part of xhci_core_exit(), not the controller!! We would not like to re-start and re-configure PHY inside Linux, and take phy initialization inside bootloader. I got word from hw team that they do not support phy shutting down from sw. hence, we do not have any sequence for current socs to shut down phy from sw. if required, I'll put forward a request to provide this control in future socs. Hi, Is this similar hardware bug to the one which MX6 PCIe is suffering ? On MX6, the bug is that you cannot reset the PCIe and PCIe PHY from software, which means that if you start PCIe in U-Boot, you cannot reliably use it in Linux. Furthermore, if you reset the MX6 via WDT, you cannot start PCIe reliably in Linux even if PCIe is not used in U-Boot at all. Is this the same type of hardware screwup where the design team didn't think reset was necessary? I have raised request for this feature in up-coming socs, and they have agreed to provide phy shut-down in future revs. However, this support is not available in current revs for which the code is sent. What do you suggest we should do for current socs? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Regarding patch: http://patchwork.ozlabs.org/patch/373593/
-Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Tuesday, April 07, 2015 7:22 PM To: Mehresh Ramneek-B31383 Cc: u-boot; s...@denx.de Subject: Re: Regarding patch: http://patchwork.ozlabs.org/patch/373593/ On Tuesday, April 07, 2015 at 08:18:03 AM, Ramneek Mehresh wrote: [...] Hi, Is this similar hardware bug to the one which MX6 PCIe is suffering ? On MX6, the bug is that you cannot reset the PCIe and PCIe PHY from software, which means that if you start PCIe in U-Boot, you cannot reliably use it in Linux. Furthermore, if you reset the MX6 via WDT, you cannot start PCIe reliably in Linux even if PCIe is not used in U-Boot at all. Is this the same type of hardware screwup where the design team didn't think reset was necessary? I have raised request for this feature in up-coming socs, and they have agreed to provide phy shut-down in future revs. However, this support is not available in current revs for which the code is sent. What do you suggest we should do for current socs? Hi, I don't know, but doesn't leaving the USB running cause trouble to Linux? I think you should at least document the reasoning why the USB stop is not implemented for this broken hardware. Hi Marek, it's not USB controller stop, it's Phy stop which is not supported. Controller stopping is supported. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Regarding patch: http://patchwork.ozlabs.org/patch/373593/
-Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Tuesday, April 07, 2015 7:44 PM To: Mehresh Ramneek-B31383 Cc: u-boot; s...@denx.de Subject: Re: Regarding patch: http://patchwork.ozlabs.org/patch/373593/ On Tuesday, April 07, 2015 at 04:05:31 PM, Ramneek Mehresh wrote: -Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Tuesday, April 07, 2015 7:22 PM To: Mehresh Ramneek-B31383 Cc: u-boot; s...@denx.de Subject: Re: Regarding patch: http://patchwork.ozlabs.org/patch/373593/ On Tuesday, April 07, 2015 at 08:18:03 AM, Ramneek Mehresh wrote: [...] Hi, Is this similar hardware bug to the one which MX6 PCIe is suffering ? On MX6, the bug is that you cannot reset the PCIe and PCIe PHY from software, which means that if you start PCIe in U-Boot, you cannot reliably use it in Linux. Furthermore, if you reset the MX6 via WDT, you cannot start PCIe reliably in Linux even if PCIe is not used in U-Boot at all. Is this the same type of hardware screwup where the design team didn't think reset was necessary? I have raised request for this feature in up-coming socs, and they have agreed to provide phy shut-down in future revs. However, this support is not available in current revs for which the code is sent. What do you suggest we should do for current socs? Hi, I don't know, but doesn't leaving the USB running cause trouble to Linux? I think you should at least document the reasoning why the USB stop is not implemented for this broken hardware. Hi Marek, it's not USB controller stop, it's Phy stop which is not supported. Controller stopping is supported. OK, does it pose a problem for Linux ? If not, then please just document it and let's stick with what there now. No, it won't create issue in Linux because Linux usb driver resets the controller (which in turn resets the phy). Please suggest what's the best place to document this. Shall I document this inside some u-boot doc file? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Regarding patch: http://patchwork.ozlabs.org/patch/373593/
-Original Message- From: Mehresh Ramneek-B31383 Sent: Tuesday, April 07, 2015 8:12 PM To: 'Marek Vasut' Cc: u-boot; s...@denx.de Subject: RE: Regarding patch: http://patchwork.ozlabs.org/patch/373593/ -Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Tuesday, April 07, 2015 7:44 PM To: Mehresh Ramneek-B31383 Cc: u-boot; s...@denx.de Subject: Re: Regarding patch: http://patchwork.ozlabs.org/patch/373593/ On Tuesday, April 07, 2015 at 04:05:31 PM, Ramneek Mehresh wrote: -Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Tuesday, April 07, 2015 7:22 PM To: Mehresh Ramneek-B31383 Cc: u-boot; s...@denx.de Subject: Re: Regarding patch: http://patchwork.ozlabs.org/patch/373593/ On Tuesday, April 07, 2015 at 08:18:03 AM, Ramneek Mehresh wrote: [...] Hi, Is this similar hardware bug to the one which MX6 PCIe is suffering ? On MX6, the bug is that you cannot reset the PCIe and PCIe PHY from software, which means that if you start PCIe in U-Boot, you cannot reliably use it in Linux. Furthermore, if you reset the MX6 via WDT, you cannot start PCIe reliably in Linux even if PCIe is not used in U-Boot at all. Is this the same type of hardware screwup where the design team didn't think reset was necessary? I have raised request for this feature in up-coming socs, and they have agreed to provide phy shut-down in future revs. However, this support is not available in current revs for which the code is sent. What do you suggest we should do for current socs? Hi, I don't know, but doesn't leaving the USB running cause trouble to Linux? I think you should at least document the reasoning why the USB stop is not implemented for this broken hardware. Hi Marek, it's not USB controller stop, it's Phy stop which is not supported. Controller stopping is supported. OK, does it pose a problem for Linux ? If not, then please just document it and let's stick with what there now. No, it won't create issue in Linux because Linux usb driver resets the controller (which in turn resets the phy). Please suggest what's the best place to document this. Shall I document this inside some u-boot doc file? I can document this inside xhci_stop() part of fsl driver. In addition, this will also be documented in FSL USB driver documentation. Please tell if this is ok. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Regarding patch: http://patchwork.ozlabs.org/patch/373593/
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Monday, January 12, 2015 8:00 PM
To: Mehresh Ramneek-B31383
Cc: u-boot
Subject: Re: Regarding patch: http://patchwork.ozlabs.org/patch/373593/
On Monday, January 12, 2015 at 06:26:24 AM, Ramneek Mehresh wrote:
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Thursday, December 18, 2014 4:46 PM
To: u-boot
Cc: Mehresh Ramneek-B31383
Subject: Re: Regarding patch:
http://patchwork.ozlabs.org/patch/373593/
On Thursday, December 18, 2014 at 09:32:56 AM, Ramneek Mehresh
wrote:
Hi Marex,
Following u-boot patch is pending for your review for some time.
Please let me know if you have any concerns. fsl/usb: Add USB XHCI
support:
http://patchwork.ozlabs.org/patch/373593/
I missed the patch completely, sorry. Next time, please keep me on
CC when submitting the patches, that helps a lot.
As for the board_usb_init, you can drop the inline and the
__board_usb_init() and do:
__weak int board_usb_init(int index, enum usb_init_type init) {
return 0;
}
Will do
The static void fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) must
shut down the controller, which I don't see happening. Why?
I could not locate any such requirement in IP documentation. Have
contacted local IP/PHY team for the same. Waiting for response from
them
This is needed, so you don't start Linux with a running USB controller.
xhci controller is already stopped in
usb_stop-usb_lowlevel_stop-xhci_reset().
I could see CMD_RUN bit getting reset in this function before the controller is
reset.
So, from your previously stated requirement, controller is halted when Linux is
started.
Other people are shutting down PHY as part of xhci_core_exit(), not the
controller!!
We would not like to re-start and re-configure PHY inside Linux, and take phy
initialization
inside bootloader. I got word from hw team that they do not support phy
shutting down from sw. hence, we do not have any sequence for current socs to
shut down phy from sw. if required, I'll put forward a request to provide
this control in future socs.
Thanks!
Best regards,
Marek Vasut
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Re: [U-Boot] Regarding USB device testing in U-boot release
Hi Marek, Thanks for the reply. Yes, we are seeing USB 3.0 pen drives from different vendors taking different times to give connect-change on latest u-boot. Out of all, HP pen drive is taking most of the time. Would it be possible for you to send the list of devices that you normally test? We just want to cross-verify if any of the same device tested on out platform is not giving any issue. Thanks and Regards, Ramneek -Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Tuesday, February 24, 2015 11:09 PM To: Mehresh Ramneek-B31383 Cc: u-boot@lists.denx.de Subject: Re: Regarding USB device testing in U-boot release On Tuesday, February 24, 2015 at 06:59:40 AM, Ramneek Mehresh wrote: Hi Marex, Hi, please keep the list on CC (fixed). Could you please confirm if some USB devices are tested before each U-boot release by Denx? If yes, then I would request you to please share the list of these devices? I do my testing with a couple of USB 2.0/USB 3.0 sticks on Altera SoCFPGA Cyclone V and newly also Arria V. I also do some testing on iMX28, 53 and 6 platforms from Freescale. The rest of the testing is up to the community. In my experience, in case there's a regression in the USB stack, someone starts complaining about it sooner rather than later. Do you have any particular device which is broken ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ls1:config: Add USB support for ls1021atwr
-Original Message- From: Sun York-R58495 Sent: Thursday, January 15, 2015 12:16 AM To: Mehresh Ramneek-B31383; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH] ls1:config: Add USB support for ls1021atwr On 12/17/2014 03:08 PM, York Sun wrote: On 10/21/2014 04:36 AM, Ramneek Mehresh wrote: Add USB EHCI/XHCI support for ls1021atwr platform and making xHCI as default mode Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021atwr.h | 28 1 file changed, 28 insertions(+) Please verify this patch on the latest u-boot. I saw compiling errors. Please fix. This patch cause compiling errors on all ls1021atwr boards. If this patch depends on other patches, please put into comment so I can apply them in order. Hi York, this patch depends on http://patchwork.ozlabs.org/patch/373593/ which is under review, and has comments from Marex. For this patch, we have dependency on IP team, and that's taking lot of time +drivers/usb/host/built-in.o: In function `usb_lowlevel_init': +drivers/usb/host/xhci.c:948: undefined reference to `xhci_hcd_init' +drivers/usb/host/built-in.o: In function `usb_lowlevel_stop': +drivers/usb/host/xhci.c:1025: undefined reference to `xhci_hcd_stop' +arm-linux-gnueabi-ld.bfd: BFD (GNU Binutils for Ubuntu) 2.22 assertion +fail ../../bfd/elf32-arm.c:7498 +arm-linux-gnueabi-ld.bfd: BFD (GNU Binutils for Ubuntu) 2.22 assertion +fail ../../bfd/elf32-arm.c:13830 +make[1]: *** [u-boot] Error 139 +make: *** [sub-make] Error 2 York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Regarding patch: http://patchwork.ozlabs.org/patch/373593/
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Thursday, December 18, 2014 4:46 PM
To: u-boot
Cc: Mehresh Ramneek-B31383
Subject: Re: Regarding patch: http://patchwork.ozlabs.org/patch/373593/
On Thursday, December 18, 2014 at 09:32:56 AM, Ramneek Mehresh wrote:
Hi Marex,
Following u-boot patch is pending for your review for some time.
Please let me know if you have any concerns. fsl/usb: Add USB XHCI
support:
http://patchwork.ozlabs.org/patch/373593/
I missed the patch completely, sorry. Next time, please keep me on CC when
submitting the patches, that helps a lot.
As for the board_usb_init, you can drop the inline and the
__board_usb_init() and do:
__weak int board_usb_init(int index, enum usb_init_type init) {
return 0;
}
Will do
The static void fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) must shut down
the controller, which I don't see happening. Why?
I could not locate any such requirement in IP documentation. Have contacted
local
IP/PHY team for the same. Waiting for response from them
- Ramneek
Thanks!
Best regards,
Marek Vasut
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[U-Boot] [PATCH] ls1:config: Add USB support for ls1021atwr
Add USB EHCI/XHCI support for ls1021atwr platform and making xHCI as default mode Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021atwr.h | 28 1 file changed, 28 insertions(+) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 45b2272..109e58c 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -28,6 +28,34 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* + * USB + */ +/*EHCI Support*/ +/*#define CONFIG_HAS_FSL_DR_USB*/ + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + +/*XHCI Support*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 1 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + +/* * Generic Timer Definitions */ #define GENERIC_TIMER_CLK 1250 -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ls1:config: Add XHCI support for ls1021aqds
Add USB XHCI support for ls1021aqds platform and making this as default mode Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021aqds.h | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index fd43a3e..c6f83b2 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -275,19 +275,30 @@ unsigned long get_board_ddr_clk(void); /* * USB */ -#define CONFIG_HAS_FSL_DR_USB +/*EHCI Support*/ +/*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif -#ifdef CONFIG_USB_EHCI +/*XHCI Support*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 1 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_CMD_EXT2 #endif -#endif /* * eTSEC -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] 85xx/b4:Correct USB DR controller liodn entry
LIODN entry for B4860/B4420 mentions USB controller as mph
insread of dr. This results in PAMU not permitting bus
transactions for USB DR controller on B4860 resulting in
USB function failure. Replacing fsl-usb2-mph with
fsl-usb2-dr allows USB DR controller bus transactions
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Reviewed-by: Sethi Varun-B16395 varun.se...@freescale.com
Reviewed-by: Sun Yusong-R58495 york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/b4860_ids.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 39b8e3e..1a30f1c 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -55,7 +55,7 @@ struct liodn_id_table liodn_tbl[] = {
SET_SDHC_LIODN(1, 552),
- SET_USB_LIODN(1, fsl-usb2-mph, 553),
+ SET_USB_LIODN(1, fsl-usb2-dr, 553),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
--
1.8.3.1
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[U-Boot] [PATCH] powerpc/8xxx: Fix in USB device-tree fixup
Fix following issues in USB device-tree fixup:
- returns when either dr_mode or phy_type not defined.
This was terminating fix-up when only either property
was defined in hwconfig string
- updates dr_mode_type or dr_phy_type with junk value when
their index is -1. Now these are updated only when their
respective index is pointing to relevant types
in modes[] and phys[] array
- dr_mode_type and dr_phy_type were not NULL for
each controller
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/fdt.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 9273745..4cec5e1 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2009-2014 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -123,14 +123,14 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
const char *modes[] = { host, peripheral, otg };
const char *phys[] = { ulpi, utmi };
- const char *dr_mode_type = NULL;
- const char *dr_phy_type = NULL;
int usb_mode_off = -1;
int usb_phy_off = -1;
char str[5];
int i, j;
for (i = 1; i = CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+ const char *dr_mode_type = NULL;
+ const char *dr_phy_type = NULL;
int mode_idx = -1, phy_idx = -1;
snprintf(str, 5, %s%d, usb, i);
if (hwconfig(str)) {
@@ -150,18 +150,16 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
}
}
- if (mode_idx 0 || phy_idx 0) {
- puts(ERROR: wrong usb mode/phy defined!!\n);
- return;
- }
-
- dr_mode_type = modes[mode_idx];
- dr_phy_type = phys[phy_idx];
-
if (mode_idx 0 phy_idx 0) {
printf(WARNING: invalid phy or mode\n);
return;
}
+
+ if (mode_idx -1)
+ dr_mode_type = modes[mode_idx];
+
+ if (phy_idx -1)
+ dr_phy_type = phys[phy_idx];
}
usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
--
1.8.3.1
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[U-Boot] [PATCH] fsl/usb: Add USB XHCI support
Add USB XHCI stack support for USB2.0/USB3.0 devices
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-fsl.c | 147 +++
include/linux/usb/xhci-fsl.h | 48 ++
3 files changed, 196 insertions(+)
create mode 100644 drivers/usb/host/xhci-fsl.c
create mode 100644 include/linux/usb/xhci-fsl.h
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 04c1a64..388d13a 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -23,6 +23,7 @@ ifdef CONFIG_MPC512X
obj-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
else
obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
endif
obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644
index 000..381c322
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,147 @@
+/*
+ * FSL USB HOST xHCI Controller
+ *
+ * (C) Copyright 2014
+ * Freescale Semiconductor, www.freescale.com
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include usb.h
+#include asm-generic/errno.h
+#include linux/compat.h
+#include linux/usb/dwc3.h
+#include linux/usb/xhci-fsl.h
+#include xhci.h
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+
+inline int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+int board_usb_init(int index, enum usb_init_type init)
+ __attribute__((weak, alias(__board_usb_init)));
+
+static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+ clrsetbits_le32(dwc3_reg-g_ctl,
+ DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+ DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+ /* Before Resetting PHY, put Core in Reset */
+ setbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+ /* After PHYs are stable we can take Core out of reset state */
+ clrbits_le32(dwc3_reg-g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+static int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+ u32 reg;
+ u32 revision;
+ unsigned int dwc3_hwparams1;
+
+ revision = readl(dwc3_reg-g_snpsid);
+ /* This should read as U3 followed by revision number */
+ if ((revision DWC3_GSNPSID_MASK) != 0x5533) {
+ puts(this is not a DesignWare USB3 DRD Core\n);
+ return -1;
+ }
+
+ dwc3_core_soft_reset(dwc3_reg);
+
+ dwc3_hwparams1 = readl(dwc3_reg-g_hwparams1);
+
+ reg = readl(dwc3_reg-g_ctl);
+ reg = ~DWC3_GCTL_SCALEDOWN_MASK;
+ reg = ~DWC3_GCTL_DISSCRAMBLE;
+ switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+ case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+ reg = ~DWC3_GCTL_DSBLCLKGTNG;
+ break;
+ default:
+ debug(No power optimization available\n);
+ }
+
+ /*
+* WORKAROUND: DWC3 revisions 1.90a have a bug
+* where the device can fail to connect at SuperSpeed
+* and falls back to high-speed mode which causes
+* the device to enter a Connect/Disconnect loop
+*/
+ if ((revision DWC3_REVISION_MASK) 0x190a)
+ reg |= DWC3_GCTL_U2RSTECN;
+
+ writel(reg, dwc3_reg-g_ctl);
+
+ return 0;
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
+{
+ int ret = 0;
+
+ ret = dwc3_core_init(fsl_xhci-dwc3_reg);
+ if (ret) {
+ debug(%s:failed to initialize core\n, __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static void fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+ return;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
+ ctx-dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = fsl_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ debug(fsl-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t
[U-Boot] [PATCH] 85xx/p1020:Define no. of usb controllers used on P1020RDB-PD platform
Define number of USB controllers used on P1020RDB-PD platform. This platform has P1020 SoC which has two USB controllers, but only first one is used on the platform Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ include/configs/p1_p2_rdb_pc.h| 4 2 files changed, 6 insertions(+) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 864e74c..27c8039 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -247,7 +247,9 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT2 +#endif #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS2 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e745945..bf00fba 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -883,6 +883,10 @@ #endif #endif +#if defined(CONFIG_P1020RDB_PD) +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 +#endif + #define CONFIG_MMC #ifdef CONFIG_MMC -- 1.8.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/83xx: Define USB1 and USB2 base addr for MPC834x
Define base addresse for both MPH(USB1) and DR(USB2) controllers
for MPC834x socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/include/asm/immap_83xx.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/immap_83xx.h
b/arch/powerpc/include/asm/immap_83xx.h
index 3c86ff6..289f7ca 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -763,6 +763,7 @@ typedef struct immap {
u8 res7[0xC];
} immap_t;
+#ifndefCONFIG_MPC834x
#ifdef CONFIG_HAS_FSL_MPH_USB
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000/* use the MPH
controller */
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
@@ -770,6 +771,10 @@ typedef struct immap {
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000/* use the DR
controller */
#endif
+#else
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
+#endif
#elif defined(CONFIG_MPC8313)
typedef struct immap {
--
1.7.11.7
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2][v3]powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs
CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
initializing all USB controllers on a given platform. This
macro is defined for all 85xx socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Change for v3:
- corrected macro mistake in fdt.c file
ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
-- ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
arch/powerpc/cpu/mpc8xxx/fdt.c| 6 --
arch/powerpc/include/asm/config_mpc85xx.h | 26 +-
2 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index eb7cbbc..9273745 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -15,7 +15,9 @@
#include phy.h
#include hwconfig.h
-#define FSL_MAX_NUM_USB_CTRLS 2
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#endif
#if defined(CONFIG_MP) (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -128,7 +130,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
char str[5];
int i, j;
- for (i = 1; i = FSL_MAX_NUM_USB_CTRLS; i++) {
+ for (i = 1; i = CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
int mode_idx = -1, phy_idx = -1;
snprintf(str, 5, %s%d, usb, i);
if (hwconfig(str)) {
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 946ea97..4cc12ee 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -133,6 +133,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2
@@ -153,6 +154,7 @@
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -162,6 +164,7 @@
#elif defined(CONFIG_P1012)
#define CONFIG_MAX_CPUS1
#define CONFIG_SYS_FSL_NUM_LAWS12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -178,6 +181,7 @@
#elif defined(CONFIG_P1013)
#define CONFIG_MAX_CPUS1
#define CONFIG_SYS_FSL_NUM_LAWS12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -196,6 +200,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
@@ -210,6 +215,7 @@
#define CONFIG_SYS_NUM_FMAN1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_QMAN_NUM_PORTALS3
#define CONFIG_SYS_BMAN_NUM_PORTALS3
#define CONFIG_SYS_FM_MURAM_SIZE 0x1
@@ -228,6 +234,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS2
@@ -243,6 +250,7 @@
#define MAX_QE_RISC1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#elif defined(CONFIG_P1022)
#define CONFIG_MAX_CPUS2
@@ -250,6 +258,7 @@
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -263,6 +272,7 @@
#define CONFIG_SYS_NUM_FMAN1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_QMAN_NUM_PORTALS3
#define CONFIG_SYS_BMAN_NUM_PORTALS3
#define CONFIG_SYS_FM_MURAM_SIZE 0x1
@@ -280,6 +290,7 @@
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
[U-Boot] [PATCH 1/2][v2]powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs
CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
initializing all USB controllers on a given platform. This
macro is defined for all 85xx socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v2: rebased on u-boot-mpc85xx-next
arch/powerpc/cpu/mpc8xxx/fdt.c| 6 --
arch/powerpc/include/asm/config_mpc85xx.h | 26 +-
2 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index eb7cbbc..ceab92f 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -15,7 +15,9 @@
#include phy.h
#include hwconfig.h
-#define FSL_MAX_NUM_USB_CTRLS 2
+#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#endif
#if defined(CONFIG_MP) (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -128,7 +130,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
char str[5];
int i, j;
- for (i = 1; i = FSL_MAX_NUM_USB_CTRLS; i++) {
+ for (i = 1; i = CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
int mode_idx = -1, phy_idx = -1;
snprintf(str, 5, %s%d, usb, i);
if (hwconfig(str)) {
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 946ea97..4cc12ee 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -133,6 +133,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2
@@ -153,6 +154,7 @@
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -162,6 +164,7 @@
#elif defined(CONFIG_P1012)
#define CONFIG_MAX_CPUS1
#define CONFIG_SYS_FSL_NUM_LAWS12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -178,6 +181,7 @@
#elif defined(CONFIG_P1013)
#define CONFIG_MAX_CPUS1
#define CONFIG_SYS_FSL_NUM_LAWS12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -196,6 +200,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
@@ -210,6 +215,7 @@
#define CONFIG_SYS_NUM_FMAN1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_QMAN_NUM_PORTALS3
#define CONFIG_SYS_BMAN_NUM_PORTALS3
#define CONFIG_SYS_FM_MURAM_SIZE 0x1
@@ -228,6 +234,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS2
@@ -243,6 +250,7 @@
#define MAX_QE_RISC1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#elif defined(CONFIG_P1022)
#define CONFIG_MAX_CPUS2
@@ -250,6 +258,7 @@
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -263,6 +272,7 @@
#define CONFIG_SYS_NUM_FMAN1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_QMAN_NUM_PORTALS3
#define CONFIG_SYS_BMAN_NUM_PORTALS3
#define CONFIG_SYS_FM_MURAM_SIZE 0x1
@@ -280,6 +290,7 @@
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -289,6 +300,7 @@
#elif defined
[U-Boot] [PATCH 2/2] powerpc/usb:Differentiate USB controller base address
Introduce different macros for storing addresses of multiple
USB controllers. This is required for successful initialization
and usage of multiple USB controllers inside u-boot
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 +-
arch/powerpc/include/asm/immap_512x.h | 6 +++---
arch/powerpc/include/asm/immap_83xx.h | 18 --
arch/powerpc/include/asm/immap_85xx.h | 9 +
drivers/usb/host/ehci-fsl.c | 15 +--
drivers/usb/host/ehci-mpc512x.c | 4 ++--
include/usb/ehci-fsl.h| 13 ++---
7 files changed, 46 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c
b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index d568f88..d9b6e47 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -315,7 +315,7 @@ void cpu_init_f (volatile immap_t * im)
#endif
#if defined(CONFIG_USB_EHCI_FSL) defined(CONFIG_MPC831x)
uint32_t temp;
- struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
+ struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
/* Configure interface. */
setbits_be32(ehci-control, REFSEL_16MHZ | UTMI_PHY_EN);
diff --git a/arch/powerpc/include/asm/immap_512x.h
b/arch/powerpc/include/asm/immap_512x.h
index 01c9eff..dc655aa 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -1255,9 +1255,9 @@ static inline u32 get_pata_base (void)
}
#endif /* __ASSEMBLY__ */
-#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000
-#define CONFIG_SYS_MPC512x_USB_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET)
+#define CONFIG_SYS_MPC512x_USB1_OFFSET 0x4000
+#define CONFIG_SYS_MPC512x_USB1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET)
#define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim))
diff --git a/arch/powerpc/include/asm/immap_83xx.h
b/arch/powerpc/include/asm/immap_83xx.h
index 57189c9..3c86ff6 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -764,9 +764,11 @@ typedef struct immap {
} immap_t;
#ifdef CONFIG_HAS_FSL_MPH_USB
-#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000/* use the MPH
controller */
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
#else
-#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000/* use the DR
controller */
#endif
#elif defined(CONFIG_MPC8313)
@@ -1031,11 +1033,15 @@ typedef struct immap {
#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
-#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
-#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
+#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000
+#endif
+#define CONFIG_SYS_MPC83xx_USB1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
+#if defined(CONFIG_MPC834x)
+#define CONFIG_SYS_MPC83xx_USB2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
#endif
-#define CONFIG_SYS_MPC83xx_USB_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
#define CONFIG_SYS_LBC_ADDR (((immap_t *)CONFIG_SYS_IMMR)-im_lbc)
#define CONFIG_SYS_TSEC1_OFFSET0x24000
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 3a10d77..147ce4f 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2938,7 +2938,6 @@ struct ccsr_pman {
#endif
#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x21
#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
-#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET0x22
@@ -2991,7 +2990,7 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x2
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
-#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
#ifdef CONFIG_TSECV2
#define CONFIG_SYS_TSEC1_OFFSET0xB
@@ -3092,8 +3091,10 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET
[U-Boot] [PATCH 1/2] powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs
CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
initializing all USB controllers on a given platform. This
macro is defined for all 85xx socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/fdt.c| 6 --
arch/powerpc/include/asm/config_mpc85xx.h | 24
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index eb7cbbc..9273745 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -15,7 +15,9 @@
#include phy.h
#include hwconfig.h
-#define FSL_MAX_NUM_USB_CTRLS 2
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#endif
#if defined(CONFIG_MP) (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -128,7 +130,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
char str[5];
int i, j;
- for (i = 1; i = FSL_MAX_NUM_USB_CTRLS; i++) {
+ for (i = 1; i = CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
int mode_idx = -1, phy_idx = -1;
snprintf(str, 5, %s%d, usb, i);
if (hwconfig(str)) {
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 15e44de..b395e1c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -127,6 +127,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2
@@ -146,6 +147,7 @@
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -154,6 +156,7 @@
#elif defined(CONFIG_P1012)
#define CONFIG_MAX_CPUS1
#define CONFIG_SYS_FSL_NUM_LAWS12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -169,6 +172,7 @@
#elif defined(CONFIG_P1013)
#define CONFIG_MAX_CPUS1
#define CONFIG_SYS_FSL_NUM_LAWS12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -186,6 +190,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
@@ -200,6 +205,7 @@
#define CONFIG_SYS_NUM_FMAN1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_QMAN_NUM_PORTALS3
#define CONFIG_SYS_BMAN_NUM_PORTALS3
#define CONFIG_SYS_FM_MURAM_SIZE 0x1
@@ -216,6 +222,7 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS2
@@ -230,6 +237,7 @@
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#elif defined(CONFIG_P1022)
#define CONFIG_MAX_CPUS2
@@ -237,6 +245,7 @@
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -249,6 +258,7 @@
#define CONFIG_SYS_NUM_FMAN1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#define CONFIG_SYS_QMAN_NUM_PORTALS3
#define CONFIG_SYS_BMAN_NUM_PORTALS3
#define CONFIG_SYS_FM_MURAM_SIZE 0x1
@@ -265,6 +275,7 @@
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -273,6 +284,7 @@
#elif defined(CONFIG_P1025)
#define
[U-Boot] [PATCH 0/2]powerpc/usb:Intergrate multiple USB controller support
Make multiple USB controllers work inside u-boot by doing the following: - Defining max. no of USB controllers for each soc - Defining proper base address for each controller so that initialization code can work for each of them Ramneek Mehresh (2): powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs powerpc/usb:Differentiate USB controller base address arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc8xxx/fdt.c| 6 -- arch/powerpc/include/asm/config_mpc85xx.h | 24 arch/powerpc/include/asm/immap_512x.h | 6 +++--- arch/powerpc/include/asm/immap_83xx.h | 18 -- arch/powerpc/include/asm/immap_85xx.h | 9 + drivers/usb/host/ehci-fsl.c | 15 +-- drivers/usb/host/ehci-mpc512x.c | 4 ++-- include/usb/ehci-fsl.h| 13 ++--- 9 files changed, 74 insertions(+), 23 deletions(-) -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/usb: Mention usb1 before usb2 inside default hwconfig string
For USB device-tree fix-up to work properly, its necessary to mention USB1 options before that of USB2 inside default hwconfig string Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/corenet_ds.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c3fb80c..1ccefb0 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -700,8 +700,8 @@ #defineCONFIG_EXTRA_ENV_SETTINGS \ hwconfig=fsl_ddr:ctlr_intlv=cacheline,\ bank_intlv=cs0_cs1; \ - usb2:dr_mode=peripheral,phy_type= __stringify(__USB_PHY_TYPE) ;\ - usb1:dr_mode=host,phy_type= __stringify(__USB_PHY_TYPE) \0\ + usb1:dr_mode=host,phy_type= __stringify(__USB_PHY_TYPE) ;\ + usb2:dr_mode=peripheral,phy_type= __stringify(__USB_PHY_TYPE) \0\ netdev=eth0\0 \ uboot= __stringify(CONFIG_UBOOTPATH) \0 \ ubootaddr= __stringify(CONFIG_SYS_TEXT_BASE) \0 \ -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH]fsl/usb: Move USB internal phy definitions to fsl_usb.h
fsl_usb.h file created to share data bewteen usb platform code
and usb ip driver. Internal phy structure definitions moved to
this file
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Applies on git://git.denx.de/u-boot.git
(branch master)
arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +--
arch/powerpc/include/asm/immap_85xx.h | 48 -
include/fsl_usb.h | 80 +++
3 files changed, 84 insertions(+), 51 deletions(-)
create mode 100644 include/fsl_usb.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 25beda2..5aa09c1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -22,6 +22,7 @@
#include asm/fsl_law.h
#include asm/fsl_serdes.h
#include asm/fsl_srio.h
+#include fsl_usb.h
#include hwconfig.h
#include linux/compiler.h
#include mp.h
@@ -595,7 +596,7 @@ skip_l2:
#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
{
- ccsr_usb_phy_t *usb_phy1 =
+ struct ccsr_usb_phy __iomem *usb_phy1 =
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
out_be32(usb_phy1-usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
@@ -603,7 +604,7 @@ skip_l2:
#endif
#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
{
- ccsr_usb_phy_t *usb_phy2 =
+ struct ccsr_usb_phy __iomem *usb_phy2 =
(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
out_be32(usb_phy2-usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
@@ -625,7 +626,7 @@ skip_l2:
#endif
#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
- ccsr_usb_phy_t *usb_phy =
+ struct ccsr_usb_phy __iomem *usb_phy =
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
setbits_be32(usb_phy-pllprg[1],
CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 81b3322..3bc0708 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2811,54 +2811,6 @@ typedef struct ccsr_pme {
u8 res4[0x400];
} ccsr_pme_t;
-#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-struct ccsr_usb_port_ctrl {
- u32 ctrl;
- u32 drvvbuscfg;
- u32 pwrfltcfg;
- u32 sts;
- u8 res_14[0xc];
- u32 bistcfg;
- u32 biststs;
- u32 abistcfg;
- u32 abiststs;
- u8 res_30[0x10];
- u32 xcvrprg;
- u32 anaprg;
- u32 anadrv;
- u32 anasts;
-};
-
-typedef struct ccsr_usb_phy {
- u32 id;
- struct ccsr_usb_port_ctrl port1;
- u8 res_50[0xc];
- u32 tvr;
- u32 pllprg[4];
- u8 res_70[0x4];
- u32 anaccfg;
- u32 dbg;
- u8 res_7c[0x4];
- struct ccsr_usb_port_ctrl port2;
- u8 res_dc[0x334];
-} ccsr_usb_phy_t;
-
-#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 0)
-#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 1)
-#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 0)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 16)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 21)
-#else
-typedef struct ccsr_usb_phy {
- u8 res0[0x18];
- u32 usb_enable_override;
- u8 res[0xe4];
-} ccsr_usb_phy_t;
-#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
-#endif
-
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
struct ccsr_raide {
u8 res0[0x543];
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
new file mode 100644
index 000..88d6a1f
--- /dev/null
+++ b/include/fsl_usb.h
@@ -0,0 +1,80 @@
+/*
+ * Freescale USB Controller
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_FSL_USB_H_
+#define _ASM_FSL_USB_H_
+
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+struct ccsr_usb_port_ctrl {
+ u32 ctrl
[U-Boot] [PATCH] powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variables
Remove getting values of usb mode and phy_type from usb_dr_mode
and usb_phy_type uboot env variables. Now, these are determined
only from hwconfig string
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/fdt.c | 22 --
1 file changed, 22 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 89966e0..eb7cbbc 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -121,11 +121,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
const char *modes[] = { host, peripheral, otg };
const char *phys[] = { ulpi, utmi };
- const char *mode = NULL;
- const char *phy_type = NULL;
const char *dr_mode_type = NULL;
const char *dr_phy_type = NULL;
- char usb1_defined = 0;
int usb_mode_off = -1;
int usb_phy_off = -1;
char str[5];
@@ -159,12 +156,6 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
dr_mode_type = modes[mode_idx];
dr_phy_type = phys[phy_idx];
- /* use usb_dr_mode and usb_phy_type if
- usb1_defined = 0; these variables are to
- be deprecated */
- if (!strcmp(str, usb1))
- usb1_defined = 1;
-
if (mode_idx 0 phy_idx 0) {
printf(WARNING: invalid phy or mode\n);
return;
@@ -183,19 +174,6 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
if (usb_phy_off 0)
return;
}
-
- if (!usb1_defined) {
- int usb_off = -1;
- mode = getenv(usb_dr_mode);
- phy_type = getenv(usb_phy_type);
- if (mode || phy_type) {
- printf(WARNING: usb_dr_mode and usb_phy_type
- are to be deprecated soon. Use
- hwconfig to set these values instead!!\n);
- fdt_fixup_usb_mode_phy_type(blob, mode,
- phy_type, usb_off);
- }
- }
}
#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
--
1.7.11.7
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2]powerpc/usb: Workaround for erratum-A006918
Erratum-A006918 prevents internal UTMI dual phy pll inside T4240
rev 1.0 from starting sometimes. Workaround involves restarting
phy pll maximum seven times with 1ms delay in each loop
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Suresh Gupta suresh.gu...@freescale.com
---
Applies on git://git.denx.de/u-boot.git
(branch master)
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 55 +++
arch/powerpc/include/asm/config_mpc85xx.h | 1 +
include/fsl_usb.h | 7
4 files changed, 67 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 5cd02cc..779b352 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -195,6 +195,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
puts(Work-around for Erratum DDR111 enabled\n);
puts(Work-around for Erratum DDR134 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006918
+ if (IS_SVR_REV(svr, 1, 0))
+ puts(Work-around for Erratum A006918 enabled\n);
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
puts(Work-around for Erratum IFC-A002769 enabled\n);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 5aa09c1..6024768 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -35,6 +35,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006918
+bool has_fsl_erratum_a006918;
+#endif
+
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -211,6 +215,47 @@ static void corenet_tb_init(void)
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006918
+void fsl_erratum_a006918_workaround(void)
+{
+ unsigned int cnt = FSL_MAX_USBPLL_RETRY_COUNT;
+ struct ccsr_usb_phy *usb_phy =
+ (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+
+ has_fsl_erratum_a006918 = true;
+
+ do {
+ /* 1ms delay required for PLL to be stable */
+ mdelay(1);
+ if ((in_be32(usb_phy-port1.sts)
+ CONFIG_SYS_FSL_USB_SYS_CLK_VALID)
+ (in_be32(usb_phy-port2.sts)
+ CONFIG_SYS_FSL_USB_SYS_CLK_VALID)) {
+ has_fsl_erratum_a006918 = false;
+ break;
+ } else {
+ clrsetbits_be32(usb_phy-pllprg[1],
+ CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN,
+ CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
+ CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
+ CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN |
+ CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV |
+ CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+ setbits_be32(usb_phy-pllprg[1],
+CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
+CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
+CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN |
+CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV |
+CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
+CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+ }
+ } while (--cnt);
+
+ if (has_fsl_erratum_a006918)
+ printf(ERROR:fsl internal utmi phy init failed\n);
+}
+#endif
+
void cpu_init_f (void)
{
extern void m8560_cpm_reset (void);
@@ -628,6 +673,8 @@ skip_l2:
#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
struct ccsr_usb_phy __iomem *usb_phy =
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+ setbits_be32(usb_phy-pllprg[0],
+CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV);
setbits_be32(usb_phy-pllprg[1],
CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
@@ -645,6 +692,14 @@ skip_l2:
CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
setbits_be32(usb_phy-port2.pwrfltcfg,
CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+
+ /* Deal with USB Erratum USB-A006918
+* UTMI phy clk instability issue
+*/
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006918
+ if (IS_SVR_REV(svr, 1, 0))
+ fsl_erratum_a006918_workaround();
+#endif
#endif
#ifdef CONFIG_FMAN_ENET
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 7ed93ac..f7926ef 100644
--- a/arch/powerpc
[U-Boot] [PATCH 2/2]powerpc/fdt: Modify USB device-tree fixup for erratum-A006918
Erratum-A006918 prevents internal UTMI phy pll from starting
sometimes. Workaround involves restarting phy pll maximum seven
times with 1ms delay in each loop. If pll still fails to start
after max retries, status property is set to fail-erratum-a006918
to stop kernel from using this device
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Applies on git://git.denx.de/u-boot.git
(branch master)
arch/powerpc/cpu/mpc8xxx/fdt.c | 91 ++
1 file changed, 74 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index eb7cbbc..0661d70 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -12,6 +12,7 @@
#include fdt_support.h
#include asm/mp.h
#include asm/fsl_serdes.h
+#include fsl_usb.h
#include phy.h
#include hwconfig.h
@@ -72,57 +73,103 @@ void ft_fixup_num_cores(void *blob) {
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
- const char *phy_type, int start_offset)
+static const char *fdt_usb_get_node_type(void *blob, int start_offset,
+ int *node_offset)
{
const char *compat_dr = fsl-usb2-dr;
const char *compat_mph = fsl-usb2-mph;
- const char *prop_mode = dr_mode;
- const char *prop_type = phy_type;
const char *node_type = NULL;
- int node_offset;
- int err;
- node_offset = fdt_node_offset_by_compatible(blob,
+ *node_offset = fdt_node_offset_by_compatible(blob,
start_offset, compat_mph);
- if (node_offset 0) {
- node_offset = fdt_node_offset_by_compatible(blob,
+ if (*node_offset 0) {
+ *node_offset = fdt_node_offset_by_compatible(blob,
start_offset, compat_dr);
- if (node_offset 0) {
- printf(WARNING: could not find compatible
+ if (*node_offset 0) {
+ printf(ERROR: could not find compatible
node %s or %s: %s.\n, compat_mph,
- compat_dr, fdt_strerror(node_offset));
+ compat_dr, fdt_strerror(*node_offset));
return -1;
- } else
+ } else {
node_type = compat_dr;
- } else
+ }
+ } else {
node_type = compat_mph;
+ }
+
+ return node_type;
+}
+
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+ const char *phy_type, int start_offset)
+{
+ const char *prop_mode = dr_mode;
+ const char *prop_type = phy_type;
+ const char *node_type = NULL;
+ int node_offset;
+ int err;
+
+ node_type = fdt_usb_get_node_type(blob, start_offset, node_offset);
+ if (node_offset 0)
+ return -1;
if (mode) {
err = fdt_setprop(blob, node_offset, prop_mode, mode,
strlen(mode) + 1);
- if (err 0)
- printf(WARNING: could not set %s for %s: %s.\n,
+
+ if (err 0) {
+ printf(ERROR: could not set %s for %s: %s.\n,
prop_mode, node_type, fdt_strerror(err));
+ }
}
if (phy_type) {
err = fdt_setprop(blob, node_offset, prop_type, phy_type,
strlen(phy_type) + 1);
if (err 0)
- printf(WARNING: could not set %s for %s: %s.\n,
+ printf(ERROR: could not set %s for %s: %s.\n,
prop_type, node_type, fdt_strerror(err));
}
return node_offset;
}
+static int fdt_fixup_usb_erratum(void *blob, const char *erratum,
+ int start_offset)
+{
+ const char *prop_erratum_a006918 = fail-erratum-a006918;
+ const char *node_type = NULL;
+ const char *prop_type = status;
+ int node_offset, err;
+
+ node_type = fdt_usb_get_node_type(blob, start_offset, node_offset);
+ if (!node_type)
+ return -1;
+
+ if (!strcmp(erratum, erratum_a006918)) {
+ err = fdt_setprop(blob, node_offset, prop_type,
+ prop_erratum_a006918,
+ strlen(prop_erratum_a006918) + 1);
+
+ if (err 0) {
+ printf(ERROR: could not set %s for %s: %s.\n,
+ prop_erratum_a006918, node_type,
+ fdt_strerror(err));
+ }
+ }
+
+ return node_offset
[U-Boot] [PATCH][v3]powerpc/usb: Fix usb device-tree fix-up
Fix USB device-tree fixup to properly handle device-tree fixup and
print appropriate message when wrong/junk dr_mode or phy_type
are mentioned in hwconfig string
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v3:
- used puts instead of printf
- error message in one line
arch/powerpc/cpu/mpc8xxx/fdt.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 2847094..2db9045 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -167,6 +167,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
}
}
+ if (mode_idx 0 || phy_idx 0) {
+ puts(ERROR: wrong usb mode/phy defined!!\n);
+ return;
+ }
+
dr_mode_type = modes[mode_idx];
dr_phy_type = phys[phy_idx];
--
1.7.11.4
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[U-Boot] [PATCH][v2]powerpc/usb: Fix usb device-tree fix-up
Fix USB device-tree fixup to properly handle device-tree fixup and
print appropriate message when wrong/junk dr_mode or phy_type
are mentioned in hwconfig string
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v2:
- changed WARNING message to ERROR message
arch/powerpc/cpu/mpc8xxx/fdt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 2847094..857adeb 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -167,6 +167,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
}
}
+ if (mode_idx 0 || phy_idx 0) {
+ printf(ERROR: wrong usb mode/phy
+defined!!\n);
+ return;
+ }
+
dr_mode_type = modes[mode_idx];
dr_phy_type = phys[phy_idx];
--
1.7.11.4
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[U-Boot] [PATCH]powerpc/usb: Fix usb device-tree fix-up
Fix USB device-tree fixup to properly handle device-tree fixup and
print appropriate message when wrong/junk dr_mode or phy_type
are mentioned in hwconfig string
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/fdt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 2847094..413e184 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -167,6 +167,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
}
}
+ if (mode_idx 0 || phy_idx 0) {
+ printf(WARNING: wrong usb mode/phy
+defined!!\n);
+ return;
+ }
+
dr_mode_type = modes[mode_idx];
dr_phy_type = phys[phy_idx];
--
1.7.11.4
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[U-Boot] [PATCH]powerpc/mpc8xxx: Fix USB device-tree fixup
Fix usb device-tree fixup:
- wrong modification of dr_mode and phy_type when
usb1 is not mentioned inside hwconfig string;
now allows hwconfig strings like:
usb2:dr_mode=host,phy_type=ulpi
- add warning message for using usb_dr_mode
and usb_phy_type env variables (if either is used)
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Applies on git://git.denx.de/u-boot.git
(branch master)
arch/powerpc/cpu/mpc8xxx/fdt.c | 50 +++
1 files changed, 34 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 09810be..26815b8 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -138,6 +138,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
const char *phys[] = { ulpi, utmi };
const char *mode = NULL;
const char *phy_type = NULL;
+ char *dr_mode_type = NULL;
+ char *dr_phy_type = NULL;
char usb1_defined = 0;
int usb_mode_off = -1;
int usb_phy_off = -1;
@@ -155,6 +157,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
break;
}
}
+
for (j = 0; j ARRAY_SIZE(phys); j++) {
if (hwconfig_subarg_cmp(str, phy_type,
phys[j])) {
@@ -162,31 +165,46 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
break;
}
}
- if (mode_idx = 0) {
- usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
- modes[mode_idx], NULL, usb_mode_off);
- if (usb_mode_off 0)
- return;
- }
- if (phy_idx = 0) {
- usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
- NULL, phys[phy_idx], usb_phy_off);
- if (usb_phy_off 0)
- return;
- }
+
+ dr_mode_type = modes[mode_idx];
+ dr_phy_type = phys[phy_idx];
+
+ /* use usb_dr_mode and usb_phy_type if
+ usb1_defined = 0; these variables are to
+ be deprecated */
if (!strcmp(str, usb1))
usb1_defined = 1;
- if (mode_idx 0 phy_idx 0)
+
+ if (mode_idx 0 phy_idx 0) {
printf(WARNING: invalid phy or mode\n);
+ return;
+ }
}
+
+ usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+ dr_mode_type, NULL, usb_mode_off);
+
+ if (usb_mode_off 0)
+ return;
+
+ usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+ NULL, dr_phy_type, usb_phy_off);
+
+ if (usb_phy_off 0)
+ return;
}
+
if (!usb1_defined) {
int usb_off = -1;
mode = getenv(usb_dr_mode);
phy_type = getenv(usb_phy_type);
- if (!mode !phy_type)
- return;
- fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
+ if (mode || phy_type) {
+ printf(WARNING: usb_dr_mode and usb_phy_type
+ are to be deprecated soon. Use
+ hwconfig to set these values instead!!\n);
+ fdt_fixup_usb_mode_phy_type(blob, mode,
+ phy_type, usb_off);
+ }
}
}
#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
--
1.7.9
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[U-Boot] [PATCH][v2]powerpc/85xx: Add USB device-tree fixup for various platforms
Add USB device-tree fixup for following platforms: MPC8536DS, P1022DS, P1023RDS, P2020COME, P2020DS, P2041RDB, P3060QDS Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- Changes for v2: - removed extra call to fdt_fixup_dr_usb() outside CONFIG_HAS_FSL_DR_USB macro for p2020come board/freescale/mpc8536ds/mpc8536ds.c |7 ++- board/freescale/p1022ds/p1022ds.c |6 +- board/freescale/p1023rds/p1023rds.c |6 +- board/freescale/p2020come/p2020come.c |4 +++- board/freescale/p2020ds/p2020ds.c |6 +- board/freescale/p2041rdb/p2041rdb.c |6 +- board/freescale/p3060qds/p3060qds.c |6 +- include/configs/MPC8536DS.h |5 - include/configs/P1022DS.h |5 - include/configs/P1023RDS.h|5 - include/configs/P2020COME.h |6 -- include/configs/P2020DS.h |5 - include/configs/P2041RDB.h|8 +++- include/configs/corenet_ds.h |8 ++-- 14 files changed, 67 insertions(+), 16 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index c9f85c8..fb20192 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -295,5 +295,10 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + +#ifdef CONFIG_HAS_FSL_MPH_USB + fdt_fixup_dr_usb(blob, bd); +#endif + } #endif diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 456d9b0..f9ba1f8 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan srikanth.sriniva...@freescale.com * Timur Tabi ti...@freescale.com * @@ -341,6 +341,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 546819c..2f87583 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * Authors: Roy Zang tie-fei.z...@freescale.com * Chunhe Lan b25...@freescale.com @@ -197,6 +197,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + fdt_fixup_fman_ethernet(blob); } #endif diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c index 8cf7bee..ba4ef87 100644 --- a/board/freescale/p2020come/p2020come.c +++ b/board/freescale/p2020come/p2020come.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -282,6 +282,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB fdt_fixup_dr_usb(blob, bd); +#endif } #endif diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index d3af6cf..d9465f9 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -261,6 +261,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 1f6a34b..51c4310 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -215,6 +215,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB
[U-Boot] [PATCH] powerpc/85xx: Add USB device-tree fixup for various platforms
Add USB device-tree fixup for following platforms: MPC8536DS, P1022DS, P1023RDS, P2020COME, P2020DS, P2041RDB, P3060QDS Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- board/freescale/mpc8536ds/mpc8536ds.c |7 ++- board/freescale/p1022ds/p1022ds.c |6 +- board/freescale/p1023rds/p1023rds.c |6 +- board/freescale/p2020come/p2020come.c |6 +- board/freescale/p2020ds/p2020ds.c |6 +- board/freescale/p2041rdb/p2041rdb.c |6 +- board/freescale/p3060qds/p3060qds.c |6 +- include/configs/MPC8536DS.h |5 - include/configs/P1022DS.h |5 - include/configs/P1023RDS.h|5 - include/configs/P2020COME.h |6 -- include/configs/P2020DS.h |5 - include/configs/P2041RDB.h|8 +++- include/configs/corenet_ds.h |8 ++-- 14 files changed, 69 insertions(+), 16 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index c9f85c8..fb20192 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -295,5 +295,10 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + +#ifdef CONFIG_HAS_FSL_MPH_USB + fdt_fixup_dr_usb(blob, bd); +#endif + } #endif diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 456d9b0..f9ba1f8 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan srikanth.sriniva...@freescale.com * Timur Tabi ti...@freescale.com * @@ -341,6 +341,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 546819c..2f87583 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * Authors: Roy Zang tie-fei.z...@freescale.com * Chunhe Lan b25...@freescale.com @@ -197,6 +197,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + fdt_fixup_fman_ethernet(blob); } #endif diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c index 8cf7bee..ce78016 100644 --- a/board/freescale/p2020come/p2020come.c +++ b/board/freescale/p2020come/p2020come.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -282,6 +282,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + fdt_fixup_dr_usb(blob, bd); } #endif diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index d3af6cf..d9465f9 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -261,6 +261,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 1f6a34b..51c4310 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -215,6 +215,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + #ifdef CONFIG_PCI
[U-Boot] [PATCH][v3]powerpc/8xxx:Add MPH controller support in USB device-tree fixup
Add support for fixing usb mode and phy type for
MPH(Multi Port Host) USB controllers in device-tree nodes.
Required for socs like P3060, P5020, etc having MPH USB controller
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v3:
- removed const* type cast for node_type
- used CONFIG_HAS_FSL_MPH_USB in condition for including
fdt_fixup_dr_usb()
arch/powerpc/cpu/mpc8xxx/fdt.c | 29 +++--
include/fdt_support.h |4 ++--
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index bc1c30e..09810be 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -86,30 +86,39 @@ void ft_fixup_num_cores(void *blob) {
}
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
-#ifdef CONFIG_HAS_FSL_DR_USB
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
const char *phy_type, int start_offset)
{
- const char *compat = fsl-usb2-dr;
+ const char *compat_dr = fsl-usb2-dr;
+ const char *compat_mph = fsl-usb2-mph;
const char *prop_mode = dr_mode;
const char *prop_type = phy_type;
+ const char *node_type = NULL;
int node_offset;
int err;
node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat);
+ start_offset, compat_mph);
if (node_offset 0) {
- printf(WARNING: could not find compatible node %s: %s.\n,
- compat, fdt_strerror(node_offset));
- return -1;
- }
+ node_offset = fdt_node_offset_by_compatible(blob,
+ start_offset, compat_dr);
+ if (node_offset 0) {
+ printf(WARNING: could not find compatible
+node %s or %s: %s.\n, compat_mph,
+ compat_dr, fdt_strerror(node_offset));
+ return -1;
+ } else
+ node_type = compat_dr;
+ } else
+ node_type = compat_mph;
if (mode) {
err = fdt_setprop(blob, node_offset, prop_mode, mode,
strlen(mode) + 1);
if (err 0)
printf(WARNING: could not set %s for %s: %s.\n,
- prop_mode, compat, fdt_strerror(err));
+ prop_mode, node_type, fdt_strerror(err));
}
if (phy_type) {
@@ -117,7 +126,7 @@ static int fdt_fixup_usb_mode_phy_type(void *blob, const
char *mode,
strlen(phy_type) + 1);
if (err 0)
printf(WARNING: could not set %s for %s: %s.\n,
- prop_type, compat, fdt_strerror(err));
+ prop_type, node_type, fdt_strerror(err));
}
return node_offset;
@@ -180,7 +189,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
}
}
-#endif /* CONFIG_HAS_FSL_DR_USB */
+#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
/*
* update crypto node properties to a specified revision of the SEC
diff --git a/include/fdt_support.h b/include/fdt_support.h
index cef3c65..4b9f84a 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -61,11 +61,11 @@ int fdt_find_and_setprop(void *fdt, const char *node, const
char *prop,
const void *val, int len, int create);
void fdt_fixup_qe_firmware(void *fdt);
-#ifdef CONFIG_HAS_FSL_DR_USB
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
void fdt_fixup_dr_usb(void *blob, bd_t *bd);
#else
static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
-#endif /* CONFIG_HAS_FSL_DR_USB */
+#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
void fdt_fixup_crypto_node(void *blob, int sec_rev);
--
1.7.1
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[U-Boot] [PATCH][v2]powerpc/8xxx:Add MPH controller support in USB device-tree fixup
Add support for fixing usb mode and phy type for
MPH(Multi Port Host) USB controllers in device-tree nodes.
Required for socs like P3060, P5020, etc having MPH USB controller
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v2:
- used compat_dr and compat_mph strings instead of
compat[] array
- removed unrelated changes/fixes(which are sent in a separate patch)
arch/powerpc/cpu/mpc8xxx/fdt.c | 29 +++--
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index bc1c30e..0dc8419 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -86,30 +86,39 @@ void ft_fixup_num_cores(void *blob) {
}
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
-#ifdef CONFIG_HAS_FSL_DR_USB
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
const char *phy_type, int start_offset)
{
- const char *compat = fsl-usb2-dr;
+ const char *compat_dr = fsl-usb2-dr;
+ const char *compat_mph = fsl-usb2-mph;
const char *prop_mode = dr_mode;
const char *prop_type = phy_type;
+ char *node_type = NULL;
int node_offset;
int err;
node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat);
+ start_offset, compat_mph);
if (node_offset 0) {
- printf(WARNING: could not find compatible node %s: %s.\n,
- compat, fdt_strerror(node_offset));
- return -1;
- }
+ node_offset = fdt_node_offset_by_compatible(blob,
+ start_offset, compat_dr);
+ if (node_offset 0) {
+ printf(WARNING: could not find compatible
+node %s or %s: %s.\n, compat_mph,
+ compat_dr, fdt_strerror(node_offset));
+ return -1;
+ } else
+ node_type = (char *)compat_dr;
+ } else
+ node_type = (char *)compat_mph;
if (mode) {
err = fdt_setprop(blob, node_offset, prop_mode, mode,
strlen(mode) + 1);
if (err 0)
printf(WARNING: could not set %s for %s: %s.\n,
- prop_mode, compat, fdt_strerror(err));
+ prop_mode, node_type, fdt_strerror(err));
}
if (phy_type) {
@@ -117,7 +126,7 @@ static int fdt_fixup_usb_mode_phy_type(void *blob, const
char *mode,
strlen(phy_type) + 1);
if (err 0)
printf(WARNING: could not set %s for %s: %s.\n,
- prop_type, compat, fdt_strerror(err));
+ prop_type, node_type, fdt_strerror(err));
}
return node_offset;
@@ -180,7 +189,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
}
}
-#endif /* CONFIG_HAS_FSL_DR_USB */
+#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
/*
* update crypto node properties to a specified revision of the SEC
--
1.7.1
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[U-Boot] [PATCH]powerpc/8xxx: Cleanup USB device-tree fixup
Some code cleanup done for USB device-tree fixup:
- handling error value returned from fdt_fixup_usb_mode_phy_type()
- using ARRAY_SIZE macro
- using snprintf instead of sprintf
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
KW Warnings fixed: using snprintf instead of sprintf
arch/powerpc/cpu/mpc8xxx/fdt.c | 18 --
1 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index d07ae1b..bc1c30e 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -137,28 +137,34 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
for (i = 1; i = FSL_MAX_NUM_USB_CTRLS; i++) {
int mode_idx = -1, phy_idx = -1;
- sprintf(str, %s%d, usb, i);
+ snprintf(str, 5, %s%d, usb, i);
if (hwconfig(str)) {
- for (j = 0; j sizeof(modes); j++) {
+ for (j = 0; j ARRAY_SIZE(modes); j++) {
if (hwconfig_subarg_cmp(str, dr_mode,
modes[j])) {
mode_idx = j;
break;
}
}
- for (j = 0; j sizeof(phys); j++) {
+ for (j = 0; j ARRAY_SIZE(phys); j++) {
if (hwconfig_subarg_cmp(str, phy_type,
phys[j])) {
phy_idx = j;
break;
}
}
- if (mode_idx = 0)
+ if (mode_idx = 0) {
usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
modes[mode_idx], NULL, usb_mode_off);
- if (phy_idx = 0)
+ if (usb_mode_off 0)
+ return;
+ }
+ if (phy_idx = 0) {
usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
NULL, phys[phy_idx], usb_phy_off);
+ if (usb_phy_off 0)
+ return;
+ }
if (!strcmp(str, usb1))
usb1_defined = 1;
if (mode_idx 0 phy_idx 0)
--
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[U-Boot] [PATCH]powerpc/8xxx:Add MPH controller support in USB device-tree fixup
Add support for fixing usb mode and phy type for
MPH(Multi Port Host) USB controllers in device-tree nodes.
Required for socs like P3060, P5020, etc having MPH USB controller.
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/fdt.c | 46 ++--
include/fdt_support.h |4 +-
2 files changed, 32 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index d07ae1b..b22e0ec 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -86,30 +86,38 @@ void ft_fixup_num_cores(void *blob) {
}
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
-#ifdef CONFIG_HAS_FSL_DR_USB
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
const char *phy_type, int start_offset)
{
- const char *compat = fsl-usb2-dr;
+ const char *compat[] = {fsl-usb2-mph, fsl-usb2-dr};
const char *prop_mode = dr_mode;
const char *prop_type = phy_type;
+ char *node_type = NULL;
int node_offset;
int err;
node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat);
+ start_offset, compat[0]);
if (node_offset 0) {
- printf(WARNING: could not find compatible node %s: %s.\n,
- compat, fdt_strerror(node_offset));
- return -1;
- }
+ node_offset = fdt_node_offset_by_compatible(blob,
+ start_offset, compat[1]);
+ if (node_offset 0) {
+ printf(WARNING: could not find compatible
+node %s or %s: %s.\n, compat[0],
+ compat[1], fdt_strerror(node_offset));
+ return -1;
+ } else
+ node_type = (char *)compat[1];
+ } else
+ node_type = (char *)compat[0];
if (mode) {
err = fdt_setprop(blob, node_offset, prop_mode, mode,
strlen(mode) + 1);
if (err 0)
printf(WARNING: could not set %s for %s: %s.\n,
- prop_mode, compat, fdt_strerror(err));
+ prop_mode, node_type, fdt_strerror(err));
}
if (phy_type) {
@@ -117,7 +125,7 @@ static int fdt_fixup_usb_mode_phy_type(void *blob, const
char *mode,
strlen(phy_type) + 1);
if (err 0)
printf(WARNING: could not set %s for %s: %s.\n,
- prop_type, compat, fdt_strerror(err));
+ prop_type, node_type, fdt_strerror(err));
}
return node_offset;
@@ -137,28 +145,34 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
for (i = 1; i = FSL_MAX_NUM_USB_CTRLS; i++) {
int mode_idx = -1, phy_idx = -1;
- sprintf(str, %s%d, usb, i);
+ snprintf(str, 5, %s%d, usb, i);
if (hwconfig(str)) {
- for (j = 0; j sizeof(modes); j++) {
+ for (j = 0; j sizeof(modes)/sizeof(char *); j++) {
if (hwconfig_subarg_cmp(str, dr_mode,
modes[j])) {
mode_idx = j;
break;
}
}
- for (j = 0; j sizeof(phys); j++) {
+ for (j = 0; j sizeof(phys)/sizeof(char *); j++) {
if (hwconfig_subarg_cmp(str, phy_type,
phys[j])) {
phy_idx = j;
break;
}
}
- if (mode_idx = 0)
+ if (mode_idx = 0) {
usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
modes[mode_idx], NULL, usb_mode_off);
- if (phy_idx = 0)
+ if (usb_mode_off 0)
+ return;
+ }
+ if (phy_idx = 0) {
usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
NULL, phys
[U-Boot] [PATCH]powerpc/85xx: Make inclusion of USB device fixup conditional
Include call to usb device-fixup only when CONFIG_HAS_FSL_DR_USB is
defined for the platform - P1020RDB, P1010RDB, P1020-PC
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
board/freescale/p1010rdb/p1010rdb.c |2 ++
board/freescale/p1_p2_rdb/p1_p2_rdb.c |2 ++
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |3 +++
3 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index 03e9da1..b9e66f7 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -275,7 +275,9 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
+#endif
/* P1014 and it's derivatives don't support CAN and eTSEC3 */
if (cpu-soc_ver == SVR_P1014 || cpu-soc_ver == SVR_P1014_E) {
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 864b3ce..cfbae69 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -264,7 +264,9 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
+#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 4671128..a60c5a2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -444,6 +444,9 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_board_fixup_qe_pins(blob);
#endif
#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
+#endif
}
#endif
--
1.6.1
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[U-Boot] [PATCH]powerpc/85xx: Make inclusion of USB device fixup conditional
Include call to usb device-fixup only when CONFIG_HAS_FSL_DR_USB is
defined for the platform - P1020RDB, P1010RDB, P1020-PC
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
board/freescale/p1010rdb/p1010rdb.c |2 ++
board/freescale/p1_p2_rdb/p1_p2_rdb.c |2 ++
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |3 +++
3 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index 03e9da1..b9e66f7 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -275,7 +275,9 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
+#endif
/* P1014 and it's derivatives don't support CAN and eTSEC3 */
if (cpu-soc_ver == SVR_P1014 || cpu-soc_ver == SVR_P1014_E) {
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 864b3ce..cfbae69 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -264,7 +264,9 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
+#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 4671128..a60c5a2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -444,6 +444,9 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_board_fixup_qe_pins(blob);
#endif
#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
+#endif
}
#endif
--
1.6.1
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[U-Boot] [PATCH] powerpc/85xx: Fix warning for USB device-fixup
Fix USB device-fixup warning node not found. This was occuring
because of static nature of start_offset variable
Static start_offset was storing offset of last node modified, and
was becoming issue if node fixup is carried multiple times,
resulting in node not found warning
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/fdt.c | 24 +---
1 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 112c603..d07ae1b 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -87,13 +87,12 @@ void ft_fixup_num_cores(void *blob) {
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
#ifdef CONFIG_HAS_FSL_DR_USB
-static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
- const char *phy_type)
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+ const char *phy_type, int start_offset)
{
const char *compat = fsl-usb2-dr;
const char *prop_mode = dr_mode;
const char *prop_type = phy_type;
- static int start_offset = -1;
int node_offset;
int err;
@@ -102,7 +101,7 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const
char *mode,
if (node_offset 0) {
printf(WARNING: could not find compatible node %s: %s.\n,
compat, fdt_strerror(node_offset));
- return;
+ return -1;
}
if (mode) {
@@ -121,16 +120,18 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const
char *mode,
prop_type, compat, fdt_strerror(err));
}
- start_offset = node_offset;
+ return node_offset;
}
void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
const char *modes[] = { host, peripheral, otg };
- const char *phys[] = { ulpi, umti };
+ const char *phys[] = { ulpi, utmi };
const char *mode = NULL;
const char *phy_type = NULL;
char usb1_defined = 0;
+ int usb_mode_off = -1;
+ int usb_phy_off = -1;
char str[5];
int i, j;
@@ -153,11 +154,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
}
}
if (mode_idx = 0)
- fdt_fixup_usb_mode_phy_type(blob,
- modes[mode_idx], NULL);
+ usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+ modes[mode_idx], NULL, usb_mode_off);
if (phy_idx = 0)
- fdt_fixup_usb_mode_phy_type(blob,
- NULL, phys[phy_idx]);
+ usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+ NULL, phys[phy_idx], usb_phy_off);
if (!strcmp(str, usb1))
usb1_defined = 1;
if (mode_idx 0 phy_idx 0)
@@ -165,11 +166,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
}
}
if (!usb1_defined) {
+ int usb_off = -1;
mode = getenv(usb_dr_mode);
phy_type = getenv(usb_phy_type);
if (!mode !phy_type)
return;
- fdt_fixup_usb_mode_phy_type(blob, mode, phy_type);
+ fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
}
}
#endif /* CONFIG_HAS_FSL_DR_USB */
--
1.6.1
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[U-Boot] [PATCH] powerpc/8xxx: Update USB mode device tree fixup
Modify support for USB mode fixup:
- Add common support for USB mode and phy type
device tree fix-up for all USB controllers
mentioned in hwconfig string
- Fetch USB mode and phy type via hwconfig; if not
defined in hwconfig, then fetch them from env
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/fdt.c | 77 +--
1 files changed, 65 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 520cb90..d9e3e7e 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -29,6 +29,10 @@
#include asm/mp.h
#include asm/fsl_serdes.h
#include phy.h
+#include hwconfig.h
+#ifdef CONFIG_HAS_FSL_DR_USB
+#include usb.h
+#endif
#if defined(CONFIG_MP) (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -84,22 +88,18 @@ void ft_fixup_num_cores(void *blob) {
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
#ifdef CONFIG_HAS_FSL_DR_USB
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+ const char *phy_type)
{
- char *mode;
- char *type;
const char *compat = fsl-usb2-dr;
const char *prop_mode = dr_mode;
const char *prop_type = phy_type;
+ static int start_offset = -1;
int node_offset;
int err;
- mode = getenv(usb_dr_mode);
- type = getenv(usb_phy_type);
- if (!mode !type)
- return;
-
- node_offset = fdt_node_offset_by_compatible(blob, 0, compat);
+ node_offset = fdt_node_offset_by_compatible(blob,
+ start_offset, compat);
if (node_offset 0) {
printf(WARNING: could not find compatible node %s: %s.\n,
compat, fdt_strerror(node_offset));
@@ -114,13 +114,66 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
prop_mode, compat, fdt_strerror(err));
}
- if (type) {
- err = fdt_setprop(blob, node_offset, prop_type, type,
- strlen(type) + 1);
+ if (phy_type) {
+ err = fdt_setprop(blob, node_offset, prop_type, phy_type,
+ strlen(phy_type) + 1);
if (err 0)
printf(WARNING: could not set %s for %s: %s.\n,
prop_type, compat, fdt_strerror(err));
}
+
+ start_offset = node_offset;
+}
+
+void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+{
+ const char *modes[] = { host, peripheral, otg };
+ const char *phys[] = { ulpi, umti };
+ const char *mode = NULL;
+ const char *phy_type = NULL;
+ char usb1_defined = 0;
+ char str[5];
+ int i, j;
+
+ for (i = 1; i = USB_MAX_DEVICE; i++) {
+ int mode_idx = -1, phy_idx = -1;
+ sprintf(str, %s%d, usb, i);
+ if (hwconfig(str)) {
+ for (j = 0; j sizeof(modes); j++) {
+ if (hwconfig_subarg_cmp(str, dr_mode,
+ modes[j])) {
+ mode_idx = j;
+ break;
+ }
+ }
+ for (j = 0; j sizeof(phys); j++) {
+ if (hwconfig_subarg_cmp(str, phy_type,
+ phys[j])) {
+ phy_idx = j;
+ break;
+ }
+ }
+ if (mode_idx = 0)
+ fdt_fixup_usb_mode_phy_type(blob,
+ modes[mode_idx], NULL);
+ if (phy_idx = 0)
+ fdt_fixup_usb_mode_phy_type(blob,
+ NULL, phys[phy_idx]);
+ if (!strcmp(str, usb1))
+ usb1_defined = 1;
+ if (mode_idx 0 phy_idx 0)
+ printf(WARNING: invalid phy or mode\n);
+ } else {
+ break;
+ }
+ }
+ if (!usb1_defined) {
+ mode = getenv(usb_dr_mode);
+ phy_type = getenv(usb_phy_type);
+ if (!mode !phy_type)
+ return;
+ fdt_fixup_usb_mode_phy_type(blob, mode, phy_type);
+ }
}
#endif /* CONFIG_HAS_FSL_DR_USB */
--
1.6.1
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[U-Boot] [PATCH][v2] qoriq/p1_p2_rdb: USB device-tree fixups for P1020
Resolve P1020 second USB controller multiplexing with eLBC
- mandatory to mention USB2 in hwconfig string to select it
over eLBC, otherwise USB2 node is removed
- works only for SPI and SD boot
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v2:
- Incorporated Wolfgang's comments
- rebased patch on http://git.denx.de/u-boot.git
- top commit:
commit 264eaa0ea967bac32214b87d60cfc86c8b22cac6
Author: Valentin Longchamp valentin.longch...@keymile.com
Date: Wed May 4 01:47:33 2011 +
board/freescale/p1_p2_rdb/p1_p2_rdb.c | 47 +
1 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index d66b130..514e55d 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -37,6 +37,7 @@
#include netdev.h
#include rtc.h
#include i2c.h
+#include hwconfig.h
DECLARE_GLOBAL_DATA_PTR;
@@ -247,6 +248,8 @@ extern void ft_pci_board_setup(void *blob);
void ft_board_setup(void *blob, bd_t *bd)
{
+ const char *soc_usb_compat = fsl-usb2-dr;
+ int off, err, usb1_off, usb2_off;
phys_addr_t base;
phys_size_t size;
@@ -260,5 +263,49 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif /* #if defined(CONFIG_PCI) */
fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_dr_usb(blob, bd);
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ /* Delete eLBC node as it is muxed with USB2 controller */
+ if (hwconfig(usb2)) {
+ const char *soc_elbc_compat = fsl,p1020-elbc;
+ off = fdt_node_offset_by_compatible(blob, -1,
+ soc_elbc_compat);
+ if (off 0) {
+ printf(WARNING: could not find compatible node
+%s: %s.\n, soc_elbc_compat,
+ fdt_strerror(off));
+ return;
+ }
+ err = fdt_del_node(blob, off);
+ if (err 0) {
+ printf(WARNING: could not remove %s: %s.\n,
+ soc_elbc_compat, fdt_strerror(err));
+ }
+ return;
+ }
+#endif
+ /* Delete USB2 node as it is muxed with eLBC */
+ usb1_off = fdt_node_offset_by_compatible(blob, -1,
+ soc_usb_compat);
+ if (usb1_off 0) {
+ printf(WARNING: could not find compatible node
+%s: %s.\n, soc_usb_compat,
+ fdt_strerror(usb1_off));
+ return;
+ }
+ usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
+soc_usb_compat);
+ if (usb2_off 0) {
+ printf(WARNING: could not find compatible node
+%s: %s.\n, soc_usb_compat,
+ fdt_strerror(usb2_off));
+ return;
+ }
+ err = fdt_del_node(blob, usb2_off);
+ if (err 0)
+ printf(WARNING: could not remove %s: %s.\n,
+ soc_usb_compat, fdt_strerror(err));
}
#endif
--
1.6.1
___
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[U-Boot] [PATCH][v2]qoriq/p1_p2_rdb: Add Dual Role USB support macro for P1020RDB
Add CONFIG_HAS_FSL_DR_USB macro for P1020RDB Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- Changes for v2: - rebased on http://git.denx.de/u-boot.git include/configs/P1_P2_RDB.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 59f9755..4f1bdfe 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -601,6 +601,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB #endif #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) -- 1.6.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH]qoriq/p1_p2_rdb: Add Dual Role USB support macro for P1020RDB
Add CONFIG_HAS_FSL_DR_USB macro for P1020RDB Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- Applies on git://git.am.freescale.net/mirrors/u-boot.git (branch master) include/configs/P1_P2_RDB.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 59f9755..4f1bdfe 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -601,6 +601,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB #endif #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) -- 1.6.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] qoriq/p1_p2_rdb: USB device-tree fixups for P1020
Resolve P1020 second USB controller multiplexing with eLBC
- mandatory to mention USB2 in hwconfig string to select it
over eLBC, otherwise USB2 node is removed
- works only for SPI and SD boot
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Applies on git://git.am.freescale.net/mirrors/u-boot.git
(branch master)
board/freescale/p1_p2_rdb/p1_p2_rdb.c | 54 +
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index d66b130..14ad895 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -37,6 +37,7 @@
#include netdev.h
#include rtc.h
#include i2c.h
+#include hwconfig.h
DECLARE_GLOBAL_DATA_PTR;
@@ -247,6 +248,11 @@ extern void ft_pci_board_setup(void *blob);
void ft_board_setup(void *blob, bd_t *bd)
{
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ const char *soc_elbc_compat = fsl,p1020-elbc;
+#endif
+ const char *soc_usb_compat = fsl-usb2-dr;
+ int off, err, usb1_off, usb2_off;
phys_addr_t base;
phys_size_t size;
@@ -260,5 +266,53 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif /* #if defined(CONFIG_PCI) */
fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_dr_usb(blob, bd);
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ /* Delete eLBC node as it is muxed with USB2 controller */
+ if (hwconfig(usb2)) {
+ off = fdt_node_offset_by_compatible(blob, -1,
+ soc_elbc_compat);
+ if (off 0) {
+ printf(WARNING: could not find compatible node
+%s: %s.\n, soc_elbc_compat,
+ fdt_strerror(off));
+ return;
+ }
+ err = fdt_del_node(blob, off);
+ if (err 0) {
+ printf(WARNING: could not remove %s: %s.\n,
+ soc_elbc_compat, fdt_strerror(err));
+ return;
+ }
+ } else {
+#endif
+ /* Delete USB2 node as it is muxed with eLBC */
+ usb1_off = fdt_node_offset_by_compatible(blob, -1,
+ soc_usb_compat);
+ if (usb1_off 0) {
+ printf(WARNING: could not find compatible node
+%s: %s.\n, soc_usb_compat,
+ fdt_strerror(usb1_off));
+ return;
+ }
+ usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
+soc_usb_compat);
+ if (usb2_off 0) {
+ printf(WARNING: could not find compatible node
+%s: %s.\n, soc_usb_compat,
+ fdt_strerror(usb2_off));
+ return;
+ }
+ err = fdt_del_node(blob, usb2_off);
+ if (err 0) {
+ printf(WARNING: could not remove %s: %s.\n,
+ soc_usb_compat, fdt_strerror(err));
+ return;
+ }
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ }
+#endif
}
#endif
--
1.6.1
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[U-Boot] [PATCH] powerpc/qoriq: Update USB mode device tree fixup
Modify support for USB mode fixup:
- Add support for fetching USB mode and phy type
via hwconfig
- Add common support for USB mode and phy type
device tree fix-up for all USB controllers
mentioned in hwconfig string
- Add USB2 controller offset
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Applies on git://git.am.freescale.net/mirrors/u-boot
(branch next)
arch/powerpc/cpu/mpc8xxx/fdt.c| 84 ++---
arch/powerpc/include/asm/immap_85xx.h |3 +-
include/fdt_support.h |6 ++-
3 files changed, 74 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 54e60bb..3744205 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -28,6 +28,8 @@
#include fdt_support.h
#include asm/mp.h
#include asm/fsl_enet.h
+#include hwconfig.h
+#include usb.h
#if defined(CONFIG_MP) (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -83,25 +85,21 @@ void ft_fixup_num_cores(void *blob) {
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
#ifdef CONFIG_HAS_FSL_DR_USB
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+ const char *phy_type)
{
- char *mode;
- char *type;
const char *compat = fsl-usb2-dr;
const char *prop_mode = dr_mode;
const char *prop_type = phy_type;
- int node_offset;
- int err;
+ static int start_offset = -1;
+ int err, node_offset;
- mode = getenv(usb_dr_mode);
- type = getenv(usb_phy_type);
- if (!mode !type)
- return;
-
- node_offset = fdt_node_offset_by_compatible(blob, 0, compat);
+ node_offset = fdt_node_offset_by_compatible(blob,
+ start_offset, compat);
if (node_offset 0) {
- printf(WARNING: could not find compatible node %s: %s.\n,
- compat, fdt_strerror(node_offset));
+ printf(WARNING: could not find compatible
+ node %s: %s.\n, compat,
+ fdt_strerror(node_offset));
return;
}
@@ -113,13 +111,65 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
prop_mode, compat, fdt_strerror(err));
}
- if (type) {
- err = fdt_setprop(blob, node_offset, prop_type, type,
- strlen(type) + 1);
+ if (phy_type) {
+ err = fdt_setprop(blob, node_offset, prop_type, phy_type,
+ strlen(phy_type) + 1);
if (err 0)
printf(WARNING: could not set %s for %s: %s.\n,
prop_type, compat, fdt_strerror(err));
}
+
+ start_offset = node_offset;
+}
+
+void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+{
+ const char *modes[] = { host, peripheral, otg };
+ const char *phys[] = { ulpi, umti };
+ const char *phy_type = NULL;
+ char usb1_defined = 0;
+ const char *mode = NULL;
+ int node_offset;
+ char str[5];
+ int err, i, j;
+
+ for (i = 1; i = USB_MAX_DEVICE; i++) {
+ int mode_idx = -1, phy_idx = -1;
+ sprintf(str, %s%d, usb, i);
+ if (hwconfig(str)) {
+ for (j = 0; j sizeof(modes); j++) {
+ if (hwconfig_subarg_cmp(str, dr_mode,
+ modes[j])) {
+ mode_idx = j;
+ break;
+ }
+ }
+ for (j = 0; j sizeof(phys); j++) {
+ if (hwconfig_subarg_cmp(str, phy_type,
+ phys[j])) {
+ phy_idx = j;
+ break;
+ }
+ }
+ if ((mode_idx = 0) || (phy_idx = 0)) {
+ fdt_fixup_usb_mode_phy_type(blob,
+ modes[mode_idx], phys[phy_idx]);
+ if (!strcmp(str, usb1))
+ usb1_defined = 1;
+ } else {
+ printf(WARNING: invalid phy or mode\n);
+ }
+ } else
