RE: [PATCH] net: ftgmac100: Add reset control
> -Original Message-
> From: Dylan Hung
> Sent: Thursday, July 27, 2023 9:58 AM
> To: Ryan Chen ; ChiaWei Wang
> ; BMC-SW ;
> j...@jms.id.au; joe.hershber...@ni.com; rfried@gmail.com;
> u-boot@lists.denx.de
> Cc: kobedy...@gmail.com; Dylan Hung
> Subject: [PATCH] net: ftgmac100: Add reset control
>
> Add optional reset control, especially for the Aspeed SOC. For the hardware
> without a reset line, the reset assertion/deassertion will be skipped.
>
> Signed-off-by: Dylan Hung
Reviewed-by: Ryan Chen
> ---
> drivers/net/ftgmac100.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index
> a50cde338a..886b97119d 100644
> --- a/drivers/net/ftgmac100.c
> +++ b/drivers/net/ftgmac100.c
> @@ -13,6 +13,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -90,6 +91,7 @@ struct ftgmac100_data {
> u32 max_speed;
>
> struct clk_bulk clks;
> + struct reset_ctl *reset_ctl;
>
> /* End of RX/TX ring buffer bits. Depend on model */
> u32 rxdes0_edorr_mask;
> @@ -568,6 +570,8 @@ static int ftgmac100_of_to_plat(struct udevice *dev)
> priv->txdes0_edotr_mask = BIT(15);
> }
>
> + priv->reset_ctl = devm_reset_control_get_optional(dev, NULL);
> +
> return clk_get_bulk(dev, >clks); }
>
> @@ -593,6 +597,12 @@ static int ftgmac100_probe(struct udevice *dev)
> if (ret)
> goto out;
>
> + if (priv->reset_ctl) {
> + ret = reset_deassert(priv->reset_ctl);
> + if (ret)
> + goto out;
> + }
> +
> /*
>* If DM MDIO is enabled, the MDIO bus will be initialized later in
>* dm_eth_phy_connect
> @@ -628,6 +638,8 @@ static int ftgmac100_remove(struct udevice *dev)
> free(priv->phydev);
> mdio_unregister(priv->bus);
> mdio_free(priv->bus);
> + if (priv->reset_ctl)
> + reset_assert(priv->reset_ctl);
> clk_release_bulk(>clks);
>
> return 0;
> --
> 2.25.1
[PATCH] configs: evb-ast2600: Enable configs to store env in SPI
Enable defconfigs relevant for storing env on SPI flash. Signed-off-by: Ryan Chen --- configs/evb-ast2600_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index 3440062156..7c09e846ac 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds" CONFIG_ENV_SIZE=0x1 +CONFIG_ENV_OFFSET=0xe +CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb" CONFIG_SPL_SERIAL=y @@ -74,6 +76,8 @@ CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE_AUTO=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y -- 2.34.1
RE: [PATCH v2 1/1] i2c:aspeed:support ast2600 i2c new register mode driver
> -Original Message- > From: Simon Glass > Sent: Tuesday, January 24, 2023 2:44 AM > To: Ryan Chen > Cc: Heiko Schocher ; BMC-SW ; > u-boot@lists.denx.de > Subject: Re: [PATCH v2 1/1] i2c:aspeed:support ast2600 i2c new register mode > driver > > Hi Ryan, > > On Fri, 20 Jan 2023 at 17:10, Ryan Chen wrote: > > > > > -Original Message- > > > From: Simon Glass > > > Sent: Saturday, January 21, 2023 5:58 AM > > > To: Ryan Chen > > > Cc: Heiko Schocher ; BMC-SW > ; > > > u-boot@lists.denx.de > > > Subject: Re: [PATCH v2 1/1] i2c:aspeed:support ast2600 i2c new > > > register mode driver > > > > > > Hi Ryan, > > > > > > On Thu, 19 Jan 2023 at 20:12, Ryan Chen > > > wrote: > > > > > > > > Hello Simon, > > > > Sorry, do you have time to check v2 patch? > > > > > > I did not see a change log on it, so was not sure anything was needed? > > > Were there changes from the previous version? > > > > There have cover latter [PATCH v2 0/1] > > https://www.mail-archive.com/u-boot@lists.denx.de/msg460560.html > > You can use patman to produce a change list on each patch, then collate the > change lists into the cover letter. That way it is easier to put it on the > patch, > which is where I would expect it, while still having the cover letter show all > changes. > > It looks OK to me..but re this one: > > ret = uclass_get_device_by_driver(UCLASS_MISC, > + > DM_DRIVER_GET(aspeed_i2c_global), > + _dev); > > Can you not use the parent device? Hello Simon, Thanks your advice. I modify it use function ofnode_get_parent to get parent node address. And send the PATCHv3 https://www.mail-archive.com/u-boot@lists.denx.de/msg462840.html > > Regards, > Simon
[PATCH v3 1/2] i2c:aspeed:support ast2600 i2c new register mode driver
Add i2c new register mode driver to support AST2600 i2c
new register mode. AST2600 i2c controller have legacy and
new register mode. The new register mode have global register
support 4 base clock for scl clock selection, and new clock
divider mode.
Signed-off-by: Ryan Chen
---
MAINTAINERS | 6 +
drivers/i2c/Kconfig | 10 ++
drivers/i2c/Makefile | 1 +
drivers/i2c/ast2600_i2c.c | 367 ++
drivers/i2c/ast2600_i2c.h | 120 +
5 files changed, 504 insertions(+)
create mode 100644 drivers/i2c/ast2600_i2c.c
create mode 100644 drivers/i2c/ast2600_i2c.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3fc4cd0f12..1cf54f0b4e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -769,6 +769,12 @@ S: Maintained
F: drivers/pci/pcie_phytium.c
F: arch/arm/dts/phytium-durian.dts
+ASPEED AST2600 I2C DRIVER
+M: Ryan Chen
+R: Aspeed BMC SW team
+S: Maintained
+F: drivers/i2c/ast2600_i2c.c
+
ASPEED FMC SPI DRIVER
M: Chin-Ting Kuo
M: Cédric Le Goater
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 08b6c7bdcc..77e2a1c4c0 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -221,6 +221,16 @@ config SYS_I2C_DW
controller is used in various SoCs, e.g. the ST SPEAr, Altera
SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
+config SYS_I2C_AST2600
+bool "AST2600 I2C Controller"
+depends on DM_I2C && ARCH_ASPEED
+help
+ Say yes here to select AST2600 I2C Host Controller. The driver
+ support AST2600 I2C new mode register. This I2C controller supports:
+ _Standard-mode (up to 100 kHz)
+ _Fast-mode (up to 400 kHz)
+ _Fast-mode Plus (up to 1 MHz)
+
config SYS_I2C_ASPEED
bool "Aspeed I2C Controller"
depends on DM_I2C && ARCH_ASPEED
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 920aafb91c..89db2d8e37 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o
obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
+obj-$(CONFIG_SYS_I2C_AST2600) += ast2600_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
diff --git a/drivers/i2c/ast2600_i2c.c b/drivers/i2c/ast2600_i2c.c
new file mode 100644
index 00..f9d9ff09b3
--- /dev/null
+++ b/drivers/i2c/ast2600_i2c.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright ASPEED Technology Inc.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "ast2600_i2c.h"
+
+/* Device private data */
+struct ast2600_i2c_priv {
+ struct clk clk;
+ struct ast2600_i2c_regs *regs;
+ void __iomem *global;
+};
+
+static int ast2600_i2c_read_data(struct ast2600_i2c_priv *priv, u8 chip_addr,
+u8 *buffer, size_t len, bool send_stop)
+{
+ int rx_cnt, ret = 0;
+ u32 cmd, isr;
+
+ for (rx_cnt = 0; rx_cnt < len; rx_cnt++, buffer++) {
+ cmd = I2CM_PKT_EN | I2CM_PKT_ADDR(chip_addr) |
+ I2CM_RX_CMD;
+ if (!rx_cnt)
+ cmd |= I2CM_START_CMD;
+
+ if ((len - 1) == rx_cnt)
+ cmd |= I2CM_RX_CMD_LAST;
+
+ if (send_stop && ((len - 1) == rx_cnt))
+ cmd |= I2CM_STOP_CMD;
+
+ writel(cmd, >regs->cmd_sts);
+
+ ret = readl_poll_timeout(>regs->isr, isr,
+isr & I2CM_PKT_DONE,
+I2C_TIMEOUT_US);
+ if (ret)
+ return -ETIMEDOUT;
+
+ *buffer =
+ I2CC_GET_RX_BUFF(readl(>regs->trx_buff));
+
+ writel(I2CM_PKT_DONE, >regs->isr);
+
+ if (isr & I2CM_TX_NAK)
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+static int ast2600_i2c_write_data(struct ast2600_i2c_priv *priv, u8 chip_addr,
+ u8 *buffer, size_t len, bool send_stop)
+{
+ int tx_cnt, ret = 0;
+ u32 cmd, isr;
+
+ if (!len) {
+ cmd = I2CM_PKT_EN | I2CM_PKT_ADDR(chip_addr) |
+ I2CM_START_CMD;
+ writel(cmd, >regs->cmd_sts);
+ ret = readl_poll_timeout(>regs->isr, isr,
+isr & I2CM_PKT_DONE,
+I2C_TIMEOUT_US);
+ if (ret)
+ return -ETIMEDOUT;
+
+ writel(I2CM_PKT_DONE, >regs->isr);
+
+ if (isr & I2CM_TX_NAK)
+ return -EREMOTEIO;
+ }
+
+
[PATCH v3 2/2] arm: aspeed: dtsi: add reg for i2c
The i2c driver have global register that i2c bus use
ofnode_get_parent to get parent register address.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2600.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 8d91eedc17..beabcf14f8 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -681,6 +681,7 @@
i2c: bus@1e78a000 {
compatible = "simple-bus";
+ reg = <0x1e78a000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e78a000 0x1000>;
--
2.34.1
[PATCH v3 0/2] Add ASPEED AST2600 I2C new controller driver
This series add AST2600 i2c new register set driver. The i2c new register set have new clock divider option for more flexiable generation. Changes in v3: -modify uclass_get_device_by_driver to ofnode_get_parent. -Add i2c reg address in dtsi node. -fix up git config name from ryan_chen to Ryan Chen. Changes in v2: -add speed support desciption in Kconfig. -modify include header ordering. -separate include register define header. -modify wording reserver to reserved. -remove defined string AST2600. -modify signle-line comment style. -remove extra (). -modify local regs for register ctrl. Ryan Chen (2): i2c:aspeed:support ast2600 i2c new register mode driver arm: aspeed: dtsi: add reg for i2c MAINTAINERS | 6 + arch/arm/dts/ast2600.dtsi | 1 + drivers/i2c/Kconfig | 10 ++ drivers/i2c/Makefile | 1 + drivers/i2c/ast2600_i2c.c | 367 ++ drivers/i2c/ast2600_i2c.h | 120 + 6 files changed, 505 insertions(+) create mode 100644 drivers/i2c/ast2600_i2c.c create mode 100644 drivers/i2c/ast2600_i2c.h -- 2.34.1
RE: [PATCH v2 1/1] i2c:aspeed:support ast2600 i2c new register mode driver
> -Original Message- > From: Simon Glass > Sent: Saturday, January 21, 2023 5:58 AM > To: Ryan Chen > Cc: Heiko Schocher ; BMC-SW ; > u-boot@lists.denx.de > Subject: Re: [PATCH v2 1/1] i2c:aspeed:support ast2600 i2c new register mode > driver > > Hi Ryan, > > On Thu, 19 Jan 2023 at 20:12, Ryan Chen > wrote: > > > > Hello Simon, > > Sorry, do you have time to check v2 patch? > > I did not see a change log on it, so was not sure anything was needed? > Were there changes from the previous version? There have cover latter [PATCH v2 0/1] https://www.mail-archive.com/u-boot@lists.denx.de/msg460560.html Ryan Chen
RE: [PATCH v2 1/1] i2c:aspeed:support ast2600 i2c new register mode driver
Hello Simon,
Sorry, do you have time to check v2 patch?
Ryan Chen
> -Original Message-
> From: Ryan Chen
> Sent: Wednesday, January 11, 2023 2:53 PM
> To: Heiko Schocher ; Ryan Chen ;
> BMC-SW ; u-boot@lists.denx.de
> Subject: [PATCH v2 1/1] i2c:aspeed:support ast2600 i2c new register mode
> driver
>
> Add i2c new register mode driver to support AST2600 i2c new register mode.
> AST2600 i2c controller have legacy and new register mode. The new register
> mode have global register support 4 base clock for scl clock selection, and
> new
> clock divider mode.
>
> Signed-off-by: ryan_chen
> ---
> MAINTAINERS | 6 +
> drivers/i2c/Kconfig | 10 +
> drivers/i2c/Makefile | 1 +
> drivers/i2c/ast2600_i2c.c | 375
> ++
> drivers/i2c/ast2600_i2c.h | 120
> 5 files changed, 512 insertions(+)
> create mode 100644 drivers/i2c/ast2600_i2c.c create mode 100644
> drivers/i2c/ast2600_i2c.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3fc4cd0f12..1cf54f0b4e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -769,6 +769,12 @@ S: Maintained
> F: drivers/pci/pcie_phytium.c
> F: arch/arm/dts/phytium-durian.dts
>
> +ASPEED AST2600 I2C DRIVER
> +M: Ryan Chen
> +R: Aspeed BMC SW team
> +S: Maintained
> +F: drivers/i2c/ast2600_i2c.c
> +
> ASPEED FMC SPI DRIVER
> M: Chin-Ting Kuo
> M: Cédric Le Goater
> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index
> 08b6c7bdcc..77e2a1c4c0 100644
> --- a/drivers/i2c/Kconfig
> +++ b/drivers/i2c/Kconfig
> @@ -221,6 +221,16 @@ config SYS_I2C_DW
> controller is used in various SoCs, e.g. the ST SPEAr, Altera
> SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
>
> +config SYS_I2C_AST2600
> +bool "AST2600 I2C Controller"
> +depends on DM_I2C && ARCH_ASPEED
> +help
> + Say yes here to select AST2600 I2C Host Controller. The driver
> + support AST2600 I2C new mode register. This I2C controller supports:
> + _Standard-mode (up to 100 kHz)
> + _Fast-mode (up to 400 kHz)
> + _Fast-mode Plus (up to 1 MHz)
> +
> config SYS_I2C_ASPEED
> bool "Aspeed I2C Controller"
> depends on DM_I2C && ARCH_ASPEED
> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index
> 920aafb91c..89db2d8e37 100644
> --- a/drivers/i2c/Makefile
> +++ b/drivers/i2c/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) +=
> cros_ec_ldo.o
>
> obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o
> obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
> +obj-$(CONFIG_SYS_I2C_AST2600) += ast2600_i2c.o
> obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
> obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
> obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o diff --git
> a/drivers/i2c/ast2600_i2c.c b/drivers/i2c/ast2600_i2c.c new file mode 100644
> index 00..0fad30b5a2
> --- /dev/null
> +++ b/drivers/i2c/ast2600_i2c.c
> @@ -0,0 +1,375 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright ASPEED Technology Inc.
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "ast2600_i2c.h"
> +
> +/* Device private data */
> +struct ast2600_i2c_priv {
> + struct clk clk;
> + struct ast2600_i2c_regs *regs;
> + void __iomem *global;
> +};
> +
> +static int ast2600_i2c_read_data(struct ast2600_i2c_priv *priv, u8 chip_addr,
> + u8 *buffer, size_t len, bool send_stop) {
> + int rx_cnt, ret = 0;
> + u32 cmd, isr;
> +
> + for (rx_cnt = 0; rx_cnt < len; rx_cnt++, buffer++) {
> + cmd = I2CM_PKT_EN | I2CM_PKT_ADDR(chip_addr) |
> + I2CM_RX_CMD;
> + if (!rx_cnt)
> + cmd |= I2CM_START_CMD;
> +
> + if ((len - 1) == rx_cnt)
> + cmd |= I2CM_RX_CMD_LAST;
> +
> + if (send_stop && ((len - 1) == rx_cnt))
> + cmd |= I2CM_STOP_CMD;
> +
> + writel(cmd, >regs->cmd_sts);
> +
> + ret = readl_poll_timeout(>regs->isr, isr,
> + isr & I2CM_PKT_DONE,
> + I2C_TIMEOUT_US);
> + if (ret)
> + return -ETIMEDOUT;
> +
> + *buffer =
> + I2CC_GET_RX_BUFF(readl(>regs->trx_buff));
> +
> + writel(I2CM_PKT_DONE, >regs->isr);
> +
> +
RE: [PATCH 1/1] i2c:aspeed:support ast2600 i2c new register mode driver
Hello, I resend the v2 version here https://www.mail-archive.com/u-boot@lists.denx.de/msg460560.html Ryan Chen > -Original Message- > From: Simon Glass > Sent: Thursday, January 12, 2023 5:08 AM > To: Ryan Chen > Cc: Heiko Schocher ; BMC-SW ; > u-boot@lists.denx.de > Subject: Re: [PATCH 1/1] i2c:aspeed:support ast2600 i2c new register mode > driver > > Hi Ryan, > > On Tue, 10 Jan 2023 at 23:48, ryan_chen > wrote: > > > > Add i2c new register mode driver to support AST2600 i2c new register > > mode. AST2600 i2c controller have legacy and new register mode. The > > new register mode have global register support 4 base clock for scl > > clock selection, and new clock divider mode. > > > > Signed-off-by: ryan_chen > > --- > > MAINTAINERS | 6 + > > drivers/i2c/Kconfig | 10 + > > drivers/i2c/Makefile | 1 + > > drivers/i2c/ast2600_i2c.c | 375 > > ++ > > drivers/i2c/ast2600_i2c.h | 120 > > 5 files changed, 512 insertions(+) > > create mode 100644 drivers/i2c/ast2600_i2c.c create mode 100644 > > drivers/i2c/ast2600_i2c.h > > Is this a new version? > > Regards, > Simon
RE: [PATCH 1/1] i2c:aspeed:support ast2600 i2c new register mode driver
Hello Simon,
Thank your feedback.
> -Original Message-
> From: Simon Glass
> Sent: Tuesday, January 10, 2023 3:47 AM
> To: Ryan Chen
> Cc: Heiko Schocher ; BMC-SW ;
> u-boot@lists.denx.de
> Subject: Re: [PATCH 1/1] i2c:aspeed:support ast2600 i2c new register mode
> driver
>
> Hi Ryan_chen,
>
> On Mon, 9 Jan 2023 at 01:30, ryan_chen
> wrote:
> >
> > Add i2c new register mode driver to support AST2600 i2c new register
> > mode. AST2600 i2c controller have legacy and new register mode. The
> > new register mode have global register support 4 base clock for scl
> > clock selection, and new clock divider mode.
> >
> > Signed-off-by: ryan_chen
> > ---
> > MAINTAINERS | 6 +
> > drivers/i2c/Kconfig | 7 +
> > drivers/i2c/Makefile | 1 +
> > drivers/i2c/ast2600_i2c.c | 480
> > ++
> > 4 files changed, 494 insertions(+)
> > create mode 100644 drivers/i2c/ast2600_i2c.c
>
> This generally looks OK, but I have quite a few minor comments, and one
> major one: could/should this driver be an update to the existing one, instead?
> That is the short of thing that really should be in your commit message.
>
This driver is now driver not be an update to the exiting one.
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index 3fc4cd0f12..1cf54f0b4e
> > 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -769,6 +769,12 @@ S: Maintained
> > F: drivers/pci/pcie_phytium.c
> > F: arch/arm/dts/phytium-durian.dts
> >
> > +ASPEED AST2600 I2C DRIVER
> > +M: Ryan Chen
> > +R: Aspeed BMC SW team
> > +S: Maintained
> > +F: drivers/i2c/ast2600_i2c.c
> > +
> > ASPEED FMC SPI DRIVER
> > M: Chin-Ting Kuo
> > M: Cédric Le Goater
> > diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index
> > 08b6c7bdcc..34f507fb3b 100644
> > --- a/drivers/i2c/Kconfig
> > +++ b/drivers/i2c/Kconfig
> > @@ -221,6 +221,13 @@ config SYS_I2C_DW
> > controller is used in various SoCs, e.g. the ST SPEAr, Altera
> > SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
> >
> > +config SYS_I2C_AST2600
> > +bool "AST2600 I2C Controller"
> > +depends on DM_I2C && ARCH_ASPEED
> > +help
> > + Say yes here to select AST2600 I2C Host Controller. The driver
> > + support AST2600 I2C new mode register.
>
> What speeds does it support?
Will modify by following.
+config SYS_I2C_AST2600
+bool "AST2600 I2C Controller"
+depends on DM_I2C && ARCH_ASPEED
+help
+ Say yes here to select AST2600 I2C Host Controller. The driver
+ support AST2600 I2C new mode register. This I2C controller supports:
+ -Standard-mode (up to 100 kHz)
+ -Fast-mode (up to 400 kHz)
+ -Fast-mode Plus (up to 1 MHz)
>Please add at least 3 lines of info.
Sorry, what do you mean about 3 lines of info?
The i2c have two lines, SDA/SCL only.
>
> A link to the datasheet would help too, either here or in doc/
>
> > +
> > config SYS_I2C_ASPEED
> > bool "Aspeed I2C Controller"
> > depends on DM_I2C && ARCH_ASPEED diff --git
> > a/drivers/i2c/Makefile b/drivers/i2c/Makefile index
> > 920aafb91c..89db2d8e37 100644
> > --- a/drivers/i2c/Makefile
> > +++ b/drivers/i2c/Makefile
> > @@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) +=
> > cros_ec_ldo.o
> >
> > obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o
> > obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
> > +obj-$(CONFIG_SYS_I2C_AST2600) += ast2600_i2c.o
> > obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
> > obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
> > obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o diff --git
> > a/drivers/i2c/ast2600_i2c.c b/drivers/i2c/ast2600_i2c.c new file mode
> > 100644 index 00..52aea460ac
> > --- /dev/null
> > +++ b/drivers/i2c/ast2600_i2c.c
> > @@ -0,0 +1,480 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright ASPEED Technology Inc.
> > + */
> > +#include
>
> The ordering is off here. Please see
>
> https://u-boot.readthedocs.io/en/latest/develop/codingstyle.html#include-files
Will update
>
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +struct ast2600_i2c_regs {
> > + u32 fun_ctrl;
> > + u32 ac_timin
RE: [PATCH 3/3] ram: ast2600: Align the RL and WL setting
> -Original Message-
> From: Dylan Hung
> Sent: Friday, November 11, 2022 3:30 PM
> To: Ryan Chen ; ChiaWei Wang
> ; j...@jms.id.au; Dylan Hung
> ; u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 3/3] ram: ast2600: Align the RL and WL setting
>
> Use macro to represent the RL and WL setting to ensure the PHY and controller
> setting are aligned.
>
> Signed-off-by: Dylan Hung
Review-by: Ryan Chen
> ---
> arch/arm/include/asm/arch-aspeed/sdram_ast2600.h | 4
> drivers/ram/aspeed/sdram_ast2600.c | 9 +
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> index d2408c0020f8..b0a91ae40d44 100644
> --- a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> +++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> @@ -104,6 +104,10 @@
> #define SDRAM_FORCE_PRECHARGE_EN BIT(4)
> #define SDRAM_REFRESH_EN BIT(0)
>
> +/* MCR14 */
> +#define SDRAM_WL_SETTING GENMASK(23, 20)
> +#define SDRAM_CL_SETTING GENMASK(19, 16)
> +
> #define SDRAM_TEST_LEN_SHIFT 4
> #define SDRAM_TEST_LEN_MASK 0xf
> #define SDRAM_TEST_START_ADDR_SHIFT 24
> diff --git a/drivers/ram/aspeed/sdram_ast2600.c
> b/drivers/ram/aspeed/sdram_ast2600.c
> index bda02d062900..5d426088be3e 100644
> --- a/drivers/ram/aspeed/sdram_ast2600.c
> +++ b/drivers/ram/aspeed/sdram_ast2600.c
> @@ -15,6 +15,7 @@
> #include
> #include
> #include
> +#include
> #include
>
> #define DDR_PHY_TBL_CHG_ADDR0xaeeddeea
> @@ -935,6 +936,7 @@ static void ast2600_sdrammc_lock(struct dram_info
> *info) static void ast2600_sdrammc_common_init(struct
> ast2600_sdrammc_regs *regs) {
> int i;
> + u32 reg;
>
> writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, >power_ctrl);
> writel(SDRAM_VIDEO_UNLOCK_KEY, >gm_protection_key); @@
> -969,6 +971,13 @@ static void ast2600_sdrammc_common_init(struct
> ast2600_sdrammc_regs *regs)
> for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
> writel(ddr4_ac_timing[i], >ac_timing[i]);
>
> + /* update CL and WL */
> + reg = readl(>ac_timing[1]);
> + reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING);
> + reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) |
> +FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5);
> + writel(reg, >ac_timing[1]);
> +
> writel(DDR4_MR01_MODE, >mr01_mode_setting);
> writel(DDR4_MR23_MODE, >mr23_mode_setting);
> writel(DDR4_MR45_MODE, >mr45_mode_setting);
> --
> 2.25.1
RE: [PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality
> -Original Message- > From: Dylan Hung > Sent: Friday, November 11, 2022 3:30 PM > To: Ryan Chen ; ChiaWei Wang > ; j...@jms.id.au; Dylan Hung > ; u-boot@lists.denx.de > Cc: BMC-SW > Subject: [PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality > > Adjust the following settings to get better timing and signal quality. > > 1. write DQS/DQ delay > - 1e6e2304[0] > - 1e6e2304[15:8] > > 2. read DQS/DQ delay > - 0x1e6e0298[0] > - 0x1e6e0298[15:8] > > 3. CLK/CA timing > - 0x1e6e01a8[31] > > 4. Read and write termination > - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8]) > - change RTT_PARK from disable to 48 ohm (MR5[8:6]) > - change RTT_WR from 120 ohm to disable (MR2[11:9]) > - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8]) > > Note1: Both DDR-PHY and DDR controller have their own registers for DDR4 > Mode Registers (MR0~MR6). This patch introduces macros to synchronize the > MR value on both sides. > > Note2: the waveform meansurement can be found in item #21 of Aspeed > AST26x0 Application note (AP note). > > Signed-off-by: Dylan Hung Review-by: Ryan Chen > --- > drivers/ram/aspeed/sdram_ast2600.c | 163 - > 1 file changed, 138 insertions(+), 25 deletions(-) > > diff --git a/drivers/ram/aspeed/sdram_ast2600.c > b/drivers/ram/aspeed/sdram_ast2600.c > index b09232a30413..bda02d062900 100644 > --- a/drivers/ram/aspeed/sdram_ast2600.c > +++ b/drivers/ram/aspeed/sdram_ast2600.c > @@ -20,6 +20,119 @@ > #define DDR_PHY_TBL_CHG_ADDR0xaeeddeea > #define DDR_PHY_TBL_END 0xaeededed > > +/** > + * phyr030[18:16] - Ron PU (PHY side) > + * phyr030[14:12] - Ron PD (PHY side) > + * b'000 : disable > + * b'001 : 240 ohm > + * b'010 : 120 ohm > + * b'011 : 80 ohm > + * b'100 : 60 ohm > + * b'101 : 48 ohm > + * b'110 : 40 ohm > + * b'111 : 34 ohm (default) > + */ > +#define PHY_RON ((0x7 << 16) | (0x7 << 12)) > + > +/** > + * phyr030[10:8] - ODT configuration (PHY side) > + * b'000 : ODT disabled > + * b'001 : 240 ohm > + * b'010 : 120 ohm > + * b'011 : 80 ohm (default) > + * b'100 : 60 ohm > + * b'101 : 48 ohm > + * b'110 : 40 ohm > + * b'111 : 34 ohm > + */ > +#define PHY_ODT (0x3 << 8) > + > +/** > + * MR1[2:1] output driver impedance > + * b'00 : 34 ohm (default) > + * b'01 : 48 ohm > + */ > +#define DRAM_RON (0x0 << 1) > + > +/** > + * DRAM ODT - synchronous ODT mode > + * RTT_WR: disable > + * RTT_NOM = RTT_PARK > + * > + * MR1[10:8] RTT_NOM > + * b'000 : RTT_NOM disable > + * b'001 : 60 ohm > + * b'010 : 120 ohm > + * b'011 : 40 ohm > + * b'100 : 240 ohm > + * b'101 : 48 ohm (default) > + * b'110 : 80 ohm > + * b'111 : 34 ohm > + * > + * MR5[8:6] RTT_PARK > + * b'000 : RTT_PARK disable > + * b'001 : 60 ohm > + * b'010 : 120 ohm > + * b'011 : 40 ohm > + * b'100 : 240 ohm > + * b'101 : 48 ohm (default) > + * b'110 : 80 ohm > + * b'111 : 34 ohm > + * > + * MR2[11:9] RTT_WR > + * b'000 : Dynamic ODT off (default) > + * b'001 : 120 ohm > + * b'010 : 240 ohm > + * b'011 : Hi-Z > + * b'100 : 80 ohm > + */ > +#define RTT_WR (0x0 << 9) > +#define RTT_NOM (0x5 << 8) > +#define RTT_PARK (0x5 << 6) > + > +/** > + * MR6[6] VrefDQ training range > + * b'0 : range 1 > + * b'1 : range 2 (default) > + */ > +#define VREFDQ_RANGE_2 BIT(6) > + > +/** > + * Latency setting: > + * AL = PL = 0 (hardware fixed setting) > + * -> WL = AL + CWL + PL = CWL > + * -> RL = AL + CL + PL = CL > + */ > +#define CONFIG_WL9 > +#define CONFIG_RL12 > +#define T_RDDATA_EN ((CONFIG_RL - 2) << 8) > +#define T_PHY_WRLAT (CONFIG_WL - 2) > + > +/* MR0 */ > +#define MR0_CL_12(BIT(4) | BIT(2)) > +#define MR0_WR12_RTP6BIT(9) > +#define MR0_DLL_RESETBIT(8) > +#define MR0_VAL (MR0_CL_12 | MR0_WR12_RTP6 | > MR0_DLL_RESET) > + > +/* MR1 */ > +#define MR1_VAL (0x0001 | RTT_NOM | DRAM_RON) > + > +/* MR2 */ > +#define MR2_CWL_90 > +#define MR2_VAL (0x | RTT_WR | MR2_CWL_9) > + > +/* MR3 ~ MR6 */ > +#define MR3_VAL 0x
RE: [PATCH 1/3] ram: ast2600: Fix incorrect statement of the register polling
> -Original Message-
> From: Dylan Hung
> Sent: Friday, November 11, 2022 3:30 PM
> To: Ryan Chen ; ChiaWei Wang
> ; j...@jms.id.au; Dylan Hung
> ; u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 1/3] ram: ast2600: Fix incorrect statement of the register
> polling
>
> The condition "~data" in the if-statement is a typo. The original intention
> is
> to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use "data == 0" for
> instead.
>
> Besides, the bit[1] of "phy_status" register is hardwired to
> SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has
> already done, remove the unnecessary checking of phy_status[1].
>
> Fixes: fde93143469f ("ram: aspeed: Add AST2600 DRAM control support")
>
> Signed-off-by: Dylan Hung
Review-by: Ryan Chen
> ---
> drivers/ram/aspeed/sdram_ast2600.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/ram/aspeed/sdram_ast2600.c
> b/drivers/ram/aspeed/sdram_ast2600.c
> index 9ad398d24155..b09232a30413 100644
> --- a/drivers/ram/aspeed/sdram_ast2600.c
> +++ b/drivers/ram/aspeed/sdram_ast2600.c
> @@ -449,7 +449,7 @@ static void ast2600_sdramphy_kick_training(struct
> dram_info *info)
>
> while (1) {
> data = readl(>phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT;
> - if (~data)
> + if (data == 0)
> break;
> }
> }
> @@ -984,11 +984,6 @@ static int ast2600_sdrammc_probe(struct udevice
> *dev)
> L_ast2600_sdramphy_train:
> ast2600_sdrammc_init_ddr4(priv);
>
> - /* make sure DDR-PHY is ready before access */
> - do {
> - reg = readl(priv->phy_status) & BIT(1);
> - } while (reg == 0);
> -
> if (ast2600_sdramphy_check_status(priv) != 0) {
> printf("DDR4 PHY training fail, retrain\n");
> goto L_ast2600_sdramphy_train;
> --
> 2.25.1
RE: [PATCH 08/10] i2c/aspeed: Add AST2600 compatible
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 08/10] i2c/aspeed: Add AST2600 compatible
>
> Signed-off-by: Joel Stanley
Reviewed-by: Ryan Chen
> ---
> drivers/i2c/ast_i2c.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c index
> 0a93d7c82911..c9ffe2d62820 100644
> --- a/drivers/i2c/ast_i2c.c
> +++ b/drivers/i2c/ast_i2c.c
> @@ -351,6 +351,7 @@ static const struct dm_i2c_ops ast_i2c_ops = { static
> const struct udevice_id ast_i2c_ids[] = {
> { .compatible = "aspeed,ast2400-i2c-bus" },
> { .compatible = "aspeed,ast2500-i2c-bus" },
> + { .compatible = "aspeed,ast2600-i2c-bus" },
> { },
> };
>
> --
> 2.35.1
RE: [PATCH 07/10] i2c/aspeed: Fix reset control
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 07/10] i2c/aspeed: Fix reset control
>
> The reset control was written for the ast2500 and directly programs the
> clocking register.
>
> So we can share the code with other SoC generations use the reset device to
> deassert the I2C reset line.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Ryan Chen
> ---
> drivers/i2c/ast_i2c.c | 22 +++---
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c index
> 2d3fecaa14ea..0a93d7c82911 100644
> --- a/drivers/i2c/ast_i2c.c
> +++ b/drivers/i2c/ast_i2c.c
> @@ -16,6 +16,7 @@
> #include
> #include
> #include
> +#include
>
> #include "ast_i2c.h"
>
> @@ -108,19 +109,26 @@ static int ast_i2c_of_to_plat(struct udevice *dev)
>
> static int ast_i2c_probe(struct udevice *dev) {
> - struct ast2500_scu *scu;
> + struct reset_ctl reset_ctl;
> + int rc;
>
> debug("Enabling I2C%u\n", dev_seq(dev));
>
> /*
>* Get all I2C devices out of Reset.
> - * Only needs to be done once, but doing it for every
> - * device does not hurt.
> + *
> + * Only needs to be done once so test before performing reset.
>*/
> - scu = ast_get_scu();
> - ast_scu_unlock(scu);
> - clrbits_le32(>sysreset_ctrl1, SCU_SYSRESET_I2C);
> - ast_scu_lock(scu);
> + rc = reset_get_by_index(dev, 0, _ctl);
> + if (rc) {
> + printf("%s: Failed to get reset signal\n", __func__);
> + return rc;
> + }
> +
> + if (reset_status(_ctl) > 0) {
> + reset_assert(_ctl);
> + reset_deassert(_ctl);
> + }
>
> ast_i2c_init_bus(dev);
>
> --
> 2.35.1
RE: [PATCH 06/10] reset/aspeed: Implement status callback
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 06/10] reset/aspeed: Implement status callback
>
> The I2C driver shares a reset line between buses, so allow it to test the
> state of
> the reset line before resetting it.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Ryan Chen
> ---
> drivers/reset/reset-ast2500.c | 19 +++
> drivers/reset/reset-ast2600.c | 17 +
> 2 files changed, 36 insertions(+)
>
> diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c
> index
> 0a1dd236aff3..d9cecf3a72e8 100644
> --- a/drivers/reset/reset-ast2500.c
> +++ b/drivers/reset/reset-ast2500.c
> @@ -48,6 +48,24 @@ static int ast2500_reset_deassert(struct reset_ctl
> *reset_ctl)
> return 0;
> }
>
> +static int ast2500_reset_status(struct reset_ctl *reset_ctl) {
> + struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> + struct ast2500_scu *scu = priv->scu;
> + int status;
> +
> + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
> +
> + if (reset_ctl->id < 32)
> + status = BIT(reset_ctl->id) & readl(>sysreset_ctrl1);
> + else
> + status = BIT(reset_ctl->id - 32) & readl(>sysreset_ctrl2);
> +
> + return !!status;
> +}
> +
> +
> +
> static int ast2500_reset_probe(struct udevice *dev) {
> int rc;
> @@ -79,6 +97,7 @@ static const struct udevice_id ast2500_reset_ids[] =
> { struct reset_ops ast2500_reset_ops = {
> .rst_assert = ast2500_reset_assert,
> .rst_deassert = ast2500_reset_deassert,
> + .rst_status = ast2500_reset_status,
> };
>
> U_BOOT_DRIVER(ast2500_reset) = {
> diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c
> index
> 985235a3ac46..1732a450efc0 100644
> --- a/drivers/reset/reset-ast2600.c
> +++ b/drivers/reset/reset-ast2600.c
> @@ -47,6 +47,22 @@ static int ast2600_reset_deassert(struct reset_ctl
> *reset_ctl)
> return 0;
> }
>
> +static int ast2600_reset_status(struct reset_ctl *reset_ctl) {
> + struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> + struct ast2600_scu *scu = priv->scu;
> + int status;
> +
> + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
> +
> + if (reset_ctl->id < 32)
> + status = BIT(reset_ctl->id) & readl(>modrst_ctrl1);
> + else
> + status = BIT(reset_ctl->id - 32) & readl(>modrst_ctrl2);
> +
> + return !!status;
> +}
> +
> static int ast2600_reset_probe(struct udevice *dev) {
> int rc;
> @@ -78,6 +94,7 @@ static const struct udevice_id ast2600_reset_ids[] =
> { struct reset_ops ast2600_reset_ops = {
> .rst_assert = ast2600_reset_assert,
> .rst_deassert = ast2600_reset_deassert,
> + .rst_status = ast2600_reset_status,
> };
>
> U_BOOT_DRIVER(ast2600_reset) = {
> --
> 2.35.1
RE: [PATCH 05/10] ARM: dts: ast2600-evb: Add I2C devices
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 05/10] ARM: dts: ast2600-evb: Add I2C devices
>
> The EVB has an EEPROM on bus 7 and a LM75 temp sensor on bus 8. Enable
> those busses we can test the I2C driver.
>
Hello,
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v5.15/arch/arm/boot/dts/aspeed-ast2600-evb.dts#L662-L687
The eeprom is under the same bus with bus#7. Please add in bus#7.
Bus#8 have LM75. Not have eeprom.
> Signed-off-by: Joel Stanley
> ---
> arch/arm/dts/ast2600-evb.dts | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
> index 0d650543134a..cee787ecc0eb 100644
> --- a/arch/arm/dts/ast2600-evb.dts
> +++ b/arch/arm/dts/ast2600-evb.dts
> @@ -174,6 +174,11 @@
>
> pinctrl-names = "default";
> pinctrl-0 = <_i2c8_default>;
> +
> + temp@2e {
> + compatible = "adi,adt7490";
> + reg = <0x2e>;
> + };
> };
>
> {
> @@ -181,6 +186,12 @@
>
> pinctrl-names = "default";
> pinctrl-0 = <_i2c9_default>;
> +
> + eeprom@50 {
> + compatible = "atmel,24c08";
> + reg = <0x50>;
> + pagesize = <16>;
> + };
> };
>
> {
> --
> 2.35.1
RE: [PATCH 04/10] ARM: dts: ast2500-evb: Add I2C devices
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 04/10] ARM: dts: ast2500-evb: Add I2C devices
>
> The EVB has an EEPROM on bus 3 and a LM75 temp sensor on bus 7. Enable
> those busses we can test the I2C driver.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Ryan Chen
> ---
> arch/arm/dts/ast2500-evb.dts | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
> index 4796ed445f57..874e042bc4cb 100644
> --- a/arch/arm/dts/ast2500-evb.dts
> +++ b/arch/arm/dts/ast2500-evb.dts
> @@ -73,3 +73,22 @@
> pinctrl-names = "default";
> pinctrl-0 = <_sd2_default>;
> };
> +
> + {
> +status = "okay";
> +
> +eeprom@50 {
> +compatible = "atmel,24c08";
> +reg = <0x50>;
> +pagesize = <16>;
> +};
> +};
> +
> + {
> + status = "okay";
> +
> +lm75@4d {
> +compatible = "national,lm75";
> +reg = <0x4d>;
> +};
> +};
> --
> 2.35.1
RE: [PATCH 03/10] ARM: dts: ast2600: Dsiable I2C nodes by default
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 03/10] ARM: dts: ast2600: Dsiable I2C nodes by default
>
> Allow boards to enable the buses they use.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Ryan Chen
> ---
> arch/arm/dts/ast2600.dtsi | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index
> 4b23d25ede0a..a37d062bcad7 100644
> --- a/arch/arm/dts/ast2600.dtsi
> +++ b/arch/arm/dts/ast2600.dtsi
> @@ -868,6 +868,7 @@
> clocks = < ASPEED_CLK_APB2>;
> pinctrl-names = "default";
> pinctrl-0 = <_i2c3_default>;
> + status = "disabled";
> };
>
> i2c3: i2c@200 {
> @@ -883,6 +884,7 @@
> clocks = < ASPEED_CLK_APB2>;
> pinctrl-names = "default";
> pinctrl-0 = <_i2c4_default>;
> + status = "disabled";
> };
>
> i2c4: i2c@280 {
> @@ -898,6 +900,7 @@
> clocks = < ASPEED_CLK_APB2>;
> pinctrl-names = "default";
> pinctrl-0 = <_i2c5_default>;
> + status = "disabled";
> };
>
> i2c5: i2c@300 {
> @@ -913,6 +916,7 @@
> clocks = < ASPEED_CLK_APB2>;
> pinctrl-names = "default";
> pinctrl-0 = <_i2c6_default>;
> + status = "disabled";
> };
>
> i2c6: i2c@380 {
> @@ -928,6 +932,7 @@
> clocks = < ASPEED_CLK_APB2>;
> pinctrl-names = "default";
> pinctrl-0 = <_i2c7_default>;
> + status = "disabled";
> };
>
> i2c7: i2c@400 {
> @@ -943,6 +948,7 @@
> clocks = < ASPEED_CLK_APB2>;
> pinctrl-names = "default";
> pinctrl-0 = <_i2c8_default>;
> + status = "disabled";
> };
>
> i2c8: i2c@480 {
> @@ -958,6 +964,7 @@
> clocks = < ASPEED_CLK_APB2>;
> pinctrl-names = "default";
> pinctrl-0 = <_i2c9_default>;
> + status = "disabled";
> };
>
> i2c9: i2c@500 {
> --
> 2.35.1
RE: [PATCH 02/10] ARM: dts: ast2600: Add I2C reset properties
> -Original Message- > From: joel.s...@gmail.com On Behalf Of Joel Stanley > Sent: Monday, June 20, 2022 3:25 PM > To: Ryan Chen ; BMC-SW > ; Heiko Schocher > Cc: u-boot@lists.denx.de; Cédric Le Goater > Subject: [PATCH 02/10] ARM: dts: ast2600: Add I2C reset properties > > The same as the upstream Linux device tree, each i2c bus has a property > specifying the reset line. > > Signed-off-by: Joel Stanley Reviewed-by: Ryan Chen > --- > arch/arm/dts/ast2600.dtsi | 16 > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index > ef5b131ac0af..4b23d25ede0a 100644 > --- a/arch/arm/dts/ast2600.dtsi > +++ b/arch/arm/dts/ast2600.dtsi > @@ -832,6 +832,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c1_default>; > @@ -847,6 +848,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c2_default>; > @@ -862,6 +864,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c3_default>; > @@ -876,6 +879,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c4_default>; > @@ -890,6 +894,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c5_default>; > @@ -904,6 +909,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c6_default>; > @@ -918,6 +924,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c7_default>; > @@ -932,6 +939,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c8_default>; > @@ -946,6 +954,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c9_default>; > @@ -960,6 +969,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; > clocks = < ASPEED_CLK_APB2>; > pinctrl-names = "default"; > pinctrl-0 = <_i2c10_default>; @@ -975,6 +985,7 @@ > compatible = "aspeed,ast2600-i2c-bus"; > bus-frequency = <10>; > interrupts = ; > + resets = < ASPEED_RESET_I2C>; >
RE: [PATCH 01/10] ARM: dts: ast2600: Add I2C pinctrl
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: Eddie James ; u-boot@lists.denx.de; Cédric Le
> Goater
> Subject: [PATCH 01/10] ARM: dts: ast2600: Add I2C pinctrl
>
> From: Eddie James
>
> Set the pinctrl groups for each I2C bus. These are essential to I2C operating
> correctly.
>
> Signed-off-by: Eddie James
> Signed-off-by: Joel Stanley
Review-by: Ryan Chen
> ---
> arch/arm/dts/ast2600.dtsi | 33 +
> 1 file changed, 33 insertions(+)
>
> diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index
> 64074309b7b2..ef5b131ac0af 100644
> --- a/arch/arm/dts/ast2600.dtsi
> +++ b/arch/arm/dts/ast2600.dtsi
> @@ -833,6 +833,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c1_default>;
> status = "disabled";
> };
>
> @@ -846,6 +848,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c2_default>;
> status = "disabled";
> };
>
> @@ -859,6 +863,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c3_default>;
> };
>
> i2c3: i2c@200 {
> @@ -871,6 +877,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c4_default>;
> };
>
> i2c4: i2c@280 {
> @@ -883,6 +891,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c5_default>;
> };
>
> i2c5: i2c@300 {
> @@ -895,6 +905,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c6_default>;
> };
>
> i2c6: i2c@380 {
> @@ -907,6 +919,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c7_default>;
> };
>
> i2c7: i2c@400 {
> @@ -919,6 +933,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c8_default>;
> };
>
> i2c8: i2c@480 {
> @@ -931,6 +947,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c9_default>;
> };
>
> i2c9: i2c@500 {
> @@ -943,6 +961,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c10_default>;
> status = "disabled";
> };
>
> @@ -956,6 +976,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c11_default>;
> status = "disabled";
> };
>
> @@ -969,6 +991,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK_APB2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c12_default>;
> status = "disabled";
> };
>
> @@ -982,6 +1006,8 @@
> bus-frequency = <10>;
> interrupts = ;
> clocks = < ASPEED_CLK
RE: [PATCH] arm: dts: ast2600: Add I2C pinctrl
> -Original Message-
> From: Joel Stanley
> Sent: Thursday, June 2, 2022 11:40 AM
> To: Eddie James
> Cc: U-Boot Mailing List ; Dylan Hung
> ; Billy Tsai ;
> ChiaWei Wang ; Simon Glass
>
> Subject: Re: [PATCH] arm: dts: ast2600: Add I2C pinctrl
>
> On Wed, 1 Jun 2022 at 16:10, Eddie James wrote:
> >
> > Set the pinctrl groups for each I2C bus. These are essential to I2C
> > operating correctly.
> >
> > Signed-off-by: Eddie James
>
> Reviewed-by: Joel Stanley
>
Reviewed-by: Ryan Chen
> > ---
> > arch/arm/dts/ast2600.dtsi | 33 +
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
> > index 64074309b7..ef5b131ac0 100644
> > --- a/arch/arm/dts/ast2600.dtsi
> > +++ b/arch/arm/dts/ast2600.dtsi
> > @@ -833,6 +833,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c1_default>;
> > status = "disabled";
> > };
> >
> > @@ -846,6 +848,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c2_default>;
> > status = "disabled";
> > };
> >
> > @@ -859,6 +863,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c3_default>;
> > };
> >
> > i2c3: i2c@200 {
> > @@ -871,6 +877,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c4_default>;
> > };
> >
> > i2c4: i2c@280 {
> > @@ -883,6 +891,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c5_default>;
> > };
> >
> > i2c5: i2c@300 {
> > @@ -895,6 +905,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c6_default>;
> > };
> >
> > i2c6: i2c@380 {
> > @@ -907,6 +919,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c7_default>;
> > };
> >
> > i2c7: i2c@400 {
> > @@ -919,6 +933,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c8_default>;
> > };
> >
> > i2c8: i2c@480 {
> > @@ -931,6 +947,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c9_default>;
> > };
> >
> > i2c9: i2c@500 {
> > @@ -943,6 +961,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_i2c10_default>;
> > status = "disabled";
> > };
> >
> > @@ -956,6 +976,8 @@
> > bus-frequency = <10>;
> > interrupts = ;
> > clocks = < ASPEED_CLK_APB2>;
>
RE: [PATCH] i2c: ast_i2c: Remove SCL direct drive mode
> -Original Message- > From: Joel Stanley > Sent: Thursday, May 19, 2022 8:28 AM > To: Eddie James ; Ryan Chen > ; BMC-SW > Cc: U-Boot Mailing List ; h...@denx.de > Subject: Re: [PATCH] i2c: ast_i2c: Remove SCL direct drive mode > > On Wed, 11 May 2022 at 20:52, Eddie James > wrote: > > > > SCL direct drive mode prevents communication with devices that do > > clock stretching, so disable. The Linux driver doesn't use this mode, > > and the engine can handle clock stretching. > > > > Signed-off-by: Eddie James > > Reviewed-by: Joel Stanley > Reviewed-by: ryan_chen > I have added the aspeed team to cc for their review. > > Ryan, we discovered this fix when testing the tpm i2c driver on the ast2600. > Yes, it should remove. Thank for inform. > > --- > > drivers/i2c/ast_i2c.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c index > > 2d3fecaa14..8b24a260c0 100644 > > --- a/drivers/i2c/ast_i2c.c > > +++ b/drivers/i2c/ast_i2c.c > > @@ -76,7 +76,7 @@ static void ast_i2c_init_bus(struct udevice *dev) > > /* Enable Master Mode. Assuming single-master */ > > writel(I2CD_MASTER_EN > >| I2CD_M_SDA_LOCK_EN > > - | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN, > > + | I2CD_MULTI_MASTER_DIS, > >>regs->fcr); > > /* Enable Interrupts */ > > writel(I2CD_INTR_TX_ACK > > -- > > 2.27.0 > >
RE: [PATCH] gpio: aspeed: Fix incorrect offset of read back register.
> -Original Message-
> From: Billy Tsai
> Sent: Wednesday, April 13, 2022 1:35 PM
> To: Ryan Chen ; ChiaWei Wang
> ; BMC-SW ;
> and...@aj.id.au; Billy Tsai ;
> u-boot@lists.denx.de
> Subject: [PATCH] gpio: aspeed: Fix incorrect offset of read back register.
>
> The offset of the current read back register is the value of the gpio pin,
> not the
> value written for the gpio output.
> This patch fix it to avoid the other gpio output value controlled by the same
> register being set incorrectly.
>
> Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver")
> Signed-off-by: Billy Tsai
Review-by: ryan_chen
> ---
> drivers/gpio/gpio-aspeed.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index
> a8a2afcb5c..2c5415c671 100644
> --- a/drivers/gpio/gpio-aspeed.c
> +++ b/drivers/gpio/gpio-aspeed.c
> @@ -211,7 +211,7 @@ static int aspeed_gpio_direction_output(struct udevice
> *dev, unsigned int offset
> struct aspeed_gpio_priv *priv = dev_get_priv(dev);
> const struct aspeed_gpio_bank *bank = to_bank(offset);
> u32 dir = readl(bank_reg(priv, bank, reg_dir));
> - u32 output = readl(bank_reg(priv, bank, reg_val));
> + u32 output = readl(bank_reg(priv, bank, reg_rdata));
>
> dir |= GPIO_BIT(offset);
> writel(dir, bank_reg(priv, bank, reg_dir)); @@ -239,7 +239,7 @@
> aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value) {
> struct aspeed_gpio_priv *priv = dev_get_priv(dev);
> const struct aspeed_gpio_bank *bank = to_bank(offset);
> - u32 data = readl(bank_reg(priv, bank, reg_val));
> + u32 data = readl(bank_reg(priv, bank, reg_rdata));
>
> if (value)
> data |= GPIO_BIT(offset);
> --
> 2.25.1
RE: [PATCH 0/3] gpio: Add AST2[456]00 GPIO driver
Hello Andrew, This patch series are ok, Please help add Reviewed-by: Ryan Chen > -Original Message- > From: Andrew Jeffery > Sent: Wednesday, February 16, 2022 7:57 AM > To: u-boot@lists.denx.de > Cc: max...@google.com; ChiaWei Wang ; > Ryan Chen ; Troy Lee > ; BMC-SW ; > j...@jms.id.au; eaja...@linux.ibm.com > Subject: [PATCH 0/3] gpio: Add AST2[456]00 GPIO driver > > Hello, > > This series adds support for the GPIO controller found in Aspeed's AST2400, > AST2500 and AST2600 BMC SoCs. > > By and large I've just extracted the work from Aspeed's SDK and submitted it. > However, the driver as found in the SDK was in-turn extracted from Linux, cut > down and adapted to u-boot. I've adjusted the copyright to reflect this (as > found in Linux) after discussion with Troy and Ryan. > > From there I've polished the patch in accordance with checkpatch and done > some tweaks to improve consistency with the kernel driver (mainly the file > name). > > I've lightly tested the driver as-presented under qemu. That said, as the code > has been lifted from Aspeed's SDK (and in-turn from Linux) the implementation > has seen much wider testing. > > Please review! > > Andrew > > Andrew Jeffery (3): > gpio: Add Aspeed GPIO driver > ARM: dts: ast2500: Add ngpios property to GPIO node > configs: evb-ast2[56]00: Enable GPIO control > > arch/arm/dts/ast2500.dtsi | 1 + > configs/evb-ast2500_defconfig | 3 + > configs/evb-ast2600_defconfig | 3 + > drivers/gpio/Kconfig | 7 + > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio-aspeed.c| 299 > ++ > 6 files changed, 314 insertions(+) > create mode 100644 drivers/gpio/gpio-aspeed.c > > -- > 2.32.0
RE: [PATCH] drivers: net: add Aspeed MDIO driver
> -Original Message-
> From: Dylan Hung
> Sent: Tuesday, November 2, 2021 1:42 PM
> To: u-boot@lists.denx.de; joe.hershber...@ni.com; rfried@gmail.com;
> Ryan Chen ; ChiaWei Wang
>
> Cc: BMC-SW
> Subject: [PATCH] drivers: net: add Aspeed MDIO driver
>
> Add a driver for the MDIO interface for Aspeed AST2600 SOC. The driver
> only supports clause 22 for now.
>
> Signed-off-by: Dylan Hung
Reviewed-by: Ryan Chen
> ---
> drivers/net/Kconfig | 7 +++
> drivers/net/Makefile | 1 +
> drivers/net/aspeed_mdio.c | 128
> ++
> 3 files changed, 136 insertions(+)
> create mode 100644 drivers/net/aspeed_mdio.c
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index
> 6c12959f37..4638180b74 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -826,6 +826,13 @@ config FSL_LS_MDIO
> This driver supports the MDIO bus found on the Fman 10G Ethernet
> MACs and
> on the mEMAC (which supports both Clauses 22 and 45).
>
> +config ASPEED_MDIO
> + bool "Aspeed MDIO interface support"
> + depends on DM_MDIO
> + help
> + This driver supports the MDIO bus of Aspeed AST2600 SOC. The
> driver
> + currently supports Clause 22.
> +
> config MDIO_MUX_MMIOREG
> bool "MDIO MUX accessed as a MMIO register access"
> depends on DM_MDIO_MUX
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile index
> e4078d15a9..fe6c00fa48 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -101,3 +101,4 @@ obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
> obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
> obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
> obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
> +obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o
> diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c new file
> mode 100644 index 00..a99715a728
> --- /dev/null
> +++ b/drivers/net/aspeed_mdio.c
> @@ -0,0 +1,128 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Aspeed MDIO driver
> + *
> + * (C) Copyright 2021 Aspeed Technology Inc.
> + *
> + * This file is inspired from the Linux kernel driver
> +drivers/net/phy/mdio-aspeed.c */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define ASPEED_MDIO_CTRL 0x0
> +#define ASPEED_MDIO_CTRL_FIRE BIT(31)
> +#define ASPEED_MDIO_CTRL_STBIT(28)
> +#define ASPEED_MDIO_CTRL_ST_C45 0
> +#define ASPEED_MDIO_CTRL_ST_C22 1
> +#define ASPEED_MDIO_CTRL_OPGENMASK(27, 26)
> +#define MDIO_C22_OP_WRITE0b01
> +#define MDIO_C22_OP_READ 0b10
> +#define ASPEED_MDIO_CTRL_PHYAD GENMASK(25, 21)
> +#define ASPEED_MDIO_CTRL_REGAD GENMASK(20, 16)
> +#define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)
> +
> +#define ASPEED_MDIO_DATA 0x4
> +#define ASPEED_MDIO_DATA_MDC_THRES GENMASK(31, 24)
> +#define ASPEED_MDIO_DATA_MDIO_EDGE BIT(23)
> +#define ASPEED_MDIO_DATA_MDIO_LATCHGENMASK(22, 20)
> +#define ASPEED_MDIO_DATA_IDLE BIT(16)
> +#define ASPEED_MDIO_DATA_MIIRDATA GENMASK(15, 0)
> +
> +#define ASPEED_MDIO_TIMEOUT_US 1000
> +
> +struct aspeed_mdio_priv {
> + void *base;
> +};
> +
> +static int aspeed_mdio_read(struct udevice *mdio_dev, int addr, int
> +devad, int reg) {
> + struct aspeed_mdio_priv *priv = dev_get_priv(mdio_dev);
> + u32 ctrl;
> + u32 data;
> + int rc;
> +
> + if (devad != MDIO_DEVAD_NONE)
> + return -EOPNOTSUPP;
> +
> + ctrl = ASPEED_MDIO_CTRL_FIRE
> + | FIELD_PREP(ASPEED_MDIO_CTRL_ST,
> ASPEED_MDIO_CTRL_ST_C22)
> + | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_READ)
> + | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr)
> + | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, reg);
> +
> + writel(ctrl, priv->base + ASPEED_MDIO_CTRL);
> +
> + rc = readl_poll_timeout(priv->base + ASPEED_MDIO_DATA, data,
> + data & ASPEED_MDIO_DATA_IDLE,
> + ASPEED_MDIO_TIMEOUT_US);
> +
> + if (rc < 0)
> + return rc;
> +
> + return FIELD_GET(ASPEED_MDIO_DATA_MIIRDATA, data); }
> +
> +static int aspeed_mdio_write(struct udevice *mdio_dev, int addr, int
> +devad, int reg, u16 val) {
> + struct aspeed_mdio_priv *priv = dev_get_priv(mdio_dev);
> + u32 ctrl;
> +
> + if (devad != MDIO_DEVAD_NONE)
&g
RE: [PATCH] ARM: dts: ast2600: Make WDT by default disabled
> -Original Message-
> From: ChiaWei Wang
> Sent: Thursday, September 16, 2021 2:10 PM
> To: u-boot@lists.denx.de
> Cc: Ryan Chen
> Subject: [PATCH] ARM: dts: ast2600: Make WDT by default disabled
>
> The WDT devices described in the general .dtsi file should be marked as
> "disabled" by default.
>
> A WDT should be then enabled in the board specific .dts file on demands.
>
> Signed-off-by: Chia-Wei Wang
Reviewed-by: Ryan Chen
> ---
> arch/arm/dts/ast2600.dtsi | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index
> ac0f08b7ea..f121f547e6 100644
> --- a/arch/arm/dts/ast2600.dtsi
> +++ b/arch/arm/dts/ast2600.dtsi
> @@ -474,21 +474,25 @@
> wdt1: watchdog@1e785000 {
> compatible = "aspeed,ast2600-wdt";
> reg = <0x1e785000 0x40>;
> + status = "disabled";
> };
>
> wdt2: watchdog@1e785040 {
> compatible = "aspeed,ast2600-wdt";
> reg = <0x1e785040 0x40>;
> + status = "disabled";
> };
>
> wdt3: watchdog@1e785080 {
> compatible = "aspeed,ast2600-wdt";
> reg = <0x1e785080 0x40>;
> + status = "disabled";
> };
>
> wdt4: watchdog@1e7850C0 {
> compatible = "aspeed,ast2600-wdt";
> reg = <0x1e7850C0 0x40>;
> + status = "disabled";
> };
>
> lpc: lpc@1e789000 {
> --
> 2.17.1
RE: [PATCH 7/7] configs: aspeed: Add defconfig for AST2600 EVB
> -Original Message- > From: ChiaWei Wang > Sent: Monday, December 14, 2020 1:54 PM > To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen > > Cc: BMC-SW > Subject: [PATCH 7/7] configs: aspeed: Add defconfig for AST2600 EVB > > Add the default configuration for the AST2600 EVB. > > Signed-off-by: Chia-Wei, Wang Reviewed-by: Ryan Chen > --- > configs/evb-ast2600_defconfig | 69 > +++ > 1 file changed, 69 insertions(+) > create mode 100644 configs/evb-ast2600_defconfig > > diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig > new file mode 100644 index 00..003fedd02a > --- /dev/null > +++ b/configs/evb-ast2600_defconfig > @@ -0,0 +1,69 @@ > +CONFIG_ARM=y > +CONFIG_SYS_DCACHE_OFF=y > +CONFIG_ARCH_ASPEED=y > +CONFIG_SYS_TEXT_BASE=0x1 > +CONFIG_ASPEED_AST2600=y > +CONFIG_TARGET_EVB_AST2600=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_SYS_MALLOC_F_LEN=0x800 > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_ENV_SIZE=0x1 > +CONFIG_SPL_SERIAL_SUPPORT=y > +CONFIG_SPL_SIZE_LIMIT=0x1 > +CONFIG_SPL=y > +# CONFIG_ARMV7_NONSEC is not set > +CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb" > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y # > +CONFIG_LEGACY_IMAGE_FORMAT is not set CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw" > +CONFIG_USE_BOOTCOMMAND=y > +CONFIG_BOOTCOMMAND="bootm 2010" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y > +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y > +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set > +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_DM_RESET=y > +CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y > CONFIG_HUSH_PARSER=y > +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y > CONFIG_CMD_MII=y > +CONFIG_CMD_PING=y CONFIG_SPL_OF_CONTROL=y > CONFIG_ENV_OVERWRITE=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y > +CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y > CONFIG_DM_I2C=y > +CONFIG_MISC=y CONFIG_SPL_MISC=y CONFIG_DM_MMC=y > CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_ASPEED=y CONFIG_PHY_REALTEK=y > CONFIG_DM_ETH=y > +CONFIG_FTGMAC100=y CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_RAM=y > +CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y > +CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y > +CONFIG_WDT=y CONFIG_HEXDUMP=y # CONFIG_SPL_HEXDUMP is not set # > +CONFIG_EFI_LOADER is not set > -- > 2.17.1
RE: [PATCH 6/7] aspeed: Add AST2600 platform support
> -Original Message- > From: ChiaWei Wang > Sent: Monday, December 14, 2020 1:54 PM > To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen > > Cc: BMC-SW > Subject: [PATCH 6/7] aspeed: Add AST2600 platform support > > Add low level platform initialization for the AST2600 SoC. > The 2-stage booting with U-Boot SPL are leveraged to support different booting > mode. > > However, currently the patch supports only the booting from memory-mapped > SPI flash. > > Signed-off-by: Chia-Wei, Wang Reviewed-by: Ryan Chen > --- > arch/arm/include/asm/arch-aspeed/boot0.h | 23 ++ > arch/arm/include/asm/arch-aspeed/platform.h | 5 + > arch/arm/mach-aspeed/Kconfig | 20 ++ > arch/arm/mach-aspeed/Makefile| 1 + > arch/arm/mach-aspeed/ast2600/Kconfig | 17 ++ > arch/arm/mach-aspeed/ast2600/Makefile| 2 + > arch/arm/mach-aspeed/ast2600/board_common.c | 105 + > arch/arm/mach-aspeed/ast2600/lowlevel_init.S | 233 +++ > arch/arm/mach-aspeed/ast2600/spl.c | 55 + > board/aspeed/evb_ast2600/Kconfig | 12 + > board/aspeed/evb_ast2600/Makefile| 1 + > board/aspeed/evb_ast2600/evb_ast2600.c | 5 + > drivers/sysreset/sysreset_ast.c | 5 + > include/configs/evb_ast2600.h| 16 ++ > 14 files changed, 500 insertions(+) > create mode 100644 arch/arm/include/asm/arch-aspeed/boot0.h > create mode 100644 arch/arm/mach-aspeed/ast2600/Kconfig > create mode 100644 arch/arm/mach-aspeed/ast2600/Makefile > create mode 100644 arch/arm/mach-aspeed/ast2600/board_common.c > create mode 100644 arch/arm/mach-aspeed/ast2600/lowlevel_init.S > create mode 100644 arch/arm/mach-aspeed/ast2600/spl.c > create mode 100644 board/aspeed/evb_ast2600/Kconfig create mode > 100644 board/aspeed/evb_ast2600/Makefile create mode 100644 > board/aspeed/evb_ast2600/evb_ast2600.c > create mode 100644 include/configs/evb_ast2600.h > > diff --git a/arch/arm/include/asm/arch-aspeed/boot0.h > b/arch/arm/include/asm/arch-aspeed/boot0.h > new file mode 100644 > index 00..368becc87a > --- /dev/null > +++ b/arch/arm/include/asm/arch-aspeed/boot0.h > @@ -0,0 +1,23 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (c) Aspeed Technology Inc. > + */ > + > +#ifndef _ASM_ARCH_BOOT0_H > +#define _ASM_ARCH_BOOT0_H > + > +_start: > + ARM_VECTORS > + > + .word 0x0 /* key location */ > + .word 0x0 /* start address of image */ > + .word 0xfc00 /* maximum image size: 63KB */ > + .word 0x0 /* signature address */ > + .word 0x0 /* header revision ID low */ > + .word 0x0 /* header revision ID high */ > + .word 0x0 /* reserved */ > + .word 0x0 /* checksum */ > + .word 0x0 /* BL2 secure header */ > + .word 0x0 /* public key or digest offset for BL2 */ > + > +#endif > diff --git a/arch/arm/include/asm/arch-aspeed/platform.h > b/arch/arm/include/asm/arch-aspeed/platform.h > index 6cee036f54..d50ec5f8a9 100644 > --- a/arch/arm/include/asm/arch-aspeed/platform.h > +++ b/arch/arm/include/asm/arch-aspeed/platform.h > @@ -13,6 +13,11 @@ > #define ASPEED_DRAM_BASE 0x8000 > #define ASPEED_SRAM_BASE 0x1e72 > #define ASPEED_SRAM_SIZE 0x9000 > +#elif defined(CONFIG_ASPEED_AST2600) > +#define ASPEED_MAC_COUNT 4 > +#define ASPEED_DRAM_BASE 0x8000 > +#define ASPEED_SRAM_BASE 0x1000 > +#define ASPEED_SRAM_SIZE 0x1 > #else > #err "Unrecognized Aspeed platform." > #endif > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig > index 4f021baa06..9a725f195a 100644 > --- a/arch/arm/mach-aspeed/Kconfig > +++ b/arch/arm/mach-aspeed/Kconfig > @@ -9,6 +9,11 @@ config SYS_SOC > config SYS_TEXT_BASE > default 0x > > +choice > + prompt "Aspeed SoC select" > + depends on ARCH_ASPEED > + default ASPEED_AST2500 > + > config ASPEED_AST2500 > bool "Support Aspeed AST2500 SoC" > depends on DM_RESET > @@ -18,6 +23,21 @@ config ASPEED_AST2500 > It is used as Board Management Controller on many server boards, > which is enabled by support of LPC and eSPI peripherals. > > +config ASPEED_AST2600 > + bool "Support Aspeed AST2600 SoC" > + select CPU_V7A > + select CPU_V7_HAS_NONSEC > + select SYS_ARCH_TIMER > + select SUPPORT_SPL > + select ENABLE_ARM_SOC_BOOT0_HOOK > + help > + The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU. > + It is used as B
RE: [PATCH 5/7] ARM: dts: aspeed: Add AST2600 SoC support
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, December 14, 2020 1:54 PM
> To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen
>
> Cc: BMC-SW
> Subject: [PATCH 5/7] ARM: dts: aspeed: Add AST2600 SoC support
>
> AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote
> Management Processor.
>
> AST2600 has significant performance improvement by integrating 1.2GHz
> dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also
> improved with more features and better performance than preceding
> AST24xx/AST25xx.
>
> Signed-off-by: Chia-Wei, Wang
Reviewed-by: Ryan Chen
> ---
> arch/arm/dts/Makefile|1 +
> arch/arm/dts/ast2600-evb.dts | 179 +++
> arch/arm/dts/ast2600-u-boot.dtsi | 44 +
> arch/arm/dts/ast2600.dtsi| 1946
> ++
> 4 files changed, 2170 insertions(+)
> create mode 100644 arch/arm/dts/ast2600-evb.dts create mode 100644
> arch/arm/dts/ast2600-u-boot.dtsi create mode 100644
> arch/arm/dts/ast2600.dtsi
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> 02d04f5a8c..3e501b0f35 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -947,6 +947,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \
> dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
>
> dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
> +dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
>
> dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
>
> diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts new
> file mode 100644 index 00..2abd31341c
> --- /dev/null
> +++ b/arch/arm/dts/ast2600-evb.dts
> @@ -0,0 +1,179 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/dts-v1/;
> +
> +#include "ast2600-u-boot.dtsi"
> +
> +/ {
> + memory {
> + device_type = "memory";
> + reg = <0x8000 0x4000>;
> + };
> +
> + chosen {
> + stdout-path =
> + };
> +
> + aliases {
> + mmc0 = _slot0;
> + mmc1 = _slot0;
> + mmc2 = _slot1;
> + spi0 =
> + spi1 =
> + spi2 =
> + ethernet0 =
> + ethernet1 =
> + ethernet2 =
> + ethernet3 =
> + };
> +
> + cpus {
> + cpu@0 {
> + clock-frequency = <8>;
> + };
> + cpu@1 {
> + clock-frequency = <8>;
> + };
> + };
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> + {
> + clock-frequency = <4>;
> +};
> +
> + {
> + status = "okay";
> +};
> +
> + {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_fmcquad_default>;
> +
> + flash@0 {
> + compatible = "spi-flash", "sst,w25q256";
> + status = "okay";
> + spi-max-frequency = <5000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + };
> +
> + flash@1 {
> + compatible = "spi-flash", "sst,w25q256";
> + status = "okay";
> + spi-max-frequency = <5000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + };
> +
> + flash@2 {
> + compatible = "spi-flash", "sst,w25q256";
> + status = "okay";
> + spi-max-frequency = <5000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + };
> +};
> +
> + {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_spi1_default _spi1abr_default
> + _spi1cs1_default _spi1wp_default
> + _spi1wp_default _spi1quad_default>;
> +
> + flash@0 {
> + compatible = "spi-flash", "sst,w25q256";
> + status = "okay";
> + spi-max-frequency = <5000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + };
> +};
> +
> + {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_spi2_default _spi2cs1_default
> + _spi2cs2_default _s
RE: [PATCH 4/7] reset: aspeed: Add AST2600 reset support
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, December 14, 2020 1:54 PM
> To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen
>
> Cc: BMC-SW
> Subject: [PATCH 4/7] reset: aspeed: Add AST2600 reset support
>
> Add controller reset support through the System Control Unit (SCU) of AST2600
> SoC.
>
> Signed-off-by: Chia-Wei, Wang
Reviewed-by: Ryan Chen
> ---
> drivers/reset/Kconfig | 9 ++
> drivers/reset/Makefile| 1 +
> drivers/reset/reset-ast2600.c | 108
> ++
> include/dt-bindings/reset/ast2600-reset.h | 70 ++
> 4 files changed, 188 insertions(+)
> create mode 100644 drivers/reset/reset-ast2600.c create mode 100644
> include/dt-bindings/reset/ast2600-reset.h
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index
> 33c2736554..f5b3f8826f 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -81,6 +81,15 @@ config RESET_AST2500
> Say Y if you want to control reset signals of different peripherals
> through System Control Unit (SCU).
>
> +config RESET_AST2600
> + bool "Reset controller driver for AST2600 SoCs"
> + depends on DM_RESET
> + default y if ASPEED_AST2600
> + help
> + Support for reset controller on AST2600 SoC.
> + Say Y if you want to control reset signals of different peripherals
> + through System Control Unit (SCU).
> +
> config RESET_ROCKCHIP
> bool "Reset controller driver for Rockchip SoCs"
> depends on DM_RESET && ARCH_ROCKCHIP && CLK diff --git
> a/drivers/reset/Makefile b/drivers/reset/Makefile index
> fa52aa3329..8a0f528076 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
> obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
> obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
> +obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
> obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
> obj-$(CONFIG_RESET_MESON) += reset-meson.o
> obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git
> a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c new file mode
> 100644 index 00..c402968fa8
> --- /dev/null
> +++ b/drivers/reset/reset-ast2600.c
> @@ -0,0 +1,108 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2020 ASPEED Technology Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct ast2600_reset_priv {
> + struct ast2600_scu *scu;
> +};
> +
> +static int ast2600_reset_request(struct reset_ctl *reset_ctl) {
> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
> + reset_ctl->dev, reset_ctl->id);
> +
> + return 0;
> +}
> +
> +static int ast2600_reset_free(struct reset_ctl *reset_ctl) {
> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
> + reset_ctl->dev, reset_ctl->id);
> +
> + return 0;
> +}
> +
> +static int ast2600_reset_assert(struct reset_ctl *reset_ctl) {
> + struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> + struct ast2600_scu *scu = priv->scu;
> +
> + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
> +
> + if (reset_ctl->id < 32)
> + writel(BIT(reset_ctl->id), scu->modrst_ctrl1);
> + else
> + writel(BIT(reset_ctl->id - 32), scu->modrst_ctrl2);
> +
> + return 0;
> +}
> +
> +static int ast2600_reset_deassert(struct reset_ctl *reset_ctl) {
> + struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> + struct ast2600_scu *scu = priv->scu;
> +
> + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
> +
> + if (reset_ctl->id < 32)
> + writel(BIT(reset_ctl->id), scu->modrst_clr1);
> + else
> + writel(BIT(reset_ctl->id - 32), scu->modrst_clr2);
> +
> + return 0;
> +}
> +
> +static int ast2600_reset_probe(struct udevice *dev) {
> + int rc;
> + struct ast2600_reset_priv *priv = dev_get_priv(dev);
> + struct udevice *scu_dev;
> +
> + /* get SCU base from clock device */
> + rc = uclass_get_device_by_driver(UCLASS_CLK,
> + DM_GET_DRIVER(aspeed_ast2600_scu),
> _dev);
> + if (rc) {
> + debug("%s: clock device n
RE: [PATCH 3/7] wdt: aspeed: Add AST2600 watchdog support
> -Original Message- > From: ChiaWei Wang > Sent: Monday, December 14, 2020 1:54 PM > To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen > > Cc: BMC-SW > Subject: [PATCH 3/7] wdt: aspeed: Add AST2600 watchdog support > > AST2600 has 8 watchdog timers including 8 sets of 32-bit decrement counters, > based on 1MHz clock. > > A 64-bit reset mask is also supported to specify which controllers should be > reset by the WDT reset. > > Signed-off-by: Chia-Wei, Wang Reviewed-by: Ryan Chen > --- > .../arm/include/asm/arch-aspeed/wdt_ast2600.h | 129 ++ > drivers/watchdog/Kconfig | 9 ++ > drivers/watchdog/Makefile | 1 + > drivers/watchdog/ast2600_wdt.c| 110 +++ > 4 files changed, 249 insertions(+) > create mode 100644 arch/arm/include/asm/arch-aspeed/wdt_ast2600.h > create mode 100644 drivers/watchdog/ast2600_wdt.c > > diff --git a/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h > b/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h > new file mode 100644 > index 00..96e8ca07e3 > --- /dev/null > +++ b/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h > @@ -0,0 +1,129 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (c) 2020 Aspeed Technology Inc. > + */ > + > +#ifndef _ASM_ARCH_WDT_AST2600_H > +#define _ASM_ARCH_WDT_AST2600_H > + > +#define WDT_BASE 0x1e785000 > + > +/* > + * Special value that needs to be written to counter_restart register > +to > + * (re)start the timer > + */ > +#define WDT_COUNTER_RESTART_VAL 0x4755 > + > +/* reset mode */ > +#define WDT_RESET_MODE_SOC 0 > +#define WDT_RESET_MODE_CHIP 1 > +#define WDT_RESET_MODE_CPU 2 > + > +/* bit-fields of WDT control register */ > +#define WDT_CTRL_2ND_BOOTBIT(7) > +#define WDT_CTRL_RESET_MODE_MASK GENMASK(6, 5) > +#define WDT_CTRL_RESET_MODE_SHIFT5 > +#define WDT_CTRL_CLK1MHZ BIT(4) > +#define WDT_CTRL_RESET BIT(1) > +#define WDT_CTRL_EN BIT(0) > + > +/* bit-fields of WDT reset mask1 register */ > +#define WDT_RESET_MASK1_RVAS BIT(25) > +#define WDT_RESET_MASK1_GPIO1BIT(24) > +#define WDT_RESET_MASK1_XDMA2BIT(23) > +#define WDT_RESET_MASK1_XDMA1BIT(22) > +#define WDT_RESET_MASK1_MCTP2BIT(21) > +#define WDT_RESET_MASK1_MCTP1BIT(20) > +#define WDT_RESET_MASK1_JTAG1BIT(19) > +#define WDT_RESET_MASK1_SD_SDIO1 BIT(18) > +#define WDT_RESET_MASK1_MAC2 BIT(17) > +#define WDT_RESET_MASK1_MAC1 BIT(16) > +#define WDT_RESET_MASK1_GPMCUBIT(15) > +#define WDT_RESET_MASK1_DPMCUBIT(14) > +#define WDT_RESET_MASK1_DP BIT(13) > +#define WDT_RESET_MASK1_HAC BIT(12) > +#define WDT_RESET_MASK1_VIDEOBIT(11) > +#define WDT_RESET_MASK1_CRT BIT(10) > +#define WDT_RESET_MASK1_GCRT BIT(9) > +#define WDT_RESET_MASK1_USB11_UHCI BIT(8) > +#define WDT_RESET_MASK1_USB_PORTABIT(7) > +#define WDT_RESET_MASK1_USB_PORTBBIT(6) > +#define WDT_RESET_MASK1_COPROC BIT(5) > +#define WDT_RESET_MASK1_SOC BIT(4) > +#define WDT_RESET_MASK1_SLI BIT(3) > +#define WDT_RESET_MASK1_AHB BIT(2) > +#define WDT_RESET_MASK1_SDRAMBIT(1) > +#define WDT_RESET_MASK1_ARM BIT(0) > + > +/* bit-fields of WDT reset mask2 register */ > +#define WDT_RESET_MASK2_ESPI BIT(26) > +#define WDT_RESET_MASK2_I3C_BUS8 BIT(25) > +#define WDT_RESET_MASK2_I3C_BUS7 BIT(24) > +#define WDT_RESET_MASK2_I3C_BUS6 BIT(23) > +#define WDT_RESET_MASK2_I3C_BUS5 BIT(22) > +#define WDT_RESET_MASK2_I3C_BUS4 BIT(21) > +#define WDT_RESET_MASK2_I3C_BUS3 BIT(20) > +#define WDT_RESET_MASK2_I3C_BUS2 BIT(19) > +#define WDT_RESET_MASK2_I3C_BUS1 BIT(18) > +#define WDT_RESET_MASK2_I3C_GLOBAL BIT(17) > +#define WDT_RESET_MASK2_I2C BIT(16) > +#define WDT_RESET_MASK2_FSI BIT(15) > +#define WDT_RESET_MASK2_ADC BIT(14) > +#define WDT_RESET_MASK2_PWM BIT(13) > +#define WDT_RESET_MASK2_PECI BIT(12) > +#define WDT_RESET_MASK2_LPC BIT(11) > +#define WDT_RESET_MASK2_MDC_MDIO BIT(10) > +#define WDT_RESET_MASK2_GPIO2BIT(9) > +#define WDT_RESET_MASK2_JTAG2BIT(8) > +#define WDT_RESET_MASK2_SD_SDIO2 BIT(7) > +#define WDT_RESET_MASK2_MAC4 BIT(6) > +#define WDT_RESET_MASK2_MAC3 BIT(5) > +#define WDT_RESET_MASK2_SOC
RE: [PATCH 2/7] ram: aspeed: Add AST2600 DRAM control support
> -Original Message- > From: ChiaWei Wang > Sent: Monday, December 14, 2020 1:54 PM > To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen > > Cc: BMC-SW ; Dylan Hung > > Subject: [PATCH 2/7] ram: aspeed: Add AST2600 DRAM control support > > From: Dylan Hung > > AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. > The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), > 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported. > > Signed-off-by: Dylan Hung > Signed-off-by: Chia-Wei, Wang Reviewed-by: Ryan Chen > --- > .../include/asm/arch-aspeed/sdram_ast2600.h | 163 +++ > drivers/ram/aspeed/Kconfig| 61 +- > drivers/ram/aspeed/Makefile |3 +- > drivers/ram/aspeed/sdram_ast2600.c| 1061 > + > 4 files changed, 1286 insertions(+), 2 deletions(-) create mode 100644 > arch/arm/include/asm/arch-aspeed/sdram_ast2600.h > create mode 100644 drivers/ram/aspeed/sdram_ast2600.c > > diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h > b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h > new file mode 100644 > index 00..d2408c0020 > --- /dev/null > +++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h > @@ -0,0 +1,163 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (c) Aspeed Technology Inc. > + */ > +#ifndef _ASM_ARCH_SDRAM_AST2600_H > +#define _ASM_ARCH_SDRAM_AST2600_H > + > +/* keys for unlocking HW */ > +#define SDRAM_UNLOCK_KEY 0xFC600309 > +#define SDRAM_VIDEO_UNLOCK_KEY 0x00440003 > + > +/* Fixed priority DRAM Requests mask */ > +#define REQ_PRI_VGA_HW_CURSOR_R 0 > +#define REQ_PRI_VGA_CRT_R 1 > +#define REQ_PRI_SOC_DISPLAY_CTRL_R 2 > +#define REQ_PRI_PCIE_BUS1_RW3 > +#define REQ_PRI_VIDEO_HIGH_PRI_W4 > +#define REQ_PRI_CPU_RW 5 > +#define REQ_PRI_SLI_RW 6 > +#define REQ_PRI_PCIE_BUS2_RW7 > +#define REQ_PRI_USB2_0_HUB_EHCI1_DMA_RW 8 #define > +REQ_PRI_USB2_0_DEV_EHCI2_DMA_RW 9 > +#define REQ_PRI_USB1_1_UHCI_HOST_RW 10 > +#define REQ_PRI_AHB_BUS_RW 11 > +#define REQ_PRI_CM3_DATA_RW 12 > +#define REQ_PRI_CM3_INST_R 13 > +#define REQ_PRI_MAC0_DMA_RW 14 > +#define REQ_PRI_MAC1_DMA_RW 15 > +#define REQ_PRI_SDIO_DMA_RW 16 > +#define REQ_PRI_PILOT_ENGINE_RW 17 > +#define REQ_PRI_XDMA1_RW18 > +#define REQ_PRI_MCTP1_RW19 > +#define REQ_PRI_VIDEO_FLAG_RW 20 > +#define REQ_PRI_VIDEO_LOW_PRI_W 21 > +#define REQ_PRI_2D_ENGINE_DATA_RW 22 > +#define REQ_PRI_ENC_ENGINE_RW 23 > +#define REQ_PRI_MCTP2_RW24 > +#define REQ_PRI_XDMA2_RW25 > +#define REQ_PRI_ECC_RSA_RW 26 > + > +#define MCR30_RESET_DLL_DELAY_EN BIT(4) > +#define MCR30_MODE_REG_SEL_SHIFT 1 > +#define MCR30_MODE_REG_SEL_MASK GENMASK(3, 1) > +#define MCR30_SET_MODE_REG BIT(0) > + > +#define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_SHIFT) | > +MCR30_SET_MODE_REG) > + > +#define MCR34_SELF_REFRESH_STATUS_MASK GENMASK(30, 28) > + > +#define MCR34_ODT_DELAY_SHIFT12 > +#define MCR34_ODT_DELAY_MASK GENMASK(15, 12) > +#define MCR34_ODT_EXT_SHIFT 10 > +#define MCR34_ODT_EXT_MASK GENMASK(11, 10) > +#define MCR34_ODT_AUTO_ONBIT(9) > +#define MCR34_ODT_EN BIT(8) > +#define MCR34_RESETN_DIS BIT(7) > +#define MCR34_MREQI_DIS BIT(6) > +#define MCR34_MREQ_BYPASS_DISBIT(5) > +#define MCR34_RGAP_CTRL_EN BIT(4) > +#define MCR34_CKE_OUT_IN_SELF_REF_DISBIT(3) > +#define MCR34_FOURCE_SELF_REF_EN BIT(2) > +#define MCR34_AUTOPWRDN_EN BIT(1) > +#define MCR34_CKE_EN BIT(0) > + > +#define MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT 16 > +#define MCR38_RW_MAX_GRANT_CNT_RQ_MASK GENMASK(20, 16) > + > +/* default request queued limitation mask (0xFFBBFFF4) */ > +#define MCR3C_DEFAULT_MASK > \ > + ~(REQ_PRI_VGA_HW_CURSOR_R | REQ_PRI_VGA_CRT_R | > REQ_PRI_PCIE_BUS1_RW | \ > + REQ_PRI_XDMA1_RW | REQ_PRI_2D_ENGINE_DATA_RW) > + > +#define MCR50_RESET_ALL_INTR BIT(31) > +#define SDRAM_CONF_ECC_AUTO_SCRUBBINGBIT(9) > +#define SDRAM_CONF_SCRAMBLE BIT(8) > +#define SDRAM_CONF_ECC_ENBIT(7) > +#define SDRAM_CONF_DUALX8BIT(5) > +#define SDRAM_CONF_DDR4 BIT(4) > +#define SDRAM_CONF_VGA_SIZE_SHIFT2
RE: [v2 2/2] cosmetic: reset: ast2500: Rename driver and configs
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, October 12, 2020 10:36 AM
> To: tr...@konsulko.com; u-boot@lists.denx.de; max...@google.com
> Cc: Ryan Chen ; BMC-SW
>
> Subject: [v2 2/2] cosmetic: reset: ast2500: Rename driver and configs
>
> 1. Rename AST2500 reset driver from ast2500-reset.c
>to reset-ast2500.c
> 2. Rename AST2500 reset kconfig option from AST2500_RESET
>to RESET_AST2500
>
> Signed-off-by: Chia-Wei, Wang
Reviewed-by: Ryan Chen
> ---
> drivers/reset/Kconfig | 2 +-
> drivers/reset/{ast2500-reset.c => reset-ast2500.c} | 0
> 2 files changed, 1 insertion(+), 1 deletion(-) rename
> drivers/reset/{ast2500-reset.c => reset-ast2500.c} (100%)
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index
> 8b243fdcc6..33c2736554 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -72,7 +72,7 @@ config RESET_UNIPHIER
> Say Y if you want to control reset signals provided by System Control
> block, Media I/O block, Peripheral Block.
>
> -config AST2500_RESET
> +config RESET_AST2500
> bool "Reset controller driver for AST2500 SoCs"
> depends on DM_RESET
> default y if ASPEED_AST2500
> diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/reset-ast2500.c
> similarity index 100% rename from drivers/reset/ast2500-reset.c rename to
> drivers/reset/reset-ast2500.c
> --
> 2.17.1
RE: [v2 1/2] reset: ast2500: Use SCU for reset control
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, October 12, 2020 10:36 AM
> To: tr...@konsulko.com; u-boot@lists.denx.de; max...@google.com
> Cc: Ryan Chen ; BMC-SW
>
> Subject: [v2 1/2] reset: ast2500: Use SCU for reset control
>
> The System Control Unit (SCU) controller of Aspeed SoCs provides the reset
> control for each peripheral.
>
> This patch refactors the reset method to leverage the SCU reset control. Thus
> the driver dependency on watchdog including dedicated WDT API and reset
> flag encoding can be eliminated.
>
> The Kconfig description is also updated accordingly.
>
> Signed-off-by: Chia-Wei, Wang
Reviewed-by: Ryan Chen
> ---
> arch/arm/dts/ast2500-u-boot.dtsi | 7 +-
> drivers/reset/Kconfig | 9 +--
> drivers/reset/ast2500-reset.c | 97 ---
> include/dt-bindings/reset/ast2500-reset.h | 73 +
> 4 files changed, 97 insertions(+), 89 deletions(-)
>
> diff --git a/arch/arm/dts/ast2500-u-boot.dtsi
> b/arch/arm/dts/ast2500-u-boot.dtsi
> index 51a5244766..ea60e4c8db 100644
> --- a/arch/arm/dts/ast2500-u-boot.dtsi
> +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> @@ -16,7 +16,6 @@
> rst: reset-controller {
> u-boot,dm-pre-reloc;
> compatible = "aspeed,ast2500-reset";
> - aspeed,wdt = <>;
> #reset-cells = <1>;
> };
>
> @@ -27,7 +26,7 @@
> 0x1e6e0200 0x1d4 >;
> #reset-cells = <1>;
> clocks = < ASPEED_CLK_MPLL>;
> - resets = < AST_RESET_SDRAM>;
> + resets = < ASPEED_RESET_SDRAM>;
> };
>
> ahb {
> @@ -41,7 +40,7 @@
> reg = <0x1e740100>;
> #reset-cells = <1>;
> clocks = < ASPEED_CLK_SDIO>;
> - resets = < AST_RESET_SDIO>;
> + resets = < ASPEED_RESET_SDIO>;
> };
>
> sdhci1: sdhci@1e740200 {
> @@ -49,7 +48,7 @@
> reg = <0x1e740200>;
> #reset-cells = <1>;
> clocks = < ASPEED_CLK_SDIO>;
> - resets = < AST_RESET_SDIO>;
> + resets = < ASPEED_RESET_SDIO>;
> };
> };
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index
> b60e11f98b..8b243fdcc6 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -74,13 +74,12 @@ config RESET_UNIPHIER
>
> config AST2500_RESET
> bool "Reset controller driver for AST2500 SoCs"
> - depends on DM_RESET && WDT_ASPEED
> + depends on DM_RESET
> default y if ASPEED_AST2500
> help
> - Support for reset controller on AST2500 SoC. This controller uses
> - watchdog to reset different peripherals and thus only supports
> - resets that are supported by watchdog. The main limitation though
> - is that some reset signals, like I2C or MISC reset multiple devices.
> + Support for reset controller on AST2500 SoC.
> + Say Y if you want to control reset signals of different peripherals
> + through System Control Unit (SCU).
>
> config RESET_ROCKCHIP
> bool "Reset controller driver for Rockchip SoCs"
> diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
> index
> beb5cd8fa8..e7b5c7deca 100644
> --- a/drivers/reset/ast2500-reset.c
> +++ b/drivers/reset/ast2500-reset.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> * Copyright 2017 Google, Inc
> + * Copyright 2020 ASPEED Technology Inc.
> */
>
> #include
> @@ -9,28 +10,26 @@
> #include
> #include
> #include
> -#include
> +#include
> #include
> #include
> -#include
>
> struct ast2500_reset_priv {
> - /* WDT used to perform resets. */
> - struct udevice *wdt;
> struct ast2500_scu *scu;
> };
>
> -static int ast2500_ofdata_to_platdata(struct udevice *dev)
> +static int ast2500_reset_request(struct reset_ctl *reset_ctl)
> {
> - struct ast2500_reset_priv *priv = dev_get_priv(dev);
> - int ret;
> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
> + reset_ctl->dev, reset_ctl->id);
>
> - ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
> -
RE: [PATCH 1/2] reset: ast2500: Use SCU for reset control
> -Original Message-
> From: ChiaWei Wang
> Sent: Tuesday, September 8, 2020 3:21 PM
> To: Ryan Chen ; max...@google.com;
> u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 1/2] reset: ast2500: Use SCU for reset control
>
> The System Control Unit (SCU) controller of Aspeed SoCs provides the reset
> control for each peripheral.
>
> This patch refactors the reset method to leverage the SCU reset control. Thus
> the driver dependency on watchdog including dedicated WDT API and reset
> flag encoding can be eliminated.
>
> The Kconfig description is also updated accordingly.
>
> Signed-off-by: Chia-Wei, Wang
Reviewed-by: Ryan Chen
> ---
> arch/arm/dts/ast2500-u-boot.dtsi | 7 +-
> drivers/reset/Kconfig | 9 +--
> drivers/reset/ast2500-reset.c | 97 ---
> include/dt-bindings/reset/ast2500-reset.h | 73 +
> 4 files changed, 97 insertions(+), 89 deletions(-)
>
> diff --git a/arch/arm/dts/ast2500-u-boot.dtsi
> b/arch/arm/dts/ast2500-u-boot.dtsi
> index 8ac4215745..ca4aac2159 100644
> --- a/arch/arm/dts/ast2500-u-boot.dtsi
> +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> @@ -15,7 +15,6 @@
> rst: reset-controller {
> u-boot,dm-pre-reloc;
> compatible = "aspeed,ast2500-reset";
> - aspeed,wdt = <>;
> #reset-cells = <1>;
> };
>
> @@ -26,7 +25,7 @@
> 0x1e6e0200 0x1d4 >;
> #reset-cells = <1>;
> clocks = < PLL_MPLL>;
> - resets = < AST_RESET_SDRAM>;
> + resets = < ASPEED_RESET_SDRAM>;
> };
>
> ahb {
> @@ -40,7 +39,7 @@
> reg = <0x1e740100>;
> #reset-cells = <1>;
> clocks = < BCLK_SDCLK>;
> - resets = < AST_RESET_SDIO>;
> + resets = < ASPEED_RESET_SDIO>;
> };
>
> sdhci1: sdhci@1e740200 {
> @@ -48,7 +47,7 @@
> reg = <0x1e740200>;
> #reset-cells = <1>;
> clocks = < BCLK_SDCLK>;
> - resets = < AST_RESET_SDIO>;
> + resets = < ASPEED_RESET_SDIO>;
> };
> };
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index
> 253902ff57..796aa267c5 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -74,13 +74,12 @@ config RESET_UNIPHIER
>
> config AST2500_RESET
> bool "Reset controller driver for AST2500 SoCs"
> - depends on DM_RESET && WDT_ASPEED
> + depends on DM_RESET
> default y if ASPEED_AST2500
> help
> - Support for reset controller on AST2500 SoC. This controller uses
> - watchdog to reset different peripherals and thus only supports
> - resets that are supported by watchdog. The main limitation though
> - is that some reset signals, like I2C or MISC reset multiple devices.
> + Support for reset controller on AST2500 SoC.
> + Say Y if you want to control reset signals of different peripherals
> + through System Control Unit (SCU).
>
> config RESET_ROCKCHIP
> bool "Reset controller driver for Rockchip SoCs"
> diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
> index
> beb5cd8fa8..e7b5c7deca 100644
> --- a/drivers/reset/ast2500-reset.c
> +++ b/drivers/reset/ast2500-reset.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> * Copyright 2017 Google, Inc
> + * Copyright 2020 ASPEED Technology Inc.
> */
>
> #include
> @@ -9,28 +10,26 @@
> #include
> #include
> #include
> -#include
> +#include
> #include
> #include
> -#include
>
> struct ast2500_reset_priv {
> - /* WDT used to perform resets. */
> - struct udevice *wdt;
> struct ast2500_scu *scu;
> };
>
> -static int ast2500_ofdata_to_platdata(struct udevice *dev)
> +static int ast2500_reset_request(struct reset_ctl *reset_ctl)
> {
> - struct ast2500_reset_priv *priv = dev_get_priv(dev);
> - int ret;
> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
> + reset_ctl->dev, reset_ctl->id);
>
> - ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
> -
RE: [PATCH 2/2] cosmetic: reset: ast2500: Rename driver and configs
> -Original Message-
> From: ChiaWei Wang
> Sent: Tuesday, September 8, 2020 3:21 PM
> To: Ryan Chen ; max...@google.com;
> u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 2/2] cosmetic: reset: ast2500: Rename driver and configs
>
> 1. Rename AST2500 reset driver from ast2500-reset.c
>to reset-ast2500.c
> 2. Rename AST2500 reset kconfig option from AST2500_RESET
>to RESET_AST2500
>
> Signed-off-by: Chia-Wei, Wang
Reviewed-by: Ryan Chen
> ---
> drivers/reset/Kconfig | 2 +-
> drivers/reset/{ast2500-reset.c => reset-ast2500.c} | 0
> 2 files changed, 1 insertion(+), 1 deletion(-) rename
> drivers/reset/{ast2500-reset.c => reset-ast2500.c} (100%)
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index
> 796aa267c5..381d222524 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -72,7 +72,7 @@ config RESET_UNIPHIER
> Say Y if you want to control reset signals provided by System Control
> block, Media I/O block, Peripheral Block.
>
> -config AST2500_RESET
> +config RESET_AST2500
> bool "Reset controller driver for AST2500 SoCs"
> depends on DM_RESET
> default y if ASPEED_AST2500
> diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/reset-ast2500.c
> similarity index 100% rename from drivers/reset/ast2500-reset.c rename to
> drivers/reset/reset-ast2500.c
> --
> 2.17.1
RE: [PATCH 2/2] ram: add ddr4 dual x8 configuration
> -Original Message- > From: Dylan Hung > Sent: Monday, September 7, 2020 4:25 PM > To: Ryan Chen ; u-boot@lists.denx.de > Cc: BMC-SW > Subject: [PATCH 2/2] ram: add ddr4 dual x8 configuration > > the aspeed ddr sdram controller needs to know if the memory chip mounted > on the board is dual x8 die or not. Or it may get the wrong size of the memory > space. > > Signed-off-by: Dylan Hung Reviewed-by: Ryan Chen > --- > drivers/ram/Kconfig| 1 + > drivers/ram/aspeed/Kconfig | 10 ++ > drivers/ram/aspeed/sdram_ast2500.c | 2 +- > 3 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 > drivers/ram/aspeed/Kconfig > > diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index > 7e6e981897..d277237288 100644 > --- a/drivers/ram/Kconfig > +++ b/drivers/ram/Kconfig > @@ -76,3 +76,4 @@ config IMXRT_SDRAM > source "drivers/ram/rockchip/Kconfig" > source "drivers/ram/sifive/Kconfig" > source "drivers/ram/stm32mp1/Kconfig" > +source "drivers/ram/aspeed/Kconfig" > diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig new file > mode 100644 index 00..020c913188 > --- /dev/null > +++ b/drivers/ram/aspeed/Kconfig > @@ -0,0 +1,10 @@ > +if RAM || SPL_RAM > +config ASPEED_DDR4_DUALX8 > + bool "Enable Dual X8 DDR4 die" > + depends on DM && OF_CONTROL && ARCH_ASPEED > + default n > + help > + Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr > sdram > + controller needs to know if the memory chip mounted on the board > is dual > + x8 die or not. Or it may get the wrong size of the memory > space. > +endif > diff --git a/drivers/ram/aspeed/sdram_ast2500.c > b/drivers/ram/aspeed/sdram_ast2500.c > index a3adaa8a99..8bfbf562c3 100644 > --- a/drivers/ram/aspeed/sdram_ast2500.c > +++ b/drivers/ram/aspeed/sdram_ast2500.c > @@ -247,7 +247,7 @@ static int ast2500_sdrammc_init_ddr4(struct > dram_info *info) > | SDRAM_PCR_RESETN_DIS > | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | > SDRAM_PCR_ODT_EXT_EN; > const u32 conf = (SDRAM_CONF_CAP_1024M << > SDRAM_CONF_CAP_SHIFT) -#ifdef CONFIG_DUALX8_RAM > +#ifdef CONFIG_ASPEED_DDR4_DUALX8 > | SDRAM_CONF_DUALX8 > #endif > | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | > SDRAM_CONF_DDR4; > -- > 2.17.1
RE: [PATCH 1/2] ram: move aspeed ram driver into drivers/ directory
> -Original Message-
> From: Dylan Hung
> Sent: Monday, September 7, 2020 4:25 PM
> To: Ryan Chen ; u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 1/2] ram: move aspeed ram driver into drivers/ directory
>
> to improve the maintainability. It is more easier to modify and add
> configurations of the driver in the centralized ram driver directory.
>
> Signed-off-by: Dylan Hung
Reviewed-by: Ryan Chen
> ---
> arch/arm/mach-aspeed/ast2500/Makefile | 2
> +-
> drivers/ram/Makefile | 1
> +
> drivers/ram/aspeed/Makefile| 3
> +++
> .../mach-aspeed/ast2500 => drivers/ram/aspeed}/sdram_ast2500.c | 0
> 4 files changed, 5 insertions(+), 1 deletion(-) create mode 100644
> drivers/ram/aspeed/Makefile rename {arch/arm/mach-aspeed/ast2500 =>
> drivers/ram/aspeed}/sdram_ast2500.c (100%)
>
> diff --git a/arch/arm/mach-aspeed/ast2500/Makefile
> b/arch/arm/mach-aspeed/ast2500/Makefile
> index 4c27c8fc46..db70432ad0 100644
> --- a/arch/arm/mach-aspeed/ast2500/Makefile
> +++ b/arch/arm/mach-aspeed/ast2500/Makefile
> @@ -1,3 +1,3 @@
> obj-y += lowlevel_init.o
> obj-y += board_common.o
> -obj-y += clk_ast2500.o sdram_ast2500.o
> +obj-y += clk_ast2500.o
> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index
> 769c9d6218..a57d506752 100644
> --- a/drivers/ram/Makefile
> +++ b/drivers/ram/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>
> obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
> obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
> +obj-$(CONFIG_ARCH_ASPEED) += aspeed/
> obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
>
> obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o diff --git
> a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile new file mode
> 100644 index 00..af604f8a4b
> --- /dev/null
> +++ b/drivers/ram/aspeed/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o
> \ No newline at end of file
> diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
> b/drivers/ram/aspeed/sdram_ast2500.c
> similarity index 100%
> rename from arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
> rename to drivers/ram/aspeed/sdram_ast2500.c
> --
> 2.17.1
RE: [PATCH v2] arm: dts: fix ast2500-evb inclusion for the correct soc family
> -Original Message- > From: Thirupathaiah Annapureddy > Sent: Wednesday, September 2, 2020 4:43 AM > To: u-boot@lists.denx.de > Cc: Maxim Sloyko ; Marek Vasut ; > thir...@microsoft.com; thir...@linux.microsoft.com; Tom Rini > ; ChiaWei Wang ; > Ryan Chen > Subject: [PATCH v2] arm: dts: fix ast2500-evb inclusion for the correct soc > family > > Include ast2500-evb.dtb for CONFIG_ASPEED_AST2500 instead of for all > aspeed targets. > > ast2400 is based on ARM926EJ-S processor (ARMv5-architecture). > ast2500 is based on ARM1176JZS processor (ARMv6-architecture). > ast2600 is based on Cortex A7 processor (ARMv7-A architecture). > Each of the above SOC is using a different ARM CPU(s) with different ARM > architecture revision. It is not possible to support all 3 of these families > in a > single binary. So there is no need to build ast2500-evb.dtb for other SOC > families. > > Signed-off-by: Thirupathaiah Annapureddy > --- > > Changes in v2: > - Incorporated the feedback from Tom Rini and Ryan Chen. > > arch/arm/dts/Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index > 7e29b9096b..33d40a05f9 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -938,7 +938,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \ > > dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb > > -dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb > +dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb > I prefer keep the Makefile logic clear use one CONFIG_ARCH_ASPEED to make all ASPEED SoC dtb. And also align with kernel tree " https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/Makefile;. Another point of view, For example, There also have AST2520 SoC which share the same CPU architecture with AST2500, And that will need another CONFIG_ASPEED_AST2520, That will cause more complicated dts Makefile. > dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb > > -- > 2.25.2
[PATCH v2 0/3] Rename ASPEED SoC clock name
This patch series refactor the exiting ASPEED clock name define sync with Linux kernel. And also add SPDX-License V2 : modify patch 2/3 title form "aspeed:clock:" -> "clock:aspeed:" description Ryan Chen (3): cosmetic: aspeed: ast2500: Rename clock header clock:aspeed: Sync with Linux kernel clock header define cosmetic: aspeed: Modify for SPDX-License arch/arm/dts/ast2500-u-boot.dtsi | 23 ++- arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 2 +- drivers/clk/aspeed/clk_ast2500.c | 40 +-- include/dt-bindings/clock/aspeed-clock.h | 42 include/dt-bindings/clock/ast2500-scu.h | 30 -- 5 files changed, 74 insertions(+), 63 deletions(-) create mode 100644 include/dt-bindings/clock/aspeed-clock.h delete mode 100644 include/dt-bindings/clock/ast2500-scu.h -- 2.17.1
[PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License
Modify SPDX-License for furture patch warning Signed-off-by: Ryan Chen --- arch/arm/dts/ast2500-u-boot.dtsi | 1 + include/dt-bindings/clock/aspeed-clock.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 29b08f16ac..51a5244766 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include #include diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index e6599deeb9..a1aa8c07ce 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +// SPDX-License-Identifier: GPL-2.0 #define ASPEED_CLK_GATE_ECLK 0 #define ASPEED_CLK_GATE_GCLK 1 -- 2.17.1
[PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header
Rename the ast2500-scu.h to aspeed-clock.h.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi| 2 +-
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c| 2 +-
drivers/clk/aspeed/clk_ast2500.c| 2 +-
include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0
4 files changed, 3 insertions(+), 3 deletions(-)
rename include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 8ac4215745..3b119e4ace 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,4 @@
-#include
+#include
#include
#include "ast2500.dtsi"
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index a3adaa8a99..8536a70a19 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -19,7 +19,7 @@
#include
#include
#include
-#include
+#include
/* These configuration parameters are taken from Aspeed SDK */
#define DDR4_MR46_MODE 0x0800
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index d1940f1884..392fe76b27 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -10,7 +10,7 @@
#include
#include
#include
-#include
+#include
#include
#include
diff --git a/include/dt-bindings/clock/ast2500-scu.h
b/include/dt-bindings/clock/aspeed-clock.h
similarity index 100%
rename from include/dt-bindings/clock/ast2500-scu.h
rename to include/dt-bindings/clock/aspeed-clock.h
--
2.17.1
[PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define
v2: modify title description aspeed:clock -> clock:aspeed
Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi | 20 +++
drivers/clk/aspeed/clk_ast2500.c | 38 +++--
include/dt-bindings/clock/aspeed-clock.h | 68 ++--
3 files changed, 68 insertions(+), 58 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 3b119e4ace..29b08f16ac 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -25,7 +25,7 @@
reg = <0x1e6e 0x174
0x1e6e0200 0x1d4 >;
#reset-cells = <1>;
- clocks = < PLL_MPLL>;
+ clocks = < ASPEED_CLK_MPLL>;
resets = < AST_RESET_SDRAM>;
};
@@ -39,7 +39,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740100>;
#reset-cells = <1>;
- clocks = < BCLK_SDCLK>;
+ clocks = < ASPEED_CLK_SDIO>;
resets = < AST_RESET_SDIO>;
};
@@ -47,7 +47,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740200>;
#reset-cells = <1>;
- clocks = < BCLK_SDCLK>;
+ clocks = < ASPEED_CLK_SDIO>;
resets = < AST_RESET_SDIO>;
};
};
@@ -56,23 +56,23 @@
};
{
- clocks = < PCLK_UART1>;
+ clocks = < ASPEED_CLK_GATE_UART1CLK>;
};
{
- clocks = < PCLK_UART2>;
+ clocks = < ASPEED_CLK_GATE_UART2CLK>;
};
{
- clocks = < PCLK_UART3>;
+ clocks = < ASPEED_CLK_GATE_UART3CLK>;
};
{
- clocks = < PCLK_UART4>;
+ clocks = < ASPEED_CLK_GATE_UART4CLK>;
};
{
- clocks = < PCLK_UART5>;
+ clocks = < ASPEED_CLK_GATE_UART5CLK>;
};
{
@@ -80,9 +80,9 @@
};
{
- clocks = < PCLK_MAC1>, < PLL_D2PLL>;
+ clocks = < ASPEED_CLK_GATE_MAC1CLK>, < ASPEED_CLK_D2PLL>;
};
{
- clocks = < PCLK_MAC2>, < PLL_D2PLL>;
+ clocks = < ASPEED_CLK_GATE_MAC1CLK>, < ASPEED_CLK_D2PLL>;
};
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 392fe76b27..aab7d14deb 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
ulong rate;
switch (clk->id) {
- case PLL_HPLL:
- case ARMCLK:
+ case ASPEED_CLK_HPLL:
/*
* This ignores dynamic/static slowdown of ARMCLK and may
* be inaccurate.
@@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_hpll_rate(clkin,
readl(>scu->h_pll_param));
break;
- case MCLK_DDR:
+ case ASPEED_CLK_MPLL:
rate = ast2500_get_mpll_rate(clkin,
readl(>scu->m_pll_param));
break;
- case BCLK_PCLK:
+ case ASPEED_CLK_APB:
{
ulong apb_div = 4 + 4 * ((readl(>scu->clk_sel1)
& SCU_PCLK_DIV_MASK)
@@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
- case BCLK_SDCLK:
+ case ASPEED_CLK_SDIO:
{
ulong apb_div = 4 + 4 * ((readl(>scu->clk_sel1)
& SCU_SDCLK_DIV_MASK)
@@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
- case PCLK_UART1:
+ case ASPEED_CLK_GATE_UART1CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
- case PCLK_UART2:
+ case ASPEED_CLK_GATE_UART2CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 2);
break;
- case PCLK_UART3:
+ case ASPEED_CLK_GATE_UART3CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 3);
break;
- case PCLK_UART4:
+ case ASPEED_CLK_GATE_UART4CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 4);
break;
- ca
RE: [PATCH 0/3] Rename ASPEED SoC clock name
> -Original Message- > From: Cédric Le Goater > Sent: Saturday, August 29, 2020 4:46 PM > To: Ryan Chen ; ChiaWei Wang > ; BMC-SW ; > lu...@denx.de; eaja...@linux.ibm.com; s...@chromium.org; > u-boot@lists.denx.de; Joel Stanley > Subject: Re: [PATCH 0/3] Rename ASPEED SoC clock name > > Hello Ryan, > > On 8/28/20 9:32 AM, Ryan Chen wrote: > > This patch series refactor the exiting ASPEED clock name define sync > > with Linux kernel. And also add SPDX-License > > All the patchset seems correct but the patch numbering is a bit confusing. I > have received : > > [1/3] cosmetic: aspeed: ast2500: Rename clock header [1/1] Remove not > used export function header. > [2/3] aspeed:clock: Sync with Linux kernel clock header define [3/3] > cosmetic: aspeed: Modify for SPDX-License > > Could you please merge the first two together maybe and resend ? > > Thanks, > > C. > Thanks the review. I will resend it for v2. > > Ryan Chen (3): > > cosmetic: aspeed: ast2500: Rename clock header > > aspeed:clock: Sync with Linux kernel clock header define > > cosmetic: aspeed: Modify for SPDX-License > > > > arch/arm/dts/ast2500-u-boot.dtsi | 23 ++- > > arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 2 +- > > drivers/clk/aspeed/clk_ast2500.c | 40 +-- > > include/dt-bindings/clock/aspeed-clock.h | 42 > > > include/dt-bindings/clock/ast2500-scu.h | 30 -- > > 5 files changed, 74 insertions(+), 63 deletions(-) create mode > > 100644 include/dt-bindings/clock/aspeed-clock.h > > delete mode 100644 include/dt-bindings/clock/ast2500-scu.h > >
[PATCH 2/3] aspeed:clock: Sync with Linux kernel clock header define
Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi | 20 +++
drivers/clk/aspeed/clk_ast2500.c | 38 +++--
include/dt-bindings/clock/aspeed-clock.h | 68 ++--
3 files changed, 68 insertions(+), 58 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 3b119e4ace..29b08f16ac 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -25,7 +25,7 @@
reg = <0x1e6e 0x174
0x1e6e0200 0x1d4 >;
#reset-cells = <1>;
- clocks = < PLL_MPLL>;
+ clocks = < ASPEED_CLK_MPLL>;
resets = < AST_RESET_SDRAM>;
};
@@ -39,7 +39,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740100>;
#reset-cells = <1>;
- clocks = < BCLK_SDCLK>;
+ clocks = < ASPEED_CLK_SDIO>;
resets = < AST_RESET_SDIO>;
};
@@ -47,7 +47,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740200>;
#reset-cells = <1>;
- clocks = < BCLK_SDCLK>;
+ clocks = < ASPEED_CLK_SDIO>;
resets = < AST_RESET_SDIO>;
};
};
@@ -56,23 +56,23 @@
};
{
- clocks = < PCLK_UART1>;
+ clocks = < ASPEED_CLK_GATE_UART1CLK>;
};
{
- clocks = < PCLK_UART2>;
+ clocks = < ASPEED_CLK_GATE_UART2CLK>;
};
{
- clocks = < PCLK_UART3>;
+ clocks = < ASPEED_CLK_GATE_UART3CLK>;
};
{
- clocks = < PCLK_UART4>;
+ clocks = < ASPEED_CLK_GATE_UART4CLK>;
};
{
- clocks = < PCLK_UART5>;
+ clocks = < ASPEED_CLK_GATE_UART5CLK>;
};
{
@@ -80,9 +80,9 @@
};
{
- clocks = < PCLK_MAC1>, < PLL_D2PLL>;
+ clocks = < ASPEED_CLK_GATE_MAC1CLK>, < ASPEED_CLK_D2PLL>;
};
{
- clocks = < PCLK_MAC2>, < PLL_D2PLL>;
+ clocks = < ASPEED_CLK_GATE_MAC1CLK>, < ASPEED_CLK_D2PLL>;
};
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 392fe76b27..aab7d14deb 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
ulong rate;
switch (clk->id) {
- case PLL_HPLL:
- case ARMCLK:
+ case ASPEED_CLK_HPLL:
/*
* This ignores dynamic/static slowdown of ARMCLK and may
* be inaccurate.
@@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_hpll_rate(clkin,
readl(>scu->h_pll_param));
break;
- case MCLK_DDR:
+ case ASPEED_CLK_MPLL:
rate = ast2500_get_mpll_rate(clkin,
readl(>scu->m_pll_param));
break;
- case BCLK_PCLK:
+ case ASPEED_CLK_APB:
{
ulong apb_div = 4 + 4 * ((readl(>scu->clk_sel1)
& SCU_PCLK_DIV_MASK)
@@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
- case BCLK_SDCLK:
+ case ASPEED_CLK_SDIO:
{
ulong apb_div = 4 + 4 * ((readl(>scu->clk_sel1)
& SCU_SDCLK_DIV_MASK)
@@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
- case PCLK_UART1:
+ case ASPEED_CLK_GATE_UART1CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
- case PCLK_UART2:
+ case ASPEED_CLK_GATE_UART2CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 2);
break;
- case PCLK_UART3:
+ case ASPEED_CLK_GATE_UART3CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 3);
break;
- case PCLK_UART4:
+ case ASPEED_CLK_GATE_UART4CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 4);
break;
- case PCLK_UART5:
+ case ASPEED_CLK_GATE_UART5CLK:
[PATCH 3/3] cosmetic: aspeed: Modify for SPDX-License
Modify SPDX-License for furture patch warning Signed-off-by: Ryan Chen --- arch/arm/dts/ast2500-u-boot.dtsi | 1 + include/dt-bindings/clock/aspeed-clock.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 29b08f16ac..51a5244766 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include #include diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index e6599deeb9..a1aa8c07ce 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +// SPDX-License-Identifier: GPL-2.0 #define ASPEED_CLK_GATE_ECLK 0 #define ASPEED_CLK_GATE_GCLK 1 -- 2.17.1
[PATCH 1/3] cosmetic: aspeed: ast2500: Rename clock header
Rename the ast2500-scu.h to aspeed-clock.h.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi| 2 +-
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c| 2 +-
drivers/clk/aspeed/clk_ast2500.c| 2 +-
include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0
4 files changed, 3 insertions(+), 3 deletions(-)
rename include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 8ac4215745..3b119e4ace 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,4 @@
-#include
+#include
#include
#include "ast2500.dtsi"
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index a3adaa8a99..8536a70a19 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -19,7 +19,7 @@
#include
#include
#include
-#include
+#include
/* These configuration parameters are taken from Aspeed SDK */
#define DDR4_MR46_MODE 0x0800
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index d1940f1884..392fe76b27 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -10,7 +10,7 @@
#include
#include
#include
-#include
+#include
#include
#include
diff --git a/include/dt-bindings/clock/ast2500-scu.h
b/include/dt-bindings/clock/aspeed-clock.h
similarity index 100%
rename from include/dt-bindings/clock/ast2500-scu.h
rename to include/dt-bindings/clock/aspeed-clock.h
--
2.17.1
[PATCH 0/3] Rename ASPEED SoC clock name
This patch series refactor the exiting ASPEED clock name define sync with Linux kernel. And also add SPDX-License Ryan Chen (3): cosmetic: aspeed: ast2500: Rename clock header aspeed:clock: Sync with Linux kernel clock header define cosmetic: aspeed: Modify for SPDX-License arch/arm/dts/ast2500-u-boot.dtsi | 23 ++- arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 2 +- drivers/clk/aspeed/clk_ast2500.c | 40 +-- include/dt-bindings/clock/aspeed-clock.h | 42 include/dt-bindings/clock/ast2500-scu.h | 30 -- 5 files changed, 74 insertions(+), 63 deletions(-) create mode 100644 include/dt-bindings/clock/aspeed-clock.h delete mode 100644 include/dt-bindings/clock/ast2500-scu.h -- 2.17.1
[PATCH 1/1] Remove not used export function header.
All driver is use clk dm model, will not use this function call.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi| 2 +-
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c| 2 +-
drivers/clk/aspeed/clk_ast2500.c| 2 +-
include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0
4 files changed, 3 insertions(+), 3 deletions(-)
rename include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 8ac4215745..3b119e4ace 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,4 @@
-#include
+#include
#include
#include "ast2500.dtsi"
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index a3adaa8a99..8536a70a19 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -19,7 +19,7 @@
#include
#include
#include
-#include
+#include
/* These configuration parameters are taken from Aspeed SDK */
#define DDR4_MR46_MODE 0x0800
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index d1940f1884..392fe76b27 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -10,7 +10,7 @@
#include
#include
#include
-#include
+#include
#include
#include
diff --git a/include/dt-bindings/clock/ast2500-scu.h
b/include/dt-bindings/clock/aspeed-clock.h
similarity index 100%
rename from include/dt-bindings/clock/ast2500-scu.h
rename to include/dt-bindings/clock/aspeed-clock.h
--
2.17.1
RE: [PATCH] arm: dts: fix ast2500-evb inclusion for correct target
Hi > -Original Message- > From: Thirupathaiah Annapureddy [mailto:thir...@linux.microsoft.com] > Sent: Thursday, August 20, 2020 8:16 AM > To: u-boot@lists.denx.de > Cc: Maxim Sloyko ; Marek Vasut ; > ChiaWei Wang ; Ryan Chen > > Subject: Re: [PATCH] arm: dts: fix ast2500-evb inclusion for correct target > > Adding Ryan and Chiawei to the list. > > On 8/17/2020 5:53 PM, Thirupathaiah Annapureddy wrote: > > Include ast2500-evb.dtb for CONFIG_TARGET_EVB_AST2500 instead of for > > all aspeed targets. There should not have to many Kconfig for ASPEED platform. I prefer use following to build all all ASPEED platform. Like following. dtb-$(CONFIG_ARCH_ASPEED) += \ ast2400-evb.dtb \ ast2500-evb.dtb \ ast2600a0-evb.dtb \ ast2600a0-ncsi.dtb \ ast2600a1-evb.dtb \ ast2600a1-ncsi.dtb \ ast2600-fpga.dtb \ ast2600-rainier.dtb \ ast2600-slt.dtb \ ast2600-tacoma.dtb > > > > Signed-off-by: Thirupathaiah Annapureddy > --- > > arch/arm/dts/Makefile | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index > > 7e29b9096b..d019f26983 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -938,7 +938,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \ > > > > dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb > > > > -dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb > > +dtb-$(CONFIG_TARGET_EVB_AST2500) += ast2500-evb.dtb > > > > dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb > > > >
[U-Boot] [PATCH] Add WinCE image load/boot cmd
The patch is to add support functions which load and boot WinCE image.
It introduces one new CMD macro named 'CONFIG_CMD_WINCE'.
The source codes have tested on STLS board.
Signed-off-by: Ryan Chen [EMAIL PROTECTED]
---
common/Makefile |1 +
common/cmd_bootm.c | 32
common/cmd_wince.c | 193 ++
include/config_cmd_all.h |1 +
include/image.h |1 +
5 files changed, 228 insertions(+), 0 deletions(-)
create mode 100644 common/cmd_wince.c
diff --git a/common/Makefile b/common/Makefile
index 4287108..e427828 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -144,6 +144,7 @@ COBJS-y += cmd_mac.o
COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
COBJS-$(CONFIG_MP) += cmd_mp.o
COBJS-$(CONFIG_CMD_SF) += cmd_sf.o
+COBJS-$(CONFIG_CMD_WINCE) += cmd_wince.o
COBJS := $(COBJS-y)
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 1c0a416..e6397d7 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -106,6 +106,10 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char
*argv[]);
#if defined(CONFIG_ARTOS) defined(CONFIG_PPC)
static boot_os_fn do_bootm_artos;
#endif
+#if defined(CONFIG_CMD_WINCE)
+static boot_os_fn do_bootm_wince;
+int do_bootwince (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+#endif
ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */
static bootm_headers_t images; /* pointers to os/initrd/fdt images */
@@ -358,6 +362,12 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char
*argv[])
do_bootm_artos (cmdtp, flag, argc, argv, images);
break;
#endif
+
+#ifdef CONFIG_CMD_WINCE
+ case IH_OS_WINCE:
+ do_bootm_wince (cmdtp, flag, argc, argv, images);
+ break;
+#endif
}
show_boot_progress (-9);
@@ -1142,3 +1152,25 @@ static void do_bootm_artos (cmd_tbl_t *cmdtp, int flag,
(*entry) (kbd, cmdline, fwenv, top);
}
#endif
+
+#if defined(CONFIG_CMD_WINCE)
+static void do_bootm_wince (cmd_tbl_t *cmdtp, int flag,
+ int argc, char *argv[],
+ bootm_headers_t *images)
+{
+ char str[80];
+ image_header_t *hdr = images-legacy_hdr_os_copy;
+
+#if defined(CONFIG_FIT)
+ if (!images-legacy_hdr_valid) {
+ fit_unsupported_reset (WinCE);
+ do_reset (cmdtp, flag, argc, argv);
+ }
+#endif
+
+sprintf(str, %x, image_get_ep (hdr)); /* write entry-point into
string */
+setenv(loadaddr, str);
+do_bootwince(cmdtp, 0, 0, NULL);
+}
+#endif/* CONFIG_CMD_WINCE */
+
diff --git a/common/cmd_wince.c b/common/cmd_wince.c
new file mode 100644
index 000..fdc2e6b
--- /dev/null
+++ b/common/cmd_wince.c
@@ -0,0 +1,193 @@
+/*
+ * 2008 (c) STMicroelectronics, Inc.
+ * Author: Ryan Chen [EMAIL PROTECTED]
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *must display the following acknowledgement:
+ * This product includes software developed by Opsycon AB, Sweden.
+ * 4. The name of the author may not be used to endorse or promote products
+ *derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include common.h
+#include command.h
+#include linux/ctype.h
+#include net.h
+
+/*
+ * Windows CE Binary Image Data Format
+ * The binary image (.bin) file format organizes data by sections. Each
section contains
+ * a section header that specifies the starting address, length, and checksum
for that
+ * section.
+ *
+ * Refer to http://msdn.microsoft.com/en-us/library/ms924510.aspx
+ *
+ * The following table shows the .bin
[U-Boot] [PATCH] Add background serial print and correct search_device function
The patch introduces a new macro 'CFG_BG_CONSOLE_SERIAL'.
It means print messages through serial port although current console isn't
serial port.
It is important for debugging and looks like multi-consoles in Linux but
without input.
Another modification in the patch is that verify if search_device function
found device.
If found, return dev. Otherwise, return NULL.
Signed-off-by: Ryan Chen [EMAIL PROTECTED]
---
common/console.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/common/console.c b/common/console.c
index 1b095b1..c60baef 100644
--- a/common/console.c
+++ b/common/console.c
@@ -132,12 +132,20 @@ void fputc (int file, const char c)
{
if (file MAX_FILES)
stdio_devices[file]-putc (c);
+#ifdef CFG_BG_CONSOLE_SERIAL
+ if((unsigned int)stdio_devices[file]-putc != (unsigned int)serial_putc)
+ serial_putc (c);
+#endif/*CFG_BG_CONSOLE_SERIAL*/
}
void fputs (int file, const char *s)
{
if (file MAX_FILES)
stdio_devices[file]-puts (s);
+#ifdef CFG_BG_CONSOLE_SERIAL
+ if((unsigned int)stdio_devices[file]-puts != (unsigned int)serial_puts)
+ serial_puts(s);
+#endif/*CFG_BG_CONSOLE_SERIAL*/
}
void fprintf (int file, const char *fmt, ...)
@@ -377,6 +385,7 @@ device_t *search_device (int flags, char *name)
{
int i, items;
device_t *dev = NULL;
+ int found_flag = 0;
items = ListNumItems (devlist);
if (name == NULL)
@@ -385,9 +394,13 @@ device_t *search_device (int flags, char *name)
for (i = 1; i = items; i++) {
dev = ListGetPtrToItem (devlist, i);
if ((dev-flags flags) (strcmp (name, dev-name) == 0)) {
+ found_flag = 1;
break;
}
}
+
+ if(!found_flag)
+ return NULL;
return dev;
}
#endif /* CFG_CONSOLE_IS_IN_ENV || CONFIG_SPLASH_SCREEN */
--
1.6.0.rc1
___
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Re: [U-Boot] [U-Boot-Users] [Part 2 of A PATCH SERIES for STLS]: Upate Makefile, MAKEALL and MAINTAINERS files in root directory!
Dear Wolfgang, Yes, I was modifying my codes in the past several days. Since I need give support to another project, I was so late to continue my push work for U-Boot. Sorry! I am unskilled on git tools, so now I also try to study how to use git-format-patch to make my patchs reasonable. I will resubmit them ASAP. Thanks for your help! Best Regards, Ryan Chen -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: Tuesday, August 19, 2008 6:10 AM To: Ryan CHEN Cc: u-boot@lists.denx.de; Antonio Maria BORNEO Subject: Re: [U-Boot-Users] [Part 2 of A PATCH SERIES for STLS]: Upate Makefile, MAKEALL and MAINTAINERS files in root directory! Dear Ryan CHEN, In message [EMAIL PROTECTED] you wrote: This is part 2 of a patch series for STLS. It will update Makefile, MAKEALL and MAINTAINERS files with STLS information! After the review comments on this list I'm still waiting for you to post an updated patch (a single one). Please note that the merge window is open *now*, so if you want to see that code in the next release, please act now. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] Life sucks, but it's better than the alternative. - Peter da Silva ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
