[U-Boot] [PATCH v5 03/14] fsl: ls-ch3: Add new header for Secure Boot
For Secure Boot, a header is used to identify key table, signature and
image address. For Ls-Ch3, there is a new header structure being used.
Currently Key extension (IE) feature is not supported. Single Key
feature is not supported. Keys must be in table format. Hence, SRK (Key
table) is by default currently always present. Max Key number has
increase from 4 to 8. 8th Key is irrevocable. A New Barker Code is being
used.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- Cleaned up commit message
Changes for v5:
- Cleaned up commit message
arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +-
arch/arm/include/asm/fsl_secure_boot.h| 4 ++
board/freescale/common/fsl_validate.c | 35 +++--
include/fsl_secboot_err.h | 3 ++
include/fsl_validate.h| 60 ---
5 files changed, 91 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 34851a9..0445dbd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -79,7 +79,8 @@
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
-
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index a32a1d7..4eb3b15 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -35,9 +35,13 @@
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
*/
+#ifndef CONFIG_ESBC_HDR_LS
+/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
+#endif
+
#ifdef CONFIG_LS1043A
/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
#define CONFIG_ESBC_ADDR_64BIT
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 8fd6dd6..c12b9c9 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -35,7 +35,13 @@ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30,
0x0d, 0x06, 0x09, 0x60,
};
static u8 hash_val[SHA256_BYTES];
+
+#ifdef CONFIG_ESBC_HDR_LS
+/* New Barker Code for LS ESBC Header */
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
+#else
static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+#endif
void branch_to_self(void) __attribute__ ((noreturn));
@@ -157,10 +163,15 @@ static int get_ie_info_addr(u32 *ie_addr)
/* This function checks srk_table_flag in header and set/reset srk_flag.*/
static u32 check_srk(struct fsl_secboot_img_priv *img)
{
+#ifdef CONFIG_ESBC_HDR_LS
+ /* In LS, No SRK Flag as SRK is always present*/
+ return 1;
+#else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
return 1;
return 0;
+#endif
}
/* This function returns ospr's key_revoc values.*/
@@ -223,6 +234,7 @@ static u32 read_validate_srk_tbl(struct
fsl_secboot_img_priv *img)
}
#endif
+#ifndef CONFIG_ESBC_HDR_LS
static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
{
struct fsl_secboot_img_hdr *hdr = >hdr;
@@ -238,6 +250,7 @@ static u32 read_validate_single_key(struct
fsl_secboot_img_priv *img)
return 0;
}
+#endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
@@ -388,6 +401,7 @@ void fsl_secboot_handle_error(int error)
case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+ case ERROR_KEY_TABLE_NOT_FOUND:
#ifdef CONFIG_KEY_REVOCATION
case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
@@ -536,11 +550,18 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
if (!key_hash && check_ie(img))
key_hash = 1;
#endif
- if (!key_hash)
+#ifndef CONFIG_ESBC_HDR_LS
+/* No single key support in LS ESBC header */
+ if (!key_hash) {
ret = algo->hash_update(algo, ctx,
img->img_key, img->hdr.key_len, 0);
+ key_hash = 1;
+ }
+#endif
if (ret)
return ret;
+ if (!key_hash)
+ return ERROR_KEY_TABLE_NOT_FOUND;
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
@@ -626,8 +647,6 @@ static int read_validate_esbc_client_header(struct
[U-Boot] [PATCH v5 09/14] armv8: fsl-lsch3: Disable SMMU during Secure Boot
During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in Bypass mode in uboot to enable CAAM transcations to pass
through.
During Nonsecure Boot, SP BootROM doesn't enable SMMU and at reset
SMMU is in bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- No changes
Changes for v5:
- Cleaned up commit message
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 +-
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 213ce3a..a39d08d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -151,7 +151,14 @@ static void erratum_a009203(void)
#endif
#endif
}
-
+void bypass_smmu(void)
+{
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+}
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
@@ -160,6 +167,15 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ if (fsl_check_boot_mode_secure() == 1)
+ bypass_smmu();
+#endif
}
#ifdef CONFIG_SCSI_AHCI_PLAT
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1fc51e0..06d4856 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -83,6 +83,21 @@
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+/* MMU 500 */
+#define SMMU_SCR0 (SMMU_BASE + 0x0)
+#define SMMU_SCR1 (SMMU_BASE + 0x4)
+#define SMMU_SCR2 (SMMU_BASE + 0x8)
+#define SMMU_SACR (SMMU_BASE + 0x10)
+#define SMMU_IDR0 (SMMU_BASE + 0x20)
+#define SMMU_IDR1 (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0 (SMMU_BASE + 0x400)
+#define SMMU_NSCR2 (SMMU_BASE + 0x408)
+#define SMMU_NSACR (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK 0x0001
+#define SCR0_USFCFG_MASK 0x0400
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
--
1.8.1.4
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[U-Boot] [PATCH v5 08/14] ls2080: Add config for endianess of CCSR GUR
The GUR (DCFG) registers in CCSR space are in Little Endian format for ls2080. Defined a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes Changes for v5: - Cleaned up commit message arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 0445dbd..057912f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -82,6 +82,9 @@ /* Secure Boot */ #define CONFIG_ESBC_HDR_LS +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + /* Cache Coherent Interconnect */ #define CCI_MN_BASE0x0400 #define CCI_MN_RNF_NODEID_LIST 0x180 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 11/14] crypto/fsl: Make CAAM transactions cacheable
This commit solves CAAM coherency issue on ls2080. When Caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/write data from/to Caches and CAAM does from Main Memory. This forces data flushes to synchronize various data structures. But even if any data in proximity of these structures is read by core, these structures again are fetched in caches. To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable. So, this commit makes CAAM transcations as Write Back with Write and Read Allocate. Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message drivers/crypto/fsl/jr.c | 13 + drivers/crypto/fsl/jr.h | 3 +++ 2 files changed, 16 insertions(+) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b766470..894fa03 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -543,7 +543,20 @@ int sec_init(void) uint32_t liodn_s; #endif + /* +* Modifying CAAM Read/Write Attributes +* For LS2080A and LS2085A +* For AXI Write - Cacheable, Write Back, Write allocate +* For AXI Read - Cacheable, Read allocate +* Only For LS2080a and LS2085a, to solve CAAM coherency issues +*/ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); + mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); +#else mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); +#endif + #ifdef CONFIG_PHYS_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 545d964..1642dbb 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -23,6 +23,9 @@ #define MCFGR_PS_SHIFT 16 #define MCFGR_AWCACHE_SHIFT8 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_ARCACHE_SHIFT12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) + #define JR_INTMASK 0x0001 #define JRCR_RESET 0x01 #define JRINT_ERR_HALT_INPROGRESS 0x4 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 13/14] SECURE BOOT: Halt execution when secure boot fail
In case of fatal failure during secure boot execution (e.g. header not
found), it is needed that the execution stops. Earlier, we assert reset
request in case in case of failure. But if the RESET_REQ is not tied off
to HRESET, this allows the execution to continue.
This can either be taken care in bootscript (Execute esbc_halt command
in case of image verification process) or it can be taken care in Uboot
Code. In this commit, doing the latter via esbc_halt().
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Chnages for v4:
- Cleaned up commit message
Changes for v5:
- Cleaned up commit message
board/freescale/common/cmd_esbc_validate.c | 2 +-
board/freescale/common/fsl_validate.c | 5 +
include/fsl_validate.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index dfa3e21..375bc24 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -8,7 +8,7 @@
#include
#include
-static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (fsl_check_boot_mode_secure() == 0) {
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index c12b9c9..95059c7 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -325,6 +325,8 @@ static void fsl_secboot_header_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
}
/*
@@ -355,6 +357,9 @@ static void fsl_secboot_image_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
+
} else {
change_sec_mon_state(HPSR_SSM_ST_TRUST,
HPSR_SSM_ST_NON_SECURE);
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index f812c1a..ff6f6b7 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -242,6 +242,9 @@ struct fsl_secboot_img_priv {
uint32_t img_size; /* ESBC Image Size */
};
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
uintptr_t img_loc);
int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
--
1.8.1.4
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[U-Boot] [PATCH v5 04/14] ls2080: Add Secure Boot support
Sec_init has been called in the starting to initialize SEC Block (CAAM) which will be used for Secure Boot validation later for both ls2080a qds and rdb. 64-bit address in ESBC Header has been enabled as this SoC is based on armv8. Secure Boot defconfigs created for boards (NOR Boot). Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message - Added new configs in defconfigs as per new intermediate patches arch/arm/include/asm/fsl_secure_boot.h | 9 +++-- board/freescale/ls2080aqds/MAINTAINERS | 6 ++ board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/MAINTAINERS | 6 ++ board/freescale/ls2080ardb/ls2080ardb.c | 5 - configs/ls2080aqds_SECURE_BOOT_defconfig | 20 configs/ls2080ardb_SECURE_BOOT_defconfig | 20 configs/ls2085aqds_SECURE_BOOT_defconfig | 20 configs/ls2085ardb_SECURE_BOOT_defconfig | 20 include/configs/ls2080aqds.h | 2 ++ include/configs/ls2080ardb.h | 2 ++ 11 files changed, 111 insertions(+), 4 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 4eb3b15..b745194 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -18,7 +18,9 @@ #ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB +#define CONFIG_CMD_HASH #define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_HW_ACCEL #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA_FREESCALE_EXP @@ -42,8 +44,11 @@ #endif -#ifdef CONFIG_LS1043A -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit + * Similiarly for LS2080 and LS2085 + */ #define CONFIG_ESBC_ADDR_64BIT #endif diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 6f99ad0..558cef1 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -8,3 +8,9 @@ F: configs/ls2080aqds_defconfig F: configs/ls2080aqds_nand_defconfig F: configs/ls2085aqds_defconfig F: configs/ls2085aqds_nand_defconfig + +LS2080A_SECURE_BOOT BOARD +M: Saksham Jain <saksham.j...@nxp.freescale.com> +S: Maintained +F: configs/ls2080aqds_SECURE_BOOT_defconfig +F: configs/ls2085aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index aa256a2..ab101a4 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -248,7 +249,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index c9f3459..0817711d 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -8,3 +8,9 @@ F: configs/ls2080ardb_defconfig F: configs/ls2080ardb_nand_defconfig F: configs/ls2085ardb_defconfig F: configs/ls2085ardb_nand_defconfig + +LS2080A_SECURE_BOOT BOARD +M: Saksham Jain <saksham.j...@nxp.freescale.com> +S: Maintained +F: configs/ls2080ardb_SECURE_BOOT_defconfig +F: configs/ls2085ardb_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c63b639..0c78a41 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080ardb_qixis.h" @@ -214,7 +215,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig new file mode 100644 index 000..408d1ee --- /dev/null +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI
[U-Boot] [PATCH v5 07/14] ls2080: Change env variable "fdt_high"
"fdt_high" env variable has been changed to 0xa000 for ls2080 during Secure Boot. This env_varible is used to specify the upper limit to be used for copying flat device tree. This address must be visible to kernel. The "fdt_high" value has been set during Secure Boot to same value as it's default value during non-secure boot. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes Changes for v5: - Cleaned up commit message arch/arm/include/asm/fsl_secure_boot.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 4d04eea..d576f2e 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -52,10 +52,17 @@ #define CONFIG_ESBC_ADDR_64BIT #endif +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xa000;" \ + "setenv initrd_high 0xcfff;"\ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#else #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfff;" \ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#endif /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 10/14] crypto/fsl: Correct 64-bit Write when MMU disabled
When MMU is disabled, 64bit Write must be at a memory aligned at 64-bit Boundary. So, this commit splits the 64-bit write into two 32-bit writes as the memory location is not guaranteed to be 64-bit aligned. The alignment exception only occurs when MMU is disabled. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes Changes for v5: - Cleaned up commit message drivers/crypto/fsl/desc_constr.h | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index 2559ccd..db6ddee 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -85,10 +85,9 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) #ifdef CONFIG_PHYS_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ - union ptr_addr_t ptr_addr; - ptr_addr.m_halfs.high = (u32)(ptr >> 32); - ptr_addr.m_halfs.low = (u32)ptr; - *offset = ptr_addr.m_whole; + union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset; + ptr_addr->m_halfs.high = (u32)(ptr >> 32); + ptr_addr->m_halfs.low = (u32)ptr; #else *offset = ptr; #endif -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 01/14] armv8: ls2080: Add SFP Configs for LS2080
In LS2080, SFP is Little Endian and Verion is 3.4 . The base address is
0x01e80200. SFP will be used in Secure Boot to read fuses.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- Cleaned up commit message
Changes for v5:
- Cleaned up commit message
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++
include/fsl_sfp.h | 3 ++-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 0ef7c9d..380d5ac 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -67,6 +67,10 @@
/* SMMU Defintions */
#define SMMU_BASE 0x0500 /* GR0 Base */
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
#define CCI_MN_RNF_NODEID_LIST 0x180
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..f1b021f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -73,6 +73,9 @@
#define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR +
0x0220)
#define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR +
0x0221)
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
index 353a123..2976a2c 100644
--- a/include/fsl_sfp.h
+++ b/include/fsl_sfp.h
@@ -32,7 +32,8 @@
/* Number of SRKH registers */
#define NUM_SRKH_REGS 8
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+#ifdefined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
+ defined(CONFIG_SYS_FSL_SFP_VER_3_4)
struct ccsr_sfp_regs {
u32 ospr; /* 0x200 */
u32 ospr1; /* 0x204 */
--
1.8.1.4
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[U-Boot] [PATCH v5 02/14] ls2080: Add configs for SEC, SecMon, SRK and DCFG
For ls2080, Added configs for various IPs used during secure boot.
Added address and endianness for SEC and Security Monitor. SRK are
Fuses in SFP (Fuses for public key's hash). These are stored in Little
Endian format.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
-Cleaned up commit message
Changes for v5:
-Cleaned up commit message
arch/arm/include/asm/arch-fsl-layerscape/config.h | 10 ++
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 380d5ac..34851a9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -70,6 +70,16 @@
/* SFP */
#define CONFIG_SYS_FSL_SFP_VER_3_4
#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index f1b021f..1fc51e0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -76,6 +76,14 @@
/* SFP */
#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 0x0700)
+#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 0x0701)
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
@@ -204,6 +212,8 @@ struct ccsr_gur {
#defineFSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF00
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
+#define RCW_SB_EN_REG_INDEX9
+#define RCW_SB_EN_MASK 0x0400
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
--
1.8.1.4
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[U-Boot] [PATCH v5 00/14] Add Support for Secure Boot on LS2080
Secure Boot ESBC has been enabled on FSL LS208x platforms. Changes for v2: - changed function fsl_secboot_validate to return address of image - corrected Bootscript header for ls1043 and ls1021 Changes for v3: - minor changes to remove compilation warnings Changes for v4: - removed IE Key extenstion support. Methodology not fixed yet. - minor changes in commit messages (clean up) Changes for v5: - Cleaned up commit messages - Changed defconfigs to add configs like CONFIG_RSA (These were added by intermediate patches since these patches were floated for review) Saksham Jain (14): armv8: ls2080: Add SFP Configs for LS2080 ls2080: Add configs for SEC, SecMon, SRK and DCFG fsl: ls-ch3: Add new header for Secure Boot ls2080: Add Secure Boot support ls2080: Add bootscript header addr for secure boot fsl: ls-ch3: Copy Bootscript and header from NOR to DDR ls2080: Change env variable "fdt_high" ls2080: Add config for endianess of CCSR GUR armv8: fsl-lsch3: Disable SMMU during Secure Boot crypto/fsl: Correct 64-bit Write when MMU disabled crypto/fsl: Make CAAM transactions cacheable SECURE_BOOT: Use default bootargs SECURE BOOT: Halt execution when secure boot fail SECURE BOOT: Change fsl_secboot_validate func to ret image addr arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 +- arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 28 + arch/arm/include/asm/fsl_secure_boot.h | 50 ++-- board/freescale/common/cmd_esbc_validate.c | 14 - board/freescale/common/fsl_validate.c | 66 +++-- board/freescale/ls2080aqds/MAINTAINERS | 6 ++ board/freescale/ls2080aqds/ls2080aqds.c| 5 +- board/freescale/ls2080ardb/MAINTAINERS | 6 ++ board/freescale/ls2080ardb/ls2080ardb.c| 5 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 20 +++ configs/ls2080ardb_SECURE_BOOT_defconfig | 20 +++ configs/ls2085aqds_SECURE_BOOT_defconfig | 20 +++ configs/ls2085ardb_SECURE_BOOT_defconfig | 20 +++ drivers/crypto/fsl/desc_constr.h | 7 +-- drivers/crypto/fsl/jr.c| 13 + drivers/crypto/fsl/jr.h| 3 + include/config_fsl_chain_trust.h | 25 +--- include/configs/ls2080aqds.h | 2 + include/configs/ls2080ardb.h | 2 + include/fsl_secboot_err.h | 3 + include/fsl_sfp.h | 3 +- include/fsl_validate.h | 67 ++ 23 files changed, 373 insertions(+), 48 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 12/14] SECURE_BOOT: Use default bootargs
For secure boot, currently we were using fixed bootargs for all SoCs. This is not needed and we can use the bootargs which are used in non-secure boot. Incase bootargs are not defined for non-secure boot of any platform, we use default bootargs. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message include/config_fsl_chain_trust.h | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index aa222bb..566fd80 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -44,11 +44,18 @@ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" */ +#ifdef CONFIG_BOOTARGS +#define CONFIG_SET_BOOTARGS"setenv bootargs \'" CONFIG_BOOTARGS" \';" +#else +#define CONFIG_SET_BOOTARGS"setenv bootargs \'root=/dev/ram " \ + "rw console=ttyS0,115200 ramdisk_size=60\';" +#endif + + #ifdef CONFIG_BOOTSCRIPT_KEY_HASH #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr " \ __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ @@ -57,8 +64,7 @@ #else #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 14/14] SECURE BOOT: Change fsl_secboot_validate func to ret image addr
Currently, fsl_secboot_validate function used to set env variable
"img_addr" to contain address of image being validated.
The function has been changed to output image addr via argument
img_addr_ptr. The command esbc_validate sets the env variable
"img_addr".
This change helps when fsl_secboot_validate function is called from
within UBOOT (because now instead of calling function
"getenv("img_addr")" we can directly get the image address).
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- Cleaned up commit message
Changes for v5:
- Cleaned up commit message
board/freescale/common/cmd_esbc_validate.c | 12 +++-
board/freescale/common/fsl_validate.c | 26 +++---
include/fsl_validate.h | 4 ++--
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index 375bc24..cefe3cc 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -29,6 +29,8 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
char *hash_str = NULL;
uintptr_t haddr;
int ret;
+ uintptr_t img_addr = 0;
+ char buf[20];
if (argc < 2)
return cmd_usage(cmdtp);
@@ -43,7 +45,15 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
* part of header. So, the function is called
* by passing this argument as 0.
*/
- ret = fsl_secboot_validate(haddr, hash_str, 0);
+ ret = fsl_secboot_validate(haddr, hash_str, _addr);
+
+ /* Need to set "img_addr" even if validation failure.
+* Required when SB_EN in RCW set and non-fatal error
+* to continue U-Boot
+*/
+ sprintf(buf, "%lx", img_addr);
+ setenv("img_addr", buf);
+
if (ret)
return 1;
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 95059c7..64e4e30 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -570,7 +570,7 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
- (u8 *)img->img_addr, img->img_size, 1);
+ (u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
if (ret)
return ret;
@@ -646,7 +646,6 @@ static void construct_img_encoded_hash_second(struct
fsl_secboot_img_priv *img)
*/
static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
{
- char buf[20];
struct fsl_secboot_img_hdr *hdr = >hdr;
void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
u8 *k, *s;
@@ -661,17 +660,14 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
/* If Image Address is not passed as argument to function,
* then Address and Size must be read from the Header.
*/
- if (img->img_addr == 0) {
+ if (*(img->img_addr_ptr) == 0) {
#ifdef CONFIG_ESBC_ADDR_64BIT
- img->img_addr = hdr->pimg64;
+ *(img->img_addr_ptr) = hdr->pimg64;
#else
- img->img_addr = hdr->pimg;
+ *(img->img_addr_ptr) = hdr->pimg;
#endif
}
- sprintf(buf, "%lx", img->img_addr);
- setenv("img_addr", buf);
-
if (!hdr->img_size)
return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
@@ -814,9 +810,17 @@ static int calculate_cmp_img_sig(struct
fsl_secboot_img_priv *img)
return 0;
}
-
+/* haddr - Address of the header of image to be validated.
+ * arg_hash_str - Option hash string. If provided, this
+ * overides the key hash in the SFP fuses.
+ * img_addr_ptr - Optional pointer to address of image to be validated.
+ * If non zero addr, this overides the addr of image in header,
+ * otherwise updated to image addr in header.
+ * Acts as both input and output of function.
+ * This pointer shouldn't be NULL.
+ */
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
- uintptr_t img_addr)
+ uintptr_t *img_addr_ptr)
{
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
ulong hash[SHA256_BYTES/sizeof(ulong)];
@@ -869,7 +873,7 @@ int fsl_secboot_validate(uintptr_t haddr, char
*arg_hash_str,
/* Update the information in Private Struct */
hdr = >hdr;
img->ehdrloc = haddr;
- img->img_addr = img_addr;
+ img->img_addr_ptr = img_addr_ptr;
e
[U-Boot] [PATCH v5 06/14] fsl: ls-ch3: Copy Bootscript and header from NOR to DDR
During Secure Boot, a bootscript is validated using its header. This patch copies both these images to DDR from NOR and then validates and executed them from DDR. (If NOR is the boot source for LS2080). This copy step is done to make this step common across booting sources. Because in case of non-xip memories (e.g. NAND, SD) it is neccessary to copy both these images to DDR. For other ARM Platforms (ls1043 and ls1020), header is not copied from NOR to DDR (otherwise customers will need to modify the existing headers). Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - for platform such as ls1043 and ls1021, boot header in NOR. Not copied to NOR. For them, fixed CONFIG_BOOTSCRIPT_HDR_ADDR to CONFIG_BS_HDR_ADDR_FLASH. Changes for v3: - No change Changes for v4: -Cleaned up commit message Changes for v5: - Cleaned up commit message arch/arm/include/asm/fsl_secure_boot.h | 28 +--- include/config_fsl_chain_trust.h | 11 +++ 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 5575934..4d04eea 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -57,11 +57,33 @@ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -/* The address needs to be modified according to NOR memory map */ +/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from + * Non-XIP Memory (Nand/SD)*/ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif +/* The address needs to be modified according to NOR and DDR memory map */ #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#define CONFIG_BS_HDR_ADDR_FLASH 0x58392 +#define CONFIG_BS_ADDR_FLASH 0x58390 +#define CONFIG_BS_HDR_ADDR_RAM 0xa392 +#define CONFIG_BS_ADDR_RAM 0xa390 +#else +#define CONFIG_BS_HDR_ADDR_FLASH 0x600a +#define CONFIG_BS_ADDR_FLASH 0x6006 +#define CONFIG_BS_HDR_ADDR_RAM 0xa006 +#define CONFIG_BS_ADDR_RAM 0xa006 +#endif + +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#define CONFIG_BS_HDR_SIZE 0x2000 +#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM +#define CONFIG_BS_SIZE 0x1000 #else -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH +/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */ #endif #include diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 45dda56..aa222bb 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -65,8 +65,6 @@ "esbc_halt\0" #endif -/* For secure boot flow, default environment used will be used */ -#if defined(CONFIG_SYS_RAMBOOT) #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ @@ -76,14 +74,19 @@ "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" +/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ "nand read $bs_ram $bs_flash $bs_size ;" #endif /* CONFIG_RAMBOOT_NAND */ -#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ - +#else +#define CONFIG_BS_COPY_CMD \ + "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_flash $bs_ram $bs_size ;" #endif +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ #ifndef CONFIG_BS_COPY_ENV #define CONFIG_BS_COPY_ENV -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 05/14] Add bootscript header addr for ls2080a secure boot
During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it is executed. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080, NOR memory map is different from earlier arm SoCs. So a new address on NOR is used for this bootscript header (0x58392). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: -Cleaned up commit message Changes for v5: -Cleaned up commit message arch/arm/include/asm/fsl_secure_boot.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b745194..5575934 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -58,7 +58,11 @@ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" /* The address needs to be modified according to NOR memory map */ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#else #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#endif #include #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MAINTAINERS : Add entry for ls2080/5 SECURE BOOT defconfigs
Added myself as maintainers for the following: 1) configs/ls2080aqds_SECURE_BOOT_defconfig 2) configs/ls2085aqds_SECURE_BOOT_defconfig 3) configs/ls2080ardb_SECURE_BOOT_defconfig 4) configs/ls2085ardb_SECURE_BOOT_defconfig Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- This patch depends on patch which adds these defconfigs: http://patchwork.ozlabs.org/patch/580644/ board/freescale/ls2080aqds/MAINTAINERS | 6 ++ board/freescale/ls2080ardb/MAINTAINERS | 6 ++ 2 files changed, 12 insertions(+) diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 6f99ad0..aacd134 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -8,3 +8,9 @@ F: configs/ls2080aqds_defconfig F: configs/ls2080aqds_nand_defconfig F: configs/ls2085aqds_defconfig F: configs/ls2085aqds_nand_defconfig + +LS2080A_SECURE_BOOT BOARD +M: Saksham Jain <saksham.j...@nxp.com> +S: Maintained +F: configs/ls2080aqds_SECURE_BOOT_defconfig +F: configs/ls2085aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index c9f3459..4356637 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -8,3 +8,9 @@ F: configs/ls2080ardb_defconfig F: configs/ls2080ardb_nand_defconfig F: configs/ls2085ardb_defconfig F: configs/ls2085ardb_nand_defconfig + +LS2080A_SECURE_BOOT BOARD +M: Saksham Jain <saksham.j...@nxp.com> +S: Maintained +F: configs/ls2080ardb_SECURE_BOOT_defconfig +F: configs/ls2085ardb_SECURE_BOOT_defconfig -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 14/14] SECURE BOOT: Change fsl_secboot_validate function to output image addr
Currently, fsl_secboot_validate function used to set env variable "img_addr"
to contain address of image being validated.
The function has been changed to output image addr via argument
img_addr_ptr. The command esbc_validate sets the env variable
"img_addr".
This change helps when fsl_secboot_validate function is called from within
UBOOT (because now instead of calling function "getenv("img_addr")"
we can directly get the image address.)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- Cleaned up commit message
board/freescale/common/cmd_esbc_validate.c | 12 +++-
board/freescale/common/fsl_validate.c | 26 +++---
include/fsl_validate.h | 4 ++--
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index 375bc24..cefe3cc 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -29,6 +29,8 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
char *hash_str = NULL;
uintptr_t haddr;
int ret;
+ uintptr_t img_addr = 0;
+ char buf[20];
if (argc < 2)
return cmd_usage(cmdtp);
@@ -43,7 +45,15 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
* part of header. So, the function is called
* by passing this argument as 0.
*/
- ret = fsl_secboot_validate(haddr, hash_str, 0);
+ ret = fsl_secboot_validate(haddr, hash_str, _addr);
+
+ /* Need to set "img_addr" even if validation failure.
+* Required when SB_EN in RCW set and non-fatal error
+* to continue U-Boot
+*/
+ sprintf(buf, "%lx", img_addr);
+ setenv("img_addr", buf);
+
if (ret)
return 1;
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 95059c7..64e4e30 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -570,7 +570,7 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
- (u8 *)img->img_addr, img->img_size, 1);
+ (u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
if (ret)
return ret;
@@ -646,7 +646,6 @@ static void construct_img_encoded_hash_second(struct
fsl_secboot_img_priv *img)
*/
static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
{
- char buf[20];
struct fsl_secboot_img_hdr *hdr = >hdr;
void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
u8 *k, *s;
@@ -661,17 +660,14 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
/* If Image Address is not passed as argument to function,
* then Address and Size must be read from the Header.
*/
- if (img->img_addr == 0) {
+ if (*(img->img_addr_ptr) == 0) {
#ifdef CONFIG_ESBC_ADDR_64BIT
- img->img_addr = hdr->pimg64;
+ *(img->img_addr_ptr) = hdr->pimg64;
#else
- img->img_addr = hdr->pimg;
+ *(img->img_addr_ptr) = hdr->pimg;
#endif
}
- sprintf(buf, "%lx", img->img_addr);
- setenv("img_addr", buf);
-
if (!hdr->img_size)
return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
@@ -814,9 +810,17 @@ static int calculate_cmp_img_sig(struct
fsl_secboot_img_priv *img)
return 0;
}
-
+/* haddr - Address of the header of image to be validated.
+ * arg_hash_str - Option hash string. If provided, this
+ * overides the key hash in the SFP fuses.
+ * img_addr_ptr - Optional pointer to address of image to be validated.
+ * If non zero addr, this overides the addr of image in header,
+ * otherwise updated to image addr in header.
+ * Acts as both input and output of function.
+ * This pointer shouldn't be NULL.
+ */
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
- uintptr_t img_addr)
+ uintptr_t *img_addr_ptr)
{
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
ulong hash[SHA256_BYTES/sizeof(ulong)];
@@ -869,7 +873,7 @@ int fsl_secboot_validate(uintptr_t haddr, char
*arg_hash_str,
/* Update the information in Private Struct */
hdr = >hdr;
img->ehdrloc = haddr;
- img->img_addr = img_addr;
+ img->img_addr_ptr = img_addr_ptr;
esbc = (u8 *)img->ehdrloc;
memcpy(hdr,
[U-Boot] [PATCH v4 10/14] crypto/fsl: Correct 64bit Write when MMU disabled
When MMU is disabled, 64bit Write must be at a memory aligned at 64bit Boundary. So, this commit splits the 64bit write into 2 -32bit writes as the memory location is not guaranteed to be 64bit aligned. The alignment exception only occurs when MMU is disabled. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes drivers/crypto/fsl/desc_constr.h | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index 2559ccd..db6ddee 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -85,10 +85,9 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) #ifdef CONFIG_PHYS_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ - union ptr_addr_t ptr_addr; - ptr_addr.m_halfs.high = (u32)(ptr >> 32); - ptr_addr.m_halfs.low = (u32)ptr; - *offset = ptr_addr.m_whole; + union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset; + ptr_addr->m_halfs.high = (u32)(ptr >> 32); + ptr_addr->m_halfs.low = (u32)ptr; #else *offset = ptr; #endif -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 13/14] SECURE BOOT: Halt execution when secure boot fail after reset request
In case of fatal failure during secure boot execution (e.g. header not found)
it is needed that the execution stops.
Earlier, we were asserting reset request in case in case of failure. But if
the RESET_REQ is not tied off to HRESET, this allows the execution to continue.
This can either be taken care in bootscript (Execute esbc_halt command in case
of
image verification process) or it can be taken care in Uboot Code.
Doing the latter via a esbc_halt.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Chnages for v4:
- Cleaned up commit message
board/freescale/common/cmd_esbc_validate.c | 2 +-
board/freescale/common/fsl_validate.c | 5 +
include/fsl_validate.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index dfa3e21..375bc24 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -8,7 +8,7 @@
#include
#include
-static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (fsl_check_boot_mode_secure() == 0) {
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index c12b9c9..95059c7 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -325,6 +325,8 @@ static void fsl_secboot_header_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
}
/*
@@ -355,6 +357,9 @@ static void fsl_secboot_image_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
+
} else {
change_sec_mon_state(HPSR_SSM_ST_TRUST,
HPSR_SSM_ST_NON_SECURE);
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index f812c1a..ff6f6b7 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -242,6 +242,9 @@ struct fsl_secboot_img_priv {
uint32_t img_size; /* ESBC Image Size */
};
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
uintptr_t img_loc);
int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
--
1.8.1.4
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[U-Boot] [PATCH v4 12/14] SECURE_BOOT: Use default bootargs during Secure Boot
For secure boot, currently we were using fixed bootargs for all SoCs. This is not needed and we can use the bootargs which are used in non-secure boot. Incase bootargs are not defined for non-secure boot of any platform, we use default bootargs. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message include/config_fsl_chain_trust.h | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index aa222bb..566fd80 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -44,11 +44,18 @@ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" */ +#ifdef CONFIG_BOOTARGS +#define CONFIG_SET_BOOTARGS"setenv bootargs \'" CONFIG_BOOTARGS" \';" +#else +#define CONFIG_SET_BOOTARGS"setenv bootargs \'root=/dev/ram " \ + "rw console=ttyS0,115200 ramdisk_size=60\';" +#endif + + #ifdef CONFIG_BOOTSCRIPT_KEY_HASH #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr " \ __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ @@ -57,8 +64,7 @@ #else #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 04/14] SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb
Following changes have been made to enable secure boot: 1) Sec_init has been called in starting to initialize SEC Block (CAAM) which will be used for Secure Boot validation later for both ls2080a qds and rdb 2) 64Bit address in ESBC Header has been enabled as this SoC is based on armv8 3) Secure Boot defconfigs created for boards (NOR Boot). Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message arch/arm/include/asm/fsl_secure_boot.h | 9 +++-- board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - configs/ls2080aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2080ardb_SECURE_BOOT_defconfig | 15 +++ configs/ls2085aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2085ardb_SECURE_BOOT_defconfig | 15 +++ include/configs/ls2080aqds.h | 2 ++ include/configs/ls2080ardb.h | 2 ++ 9 files changed, 79 insertions(+), 4 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 3e46c63..e65caed 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -18,7 +18,9 @@ #ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB +#define CONFIG_CMD_HASH #define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_HW_ACCEL #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP @@ -47,8 +49,11 @@ #endif -#ifdef CONFIG_LS1043A -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit + * Similiarly for LS2080 and LS2085 + */ #define CONFIG_ESBC_ADDR_64BIT #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index aa256a2..ab101a4 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -248,7 +249,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c63b639..0c78a41 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080ardb_qixis.h" @@ -214,7 +215,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig new file mode 100644 index 000..5c50894 --- /dev/null +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig new file mode 100644 index 000..9456e04 --- /dev/null +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2085aqds_SECURE_BOOT_defconfig b/configs/ls2085aqds_SECURE_BOOT_defconfig new file mode 100644 index 000..8f96fc0 --- /dev/null +++ b/configs/ls2085aqds_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +C
[U-Boot] [PATCH v4 03/14] SECURE BOOT: Add new ESBC header for ls-ch3 Secure Boot
For Secure Boot, a header is used to identify key table, signature
and image address. For LS-CH3, there is a new header structure being used.
The following changes are there in the new header:
1) Currently IE Table (Key extension) feature is not supported
2) Single Key feature is not supported. Keys must be in table format.
3) Hence, SRK (Key table) is by default currently always present.
4) Max Key number has increase from 4 to 8. 8th Key is unrevockable.
5) New Barker Code is being used.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- Cleaned up commit message
arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +-
arch/arm/include/asm/fsl_secure_boot.h| 4 ++
board/freescale/common/fsl_validate.c | 35 +++--
include/fsl_secboot_err.h | 3 ++
include/fsl_validate.h| 60 ---
5 files changed, 91 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index d2d54b7..e975e25 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -79,7 +79,8 @@
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
-
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index 0da0599..3e46c63 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -40,9 +40,13 @@
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
*/
+#ifndef CONFIG_ESBC_HDR_LS
+/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
+#endif
+
#ifdef CONFIG_LS1043A
/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
#define CONFIG_ESBC_ADDR_64BIT
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 8fd6dd6..c12b9c9 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -35,7 +35,13 @@ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30,
0x0d, 0x06, 0x09, 0x60,
};
static u8 hash_val[SHA256_BYTES];
+
+#ifdef CONFIG_ESBC_HDR_LS
+/* New Barker Code for LS ESBC Header */
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
+#else
static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+#endif
void branch_to_self(void) __attribute__ ((noreturn));
@@ -157,10 +163,15 @@ static int get_ie_info_addr(u32 *ie_addr)
/* This function checks srk_table_flag in header and set/reset srk_flag.*/
static u32 check_srk(struct fsl_secboot_img_priv *img)
{
+#ifdef CONFIG_ESBC_HDR_LS
+ /* In LS, No SRK Flag as SRK is always present*/
+ return 1;
+#else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
return 1;
return 0;
+#endif
}
/* This function returns ospr's key_revoc values.*/
@@ -223,6 +234,7 @@ static u32 read_validate_srk_tbl(struct
fsl_secboot_img_priv *img)
}
#endif
+#ifndef CONFIG_ESBC_HDR_LS
static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
{
struct fsl_secboot_img_hdr *hdr = >hdr;
@@ -238,6 +250,7 @@ static u32 read_validate_single_key(struct
fsl_secboot_img_priv *img)
return 0;
}
+#endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
@@ -388,6 +401,7 @@ void fsl_secboot_handle_error(int error)
case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+ case ERROR_KEY_TABLE_NOT_FOUND:
#ifdef CONFIG_KEY_REVOCATION
case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
@@ -536,11 +550,18 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
if (!key_hash && check_ie(img))
key_hash = 1;
#endif
- if (!key_hash)
+#ifndef CONFIG_ESBC_HDR_LS
+/* No single key support in LS ESBC header */
+ if (!key_hash) {
ret = algo->hash_update(algo, ctx,
img->img_key, img->hdr.key_len, 0);
+ key_hash = 1;
+ }
+#endif
if (ret)
return ret;
+ if (!key_hash)
+ return ERROR_KEY_TABLE_NOT_FOUND;
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
@@ -626,8 +647,6 @@ static int read_validate_esbc_
[U-Boot] [PATCH v4 06/14] SECURE BOOT: Copy Bootscript and header from NOR to DDR for LS2080/5
During Secure Boot, a bootscript is validated using its header. This patch copies both these images to DDR from NOR and then validates and executed them from DDR. (If NOR is the boot source for LS2080 and LS2085). This copy step is done to make this step common across booting sources. Because in case of non-xip memories (e.g. NAND, SD) it is neccessary to copy both these images to DDR. For other ARM Platforms (ls1043 and ls1020), header is not copied from NOR to DDR (otherwise customers will need to modify the existing headers). Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - for platform such as ls1043 and ls1021, boot header in NOR. Not copied to NOR. For them, fixed CONFIG_BOOTSCRIPT_HDR_ADDR to CONFIG_BS_HDR_ADDR_FLASH. Changes for v3: - No change Changes for v4: -Cleaned up commit message arch/arm/include/asm/fsl_secure_boot.h | 28 +--- include/config_fsl_chain_trust.h | 11 +++ 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 7c55ea1..7ab9623 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -62,11 +62,33 @@ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -/* The address needs to be modified according to NOR memory map */ +/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from + * Non-XIP Memory (Nand/SD)*/ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif +/* The address needs to be modified according to NOR and DDR memory map */ #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#define CONFIG_BS_HDR_ADDR_FLASH 0x58392 +#define CONFIG_BS_ADDR_FLASH 0x58390 +#define CONFIG_BS_HDR_ADDR_RAM 0xa392 +#define CONFIG_BS_ADDR_RAM 0xa390 +#else +#define CONFIG_BS_HDR_ADDR_FLASH 0x600a +#define CONFIG_BS_ADDR_FLASH 0x6006 +#define CONFIG_BS_HDR_ADDR_RAM 0xa006 +#define CONFIG_BS_ADDR_RAM 0xa006 +#endif + +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#define CONFIG_BS_HDR_SIZE 0x2000 +#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM +#define CONFIG_BS_SIZE 0x1000 #else -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH +/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */ #endif #include diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 45dda56..aa222bb 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -65,8 +65,6 @@ "esbc_halt\0" #endif -/* For secure boot flow, default environment used will be used */ -#if defined(CONFIG_SYS_RAMBOOT) #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ @@ -76,14 +74,19 @@ "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" +/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ "nand read $bs_ram $bs_flash $bs_size ;" #endif /* CONFIG_RAMBOOT_NAND */ -#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ - +#else +#define CONFIG_BS_COPY_CMD \ + "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_flash $bs_ram $bs_size ;" #endif +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ #ifndef CONFIG_BS_COPY_ENV #define CONFIG_BS_COPY_ENV -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 09/14] armv8: fsl-lsch3: Disable SMMU during Secure Boot
During secure boot, SMMU is enabled on POR by SP bootrom.
SMMU needs to be put in Bypass mode in uboot to
enable CAAM transcations to pass through.
During Nonsecure Boot, SP BootROM doesn't enable SMMU and
at reset SMMU is in bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- No changes
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 +-
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7ff0148..0043523 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -151,7 +151,14 @@ static void erratum_a009203(void)
#endif
#endif
}
-
+void bypass_smmu(void)
+{
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+}
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
@@ -160,6 +167,15 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ if (fsl_check_boot_mode_secure() == 1)
+ bypass_smmu();
+#endif
}
#ifdef CONFIG_SCSI_AHCI_PLAT
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1fc51e0..06d4856 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -83,6 +83,21 @@
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+/* MMU 500 */
+#define SMMU_SCR0 (SMMU_BASE + 0x0)
+#define SMMU_SCR1 (SMMU_BASE + 0x4)
+#define SMMU_SCR2 (SMMU_BASE + 0x8)
+#define SMMU_SACR (SMMU_BASE + 0x10)
+#define SMMU_IDR0 (SMMU_BASE + 0x20)
+#define SMMU_IDR1 (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0 (SMMU_BASE + 0x400)
+#define SMMU_NSCR2 (SMMU_BASE + 0x408)
+#define SMMU_NSACR (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK 0x0001
+#define SCR0_USFCFG_MASK 0x0400
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
--
1.8.1.4
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[U-Boot] [PATCH v4 08/14] armv8 : ls2080: Add config for endianess of CCSR GUR
The GUR (DCFG) registers in CCSR space are in LE format for ls2080/ls2085. Defined a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index e975e25..7f95191 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -82,6 +82,9 @@ /* Secure Boot */ #define CONFIG_ESBC_HDR_LS +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + /* Cache Coherent Interconnect */ #define CCI_MN_BASE0x0400 #define CCI_MN_RNF_NODEID_LIST 0x180 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 11/14] crypto/fsl: Make CAAM transactions cacheable
To solve CAAM coherency issue on ls2080a and ls2085a. When Caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/write data from/to Caches and CAAM does from Main Memory. This forces data flushes to synchronize various data structures But even if any data in proximity of these structures is read by core, these structures again are fetched in caches. To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable. So, this commit makes CAAM transcations as Write Back with Write and Read Allocate. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message drivers/crypto/fsl/jr.c | 13 + drivers/crypto/fsl/jr.h | 3 +++ 2 files changed, 16 insertions(+) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b553e3c..987d946 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -530,7 +530,20 @@ int sec_init(void) uint32_t mcr = sec_in32(>mcfgr); int ret = 0; + /* +* Modifying CAAM Read/Write Attributes +* For LS2080A and LS2085A +* For AXI Write - Cacheable, Write Back, Write allocate +* For AXI Read - Cacheable, Read allocate +* Only For LS2080a and LS2085a, to solve CAAM coherency issues +*/ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); + mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); +#else mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); +#endif + #ifdef CONFIG_PHYS_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 5899696..1f2e324 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -23,6 +23,9 @@ #define MCFGR_PS_SHIFT 16 #define MCFGR_AWCACHE_SHIFT8 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_ARCACHE_SHIFT12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) + #define JR_INTMASK 0x0001 #define JRCR_RESET 0x01 #define JRINT_ERR_HALT_INPROGRESS 0x4 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 07/14] SECURE BOOT: Change env variable "fdt_high" for LS2080a and LS2085a
"fdt_high" env variable has been changed to 0xa000 for ls2080a and ls2085a during Secure Boot. This env_varible is used to specify the upper limit to be used for copying flat device tree. This address must be visible to kernel. The "fdt_high" value has been set during Secure Boot to same value as it's default value during non-secure boot. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes arch/arm/include/asm/fsl_secure_boot.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 7ab9623..eafdc0b 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -57,10 +57,17 @@ #define CONFIG_ESBC_ADDR_64BIT #endif +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xa000;" \ + "setenv initrd_high 0xcfff;"\ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#else #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfff;" \ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#endif /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 02/14] armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and RCW
For ls2080, Added configs for various IPs used during secure boot
Added address and endianness for SEC and Security Monitor.
SRK - Fuses in SFP (Fused for public keys hash)
These are stored in LE format.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
-Cleaned up commit message
arch/arm/include/asm/arch-fsl-layerscape/config.h | 10 ++
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 997ff00a..d2d54b7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -70,6 +70,16 @@
/* SFP */
#define CONFIG_SYS_FSL_SFP_VER_3_4
#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index f1b021f..1fc51e0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -76,6 +76,14 @@
/* SFP */
#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 0x0700)
+#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 0x0701)
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
@@ -204,6 +212,8 @@ struct ccsr_gur {
#defineFSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF00
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
+#define RCW_SB_EN_REG_INDEX9
+#define RCW_SB_EN_MASK 0x0400
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
--
1.8.1.4
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[U-Boot] [PATCH v4 00/14] Add Support for Secure Boot on LS208x
Secure Boot ESBC has been enabled on FSL LS208x platforms. Changes for v2: - changed function fsl_secboot_validate to return address of image - corrected Bootscript header for ls1043 and ls1021 Changes for v3: - minor changes to remove compilation warnings Changes ofr v4: - removed IE Key extenstion support. Methodology not fixed yet. - minor changes in commit messages (clean up) Saksham Jain (14): armv8: ls2080: Add SFP Configs for LS2080/LS2085 armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and RCW SECURE BOOT: Add new ESBC header for ls-ch3 Secure Boot SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb armv8: fsl-lsch3: Add bootscript header address for Secure Boot SECURE BOOT: Copy Bootscript and header from NOR to DDR for LS2080/5 SECURE BOOT: Change env variable "fdt_high" for LS2080a and LS2085a armv8 : ls2080: Add config for endianess of CCSR GUR armv8: fsl-lsch3: Disable SMMU during Secure Boot crypto/fsl: Correct 64bit Write when MMU disabled crypto/fsl: Make CAAM transactions cacheable SECURE_BOOT: Use default bootargs during Secure Boot SECURE BOOT: Halt execution when secure boot fail after reset request SECURE BOOT: Change fsl_secboot_validate function to output image addr arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 +- arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 28 + arch/arm/include/asm/fsl_secure_boot.h | 50 ++-- board/freescale/common/cmd_esbc_validate.c | 14 - board/freescale/common/fsl_validate.c | 66 +++-- board/freescale/ls2080aqds/ls2080aqds.c| 5 +- board/freescale/ls2080ardb/ls2080ardb.c| 5 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 15 + configs/ls2080ardb_SECURE_BOOT_defconfig | 15 + configs/ls2085aqds_SECURE_BOOT_defconfig | 15 + configs/ls2085ardb_SECURE_BOOT_defconfig | 15 + drivers/crypto/fsl/desc_constr.h | 7 +-- drivers/crypto/fsl/jr.c| 13 + drivers/crypto/fsl/jr.h| 3 + include/config_fsl_chain_trust.h | 25 +--- include/configs/ls2080aqds.h | 2 + include/configs/ls2080ardb.h | 2 + include/fsl_secboot_err.h | 3 + include/fsl_sfp.h | 3 +- include/fsl_validate.h | 67 ++ 21 files changed, 341 insertions(+), 48 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 01/14] armv8: ls2080: Add SFP Configs for LS2080/LS2085
In LS2080/LS2085, SFP is LE and Ver is 3.4
The base address is 0x01e80200
SFP will be used in Secure Boot to read fuses.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- Cleaned up commit message
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++
include/fsl_sfp.h | 3 ++-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index ff3b1be..997ff00a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -67,6 +67,10 @@
/* SMMU Defintions */
#define SMMU_BASE 0x0500 /* GR0 Base */
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
#define CCI_MN_RNF_NODEID_LIST 0x180
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..f1b021f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -73,6 +73,9 @@
#define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR +
0x0220)
#define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR +
0x0221)
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
index 353a123..2976a2c 100644
--- a/include/fsl_sfp.h
+++ b/include/fsl_sfp.h
@@ -32,7 +32,8 @@
/* Number of SRKH registers */
#define NUM_SRKH_REGS 8
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+#ifdefined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
+ defined(CONFIG_SYS_FSL_SFP_VER_3_4)
struct ccsr_sfp_regs {
u32 ospr; /* 0x200 */
u32 ospr1; /* 0x204 */
--
1.8.1.4
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[U-Boot] [PATCH v4 05/14] armv8: fsl-lsch3: Add bootscript header address for Secure Boot
During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it is executed. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080/5, NOR memory map is different from earlier arm SoCs. So a new address on NOR is used for this bootscript header. (0x58392). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: -Cleaned up commit message arch/arm/include/asm/fsl_secure_boot.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index e65caed..7c55ea1 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -63,7 +63,11 @@ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" /* The address needs to be modified according to NOR memory map */ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#else #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#endif #include #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 02/15] armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and RCW
For ls2080, Added configs for various IPs used during secure boot
Added address and endianness for SEC and Security Monitor.
SRK - Fuses in SFP (Fused for public keys hash)
These are stored in LE format.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
arch/arm/include/asm/arch-fsl-layerscape/config.h | 10 ++
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5a33ff1..16f60a1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -70,6 +70,16 @@
/* SFP */
#define CONFIG_SYS_FSL_SFP_VER_3_4
#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index f1b021f..1fc51e0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -76,6 +76,14 @@
/* SFP */
#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 0x0700)
+#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 0x0701)
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
@@ -204,6 +212,8 @@ struct ccsr_gur {
#defineFSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF00
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
+#define RCW_SB_EN_REG_INDEX9
+#define RCW_SB_EN_MASK 0x0400
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
--
1.8.1.4
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[U-Boot] [PATCH v3 01/15] armv8: ls2080: Add SFP Configs for LS2080/LS2085
In LS2080/LS2085, SFP is LE and Ver is 3.4
The base address is 0x01e80200
SFP will be used in Secure Boot to read fuses.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++
include/fsl_sfp.h | 3 ++-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 49b113d..5a33ff1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -67,6 +67,10 @@
/* SMMU Defintions */
#define SMMU_BASE 0x0500 /* GR0 Base */
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
#define CCI_MN_RNF_NODEID_LIST 0x180
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..f1b021f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -73,6 +73,9 @@
#define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR +
0x0220)
#define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR +
0x0221)
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
index 353a123..2976a2c 100644
--- a/include/fsl_sfp.h
+++ b/include/fsl_sfp.h
@@ -32,7 +32,8 @@
/* Number of SRKH registers */
#define NUM_SRKH_REGS 8
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+#ifdefined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
+ defined(CONFIG_SYS_FSL_SFP_VER_3_4)
struct ccsr_sfp_regs {
u32 ospr; /* 0x200 */
u32 ospr1; /* 0x204 */
--
1.8.1.4
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[U-Boot] [PATCH v3 00/15] Add Support for Secure Boot on LS208x
Secure Boot ESBC has been enabled on FSL LS208x platforms. This patchset is dependent on http://patchwork.ozlabs.org/patch/571612/ Changes for v2: - changed function fsl_secboot_validate to return address of image - corrected Bootscript header for ls1043 and ls1021 Changes for v3: - minor changes to remove compilation warnings Saksham Jain (15): armv8: ls2080: Add SFP Configs for LS2080/LS2085 armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and RCW SECURE BOOT: Add new ESBC header for ls-ch3 Secure Boot SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb armv8: fsl-lsch3: Add bootscript header address for Secure Boot SECURE BOOT: Copy Bootscript and header from NOR to DDR for LS2080/5 SECURE BOOT: Change env variable "fdt_high" for LS2080a and LS2085a armv8 : ls2080: Add config for endianess of CCSR GUR armv8: fsl-lsch3: Disable SMMU during Secure Boot crypto/fsl: Correct 64bit Write when MMU disabled crypto/fsl: Make CAAM transactions cacheable SECURE_BOOT: Use default bootargs during Secure Boot SECURE BOOT: Halt execution when secure boot fail after reset request SECURE BOOT: Change fsl_secboot_validate function to output image addr SECURE_BOOT: Enable IE (Key extention) Feature in Ls2085a & LS2088a arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 ++- arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 +++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 28 arch/arm/include/asm/fsl_secure_boot.h | 50 ++- board/freescale/common/cmd_esbc_validate.c | 14 +- board/freescale/common/fsl_validate.c | 159 + board/freescale/ls2080aqds/ls2080aqds.c| 5 +- board/freescale/ls2080ardb/ls2080ardb.c| 5 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 15 ++ configs/ls2080ardb_SECURE_BOOT_defconfig | 15 ++ configs/ls2085aqds_SECURE_BOOT_defconfig | 15 ++ configs/ls2085ardb_SECURE_BOOT_defconfig | 15 ++ drivers/crypto/fsl/desc_constr.h | 7 +- drivers/crypto/fsl/jr.c| 13 ++ drivers/crypto/fsl/jr.h| 3 + include/config_fsl_chain_trust.h | 25 ++-- include/configs/ls2080aqds.h | 2 + include/configs/ls2080ardb.h | 2 + include/fsl_secboot_err.h | 3 + include/fsl_sfp.h | 3 +- include/fsl_validate.h | 88 ++-- 21 files changed, 440 insertions(+), 63 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 13/15] SECURE BOOT: Halt execution when secure boot fail after reset request
In case of fatal failure during secure boot execution (e.g. header not found)
it is needed that the execution stops.
Earlier, we were asserting reset request in case in case of failure. But if
the RESET_REQ is not tied off to HRESET, this allows the execution to continue.
This can either be taken care in bootscript (Execute esbc_halt command in case
of
image verification process) or it can be taken care in Uboot Code.
Doing the latter via a esbc_halt.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
board/freescale/common/cmd_esbc_validate.c | 2 +-
board/freescale/common/fsl_validate.c | 5 +
include/fsl_validate.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index dfa3e21..375bc24 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -8,7 +8,7 @@
#include
#include
-static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (fsl_check_boot_mode_secure() == 0) {
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index c12b9c9..95059c7 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -325,6 +325,8 @@ static void fsl_secboot_header_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
}
/*
@@ -355,6 +357,9 @@ static void fsl_secboot_image_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
+
} else {
change_sec_mon_state(HPSR_SSM_ST_TRUST,
HPSR_SSM_ST_NON_SECURE);
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index f812c1a..ff6f6b7 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -242,6 +242,9 @@ struct fsl_secboot_img_priv {
uint32_t img_size; /* ESBC Image Size */
};
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
uintptr_t img_loc);
int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
--
1.8.1.4
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[U-Boot] [PATCH v3 15/15] SECURE_BOOT: Enable IE (Key extention) Feature in Ls2085a & LS2088a
For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a veriied table of public keys
can be used. The latter feature is called IE Key Extension Feature.
For earlier SoCs, BootROM used to verify IE Key Table and then write the
address of this table in a secure register (SCRATCHREG). But in LS2088 and
LS2085, no such secure registers are available. Hence IE Table is left to be
verified by Uboot.
The new procedure is to first verify IE table using Keys stored in fuses,
and then use the keys in this table to verify further images. So the steps
are:
1) Verify IE Table (If "IE Table Flag" set in any image
i.e. Verify IE Table only when any image needs IE Table's Key to be verified)
2) Install IE table. (To be used across verification of multiple images.
Stored in a static global structure.)
3) If IE flag enabled in header of any image, Use keys from IE table,
otherwise use keys tied up with SoC's fuses (SRK).
The address of IE Table HDR is fixed for NOR. In case of boot from other
devices, IE Table and it's Header needs to be copied to an XIP Memory.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
-changes to remove compliation warning for various platforms
arch/arm/include/asm/fsl_secure_boot.h | 6 +--
board/freescale/common/fsl_validate.c | 97 --
include/fsl_validate.h | 23 +++-
3 files changed, 105 insertions(+), 21 deletions(-)
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index eafdc0b..061c9f5 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -41,11 +41,11 @@
* in boot ROM of the SoC.
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
+ * For LS, this feature is available for all device if IE Table
+ * is copied to XIP memory
+ * Also, for LS, ISBC doesn't verify this table.
*/
-#ifndef CONFIG_ESBC_HDR_LS
-/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
-#endif
#endif
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 64e4e30..248a759 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -27,6 +27,10 @@
#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
((key_len) == 2 * KEY_SIZE_BYTES))
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+/* Global data structure */
+static struct fsl_secboot_glb glb;
+#endif
/* This array contains DER value for SHA-256 */
static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
@@ -60,7 +64,7 @@ self:
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 check_ie(struct fsl_secboot_img_priv *img)
{
- if (img->hdr.ie_flag)
+ if (img->hdr.ie_flag & IE_FLAG_MASK)
return 1;
return 0;
@@ -119,7 +123,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
}
#endif
-static int get_ie_info_addr(u32 *ie_addr)
+#if !defined(CONFIG_ESBC_HDR_LS)
+static int get_ie_info_addr(uintptr_t *ie_addr)
{
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
@@ -147,16 +152,17 @@ static int get_ie_info_addr(u32 *ie_addr)
/* IE Key Table is the first entry in the SG Table */
#if defined(CONFIG_MPC85xx)
- *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
- flash_base_addr;
+ *ie_addr = (uintptr_t)((sg_tbl->src_addr &
+ ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ flash_base_addr);
#else
- *ie_addr = sg_tbl->src_addr;
+ *ie_addr = (uintptr_t)sg_tbl->src_addr;
#endif
- debug("IE Table address is %x\n", *ie_addr);
+ debug("IE Table address is %lx\n", *ie_addr);
return 0;
}
-
+#endif /* CONFIG_ESBC_HDR_LS */
#endif
#ifdef CONFIG_KEY_REVOCATION
@@ -164,7 +170,10 @@ static int get_ie_info_addr(u32 *ie_addr)
static u32 check_srk(struct fsl_secboot_img_priv *img)
{
#ifdef CONFIG_ESBC_HDR_LS
- /* In LS, No SRK Flag as SRK is always present*/
+ /* In LS, No SRK Flag as SRK is always present if IE not present*/
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ return !check_ie(img);
+#endif
return 1;
#else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
@@ -253,14 +262,51 @@ static u32 read_validate_single_key(struct
fsl_secboot_img_priv *img)
#endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+
+#if defined(CONFIG_ESBC_HDR_LS)
+static void install_ie_tbl(uintptr_t ie_tbl_addr,
+
[U-Boot] [PATCH v3 14/15] SECURE BOOT: Change fsl_secboot_validate function to output image addr
Currently, fsl_secboot_validate function used to set env variable "img_addr"
to contain address of image being validated.
The function has been changed to output image addr via argument
img_addr_ptr. The command esbc_validate sets the env variable
"img_addr".
This change helps when fsl_secboot_validate function is called from within
UBOOT (because now instead of calling function "getenv("img_addr")"
we can directly get the image address.)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- Not present in v1 patches.
Changes for v3:
- No changes
board/freescale/common/cmd_esbc_validate.c | 12 +++-
board/freescale/common/fsl_validate.c | 26 +++---
include/fsl_validate.h | 4 ++--
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index 375bc24..cefe3cc 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -29,6 +29,8 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
char *hash_str = NULL;
uintptr_t haddr;
int ret;
+ uintptr_t img_addr = 0;
+ char buf[20];
if (argc < 2)
return cmd_usage(cmdtp);
@@ -43,7 +45,15 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
* part of header. So, the function is called
* by passing this argument as 0.
*/
- ret = fsl_secboot_validate(haddr, hash_str, 0);
+ ret = fsl_secboot_validate(haddr, hash_str, _addr);
+
+ /* Need to set "img_addr" even if validation failure.
+* Required when SB_EN in RCW set and non-fatal error
+* to continue U-Boot
+*/
+ sprintf(buf, "%lx", img_addr);
+ setenv("img_addr", buf);
+
if (ret)
return 1;
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 95059c7..64e4e30 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -570,7 +570,7 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
- (u8 *)img->img_addr, img->img_size, 1);
+ (u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
if (ret)
return ret;
@@ -646,7 +646,6 @@ static void construct_img_encoded_hash_second(struct
fsl_secboot_img_priv *img)
*/
static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
{
- char buf[20];
struct fsl_secboot_img_hdr *hdr = >hdr;
void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
u8 *k, *s;
@@ -661,17 +660,14 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
/* If Image Address is not passed as argument to function,
* then Address and Size must be read from the Header.
*/
- if (img->img_addr == 0) {
+ if (*(img->img_addr_ptr) == 0) {
#ifdef CONFIG_ESBC_ADDR_64BIT
- img->img_addr = hdr->pimg64;
+ *(img->img_addr_ptr) = hdr->pimg64;
#else
- img->img_addr = hdr->pimg;
+ *(img->img_addr_ptr) = hdr->pimg;
#endif
}
- sprintf(buf, "%lx", img->img_addr);
- setenv("img_addr", buf);
-
if (!hdr->img_size)
return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
@@ -814,9 +810,17 @@ static int calculate_cmp_img_sig(struct
fsl_secboot_img_priv *img)
return 0;
}
-
+/* haddr - Address of the header of image to be validated.
+ * arg_hash_str - Option hash string. If provided, this
+ * overides the key hash in the SFP fuses.
+ * img_addr_ptr - Optional pointer to address of image to be validated.
+ * If non zero addr, this overides the addr of image in header,
+ * otherwise updated to image addr in header.
+ * Acts as both input and output of function.
+ * This pointer shouldn't be NULL.
+ */
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
- uintptr_t img_addr)
+ uintptr_t *img_addr_ptr)
{
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
ulong hash[SHA256_BYTES/sizeof(ulong)];
@@ -869,7 +873,7 @@ int fsl_secboot_validate(uintptr_t haddr, char
*arg_hash_str,
/* Update the information in Private Struct */
hdr = >hdr;
img->ehdrloc = haddr;
- img->img_addr = img_addr;
+ img->img_addr_ptr = img_addr_ptr;
esbc = (u8 *)img->ehdrloc;
memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr))
[U-Boot] [PATCH v3 05/15] armv8: fsl-lsch3: Add bootscript header address for Secure Boot
During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it is executed. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080/5, NOR memory map is different from earlier arm SoCs. So a new address on NOR is used for this bootscript header. (0x58392). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes arch/arm/include/asm/fsl_secure_boot.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index e65caed..7c55ea1 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -63,7 +63,11 @@ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" /* The address needs to be modified according to NOR memory map */ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#else #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#endif #include #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 04/15] SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb
Following changes have been made to enable secure boot: 1) Sec_init has been called in starting to initialize SEC Block (CAAM) which will be used for Secure Boot validation later for both ls2080a qds and rdb 2) 64Bit address in ESBC Header has been enabled as this SoC is based on armv8 3) Secure Boot defconfigs created for boards (NOR Boot). Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes arch/arm/include/asm/fsl_secure_boot.h | 9 +++-- board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - configs/ls2080aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2080ardb_SECURE_BOOT_defconfig | 15 +++ configs/ls2085aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2085ardb_SECURE_BOOT_defconfig | 15 +++ include/configs/ls2080aqds.h | 2 ++ include/configs/ls2080ardb.h | 2 ++ 9 files changed, 79 insertions(+), 4 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 3e46c63..e65caed 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -18,7 +18,9 @@ #ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB +#define CONFIG_CMD_HASH #define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_HW_ACCEL #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP @@ -47,8 +49,11 @@ #endif -#ifdef CONFIG_LS1043A -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit + * Similiarly for LS2080 and LS2085 + */ #define CONFIG_ESBC_ADDR_64BIT #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index aa256a2..ab101a4 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -248,7 +249,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c63b639..0c78a41 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080ardb_qixis.h" @@ -214,7 +215,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig new file mode 100644 index 000..5c50894 --- /dev/null +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig new file mode 100644 index 000..9456e04 --- /dev/null +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2085aqds_SECURE_BOOT_defconfig b/configs/ls2085aqds_SECURE_BOOT_defconfig new file mode 100644 index 000..8f96fc0 --- /dev/null +++ b/configs/ls2085aqds_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds
[U-Boot] [PATCH v3 03/15] SECURE BOOT: Add new ESBC header for ls-ch3 Secure Boot
For Secure Boot, a header is used to identify key table, signature
and image address. For LS-CH3, there is a new header structure being used.
The following changes are there in the new header:
1) Currently IE Table (Key extension) feature is not supported
2) Single Key feature is not supported. Keys must be in table format.
3) Hence, SRK (Key table) is by default currently always present.
4) Max Key number has increase from 4 to 8. 8th Key is unrevockable.
5) New Barker Code is being used.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +-
arch/arm/include/asm/fsl_secure_boot.h| 4 ++
board/freescale/common/fsl_validate.c | 35 +++--
include/fsl_secboot_err.h | 3 ++
include/fsl_validate.h| 60 ---
5 files changed, 91 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 16f60a1..d2ea525 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -79,7 +79,8 @@
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
-
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index 0da0599..3e46c63 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -40,9 +40,13 @@
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
*/
+#ifndef CONFIG_ESBC_HDR_LS
+/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
+#endif
+
#ifdef CONFIG_LS1043A
/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
#define CONFIG_ESBC_ADDR_64BIT
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 8fd6dd6..c12b9c9 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -35,7 +35,13 @@ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30,
0x0d, 0x06, 0x09, 0x60,
};
static u8 hash_val[SHA256_BYTES];
+
+#ifdef CONFIG_ESBC_HDR_LS
+/* New Barker Code for LS ESBC Header */
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
+#else
static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+#endif
void branch_to_self(void) __attribute__ ((noreturn));
@@ -157,10 +163,15 @@ static int get_ie_info_addr(u32 *ie_addr)
/* This function checks srk_table_flag in header and set/reset srk_flag.*/
static u32 check_srk(struct fsl_secboot_img_priv *img)
{
+#ifdef CONFIG_ESBC_HDR_LS
+ /* In LS, No SRK Flag as SRK is always present*/
+ return 1;
+#else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
return 1;
return 0;
+#endif
}
/* This function returns ospr's key_revoc values.*/
@@ -223,6 +234,7 @@ static u32 read_validate_srk_tbl(struct
fsl_secboot_img_priv *img)
}
#endif
+#ifndef CONFIG_ESBC_HDR_LS
static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
{
struct fsl_secboot_img_hdr *hdr = >hdr;
@@ -238,6 +250,7 @@ static u32 read_validate_single_key(struct
fsl_secboot_img_priv *img)
return 0;
}
+#endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
@@ -388,6 +401,7 @@ void fsl_secboot_handle_error(int error)
case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+ case ERROR_KEY_TABLE_NOT_FOUND:
#ifdef CONFIG_KEY_REVOCATION
case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
@@ -536,11 +550,18 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
if (!key_hash && check_ie(img))
key_hash = 1;
#endif
- if (!key_hash)
+#ifndef CONFIG_ESBC_HDR_LS
+/* No single key support in LS ESBC header */
+ if (!key_hash) {
ret = algo->hash_update(algo, ctx,
img->img_key, img->hdr.key_len, 0);
+ key_hash = 1;
+ }
+#endif
if (ret)
return ret;
+ if (!key_hash)
+ return ERROR_KEY_TABLE_NOT_FOUND;
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
@@ -626,8 +647,6 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *i
[U-Boot] [PATCH v3 06/15] SECURE BOOT: Copy Bootscript and header from NOR to DDR for LS2080/5
During Secure Boot, a bootscript is validated using its header. This patch copies both these images to DDR from NOR and then validates and executed them from DDR. (If NOR is the boot source for LS2080 and LS2085). This copy step is done to make this step common across booting sources. Because in case of non-xip memories (e.g. NAND, SD) it is neccessary to copy both these images to DDR. For other ARM Platforms (ls1043 and ls1020), header is not copied from NOR to DDR (otherwise customers will need to modify the existing headers). Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - for platform such as ls1043 and ls1021, boot header in NOR. Not copied to NOR. For them, fixed CONFIG_BOOTSCRIPT_HDR_ADDR to CONFIG_BS_HDR_ADDR_FLASH. Changes for v3: - No change arch/arm/include/asm/fsl_secure_boot.h | 28 +--- include/config_fsl_chain_trust.h | 11 +++ 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 7c55ea1..7ab9623 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -62,11 +62,33 @@ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -/* The address needs to be modified according to NOR memory map */ +/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from + * Non-XIP Memory (Nand/SD)*/ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif +/* The address needs to be modified according to NOR and DDR memory map */ #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#define CONFIG_BS_HDR_ADDR_FLASH 0x58392 +#define CONFIG_BS_ADDR_FLASH 0x58390 +#define CONFIG_BS_HDR_ADDR_RAM 0xa392 +#define CONFIG_BS_ADDR_RAM 0xa390 +#else +#define CONFIG_BS_HDR_ADDR_FLASH 0x600a +#define CONFIG_BS_ADDR_FLASH 0x6006 +#define CONFIG_BS_HDR_ADDR_RAM 0xa006 +#define CONFIG_BS_ADDR_RAM 0xa006 +#endif + +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#define CONFIG_BS_HDR_SIZE 0x2000 +#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM +#define CONFIG_BS_SIZE 0x1000 #else -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH +/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */ #endif #include diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 45dda56..aa222bb 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -65,8 +65,6 @@ "esbc_halt\0" #endif -/* For secure boot flow, default environment used will be used */ -#if defined(CONFIG_SYS_RAMBOOT) #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ @@ -76,14 +74,19 @@ "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" +/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ "nand read $bs_ram $bs_flash $bs_size ;" #endif /* CONFIG_RAMBOOT_NAND */ -#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ - +#else +#define CONFIG_BS_COPY_CMD \ + "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_flash $bs_ram $bs_size ;" #endif +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ #ifndef CONFIG_BS_COPY_ENV #define CONFIG_BS_COPY_ENV -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 07/15] SECURE BOOT: Change env variable "fdt_high" for LS2080a and LS2085a
"fdt_high" env variable has been changed to 0xa000 for ls2080a and ls2085a during Secure Boot. This env_varible is used to specify the upper limit to be used for copying flat device tree. This address must be visible to kernel. The "fdt_high" value has been set during Secure Boot to same value as it's default value during non-secure boot. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes arch/arm/include/asm/fsl_secure_boot.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 7ab9623..eafdc0b 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -57,10 +57,17 @@ #define CONFIG_ESBC_ADDR_64BIT #endif +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xa000;" \ + "setenv initrd_high 0xcfff;"\ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#else #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfff;" \ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#endif /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 12/15] SECURE_BOOT: Use default bootargs during Secure Boot
For secure boot, currently we were using fixed bootargs for all SoCs. This is not needed and we can use the bootargs which are used in non-secure boot. Incase bootargs are not defined for non-secure boot of any platform, we use default bootargs. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes include/config_fsl_chain_trust.h | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index aa222bb..566fd80 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -44,11 +44,18 @@ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" */ +#ifdef CONFIG_BOOTARGS +#define CONFIG_SET_BOOTARGS"setenv bootargs \'" CONFIG_BOOTARGS" \';" +#else +#define CONFIG_SET_BOOTARGS"setenv bootargs \'root=/dev/ram " \ + "rw console=ttyS0,115200 ramdisk_size=60\';" +#endif + + #ifdef CONFIG_BOOTSCRIPT_KEY_HASH #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr " \ __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ @@ -57,8 +64,7 @@ #else #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 10/15] crypto/fsl: Correct 64bit Write when MMU disabled
When MMU is disabled, 64bit Write must be at a memory aligned at 64bit Boundary. So, this commit splits the 64bit write into 2 -32bit writes as the memory location is not guaranteed to be 64bit aligned. The alignment exception only occurs when MMU is disabled. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changed for v3: - No changes drivers/crypto/fsl/desc_constr.h | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index 2559ccd..db6ddee 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -85,10 +85,9 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) #ifdef CONFIG_PHYS_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ - union ptr_addr_t ptr_addr; - ptr_addr.m_halfs.high = (u32)(ptr >> 32); - ptr_addr.m_halfs.low = (u32)ptr; - *offset = ptr_addr.m_whole; + union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset; + ptr_addr->m_halfs.high = (u32)(ptr >> 32); + ptr_addr->m_halfs.low = (u32)ptr; #else *offset = ptr; #endif -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 11/15] crypto/fsl: Make CAAM transactions cacheable
To solve CAAM coherency issue on ls2080a and ls2085a. When Caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/write data from/to Caches and CAAM does from Main Memory. This forces data flushes to synchronize various data structures But even if any data in proximity of these structures is read by core, these structures again are fetched in caches. To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable. So, this commit makes CAAM transcations as Write Back with Write and Read Allocate. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes drivers/crypto/fsl/jr.c | 13 + drivers/crypto/fsl/jr.h | 3 +++ 2 files changed, 16 insertions(+) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b8c0c0a..01d9967 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -539,7 +539,20 @@ int sec_init(void) uint32_t liodn_s; #endif + /* +* Modifying CAAM Read/Write Attributes +* For LS2080A and LS2085A +* For AXI Write - Cacheable, Write Back, Write allocate +* For AXI Read - Cacheable, Read allocate +* Only For LS2080a and LS2085a, to solve CAAM coherency issues +*/ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); + mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); +#else mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); +#endif + #ifdef CONFIG_PHYS_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 5899696..1f2e324 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -23,6 +23,9 @@ #define MCFGR_PS_SHIFT 16 #define MCFGR_AWCACHE_SHIFT8 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_ARCACHE_SHIFT12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) + #define JR_INTMASK 0x0001 #define JRCR_RESET 0x01 #define JRINT_ERR_HALT_INPROGRESS 0x4 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 08/15] armv8 : ls2080: Add config for endianess of CCSR GUR
The GUR (DCFG) registers in CCSR space are in LE format for ls2080/ls2085. Defined a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes Changes for v3: - No changes arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index d2ea525..08d9bcc 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -82,6 +82,9 @@ /* Secure Boot */ #define CONFIG_ESBC_HDR_LS +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + /* Cache Coherent Interconnect */ #define CCI_MN_BASE0x0400 #define CCI_MN_RNF_NODEID_LIST 0x180 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 09/15] armv8: fsl-lsch3: Disable SMMU during Secure Boot
During secure boot, SMMU is enabled on POR by SP bootrom.
SMMU needs to be put in Bypass mode in uboot to
enable CAAM transcations to pass through.
During Nonsecure Boot, SP BootROM doesn't enable SMMU and
at reset SMMU is in bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 +-
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d97a445..c52fd69 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -151,7 +151,14 @@ static void erratum_a009203(void)
#endif
#endif
}
-
+void bypass_smmu(void)
+{
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+}
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
@@ -160,6 +167,15 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ if (fsl_check_boot_mode_secure() == 1)
+ bypass_smmu();
+#endif
}
#ifdef CONFIG_SCSI_AHCI_PLAT
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1fc51e0..06d4856 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -83,6 +83,21 @@
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+/* MMU 500 */
+#define SMMU_SCR0 (SMMU_BASE + 0x0)
+#define SMMU_SCR1 (SMMU_BASE + 0x4)
+#define SMMU_SCR2 (SMMU_BASE + 0x8)
+#define SMMU_SACR (SMMU_BASE + 0x10)
+#define SMMU_IDR0 (SMMU_BASE + 0x20)
+#define SMMU_IDR1 (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0 (SMMU_BASE + 0x400)
+#define SMMU_NSCR2 (SMMU_BASE + 0x408)
+#define SMMU_NSACR (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK 0x0001
+#define SCR0_USFCFG_MASK 0x0400
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
--
1.8.1.4
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[U-Boot] [PATCH v2 06/15] SECURE BOOT: Copy Bootscript and header from NOR to DDR for LS2080/5
During Secure Boot, a bootscript is validated using its header. This patch copies both these images to DDR from NOR and then validates and executed them from DDR. (If NOR is the boot source for LS2080 and LS2085). This copy step is done to make this step common across booting sources. Because in case of non-xip memories (e.g. NAND, SD) it is neccessary to copy both these images to DDR. For other ARM Platforms (ls1043 and ls1020), header is not copied from NOR to DDR (otherwise customers will need to modify the existing headers). Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - for platform such as ls1043 and ls1021, boot header in NOR. Not copied to NOR. For them, fixed CONFIG_BOOTSCRIPT_HDR_ADDR to CONFIG_BS_HDR_ADDR_FLASH. arch/arm/include/asm/fsl_secure_boot.h | 28 +--- include/config_fsl_chain_trust.h | 11 +++ 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 7c55ea1..7ab9623 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -62,11 +62,33 @@ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -/* The address needs to be modified according to NOR memory map */ +/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from + * Non-XIP Memory (Nand/SD)*/ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif +/* The address needs to be modified according to NOR and DDR memory map */ #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#define CONFIG_BS_HDR_ADDR_FLASH 0x58392 +#define CONFIG_BS_ADDR_FLASH 0x58390 +#define CONFIG_BS_HDR_ADDR_RAM 0xa392 +#define CONFIG_BS_ADDR_RAM 0xa390 +#else +#define CONFIG_BS_HDR_ADDR_FLASH 0x600a +#define CONFIG_BS_ADDR_FLASH 0x6006 +#define CONFIG_BS_HDR_ADDR_RAM 0xa006 +#define CONFIG_BS_ADDR_RAM 0xa006 +#endif + +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#define CONFIG_BS_HDR_SIZE 0x2000 +#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM +#define CONFIG_BS_SIZE 0x1000 #else -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH +/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */ #endif #include diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 45dda56..aa222bb 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -65,8 +65,6 @@ "esbc_halt\0" #endif -/* For secure boot flow, default environment used will be used */ -#if defined(CONFIG_SYS_RAMBOOT) #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ @@ -76,14 +74,19 @@ "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" +/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ "nand read $bs_ram $bs_flash $bs_size ;" #endif /* CONFIG_RAMBOOT_NAND */ -#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ - +#else +#define CONFIG_BS_COPY_CMD \ + "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_flash $bs_ram $bs_size ;" #endif +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ #ifndef CONFIG_BS_COPY_ENV #define CONFIG_BS_COPY_ENV -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 07/15] SECURE BOOT: Change env variable "fdt_high" for LS2080a and LS2085a
"fdt_high" env variable has been changed to 0xa000 for ls2080a and ls2085a during Secure Boot. This env_varible is used to specify the upper limit to be used for copying flat device tree. This address must be visible to kernel. The "fdt_high" value has been set during Secure Boot to same value as it's default value during non-secure boot. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes arch/arm/include/asm/fsl_secure_boot.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 7ab9623..eafdc0b 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -57,10 +57,17 @@ #define CONFIG_ESBC_ADDR_64BIT #endif +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xa000;" \ + "setenv initrd_high 0xcfff;"\ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#else #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfff;" \ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#endif /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 10/15] crypto/fsl: Correct 64bit Write when MMU disabled
When MMU is disabled, 64bit Write must be at a memory aligned at 64bit Boundary. So, this commit splits the 64bit write into 2 -32bit writes as the memory location is not guaranteed to be 64bit aligned. The alignment exception only occurs when MMU is disabled. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes drivers/crypto/fsl/desc_constr.h | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index 2559ccd..db6ddee 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -85,10 +85,9 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) #ifdef CONFIG_PHYS_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ - union ptr_addr_t ptr_addr; - ptr_addr.m_halfs.high = (u32)(ptr >> 32); - ptr_addr.m_halfs.low = (u32)ptr; - *offset = ptr_addr.m_whole; + union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset; + ptr_addr->m_halfs.high = (u32)(ptr >> 32); + ptr_addr->m_halfs.low = (u32)ptr; #else *offset = ptr; #endif -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 13/15] SECURE BOOT: Halt execution when secure boot fail after reset request
In case of fatal failure during secure boot execution (e.g. header not found)
it is needed that the execution stops.
Earlier, we were asserting reset request in case in case of failure. But if
the RESET_REQ is not tied off to HRESET, this allows the execution to continue.
This can either be taken care in bootscript (Execute esbc_halt command in case
of
image verification process) or it can be taken care in Uboot Code.
Doing the latter via a esbc_halt.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
board/freescale/common/cmd_esbc_validate.c | 2 +-
board/freescale/common/fsl_validate.c | 5 +
include/fsl_validate.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index dfa3e21..375bc24 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -8,7 +8,7 @@
#include
#include
-static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (fsl_check_boot_mode_secure() == 0) {
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index c12b9c9..95059c7 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -325,6 +325,8 @@ static void fsl_secboot_header_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
}
/*
@@ -355,6 +357,9 @@ static void fsl_secboot_image_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
+
} else {
change_sec_mon_state(HPSR_SSM_ST_TRUST,
HPSR_SSM_ST_NON_SECURE);
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index f812c1a..ff6f6b7 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -242,6 +242,9 @@ struct fsl_secboot_img_priv {
uint32_t img_size; /* ESBC Image Size */
};
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
uintptr_t img_loc);
int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
--
1.8.1.4
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[U-Boot] [PATCH v2 08/15] armv8 : ls2080: Add config for endianess of CCSR GUR
The GUR (DCFG) registers in CCSR space are in LE format for ls2080/ls2085. Defined a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index d2ea525..08d9bcc 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -82,6 +82,9 @@ /* Secure Boot */ #define CONFIG_ESBC_HDR_LS +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + /* Cache Coherent Interconnect */ #define CCI_MN_BASE0x0400 #define CCI_MN_RNF_NODEID_LIST 0x180 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 11/15] crypto/fsl: Make CAAM transactions cacheable
To solve CAAM coherency issue on ls2080a and ls2085a. When Caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/write data from/to Caches and CAAM does from Main Memory. This forces data flushes to synchronize various data structures But even if any data in proximity of these structures is read by core, these structures again are fetched in caches. To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable. So, this commit makes CAAM transcations as Write Back with Write and Read Allocate. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes drivers/crypto/fsl/jr.c | 13 + drivers/crypto/fsl/jr.h | 3 +++ 2 files changed, 16 insertions(+) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b8c0c0a..01d9967 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -539,7 +539,20 @@ int sec_init(void) uint32_t liodn_s; #endif + /* +* Modifying CAAM Read/Write Attributes +* For LS2080A and LS2085A +* For AXI Write - Cacheable, Write Back, Write allocate +* For AXI Read - Cacheable, Read allocate +* Only For LS2080a and LS2085a, to solve CAAM coherency issues +*/ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); + mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); +#else mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); +#endif + #ifdef CONFIG_PHYS_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 5899696..1f2e324 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -23,6 +23,9 @@ #define MCFGR_PS_SHIFT 16 #define MCFGR_AWCACHE_SHIFT8 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_ARCACHE_SHIFT12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) + #define JR_INTMASK 0x0001 #define JRCR_RESET 0x01 #define JRINT_ERR_HALT_INPROGRESS 0x4 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 09/15] armv8: fsl-lsch3: Disable SMMU during Secure Boot
During secure boot, SMMU is enabled on POR by SP bootrom.
SMMU needs to be put in Bypass mode in uboot to
enable CAAM transcations to pass through.
During Nonsecure Boot, SP BootROM doesn't enable SMMU and
at reset SMMU is in bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 +-
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d97a445..c52fd69 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -151,7 +151,14 @@ static void erratum_a009203(void)
#endif
#endif
}
-
+void bypass_smmu(void)
+{
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+}
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
@@ -160,6 +167,15 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ if (fsl_check_boot_mode_secure() == 1)
+ bypass_smmu();
+#endif
}
#ifdef CONFIG_SCSI_AHCI_PLAT
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1fc51e0..06d4856 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -83,6 +83,21 @@
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+/* MMU 500 */
+#define SMMU_SCR0 (SMMU_BASE + 0x0)
+#define SMMU_SCR1 (SMMU_BASE + 0x4)
+#define SMMU_SCR2 (SMMU_BASE + 0x8)
+#define SMMU_SACR (SMMU_BASE + 0x10)
+#define SMMU_IDR0 (SMMU_BASE + 0x20)
+#define SMMU_IDR1 (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0 (SMMU_BASE + 0x400)
+#define SMMU_NSCR2 (SMMU_BASE + 0x408)
+#define SMMU_NSACR (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK 0x0001
+#define SCR0_USFCFG_MASK 0x0400
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
--
1.8.1.4
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[U-Boot] [PATCH v2 14/15] SECURE BOOT: Change fsl_secboot_validate function to output image addr
Currently, fsl_secboot_validate function used to set env variable "img_addr"
to contain address of image being validated.
The function has been changed to output image addr via argument
img_addr_ptr. The command esbc_validate sets the env variable
"img_addr".
This change helps when fsl_secboot_validate function is called from within
UBOOT (because now instead of calling function "getenv("img_addr")"
we can directly get the image address.)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- Not present in v1 patches.
board/freescale/common/cmd_esbc_validate.c | 12 +++-
board/freescale/common/fsl_validate.c | 26 +++---
include/fsl_validate.h | 4 ++--
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index 375bc24..cefe3cc 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -29,6 +29,8 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
char *hash_str = NULL;
uintptr_t haddr;
int ret;
+ uintptr_t img_addr = 0;
+ char buf[20];
if (argc < 2)
return cmd_usage(cmdtp);
@@ -43,7 +45,15 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
* part of header. So, the function is called
* by passing this argument as 0.
*/
- ret = fsl_secboot_validate(haddr, hash_str, 0);
+ ret = fsl_secboot_validate(haddr, hash_str, _addr);
+
+ /* Need to set "img_addr" even if validation failure.
+* Required when SB_EN in RCW set and non-fatal error
+* to continue U-Boot
+*/
+ sprintf(buf, "%lx", img_addr);
+ setenv("img_addr", buf);
+
if (ret)
return 1;
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 95059c7..64e4e30 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -570,7 +570,7 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
- (u8 *)img->img_addr, img->img_size, 1);
+ (u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
if (ret)
return ret;
@@ -646,7 +646,6 @@ static void construct_img_encoded_hash_second(struct
fsl_secboot_img_priv *img)
*/
static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
{
- char buf[20];
struct fsl_secboot_img_hdr *hdr = >hdr;
void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
u8 *k, *s;
@@ -661,17 +660,14 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
/* If Image Address is not passed as argument to function,
* then Address and Size must be read from the Header.
*/
- if (img->img_addr == 0) {
+ if (*(img->img_addr_ptr) == 0) {
#ifdef CONFIG_ESBC_ADDR_64BIT
- img->img_addr = hdr->pimg64;
+ *(img->img_addr_ptr) = hdr->pimg64;
#else
- img->img_addr = hdr->pimg;
+ *(img->img_addr_ptr) = hdr->pimg;
#endif
}
- sprintf(buf, "%lx", img->img_addr);
- setenv("img_addr", buf);
-
if (!hdr->img_size)
return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
@@ -814,9 +810,17 @@ static int calculate_cmp_img_sig(struct
fsl_secboot_img_priv *img)
return 0;
}
-
+/* haddr - Address of the header of image to be validated.
+ * arg_hash_str - Option hash string. If provided, this
+ * overides the key hash in the SFP fuses.
+ * img_addr_ptr - Optional pointer to address of image to be validated.
+ * If non zero addr, this overides the addr of image in header,
+ * otherwise updated to image addr in header.
+ * Acts as both input and output of function.
+ * This pointer shouldn't be NULL.
+ */
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
- uintptr_t img_addr)
+ uintptr_t *img_addr_ptr)
{
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
ulong hash[SHA256_BYTES/sizeof(ulong)];
@@ -869,7 +873,7 @@ int fsl_secboot_validate(uintptr_t haddr, char
*arg_hash_str,
/* Update the information in Private Struct */
hdr = >hdr;
img->ehdrloc = haddr;
- img->img_addr = img_addr;
+ img->img_addr_ptr = img_addr_ptr;
esbc = (u8 *)img->ehdrloc;
memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
diff --git a/includ
[U-Boot] [PATCH v2 01/15] armv8: ls2080: Add SFP Configs for LS2080/LS2085
In LS2080/LS2085, SFP is LE and Ver is 3.4
The base address is 0x01e80200
SFP will be used in Secure Boot to read fuses.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++
include/fsl_sfp.h | 3 ++-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 49b113d..5a33ff1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -67,6 +67,10 @@
/* SMMU Defintions */
#define SMMU_BASE 0x0500 /* GR0 Base */
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
#define CCI_MN_RNF_NODEID_LIST 0x180
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..f1b021f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -73,6 +73,9 @@
#define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR +
0x0220)
#define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR +
0x0221)
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
index 353a123..2976a2c 100644
--- a/include/fsl_sfp.h
+++ b/include/fsl_sfp.h
@@ -32,7 +32,8 @@
/* Number of SRKH registers */
#define NUM_SRKH_REGS 8
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+#ifdefined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
+ defined(CONFIG_SYS_FSL_SFP_VER_3_4)
struct ccsr_sfp_regs {
u32 ospr; /* 0x200 */
u32 ospr1; /* 0x204 */
--
1.8.1.4
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[U-Boot] [PATCH v2 00/15] Add Support for Secure Boot on LS208x
Secure Boot ESBC has been enabled on FSL LS208x platforms. This patchset is dependent on http://patchwork.ozlabs.org/patch/571612/ Changes for v2: - changed function fsl_secboot_validate to return address of image - corrected Bootscript header for ls1043 and ls1021 Saksham Jain (15): armv8: ls2080: Add SFP Configs for LS2080/LS2085 armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and RCW SECURE BOOT: Add new ESBC header for ls-ch3 Secure Boot SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb armv8: fsl-lsch3: Add bootscript header address for Secure Boot SECURE BOOT: Copy Bootscript and header from NOR to DDR for LS2080/5 SECURE BOOT: Change env variable "fdt_high" for LS2080a and LS2085a armv8 : ls2080: Add config for endianess of CCSR GUR armv8: fsl-lsch3: Disable SMMU during Secure Boot crypto/fsl: Correct 64bit Write when MMU disabled crypto/fsl: Make CAAM transactions cacheable SECURE_BOOT: Use default bootargs during Secure Boot SECURE BOOT: Halt execution when secure boot fail after reset request SECURE BOOT: Change fsl_secboot_validate function to output image addr SECURE_BOOT: Enable IE (Key extention) Feature in Ls2085a & LS2088a arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 ++- arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 +++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 28 arch/arm/include/asm/fsl_secure_boot.h | 50 ++- board/freescale/common/cmd_esbc_validate.c | 14 +- board/freescale/common/fsl_validate.c | 157 + board/freescale/ls2080aqds/ls2080aqds.c| 5 +- board/freescale/ls2080ardb/ls2080ardb.c| 5 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 15 ++ configs/ls2080ardb_SECURE_BOOT_defconfig | 15 ++ configs/ls2085aqds_SECURE_BOOT_defconfig | 15 ++ configs/ls2085ardb_SECURE_BOOT_defconfig | 15 ++ drivers/crypto/fsl/desc_constr.h | 7 +- drivers/crypto/fsl/jr.c| 13 ++ drivers/crypto/fsl/jr.h| 3 + include/config_fsl_chain_trust.h | 25 ++-- include/configs/ls2080aqds.h | 2 + include/configs/ls2080ardb.h | 2 + include/fsl_secboot_err.h | 3 + include/fsl_sfp.h | 3 +- include/fsl_validate.h | 88 ++-- 21 files changed, 438 insertions(+), 63 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 03/15] SECURE BOOT: Add new ESBC header for ls-ch3 Secure Boot
For Secure Boot, a header is used to identify key table, signature
and image address. For LS-CH3, there is a new header structure being used.
The following changes are there in the new header:
1) Currently IE Table (Key extension) feature is not supported
2) Single Key feature is not supported. Keys must be in table format.
3) Hence, SRK (Key table) is by default currently always present.
4) Max Key number has increase from 4 to 8. 8th Key is unrevockable.
5) New Barker Code is being used.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +-
arch/arm/include/asm/fsl_secure_boot.h| 4 ++
board/freescale/common/fsl_validate.c | 35 +++--
include/fsl_secboot_err.h | 3 ++
include/fsl_validate.h| 60 ---
5 files changed, 91 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 16f60a1..d2ea525 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -79,7 +79,8 @@
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
-
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index 0da0599..3e46c63 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -40,9 +40,13 @@
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
*/
+#ifndef CONFIG_ESBC_HDR_LS
+/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
+#endif
+
#ifdef CONFIG_LS1043A
/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
#define CONFIG_ESBC_ADDR_64BIT
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 8fd6dd6..c12b9c9 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -35,7 +35,13 @@ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30,
0x0d, 0x06, 0x09, 0x60,
};
static u8 hash_val[SHA256_BYTES];
+
+#ifdef CONFIG_ESBC_HDR_LS
+/* New Barker Code for LS ESBC Header */
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
+#else
static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+#endif
void branch_to_self(void) __attribute__ ((noreturn));
@@ -157,10 +163,15 @@ static int get_ie_info_addr(u32 *ie_addr)
/* This function checks srk_table_flag in header and set/reset srk_flag.*/
static u32 check_srk(struct fsl_secboot_img_priv *img)
{
+#ifdef CONFIG_ESBC_HDR_LS
+ /* In LS, No SRK Flag as SRK is always present*/
+ return 1;
+#else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
return 1;
return 0;
+#endif
}
/* This function returns ospr's key_revoc values.*/
@@ -223,6 +234,7 @@ static u32 read_validate_srk_tbl(struct
fsl_secboot_img_priv *img)
}
#endif
+#ifndef CONFIG_ESBC_HDR_LS
static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
{
struct fsl_secboot_img_hdr *hdr = >hdr;
@@ -238,6 +250,7 @@ static u32 read_validate_single_key(struct
fsl_secboot_img_priv *img)
return 0;
}
+#endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
@@ -388,6 +401,7 @@ void fsl_secboot_handle_error(int error)
case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+ case ERROR_KEY_TABLE_NOT_FOUND:
#ifdef CONFIG_KEY_REVOCATION
case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
@@ -536,11 +550,18 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
if (!key_hash && check_ie(img))
key_hash = 1;
#endif
- if (!key_hash)
+#ifndef CONFIG_ESBC_HDR_LS
+/* No single key support in LS ESBC header */
+ if (!key_hash) {
ret = algo->hash_update(algo, ctx,
img->img_key, img->hdr.key_len, 0);
+ key_hash = 1;
+ }
+#endif
if (ret)
return ret;
+ if (!key_hash)
+ return ERROR_KEY_TABLE_NOT_FOUND;
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
@@ -626,8 +647,6 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
u8 *k, *s;
u32 ret =
[U-Boot] [PATCH v2 02/15] armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and RCW
For ls2080, Added configs for various IPs used during secure boot
Added address and endianness for SEC and Security Monitor.
SRK - Fuses in SFP (Fused for public keys hash)
These are stored in LE format.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
arch/arm/include/asm/arch-fsl-layerscape/config.h | 10 ++
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5a33ff1..16f60a1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -70,6 +70,16 @@
/* SFP */
#define CONFIG_SYS_FSL_SFP_VER_3_4
#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index f1b021f..1fc51e0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -76,6 +76,14 @@
/* SFP */
#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 0x0700)
+#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 0x0701)
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
@@ -204,6 +212,8 @@ struct ccsr_gur {
#defineFSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF00
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
+#define RCW_SB_EN_REG_INDEX9
+#define RCW_SB_EN_MASK 0x0400
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
--
1.8.1.4
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[U-Boot] [PATCH v2 04/15] SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb
Following changes have been made to enable secure boot: 1) Sec_init has been called in starting to initialize SEC Block (CAAM) which will be used for Secure Boot validation later for both ls2080a qds and rdb 2) 64Bit address in ESBC Header has been enabled as this SoC is based on armv8 3) Secure Boot defconfigs created for boards (NOR Boot). Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes arch/arm/include/asm/fsl_secure_boot.h | 9 +++-- board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - configs/ls2080aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2080ardb_SECURE_BOOT_defconfig | 15 +++ configs/ls2085aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2085ardb_SECURE_BOOT_defconfig | 15 +++ include/configs/ls2080aqds.h | 2 ++ include/configs/ls2080ardb.h | 2 ++ 9 files changed, 79 insertions(+), 4 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 3e46c63..e65caed 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -18,7 +18,9 @@ #ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB +#define CONFIG_CMD_HASH #define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_HW_ACCEL #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP @@ -47,8 +49,11 @@ #endif -#ifdef CONFIG_LS1043A -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit + * Similiarly for LS2080 and LS2085 + */ #define CONFIG_ESBC_ADDR_64BIT #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index aa256a2..ab101a4 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -248,7 +249,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c63b639..0c78a41 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080ardb_qixis.h" @@ -214,7 +215,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig new file mode 100644 index 000..5c50894 --- /dev/null +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig new file mode 100644 index 000..9456e04 --- /dev/null +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2085aqds_SECURE_BOOT_defconfig b/configs/ls2085aqds_SECURE_BOOT_defconfig new file mode 100644 index 000..8f96fc0 --- /dev/null +++ b/configs/ls2085aqds_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR
[U-Boot] [PATCH v2 05/15] armv8: fsl-lsch3: Add bootscript header address for Secure Boot
During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it is executed. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080/5, NOR memory map is different from earlier arm SoCs. So a new address on NOR is used for this bootscript header. (0x58392). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes arch/arm/include/asm/fsl_secure_boot.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index e65caed..7c55ea1 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -63,7 +63,11 @@ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" /* The address needs to be modified according to NOR memory map */ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#else #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#endif #include #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 15/15] SECURE_BOOT: Enable IE (Key extention) Feature in Ls2085a & LS2088a
For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a veriied table of public keys
can be used. The latter feature is called IE Key Extension Feature.
For earlier SoCs, BootROM used to verify IE Key Table and then write the
address of this table in a secure register (SCRATCHREG). But in LS2088 and
LS2085, no such secure registers are available. Hence IE Table is left to be
verified by Uboot.
The new procedure is to first verify IE table using Keys stored in fuses,
and then use the keys in this table to verify further images. So the steps
are:
1) Verify IE Table (If "IE Table Flag" set in any image
i.e. Verify IE Table only when any image needs IE Table's Key to be verified)
2) Install IE table. (To be used across verification of multiple images.
Stored in a static global structure.)
3) If IE flag enabled in header of any image, Use keys from IE table,
otherwise use keys tied up with SoC's fuses (SRK).
The address of IE Table HDR is fixed for NOR. In case of boot from other
devices, IE Table and it's Header needs to be copied to an XIP Memory.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- shifted glb struct in fsl_validate.c to .bss section from heap
- freed struct fsl_secboot_img_priv in fsl_validate.c at end
- for ie_table, using img addr return by fsl_secboot_validate function
instead of using getenv("img_addr")
arch/arm/include/asm/fsl_secure_boot.h | 6 +--
board/freescale/common/fsl_validate.c | 95 --
include/fsl_validate.h | 23 +++-
3 files changed, 103 insertions(+), 21 deletions(-)
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index eafdc0b..061c9f5 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -41,11 +41,11 @@
* in boot ROM of the SoC.
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
+ * For LS, this feature is available for all device if IE Table
+ * is copied to XIP memory
+ * Also, for LS, ISBC doesn't verify this table.
*/
-#ifndef CONFIG_ESBC_HDR_LS
-/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
-#endif
#endif
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 64e4e30..d60a8a9 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -27,6 +27,8 @@
#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
((key_len) == 2 * KEY_SIZE_BYTES))
+/* Global data structure */
+static struct fsl_secboot_glb glb;
/* This array contains DER value for SHA-256 */
static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
@@ -60,7 +62,7 @@ self:
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 check_ie(struct fsl_secboot_img_priv *img)
{
- if (img->hdr.ie_flag)
+ if (img->hdr.ie_flag & IE_FLAG_MASK)
return 1;
return 0;
@@ -119,7 +121,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
}
#endif
-static int get_ie_info_addr(u32 *ie_addr)
+#if !defined(CONFIG_ESBC_HDR_LS)
+static int get_ie_info_addr(uintptr_t *ie_addr)
{
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
@@ -147,16 +150,17 @@ static int get_ie_info_addr(u32 *ie_addr)
/* IE Key Table is the first entry in the SG Table */
#if defined(CONFIG_MPC85xx)
- *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
- flash_base_addr;
+ *ie_addr = (uintptr_t)((sg_tbl->src_addr &
+ ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ flash_base_addr);
#else
- *ie_addr = sg_tbl->src_addr;
+ *ie_addr = (uintptr_t)sg_tbl->src_addr;
#endif
- debug("IE Table address is %x\n", *ie_addr);
+ debug("IE Table address is %lx\n", *ie_addr);
return 0;
}
-
+#endif /* CONFIG_ESBC_HDR_LS */
#endif
#ifdef CONFIG_KEY_REVOCATION
@@ -164,7 +168,10 @@ static int get_ie_info_addr(u32 *ie_addr)
static u32 check_srk(struct fsl_secboot_img_priv *img)
{
#ifdef CONFIG_ESBC_HDR_LS
- /* In LS, No SRK Flag as SRK is always present*/
+ /* In LS, No SRK Flag as SRK is always present if IE not present*/
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ return !check_ie(img);
+#endif
return 1;
#else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
@@ -253,14 +260,51 @@ static u32 read_validate_single_key(struct
fsl_secboot_img_priv *img)
#endif /* CONFIG_ESBC_HDR_LS *
[U-Boot] [PATCH v2 12/15] SECURE_BOOT: Use default bootargs during Secure Boot
For secure boot, currently we were using fixed bootargs for all SoCs. This is not needed and we can use the bootargs which are used in non-secure boot. Incase bootargs are not defined for non-secure boot of any platform, we use default bootargs. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- Changes for v2: - No changes include/config_fsl_chain_trust.h | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index aa222bb..566fd80 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -44,11 +44,18 @@ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" */ +#ifdef CONFIG_BOOTARGS +#define CONFIG_SET_BOOTARGS"setenv bootargs \'" CONFIG_BOOTARGS" \';" +#else +#define CONFIG_SET_BOOTARGS"setenv bootargs \'root=/dev/ram " \ + "rw console=ttyS0,115200 ramdisk_size=60\';" +#endif + + #ifdef CONFIG_BOOTSCRIPT_KEY_HASH #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr " \ __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ @@ -57,8 +64,7 @@ #else #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/14] SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb
Following changes have been made to enable secure boot: 1) Sec_init has been called in starting to initialize SEC Block (CAAM) which will be used for Secure Boot validation later for both ls2080a qds and rdb 2) 64Bit address in ESBC Header has been enabled as this SoC is based on armv8 3) Secure Boot defconfigs created for boards (NOR Boot). Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- arch/arm/include/asm/fsl_secure_boot.h | 9 +++-- board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - configs/ls2080aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2080ardb_SECURE_BOOT_defconfig | 15 +++ configs/ls2085aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2085ardb_SECURE_BOOT_defconfig | 15 +++ include/configs/ls2080aqds.h | 2 ++ include/configs/ls2080ardb.h | 2 ++ 9 files changed, 79 insertions(+), 4 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 3e46c63..e65caed 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -18,7 +18,9 @@ #ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB +#define CONFIG_CMD_HASH #define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_HW_ACCEL #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP @@ -47,8 +49,11 @@ #endif -#ifdef CONFIG_LS1043A -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit + * Similiarly for LS2080 and LS2085 + */ #define CONFIG_ESBC_ADDR_64BIT #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index aa256a2..ab101a4 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -248,7 +249,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c63b639..0c78a41 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls2080ardb_qixis.h" @@ -214,7 +215,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig new file mode 100644 index 000..5c50894 --- /dev/null +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig new file mode 100644 index 000..9456e04 --- /dev/null +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2085aqds_SECURE_BOOT_defconfig b/configs/ls2085aqds_SECURE_BOOT_defconfig new file mode 100644 index 000..8f96fc0 --- /dev/null +++ b/configs/ls2085aqds_SECURE_BOOT_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A, SECURE_BOOT" +# C
[U-Boot] [PATCH 10/14] crypto/fsl: Correct 64bit Write when MMU disabled
When MMU is disabled, 64bit Write must be at a memory aligned at 64bit Boundary. So, this commit splits the 64bit write into 2 -32bit writes as the memory location is not guaranteed to be 64bit aligned. The alignment exception only occurs when MMU is disabled. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- drivers/crypto/fsl/desc_constr.h | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index 2559ccd..db6ddee 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -85,10 +85,9 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) #ifdef CONFIG_PHYS_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ - union ptr_addr_t ptr_addr; - ptr_addr.m_halfs.high = (u32)(ptr >> 32); - ptr_addr.m_halfs.low = (u32)ptr; - *offset = ptr_addr.m_whole; + union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset; + ptr_addr->m_halfs.high = (u32)(ptr >> 32); + ptr_addr->m_halfs.low = (u32)ptr; #else *offset = ptr; #endif -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/14] SECURE BOOT: Add new ESBC header for ls-ch3 Secure Boot
For Secure Boot, a header is used to identify key table, signature
and image address. For LS-CH3, there is a new header structure being used.
The following changes are there in the new header:
1) Currently IE Table (Key extension) feature is not supported
2) Single Key feature is not supported. Keys must be in table format.
3) Hence, SRK (Key table) is by default currently always present.
4) Max Key number has increase from 4 to 8. 8th Key is unrevockable.
5) New Barker Code is being used.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +-
arch/arm/include/asm/fsl_secure_boot.h| 4 ++
board/freescale/common/fsl_validate.c | 35 +++--
include/fsl_secboot_err.h | 3 ++
include/fsl_validate.h| 60 ---
5 files changed, 91 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 16f60a1..d2ea525 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -79,7 +79,8 @@
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
-
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index 0da0599..3e46c63 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -40,9 +40,13 @@
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
*/
+#ifndef CONFIG_ESBC_HDR_LS
+/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
+#endif
+
#ifdef CONFIG_LS1043A
/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
#define CONFIG_ESBC_ADDR_64BIT
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 8fd6dd6..c12b9c9 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -35,7 +35,13 @@ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30,
0x0d, 0x06, 0x09, 0x60,
};
static u8 hash_val[SHA256_BYTES];
+
+#ifdef CONFIG_ESBC_HDR_LS
+/* New Barker Code for LS ESBC Header */
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
+#else
static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+#endif
void branch_to_self(void) __attribute__ ((noreturn));
@@ -157,10 +163,15 @@ static int get_ie_info_addr(u32 *ie_addr)
/* This function checks srk_table_flag in header and set/reset srk_flag.*/
static u32 check_srk(struct fsl_secboot_img_priv *img)
{
+#ifdef CONFIG_ESBC_HDR_LS
+ /* In LS, No SRK Flag as SRK is always present*/
+ return 1;
+#else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
return 1;
return 0;
+#endif
}
/* This function returns ospr's key_revoc values.*/
@@ -223,6 +234,7 @@ static u32 read_validate_srk_tbl(struct
fsl_secboot_img_priv *img)
}
#endif
+#ifndef CONFIG_ESBC_HDR_LS
static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
{
struct fsl_secboot_img_hdr *hdr = >hdr;
@@ -238,6 +250,7 @@ static u32 read_validate_single_key(struct
fsl_secboot_img_priv *img)
return 0;
}
+#endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
@@ -388,6 +401,7 @@ void fsl_secboot_handle_error(int error)
case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+ case ERROR_KEY_TABLE_NOT_FOUND:
#ifdef CONFIG_KEY_REVOCATION
case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
@@ -536,11 +550,18 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
if (!key_hash && check_ie(img))
key_hash = 1;
#endif
- if (!key_hash)
+#ifndef CONFIG_ESBC_HDR_LS
+/* No single key support in LS ESBC header */
+ if (!key_hash) {
ret = algo->hash_update(algo, ctx,
img->img_key, img->hdr.key_len, 0);
+ key_hash = 1;
+ }
+#endif
if (ret)
return ret;
+ if (!key_hash)
+ return ERROR_KEY_TABLE_NOT_FOUND;
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
@@ -626,8 +647,6 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
u8 *k, *s;
u32 ret = 0;
-#ifdef CONFIG_KEY_REV
[U-Boot] [PATCH 13/14] SECURE BOOT: Halt execution when secure boot fail after reset request
In case of fatal failure during secure boot execution (e.g. header not found)
it is needed that the execution stops.
Earlier, we were asserting reset request in case in case of failure. But if
the RESET_REQ is not tied off to HRESET, this allows the execution to continue.
This can either be taken care in bootscript (Execute esbc_halt command in case
of
image verification process) or it can be taken care in Uboot Code.
Doing the latter via a esbc_halt.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
board/freescale/common/cmd_esbc_validate.c | 2 +-
board/freescale/common/fsl_validate.c | 5 +
include/fsl_validate.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index dfa3e21..375bc24 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -8,7 +8,7 @@
#include
#include
-static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (fsl_check_boot_mode_secure() == 0) {
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index c12b9c9..95059c7 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -325,6 +325,8 @@ static void fsl_secboot_header_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
}
/*
@@ -355,6 +357,9 @@ static void fsl_secboot_image_verification_failure(void)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
+
} else {
change_sec_mon_state(HPSR_SSM_ST_TRUST,
HPSR_SSM_ST_NON_SECURE);
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index f812c1a..ff6f6b7 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -242,6 +242,9 @@ struct fsl_secboot_img_priv {
uint32_t img_size; /* ESBC Image Size */
};
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
uintptr_t img_loc);
int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
--
1.8.1.4
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[U-Boot] [PATCH 05/14] armv8: fsl-lsch3: Add bootscript header address for Secure Boot
During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it is executed. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080/5, NOR memory map is different from earlier arm SoCs. So a new address on NOR is used for this bootscript header. (0x58392). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- arch/arm/include/asm/fsl_secure_boot.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index e65caed..7c55ea1 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -63,7 +63,11 @@ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" /* The address needs to be modified according to NOR memory map */ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#else #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#endif #include #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/14] SECURE BOOT: Change env variable "fdt_high" for LS2080a and LS2085a
"fdt_high" env variable has been changed to 0xa000 for ls2080a and ls2085a during Secure Boot. This env_varible is used to specify the upper limit to be used for copying flat device tree. This address must be visible to kernel. The "fdt_high" value has been set during Secure Boot to same value as it's default value during non-secure boot. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- arch/arm/include/asm/fsl_secure_boot.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 4bd0517..2d61436 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -57,10 +57,17 @@ #define CONFIG_ESBC_ADDR_64BIT #endif +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xa000;" \ + "setenv initrd_high 0xcfff;"\ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#else #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfff;" \ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#endif /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/14] armv8: ls2080: Add SFP Configs for LS2080/LS2085
In LS2080/LS2085, SFP is LE and Ver is 3.4
The base address is 0x01e80200
SFP will be used in Secure Boot to read fuses.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++
include/fsl_sfp.h | 3 ++-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 49b113d..5a33ff1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -67,6 +67,10 @@
/* SMMU Defintions */
#define SMMU_BASE 0x0500 /* GR0 Base */
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
#define CCI_MN_RNF_NODEID_LIST 0x180
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..f1b021f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -73,6 +73,9 @@
#define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR +
0x0220)
#define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR +
0x0221)
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
index 353a123..2976a2c 100644
--- a/include/fsl_sfp.h
+++ b/include/fsl_sfp.h
@@ -32,7 +32,8 @@
/* Number of SRKH registers */
#define NUM_SRKH_REGS 8
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+#ifdefined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
+ defined(CONFIG_SYS_FSL_SFP_VER_3_4)
struct ccsr_sfp_regs {
u32 ospr; /* 0x200 */
u32 ospr1; /* 0x204 */
--
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[U-Boot] [PATCH 06/14] SECURE BOOT: Copy Bootscript and header from NOR to DDR for LS2080/5
During Secure Boot, a bootscript is validated using its header. This patch copies both these images to DDR from NOR and then validates and executed them from DDR. (If NOR is the boot source for LS2080 and LS2085). This copy step is done to make this step common across booting sources. Because in case of non-xip memories (e.g. NAND, SD) it is neccessary to copy both these images to DDR. For other ARM Platforms (ls1043 and ls1020), header is not copied from NOR to DDR (otherwise customers will need to modify the existing headers). Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- arch/arm/include/asm/fsl_secure_boot.h | 23 --- include/config_fsl_chain_trust.h | 11 +++ 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 7c55ea1..4bd0517 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -62,13 +62,30 @@ "setenv initrd_high 0xcfff;"\ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -/* The address needs to be modified according to NOR memory map */ +/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from + * Non-XIP Memory (Nand/SD)*/ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif +/* The address needs to be modified according to NOR and DDR memory map */ #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x58392 +#define CONFIG_BS_HDR_ADDR_FLASH 0x58392 +#define CONFIG_BS_ADDR_FLASH 0x58390 +#define CONFIG_BS_HDR_ADDR_RAM 0xa392 +#define CONFIG_BS_ADDR_RAM 0xa390 #else -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a +#define CONFIG_BS_HDR_ADDR_FLASH 0x600a +#define CONFIG_BS_ADDR_FLASH 0x6006 +#define CONFIG_BS_HDR_ADDR_RAM 0xa006 +#define CONFIG_BS_ADDR_RAM 0xa006 #endif +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#define CONFIG_BS_HDR_SIZE 0x2000 +#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM +#define CONFIG_BS_SIZE 0x1000 + #include #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 45dda56..aa222bb 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -65,8 +65,6 @@ "esbc_halt\0" #endif -/* For secure boot flow, default environment used will be used */ -#if defined(CONFIG_SYS_RAMBOOT) #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ @@ -76,14 +74,19 @@ "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" +/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ "nand read $bs_ram $bs_flash $bs_size ;" #endif /* CONFIG_RAMBOOT_NAND */ -#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ - +#else +#define CONFIG_BS_COPY_CMD \ + "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_flash $bs_ram $bs_size ;" #endif +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ #ifndef CONFIG_BS_COPY_ENV #define CONFIG_BS_COPY_ENV -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/14] armv8: fsl-lsch3: Disable SMMU during Secure Boot
During secure boot, SMMU is enabled on POR by SP bootrom.
SMMU needs to be put in Bypass mode in uboot to
enable CAAM transcations to pass through.
During Nonsecure Boot, SP BootROM doesn't enable SMMU and
at reset SMMU is in bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 +-
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d97a445..c52fd69 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -151,7 +151,14 @@ static void erratum_a009203(void)
#endif
#endif
}
-
+void bypass_smmu(void)
+{
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+}
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
@@ -160,6 +167,15 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ if (fsl_check_boot_mode_secure() == 1)
+ bypass_smmu();
+#endif
}
#ifdef CONFIG_SCSI_AHCI_PLAT
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1fc51e0..06d4856 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -83,6 +83,21 @@
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+/* MMU 500 */
+#define SMMU_SCR0 (SMMU_BASE + 0x0)
+#define SMMU_SCR1 (SMMU_BASE + 0x4)
+#define SMMU_SCR2 (SMMU_BASE + 0x8)
+#define SMMU_SACR (SMMU_BASE + 0x10)
+#define SMMU_IDR0 (SMMU_BASE + 0x20)
+#define SMMU_IDR1 (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0 (SMMU_BASE + 0x400)
+#define SMMU_NSCR2 (SMMU_BASE + 0x408)
+#define SMMU_NSACR (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK 0x0001
+#define SCR0_USFCFG_MASK 0x0400
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
--
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[U-Boot] [PATCH 14/14] SECURE_BOOT: Enable IE (Key extention) Feature in Ls2085a & LS2088a
For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a veriied table of public keys
can be used. The latter feature is called IE Key Extension Feature.
For earlier SoCs, BootROM used to verify IE Key Table and then write the
address of this table in a secure register (SCRATCHREG). But in LS2088 and
LS2085, no such secure registers are available. Hence IE Table is left to be
verified by Uboot.
The new procedure is to first verify IE table using Keys stored in fuses,
and then use the keys in this table to verify further images. So the steps
are:
1) Verify IE Table (If "IE Table Flag" set in any image
i.e. Verify IE Table only when any image needs IE Table's Key to be verified)
2) Install IE table. (To be used across verification of multiple images.
Stored in a static global structure.)
3) If IE flag enabled in header of any image, Use keys from IE table,
otherwise use keys tied up with SoC's fuses (SRK).
The address of IE Table HDR is fixed for NOR. In case of boot from other
devices, IE Table and it's Header needs to be copied to an XIP Memory.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
arch/arm/include/asm/fsl_secure_boot.h | 6 +-
board/freescale/common/fsl_validate.c | 111 -
include/fsl_validate.h | 23 ++-
3 files changed, 119 insertions(+), 21 deletions(-)
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index 2d61436..09605dd 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -41,11 +41,11 @@
* in boot ROM of the SoC.
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
+ * For LS, this feature is available for all device if IE Table
+ * is copied to XIP memory
+ * Also, for LS, ISBC doesn't verify this table.
*/
-#ifndef CONFIG_ESBC_HDR_LS
-/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
-#endif
#endif
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 95059c7..0620330 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -27,6 +27,8 @@
#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
((key_len) == 2 * KEY_SIZE_BYTES))
+/* Global data structure */
+static struct fsl_secboot_glb *glb;
/* This array contains DER value for SHA-256 */
static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
@@ -60,7 +62,7 @@ self:
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 check_ie(struct fsl_secboot_img_priv *img)
{
- if (img->hdr.ie_flag)
+ if (img->hdr.ie_flag & IE_FLAG_MASK)
return 1;
return 0;
@@ -119,7 +121,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
}
#endif
-static int get_ie_info_addr(u32 *ie_addr)
+#if !defined(CONFIG_ESBC_HDR_LS)
+static int get_ie_info_addr(uintptr_t *ie_addr)
{
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
@@ -147,16 +150,17 @@ static int get_ie_info_addr(u32 *ie_addr)
/* IE Key Table is the first entry in the SG Table */
#if defined(CONFIG_MPC85xx)
- *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
- flash_base_addr;
+ *ie_addr = (uintptr_t)((sg_tbl->src_addr &
+ ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ flash_base_addr);
#else
- *ie_addr = sg_tbl->src_addr;
+ *ie_addr = (uintptr_t)sg_tbl->src_addr;
#endif
- debug("IE Table address is %x\n", *ie_addr);
+ debug("IE Table address is %lx\n", *ie_addr);
return 0;
}
-
+#endif /* CONFIG_ESBC_HDR_LS */
#endif
#ifdef CONFIG_KEY_REVOCATION
@@ -164,7 +168,10 @@ static int get_ie_info_addr(u32 *ie_addr)
static u32 check_srk(struct fsl_secboot_img_priv *img)
{
#ifdef CONFIG_ESBC_HDR_LS
- /* In LS, No SRK Flag as SRK is always present*/
+ /* In LS, No SRK Flag as SRK is always present if IE not present*/
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ return !check_ie(img);
+#endif
return 1;
#else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
@@ -253,14 +260,61 @@ static u32 read_validate_single_key(struct
fsl_secboot_img_priv *img)
#endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+
+#if defined(CONFIG_ESBC_HDR_LS)
+static void install_ie_tbl(uintptr_t ie_tbl_addr,
+ struct fsl_secboot_img_priv *img)
+{
+ /* Copy IE tbl to Global Data */
+ memcpy(>ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info));
+
[U-Boot] [PATCH 11/14] crypto/fsl: Make CAAM transactions cacheable
To solve CAAM coherency issue on ls2080a and ls2085a. When Caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/write data from/to Caches and CAAM does from Main Memory. This forces data flushes to synchronize various data structures But even if any data in proximity of these structures is read by core, these structures again are fetched in caches. To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable. So, this commit makes CAAM transcations as Write Back with Write and Read Allocate. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- drivers/crypto/fsl/jr.c | 13 + drivers/crypto/fsl/jr.h | 3 +++ 2 files changed, 16 insertions(+) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b8c0c0a..01d9967 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -539,7 +539,20 @@ int sec_init(void) uint32_t liodn_s; #endif + /* +* Modifying CAAM Read/Write Attributes +* For LS2080A and LS2085A +* For AXI Write - Cacheable, Write Back, Write allocate +* For AXI Read - Cacheable, Read allocate +* Only For LS2080a and LS2085a, to solve CAAM coherency issues +*/ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); + mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); +#else mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); +#endif + #ifdef CONFIG_PHYS_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 5899696..1f2e324 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -23,6 +23,9 @@ #define MCFGR_PS_SHIFT 16 #define MCFGR_AWCACHE_SHIFT8 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_ARCACHE_SHIFT12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) + #define JR_INTMASK 0x0001 #define JRCR_RESET 0x01 #define JRINT_ERR_HALT_INPROGRESS 0x4 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 12/14] SECURE_BOOT: Use default bootargs during Secure Boot
For secure boot, currently we were using fixed bootargs for all SoCs. This is not needed and we can use the bootargs which are used in non-secure boot. Incase bootargs are not defined for non-secure boot of any platform, we use default bootargs. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- include/config_fsl_chain_trust.h | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index aa222bb..566fd80 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -44,11 +44,18 @@ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" */ +#ifdef CONFIG_BOOTARGS +#define CONFIG_SET_BOOTARGS"setenv bootargs \'" CONFIG_BOOTARGS" \';" +#else +#define CONFIG_SET_BOOTARGS"setenv bootargs \'root=/dev/ram " \ + "rw console=ttyS0,115200 ramdisk_size=60\';" +#endif + + #ifdef CONFIG_BOOTSCRIPT_KEY_HASH #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr " \ __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ @@ -57,8 +64,7 @@ #else #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=60\';"\ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV\ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/14] armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and RCW
For ls2080, Added configs for various IPs used during secure boot
Added address and endianness for SEC and Security Monitor.
SRK - Fuses in SFP (Fused for public keys hash)
These are stored in LE format.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 10 ++
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5a33ff1..16f60a1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -70,6 +70,16 @@
/* SFP */
#define CONFIG_SYS_FSL_SFP_VER_3_4
#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE0x0400
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index f1b021f..1fc51e0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -76,6 +76,14 @@
/* SFP */
#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200)
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 0x0700)
+#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 0x0701)
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0x00e9)
+
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
@@ -204,6 +212,8 @@ struct ccsr_gur {
#defineFSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF00
#defineFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
+#define RCW_SB_EN_REG_INDEX9
+#define RCW_SB_EN_MASK 0x0400
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
--
1.8.1.4
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[U-Boot] [PATCH 00/14] Add Support for Secure Boot on LS208x
Secure Boot ESBC has been enabled on FSL LS208x platforms. This patchset is dependent on http://patchwork.ozlabs.org/patch/571612/ Saksham Jain (14): armv8: ls2080: Add SFP Configs for LS2080/LS2085 armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and RCW SECURE BOOT: Add new ESBC header for ls-ch3 Secure Boot SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb armv8: fsl-lsch3: Add bootscript header address for Secure Boot SECURE BOOT: Copy Bootscript and header from NOR to DDR for LS2080/5 SECURE BOOT: Change env variable "fdt_high" for LS2080a and LS2085a armv8 : ls2080: Add config for endianess of CCSR GUR armv8: fsl-lsch3: Disable SMMU during Secure Boot crypto/fsl: Correct 64bit Write when MMU disabled crypto/fsl: Make CAAM transactions cacheable SECURE_BOOT: Use default bootargs during Secure Boot SECURE BOOT: Halt execution when secure boot fail after reset request SECURE_BOOT: Enable IE (Key extention) Feature in Ls2085a & LS2088a arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 ++- arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 +++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 28 arch/arm/include/asm/fsl_secure_boot.h | 45 ++- board/freescale/common/cmd_esbc_validate.c | 2 +- board/freescale/common/fsl_validate.c | 149 ++--- board/freescale/ls2080aqds/ls2080aqds.c| 5 +- board/freescale/ls2080ardb/ls2080ardb.c| 5 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2080ardb_SECURE_BOOT_defconfig | 15 +++ configs/ls2085aqds_SECURE_BOOT_defconfig | 15 +++ configs/ls2085ardb_SECURE_BOOT_defconfig | 15 +++ drivers/crypto/fsl/desc_constr.h | 7 +- drivers/crypto/fsl/jr.c| 13 ++ drivers/crypto/fsl/jr.h| 3 + include/config_fsl_chain_trust.h | 25 ++-- include/configs/ls2080aqds.h | 2 + include/configs/ls2080ardb.h | 2 + include/fsl_secboot_err.h | 3 + include/fsl_sfp.h | 3 +- include/fsl_validate.h | 84 ++-- 21 files changed, 422 insertions(+), 50 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/14] armv8 : ls2080: Add config for endianess of CCSR GUR
The GUR (DCFG) registers in CCSR space are in LE format for ls2080/ls2085. Defined a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> Signed-off-by: Saksham Jain <saksham.j...@nxp.com> --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index d2ea525..08d9bcc 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -82,6 +82,9 @@ /* Secure Boot */ #define CONFIG_ESBC_HDR_LS +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + /* Cache Coherent Interconnect */ #define CCI_MN_BASE0x0400 #define CCI_MN_RNF_NODEID_LIST 0x180 -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
