[PATCH,v2,1/2] spi: mtk_snor: add support for MTK SPI NOR controller
From: "SkyLake.Huang"
This patch adds support for MTK SPI NOR controller, which you
can see on mt7622 & mt7629.
1. This controller is designed only for SPI NOR. We can't adjust
its bus clock dynamically. Set clock in dts instead.
2. This controller only supports 1-1-1 write mode.
3. Remove mtk_snor_match_read() since upper SPI-MEM layer already
handles command.
4. sf read/write/update commands are tested with this driver.
Signed-off-by: SkyLake.Huang
---
drivers/spi/Kconfig| 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mtk_snor.c | 563 +
3 files changed, 571 insertions(+)
create mode 100644 drivers/spi/mtk_snor.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index cd19b2d4b3..7417335e6a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -218,6 +218,13 @@ config MT7621_SPI
the SPI NOR flash on platforms embedding this Ralink / MediaTek
SPI core, like MT7621/7628/7688.
+config MTK_SNOR
+ bool "Mediatek SPI-NOR controller driver"
+ depends on SPI_MEM
+ help
+ Enable the Mediatek SPINOR controller driver. This driver has
+ better read/write performance with NOR.
+
config MTK_SNFI_SPI
bool "Mediatek SPI memory controller driver"
depends on SPI_MEM
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index dc9ea34c0a..d8747c1299 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
+obj-$(CONFIG_MTK_SNOR) += mtk_snor.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c
new file mode 100644
index 00..04f588a75d
--- /dev/null
+++ b/drivers/spi/mtk_snor.c
@@ -0,0 +1,563 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Mediatek SPI-NOR controller driver
+//
+// Copyright (C) 2020 SkyLake Huang
+//
+// Some parts are based on drivers/spi/spi-mtk-nor.c of linux version
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DRIVER_NAME "mtk-spi-nor"
+
+#define MTK_NOR_REG_CMD 0x00
+#define MTK_NOR_CMD_WRSR BIT(5)
+#define MTK_NOR_CMD_WRITE BIT(4)
+#define MTK_NOR_CMD_PROGRAM BIT(2)
+#define MTK_NOR_CMD_RDSR BIT(1)
+#define MTK_NOR_CMD_READ BIT(0)
+#define MTK_NOR_CMD_MASK GENMASK(5, 0)
+
+#define MTK_NOR_REG_PRG_CNT 0x04
+#define MTK_NOR_REG_RDSR 0x08
+#define MTK_NOR_REG_RDATA 0x0c
+
+#define MTK_NOR_REG_RADR0 0x10
+#define MTK_NOR_REG_RADR(n) (MTK_NOR_REG_RADR0 + 4 * (n))
+#define MTK_NOR_REG_RADR3 0xc8
+
+#define MTK_NOR_REG_WDATA 0x1c
+
+#define MTK_NOR_REG_PRGDATA0 0x20
+#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n))
+#define MTK_NOR_REG_PRGDATA_MAX 5
+
+#define MTK_NOR_REG_SHIFT0 0x38
+#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n))
+#define MTK_NOR_REG_SHIFT_MAX 9
+
+#define MTK_NOR_REG_CFG1 0x60
+#define MTK_NOR_FAST_READ BIT(0)
+
+#define MTK_NOR_REG_CFG2 0x64
+#define MTK_NOR_WR_CUSTOM_OP_EN BIT(4)
+#define MTK_NOR_WR_BUF_EN BIT(0)
+
+#define MTK_NOR_REG_PP_DATA 0x98
+
+#define MTK_NOR_REG_IRQ_STAT 0xa8
+#define MTK_NOR_REG_IRQ_EN 0xac
+#define MTK_NOR_IRQ_DMA BIT(7)
+#define MTK_NOR_IRQ_WRSR BIT(5)
+#define MTK_NOR_IRQ_MASK GENMASK(7, 0)
+
+#define MTK_NOR_REG_CFG3 0xb4
+#define MTK_NOR_DISABLE_WREN BIT(7)
+#define MTK_NOR_DISABLE_SR_POLL BIT(5)
+
+#define MTK_NOR_REG_WP 0xc4
+#define MTK_NOR_ENABLE_SF_CMD 0x30
+
+#define MTK_NOR_REG_BUSCFG 0xcc
+#define MTK_NOR_4B_ADDR BIT(4)
+#define MTK_NOR_QUAD_ADDR BIT(3)
+#define MTK_NOR_QUAD_READ BIT(2)
+#define MTK_NOR_DUAL_ADDR BIT(1)
+#define MTK_NOR_DUAL_READ BIT(0)
+#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0)
+
+#define MTK_NOR_REG_DMA_CTL 0x718
+#define MTK_NOR_DMA_START BIT(0)
+
+#define MTK_NOR_REG_DMA_FADR 0x71c
+#define MTK_NOR_REG_DMA_DADR 0x720
+#define MTK_NOR_REG_DMA_END_DADR 0x724
+
+#define MTK_NOR_PRG_MAX_SIZE 6
+// Reading DMA src/dst addresses have to be 16-byte aligned
+#define MTK_NOR_DMA_ALIGN 16
+#define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
+// and we allocate a bounce buffer if destination address isn't aligned.
+#define MTK_NOR_BOUNCE_BUF_SIZE PAGE_SIZE
+
+// Buffered page program can do one 128-byte transfer
+#define MTK_NOR_PP_SIZE 128
+
+#define CLK_TO_US(priv, clkcnt) DIV_ROUND_UP(clkcnt, (priv)->spi_freq /
100)
+
+#define MTK_NOR_UNLOCK_ALL 0x0
+
+struct mtk_snor_priv {
+ struct device *dev;
+ void __iomem *base;
+ u8 *buffer;
+ struct clk spi_clk;
+ struct clk ctlr_clk;
+ unsigned int spi_freq;
+ bool wbuf_en;
+};
+
+static inline void mtk_snor_r
[PATCH 0/2] *** Add support for Mediatek mt762x SoC ***
From: "SkyLake.Huang" This patch adds support MTK's SPI NOR controller on mt7622 & mt7629. With this controller, you can access SPI NOR with better performance on mt762x platform. SkyLake.Huang (2): spi: mtk_snor: add support for MTK SPI NOR controller arm: dts: enable MTK SPI NOR controller driver arch/arm/dts/mt7622-rfb.dts | 16 +- arch/arm/dts/mt7622.dtsi | 11 + arch/arm/dts/mt7629-rfb.dts | 16 +- arch/arm/dts/mt7629.dtsi | 11 + configs/mt7622_rfb_defconfig | 3 +- configs/mt7629_rfb_defconfig | 3 +- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mtk_snor.c | 563 +++ 9 files changed, 627 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/mtk_snor.c -- 2.18.0
[PATCH,v2,2/2] arm: dts: enable MTK SPI NOR controller driver
From: "SkyLake.Huang"
1. Enable MTK SPI NOR controller driver on mt7622 & mt7629.
2. Enable quad mode for read and single mode for write.
Signed-off-by: SkyLake.Huang
---
arch/arm/dts/mt7622-rfb.dts | 16 +++-
arch/arm/dts/mt7622.dtsi | 11 +++
arch/arm/dts/mt7629-rfb.dts | 16 +++-
arch/arm/dts/mt7629.dtsi | 11 +++
configs/mt7622_rfb_defconfig | 3 ++-
configs/mt7629_rfb_defconfig | 3 ++-
6 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index ef7d0f0270..c2f1ad2011 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -19,7 +19,7 @@
};
aliases {
- spi0 =
+ spi0 =
};
memory@4000 {
@@ -165,11 +165,25 @@
pinctrl-names = "default", "snfi";
pinctrl-0 = <_pins>;
pinctrl-1 = <_pins>;
+ status = "disabled";
+
+ spi-flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
status = "okay";
spi-flash@0{
compatible = "jedec,spi-nor";
reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index 5c2e0251de..0127474c95 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -53,6 +53,17 @@
#size-cells = <0>;
};
+ snor: snor@11014000 {
+ compatible = "mediatek,mtk-snor";
+ reg = <0x11014000 0x1000>;
+ clocks = < CLK_PERI_FLASH_PD>,
+< CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <>;
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index 5cc7294de6..df43cc49c5 100644
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -14,7 +14,7 @@
compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
aliases {
- spi0 =
+ spi0 =
};
chosen {
@@ -69,11 +69,25 @@
pinctrl-names = "default", "snfi";
pinctrl-0 = <_pins>;
pinctrl-1 = <_pins>;
+ status = "disabled";
+
+ spi-flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
status = "okay";
spi-flash@0{
compatible = "jedec,spi-nor";
reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index 6850e0058d..05394266e0 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -223,6 +223,17 @@
#size-cells = <0>;
};
+ snor: snor@11014000 {
+ compatible = "mediatek,mtk-snor";
+ reg = <0x11014000 0x1000>;
+ clocks = < CLK_PERI_FLASH_PD>,
+< CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ssusbsys: ssusbsys@1a00 {
compatible = "mediatek,mt7629-ssusbsys", "syscon";
reg = <0x1a00 0x1000>;
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
index ccf926e104..347f5f6b12 100644
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -49,7 +49,8 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_MTK_SNFI_SPI=y
+# CONFIG_MTK_SNFI_SPI is not set
+CONFIG_MTK_SNOR=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_TIMER=y
CONFIG_MTK_TIMER=y
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index d9032d4493..3691223510 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -75,7 +75,8 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_MTK_SNFI_SPI=y
+# CONFIG_MTK_SNFI_SPI is not set
+CONFIG_MTK_SNOR=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
--
2.18.0
Re: [PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller
On Tue, 2020-12-08 at 01:48 +0800, Jagan Teki wrote: > On Fri, Nov 13, 2020 at 8:32 AM SkyLake Huang > wrote: > > > > From: "SkyLake.Huang" > > > > This patch adds support for MTK SPI NOR controller, which you > > can see on mt7622 & mt7629. > > > > This controller is designed only for SPI NOR. We can't adjust > > its bus clock dynamically. Set clock in dts instead. > > > > Signed-off-by: SkyLake.Huang > > --- > > drivers/spi/Kconfig| 7 + > > drivers/spi/Makefile | 1 + > > drivers/spi/mtk_snor.c | 597 + > > 3 files changed, 605 insertions(+) > > create mode 100644 drivers/spi/mtk_snor.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > > index fae2040af8..670af450c1 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -174,6 +174,13 @@ config MT7621_SPI > > the SPI NOR flash on platforms embedding this Ralink / MediaTek > > SPI core, like MT7621/7628/7688. > > > > +config MTK_SNOR > > + bool "Mediatek SPI-NOR controller driver" > > + depends on SPI_MEM > > + help > > + Enable the Mediatek SPINOR controller driver. This driver has > > + better read/write performance with NOR. > > + > > config MTK_SNFI_SPI > > bool "Mediatek SPI memory controller driver" > > depends on SPI_MEM > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > > index ae4f2958f8..efe92f6b18 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -38,6 +38,7 @@ obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o > > obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o > > obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o > > obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o > > +obj-$(CONFIG_MTK_SNOR) += mtk_snor.o > > obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o > > obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o > > obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o > > diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c > > new file mode 100644 > > index 00..0a92f1c5a8 > > --- /dev/null > > +++ b/drivers/spi/mtk_snor.c > > @@ -0,0 +1,597 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Mediatek SPI-NOR controller driver > > +// > > +// Copyright (C) 2020 SkyLake Huang > > +// > > +// Some parts are based on drivers/spi/spi-mtk-nor.c of linux version > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define DRIVER_NAME "mtk-spi-nor" > > + > > +#define MTK_NOR_REG_CMD0x00 > > +#define MTK_NOR_CMD_WRSR BIT(5) > > +#define MTK_NOR_CMD_WRITE BIT(4) > > +#define MTK_NOR_CMD_PROGRAMBIT(2) > > +#define MTK_NOR_CMD_RDSR BIT(1) > > +#define MTK_NOR_CMD_READ BIT(0) > > +#define MTK_NOR_CMD_MASK GENMASK(5, 0) > > + > > +#define MTK_NOR_REG_PRG_CNT0x04 > > +#define MTK_NOR_REG_RDSR 0x08 > > +#define MTK_NOR_REG_RDATA 0x0c > > + > > +#define MTK_NOR_REG_RADR0 0x10 > > +#define MTK_NOR_REG_RADR(n)(MTK_NOR_REG_RADR0 + 4 * (n)) > > +#define MTK_NOR_REG_RADR3 0xc8 > > + > > +#define MTK_NOR_REG_WDATA 0x1c > > + > > +#define MTK_NOR_REG_PRGDATA0 0x20 > > +#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n)) > > +#define MTK_NOR_REG_PRGDATA_MAX5 > > + > > +#define MTK_NOR_REG_SHIFT0 0x38 > > +#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n)) > > +#define MTK_NOR_REG_SHIFT_MAX 9 > > + > > +#define MTK_NOR_REG_CFG1 0x60 > > +#define MTK_NOR_FAST_READ BIT(0) > > + > > +#define MTK_NOR_REG_CFG2 0x64 > > +#define MTK_NOR_WR_CUSTOM_OP_ENBIT(4) > > +#define MTK_NOR_WR_BUF_EN BIT(0) > > + > > +#define MTK_NOR_REG_PP_DATA0x98 > > + > > +#define MTK_NOR_REG_IRQ_STAT 0xa8 > > +#define MTK_NOR_REG_IRQ_EN 0xac > > +#define MTK_NOR_IRQ_
Re: [PATCH 0/2] *** Add support for Mediatek mt762x SoC ***
HiJagan, On Fri, 2020-11-13 at 11:02 +0800, SkyLake Huang wrote: > From: "SkyLake.Huang" > > This patch adds support MTK's SPI NOR controller on > mt7622 & mt7629. With this controller, you can access > SPI NOR with better performance on mt762x platform. > > SkyLake.Huang (2): > spi: mtk_snor: add support for MTK SPI NOR controller > arm: dts: enable MTK SPI NOR controller driver > > arch/arm/dts/mt7622-rfb.dts | 14 +- > arch/arm/dts/mt7622.dtsi | 7 + > arch/arm/dts/mt7629-rfb.dts | 14 +- > arch/arm/dts/mt7629.dtsi | 9 + > configs/mt7622_rfb_defconfig | 3 +- > configs/mt7629_rfb_defconfig | 3 +- > drivers/spi/Kconfig | 7 + > drivers/spi/Makefile | 1 + > drivers/spi/mtk_snor.c | 597 +++ > 9 files changed, 651 insertions(+), 4 deletions(-) > create mode 100644 drivers/spi/mtk_snor.c > A gentle ping.
[PATCH 2/2] arm: dts: enable MTK SPI NOR controller driver
From: "SkyLake.Huang"
Enable MTK SPI NOR controller driver on mt7622 & mt7629.
Signed-off-by: SkyLake.Huang
---
arch/arm/dts/mt7622-rfb.dts | 14 +-
arch/arm/dts/mt7622.dtsi | 7 +++
arch/arm/dts/mt7629-rfb.dts | 14 +-
arch/arm/dts/mt7629.dtsi | 9 +
configs/mt7622_rfb_defconfig | 3 ++-
configs/mt7629_rfb_defconfig | 3 ++-
6 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index 52b34fa3b3..9322c54a3c 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -19,7 +19,7 @@
};
aliases {
- spi0 =
+ spi0 =
};
memory@4000 {
@@ -151,6 +151,18 @@
quad-spi;
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+
+ spi-flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index e511432da9..53d24ac63d 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -68,7 +68,14 @@
assigned-clock-parents = < CLK_TOP_SYSPLL1_D2>,
< CLK_TOP_UNIVPLL2_D8>;
+ };
+ snor: snor@11014000 {
+ compatible = "mediatek,mtk-snor";
+ reg = <0x11014000 0x1000>;
+ clocks = < CLK_PERI_FLASH_PD>,
+< CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
status = "disabled";
};
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index 687fe1c029..c75c4c7a38 100644
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -14,7 +14,7 @@
compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
aliases {
- spi0 =
+ spi0 =
};
chosen {
@@ -76,6 +76,18 @@
};
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+
+ spi-flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index a33a74a556..b268db7498 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -222,6 +222,15 @@
#size-cells = <0>;
};
+ snor: snor@11014000 {
+ compatible = "mediatek,mtk-snor";
+ reg = <0x11014000 0x1000>;
+ clocks = < CLK_PERI_FLASH_PD>,
+< CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ status = "disabled";
+ };
+
ethsys: syscon@1b00 {
compatible = "mediatek,mt7629-ethsys", "syscon";
reg = <0x1b00 0x1000>;
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
index ae5fda52d7..4747470f08 100644
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -54,7 +54,8 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_MTK_SNFI_SPI=y
+# CONFIG_MTK_SNFI_SPI is not set
+CONFIG_MTK_SNOR=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_TIMER=y
CONFIG_MTK_TIMER=y
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index 9b94c2038e..b5a5059998 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -65,7 +65,8 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_MTK_SNFI_SPI=y
+# CONFIG_MTK_SNFI_SPI is not set
+CONFIG_MTK_SNOR=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
--
2.18.0
[PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller
From: "SkyLake.Huang" This patch adds support for MTK SPI NOR controller, which you can see on mt7622 & mt7629. This controller is designed only for SPI NOR. We can't adjust its bus clock dynamically. Set clock in dts instead. Signed-off-by: SkyLake.Huang --- drivers/spi/Kconfig| 7 + drivers/spi/Makefile | 1 + drivers/spi/mtk_snor.c | 597 + 3 files changed, 605 insertions(+) create mode 100644 drivers/spi/mtk_snor.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fae2040af8..670af450c1 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -174,6 +174,13 @@ config MT7621_SPI the SPI NOR flash on platforms embedding this Ralink / MediaTek SPI core, like MT7621/7628/7688. +config MTK_SNOR + bool "Mediatek SPI-NOR controller driver" + depends on SPI_MEM + help + Enable the Mediatek SPINOR controller driver. This driver has + better read/write performance with NOR. + config MTK_SNFI_SPI bool "Mediatek SPI memory controller driver" depends on SPI_MEM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ae4f2958f8..efe92f6b18 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o +obj-$(CONFIG_MTK_SNOR) += mtk_snor.o obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c new file mode 100644 index 00..0a92f1c5a8 --- /dev/null +++ b/drivers/spi/mtk_snor.c @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Mediatek SPI-NOR controller driver +// +// Copyright (C) 2020 SkyLake Huang +// +// Some parts are based on drivers/spi/spi-mtk-nor.c of linux version + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "mtk-spi-nor" + +#define MTK_NOR_REG_CMD0x00 +#define MTK_NOR_CMD_WRSR BIT(5) +#define MTK_NOR_CMD_WRITE BIT(4) +#define MTK_NOR_CMD_PROGRAMBIT(2) +#define MTK_NOR_CMD_RDSR BIT(1) +#define MTK_NOR_CMD_READ BIT(0) +#define MTK_NOR_CMD_MASK GENMASK(5, 0) + +#define MTK_NOR_REG_PRG_CNT0x04 +#define MTK_NOR_REG_RDSR 0x08 +#define MTK_NOR_REG_RDATA 0x0c + +#define MTK_NOR_REG_RADR0 0x10 +#define MTK_NOR_REG_RADR(n)(MTK_NOR_REG_RADR0 + 4 * (n)) +#define MTK_NOR_REG_RADR3 0xc8 + +#define MTK_NOR_REG_WDATA 0x1c + +#define MTK_NOR_REG_PRGDATA0 0x20 +#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n)) +#define MTK_NOR_REG_PRGDATA_MAX5 + +#define MTK_NOR_REG_SHIFT0 0x38 +#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n)) +#define MTK_NOR_REG_SHIFT_MAX 9 + +#define MTK_NOR_REG_CFG1 0x60 +#define MTK_NOR_FAST_READ BIT(0) + +#define MTK_NOR_REG_CFG2 0x64 +#define MTK_NOR_WR_CUSTOM_OP_ENBIT(4) +#define MTK_NOR_WR_BUF_EN BIT(0) + +#define MTK_NOR_REG_PP_DATA0x98 + +#define MTK_NOR_REG_IRQ_STAT 0xa8 +#define MTK_NOR_REG_IRQ_EN 0xac +#define MTK_NOR_IRQ_DMABIT(7) +#define MTK_NOR_IRQ_WRSR BIT(5) +#define MTK_NOR_IRQ_MASK GENMASK(7, 0) + +#define MTK_NOR_REG_CFG3 0xb4 +#define MTK_NOR_DISABLE_WREN BIT(7) +#define MTK_NOR_DISABLE_SR_POLLBIT(5) + +#define MTK_NOR_REG_WP 0xc4 +#define MTK_NOR_ENABLE_SF_CMD 0x30 + +#define MTK_NOR_REG_BUSCFG 0xcc +#define MTK_NOR_4B_ADDRBIT(4) +#define MTK_NOR_QUAD_ADDR BIT(3) +#define MTK_NOR_QUAD_READ BIT(2) +#define MTK_NOR_DUAL_ADDR BIT(1) +#define MTK_NOR_DUAL_READ BIT(0) +#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0) + +#define MTK_NOR_REG_DMA_CTL0x718 +#define MTK_NOR_DMA_START BIT(0) + +#define MTK_NOR_REG_DMA_FADR 0x71c +#define MTK_NOR_REG_DMA_DADR 0x720 +#define MTK_NOR_REG_DMA_END_DADR 0x724 + +#define MTK_NOR_PRG_MAX_SIZE 6 +// Reading DMA src/dst addresses have to be 16-byte aligned +#define MTK_NOR_DMA_ALIGN 16 +#define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1) +// and we allocate a bounce buffer if destination address isn't aligned. +#define MTK_NOR_BOUNCE_BUF_SIZEPAGE_SIZE + +
[PATCH 0/2] *** Add support for Mediatek mt762x SoC ***
From: "SkyLake.Huang" This patch adds support MTK's SPI NOR controller on mt7622 & mt7629. With this controller, you can access SPI NOR with better performance on mt762x platform. SkyLake.Huang (2): spi: mtk_snor: add support for MTK SPI NOR controller arm: dts: enable MTK SPI NOR controller driver arch/arm/dts/mt7622-rfb.dts | 14 +- arch/arm/dts/mt7622.dtsi | 7 + arch/arm/dts/mt7629-rfb.dts | 14 +- arch/arm/dts/mt7629.dtsi | 9 + configs/mt7622_rfb_defconfig | 3 +- configs/mt7629_rfb_defconfig | 3 +- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mtk_snor.c | 597 +++ 9 files changed, 651 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/mtk_snor.c -- 2.18.0
