Re: [PATCH] arm: exynos: Migrate E850-96 board to OF_UPSTREAM
+ Krzysztof, Fyi..
On Fri, 24 May 2024 at 03:33, Sam Protsenko wrote:
>
> Use upstream device tree files and bindings. To do so:
> - imply (enable) OF_UPSTREAM option for E850-96 target
> - point DEFAULT_DEVICE_TREE in E850-96 config to upstream dts
> - remove now not needed local dts files, binding docs and headers
> - update MAINTAINERS correspondingly
>
> Upstream device tree files for Exynos850 SoC and E850-96 board are
> pretty much the same as local (removed) ones, so the conversion is
> rather straightforward and painless in this case. The appended dts file
> (arch/arm/dts/exynos850-e850-96-u-boot.dtsi) stays unchanged.
>
> The only remaining local dt-bindings doc for E850-96 board is
> exynos-pmu.yaml. It wasn't removed as it's quite different from Linux
> kernel version. Particularly U-Boot local version of exynos-pmu.yaml
> describes "samsung,uart-debug-1" property, which is not present in Linux
> kernel binding. Later it might be upstreamed to Linux kernel, and once
> it's done the U-Boot exynos-pmu.yaml binding can be removed.
>
> No functional change.
>
> Signed-off-by: Sam Protsenko
> ---
> MAINTAINERS | 7 +-
> arch/arm/dts/Makefile | 1 -
> arch/arm/dts/exynos850-e850-96.dts| 273 --
> arch/arm/dts/exynos850-pinctrl.dtsi | 663 --
> arch/arm/dts/exynos850.dtsi | 809 --
> arch/arm/mach-exynos/Kconfig | 1 +
> configs/e850-96_defconfig | 2 +-
> .../clock/samsung,exynos850-clock.yaml| 307 ---
> .../soc/samsung/exynos-usi.yaml | 162
> include/dt-bindings/clock/exynos850.h | 337
> include/dt-bindings/soc/samsung,exynos-usi.h | 17 -
> 11 files changed, 3 insertions(+), 2576 deletions(-)
> delete mode 100644 arch/arm/dts/exynos850-e850-96.dts
> delete mode 100644 arch/arm/dts/exynos850-pinctrl.dtsi
> delete mode 100644 arch/arm/dts/exynos850.dtsi
> delete mode 100644
> doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
> delete mode 100644 doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
> delete mode 100644 include/dt-bindings/clock/exynos850.h
> delete mode 100644 include/dt-bindings/soc/samsung,exynos-usi.h
>
Acked-by: Sumit Garg
-Sumit
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 638b2fdd442f..f8afd7d51e2e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -578,19 +578,14 @@ F:drivers/clk/exynos/clk.h
> ARM SAMSUNG EXYNOS850 SOC
> M: Sam Protsenko
> S: Maintained
> -F: arch/arm/dts/exynos850-pinctrl.dtsi
> -F: arch/arm/dts/exynos850.dtsi
> -F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
> F: drivers/clk/exynos/clk-exynos850.c
> F: drivers/pinctrl/exynos/pinctrl-exynos850.c
> -F: include/dt-bindings/clock/exynos850.h
>
> ARM SAMSUNG SOC DRIVERS
> M: Sam Protsenko
> S: Maintained
> -F: doc/device-tree-bindings/soc/samsung/*
> +F: doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
> F: drivers/soc/samsung/*
> -F: include/dt-bindings/soc/samsung,*.h
>
> ARM SANCLOUD
> M: Paul Barker
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index a5c82ebf7a5f..4b72d9f64863 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -31,7 +31,6 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
> dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
> dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
> dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
> -dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb
>
> dtb-$(CONFIG_ARCH_APPLE) += \
> t8103-j274.dtb \
> diff --git a/arch/arm/dts/exynos850-e850-96.dts
> b/arch/arm/dts/exynos850-e850-96.dts
> deleted file mode 100644
> index f074df8982b3..
> --- a/arch/arm/dts/exynos850-e850-96.dts
> +++ /dev/null
> @@ -1,273 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * WinLink E850-96 board device tree source
> - *
> - * Copyright (C) 2018 Samsung Electronics Co., Ltd.
> - * Copyright (C) 2021 Linaro Ltd.
> - *
> - * Device tree source file for WinLink's E850-96 board which is based on
> - * Samsung Exynos850 SoC.
> - */
> -
> -/dts-v1/;
> -
> -#include "exynos850.dtsi"
> -#include
> -#include
> -#include
> -
> -/ {
> - model = "WinLink E850-96 board";
> - compatible = "winlink,e850-96", "samsung,exynos850";
> -
> - aliases {
> - mmc0 = _0;
> - serial0 = _0;
> -
Re: [PATCH v2 2/5] dt-bindings: clock: qcom: ipq4019: drop downstream file
On Thu, 23 May 2024 at 23:08, Robert Marko wrote: > > IPQ4019 clock dt-bindings are available in Linux upstream, and we can just > use those instead of carrying a downstream file that matches the upstream one > anyway. > > Signed-off-by: Robert Marko > --- > Changes in v2: > * Drop the downstream dt-bindings header as it matches the upstream Linux one > > include/dt-bindings/clock/qcom,gcc-ipq4019.h | 169 --- > 1 file changed, 169 deletions(-) > delete mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h > Reviewed-by: Sumit Garg -Sumit > diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h > b/include/dt-bindings/clock/qcom,gcc-ipq4019.h > deleted file mode 100644 > index 7e8a7be6dc..00 > --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h > +++ /dev/null > @@ -1,169 +0,0 @@ > -/* Copyright (c) 2015 The Linux Foundation. All rights reserved. > - * > - * Permission to use, copy, modify, and/or distribute this software for any > - * purpose with or without fee is hereby granted, provided that the above > - * copyright notice and this permission notice appear in all copies. > - * > - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES > - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF > - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR > - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES > - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN > - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF > - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. > - * > - */ > -#ifndef __QCOM_CLK_IPQ4019_H__ > -#define __QCOM_CLK_IPQ4019_H__ > - > -#define GCC_DUMMY_CLK 0 > -#define AUDIO_CLK_SRC 1 > -#define BLSP1_QUP1_I2C_APPS_CLK_SRC2 > -#define BLSP1_QUP1_SPI_APPS_CLK_SRC3 > -#define BLSP1_QUP2_I2C_APPS_CLK_SRC4 > -#define BLSP1_QUP2_SPI_APPS_CLK_SRC5 > -#define BLSP1_UART1_APPS_CLK_SRC 6 > -#define BLSP1_UART2_APPS_CLK_SRC 7 > -#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 > -#define GCC_APPS_CLK_SRC 9 > -#define GCC_APPS_AHB_CLK_SRC 10 > -#define GP1_CLK_SRC11 > -#define GP2_CLK_SRC12 > -#define GP3_CLK_SRC13 > -#define SDCC1_APPS_CLK_SRC 14 > -#define FEPHY_125M_DLY_CLK_SRC 15 > -#define WCSS2G_CLK_SRC 16 > -#define WCSS5G_CLK_SRC 17 > -#define GCC_APSS_AHB_CLK 18 > -#define GCC_AUDIO_AHB_CLK 19 > -#define GCC_AUDIO_PWM_CLK 20 > -#define GCC_BLSP1_AHB_CLK 21 > -#define GCC_BLSP1_QUP1_I2C_APPS_CLK22 > -#define GCC_BLSP1_QUP1_SPI_APPS_CLK23 > -#define GCC_BLSP1_QUP2_I2C_APPS_CLK24 > -#define GCC_BLSP1_QUP2_SPI_APPS_CLK25 > -#define GCC_BLSP1_UART1_APPS_CLK 26 > -#define GCC_BLSP1_UART2_APPS_CLK 27 > -#define GCC_DCD_XO_CLK 28 > -#define GCC_GP1_CLK29 > -#define GCC_GP2_CLK30 > -#define GCC_GP3_CLK31 > -#define GCC_BOOT_ROM_AHB_CLK 32 > -#define GCC_CRYPTO_AHB_CLK 33 > -#define GCC_CRYPTO_AXI_CLK 34 > -#define GCC_CRYPTO_CLK 35 > -#define GCC_ESS_CLK36 > -#define GCC_IMEM_AXI_CLK 37 > -#define GCC_IMEM_CFG_AHB_CLK 38 > -#define GCC_PCIE_AHB_CLK 39 > -#define GCC_PCIE_AXI_M_CLK 40 > -#define GCC_PCIE_AXI_S_CLK 41 > -#define GCC_PCNOC_AHB_CLK 42 > -#define GCC_PRNG_AHB_CLK 43 > -#define GCC_QPIC_AHB_CLK 44 > -#define GCC_QPIC_CLK 45 > -#define GCC_SDCC1_AHB_CLK 46 > -#define GCC_SDCC1_APPS_CLK 47 > -#define GCC_SNOC_PCNOC_AHB_CLK
Re: [PATCH v2] arm: dts: k3-j7200: Move to OF_UPSTREAM
On Tue, 21 May 2024 at 11:18, Aniket Limaye wrote:
>
> Move to using OF_UPSTREAM config and thus using the devicetree-rebasing
> subtree.
>
> Signed-off-by: Aniket Limaye
> ---
>
> Boot logs:
> https://gist.github.com/aniket-l/aab91bb12d2495c54da094fca49c369f
>
> Changes in v2:
> - Rebased to next
> - Removed dependency on binman templating series [1] as per [2]
>
> [1]: https://lore.kernel.org/all/20240322131011.1029620-1-n-fran...@ti.com/
> [2]: https://lore.kernel.org/u-boot/20240520095916.1809962-1-n-fran...@ti.com/
>
> ---
> arch/arm/dts/Makefile |1 -
> arch/arm/dts/k3-j7200-binman.dtsi |2 +-
> .../k3-j7200-common-proc-board-u-boot.dtsi| 14 +-
> arch/arm/dts/k3-j7200-common-proc-board.dts | 396 -
> arch/arm/dts/k3-j7200-main.dtsi | 1284 -
> arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 647 -
> arch/arm/dts/k3-j7200-som-p0.dtsi | 327 -
> arch/arm/dts/k3-j7200-thermal.dtsi| 47 -
> arch/arm/dts/k3-j7200.dtsi| 164 ---
> configs/j7200_evm_a72_defconfig |3 +-
> 10 files changed, 8 insertions(+), 2877 deletions(-)
> delete mode 100644 arch/arm/dts/k3-j7200-common-proc-board.dts
> delete mode 100644 arch/arm/dts/k3-j7200-main.dtsi
> delete mode 100644 arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
> delete mode 100644 arch/arm/dts/k3-j7200-som-p0.dtsi
> delete mode 100644 arch/arm/dts/k3-j7200-thermal.dtsi
> delete mode 100644 arch/arm/dts/k3-j7200.dtsi
>
Acked-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index f7032f1e175..ea8fee8e25c 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1194,7 +1194,6 @@ dtb-$(CONFIG_SOC_K3_AM654) += \
>
> dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
> k3-j721e-r5-common-proc-board.dtb \
> - k3-j7200-common-proc-board.dtb \
> k3-j7200-r5-common-proc-board.dtb \
> k3-j721e-sk.dtb \
> k3-j721e-r5-sk.dtb \
> diff --git a/arch/arm/dts/k3-j7200-binman.dtsi
> b/arch/arm/dts/k3-j7200-binman.dtsi
> index 06db8659876..b6e0aa37971 100644
> --- a/arch/arm/dts/k3-j7200-binman.dtsi
> +++ b/arch/arm/dts/k3-j7200-binman.dtsi
> @@ -180,7 +180,7 @@
>
> #ifdef CONFIG_TARGET_J7200_A72_EVM
>
> -#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb"
> +#define SPL_J7200_EVM_DTB "spl/dts/ti/k3-j7200-common-proc-board.dtb"
> #define J7200_EVM_DTB "u-boot.dtb"
>
> {
> diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
> b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
> index 485f17c5f06..045ef170e17 100644
> --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
> +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
> @@ -26,8 +26,12 @@
> _mcu_wakeup {
> bootph-all;
>
> - chipid@4314 {
> + wkup_conf: bus@4300 {
> bootph-all;
> +
> + chipid: chipid@14 {
> + bootph-all;
> + };
> };
> };
>
> @@ -40,14 +44,6 @@
> };
>
> _udmap {
> - reg = <0x0 0x285c 0x0 0x100>,
> - <0x0 0x284c 0x0 0x4000>,
> - <0x0 0x2a80 0x0 0x4>,
> - <0x0 0x284a 0x0 0x4000>,
> - <0x0 0x2aa0 0x0 0x4>,
> - <0x0 0x2840 0x0 0x2000>;
> - reg-names = "gcfg", "rchan", "rchanrt", "tchan",
> - "tchanrt", "rflow";
> bootph-all;
> };
>
> diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
> b/arch/arm/dts/k3-j7200-common-proc-board.dts
> deleted file mode 100644
> index cee2b4b0eb8..000
> --- a/arch/arm/dts/k3-j7200-common-proc-board.dts
> +++ /dev/null
> @@ -1,396 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> - */
> -
> -/dts-v1/;
> -
> -#include "k3-j7200-som-p0.dtsi"
> -#include
> -#include
> -#include
> -
> -#include "k3-serdes.h"
> -
> -/ {
> - compatible = "ti,j7200-evm", "ti,j7200";
> - model = "Texas Instruments J7200 EVM";
> -
> - aliases {
> - serial0 = _uart0;
> - serial1 = _uart0;
> - serial2 = _uart0;
> -
Re: [PATCH v2] board: rockchip: add ArmSoM Sige7 Rk3588 board
On Wed, 22 May 2024 at 23:33, Quentin Schulz wrote: > > Hi Jianfeng Liu, > > On 5/22/24 6:58 PM, Jianfeng Liu wrote: > [...] > > Note that these commits: > > - e18e5e8188f2 (arm64: dts: rockchip: add USBDP phys on rk3588) > > - 6fca4edb93d3 (arm64: dts: rockchip: Add rk3588 GPU node) > > are not synced to u-boot, so I remove usb3 drd nodes and gpu from kernel > > devicetree. > [...]> diff --git > a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts > b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts > > new file mode 100644 > > index 00..c7b46536ec > > --- /dev/null > > +++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts > > Sorry, I failed to explain properly what was expected. > > dts/upstream should never be touched except with > dts/update-dts-subtree.sh script. > > Sadly, your board is not supported in v6.9 yet, only in the upcoming > v6.10 :/ > > So we have two options, we keep the dts in arch/arm/dts/ like you used > to do, until we merge v6.10 dts in U-Boot (probably for v2024.10?), or > we cherry-pick the changes for your board with dts/update-dts-subtree.sh > script, see the instructions in the docs Tom has started writing: > https://lore.kernel.org/u-boot/20240517174930.1028063-2-tr...@konsulko.com/. > I would very much like to see someone starting to look into the second > option :) > > However... it seems we'll likely need to also cherry-pick patches for > the GPU (should probably be straightforward as nothing would be using > the GPU anyway in U-Boot) and the USBDP PHY... but this one we would > need to update all -u-boot.dtsi for rk3588(s) boards that have it > already to make it use the new label/DT, make sure that the driver still > works... etc. Maybe not a small feat, but someone will have to do it at > some point anyway :) > > You'd be the first one to do this cherry-picking into dts/upstream, so > it'd be really interesting to us if you could provide feedback on what > is unclear/not working, etc... so we can update the documentation or fix > tools if they were to be insufficient. +1 Although it is very much similar to normal cherry-picking patches, the dts/update-dts-subtree.sh script is just there to hide the git subtree specific details. -Sumit > > Looking forward to your next patch, > Cheers, > Quentin
Re: [PATCH] arm: dts: mvebu: Migrate to upstream DT for Synology DS116 (Armada 385) board
On Thu, 23 May 2024 at 03:22, Tony Dinh wrote:
>
> Enable OF_UPSTREAM to use upstream DT and add marvell/ prefix to the
> DEFAULT_DEVICE_TREE in DS116 defconfig. Remove current DTS in
> arch/arm/dts/ directory.
>
> Signed-off-by: Tony Dinh
> ---
>
> arch/arm/dts/Makefile | 1 -
> arch/arm/dts/armada-385-synology-ds116.dts | 291 -
> configs/ds116_defconfig| 3 +-
> 3 files changed, 2 insertions(+), 293 deletions(-)
> delete mode 100644 arch/arm/dts/armada-385-synology-ds116.dts
>
Acked-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index a5c82ebf7a..75f7e616b4 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -155,7 +155,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
> armada-385-atl-x530.dtb \
> armada-385-atl-x530DP.dtb \
> armada-385-db-88f6820-amc.dtb \
> - armada-385-synology-ds116.dtb \
> armada-385-thecus-n2350.dtb \
> armada-385-turris-omnia.dtb \
> armada-388-clearfog.dtb \
> diff --git a/arch/arm/dts/armada-385-synology-ds116.dts
> b/arch/arm/dts/armada-385-synology-ds116.dts
> deleted file mode 100644
> index 82a0373f7f..00
> --- a/arch/arm/dts/armada-385-synology-ds116.dts
> +++ /dev/null
> @@ -1,291 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> -/*
> - * Device Tree file for Synology DS116 NAS
> - *
> - * Copyright (C) 2017 Willy Tarreau
> - */
> -
> -/dts-v1/;
> -#include "armada-385.dtsi"
> -#include
> -
> -/ {
> - model = "Synology DS116";
> - compatible = "marvell,a385-gp", "marvell,armada385",
> "marvell,armada380";
> -
> - chosen {
> - stdout-path = "serial0:115200n8";
> - };
> -
> - memory {
> - device_type = "memory";
> - reg = <0x 0x4000>; /* 1 GB */
> - };
> -
> - soc {
> - ranges = - MBUS_ID(0x01, 0x1d) 0 0xfff0 0x10
> - MBUS_ID(0x09, 0x19) 0 0xf110 0x1
> - MBUS_ID(0x09, 0x15) 0 0xf111 0x1
> - MBUS_ID(0x0c, 0x04) 0 0xf120 0x10>;
> -
> - internal-regs {
> - i2c@11000 {
> - pinctrl-names = "default";
> - pinctrl-0 = <_pins>;
> - status = "okay";
> - clock-frequency = <10>;
> -
> - eeprom@57 {
> - compatible = "atmel,24c64";
> - reg = <0x57>;
> - };
> - };
> -
> - serial@12000 {
> - pinctrl-names = "default";
> - pinctrl-0 = <_pins>;
> - status = "okay";
> - };
> -
> - serial@12100 {
> - /* A PIC16F1829 is connected to uart1 at 9600
> bps,
> -* and takes single-character orders :
> -* "1" : power off // already handled by
> the poweroff node
> -* "2" : short beep
> -* "3" : long beep
> -* "4" : turn the power LED ON
> -* "5" : flash the power LED
> -* "6" : turn the power LED OFF
> -* "7" : turn the status LED OFF
> -* "8" : turn the status LED ON
> -* "9" : flash the status LED
> -* "A" : flash the motherboard LED (D8)
> -* "B" : turn the motherboard LED OFF
> -* "C" : hard reset
> -*/
> - pinctrl-names = "default";
> - pinctrl-0 = <_pins>;
> - status = "okay";
> - };
Re: [PATCH FOR TESTING ONLY RFC 4/4] sunxi-d1s-t113: Add D1 and T113 PWM node
On Sat, 18 May 2024 at 09:25, John Watts wrote:
>
> This is based on the binding from the as yet unmerged kernel series:
>
> https://lore.kernel.org/linux-kernel/20240131125920.2879433-2-privates...@gmail.com/
>
> Signed-off-by: John Watts
> ---
> arch/riscv/dts/sunxi-d1s-t113.dtsi | 12
> dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi | 12
> 2 files changed, 24 insertions(+)
>
> diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi
> b/arch/riscv/dts/sunxi-d1s-t113.dtsi
> index 822f022eec..92b6432f77 100644
> --- a/arch/riscv/dts/sunxi-d1s-t113.dtsi
> +++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi
> @@ -145,6 +145,18 @@
> };
> };
>
> + pwm: pwm@2000c00 {
> + compatible = "allwinner,sun20i-d1-pwm";
> + reg = <0x02000c00 0x400>;
> + clocks = < CLK_BUS_PWM>,
> +<>,
> +< CLK_APB0>;
> + clock-names = "bus", "hosc", "apb0";
> + resets = < RST_BUS_PWM>;
> + status = "disabled";
> + #pwm-cells = <0x3>;
> + };
> +
> ccu: clock-controller@2001000 {
> compatible = "allwinner,sun20i-d1-ccu";
> reg = <0x2001000 0x1000>;
> diff --git a/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
> b/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
> index 5a9d7f5a75..435a1e66aa 100644
> --- a/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
> +++ b/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
> @@ -145,6 +145,18 @@
> };
> };
>
> + pwm: pwm@2000c00 {
> + compatible = "allwinner,sun20i-d1-pwm";
> + reg = <0x02000c00 0x400>;
> + clocks = < CLK_BUS_PWM>,
> +<>,
> +< CLK_APB0>;
> + clock-names = "bus", "hosc", "apb0";
> + resets = < RST_BUS_PWM>;
> + status = "disabled";
> + #pwm-cells = <0x3>;
> + };
> +
This change shouldn't be needed for your testing purposes too. It only
comes into picture once you enable OF_UPSTREAM. BTW, DT source files
in dts/upstream are strictly following/syncing against Linux kernel DT
sources. So all the custom U-Boot specific DT stuff belongs to
arch/${ARCH}/dts/.
-Sumit
> ccu: clock-controller@2001000 {
> compatible = "allwinner,sun20i-d1-ccu";
> reg = <0x2001000 0x1000>;
>
> --
> 2.45.1
>
Re: [RESEND PATCH 4/4] omap3: igep0x00: Migrate to use upstream DT
On Sat, 18 May 2024 at 18:36, Javier Martinez Canillas
wrote:
>
> From: Javier Martinez Canillas
>
> Enable OF_UPSTREAM to use upstream DT and add a ti/omap/ prefix to the
> DEFAULT_DEVICE_TREE config option.
>
> That way, a DTS from the upstream dts/upstream/src/ directory is used
> instead of the arch/$(ARCH)/dts/ directory. These in turn are removed.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> arch/arm/dts/Makefile | 3 -
> arch/arm/dts/omap3-igep.dtsi| 247 --
> arch/arm/dts/omap3-igep0020-common.dtsi | 261
> arch/arm/dts/omap3-igep0020.dts | 47 -
> configs/igep00x0_defconfig | 3 +-
> 5 files changed, 2 insertions(+), 559 deletions(-)
> delete mode 100644 arch/arm/dts/omap3-igep.dtsi
> delete mode 100644 arch/arm/dts/omap3-igep0020-common.dtsi
> delete mode 100644 arch/arm/dts/omap3-igep0020.dts
>
Acked-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index a5c82ebf7a5f..a9bd4921718e 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1030,9 +1030,6 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
>
> dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
>
> -dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
> - omap3-igep0020.dtb
> -
> dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
> omap4-panda.dtb \
> omap4-panda-es.dtb
> diff --git a/arch/arm/dts/omap3-igep.dtsi b/arch/arm/dts/omap3-igep.dtsi
> deleted file mode 100644
> index 219202610463..
> --- a/arch/arm/dts/omap3-igep.dtsi
> +++ /dev/null
> @@ -1,247 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Common device tree for IGEP boards based on AM/DM37x
> - *
> - * Copyright (C) 2012 Javier Martinez Canillas
> - * Copyright (C) 2012 Enric Balletbo i Serra
> - */
> -/dts-v1/;
> -
> -#include "omap36xx.dtsi"
> -
> -/ {
> - memory@8000 {
> - device_type = "memory";
> - reg = <0x8000 0x2000>; /* 512 MB */
> - };
> -
> - chosen {
> - stdout-path =
> - };
> -
> - sound {
> - compatible = "ti,omap-twl4030";
> - ti,model = "igep2";
> - ti,mcbsp = <>;
> - };
> -
> - vdd33: regulator-vdd33 {
> - compatible = "regulator-fixed";
> - regulator-name = "vdd33";
> - regulator-always-on;
> - };
> -
> -};
> -
> -_pmx_core {
> - gpmc_pins: pinmux_gpmc_pins {
> - pinctrl-single,pins = <
> - /* OneNAND seems to require PIN_INPUT on clock. */
> -OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)
>/* gpmc_clk.gpmc_clk */
> - >;
> - };
> -
> - uart1_pins: pinmux_uart1_pins {
> - pinctrl-single,pins = <
> - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)
> /* uart1_rx.uart1_rx */
> - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0)
> /* uart1_tx.uart1_tx */
> - >;
> - };
> -
> - uart3_pins: pinmux_uart3_pins {
> - pinctrl-single,pins = <
> - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)
> /* uart3_rx.uart3_rx */
> - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)
> /* uart3_tx.uart3_tx */
> - >;
> - };
> -
> - mcbsp2_pins: pinmux_mcbsp2_pins {
> - pinctrl-single,pins = <
> - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)
> /* mcbsp2_fsx.mcbsp2_fsx */
> - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)
> /* mcbsp2_clkx.mcbsp2_clkx */
> - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)
> /* mcbsp2_dr.mcbsp2.dr */
> - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)
> /* mcbsp2_dx.mcbsp2_dx */
> - >;
> - };
> -
> - mmc1_pins: pinmux_mmc1_pins {
> - pinctrl-single,pins = <
> - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP |
> MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
> - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP |
> MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
> - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP |
> MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
> - OMAP3
Re: [PATCH 08/10] dts/upsteam: Add Makefile for xtensa
On Mon, 20 May 2024 at 02:24, Jiaxun Yang wrote: > > It is required to get it xtensa OF_UPSTREAM work. > > Signed-off-by: Jiaxun Yang > --- > dts/upstream/src/xtensa/Makefile | 14 ++ > 1 file changed, 14 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/dts/upstream/src/xtensa/Makefile > b/dts/upstream/src/xtensa/Makefile > new file mode 100644 > index ..2a81acb32bc3 > --- /dev/null > +++ b/dts/upstream/src/xtensa/Makefile > @@ -0,0 +1,14 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +include $(srctree)/scripts/Makefile.dts > + > +targets += $(dtb-y) > + > +# Add any required device tree compiler flags here > +DTC_FLAGS += -a 0x8 > + > +PHONY += dtbs > +dtbs: $(addprefix $(obj)/, $(dtb-y)) > + @: > + > +clean-files := *.dtb *.dtbo */*.dtb */*.dtbo > > -- > 2.43.0 >
Re: [PATCH] ARM: dts: renesas: Reserve space in 64bit R-Car DTs
On Mon, 20 May 2024 at 02:11, Marek Vasut wrote: > > Reserve 4 kiB of space in 64bit R-Car DTs when those DTs are compiled > to permit patching in OpTee-OS /firmware node, /reserved-memory node, > possibly also additional /memory@ nodes and RPC node by TFA. > > This duplicates behavior in arch/arm/dts/Makefile with OF_UPSTREAM. > > Signed-off-by: Marek Vasut > --- > Cc: Sumit Garg > Cc: Tom Rini > --- > dts/upstream/src/arm64/Makefile | 4 > 1 file changed, 4 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/dts/upstream/src/arm64/Makefile b/dts/upstream/src/arm64/Makefile > index 9a8f6aa3584..26a83d3d29d 100644 > --- a/dts/upstream/src/arm64/Makefile > +++ b/dts/upstream/src/arm64/Makefile > @@ -7,6 +7,10 @@ targets += $(dtb-y) > # Add any required device tree compiler flags here > DTC_FLAGS += -a 0x8 > > +ifdef CONFIG_RCAR_64 > +DTC_FLAGS += -R 4 -p 0x1000 > +endif > + > PHONY += dtbs > dtbs: $(addprefix $(obj)/, $(dtb-y)) > @: > -- > 2.43.0 >
Re: [PATCH v3 11/12] MIPS: boston: Migrate to OF_UPSTREAM
On Mon, 20 May 2024 at 04:17, Tom Rini wrote: > > On Sun, May 19, 2024 at 09:57:03PM +0100, Jiaxun Yang wrote: > > > > > > 在2024年5月19日五月 下午7:20，Daniel Schwierzeck写道： > > > > > > Reviewed-by: Daniel Schwierzeck > > > > > Hi Daniel, > > > > Thanks for reviewing the series. > > > > > [...] > > > > > > should be 'select' because the switch to upstream DTS is permanent and > > > it does not make sense for the user to be able to deselect this option > > > > > > > Do you want me to send another version or are you going to fix > > it as you apply the patch? > > So, in the case of OF_UPTREAM, it's "imply OF_UPSTREAM" everywhere else > and while there's a case to be made it should be select instead, that's > probably a future clean-up for all users. I think it depends on whether OF_UPSTREAM is enabled for a SoC (with multiple board variants) or a single target board (I suppose that's the case here). For the former case, "imply" would be preferred since we can't enforce a policy at SoC level where new boards are coming up which have to opt out of OF_UPSTREAM. For the latter case, "select" would be preferred. However, I agree that it can be a future cleanup patch. -Sumit > > -- > Tom
Re: [PATCH 12/13] MIPS: boston: Migrate to OF_UPSTREAM
On Thu, 16 May 2024 at 17:29, Jiaxun Yang wrote:
>
>
>
> 在2024年5月14日五月 上午6:45，Sumit Garg写道：
> > Hi Jiaxun,
> >
> [...]
> >> @@ -0,0 +1,10 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +
> >> +_regs {
> >> + compatible = "img,boston-platform-regs", "syscon", "simple-mfd";
> >> + bootph-all;
> >> +};
> >> +
> >> +_boston {
> >> + bootph-all;
> >> +};
> >
> > You can try to push these overrides to upstream DTS as well, so you
> > won't have to maintain them in U-Boot.
>
> Hi Sumit,
>
> Thanks for your comments! For the compatible override, I already sent
> patch to upstream. However, I have a question, Can we really do bootph-all
> in linux upstream?
Yes.
>
> I don't think it's documented in upstream dt bindings.
>
It has been documented as part of core schema DT bindings here [1].
[1]
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/bootph.yaml
-Sumit
Re: [PATCH 1/1] Squashed 'dts/upstream/' changes from b35b9bd1d4ee..7e08733c96c8
On Wed, 15 May 2024 at 21:30, Tom Rini wrote: > > On Wed, May 15, 2024 at 11:39:08AM +0200, Jonas Karlman wrote: > > [snip] > > My main concern is how to best handle new boards and features/drivers. > > E.g. for Rockchip the RK3588 SoC is under active development, new boards > > and features/drivers are actively added/fixed in upstream Linux. > > To this question specifically, dts/update-dts-subtree.sh has a "pick" > option and in some previous quick testing, it does what one would hope. > So for this case you could pick the N commits that need to be brought > it, the resulting patch would be small enough to send to the list > normally (the resync patch for v6.9 is 2.7MB) and then when I do the > next full resync it goes cleanly still. That sounds like a good alternative although it was proposed for any fixes to be incorporated but it's worth giving it a try for new features too. I think as long as the cherry pick is clean with all dependencies being picked up properly, the next sync should work cleanly. -Sumit > > -- > Tom
Re: [PATCH 1/1] Squashed 'dts/upstream/' changes from b35b9bd1d4ee..7e08733c96c8
On Wed, 15 May 2024 at 15:09, Jonas Karlman wrote:
>
> Hi Sumit,
>
> On 2024-05-15 10:49, Sumit Garg wrote:
> > Hi Jonas,
> >
> > On Wed, 15 May 2024 at 13:11, Jonas Karlman wrote:
> >>
> >> Hi Tom,
> >>
> >> On 2024-05-14 18:42, Tom Rini wrote:>
> >>> git-subtree-dir: dts/upstream
> >>> git-subtree-split: 7e08733c96c84eb323f47e9b248c924e2ac6272a
> >>> ---
> >>> This moves OF_UPSTREAM to be tracking the v6.9 release and is for the
> >>> -next branch. To test these changes yourself locally, either use my
> >>> "WIP/14May2024-next" branch or run:
> >>> ./dts/update-dts-subtree.sh pull v6.9-dts
> >>> yourself locally. I intend to wait a few days to apply this to -next, to
> >>> give people time to test.
> >>>
> >>
> >> There are currently more boards/SoCs that use OF_UPSTREAM in master
> >> branch than in next branch, a few Rockchip SoCs and other boards/SoCs.
> >
> > Glad to see more OF_UPSTREAM adoption.
> >
> >> Next dts/upstream sync will probably be good to do together with a merge
> >> of master into next :-)
> >
> > I don't have any particular opinion here and rather leave it upto Tom
> > how he would like to merge stuff.
> >
> >>
> >> Also what is the expected sync cadence of dts/upstream? Linux v6.10 will
> >> probably be released shortly after U-Boot v2024.07. So will next sync be
> >> to v6.10-dts if that happens in the U-Boot merge window or do we expect
> >> 2024.10 to use v6.9 DTs if the v6.10 release gets delayed and miss the
> >> U-Boot merge window?
> >>
> >> Linux kernel typically have all major DT changes in -rc1 and fixes in
> >> later -rcX, so for next branch I would suggest an early sync to a
> >> v6.10-rcX-dts tag, and then sync to the final v6.10-dts tag once v6.10
> >> gets released. That should give more time for testing, migration and
> >> cleanup using v6.10 DTs in time for a 2024.10 release.
> >
> > I can see the reasoning for an aggressive DT syncing approach, it has
> > been brought up in the past too. And the major reason for the current
> > moderate sync approach [1] is to limit any DT ABI breakages for
> > U-Boot, we are even prone to breakages with syncs against major Linux
> > kernel releases (eg. v6.10-dts etc.). It has been a long time
> > discussion topic where we have been advocating about requirements for
> > DT ABI stability [2].
> >
> > So having DT syncs done during the merge window will shorten the
> > testing window for developers/maintainers. And more syncs means a
> > multiplicative factor for testing. However, time will tell with more
> > and more platforms adopting OF_UPSTREAM, if there are any real DT ABI
> > breakages seen in the future. But surely if they are very rare then I
> > am open to adopting aggressive DT sync approaches.
>
> I agree that syncing multiple rcX tags may not be that helpful, but an
> approach where maybe rc1, rc2 or rc3 and then the final tag is merged or
> something similar. At least when we can foresee when next Linux version
> will be released close to an U-Boot release. At least early in U-Boot
> release cycle know what Linux version dts/upstream will be targeted.
>
> My main concern is how to best handle new boards and features/drivers.
> E.g. for Rockchip the RK3588 SoC is under active development, new boards
> and features/drivers are actively added/fixed in upstream Linux.
>
> New Rockchip boards have typically been added after board DT have been
> merged into linux maintainer tree. Now if we wait until merge window to
> do a dts/upstream sync, the result may be that it may take up to three
> U-Boot releases until a new board is easily added using dts/upstream.
>
> Another approach could be that we add new boards using !OF_UPSTREAM once
> they are merged into linux maintainer tree. And then migrate the board
> to use OF_UPSTREAM once the board finally ends up in dts/upstream.
>
> But that can also be problematic when board .dts-file start referencing
> nodes/symbols not yet added in the soc .dts-file in dts/upstream.
> Adding the "missing" but maintainer merged soc nodes to the soc
> u-boot.dtsi could be one way to work around such issue.
I would suggest you to then maintain the under development soc
.dts-file in U-Boot too. Since with !OF_UPSTREAM, the soc .dts-file
present in the U-Boot DTS tree (arch/${ARCH}/dts/) will be used
instead of one from dts/upstream. This was especially done to support
use-cases like this via the directory include ordering. You c
Re: [PATCH 1/1] Squashed 'dts/upstream/' changes from b35b9bd1d4ee..7e08733c96c8
Hi Jonas, On Wed, 15 May 2024 at 13:11, Jonas Karlman wrote: > > Hi Tom, > > On 2024-05-14 18:42, Tom Rini wrote:> > > git-subtree-dir: dts/upstream > > git-subtree-split: 7e08733c96c84eb323f47e9b248c924e2ac6272a > > --- > > This moves OF_UPSTREAM to be tracking the v6.9 release and is for the > > -next branch. To test these changes yourself locally, either use my > > "WIP/14May2024-next" branch or run: > > ./dts/update-dts-subtree.sh pull v6.9-dts > > yourself locally. I intend to wait a few days to apply this to -next, to > > give people time to test. > > > > There are currently more boards/SoCs that use OF_UPSTREAM in master > branch than in next branch, a few Rockchip SoCs and other boards/SoCs. Glad to see more OF_UPSTREAM adoption. > Next dts/upstream sync will probably be good to do together with a merge > of master into next :-) I don't have any particular opinion here and rather leave it upto Tom how he would like to merge stuff. > > Also what is the expected sync cadence of dts/upstream? Linux v6.10 will > probably be released shortly after U-Boot v2024.07. So will next sync be > to v6.10-dts if that happens in the U-Boot merge window or do we expect > 2024.10 to use v6.9 DTs if the v6.10 release gets delayed and miss the > U-Boot merge window? > > Linux kernel typically have all major DT changes in -rc1 and fixes in > later -rcX, so for next branch I would suggest an early sync to a > v6.10-rcX-dts tag, and then sync to the final v6.10-dts tag once v6.10 > gets released. That should give more time for testing, migration and > cleanup using v6.10 DTs in time for a 2024.10 release. I can see the reasoning for an aggressive DT syncing approach, it has been brought up in the past too. And the major reason for the current moderate sync approach [1] is to limit any DT ABI breakages for U-Boot, we are even prone to breakages with syncs against major Linux kernel releases (eg. v6.10-dts etc.). It has been a long time discussion topic where we have been advocating about requirements for DT ABI stability [2]. So having DT syncs done during the merge window will shorten the testing window for developers/maintainers. And more syncs means a multiplicative factor for testing. However, time will tell with more and more platforms adopting OF_UPSTREAM, if there are any real DT ABI breakages seen in the future. But surely if they are very rare then I am open to adopting aggressive DT sync approaches. [1] https://docs.u-boot.org/en/latest/develop/devicetree/control.html#resyncing-with-devicetree-rebasing [2] https://www.mail-archive.com/boot-architecture@lists.linaro.org/msg02162.html -Sumit > > Regards, > Jonas
Re: [PATCH 12/13] MIPS: boston: Migrate to OF_UPSTREAM
Hi Jiaxun,
On Mon, 13 May 2024 at 23:43, Jiaxun Yang wrote:
>
> We can now boot with upstream devicetree.
>
> Signed-off-by: Jiaxun Yang
> ---
> arch/mips/Kconfig| 1 +
> arch/mips/dts/Makefile | 1 -
> arch/mips/dts/boston-u-boot.dtsi | 10 ++
> arch/mips/dts/img,boston.dts | 222
> ---
> board/imgtec/boston/MAINTAINERS | 1 +
> configs/boston32r2_defconfig | 2 +-
> configs/boston32r2el_defconfig | 2 +-
> configs/boston32r6_defconfig | 2 +-
> configs/boston32r6el_defconfig | 2 +-
> configs/boston64r2_defconfig | 2 +-
> configs/boston64r2el_defconfig | 2 +-
> configs/boston64r6_defconfig | 2 +-
> configs/boston64r6el_defconfig | 2 +-
> 13 files changed, 20 insertions(+), 231 deletions(-)
>
Thanks for your efforts although I have a further suggestion below but FWIW:
Reviewed-by: Sumit Garg
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 748b5175b2eb..733a8de4fb83 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -146,6 +146,7 @@ config TARGET_BOSTON
> select SUPPORTS_CPU_MIPS64_R2
> select SUPPORTS_CPU_MIPS64_R6
> select SUPPORTS_LITTLE_ENDIAN
> + imply OF_UPSTREAM
> imply BOOTSTD_FULL
> imply CLK
> imply CLK_BOSTON
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> index 14fbce597b9e..5478dcd8d025 100644
> --- a/arch/mips/dts/Makefile
> +++ b/arch/mips/dts/Makefile
> @@ -3,7 +3,6 @@
> dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
> dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
> dtb-$(CONFIG_TARGET_AP152) += ap152.dtb
> -dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
> dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
> dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
> dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
> diff --git a/arch/mips/dts/boston-u-boot.dtsi
> b/arch/mips/dts/boston-u-boot.dtsi
> new file mode 100644
> index ..1b0c0a289613
> --- /dev/null
> +++ b/arch/mips/dts/boston-u-boot.dtsi
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +_regs {
> + compatible = "img,boston-platform-regs", "syscon", "simple-mfd";
> + bootph-all;
> +};
> +
> +_boston {
> + bootph-all;
> +};
You can try to push these overrides to upstream DTS as well, so you
won't have to maintain them in U-Boot.
-Sumit
> diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts
> deleted file mode 100644
> index c1a73963037d..
> --- a/arch/mips/dts/img,boston.dts
> +++ /dev/null
> @@ -1,222 +0,0 @@
> -/dts-v1/;
> -
> -#include
> -#include
> -#include
> -#include
> -
> -/ {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "img,boston";
> -
> - chosen {
> - stdout-path =
> - };
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - cpu@0 {
> - device_type = "cpu";
> - compatible = "img,mips";
> - reg = <0>;
> - clocks = <_boston BOSTON_CLK_CPU>;
> - };
> - };
> -
> - memory@0 {
> - device_type = "memory";
> - reg = <0x 0x1000>;
> - };
> -
> - gic: interrupt-controller {
> - compatible = "mti,gic";
> -
> - interrupt-controller;
> - #interrupt-cells = <3>;
> -
> - timer {
> - compatible = "mti,gic-timer";
> - interrupts = ;
> - clocks = <_boston BOSTON_CLK_CPU>;
> - };
> - };
> -
> - pci0: pci@1000 {
> - status = "disabled";
> - compatible = "xlnx,axi-pcie-host-1.00.a";
> - device_type = "pci";
> - reg = <0x1000 0x200>;
> -
> - #address-cells = <3>;
> - #size-cells = <2>;
> - #interrupt-cells = <1>;
> -
> - interrupt-parent = <>;
> - interrupts = ;
> -
> - ranges = <0x0200 0 0x4000
> - 0x4000 0 0x4000>;
> -
> - interrupt-map-mask = <0 0 0 7>;
> - interrupt-map = <0 0 0 1 _intc 0&
Re: [PATCH 11/13] dts/upstream: Add Makefile for MIPS
Hi Jiaxun, On Mon, 13 May 2024 at 23:43, Jiaxun Yang wrote: > > It is required to make OF_UPSTREAM work. > > Signed-off-by: Jiaxun Yang > --- > dts/upstream/src/mips/Makefile | 14 ++ > 1 file changed, 14 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/dts/upstream/src/mips/Makefile b/dts/upstream/src/mips/Makefile > new file mode 100644 > index ..9a8f6aa35846 > --- /dev/null > +++ b/dts/upstream/src/mips/Makefile > @@ -0,0 +1,14 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +include $(srctree)/scripts/Makefile.dts > + > +targets += $(dtb-y) > + > +# Add any required device tree compiler flags here > +DTC_FLAGS += -a 0x8 > + > +PHONY += dtbs > +dtbs: $(addprefix $(obj)/, $(dtb-y)) > + @: > + > +clean-files := */*.dtb */*.dtbo > > -- > 2.34.1 >
Re: [PATCH] mach-snapdragon: do carveouts for qcs404 only
On Wed, 8 May 2024 at 18:09, Caleb Connolly wrote: > > Hi Sam, > > On 08/05/2024 13:40, Sam Day wrote: > > Salutations Sumit, > > > > On Wednesday, 8 May 2024 at 11:14 AM, Sumit Garg > > wrote: > > > >> > >> > >> Hi Sam, > >> > >> On Wed, 8 May 2024 at 00:11, Sam Day m...@samcday.com wrote: > >> > >>> The newly introduced carve_out_reserved_memory causes issues when > >>> U-Boot is chained from the lk2nd bootloader. lk2nd provides a > >>> simple-framebuffer device and marks the framebuffer region as no-map in > >>> the supplied /reserved-memory. Consequently, the simple_video driver > >>> triggers a page fault when it tries to write to this region. > >> > >> > >> How does the corresponding Linux kernel driver handle this? > > > > Firstly: I'm something of a middle-man here. I would consider Caleb the > > authoritative source on the carveouts stuff (since they wrote it) and > > Nikita Travkin the authority on the simplefb handoff (since he originally > > wrote it for lk2nd to hand off to Linux simpledrm and then adapted it to > > work with U-Boot simplefb). > > > > I consulted with Nikita on your first question here. He linked me to this > > snippet: > > https://elixir.bootlin.com/linux/v6.9-rc7/source/drivers/gpu/drm/tiny/simpledrm.c#L877 > > > >> Is the > >> framebuffer region required to be mapped as normal memory or device > >> type or something else? > > > > So I guess based on the link above, it's just mapped as normal uncached > > memory. > > > > I tried to do something like this a few days ago in U-Boot, but a) it > > doesn't work and b) I have no idea what I'm doing: > > https://github.com/samcday/u-boot/commit/c100cb3711ddf5b01601691f3e6a9ec890d9a496 Can you start adding some debug prints as to what might be happening? Also, look at my proposal below to hook memory mapping properly for drivers. > > > > After talking with Caleb about this for a bit, they suggested the patch you > > see here as what I guess could be considered a "stopgap" solution that > > hopefully makes it into 2024.07. > > > >> Similarly would normal memory type work for > >> all other reserved memory regions marked as no-map? > > > > I'll let Caleb weigh in here. My understanding is that the other regions > > *should* be marked as PTE_TYPE_FAULT because otherwise drivers might > > inadvertently speculatively access regions that are very much off-limits, > > such as TZ app regions. > > Right, carving out reserved regions and having the driver handle them is > theoretically the "correct" thing to do here. But I'm not sure that the > additional complexity offers much value from a U-Boot context. > > If we can teach the armv8 PT/cache code to handle this better, and teach > all the drivers to map their regions on-demand, this would probably help > us a lot (especially as right now if you attempt to access dead space > between peripherals then you'll hang the bus...). But U-Boot is a ways > away from that. I am not sure if U-Boot is really that far away although you can say the infrastructure is not hooked up for Arm. Have a look into map_physmem() and unmap_physmem() utilized by various drivers which are actually hooked up on MIPS. So I think the right way to approach this feature on Qcom platforms is to start hooking up those APIs on mach-snapdragon to begin with via mmu_set_region_dcache_behaviour() underneath. We can always go ahead and make it more generic if needed on other platforms too. -Sumit
Re: [PATCH] mach-snapdragon: do carveouts for qcs404 only
Hi Sam,
On Wed, 8 May 2024 at 00:11, Sam Day wrote:
>
> The newly introduced carve_out_reserved_memory causes issues when
> U-Boot is chained from the lk2nd bootloader. lk2nd provides a
> simple-framebuffer device and marks the framebuffer region as no-map in
> the supplied /reserved-memory. Consequently, the simple_video driver
> triggers a page fault when it tries to write to this region.
How does the corresponding Linux kernel driver handle this? Is the
framebuffer region required to be mapped as normal memory or device
type or something else? Similarly would normal memory type work for
all other reserved memory regions marked as no-map?
-Sumit
>
> As per Caleb's advice, this simple patch only does the carveouts for the
> qcs404 SoC for which it was originally designed. The intent is to do the
> carveouts for more Qualcomm SoCs in future.
>
> ---
> I'm not sure if it's feasible to get this in for the 2024.07 release,
> but it'd be great if we could - it's the only thing that breaks U-Boot
> master on msm8916 devices that chain from lk2nd.
>
> Signed-off-by: Sam Day
> ---
> arch/arm/mach-snapdragon/board.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-snapdragon/board.c
> b/arch/arm/mach-snapdragon/board.c
> index 3d5994c878..b439a19ec7 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -467,10 +467,12 @@ void enable_caches(void)
> gd->arch.tlb_addr = tlb_addr;
> gd->arch.tlb_size = tlb_size;
>
> - carveout_start = get_timer(0);
> - /* Takes ~20-50ms on SDM845 */
> - carve_out_reserved_memory();
> - debug("carveout time: %lums\n", get_timer(carveout_start));
> -
> + /* We do the carveouts only for QCS404, for now. */
> + if (fdt_node_check_compatible(gd->fdt_blob, 0, "qcom,qcs404") == 0) {
> + carveout_start = get_timer(0);
> + /* Takes ~20-50ms on SDM845 */
> + carve_out_reserved_memory();
> + debug("carveout time: %lums\n", get_timer(carveout_start));
> + }
> dcache_enable();
> }
>
> ---
> base-commit: 1c40dda60f5f7e83a6d6f541cf5a57eb7e8ec43c
> change-id: 20240507-qcs404-carveout-only-7a15bbf3fd89
>
> Best regards,
> --
> Sam Day
>
>
Re: [PATCH 108/149] board: qualcomm: Remove and add needed includes
On Wed, 1 May 2024 at 08:15, Tom Rini wrote: > > Remove from this board vendor directory and when needed > add missing include files directly. > > Signed-off-by: Tom Rini > --- > Cc: Ramon Fried > Cc: Caleb Connolly > Cc: Neil Armstrong > Cc: Sumit Garg > Cc: Jorge Ramirez-Ortiz > --- > board/qualcomm/dragonboard410c/dragonboard410c.c | 1 - > board/qualcomm/dragonboard820c/dragonboard820c.c | 1 - > 2 files changed, 2 deletions(-) > Reviewed-by: Sumit Garg -Sumit > diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c > b/board/qualcomm/dragonboard410c/dragonboard410c.c > index fbbfc0e65e24..bd2e213b3bca 100644 > --- a/board/qualcomm/dragonboard410c/dragonboard410c.c > +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c > @@ -6,7 +6,6 @@ > */ > > #include > -#include > #include > #include > #include > diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c > b/board/qualcomm/dragonboard820c/dragonboard820c.c > index ac7de711c588..da59db01 100644 > --- a/board/qualcomm/dragonboard820c/dragonboard820c.c > +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c > @@ -13,7 +13,6 @@ > #include > #include > #include > -#include > #include > #include > #include > -- > 2.34.1 >
Re: [PATCH v4 0/7] Add SE HMBSC board support
On Tue, 23 Apr 2024 at 17:29, Caleb Connolly wrote: > > Applied, thanks. Thanks. > > (b4 didn't seem to detect this series properly, hence the manual mail). > Switching my workflow to b4 is on my ToDo list. I hope to do it sooner rather than later. -Sumit > On 12/04/2024 11:54, Sumit Garg wrote: > > SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major > > difference from db410c is serial port where HMIBSC board uses UART1 as > > the debug console with an RS232 port, patch #2 - #5 adds corresponding > > driver support. > > > > Patch #6 adds main HMIBSC board specific bits, features: > > - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) > > - 2GiB RAM > > - 64GiB eMMC, SD slot > > - WiFi and Bluetooth > > - 2x Host, 1x Device USB port > > - HDMI > > - Discrete TPM2 chip over SPI > > > > Features enabled in U-Boot: > > - RAUC updates (refer [2] for more details) > > - Environment protection > > - USB based ethernet adaptors > > > > Feedback is very much welcome. > > > > Changes in v4: > > - Rebased on top of qcom-main [4]. > > - Split out board DTS patch as #6. > > - Convert to text based environment as hmibsc.env. > > - MMC regression has been reported for qcom-main branch here [5]. > > - Collected further review tag. > > > > Changes in v3: > > - Rebased on top of qcom-next [1]. > > - Collected some review tags. > > - Incorporated misc. comments from Caleb and Stephen. > > - Split patch#4 as requested. > > - Linux HMIBSC board DTS has already been reviewed here [3], I have > >incorporated that for U-Boot too. > > > > Changes in v2: > > - Rebased on top on qcom-next [1]. > > - Added patch#1 as a fix for generic qcom board support. > > - Added patch#4 to enable driving GPIO pins based on pinctrl > >configuration. This replaces the custom GPIO configuration. > > - Added proper DTS file for HMIBSC board based on Linux DT pattern. > > - Merged board support patches into a single patch#5. > > > > [1] > > https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-next?ref_type=heads > > [2] https://rauc.readthedocs.io/en/latest/ > > [3] > > https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.g...@linaro.org/ > > [4] > > https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-main/?ref_type=heads > > [5] > > https://lore.kernel.org/all/cafa6wyo+3vroudfuvh390taviqx8pmqroqdtsn0yu6bd5yy...@mail.gmail.com/ > > > > Sumit Garg (7): > >qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default > >apq8016: Add support for UART1 clocks and pinmux > >serial_msm: Enable RS232 flow control > >pinctrl: qcom: Add support for driving GPIO pins output > >pinctrl: qcom: apq8016: Add GPIO pinctrl function > >arm: dts: qcom: Add Schneider HMIBSC board dts > >board: add support for Schneider HMIBSC board > > > > arch/arm/Kconfig | 2 +- > > arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++ > > board/schneider/hmibsc/MAINTAINERS| 6 + > > board/schneider/hmibsc/hmibsc.env | 40 ++ > > configs/hmibsc_defconfig | 87 > > doc/board/index.rst | 1 + > > doc/board/schneider/hmibsc.rst| 45 ++ > > doc/board/schneider/index.rst | 9 + > > drivers/clk/qcom/clock-apq8016.c | 38 +- > > drivers/pinctrl/qcom/pinctrl-apq8016.c| 2 + > > drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- > > drivers/serial/serial_msm.c | 24 +- > > include/configs/hmibsc.h | 16 + > > 13 files changed, 760 insertions(+), 26 deletions(-) > > create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts > > create mode 100644 board/schneider/hmibsc/MAINTAINERS > > create mode 100644 board/schneider/hmibsc/hmibsc.env > > create mode 100644 configs/hmibsc_defconfig > > create mode 100644 doc/board/schneider/hmibsc.rst > > create mode 100644 doc/board/schneider/index.rst > > create mode 100644 include/configs/hmibsc.h > > > > -- > // Caleb (they/them)
Re: [PATCH 0/3] qcom: switch to OF_UPSTREAM
On Thu, 18 Apr 2024 at 10:24, Caleb Connolly wrote: > > This series does the initial switch to OF_UPSTREAM for Qualcomm > platforms. The DT files we have in U-Boot are outdated by now, so drop > them and move to upstream. > > Patch 2 drops all the Qualcomm dts files that are now provided in > dts/upstream. As some of the files exceed the 100k size limit by > themselves I thought it would be easier to just lump them together > rather than trying to split them up. > > The associated qcom headers will be cleaned up in future patches. > > --- > Caleb Connolly (3): > mach-snapdragon: use OF_UPSTREAM > arm: dts: drop qcom dts files > qcom_defconfig: set SYS_INIT_SP_BSS_OFFSET > Reviewed-by: Sumit Garg -Sumit > MAINTAINERS |4 - > arch/arm/Kconfig|1 + > arch/arm/dts/apq8016-sbc.dts| 729 > arch/arm/dts/apq8096-db820c.dts | 1137 -- > arch/arm/dts/msm8916-pm8916.dtsi| 157 - > arch/arm/dts/msm8916.dtsi | 2702 - > arch/arm/dts/msm8996.dtsi | 3884 -- > arch/arm/dts/pm8916.dtsi| 178 - > arch/arm/dts/pm8994.dtsi| 152 - > arch/arm/dts/pm8998.dtsi| 130 - > arch/arm/dts/pmi8994.dtsi | 65 - > arch/arm/dts/pmi8998.dtsi | 98 - > arch/arm/dts/pms405.dtsi| 149 - > arch/arm/dts/qcs404-evb-4000.dts| 96 - > arch/arm/dts/qcs404-evb.dtsi| 389 -- > arch/arm/dts/qcs404.dtsi| 1829 - > arch/arm/dts/sdm845-db845c.dts | 1190 -- > arch/arm/dts/sdm845-samsung-starqltechn.dts | 460 --- > arch/arm/dts/sdm845-wcd9340.dtsi| 86 - > arch/arm/dts/sdm845.dtsi| 5752 > --- > configs/dragonboard410c_defconfig |2 +- > configs/dragonboard820c_defconfig |2 +- > configs/qcom_defconfig |3 +- > 23 files changed, 5 insertions(+), 19190 deletions(-) > --- > base-commit: d5460b082cd6afd0e07c0ec0e5a82d1af8dc09f7 > > // Caleb (they/them) >
Re: [PATCH v3 1/3] clk: imx8mm: Add support for PCIe clocks
Hi Tim,
On Fri, 19 Apr 2024 at 08:29, Tim Harvey wrote:
>
> Add support for PCIe clocks required to enable PCIe support on
> iMX8MM SoC.
>
> Signed-off-by: Tim Harvey
> ---
> v3: wrap pcie clk config around IS_ENABLED to avoid SPL growth as
> suggested by Marek
> ---
> drivers/clk/imx/clk-imx8mm.c | 27 +++
> 1 file changed, 27 insertions(+)
>
Although I was at EOSS last week, it is really nice to see more iMX
SoCs adopting the modern PCIe DW iMX driver.
-Sumit
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index b5c253e49663..1a00dd1d287b 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -66,6 +66,17 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m",
> "sys_pll1_160m", "sys_
> static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m",
> "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
> "video_pll1_out", "audio_pll2_out",
> "sys_pll1_133m", };
>
> +#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
> +static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m",
> "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
> + "sys_pll1_800m",
> "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
> +
> +static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m",
> "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2",
> + "clk_ext3", "clk_ext4",
> "sys_pll1_400m", };
> +
> +static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m",
> "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
> + "sys_pll2_100m",
> "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
> +#endif
> +
> #ifndef CONFIG_SPL_BUILD
> static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
> "sys_pll1_160m", "sys_pll1_40m",
> "sys_pll3_out", "clk_ext1",
> "sys_pll1_80m", "video_pll1_out", };
> @@ -256,6 +267,17 @@ static int imx8mm_clk_probe(struct udevice *dev)
> imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base +
> 0x8b80));
>
> /* IP */
> +#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
> + clk_dm(IMX8MM_CLK_PCIE1_CTRL,
> + imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
> + base + 0xa300));
> + clk_dm(IMX8MM_CLK_PCIE1_PHY,
> + imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
> + base + 0xa380));
> + clk_dm(IMX8MM_CLK_PCIE1_AUX,
> + imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
> + base + 0xa400));
> +#endif
> clk_dm(IMX8MM_CLK_USDHC1,
>imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
>base + 0xac00));
> @@ -339,6 +361,11 @@ static int imx8mm_clk_probe(struct udevice *dev)
>imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
> #endif
>
> +#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
> + clk_dm(IMX8MM_CLK_PCIE1_ROOT,
> + imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250,
> 0));
> +#endif
> +
> #if CONFIG_IS_ENABLED(DM_SPI)
> clk_dm(IMX8MM_CLK_ECSPI1,
>imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base +
> 0xb280));
> --
> 2.25.1
>
Re: [PATCH v4 0/7] Add SE HMBSC board support
Hi Caleb, On Fri, 12 Apr 2024 at 02:54, Sumit Garg wrote: > > SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major > difference from db410c is serial port where HMIBSC board uses UART1 as > the debug console with an RS232 port, patch #2 - #5 adds corresponding > driver support. > > Patch #6 adds main HMIBSC board specific bits, features: > - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) > - 2GiB RAM > - 64GiB eMMC, SD slot > - WiFi and Bluetooth > - 2x Host, 1x Device USB port > - HDMI > - Discrete TPM2 chip over SPI > > Features enabled in U-Boot: > - RAUC updates (refer [2] for more details) > - Environment protection > - USB based ethernet adaptors > > Feedback is very much welcome. > > Changes in v4: > - Rebased on top of qcom-main [4]. > - Split out board DTS patch as #6. > - Convert to text based environment as hmibsc.env. > - MMC regression has been reported for qcom-main branch here [5]. > - Collected further review tag. I haven't seen any further comments on this series. Can you help pick it up? -Sumit > > Changes in v3: > - Rebased on top of qcom-next [1]. > - Collected some review tags. > - Incorporated misc. comments from Caleb and Stephen. > - Split patch#4 as requested. > - Linux HMIBSC board DTS has already been reviewed here [3], I have > incorporated that for U-Boot too. > > Changes in v2: > - Rebased on top on qcom-next [1]. > - Added patch#1 as a fix for generic qcom board support. > - Added patch#4 to enable driving GPIO pins based on pinctrl > configuration. This replaces the custom GPIO configuration. > - Added proper DTS file for HMIBSC board based on Linux DT pattern. > - Merged board support patches into a single patch#5. > > [1] > https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-next?ref_type=heads > [2] https://rauc.readthedocs.io/en/latest/ > [3] > https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.g...@linaro.org/ > [4] > https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-main/?ref_type=heads > [5] > https://lore.kernel.org/all/cafa6wyo+3vroudfuvh390taviqx8pmqroqdtsn0yu6bd5yy...@mail.gmail.com/ > > Sumit Garg (7): > qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default > apq8016: Add support for UART1 clocks and pinmux > serial_msm: Enable RS232 flow control > pinctrl: qcom: Add support for driving GPIO pins output > pinctrl: qcom: apq8016: Add GPIO pinctrl function > arm: dts: qcom: Add Schneider HMIBSC board dts > board: add support for Schneider HMIBSC board > > arch/arm/Kconfig | 2 +- > arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++ > board/schneider/hmibsc/MAINTAINERS| 6 + > board/schneider/hmibsc/hmibsc.env | 40 ++ > configs/hmibsc_defconfig | 87 > doc/board/index.rst | 1 + > doc/board/schneider/hmibsc.rst| 45 ++ > doc/board/schneider/index.rst | 9 + > drivers/clk/qcom/clock-apq8016.c | 38 +- > drivers/pinctrl/qcom/pinctrl-apq8016.c| 2 + > drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- > drivers/serial/serial_msm.c | 24 +- > include/configs/hmibsc.h | 16 + > 13 files changed, 760 insertions(+), 26 deletions(-) > create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts > create mode 100644 board/schneider/hmibsc/MAINTAINERS > create mode 100644 board/schneider/hmibsc/hmibsc.env > create mode 100644 configs/hmibsc_defconfig > create mode 100644 doc/board/schneider/hmibsc.rst > create mode 100644 doc/board/schneider/index.rst > create mode 100644 include/configs/hmibsc.h > > -- > 2.34.1 >
[PATCH v4 7/7] board: add support for Schneider HMIBSC board
Support for Schneider Electric HMIBSC. Features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI
Features enabled in U-Boot:
- RAUC updates
- Environment protection
- USB based ethernet adaptors
Signed-off-by: Sumit Garg
---
board/schneider/hmibsc/MAINTAINERS | 6 +++
board/schneider/hmibsc/hmibsc.env | 40 ++
configs/hmibsc_defconfig | 87 ++
doc/board/index.rst| 1 +
doc/board/schneider/hmibsc.rst | 45
doc/board/schneider/index.rst | 9
include/configs/hmibsc.h | 16 ++
7 files changed, 204 insertions(+)
create mode 100644 board/schneider/hmibsc/MAINTAINERS
create mode 100644 board/schneider/hmibsc/hmibsc.env
create mode 100644 configs/hmibsc_defconfig
create mode 100644 doc/board/schneider/hmibsc.rst
create mode 100644 doc/board/schneider/index.rst
create mode 100644 include/configs/hmibsc.h
diff --git a/board/schneider/hmibsc/MAINTAINERS
b/board/schneider/hmibsc/MAINTAINERS
new file mode 100644
index 000..0f31bbda966
--- /dev/null
+++ b/board/schneider/hmibsc/MAINTAINERS
@@ -0,0 +1,6 @@
+HMIBSC BOARD
+M: Sumit Garg
+S: Maintained
+F: board/schneider/hmibsc/
+F: include/configs/hmibsc.h
+F: configs/hmibsc_defconfig
diff --git a/board/schneider/hmibsc/hmibsc.env
b/board/schneider/hmibsc/hmibsc.env
new file mode 100644
index 000..da3d892f91d
--- /dev/null
+++ b/board/schneider/hmibsc/hmibsc.env
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+loadaddr=0x9000
+bootcmd=
+ echo "Booting RAUC A/B system";
+ setenv devtype mmc; setenv devnum 0;
+ test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B";
+ test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3;
+ test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3;
+ setenv raucslot;
+ for BOOT_SLOT in "${BOOT_ORDER}"; do
+ if test "x${raucslot}" != "x"; then
+ echo "skip remaining slots...";
+ elif test "x${BOOT_SLOT}" = "xA"; then
+ if test ${BOOT_A_LEFT} -gt 0; then
+ setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1;
+ echo "Found valid RAUC slot A";
+ setenv raucslot "rauc.slot=A";
+ setenv raucpart A; setenv distro_bootpart 6;
+ fi;
+ elif test "x${BOOT_SLOT}" = "xB"; then
+ if test ${BOOT_B_LEFT} -gt 0; then
+ setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1;
+ echo "Found valid RAUC slot B";
+ setenv raucslot "rauc.slot=B";
+ setenv raucpart B; setenv distro_bootpart 7;
+ fi;
+ fi;
+ done;
+ if test -n "${raucslot}"; then
+ setenv bootargs console=ttyMSM1
root=PARTLABEL=rootfs_${raucpart} rw rootwait ${raucslot};
+ saveenv;
+ else
+ echo "No valid RAUC slot found. Resetting tries to 3";
+ setenv BOOT_A_LEFT 3;
+ setenv BOOT_B_LEFT 3;
+ saveenv;
+ reset;
+ fi;
+ load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} /boot/fitImage
&& bootm;
diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig
new file mode 100644
index 000..a07689894ef
--- /dev/null
+++ b/configs/hmibsc_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="schneider"
+CONFIG_SYS_BOARD="hmibsc"
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_TEXT_BASE=0x8f60
+CONFIG_SYS_MALLOC_LEN=0x802000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DEFAULT_DEVICE_TREE="apq8016-schneider-hmibsc"
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_IDENT_STRING="\nSchneider Electric-HMIBSC"
+CONFIG_SYS_LOAD_ADDR=0x8008
+CONFIG_REMAKE_ELF=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_CBSIZE=2048
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="hmibsc => "
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART
[PATCH v4 6/7] arm: dts: qcom: Add Schneider HMIBSC board dts
Schneider HMIBSC board dts has already been reviewed upstream on the
linux-arm-msm mailing list. So once it comes through the Linux kernel
release cycle into the U-Boot dts/upstream subtree, a switch to
OF_UPSTREAM can be made. For the time being maintain the U-Boot copy.
Link:
https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.g...@linaro.org/
Signed-off-by: Sumit Garg
---
arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++
1 file changed, 491 insertions(+)
create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts
diff --git a/arch/arm/dts/apq8016-schneider-hmibsc.dts
b/arch/arm/dts/apq8016-schneider-hmibsc.dts
new file mode 100644
index 000..75c6137e5a1
--- /dev/null
+++ b/arch/arm/dts/apq8016-schneider-hmibsc.dts
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ model = "Schneider Electric HMIBSC Board";
+ compatible = "schneider,apq8016-hmibsc", "qcom,apq8016";
+
+ aliases {
+ i2c1 = _i2c6;
+ i2c3 = _i2c4;
+ i2c4 = _i2c3;
+ mmc0 = _1; /* eMMC */
+ mmc1 = _2; /* SD card */
+ serial0 = _uart1;
+ serial1 = _uart2;
+ spi0 = _spi5;
+ usid0 = _0;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-0 = <_key_volp_n_default>;
+ pinctrl-names = "default";
+
+ button {
+ label = "Volume Up";
+ linux,code = ;
+ gpios = < 107 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <_mpps_leds>;
+ pinctrl-names = "default";
+
+ led-1 {
+ function = LED_FUNCTION_WLAN;
+ color = ;
+ gpios = <_mpps 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_BLUETOOTH;
+ color = ;
+ gpios = <_mpps 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+ };
+
+ memory@8000 {
+ reg = <0 0x8000 0 0x4000>;
+ };
+
+ reserved-memory {
+ ramoops@bff0 {
+ compatible = "ramoops";
+ reg = <0x0 0xbff0 0x0 0x10>;
+ record-size = <0x2>;
+ console-size = <0x2>;
+ ftrace-size = <0x2>;
+ ecc-size = <16>;
+ };
+ };
+
+ usb-hub {
+ compatible = "smsc,usb3503";
+ reset-gpios = <_gpios 1 GPIO_ACTIVE_LOW>;
+ initial-mode = <1>;
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = < 110 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <_id_default>;
+ pinctrl-names = "default";
+ };
+};
+
+_i2c3 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
+};
+
+_i2c4 {
+ status = "okay";
+
+ adv_bridge: bridge@39 {
+ compatible = "adi,adv7533";
+ reg = <0x39>;
+ interrupts-extended = < 31 IRQ_TYPE_EDGE_FALLING>;
+
+ adi,dsi-lanes = <4>;
+ clocks = < RPM_SMD_BB_CLK2>;
+ clock-names = "cec";
+ pd-gpios = < 32 GPIO_ACTIVE_HIGH>;
+
+ avdd-supply = <_l6>;
+ a2vdd-supply = <_l6>;
+ dvdd-supply = <_l6>;
+ pvdd-supply = <_
[PATCH v4 5/7] pinctrl: qcom: apq8016: Add GPIO pinctrl function
Add GPIO pinctrl function to enable driving GPIO pins as output low or
high.
Signed-off-by: Sumit Garg
---
drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 1ee8b7db1a2..b14a8921af4 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"gpio", 0},
{"blsp_uart1", 2},
{"blsp_uart2", 2},
};
--
2.34.1
[PATCH v4 4/7] pinctrl: qcom: Add support for driving GPIO pins output
Add support for driving the GPIO pins as output low or high.
Signed-off-by: Sumit Garg
---
drivers/pinctrl/qcom/pinctrl-qcom.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c
b/drivers/pinctrl/qcom/pinctrl-qcom.c
index 909e566acf5..e68971b37ff 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -29,15 +29,24 @@ struct msm_pinctrl_priv {
#define GPIO_CONFIG_REG(priv, x) \
(qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
-#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
-#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_DISABLE BIT(9)
+#define GPIO_IN_OUT_REG(priv, x) \
+ (GPIO_CONFIG_REG(priv, x) + 0x4)
+
+#define TLMM_GPIO_PULL_MASKGENMASK(1, 0)
+#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
+#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
+#define TLMM_GPIO_OUTPUT_MASK BIT(1)
+#define TLMM_GPIO_OE_MASK BIT(9)
+
+/* GPIO register shifts. */
+#define GPIO_OUT_SHIFT 1
static const struct pinconf_param msm_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
+ { "output-high", PIN_CONFIG_OUTPUT, 1, },
+ { "output-low", PIN_CONFIG_OUTPUT, 0, },
};
static int msm_get_functions_count(struct udevice *dev)
@@ -90,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int
pin_selector,
return 0;
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
- TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
+ TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2);
return 0;
}
@@ -117,6 +126,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned
int pin_selector,
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv,
pin_selector),
TLMM_GPIO_PULL_MASK, argument);
break;
+ case PIN_CONFIG_OUTPUT:
+ writel(argument << GPIO_OUT_SHIFT,
+ priv->base + GPIO_IN_OUT_REG(priv, pin_selector));
+ setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
+TLMM_GPIO_OE_MASK);
+ break;
default:
return 0;
}
--
2.34.1
[PATCH v4 3/7] serial_msm: Enable RS232 flow control
SE HMIBSC board debug console requires RS232 flow control, so enable corresponding support if RS232 gpios are present. Reviewed-by: Caleb Connolly Signed-off-by: Sumit Garg --- drivers/serial/serial_msm.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 4de10e75191..3142ecf7362 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -53,10 +53,11 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC -#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 -#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 -#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC +#define MSM_BOOT_UART_DM_8_N_1_MODE0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define MSM_UART_MR1_RX_RDY_CTLBIT(7) DECLARE_GLOBAL_DATA_PTR; @@ -182,7 +183,9 @@ static void uart_dm_init(struct msm_serial_data *priv) mdelay(5); writel(priv->clk_bit_rate, priv->base + UARTDM_CSR); - writel(0x0, priv->base + UARTDM_MR1); + + /* Enable RS232 flow control to support RS232 db9 connector */ + writel(MSM_UART_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1); writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); -- 2.34.1
[PATCH v4 2/7] apq8016: Add support for UART1 clocks and pinmux
SE HMIBSC board uses UART1 as the main debug console, so add
corresponding clocks and pinmux support. Along with that update
instructions to enable clocks for debug UART support.
Reviewed-by: Caleb Connolly
Signed-off-by: Sumit Garg
---
drivers/clk/qcom/clock-apq8016.c | 38 ++
drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
drivers/serial/serial_msm.c| 11 ++--
3 files changed, 35 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 5a5868169c8..9556b94774a 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -31,7 +31,8 @@
#define BLSP1_AHB_CBCR 0x1008
/* Uart clock control registers */
-#define BLSP1_UART2_BCR(0x3028)
+#define BLSP1_UART1_APPS_CBCR (0x203C)
+#define BLSP1_UART1_APPS_CMD_RCGR (0x2044)
#define BLSP1_UART2_APPS_CBCR (0x302C)
#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
@@ -52,7 +53,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
};
/* SDHCI */
-static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
+static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
{
int div = 15; /* 100MHz default */
@@ -70,20 +71,35 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int
slot, uint rate)
}
/* UART: 115200 */
-int apq8016_clk_init_uart(phys_addr_t base)
+int apq8016_clk_init_uart(phys_addr_t base, unsigned long id)
{
+ u32 cmd_rcgr, apps_cbcr;
+
+ switch (id) {
+ case GCC_BLSP1_UART1_APPS_CLK:
+ cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR;
+ apps_cbcr = BLSP1_UART1_APPS_CBCR;
+ break;
+ case GCC_BLSP1_UART2_APPS_CLK:
+ cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR;
+ apps_cbcr = BLSP1_UART2_APPS_CBCR;
+ break;
+ default:
+ return 0;
+ }
+
/* Enable AHB clock */
clk_enable_vote_clk(base, _blsp1_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */
- clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625,
-CFG_CLK_SRC_GPLL0, 16);
+ clk_rcg_set_rate_mnd(base, cmd_rcgr, 1, 144, 15625, CFG_CLK_SRC_GPLL0,
+16);
/* Vote for gpll0 clock */
clk_enable_gpll0(base, _vote_clk);
/* Enable core clk */
- clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR);
+ clk_enable_cbc(base + apps_cbcr);
return 0;
}
@@ -94,14 +110,12 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong
rate)
switch (clk->id) {
case GCC_SDCC1_APPS_CLK: /* SDC1 */
- return clk_init_sdc(priv, 0, rate);
- break;
+ return apq8016_clk_init_sdc(priv, 0, rate);
case GCC_SDCC2_APPS_CLK: /* SDC2 */
- return clk_init_sdc(priv, 1, rate);
- break;
+ return apq8016_clk_init_sdc(priv, 1, rate);
+ case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */
case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
- return apq8016_clk_init_uart(priv->base);
- break;
+ return apq8016_clk_init_uart(priv->base, clk->id);
default:
return 0;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index a9a00f4b081..1ee8b7db1a2 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"blsp_uart1", 2},
{"blsp_uart2", 2},
};
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index ac4280c6c4c..4de10e75191 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -248,12 +248,17 @@ static struct msm_serial_data init_serial_data = {
#include
/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916
*/
-//int apq8016_clk_init_uart(phys_addr_t gcc_base);
+//int apq8016_clk_init_uart(phys_addr_t gcc_base, unsigned long id);
static inline void _debug_uart_init(void)
{
- /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on
MSM8916 */
- //apq8016_clk_init_uart(0x180);
+ /*
+* Uncomment to turn on UART clocks when debugging U-Boot as aboot
+* on MSM8916. Supported debug UART clock IDs:
+* - db410c: GCC_BLSP1_UART2_APPS_CLK
+* - HMIBSC: GCC_BLSP1_UART1_APPS_CLK
+*/
+ //apq8016_clk_init_uart(0x180, );
uart_dm_init(_serial_data);
}
--
2.34.1
[PATCH v4 1/7] qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default
Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow
ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is
loaded as a first stage bootloader. It leads to secondary CPUs bringup
failure and later causing the Linux kernel to freeze.
So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's
actually required.
Fixes: 059d526af312 ("mach-snapdragon: generalise board support")
Reviewed-by: Caleb Connolly
Signed-off-by: Sumit Garg
---
arch/arm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 23ee25269a2..1d451c46d32 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1088,7 +1088,7 @@ config ARCH_SNAPDRAGON
select BOARD_LATE_INIT
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR
- select LINUX_KERNEL_IMAGE_HEADER
+ select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
imply CMD_DM
config ARCH_SOCFPGA
--
2.34.1
[PATCH v4 0/7] Add SE HMBSC board support
SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major difference from db410c is serial port where HMIBSC board uses UART1 as the debug console with an RS232 port, patch #2 - #5 adds corresponding driver support. Patch #6 adds main HMIBSC board specific bits, features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI Features enabled in U-Boot: - RAUC updates (refer [2] for more details) - Environment protection - USB based ethernet adaptors Feedback is very much welcome. Changes in v4: - Rebased on top of qcom-main [4]. - Split out board DTS patch as #6. - Convert to text based environment as hmibsc.env. - MMC regression has been reported for qcom-main branch here [5]. - Collected further review tag. Changes in v3: - Rebased on top of qcom-next [1]. - Collected some review tags. - Incorporated misc. comments from Caleb and Stephen. - Split patch#4 as requested. - Linux HMIBSC board DTS has already been reviewed here [3], I have incorporated that for U-Boot too. Changes in v2: - Rebased on top on qcom-next [1]. - Added patch#1 as a fix for generic qcom board support. - Added patch#4 to enable driving GPIO pins based on pinctrl configuration. This replaces the custom GPIO configuration. - Added proper DTS file for HMIBSC board based on Linux DT pattern. - Merged board support patches into a single patch#5. [1] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-next?ref_type=heads [2] https://rauc.readthedocs.io/en/latest/ [3] https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.g...@linaro.org/ [4] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-main/?ref_type=heads [5] https://lore.kernel.org/all/cafa6wyo+3vroudfuvh390taviqx8pmqroqdtsn0yu6bd5yy...@mail.gmail.com/ Sumit Garg (7): qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default apq8016: Add support for UART1 clocks and pinmux serial_msm: Enable RS232 flow control pinctrl: qcom: Add support for driving GPIO pins output pinctrl: qcom: apq8016: Add GPIO pinctrl function arm: dts: qcom: Add Schneider HMIBSC board dts board: add support for Schneider HMIBSC board arch/arm/Kconfig | 2 +- arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++ board/schneider/hmibsc/MAINTAINERS| 6 + board/schneider/hmibsc/hmibsc.env | 40 ++ configs/hmibsc_defconfig | 87 doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst| 45 ++ doc/board/schneider/index.rst | 9 + drivers/clk/qcom/clock-apq8016.c | 38 +- drivers/pinctrl/qcom/pinctrl-apq8016.c| 2 + drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- drivers/serial/serial_msm.c | 24 +- include/configs/hmibsc.h | 16 + 13 files changed, 760 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 board/schneider/hmibsc/hmibsc.env create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h -- 2.34.1
Re: [PATCH 1/7] mmc: msm_sdhci: correct vendor_spec_cap0 register for v5
On Fri, 12 Apr 2024 at 14:06, Neil Armstrong wrote:
>
> On 11/04/2024 15:59, Sumit Garg wrote:
> > On Tue, 9 Apr 2024 at 23:33, Caleb Connolly
> > wrote:
> >>
> >> The V4 and V5 controllers have quite varied register layouts. Inherit
> >> the register offsets and naming from the Linux driver. More version
> >> specific offsets can be inherited from Linux as needed.
> >>
> >> Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support")
> >> Signed-off-by: Caleb Connolly
> >> ---
> >> drivers/mmc/msm_sdhci.c | 11 +++
> >> 1 file changed, 7 insertions(+), 4 deletions(-)
> >>
> >
> > This patch broke booting on the HMIBSC board, have you tested it on
> > db410c? It's very likely that this has caused regression there too.
> >
> > Error observed:
> >
> > sdhci_send_command: Timeout for status update: 0001
>
> Indeed swapping the core_vendor_spec_capabilities0 between msm_sdhc_v5_var &
> msm_sdhc_mci_var
> fixes this and I'm now able to enable SDCard on the SM8550-HDK
Yeah this fixed the problem for me too. I am unsure how it worked for
Caleb on db845c.
Caleb,
Can you fix up this patch which is already in your tree already?
-Sumit
>
> Neil
>
> >
> > -Sumit
> >
> >> diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
> >> index 059cb3da77c5..f23d425144ef 100644
> >> --- a/drivers/mmc/msm_sdhci.c
> >> +++ b/drivers/mmc/msm_sdhci.c
> >> @@ -32,11 +32,8 @@
> >> #define SDCC_MCI_STATUS2 0x6C
> >> #define SDCC_MCI_STATUS2_MCI_ACT 0x1
> >> #define SDCC_MCI_HC_MODE 0x78
> >>
> >> -/* Non standard (?) SDHCI register */
> >> -#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
> >> -
> >> struct msm_sdhc_plat {
> >> struct mmc_config cfg;
> >> struct mmc mmc;
> >> };
> >> @@ -48,8 +45,10 @@ struct msm_sdhc {
> >> };
> >>
> >> struct msm_sdhc_variant_info {
> >> bool mci_removed;
> >> +
> >> + u32 core_vendor_spec_capabilities0;
> >> };
> >>
> >> DECLARE_GLOBAL_DATA_PTR;
> >>
> >> @@ -180,9 +179,9 @@ static int msm_sdc_probe(struct udevice *dev)
> >> */
> >> if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
> >> caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
> >> caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
> >> - writel(caps, host->ioaddr +
> >> SDHCI_VENDOR_SPEC_CAPABILITIES0);
> >> + writel(caps, host->ioaddr +
> >> var_info->core_vendor_spec_capabilities0);
> >> }
> >>
> >> ret = mmc_of_parse(dev, >cfg);
> >> if (ret)
> >> @@ -243,12 +242,16 @@ static int msm_sdc_bind(struct udevice *dev)
> >> }
> >>
> >> static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
> >> .mci_removed = false,
> >> +
> >> + .core_vendor_spec_capabilities0 = 0x21c,
> >> };
> >>
> >> static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
> >> .mci_removed = true,
> >> +
> >> + .core_vendor_spec_capabilities0 = 0x11c,
> >> };
> >>
> >> static const struct udevice_id msm_mmc_ids[] = {
> >> { .compatible = "qcom,sdhci-msm-v4", .data =
> >> (ulong)_sdhc_mci_var },
> >>
> >> --
> >> 2.44.0
> >>
>
Re: [PATCH 1/7] mmc: msm_sdhci: correct vendor_spec_cap0 register for v5
On Tue, 9 Apr 2024 at 23:33, Caleb Connolly wrote:
>
> The V4 and V5 controllers have quite varied register layouts. Inherit
> the register offsets and naming from the Linux driver. More version
> specific offsets can be inherited from Linux as needed.
>
> Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support")
> Signed-off-by: Caleb Connolly
> ---
> drivers/mmc/msm_sdhci.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
This patch broke booting on the HMIBSC board, have you tested it on
db410c? It's very likely that this has caused regression there too.
Error observed:
sdhci_send_command: Timeout for status update: 0001
-Sumit
> diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
> index 059cb3da77c5..f23d425144ef 100644
> --- a/drivers/mmc/msm_sdhci.c
> +++ b/drivers/mmc/msm_sdhci.c
> @@ -32,11 +32,8 @@
> #define SDCC_MCI_STATUS2 0x6C
> #define SDCC_MCI_STATUS2_MCI_ACT 0x1
> #define SDCC_MCI_HC_MODE 0x78
>
> -/* Non standard (?) SDHCI register */
> -#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
> -
> struct msm_sdhc_plat {
> struct mmc_config cfg;
> struct mmc mmc;
> };
> @@ -48,8 +45,10 @@ struct msm_sdhc {
> };
>
> struct msm_sdhc_variant_info {
> bool mci_removed;
> +
> + u32 core_vendor_spec_capabilities0;
> };
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -180,9 +179,9 @@ static int msm_sdc_probe(struct udevice *dev)
> */
> if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
> caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
> caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
> - writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
> + writel(caps, host->ioaddr +
> var_info->core_vendor_spec_capabilities0);
> }
>
> ret = mmc_of_parse(dev, >cfg);
> if (ret)
> @@ -243,12 +242,16 @@ static int msm_sdc_bind(struct udevice *dev)
> }
>
> static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
> .mci_removed = false,
> +
> + .core_vendor_spec_capabilities0 = 0x21c,
> };
>
> static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
> .mci_removed = true,
> +
> + .core_vendor_spec_capabilities0 = 0x11c,
> };
>
> static const struct udevice_id msm_mmc_ids[] = {
> { .compatible = "qcom,sdhci-msm-v4", .data = (ulong)_sdhc_mci_var
> },
>
> --
> 2.44.0
>
[PATCH v2] mach-snapdragon: Allow other board vendors apart from Qcom
Qcom SoCs derived boards can come from various OEMs/ODMs and not just Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly corressponding to the actual board vendor. Suggested-by: Stephan Gerhold Reviewed-by: Caleb Connolly Signed-off-by: Sumit Garg --- Changes in v2: - Retained default vendor being "qualcomm". - Collected review tag. arch/arm/mach-snapdragon/Kconfig | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 96e44e2c549..536960b83c3 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -4,7 +4,12 @@ config SYS_SOC default "snapdragon" config SYS_VENDOR + string "Snapdragon board vendor" default "qualcomm" + help + Allows to specify vendor for the Snapdragon SoCs based boards. + Based on this option board// + will be used as the custom board directory. config SYS_MALLOC_F_LEN default 0x2000 @@ -19,12 +24,11 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x8000 config SYS_BOARD - string "Qualcomm custom board" + string "Snapdragon SoCs based board" help - The Dragonboard 410c and 820c have additional board init - code that isn't shared with other Qualcomm boards. - Based on this option board/qualcomm/ will - be used. + Allows to specify the Snapdragon SoCs based board name. + Based on this option board// + will be used as the custom board directory. config SYS_CONFIG_NAME string "Board configuration name" -- 2.34.1
Re: [PATCH v2 0/4] qcom: pinctrl drivers for qcm2290/sm6115/sm8250
On Wed, 10 Apr 2024 at 23:23, Caleb Connolly wrote: > > Introduce pinctrl drivers for three new SoCs and enable them. > > Signed-off-by: Caleb Connolly > --- > Changes in v2: > - Fix a few formatting issues > - Link to v1: > https://lore.kernel.org/r/20240408-b4-qcom-rbx-soc-v1-0-900db37b8...@linaro.org > > --- > Caleb Connolly (4): > pinctrl: qcom: add qcm2290 pinctrl driver > pinctrl: qcom: add sm6115 pinctrl driver > pinctrl: qcom: add sm8250 pinctrl driver > qcom_defconfig: enable pinctrl for new qcm2290/sm6115/sm8250 > Acked-by: Sumit Garg -Sumit > configs/qcom_defconfig | 3 + > drivers/pinctrl/qcom/Kconfig | 21 > drivers/pinctrl/qcom/Makefile | 3 + > drivers/pinctrl/qcom/pinctrl-qcm2290.c | 70 > drivers/pinctrl/qcom/pinctrl-sm6115.c | 200 > + > drivers/pinctrl/qcom/pinctrl-sm8250.c | 99 > 6 files changed, 396 insertions(+) > --- > change-id: 20240408-b4-qcom-rbx-soc-44ee99c8b799 > base-commit: 4ba549b0a4e67c563785ab144edf47e108b34822 > > // Caleb (they/them) >
Re: [PATCH v2 0/2] phy: qcom: add support for the Qualcomm Synopsys eUSB2 PHY
On Wed, 10 Apr 2024 at 21:31, Neil Armstrong wrote: > > Add support for the new Qualcomm Synopsys eUSB2 PHY found in the > SM8550 and SM8650 SoCs. > > Finally enable the driver in the Qualcomm defconfig. > > Signed-off-by: Neil Armstrong > --- > Changes in v2: > - fixed driver build failure due to missin } > - Link to v1: > https://lore.kernel.org/r/20240405-topic-sm8x50-usb-phy-v1-0-8a8604bf8...@linaro.org > > --- > Neil Armstrong (2): > phy: qcom: add Synopsys eUSB2 PHY driver > qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver > Acked-by: Sumit Garg -Sumit > configs/qcom_defconfig | 1 + > drivers/phy/qcom/Kconfig | 8 + > drivers/phy/qcom/Makefile | 1 + > drivers/phy/qcom/phy-qcom-snps-eusb2.c | 366 > + > 4 files changed, 376 insertions(+) > --- > base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb > change-id: 20240404-topic-sm8x50-usb-phy-d09a98f72d1b > > Best regards, > -- > Neil Armstrong >
[PATCH] mach-snapdragon: Allow other board vendors apart from Qcom
Qcom SoCs derived boards can come from various OEMs/ODMs and not just Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly corressponding to the actual board vendor. Suggested-by: Stephan Gerhold Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/Kconfig | 15 +-- configs/dragonboard410c_defconfig | 1 + configs/dragonboard820c_defconfig | 1 + 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 96e44e2c549..4615a140d0d 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -4,7 +4,11 @@ config SYS_SOC default "snapdragon" config SYS_VENDOR - default "qualcomm" + string "Snapdragon board vendor" + help + Allows to specify vendor for the Snapdragon SoCs based boards. + Based on this option board// + will be used as the custom board directory. config SYS_MALLOC_F_LEN default 0x2000 @@ -19,12 +23,11 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x8000 config SYS_BOARD - string "Qualcomm custom board" + string "Snapdragon SoCs based board" help - The Dragonboard 410c and 820c have additional board init - code that isn't shared with other Qualcomm boards. - Based on this option board/qualcomm/ will - be used. + Allows to specify the Snapdragon SoCs based board name. + Based on this option board// + will be used as the custom board directory. config SYS_CONFIG_NAME string "Board configuration name" diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 260a8349d3b..3b6f50307a3 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_VENDOR="qualcomm" CONFIG_SYS_BOARD="dragonboard410c" CONFIG_COUNTER_FREQUENCY=1900 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index ebc80eb2a46..a795497ef5d 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_VENDOR="qualcomm" CONFIG_SYS_BOARD="dragonboard820c" CONFIG_COUNTER_FREQUENCY=1900 CONFIG_ARCH_SNAPDRAGON=y -- 2.34.1
Re: [PATCH 3/4] clk/qcom: add driver for sm8250 GCC
Hi Caleb,
On Mon, 8 Apr 2024 at 18:37, Caleb Connolly wrote:
>
> Add a clock driver for the SM8250 SoC. This driver can enable necessary
> clocks for UART, UFS, USB, and MMC.
>
> Signed-off-by: Caleb Connolly
> ---
> drivers/clk/qcom/Kconfig| 8 ++
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clock-qcom.h | 1 +
> drivers/clk/qcom/clock-sm8250.c | 282
>
> 4 files changed, 292 insertions(+)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 6afa62e19879..d4bd8c7e6ba6 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -62,7 +62,15 @@ config CLK_QCOM_SM6115
> Say Y here to enable support for the Global Clock Controller
> on the Snapdragon SM6115 SoC. This driver supports the clocks
> and resets exposed by the GCC hardware block.
>
> +config CLK_QCOM_SM8250
> + bool "Qualcomm SM8250 GCC"
> + select CLK_QCOM
> + help
> + Say Y here to enable support for the Global Clock Controller
> + on the Snapdragon SM8250 SoC. This driver supports the clocks
> + and resets exposed by the GCC hardware block.
> +
> endmenu
>
> endif
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index d38c5a9fb849..f7fc8b9a70f5 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -9,4 +9,5 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
> obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
> obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
> obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
> +obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index ec524157df2b..cc170d8e3f9e 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -9,8 +9,9 @@
>
> #define CFG_CLK_SRC_CXO (0 << 8)
> #define CFG_CLK_SRC_GPLL0 (1 << 8)
> #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
> +#define CFG_CLK_SRC_GPLL9 (2 << 8)
> #define CFG_CLK_SRC_GPLL6 (4 << 8)
> #define CFG_CLK_SRC_GPLL7 (3 << 8)
> #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
> #define CFG_CLK_SRC_MASK (7 << 8)
> diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c
> new file mode 100644
> index ..af10fc116219
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-sm8250.c
> @@ -0,0 +1,282 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Clock drivers for Qualcomm sm8250
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "clock-qcom.h"
> +
> +#define GCC_SE12_UART_RCG_REG 0x184D0
> +#define GCC_SDCC2_APPS_CLK_SRC_REG 0x1400c
> +
> +#define APCS_GPLL0_ENA_VOTE 0x79000
> +#define APCS_GPLL9_STATUS 0x1c000
> +#define APCS_GPLLX_ENA_REG 0x52018
> +
> +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
> +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
> +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf064
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = {
> + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> + F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
> + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
> + F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
> + F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
> + F(5000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
> + F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
> + F(7500, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
> + F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
> + F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
> + F(1, CFG_CLK_SRC_GPLL0, 6, 0, 0),
> + {}
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> + F(40, CFG_CLK_SRC_CXO, 12, 1, 4),
> + F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
> + F(2500, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
> + F(5000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
> + F(1, CFG_CLK_SRC_GPLL0, 6, 0, 0),
> + F(20200, CFG_CLK_SRC_GPLL9, 4, 0, 0),
> + {}
> +};
> +
> +static struct pll_vote_clk gpll9_vote_clk = {
> + .status = APCS_GPLL9_STATUS,
> + .status_bit = BIT(31),
> + .ena_vote = APCS_GPLLX_ENA_REG,
> + .vote_bit = BIT(9),
> +};
> +
> +static ulong sm8250_set_rate(struct clk *clk, ulong rate)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> + const struct freq_tbl *freq;
> +
> + if (clk->id < priv->data->num_clks)
> + debug("%s: %s, requested rate=%ld\n", __func__,
> + priv->data->clks[clk->id].name, rate);
> +
> + switch (clk->id) {
> + case GCC_QUPV3_WRAP1_S4_CLK: /*UART2*/
> + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s4_clk_src,
Re: [PATCH] MAINTAINERS: add Qualcomm mailing list
On Tue, 9 Apr 2024 at 20:32, Caleb Connolly wrote: > > Add the newly created u-boot-qcom mailing list to keep track of Qualcomm > patches. > > Additionally, link to the U-Boot Snapdragon custodian tree. > > Signed-off-by: Caleb Connolly > --- > > Cc: Neil Armstrong > Cc: Sumit Garg > Cc: u-boot@lists.denx.de > --- > MAINTAINERS | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/MAINTAINERS b/MAINTAINERS > index 0462ade4ac60..c0d2b5138fca 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -602,9 +602,11 @@ F: arch/arm/dts/am335x-sancloud* > ARM SNAPDRAGON > M: Caleb Connolly > M: Neil Armstrong > R: Sumit Garg > +L: u-boot-q...@groups.io > S: Maintained > +T: git https://source.denx.de/u-boot/custodians/u-boot-snapdragon.git > F: arch/arm/dts/msm8*.dtsi > F: arch/arm/dts/pm8???.dtsi > F: arch/arm/dts/pms405.dtsi > F: arch/arm/dts/sdm845.dtsi > -- > 2.44.0 >
Re: [PATCH 7/7] dts: sdm845-db845c-u-boot: adjust MMC clocks
Hi Caleb,
On Tue, 9 Apr 2024 at 23:33, Caleb Connolly wrote:
>
> Remove the reference to the xo clock which is on the unsupported rpmhcc
> clock controller. It isn't needed for MMC functionality.
Can it rather be handled via a NOP clock driver for rpmhcc? I suppose
this kind of DT modifications would push us away from upstream DT
compatibility.
-Sumit
>
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/dts/sdm845-db845c-u-boot.dtsi | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi
> b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
> index 906f9faa5451..9e4533e603c5 100644
> --- a/arch/arm/dts/sdm845-db845c-u-boot.dtsi
> +++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
> @@ -6,4 +6,11 @@
> */
> _3p3v_dual {
> regulator-always-on;
> };
> +
> +_2 {
> + /* Remove the unsupported rpmhcc xo clock reference */
> + clocks = < GCC_SDCC2_AHB_CLK>,
> +< GCC_SDCC2_APPS_CLK>;
> + clock-names = "iface", "core";
> +};
>
> --
> 2.44.0
>
Re: [PATCH 3/3] qcom_defconfig: enable SM8550 & SM8650 pinctrl driver
On Fri, 5 Apr 2024 at 13:45, Neil Armstrong wrote: > > Enable the SM8550 & SM8650 pinctrl drivers for Qualcomm defconfig. > > Signed-off-by: Neil Armstrong > --- > configs/qcom_defconfig | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Sumit Garg -Sumit > diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig > index 222db6448ab..a92b6ef7911 100644 > --- a/configs/qcom_defconfig > +++ b/configs/qcom_defconfig > @@ -43,6 +43,8 @@ CONFIG_PHY=y > CONFIG_PINCTRL=y > CONFIG_PINCTRL_QCOM_QCS404=y > CONFIG_PINCTRL_QCOM_SDM845=y > +CONFIG_PINCTRL_QCOM_SM8550=y > +CONFIG_PINCTRL_QCOM_SM8650=y > CONFIG_DM_PMIC=y > CONFIG_PMIC_QCOM=y > CONFIG_SCSI=y > > -- > 2.34.1 >
Re: [PATCH 2/3] pinctrl: qcom: Add SM8650 pinctrl driver
On Fri, 5 Apr 2024 at 13:45, Neil Armstrong wrote:
>
> Add pinctrl driver for the TLMM block found in the SM8650 SoC.
>
> This driver only handles the gpio and qup2_se7 pinmux, and makes sure
> the pinconf applies on SDC2 pins.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/pinctrl/qcom/Kconfig | 7
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-sm8650.c | 75
> +++
> 3 files changed, 83 insertions(+)
>
Acked-by: Sumit Garg
-Sumit
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index f760bbcdd52..e0196a83e60 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -48,6 +48,13 @@ config PINCTRL_QCOM_SM8550
> Say Y here to enable support for pinctrl on the Snapdragon SM8550
> SoC,
> as well as the associated GPIO driver.
>
> +config PINCTRL_QCOM_SM8650
> + bool "Qualcomm SM8650 GCC"
> + select PINCTRL_QCOM
> + help
> + Say Y here to enable support for pinctrl on the Snapdragon SM8650
> SoC,
> + as well as the associated GPIO driver.
> +
> endmenu
>
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 970902e28c8..d83e89ef4f0 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
> obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
> obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
> obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o
> +obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c
> b/drivers/pinctrl/qcom/pinctrl-sm8650.c
> new file mode 100644
> index 000..932132fa4a6
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Qualcomm sm8650 pinctrl
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + *
> + */
> +
> +#include
> +#include
> +
> +#include "pinctrl-qcom.h"
> +
> +#define MAX_PIN_NAME_LEN 32
> +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
> +
> +static const struct pinctrl_function msm_pinctrl_functions[] = {
> + {"qup2_se7", 1},
> + {"gpio", 0},
> +};
> +
> +static const char *sm8650_get_function_name(struct udevice *dev,
> +unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].name;
> +}
> +
> +static const char *sm8650_get_pin_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + static const char *special_pins_names[] = {
> + "ufs_reset",
> + "sdc2_clk",
> + "sdc2_cmd",
> + "sdc2_data",
> + };
> +
> + if (selector >= 210 && selector <= 213)
> + snprintf(pin_name, MAX_PIN_NAME_LEN,
> special_pins_names[selector - 210]);
> + else
> + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
> +
> + return pin_name;
> +}
> +
> +static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin,
> + unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].val;
> +}
> +
> +static struct msm_pinctrl_data sm8650_data = {
> + .pin_data = {
> + .pin_count = 214,
> + .special_pins_start = 210,
> + },
> + .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
> + .get_function_name = sm8650_get_function_name,
> + .get_function_mux = sm8650_get_function_mux,
> + .get_pin_name = sm8650_get_pin_name,
> +};
> +
> +static const struct udevice_id msm_pinctrl_ids[] = {
> + { .compatible = "qcom,sm8650-tlmm", .data = (ulong)_data },
> + { /* Sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_sm8650) = {
> + .name = "pinctrl_sm8650",
> + .id = UCLASS_NOP,
> + .of_match = msm_pinctrl_ids,
> + .ops= _pinctrl_ops,
> + .bind = msm_pinctrl_bind,
> +};
> +
>
> --
> 2.34.1
>
Re: [PATCH 1/3] pinctrl: qcom: Add SM8550 pinctrl driver
On Fri, 5 Apr 2024 at 13:45, Neil Armstrong wrote:
>
> Add pinctrl driver for the TLMM block found in the SM8550 SoC.
>
> This driver only handles the gpio and qup1_se7 pinmux, and makes sure
> the pinconf applies on SDC2 pins.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/pinctrl/qcom/Kconfig | 7
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-sm8550.c | 75
> +++
> 3 files changed, 83 insertions(+)
>
Acked-by: Sumit Garg
-Sumit
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 2fe63981478..f760bbcdd52 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -41,6 +41,13 @@ config PINCTRL_QCOM_SDM845
> Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
> as well as the associated GPIO driver.
>
> +config PINCTRL_QCOM_SM8550
> + bool "Qualcomm SM8550 GCC"
> + select PINCTRL_QCOM
> + help
> + Say Y here to enable support for pinctrl on the Snapdragon SM8550
> SoC,
> + as well as the associated GPIO driver.
> +
> endmenu
>
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 6d9aca6d7b7..970902e28c8 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
> obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
> obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
> obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
> +obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c
> b/drivers/pinctrl/qcom/pinctrl-sm8550.c
> new file mode 100644
> index 000..d9a8a652111
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Qualcomm sm8550 pinctrl
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + *
> + */
> +
> +#include
> +#include
> +
> +#include "pinctrl-qcom.h"
> +
> +#define MAX_PIN_NAME_LEN 32
> +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
> +
> +static const struct pinctrl_function msm_pinctrl_functions[] = {
> + {"qup1_se7", 1},
> + {"gpio", 0},
> +};
> +
> +static const char *sm8550_get_function_name(struct udevice *dev,
> +unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].name;
> +}
> +
> +static const char *sm8550_get_pin_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + static const char *special_pins_names[] = {
> + "ufs_reset",
> + "sdc2_clk",
> + "sdc2_cmd",
> + "sdc2_data",
> + };
> +
> + if (selector >= 210 && selector <= 213)
> + snprintf(pin_name, MAX_PIN_NAME_LEN,
> special_pins_names[selector - 210]);
> + else
> + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
> +
> + return pin_name;
> +}
> +
> +static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin,
> + unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].val;
> +}
> +
> +static struct msm_pinctrl_data sm8550_data = {
> + .pin_data = {
> + .pin_count = 214,
> + .special_pins_start = 210,
> + },
> + .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
> + .get_function_name = sm8550_get_function_name,
> + .get_function_mux = sm8550_get_function_mux,
> + .get_pin_name = sm8550_get_pin_name,
> +};
> +
> +static const struct udevice_id msm_pinctrl_ids[] = {
> + { .compatible = "qcom,sm8550-tlmm", .data = (ulong)_data },
> + { /* Sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_sm8550) = {
> + .name = "pinctrl_sm8550",
> + .id = UCLASS_NOP,
> + .of_match = msm_pinctrl_ids,
> + .ops= _pinctrl_ops,
> + .bind = msm_pinctrl_bind,
> +};
> +
>
> --
> 2.34.1
>
Re: [PATCH 1/3] clk: qcom: Add SM8550 clock driver
On Wed, 10 Apr 2024 at 15:00, wrote:
>
> On 10/04/2024 11:27, Sumit Garg wrote:
> > On Wed, 10 Apr 2024 at 14:46, Neil Armstrong
> > wrote:
> >>
> >> On 10/04/2024 11:13, Sumit Garg wrote:
> >>> Hi Neil,
> >>>
> >>> On Thu, 4 Apr 2024 at 22:16, Neil Armstrong
> >>> wrote:
> >>>>
> >>>> Add the GCC and TCSRCC clock driver for the SM8550 SoC.
> >>>>
> >>>> The GCC driver uses the clk-qcom infrastructure to support GDSCs,
> >>>> Resets and gates. While the TCSRCC is a simpler clock driver which
> >>>> only supports gates.
> >>>>
> >>>> The GCC enable and set_rate callbacks contains some tweaks to
> >>>> setup clocks for Debug UART, SDCard controller and USB.
> >>>
> >>> Okay so these are the peripherals you intend to support to begin with.
> >>>
> >>>>
> >>>> The TCSRCC gates returns the XO frequency, which is used by the
> >>>> Synopsys eUSB2 driver to determine the PHY configuration.
> >>>>
> >>>> Signed-off-by: Neil Armstrong
> >>>> ---
> >>>>drivers/clk/qcom/Kconfig| 8 +
> >>>>drivers/clk/qcom/Makefile | 1 +
> >>>>drivers/clk/qcom/clock-sm8550.c | 335
> >>>>
> >>>>3 files changed, 344 insertions(+)
> >>>>
> >>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >>>> index 8dae635ac2c..c908a3d19c9 100644
> >>>> --- a/drivers/clk/qcom/Kconfig
> >>>> +++ b/drivers/clk/qcom/Kconfig
> >>>> @@ -47,6 +47,14 @@ config CLK_QCOM_SDM845
> >>>> on the Snapdragon 845 SoC. This driver supports the clocks
> >>>> and resets exposed by the GCC hardware block.
> >>>>
> >>>> +config CLK_QCOM_SM8550
> >>>> + bool "Qualcomm SM8550 GCC"
> >>>> + select CLK_QCOM
> >>>> + help
> >>>> + Say Y here to enable support for the Global Clock Controller
> >>>> + on the Snapdragon SM8550 SoC. This driver supports the clocks
> >>>> + and resets exposed by the GCC hardware block.
> >>>> +
> >>>>endmenu
> >>>>
> >>>>endif
> >>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >>>> index cb179fdac58..d9ac5719f49 100644
> >>>> --- a/drivers/clk/qcom/Makefile
> >>>> +++ b/drivers/clk/qcom/Makefile
> >>>> @@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
> >>>>obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
> >>>>obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
> >>>>obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> >>>> +obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
> >>>> diff --git a/drivers/clk/qcom/clock-sm8550.c
> >>>> b/drivers/clk/qcom/clock-sm8550.c
> >>>> new file mode 100644
> >>>> index 000..c0249925cc7
> >>>> --- /dev/null
> >>>> +++ b/drivers/clk/qcom/clock-sm8550.c
> >>>> @@ -0,0 +1,335 @@
> >>>> +// SPDX-License-Identifier: BSD-3-Clause
> >>>> +/*
> >>>> + * Clock drivers for Qualcomm sm8550
> >>>> + *
> >>>> + * (C) Copyright 2024 Linaro Ltd.
> >>>> + */
> >>>> +
> >>>> +#include
> >>>> +#include
> >>>> +#include
> >>>> +#include
> >>>> +#include
> >>>> +#include
> >>>> +#include
> >>>> +#include
> >>>> +#include
> >>>> +
> >>>> +#include "clock-qcom.h"
> >>>> +
> >>>> +/* On-board TCXO, TOFIX get from DT */
> >>>> +#define TCXO_RATE 3840
> >>>> +
> >>>> +/* bi_tcxo_div2 divided after RPMh output */
> >>>> +#define TCXO_DIV2_RATE (TCXO_RATE / 2)
> >>>> +
> >>>> +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = {
> >>>> + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> >>>> + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> >>>> + F(1920, CFG
Re: [PATCH 1/3] clk: qcom: Add SM8550 clock driver
On Wed, 10 Apr 2024 at 14:46, Neil Armstrong wrote:
>
> On 10/04/2024 11:13, Sumit Garg wrote:
> > Hi Neil,
> >
> > On Thu, 4 Apr 2024 at 22:16, Neil Armstrong
> > wrote:
> >>
> >> Add the GCC and TCSRCC clock driver for the SM8550 SoC.
> >>
> >> The GCC driver uses the clk-qcom infrastructure to support GDSCs,
> >> Resets and gates. While the TCSRCC is a simpler clock driver which
> >> only supports gates.
> >>
> >> The GCC enable and set_rate callbacks contains some tweaks to
> >> setup clocks for Debug UART, SDCard controller and USB.
> >
> > Okay so these are the peripherals you intend to support to begin with.
> >
> >>
> >> The TCSRCC gates returns the XO frequency, which is used by the
> >> Synopsys eUSB2 driver to determine the PHY configuration.
> >>
> >> Signed-off-by: Neil Armstrong
> >> ---
> >> drivers/clk/qcom/Kconfig| 8 +
> >> drivers/clk/qcom/Makefile | 1 +
> >> drivers/clk/qcom/clock-sm8550.c | 335
> >>
> >> 3 files changed, 344 insertions(+)
> >>
> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >> index 8dae635ac2c..c908a3d19c9 100644
> >> --- a/drivers/clk/qcom/Kconfig
> >> +++ b/drivers/clk/qcom/Kconfig
> >> @@ -47,6 +47,14 @@ config CLK_QCOM_SDM845
> >>on the Snapdragon 845 SoC. This driver supports the clocks
> >>and resets exposed by the GCC hardware block.
> >>
> >> +config CLK_QCOM_SM8550
> >> + bool "Qualcomm SM8550 GCC"
> >> + select CLK_QCOM
> >> + help
> >> + Say Y here to enable support for the Global Clock Controller
> >> + on the Snapdragon SM8550 SoC. This driver supports the clocks
> >> + and resets exposed by the GCC hardware block.
> >> +
> >> endmenu
> >>
> >> endif
> >> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >> index cb179fdac58..d9ac5719f49 100644
> >> --- a/drivers/clk/qcom/Makefile
> >> +++ b/drivers/clk/qcom/Makefile
> >> @@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
> >> obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
> >> obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
> >> obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> >> +obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
> >> diff --git a/drivers/clk/qcom/clock-sm8550.c
> >> b/drivers/clk/qcom/clock-sm8550.c
> >> new file mode 100644
> >> index 000..c0249925cc7
> >> --- /dev/null
> >> +++ b/drivers/clk/qcom/clock-sm8550.c
> >> @@ -0,0 +1,335 @@
> >> +// SPDX-License-Identifier: BSD-3-Clause
> >> +/*
> >> + * Clock drivers for Qualcomm sm8550
> >> + *
> >> + * (C) Copyright 2024 Linaro Ltd.
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +
> >> +#include "clock-qcom.h"
> >> +
> >> +/* On-board TCXO, TOFIX get from DT */
> >> +#define TCXO_RATE 3840
> >> +
> >> +/* bi_tcxo_div2 divided after RPMh output */
> >> +#define TCXO_DIV2_RATE (TCXO_RATE / 2)
> >> +
> >> +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = {
> >> + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> >> + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> >> + F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
> >> + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
> >> + F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
> >> + F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
> >> + F(5120, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375),
> >> + F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
> >> + F(7500, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
> >> + F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
> >> + F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
> >> + F(1, CFG_CLK_SRC_GPLL0, 6, 0, 0),
> >> + { }
> >> +};
> >> +
> >> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> >> + F(40, CFG_CLK_SRC_CXO, 12, 1, 4),
> >> +
Re: [PATCH 2/3] clk: qcom: Add SM8650 clock driver
On Thu, 4 Apr 2024 at 22:16, Neil Armstrong wrote:
>
> Add the GCC and TCSRCC clock driver for the SM8650 SoC.
>
> The GCC driver uses the clk-qcom infrastructure to support GDSCs,
> Resets and gates. While the TCSRCC is a simpler clock driver which
> only supports gates.
>
> The GCC enable and set_rate callbacks contains some tweaks to
> setup clocks for Debug UART, SDCard controller and USB.
>
Similar comments as on patch#1, we should drop the bits that we don't
intend to support as of now.
-Sumit
> The TCSRCC gates returns the XO frequency, which is used by the
> Synopsys eUSB2 driver to determine the PHY configuration.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/clk/qcom/Kconfig| 8 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clock-sm8650.c | 332
>
> 3 files changed, 341 insertions(+)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index c908a3d19c9..a9216ea30d4 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -55,6 +55,14 @@ config CLK_QCOM_SM8550
> on the Snapdragon SM8550 SoC. This driver supports the clocks
> and resets exposed by the GCC hardware block.
>
> +config CLK_QCOM_SM8650
> + bool "Qualcomm SM8650 GCC"
> + select CLK_QCOM
> + help
> + Say Y here to enable support for the Global Clock Controller
> + on the Snapdragon SM8650 SoC. This driver supports the clocks
> + and resets exposed by the GCC hardware block.
> +
> endmenu
>
> endif
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index d9ac5719f49..3ccb4ffae76 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
> obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
> obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
> +obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o
> diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c
> new file mode 100644
> index 000..0ce83e9b243
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-sm8650.c
> @@ -0,0 +1,332 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Clock drivers for Qualcomm sm8650
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "clock-qcom.h"
> +
> +/* On-board TCXO, TOFIX get from DT */
> +#define TCXO_RATE 3840
> +
> +/* bi_tcxo_div2 divided after RPMh output */
> +#define TCXO_DIV2_RATE (TCXO_RATE / 2)
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = {
> + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> + F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
> + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
> + F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
> + F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
> + F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
> + F(7500, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
> + F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
> + F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
> + F(1, CFG_CLK_SRC_GPLL0, 6, 0, 0),
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> + F(40, CFG_CLK_SRC_CXO, 12, 1, 4),
> + F(2500, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
> + F(1, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
> + /* TOFIX F(20200, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
> + F(6667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
> + F(1, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
> + F(2, CFG_CLK_SRC_GPLL0, 3, 0, 0),
> + F(24000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
> + { }
> +};
> +
> +static ulong sm8650_set_rate(struct clk *clk, ulong rate)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> + const struct freq_tbl *freq;
> +
> + switch (clk->id) {
> + case GCC_QUPV3_WRAP2_S7_CLK: /* UART15 */
> + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s3_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x1e898,
> +freq->pre_div, freq->m, freq->n,
> freq->src, 16);
> + return freq->freq;
> + case GCC_SDCC2_APPS_CLK:
> + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x14018,
> +freq->pre_div, freq->m, freq->n,
> freq->src, 8);
> + return freq->freq;
> + case GCC_USB30_PRIM_MASTER_CLK:
> + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src,
Re: [PATCH 1/3] clk: qcom: Add SM8550 clock driver
Hi Neil,
On Thu, 4 Apr 2024 at 22:16, Neil Armstrong wrote:
>
> Add the GCC and TCSRCC clock driver for the SM8550 SoC.
>
> The GCC driver uses the clk-qcom infrastructure to support GDSCs,
> Resets and gates. While the TCSRCC is a simpler clock driver which
> only supports gates.
>
> The GCC enable and set_rate callbacks contains some tweaks to
> setup clocks for Debug UART, SDCard controller and USB.
Okay so these are the peripherals you intend to support to begin with.
>
> The TCSRCC gates returns the XO frequency, which is used by the
> Synopsys eUSB2 driver to determine the PHY configuration.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/clk/qcom/Kconfig| 8 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clock-sm8550.c | 335
>
> 3 files changed, 344 insertions(+)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 8dae635ac2c..c908a3d19c9 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -47,6 +47,14 @@ config CLK_QCOM_SDM845
> on the Snapdragon 845 SoC. This driver supports the clocks
> and resets exposed by the GCC hardware block.
>
> +config CLK_QCOM_SM8550
> + bool "Qualcomm SM8550 GCC"
> + select CLK_QCOM
> + help
> + Say Y here to enable support for the Global Clock Controller
> + on the Snapdragon SM8550 SoC. This driver supports the clocks
> + and resets exposed by the GCC hardware block.
> +
> endmenu
>
> endif
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index cb179fdac58..d9ac5719f49 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
> obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
> obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
> obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> +obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
> diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
> new file mode 100644
> index 000..c0249925cc7
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-sm8550.c
> @@ -0,0 +1,335 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Clock drivers for Qualcomm sm8550
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "clock-qcom.h"
> +
> +/* On-board TCXO, TOFIX get from DT */
> +#define TCXO_RATE 3840
> +
> +/* bi_tcxo_div2 divided after RPMh output */
> +#define TCXO_DIV2_RATE (TCXO_RATE / 2)
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = {
> + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> + F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
> + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
> + F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
> + F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
> + F(5120, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375),
> + F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
> + F(7500, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
> + F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
> + F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
> + F(1, CFG_CLK_SRC_GPLL0, 6, 0, 0),
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> + F(40, CFG_CLK_SRC_CXO, 12, 1, 4),
> + F(2500, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
> + F(3750, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
> + F(5000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
> + F(1, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
> + /* TOFIX F(20200, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
> + F(6667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
> + F(1, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
> + F(2, CFG_CLK_SRC_GPLL0, 3, 0, 0),
> + F(24000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
> + { }
> +};
> +
> +static ulong sm8550_set_rate(struct clk *clk, ulong rate)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> + const struct freq_tbl *freq;
> +
> + switch (clk->id) {
> + case GCC_QUPV3_WRAP1_S7_CLK: /* UART7 */
> + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s2_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x18898,
> +freq->pre_div, freq->m, freq->n,
> freq->src, 16);
> + return freq->freq;
> + case GCC_SDCC2_APPS_CLK:
> + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x14018,
> +freq->pre_div, freq->m, freq->n,
> freq->src, 8);
> +
Re: [PATCH v3 6/6] board: add support for Schneider HMIBSC board
On Fri, 5 Apr 2024 at 20:16, Stephan Gerhold wrote:
>
> On Fri, Apr 05, 2024 at 02:37:42PM +0530, Sumit Garg wrote:
> > Support for Schneider Electric HMIBSC. Features:
> > - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
> > - 2GiB RAM
> > - 64GiB eMMC, SD slot
> > - WiFi and Bluetooth
> > - 2x Host, 1x Device USB port
> > - HDMI
> > - Discrete TPM2 chip over SPI
> >
> > Features enabled in U-Boot:
> > - RAUC updates
> > - Environment protection
> > - USB based ethernet adaptors
> >
> > Signed-off-by: Sumit Garg
>
> I don't think this is a big deal but this patch would be a bit easier to
> skim over if you move the (unmodified?) import of the Linux
> apq8016-schneider-hmibsc.dts to a separate patch with a clear note in
> the commit message
>
> - where it comes from (link to Linux patch), and
> - that it can be removed again with a future update of the upstream DTs
>in U-Boot (once it is applied upstream at least).
>
> You kind of have that information in the cover letter but I think it
> would be good to have it in the commit message.
Although the general practice in U-Boot is to have the board DTS file
submitted along with board code, if it makes review easier via
separating the unmodified import of the board DTS file then I can do
that.
>
> > ---
> > arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++
> > board/schneider/hmibsc/MAINTAINERS| 6 +
> > configs/hmibsc_defconfig | 86
> > doc/board/index.rst | 1 +
> > doc/board/schneider/hmibsc.rst| 45 ++
> > doc/board/schneider/index.rst | 9 +
> > include/configs/hmibsc.h | 57 +++
> > 7 files changed, 695 insertions(+)
> > create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts
> > create mode 100644 board/schneider/hmibsc/MAINTAINERS
> > create mode 100644 configs/hmibsc_defconfig
> > create mode 100644 doc/board/schneider/hmibsc.rst
> > create mode 100644 doc/board/schneider/index.rst
> > create mode 100644 include/configs/hmibsc.h
> >
> > [...]
> > diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h
> > new file mode 100644
> > index 000..66dfa549ce1
> > --- /dev/null
> > +++ b/include/configs/hmibsc.h
> > @@ -0,0 +1,57 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Board configuration file for HMIBSC
> > + *
> > + * (C) Copyright 2024 Sumit Garg
> > + */
> > +
> > +#ifndef __CONFIGS_HMIBSC_H
> > +#define __CONFIGS_HMIBSC_H
> > +
> > +/* PHY needs a longer aneg time */
> > +#define PHY_ANEG_TIMEOUT 8000
> > +
> > +#define HMIBSC_BOOTCOMMAND \
> > + "setenv devtype mmc; setenv devnum 0; " \
> > + "test -n \"${BOOT_ORDER}\" || setenv BOOT_ORDER \"A B\"; " \
> > + "test -n \"${BOOT_A_LEFT}\" || setenv BOOT_A_LEFT 3; " \
> > + "test -n \"${BOOT_B_LEFT}\" || setenv BOOT_B_LEFT 3; " \
> > + "setenv raucslot; " \
> > + "for BOOT_SLOT in \"${BOOT_ORDER}\"; do " \
> > + " if test \"x${raucslot}\" != \"x\"; then " \
> > + " echo \"skip remaining slots...\"; " \
> > + " elif test \"x${BOOT_SLOT}\" = \"xA\"; then " \
> > + "if test ${BOOT_A_LEFT} -gt 0; then " \
> > + " setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1; " \
> > + " echo \"Found valid RAUC slot A\"; " \
> > + " setenv raucslot \"rauc.slot=A\"; " \
> > + " setenv raucpart A; setenv distro_bootpart 6;" \
> > + "fi; " \
> > + " elif test \"x${BOOT_SLOT}\" = \"xB\"; then " \
> > + "if test ${BOOT_B_LEFT} -gt 0; then " \
> > + " setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1; " \
> > + " echo \"Found valid RAUC slot B\"; " \
> > + " setenv raucslot \"rauc.slot=B\"; " \
> > + " setenv raucpart B; setenv distro_bootpart 7;" \
> > + "fi; " \
> > + " fi; " \
> > + "done; " \
> > + "if test -n \"${raucslot}\"; then " \
> > + " setenv bootargs console=ttyMSM1 root=PARTLABEL=rootfs_${raucpart}
> > rw rootwait ${raucslot};
Re: [RFC PATCH 01/15] DO-NOT-MERGE: dts: upstream: src: Necessary pulls from upstream dts
On Fri, 5 Apr 2024 at 11:17, Jayesh Choudhary wrote: > > Hello Sumit, > > On 05/04/24 10:27, Sumit Garg wrote: > > Hi Jayesh, > > > > On Thu, 4 Apr 2024 at 14:30, Jayesh Choudhary wrote: > >> > >> j722s dts support that needs to be pulled from devicetree-rebasing > >> tree. The whole series depends on this support. > >> > > > > Which devicetree-rebasing tag does this patch depend upon? v6.8-dts > > has already made its way to U-Boot mainline [1]. > > > > [1] > > https://source.denx.de/u-boot/u-boot/-/commit/bc39e06778168a34bb4e0a34fbee4edbde4414d8 > > > > These patches are on top of the next branch (same commit) > The required patches[0][2][3] are in tag v6.9-rc1-dts. > Okay, the next sync is expected to happen when U-Boot next branch opens again and I suppose during that time frame only Linux kernel v6.9 will be released. If you are targeting the U-Boot July release then you have to opt out of OF_UPSTREAM. -Sumit > [0]: > <https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/commit/?id=1339c374a4c10f184d2bb4c6dadd3155f9260599> > [2]: > <https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/commit/?id=4dd9e11aa40f6d7bb2bd4993a8ddf17c935c9686> > [3]: > <https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/commit/?id=ec136bb18fcc85d32787530bc065bd97ee3bba60> > > -Jayesh > > > > -Sumit > > > >> Signed-off-by: Jayesh Choudhary > >> --- > >> dts/upstream/Bindings/arm/ti/k3.yaml | 6 + > >> dts/upstream/src/arm64/ti/k3-j722s-evm.dts | 383 + > >> dts/upstream/src/arm64/ti/k3-j722s.dtsi| 89 + > >> dts/upstream/src/arm64/ti/k3-pinctrl.h | 3 + > >> 4 files changed, 481 insertions(+) > >> create mode 100644 dts/upstream/src/arm64/ti/k3-j722s-evm.dts > >> create mode 100644 dts/upstream/src/arm64/ti/k3-j722s.dtsi > >> > >> diff --git a/dts/upstream/Bindings/arm/ti/k3.yaml > >> b/dts/upstream/Bindings/arm/ti/k3.yaml > >> index c6506bccfe..d526723484 100644 > >> --- a/dts/upstream/Bindings/arm/ti/k3.yaml > >> +++ b/dts/upstream/Bindings/arm/ti/k3.yaml > >> @@ -123,6 +123,12 @@ properties: > >> - ti,j721s2-evm > >> - const: ti,j721s2 > >> > >> + - description: K3 J722S SoC and Boards > >> +items: > >> + - enum: > >> + - ti,j722s-evm > >> + - const: ti,j722s > >> + > >> - description: K3 J784s4 SoC > >> items: > >> - enum: > > [...]
[PATCH v3 6/6] board: add support for Schneider HMIBSC board
Support for Schneider Electric HMIBSC. Features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI
Features enabled in U-Boot:
- RAUC updates
- Environment protection
- USB based ethernet adaptors
Signed-off-by: Sumit Garg
---
arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++
board/schneider/hmibsc/MAINTAINERS| 6 +
configs/hmibsc_defconfig | 86
doc/board/index.rst | 1 +
doc/board/schneider/hmibsc.rst| 45 ++
doc/board/schneider/index.rst | 9 +
include/configs/hmibsc.h | 57 +++
7 files changed, 695 insertions(+)
create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts
create mode 100644 board/schneider/hmibsc/MAINTAINERS
create mode 100644 configs/hmibsc_defconfig
create mode 100644 doc/board/schneider/hmibsc.rst
create mode 100644 doc/board/schneider/index.rst
create mode 100644 include/configs/hmibsc.h
diff --git a/arch/arm/dts/apq8016-schneider-hmibsc.dts
b/arch/arm/dts/apq8016-schneider-hmibsc.dts
new file mode 100644
index 000..75c6137e5a1
--- /dev/null
+++ b/arch/arm/dts/apq8016-schneider-hmibsc.dts
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ model = "Schneider Electric HMIBSC Board";
+ compatible = "schneider,apq8016-hmibsc", "qcom,apq8016";
+
+ aliases {
+ i2c1 = _i2c6;
+ i2c3 = _i2c4;
+ i2c4 = _i2c3;
+ mmc0 = _1; /* eMMC */
+ mmc1 = _2; /* SD card */
+ serial0 = _uart1;
+ serial1 = _uart2;
+ spi0 = _spi5;
+ usid0 = _0;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-0 = <_key_volp_n_default>;
+ pinctrl-names = "default";
+
+ button {
+ label = "Volume Up";
+ linux,code = ;
+ gpios = < 107 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <_mpps_leds>;
+ pinctrl-names = "default";
+
+ led-1 {
+ function = LED_FUNCTION_WLAN;
+ color = ;
+ gpios = <_mpps 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_BLUETOOTH;
+ color = ;
+ gpios = <_mpps 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+ };
+
+ memory@8000 {
+ reg = <0 0x8000 0 0x4000>;
+ };
+
+ reserved-memory {
+ ramoops@bff0 {
+ compatible = "ramoops";
+ reg = <0x0 0xbff0 0x0 0x10>;
+ record-size = <0x2>;
+ console-size = <0x2>;
+ ftrace-size = <0x2>;
+ ecc-size = <16>;
+ };
+ };
+
+ usb-hub {
+ compatible = "smsc,usb3503";
+ reset-gpios = <_gpios 1 GPIO_ACTIVE_LOW>;
+ initial-mode = <1>;
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = < 110 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <_id_default>;
+ pinctrl-names = "default";
+ };
+};
+
+_i2c3 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
+};
+
+_i2c4 {
+ status = "okay";
+
+ adv_bridge: bridge@39 {
+ c
[PATCH v3 5/6] pinctrl: qcom: apq8016: Add GPIO pinctrl function
Add GPIO pinctrl function to enable driving GPIO pins as output low or
high.
Signed-off-by: Sumit Garg
---
drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 1ee8b7db1a2..b14a8921af4 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"gpio", 0},
{"blsp_uart1", 2},
{"blsp_uart2", 2},
};
--
2.34.1
[PATCH v3 4/6] pinctrl: qcom: Add support for driving GPIO pins output
Add support for driving the GPIO pins as output low or high.
Signed-off-by: Sumit Garg
---
drivers/pinctrl/qcom/pinctrl-qcom.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c
b/drivers/pinctrl/qcom/pinctrl-qcom.c
index 909e566acf5..e68971b37ff 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -29,15 +29,24 @@ struct msm_pinctrl_priv {
#define GPIO_CONFIG_REG(priv, x) \
(qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
-#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
-#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_DISABLE BIT(9)
+#define GPIO_IN_OUT_REG(priv, x) \
+ (GPIO_CONFIG_REG(priv, x) + 0x4)
+
+#define TLMM_GPIO_PULL_MASKGENMASK(1, 0)
+#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
+#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
+#define TLMM_GPIO_OUTPUT_MASK BIT(1)
+#define TLMM_GPIO_OE_MASK BIT(9)
+
+/* GPIO register shifts. */
+#define GPIO_OUT_SHIFT 1
static const struct pinconf_param msm_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
+ { "output-high", PIN_CONFIG_OUTPUT, 1, },
+ { "output-low", PIN_CONFIG_OUTPUT, 0, },
};
static int msm_get_functions_count(struct udevice *dev)
@@ -90,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int
pin_selector,
return 0;
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
- TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
+ TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2);
return 0;
}
@@ -117,6 +126,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned
int pin_selector,
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv,
pin_selector),
TLMM_GPIO_PULL_MASK, argument);
break;
+ case PIN_CONFIG_OUTPUT:
+ writel(argument << GPIO_OUT_SHIFT,
+ priv->base + GPIO_IN_OUT_REG(priv, pin_selector));
+ setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
+TLMM_GPIO_OE_MASK);
+ break;
default:
return 0;
}
--
2.34.1
[PATCH v3 3/6] serial_msm: Enable RS232 flow control
SE HMIBSC board debug console requires RS232 flow control, so enable corresponding support if RS232 gpios are present. Reviewed-by: Caleb Connolly Signed-off-by: Sumit Garg --- drivers/serial/serial_msm.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 4de10e75191..3142ecf7362 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -53,10 +53,11 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC -#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 -#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 -#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC +#define MSM_BOOT_UART_DM_8_N_1_MODE0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define MSM_UART_MR1_RX_RDY_CTLBIT(7) DECLARE_GLOBAL_DATA_PTR; @@ -182,7 +183,9 @@ static void uart_dm_init(struct msm_serial_data *priv) mdelay(5); writel(priv->clk_bit_rate, priv->base + UARTDM_CSR); - writel(0x0, priv->base + UARTDM_MR1); + + /* Enable RS232 flow control to support RS232 db9 connector */ + writel(MSM_UART_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1); writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); -- 2.34.1
[PATCH v3 2/6] apq8016: Add support for UART1 clocks and pinmux
SE HMIBSC board uses UART1 as the main debug console, so add
corresponding clocks and pinmux support. Along with that update
instructions to enable clocks for debug UART support.
Signed-off-by: Sumit Garg
---
drivers/clk/qcom/clock-apq8016.c | 38 ++
drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
drivers/serial/serial_msm.c| 11 ++--
3 files changed, 35 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 5a5868169c8..9556b94774a 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -31,7 +31,8 @@
#define BLSP1_AHB_CBCR 0x1008
/* Uart clock control registers */
-#define BLSP1_UART2_BCR(0x3028)
+#define BLSP1_UART1_APPS_CBCR (0x203C)
+#define BLSP1_UART1_APPS_CMD_RCGR (0x2044)
#define BLSP1_UART2_APPS_CBCR (0x302C)
#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
@@ -52,7 +53,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
};
/* SDHCI */
-static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
+static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
{
int div = 15; /* 100MHz default */
@@ -70,20 +71,35 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int
slot, uint rate)
}
/* UART: 115200 */
-int apq8016_clk_init_uart(phys_addr_t base)
+int apq8016_clk_init_uart(phys_addr_t base, unsigned long id)
{
+ u32 cmd_rcgr, apps_cbcr;
+
+ switch (id) {
+ case GCC_BLSP1_UART1_APPS_CLK:
+ cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR;
+ apps_cbcr = BLSP1_UART1_APPS_CBCR;
+ break;
+ case GCC_BLSP1_UART2_APPS_CLK:
+ cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR;
+ apps_cbcr = BLSP1_UART2_APPS_CBCR;
+ break;
+ default:
+ return 0;
+ }
+
/* Enable AHB clock */
clk_enable_vote_clk(base, _blsp1_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */
- clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625,
-CFG_CLK_SRC_GPLL0, 16);
+ clk_rcg_set_rate_mnd(base, cmd_rcgr, 1, 144, 15625, CFG_CLK_SRC_GPLL0,
+16);
/* Vote for gpll0 clock */
clk_enable_gpll0(base, _vote_clk);
/* Enable core clk */
- clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR);
+ clk_enable_cbc(base + apps_cbcr);
return 0;
}
@@ -94,14 +110,12 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong
rate)
switch (clk->id) {
case GCC_SDCC1_APPS_CLK: /* SDC1 */
- return clk_init_sdc(priv, 0, rate);
- break;
+ return apq8016_clk_init_sdc(priv, 0, rate);
case GCC_SDCC2_APPS_CLK: /* SDC2 */
- return clk_init_sdc(priv, 1, rate);
- break;
+ return apq8016_clk_init_sdc(priv, 1, rate);
+ case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */
case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
- return apq8016_clk_init_uart(priv->base);
- break;
+ return apq8016_clk_init_uart(priv->base, clk->id);
default:
return 0;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index a9a00f4b081..1ee8b7db1a2 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"blsp_uart1", 2},
{"blsp_uart2", 2},
};
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index ac4280c6c4c..4de10e75191 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -248,12 +248,17 @@ static struct msm_serial_data init_serial_data = {
#include
/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916
*/
-//int apq8016_clk_init_uart(phys_addr_t gcc_base);
+//int apq8016_clk_init_uart(phys_addr_t gcc_base, unsigned long id);
static inline void _debug_uart_init(void)
{
- /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on
MSM8916 */
- //apq8016_clk_init_uart(0x180);
+ /*
+* Uncomment to turn on UART clocks when debugging U-Boot as aboot
+* on MSM8916. Supported debug UART clock IDs:
+* - db410c: GCC_BLSP1_UART2_APPS_CLK
+* - HMIBSC: GCC_BLSP1_UART1_APPS_CLK
+*/
+ //apq8016_clk_init_uart(0x180, );
uart_dm_init(_serial_data);
}
--
2.34.1
[PATCH v3 1/6] qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default
Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow
ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is
loaded as a first stage bootloader. It leads to secondary CPUs bringup
failure and later causing the Linux kernel to freeze.
So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's
actually required.
Fixes: 059d526af312 ("mach-snapdragon: generalise board support")
Reviewed-by: Caleb Connolly
Signed-off-by: Sumit Garg
---
arch/arm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4cdf08dd695..08ae7e51a6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1088,7 +1088,7 @@ config ARCH_SNAPDRAGON
select BOARD_LATE_INIT
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR
- select LINUX_KERNEL_IMAGE_HEADER
+ select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
imply CMD_DM
config ARCH_SOCFPGA
--
2.34.1
[PATCH v3 0/6] Add SE HMBSC board support
SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major difference from db410c is serial port where HMIBSC board uses UART1 as the debug console with an RS232 port, patch #2 - #5 adds corresponding driver support. Patch #6 adds main HMIBSC board specific bits, features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI Features enabled in U-Boot: - RAUC updates (refer [2] for more details) - Environment protection - USB based ethernet adaptors Feedback is very much welcome. Changes in v3: - Rebased on top of qcom-next [1]. - Collected some review tags. - Incorporated misc. comments from Caleb and Stephen. - Split patch#4 as requested. - Linux HMIBSC board DTS has already been reviewed here [3], I have incorporated that for U-Boot too. Changes in v2: - Rebased on top on qcom-next [1]. - Added patch#1 as a fix for generic qcom board support. - Added patch#4 to enable driving GPIO pins based on pinctrl configuration. This replaces the custom GPIO configuration. - Added proper DTS file for HMIBSC board based on Linux DT pattern. - Merged board support patches into a single patch#5. [1] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-next?ref_type=heads [2] https://rauc.readthedocs.io/en/latest/ [3] https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.g...@linaro.org/ Sumit Garg (6): qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default apq8016: Add support for UART1 clocks and pinmux serial_msm: Enable RS232 flow control pinctrl: qcom: Add support for driving GPIO pins output pinctrl: qcom: apq8016: Add GPIO pinctrl function board: add support for Schneider HMIBSC board arch/arm/Kconfig | 2 +- arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++ board/schneider/hmibsc/MAINTAINERS| 6 + configs/hmibsc_defconfig | 86 doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst| 45 ++ doc/board/schneider/index.rst | 9 + drivers/clk/qcom/clock-apq8016.c | 38 +- drivers/pinctrl/qcom/pinctrl-apq8016.c| 2 + drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- drivers/serial/serial_msm.c | 24 +- include/configs/hmibsc.h | 57 +++ 12 files changed, 760 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h -- 2.34.1
Re: [RFC PATCH 01/15] DO-NOT-MERGE: dts: upstream: src: Necessary pulls from upstream dts
Hi Jayesh,
On Thu, 4 Apr 2024 at 14:30, Jayesh Choudhary wrote:
>
> j722s dts support that needs to be pulled from devicetree-rebasing
> tree. The whole series depends on this support.
>
Which devicetree-rebasing tag does this patch depend upon? v6.8-dts
has already made its way to U-Boot mainline [1].
[1]
https://source.denx.de/u-boot/u-boot/-/commit/bc39e06778168a34bb4e0a34fbee4edbde4414d8
-Sumit
> Signed-off-by: Jayesh Choudhary
> ---
> dts/upstream/Bindings/arm/ti/k3.yaml | 6 +
> dts/upstream/src/arm64/ti/k3-j722s-evm.dts | 383 +
> dts/upstream/src/arm64/ti/k3-j722s.dtsi| 89 +
> dts/upstream/src/arm64/ti/k3-pinctrl.h | 3 +
> 4 files changed, 481 insertions(+)
> create mode 100644 dts/upstream/src/arm64/ti/k3-j722s-evm.dts
> create mode 100644 dts/upstream/src/arm64/ti/k3-j722s.dtsi
>
> diff --git a/dts/upstream/Bindings/arm/ti/k3.yaml
> b/dts/upstream/Bindings/arm/ti/k3.yaml
> index c6506bccfe..d526723484 100644
> --- a/dts/upstream/Bindings/arm/ti/k3.yaml
> +++ b/dts/upstream/Bindings/arm/ti/k3.yaml
> @@ -123,6 +123,12 @@ properties:
>- ti,j721s2-evm
>- const: ti,j721s2
>
> + - description: K3 J722S SoC and Boards
> +items:
> + - enum:
> + - ti,j722s-evm
> + - const: ti,j722s
> +
>- description: K3 J784s4 SoC
> items:
>- enum:
> diff --git a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
> b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
> new file mode 100644
> index 00..cee3a8661d
> --- /dev/null
> +++ b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
> @@ -0,0 +1,383 @@
> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
> +/*
> + * Device Tree file for the J722S EVM
> + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + *
> + * Schematics: https://www.ti.com/lit/zip/sprr495
> + */
> +
> +/dts-v1/;
> +
> +#include
> +#include "k3-j722s.dtsi"
> +
> +/ {
> + compatible = "ti,j722s-evm", "ti,j722s";
> + model = "Texas Instruments J722S EVM";
> +
> + aliases {
> + serial0 = _uart0;
> + serial2 = _uart0;
> + mmc0 =
> + mmc1 =
> + };
> +
> + chosen {
> + stdout-path = _uart0;
> + };
> +
> + memory@8000 {
> + /* 8G RAM */
> + reg = <0x 0x8000 0x 0x8000>,
> + <0x0008 0x8000 0x0001 0x8000>;
> + device_type = "memory";
> + bootph-pre-ram;
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + secure_tfa_ddr: tfa@9e78 {
> + reg = <0x00 0x9e78 0x00 0x8>;
> + no-map;
> + };
> +
> + secure_ddr: optee@9e80 {
> + reg = <0x00 0x9e80 0x00 0x0180>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_memory_region: r5f-memory@a010 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa010 0x00 0xf0>;
> + no-map;
> + };
> +
> + };
> +
> + vmain_pd: regulator-0 {
> + /* TPS65988 PD CONTROLLER OUTPUT */
> + compatible = "regulator-fixed";
> + regulator-name = "vmain_pd";
> + regulator-min-microvolt = <500>;
> + regulator-max-microvolt = <500>;
> + regulator-always-on;
> + regulator-boot-on;
> + bootph-all;
> + };
> +
> + vsys_5v0: regulator-vsys5v0 {
> + /* Output of LM5140 */
> + compatible = "regulator-fixed";
> + regulator-name = "vsys_5v0";
> + regulator-min-microvolt = <500>;
> + regulator-max-microvolt = <500>;
> + vin-supply = <_pd>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_mmc1: regulator-mmc1 {
> + /* TPS22918DBVR */
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_mmc1";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = < 15 GPIO_ACTIVE_HIGH>;
> + bootph-all;
> + };
> +
> + vdd_sd_dv: regulator-TLV71033 {
> + compatible = "regulator-gpio";
> + regulator-name = "tlv71033";
> + pinctrl-names = "default";
> + pinctrl-0 = <_sd_dv_pins_default>;
> + regulator-min-microvolt = <180>;
> +
Re: [PATCH v1] verdin-imx8mm/verdin-imx8mp: move imx verdins to OF_UPSTREAM
On Wed, 3 Apr 2024 at 12:51, Marcel Ziswiler wrote:
>
> From: Marcel Ziswiler
>
> Move verdin-imx8mm and verdin-imx8mp to OF_UPSTREAM:
> - handle the fact that dtbs now have a 'freescale/' prefix
> - imply OF_UPSTREAM
> - remove redundant files from arch/arm/dts leaving only the
> *-u-boot.dtsi files
> - update MAINTAINERS files
>
> Signed-off-by: Marcel Ziswiler
>
> ---
>
> arch/arm/dts/Makefile |2 -
> arch/arm/dts/imx8mm-verdin-dev.dtsi | 160 ---
> arch/arm/dts/imx8mm-verdin-wifi-dev.dts | 18 -
> arch/arm/dts/imx8mm-verdin-wifi.dtsi| 94 --
> arch/arm/dts/imx8mm-verdin.dtsi | 1319 -
> arch/arm/dts/imx8mp-verdin-dev.dtsi | 165 ---
> arch/arm/dts/imx8mp-verdin-wifi-dev.dts | 18 -
> arch/arm/dts/imx8mp-verdin-wifi.dtsi| 87 --
> arch/arm/dts/imx8mp-verdin.dtsi | 1438 ---
> arch/arm/mach-imx/imx8m/Kconfig |2 +
> board/toradex/verdin-imx8mm/MAINTAINERS |4 -
> board/toradex/verdin-imx8mp/MAINTAINERS |4 -
> configs/verdin-imx8mm_defconfig |2 +-
> configs/verdin-imx8mp_defconfig |2 +-
> 14 files changed, 4 insertions(+), 3311 deletions(-)
> delete mode 100644 arch/arm/dts/imx8mm-verdin-dev.dtsi
> delete mode 100644 arch/arm/dts/imx8mm-verdin-wifi-dev.dts
> delete mode 100644 arch/arm/dts/imx8mm-verdin-wifi.dtsi
> delete mode 100644 arch/arm/dts/imx8mm-verdin.dtsi
> delete mode 100644 arch/arm/dts/imx8mp-verdin-dev.dtsi
> delete mode 100644 arch/arm/dts/imx8mp-verdin-wifi-dev.dts
> delete mode 100644 arch/arm/dts/imx8mp-verdin-wifi.dtsi
> delete mode 100644 arch/arm/dts/imx8mp-verdin.dtsi
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 18fedc16740..cd8aa0b4143 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1082,7 +1082,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
> imx8mm-phg.dtb \
> imx8mm-phyboard-polis-rdk.dtb \
> imx8mm-phygate-tauri-l.dtb \
> - imx8mm-verdin-wifi-dev.dtb \
> imx8mn-bsh-smm-s2.dtb \
> imx8mn-bsh-smm-s2pro.dtb \
> imx8mq-cm.dtb \
> @@ -1104,7 +1103,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
> imx8mp-icore-mx8mp-edimm2.2.dtb \
> imx8mp-msc-sm2s.dtb \
> imx8mp-phyboard-pollux-rdk.dtb \
> - imx8mp-verdin-wifi-dev.dtb \
> imx8mq-pico-pi.dtb \
> imx8mq-kontron-pitx-imx8m.dtb \
> imx8mq-librem5-r4.dtb
> diff --git a/arch/arm/dts/imx8mm-verdin-dev.dtsi
> b/arch/arm/dts/imx8mm-verdin-dev.dtsi
> deleted file mode 100644
> index 3c4b8ca125e..000
> --- a/arch/arm/dts/imx8mm-verdin-dev.dtsi
> +++ /dev/null
> @@ -1,160 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> -/*
> - * Copyright 2022 Toradex
> - */
> -
> -/ {
> - sound_card: sound-card {
> - compatible = "simple-audio-card";
> - simple-audio-card,bitclock-master = <_master>;
> - simple-audio-card,format = "i2s";
> - simple-audio-card,frame-master = <_master>;
> - simple-audio-card,mclk-fs = <256>;
> - simple-audio-card,name = "imx8mm-nau8822";
> - simple-audio-card,routing =
> - "Headphones", "LHP",
> - "Headphones", "RHP",
> - "Speaker", "LSPK",
> - "Speaker", "RSPK",
> - "Line Out", "AUXOUT1",
> - "Line Out", "AUXOUT2",
> - "LAUX", "Line In",
> - "RAUX", "Line In",
> - "LMICP", "Mic In",
> - "RMICP", "Mic In";
> - simple-audio-card,widgets =
> - "Headphones", "Headphones",
> - "Line Out", "Line Out",
> - "Speaker", "Speaker",
> - "Microphone", "Mic In",
> - "Line", "Line In";
> -
> - dailink_master: simple-audio-card,codec {
> - clocks = < IMX8MM_CLK_SAI2_ROOT>;
> - sound-dai = <_1a>;
> - };
> -
> - simple-audio-card,cpu {
> - sound-dai = <>;
> - };
>
Re: [PATCH 1/3] arm64: imx: imx8mp-beacon: Migrate to OF_UPSTREAM
On Thu, 4 Apr 2024 at 08:29, Adam Ford wrote:
>
> The imx8mp-beacon boards can migrate to OF_UPSTREAM which also
> allows for the removal the device tree files.
>
> Signed-off-by: Adam Ford
>
For the series:
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index d85a33055c..04ffa1f165 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1095,7 +1095,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
> imx8mn-beacon-kit.dtb \
> imx8mq-mnt-reform2.dtb \
> imx8mq-phanbell.dtb \
> - imx8mp-beacon-kit.dtb \
> imx8mp-data-modul-edm-sbc.dtb \
> imx8mp-dhcom-som-overlay-rev100.dtbo \
> imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
> diff --git a/arch/arm/dts/imx8mp-beacon-kit.dts
> b/arch/arm/dts/imx8mp-beacon-kit.dts
> deleted file mode 100644
> index a08057410b..00
> --- a/arch/arm/dts/imx8mp-beacon-kit.dts
> +++ /dev/null
> @@ -1,783 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> -/*
> - * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
> - */
> -
> -/dts-v1/;
> -
> -#include
> -#include
> -#include "imx8mp.dtsi"
> -#include "imx8mp-beacon-som.dtsi"
> -
> -/ {
> - model = "Beacon EmbeddedWorks i.MX8MPlus Development kit";
> - compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
> -
> - aliases {
> - ethernet0 =
> - ethernet1 =
> - };
> -
> - chosen {
> - stdout-path =
> - };
> -
> - clk_xtal25: clock-xtal25 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <2500>;
> - };
> -
> - connector {
> - compatible = "usb-c-connector";
> - label = "USB-C";
> - data-role = "dual";
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> -
> - hs_ep: endpoint {
> - remote-endpoint = <_hs_ep>;
> - };
> - };
> - port@1 {
> - reg = <1>;
> -
> - ss_ep: endpoint {
> - remote-endpoint = <_in_ep>;
> - };
> - };
> - };
> - };
> -
> - dmic_codec: dmic-codec {
> - compatible = "dmic-codec";
> - num-channels = <1>;
> - #sound-dai-cells = <0>;
> - };
> -
> - gpio-keys {
> - compatible = "gpio-keys";
> - autorepeat;
> -
> - button-0 {
> - label = "btn0";
> - linux,code = ;
> - gpios = <_1 12 (GPIO_ACTIVE_LOW |
> GPIO_PULL_UP)>;
> - wakeup-source;
> - };
> -
> - button-1 {
> - label = "btn1";
> - linux,code = ;
> - gpios = <_1 13 (GPIO_ACTIVE_LOW |
> GPIO_PULL_UP)>;
> - wakeup-source;
> - };
> -
> - button-2 {
> - label = "btn2";
> - linux,code = ;
> - gpios = <_1 14 (GPIO_ACTIVE_LOW |
> GPIO_PULL_UP)>;
> - wakeup-source;
> - };
> -
> - button-3 {
> - label = "btn3";
> - linux,code = ;
> - gpios = <_1 15 (GPIO_ACTIVE_LOW |
> GPIO_PULL_UP)>;
> - wakeup-source;
> - };
> - };
> -
> - bridge-connector {
> - compatible = "hdmi-connector";
> - type = "a";
> -
> - port {
> - hdmi_con: endpoint {
> - remote-endpoint = <_out>;
> - };
> - };
> - };
> -
> - leds {
> - compatible = "gpio-leds";
> - pinctrl-names = "
Re: [PATCH v1] verdin-am62: move verdin am62 to OF_UPSTREAM
On Wed, 3 Apr 2024 at 12:45, Marcel Ziswiler wrote:
>
> From: Marcel Ziswiler
>
> Move verdin-am62 to OF_UPSTREAM:
> - handle the fact that dtbs now have a 'ti/' prefix
> - imply OF_UPSTREAM
> - remove redundant files from arch/arm/dts leaving only the
> *-u-boot.dtsi files
> - update MAINTAINERS file
>
> Signed-off-by: Marcel Ziswiler
>
> ---
>
> arch/arm/dts/Makefile |1 -
> arch/arm/dts/k3-am62-verdin-dev.dtsi | 240 ---
> arch/arm/dts/k3-am62-verdin-wifi.dtsi | 45 -
> arch/arm/dts/k3-am62-verdin.dtsi | 1443 -
> .../dts/k3-am625-verdin-wifi-dev-binman.dtsi |2 +-
> arch/arm/dts/k3-am625-verdin-wifi-dev.dts | 22 -
> arch/arm/mach-k3/am62x/Kconfig|1 +
> board/toradex/verdin-am62/MAINTAINERS |4 -
> configs/verdin-am62_a53_defconfig |2 +-
> 9 files changed, 3 insertions(+), 1757 deletions(-)
> delete mode 100644 arch/arm/dts/k3-am62-verdin-dev.dtsi
> delete mode 100644 arch/arm/dts/k3-am62-verdin-wifi.dtsi
> delete mode 100644 arch/arm/dts/k3-am62-verdin.dtsi
> delete mode 100644 arch/arm/dts/k3-am625-verdin-wifi-dev.dts
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 7b7788f7550..18fedc16740 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1416,7 +1416,6 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
> k3-am625-r5-sk.dtb \
> k3-am625-beagleplay.dtb \
> k3-am625-r5-beagleplay.dtb \
> - k3-am625-verdin-wifi-dev.dtb \
> k3-am625-verdin-r5.dtb \
> k3-am625-phyboard-lyra-rdk.dtb \
> k3-am625-r5-phycore-som-2gb.dtb
> diff --git a/arch/arm/dts/k3-am62-verdin-dev.dtsi
> b/arch/arm/dts/k3-am62-verdin-dev.dtsi
> deleted file mode 100644
> index 6701cb8974b..000
> --- a/arch/arm/dts/k3-am62-verdin-dev.dtsi
> +++ /dev/null
> @@ -1,240 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> -/*
> - * Copyright 2023 Toradex
> - *
> - * Common dtsi for Verdin AM62 SoM on Development carrier board
> - *
> - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
> - *
> https://www.toradex.com/products/carrier-board/verdin-development-board-kit
> - */
> -
> -/ {
> - sound {
> - compatible = "simple-audio-card";
> - simple-audio-card,bitclock-master = <_dai>;
> - simple-audio-card,format = "i2s";
> - simple-audio-card,frame-master = <_dai>;
> - simple-audio-card,name = "verdin-nau8822";
> - simple-audio-card,routing =
> - "Headphones", "LHP",
> - "Headphones", "RHP",
> - "Speaker", "LSPK",
> - "Speaker", "RSPK",
> - "Line Out", "AUXOUT1",
> - "Line Out", "AUXOUT2",
> - "LAUX", "Line In",
> - "RAUX", "Line In",
> - "LMICP", "Mic In",
> - "RMICP", "Mic In";
> - simple-audio-card,widgets =
> - "Headphones", "Headphones",
> - "Line Out", "Line Out",
> - "Speaker", "Speaker",
> - "Microphone", "Mic In",
> - "Line", "Line In";
> -
> - codec_dai: simple-audio-card,codec {
> - clocks = <_refclk1>;
> - sound-dai = <_1a>;
> - };
> -
> - simple-audio-card,cpu {
> - sound-dai = <>;
> - };
> - };
> -};
> -
> -/* Verdin ETHs */
> - {
> - pinctrl-names = "default";
> - pinctrl-0 = <_rgmii1>, <_rgmii2>;
> - status = "okay";
> -};
> -
> -/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
> -_mdio {
> - status = "okay";
> -
> - cpsw3g_phy1: ethernet-phy@7 {
> - compatible = "ethernet-phy-ieee802.3-c22";
> -
Re: [PATCH v5 03/16] phy: qcom: Add SNPS femto v2 USB HS phy
On Tue, 2 Apr 2024 at 15:37, Caleb Connolly wrote:
>
> Hi Sumit,
>
> On 01/04/2024 06:46, Sumit Garg wrote:
> > On Thu, 28 Mar 2024 at 23:29, Caleb Connolly
> > wrote:
> >>
> >> From: Bhupesh Sharma
> >>
> >> Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy"
> >> driver, notable the SM8250 SoC which will gain U-Boot support in
> >> upcoming patches.
> >>
> >> Introduce a driver based on the Linux driver.
> >>
> >> Signed-off-by: Bhupesh Sharma
> >> [code cleanup, align symbol names with Linux, switch to clk/reset_bulk
> >> APIs]
> >> Signed-off-by: Caleb Connolly
> >> ---
> >> drivers/phy/qcom/Kconfig | 8 ++
> >> drivers/phy/qcom/Makefile | 1 +
> >> drivers/phy/qcom/phy-qcom-snps-femto-v2.c | 207
> >> ++
> >> 3 files changed, 216 insertions(+)
> >>
> ...
> >> diff --git a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
> >> b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
> >> new file mode 100644
> >> index ..58eb01972402
> >> --- /dev/null
> >> +++ b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
> ...
> >> +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32
> >> offset,
> >> + u32 mask, u32 val)
> >> +{
> >> + u32 reg;
> >> +
> >> + reg = readl_relaxed(base + offset);
> >> +
> >> + reg &= ~mask;
> >> + reg |= val & mask;
> >> + writel_relaxed(reg, base + offset);
> >> +
> >> + /* Ensure above write is completed */
> >> + readl_relaxed(base + offset);
> >
> > It looks like you have missed addressing comments related to this API.
> > Again, why do we need this special handling in U-Boot? Why not just
> > clrsetbits_le32()?
>
> I have tried to find more info about this, but from what I can tell it's
> important (my guess is that it's a weird bus arbitration thing with the
> QMP phy's).
>
> If I replace this with clrsetbits_le32() then my SM8250 board crashdumps
> while probing USB. So it is needed (and I'm wondering now if I ought to
> switch back to this for the dwc3 qcom glue as well).
Strange, probably it's due to some strict device memory ordering
rules. If you can add some reasoning in comments for this API then
feel free to add:
Acked-by: Sumit Garg
-Sumit
Re: [PATCH 00/31] rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs
On Mon, 1 Apr 2024 at 16:34, Jonas Karlman wrote:
>
> On 2024-04-01 12:53, Sumit Garg wrote:
> > On Mon, 1 Apr 2024 at 15:31, Jonas Karlman wrote:
> >>
> >> On 2024-04-01 11:45, Jonas Karlman wrote:
> >>> Hi Sumit,
> >>>
> >>> On 2024-04-01 10:52, Sumit Garg wrote:
> >>>> Hi Jonas,
> >>>>
> >>>> On Mon, 1 Apr 2024 at 01:59, Jonas Karlman wrote:
> >>>>>
> >>>>> This series adds support for new clocks used in linux v6.8 device trees,
> >>>>> enables use of FIT signature check for checksum validation and fixes
> >>>>> loading FIT from SD-card when loading FIT from eMMC fails.
> >>>>>
> >>>>> After this series it should be possible to move RK3399 boards to use
> >>>>> OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
> >>>>>
> >>>>
> >>>> Thanks for putting this effort together. A switch to v6.8 tag for
> >>>> OF_UPSTREAM will happen as part of patch [1]. So if you want to save
> >>>> further effort then you can just rebase with a switch to OF_UPSTREAM
> >>>> once that patch [1] lands in next.
> >>>
> >>> Because this is a jump of device tree files from v5.14-rc1 to v6.8,
> >>> reviewability and being able to cherry-pick these changes to my
> >>> rk3xxx-2024.04 branch, I think it is much more appropriate to first sync
> >>> everything to v6.8 and then in a separate series move to OF_UPSTREAM.
> >>> Else it can be very hard to understand some of the changes that has been
> >>> and was needed to be made to u-boot.dtsi files.
> >>
> >> Also forgot to mention that these synced DT files still contains some
> >> minor modification in #include dtsi paths of files that is shared
> >> between rk3288 (armv7) and rk3399 (armv8),
> >
> > I can only see rockchip-u-boot.dtsi being shared which should be
> > handled automatically. Is there anything else I am missing here?
>
> The following is a diff of arch/arm/dts rk3399 DTs after this series
> compared to fully synced v6.8.
This is due to the different DTS directory structure within U-Boot.
With OF_UPSTREAM, these modifications aren't required anymore.
>
> Also the content of cros-ec-keyboard.dtsi was excluded in this sync
> because it initially caused compile issues.
I suppose that's due to missing #include
for cros-ec-keyboard.dtsi. Once
you enable OF_UPSTREAM then let me know if you encounter such issues.
-Sumit
>
> diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi
> index d90fe4d40d48..789fd0dcc88b 100644
> --- a/arch/arm/dts/rk3399-gru.dtsi
> +++ b/arch/arm/dts/rk3399-gru.dtsi
> @@ -684,8 +684,8 @@ ap_i2c_audio: {
> status = "okay";
> };
>
> -#include
> -#include
> +#include
> +#include
>
> {
> /*
> diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10.dts
> b/arch/arm/dts/rk3399pro-rock-pi-n10.dts
> index bf026786fa92..c58fb7658d7a 100644
> --- a/arch/arm/dts/rk3399pro-rock-pi-n10.dts
> +++ b/arch/arm/dts/rk3399pro-rock-pi-n10.dts
> @@ -8,7 +8,7 @@
> /dts-v1/;
> #include "rk3399.dtsi"
> #include "rk3399-opp.dtsi"
> -#include
> +#include
> #include "rk3399pro-vmarc-som.dtsi"
>
> / {
>
> Regards,
> Jonas
>
> >
> > -Sumit
>
Re: [PATCH 00/31] rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs
On Mon, 1 Apr 2024 at 15:54, Jonas Karlman wrote: > > On 2024-04-01 12:08, Sumit Garg wrote: > > On Mon, 1 Apr 2024 at 15:15, Jonas Karlman wrote: > >> > >> Hi Sumit, > >> > >> On 2024-04-01 10:52, Sumit Garg wrote: > >>> Hi Jonas, > >>> > >>> On Mon, 1 Apr 2024 at 01:59, Jonas Karlman wrote: > >>>> > >>>> This series adds support for new clocks used in linux v6.8 device trees, > >>>> enables use of FIT signature check for checksum validation and fixes > >>>> loading FIT from SD-card when loading FIT from eMMC fails. > >>>> > >>>> After this series it should be possible to move RK3399 boards to use > >>>> OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag. > >>>> > >>> > >>> Thanks for putting this effort together. A switch to v6.8 tag for > >>> OF_UPSTREAM will happen as part of patch [1]. So if you want to save > >>> further effort then you can just rebase with a switch to OF_UPSTREAM > >>> once that patch [1] lands in next. > >> > >> Because this is a jump of device tree files from v5.14-rc1 to v6.8, > >> reviewability and being able to cherry-pick these changes to my > >> rk3xxx-2024.04 branch, I think it is much more appropriate to first sync > >> everything to v6.8 and then in a separate series move to OF_UPSTREAM. > >> Else it can be very hard to understand some of the changes that has been > >> and was needed to be made to u-boot.dtsi files. > > > > That's fair given it's a long pending DT sync. > > > >> > >> Reviewability is one of the shortcomings with a switch to OF_UPSTREAM. > > > > I suppose the reasoning behind this thinking can be that people are > > used to reviewing DTs alongside driver changes. However, these patches > > aren't actual DT changes but rather DT imports which IMHO is a > > distraction for the reviewer. The actual DT can be looked into > > dts/upstream/ directory while reviewing the changes. > > Things like following was easier to spot when reviewing DT syncs: > - A property that U-Boot depends on gets removed, as in [1]. That seems to be due to DT bindings compliance check where DT bindings are the ABI. Although it is unfortunate due to dependency on legacy DT, now we have the same dtbs_check in U-Boot too: $ make _defconfig $ make -j`nproc` dtbs_check This shall keep U-Boot in compliance with DT bindings and help avoid such dependencies. > - Some DT changes can break changes that has been made to u-boot.dtsi > files, e.g. a symbol to a node is no longer available in upstream but > referenced in u-boot.dtsi files (happened in this series). Node names aren't a DT ABI so we should expect some changes there. > - Changes in DT may require a workaround in a u-boot.dtsi file. > - u-boot.dtsi contains workarounds that has not yet been upstream but > can be removed in a future DT sync. Agree, we should try to minimize modifications via u-boot.dtsi especially all the bootph* related properties should be posted upstream. > - Driver incompatibilities due to initial driver imported from vendor > ended up not fully compatible with upstream linux driver / dt-binding. Given all the above and the big jump in DT sync for Rockchip platforms, I am fine with the transition being step by step. -Sumit > > [2] > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=4d08b19629495b29601991d09d07865694c25199 >
Re: [PATCH 00/31] rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs
On Mon, 1 Apr 2024 at 15:31, Jonas Karlman wrote: > > On 2024-04-01 11:45, Jonas Karlman wrote: > > Hi Sumit, > > > > On 2024-04-01 10:52, Sumit Garg wrote: > >> Hi Jonas, > >> > >> On Mon, 1 Apr 2024 at 01:59, Jonas Karlman wrote: > >>> > >>> This series adds support for new clocks used in linux v6.8 device trees, > >>> enables use of FIT signature check for checksum validation and fixes > >>> loading FIT from SD-card when loading FIT from eMMC fails. > >>> > >>> After this series it should be possible to move RK3399 boards to use > >>> OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag. > >>> > >> > >> Thanks for putting this effort together. A switch to v6.8 tag for > >> OF_UPSTREAM will happen as part of patch [1]. So if you want to save > >> further effort then you can just rebase with a switch to OF_UPSTREAM > >> once that patch [1] lands in next. > > > > Because this is a jump of device tree files from v5.14-rc1 to v6.8, > > reviewability and being able to cherry-pick these changes to my > > rk3xxx-2024.04 branch, I think it is much more appropriate to first sync > > everything to v6.8 and then in a separate series move to OF_UPSTREAM. > > Else it can be very hard to understand some of the changes that has been > > and was needed to be made to u-boot.dtsi files. > > Also forgot to mention that these synced DT files still contains some > minor modification in #include dtsi paths of files that is shared > between rk3288 (armv7) and rk3399 (armv8), I can only see rockchip-u-boot.dtsi being shared which should be handled automatically. Is there anything else I am missing here? -Sumit
Re: [PATCH 00/31] rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs
On Mon, 1 Apr 2024 at 15:15, Jonas Karlman wrote: > > Hi Sumit, > > On 2024-04-01 10:52, Sumit Garg wrote: > > Hi Jonas, > > > > On Mon, 1 Apr 2024 at 01:59, Jonas Karlman wrote: > >> > >> This series adds support for new clocks used in linux v6.8 device trees, > >> enables use of FIT signature check for checksum validation and fixes > >> loading FIT from SD-card when loading FIT from eMMC fails. > >> > >> After this series it should be possible to move RK3399 boards to use > >> OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag. > >> > > > > Thanks for putting this effort together. A switch to v6.8 tag for > > OF_UPSTREAM will happen as part of patch [1]. So if you want to save > > further effort then you can just rebase with a switch to OF_UPSTREAM > > once that patch [1] lands in next. > > Because this is a jump of device tree files from v5.14-rc1 to v6.8, > reviewability and being able to cherry-pick these changes to my > rk3xxx-2024.04 branch, I think it is much more appropriate to first sync > everything to v6.8 and then in a separate series move to OF_UPSTREAM. > Else it can be very hard to understand some of the changes that has been > and was needed to be made to u-boot.dtsi files. That's fair given it's a long pending DT sync. > > Reviewability is one of the shortcomings with a switch to OF_UPSTREAM. I suppose the reasoning behind this thinking can be that people are used to reviewing DTs alongside driver changes. However, these patches aren't actual DT changes but rather DT imports which IMHO is a distraction for the reviewer. The actual DT can be looked into dts/upstream/ directory while reviewing the changes. -Sumit > > Regards, > Jonas > > > > > [1] https://lists.denx.de/pipermail/u-boot/2024-March/549611.html > > > > -Sumit > > > >> I have runtime tested this series on following devices: > >> - 96boards Rock960 > >> - Khadas Edge Captain > >> - Pine64 PineBook Pro > >> - Pine64 RockPro64 > >> - Radxa ROCK 4C+ > >> - Radxa ROCK 4SE > >> - Radxa ROCK Pi 4A > >> - Radxa ROCK Pi 4B+ > >> > >> This series depends on the following series: > >> - Enable booting from SPI flash on ROCK Pi 4 [1] > >> - rockchip: spl: Cache boot source id for later use [2] > >> > >> A copy of this series and all its depends can be found at [3] > >> > >> [1] https://patchwork.ozlabs.org/cover/1912469/ > >> [2] https://patchwork.ozlabs.org/cover/1915071/ > >> [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1 > >> > >> Jonas Karlman (31): > >> rockchip: rk3399-gru: Fix max SPL size on bob and kevin > >> rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr > >> rockchip: rk3399: Sort imply statements alphabetically > >> rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation > >> rockchip: rk3399: Enable random generator on all boards > >> rockchip: rk3399: Imply support for GbE PHY > >> rockchip: rk3399: Enable DT overlay support on all boards > >> rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options > >> rockchip: rk3399: Add a default spl-boot-order prop > >> rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC > >> clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC > >> clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock > >> clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock > >> clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support > >> rockchip: rk3399: Sync soc device tree from linux v6.8 > >> rockchip: rk3399-gru: Sync device tree from linux v6.8 > >> rockchip: rk3399-puma: Sync DT from linux v6.8 > >> rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 > >> rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 > >> rockchip: rk3399-leez: Sync device tree from linux v6.8 > >> rockchip: rk3399-evb: Sync device tree from linux v6.8 > >> rockchip: rk3399-firefly: Sync device tree from linux v6.8 > >> rockchip: rk3399-orangepi: Sync device tree from linux v6.8 > >> rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 > >> rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 > >> rockchip: rk3399-rock960: Sync device tree from linux v6.8 > >> rockchip: rk3399-khadas: Sync device tree from linux v6.8 > >> rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 > >> ro
Re: [PATCH 11/31] clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC
On Mon, 1 Apr 2024 at 02:01, Jonas Karlman wrote: > > Sync rk3399-cru.h with one from linux v6.2+ and fix use of the > SCLK_DDRCLK name that was only used by U-Boot. > > Signed-off-by: Jonas Karlman > --- > arch/arm/dts/rk3399-u-boot.dtsi| 2 +- > drivers/clk/rockchip/clk_rk3399.c | 2 +- > include/dt-bindings/clock/rk3399-cru.h | 30 ++ You shouldn't need to sync this header but rather just drop it which will lead to ./dts/upstream/include/dt-bindings/clock/rk3399-cru.h being included automatically. Similarly you should be able to drop all other duplicate headers as demonstrated by this [1] patch-set. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=399954 -Sumit > 3 files changed, 18 insertions(+), 16 deletions(-) > > diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi > index 69e6b808a69b..adb64d17e040 100644 > --- a/arch/arm/dts/rk3399-u-boot.dtsi > +++ b/arch/arm/dts/rk3399-u-boot.dtsi > @@ -44,7 +44,7 @@ > compatible = "rockchip,rk3399-dmc"; > devfreq-events = <>; > interrupts = ; > - clocks = < SCLK_DDRCLK>; > + clocks = < SCLK_DDRC>; > clock-names = "dmc_clk"; > reg = <0x0 0xffa8 0x0 0x0800 >0x0 0xffa80800 0x0 0x1800 > diff --git a/drivers/clk/rockchip/clk_rk3399.c > b/drivers/clk/rockchip/clk_rk3399.c > index 80f65a237e8e..f0ce54067f8c 100644 > --- a/drivers/clk/rockchip/clk_rk3399.c > +++ b/drivers/clk/rockchip/clk_rk3399.c > @@ -1049,7 +1049,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong > rate) > * return 0 to satisfy clk_set_defaults during device probe. > */ > return 0; > - case SCLK_DDRCLK: > + case SCLK_DDRC: > ret = rk3399_ddr_set_clk(priv->cru, rate); > break; > case PCLK_EFUSE1024NS: > diff --git a/include/dt-bindings/clock/rk3399-cru.h > b/include/dt-bindings/clock/rk3399-cru.h > index 211faf8fa891..39169d94a44e 100644 > --- a/include/dt-bindings/clock/rk3399-cru.h > +++ b/include/dt-bindings/clock/rk3399-cru.h > @@ -1,6 +1,7 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > /* > * Copyright (c) 2016 Rockchip Electronics Co. Ltd. > + * Author: Xing Zheng > */ > > #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H > @@ -121,16 +122,17 @@ > #define SCLK_DPHY_RX0_CFG 165 > #define SCLK_RMII_SRC 166 > #define SCLK_PCIEPHY_REF100M 167 > -#define SCLK_USBPHY0_480M_SRC 168 > -#define SCLK_USBPHY1_480M_SRC 169 > -#define SCLK_DDRCLK170 > -#define SCLK_TESTOUT2 171 > +#define SCLK_DDRC 168 > +#define SCLK_TESTCLKOUT1 169 > +#define SCLK_TESTCLKOUT2 170 > > #define DCLK_VOP0 180 > #define DCLK_VOP1 181 > #define DCLK_VOP0_DIV 182 > #define DCLK_VOP1_DIV 183 > #define DCLK_M0_PERILP 184 > +#define DCLK_VOP0_FRAC 185 > +#define DCLK_VOP1_FRAC 186 > > #define FCLK_CM0S 190 > > @@ -545,8 +547,8 @@ > #define SRST_H_PERILP0 171 > #define SRST_H_PERILP0_NOC 172 > #define SRST_ROM 173 > -#define SRST_CRYPTO_S 174 > -#define SRST_CRYPTO_M 175 > +#define SRST_CRYPTO0_S 174 > +#define SRST_CRYPTO0_M 175 > > /* cru_softrst_con11 */ > #define SRST_P_DCF 176 > @@ -554,7 +556,7 @@ > #define SRST_CM0S 178 > #define SRST_CM0S_DBG 179 > #define SRST_CM0S_PO 180 > -#define SRST_CRYPTO181 > +#define SRST_CRYPTO0 181 > #define SRST_P_PERILP1_SGRF182 > #define SRST_P_PERILP1_GRF 183 > #define SRST_CRYPTO1_S 184 > @@ -592,13 +594,13 @@ > #define SRST_P_SPI0214 > #define SRST_P_SPI1215 > #define SRST_P_SPI2216 > -#define SRST_P_SPI4217 > -#define SRST_P_SPI5218 > +#define SRST_P_SPI3217 > +#define SRST_P_SPI4218 > #define SRST_SPI0 219 > #define SRST_SPI1 220 > #define SRST_SPI2 221 > -#define SRST_SPI4 222 > -#define SRST_SPI5 223 > +#define SRST_SPI3 222 > +#define SRST_SPI4 223 > > /* cru_softrst_con14 */ > #define SRST_I2S0_8CH 224 > @@ -720,8 +722,8 @@ > #define SRST_H_CM0S_NOC3 > #define SRST_DBG_CM0S 4 > #define
Re: [PATCH 00/31] rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs
Hi Jonas, On Mon, 1 Apr 2024 at 01:59, Jonas Karlman wrote: > > This series adds support for new clocks used in linux v6.8 device trees, > enables use of FIT signature check for checksum validation and fixes > loading FIT from SD-card when loading FIT from eMMC fails. > > After this series it should be possible to move RK3399 boards to use > OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag. > Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next. [1] https://lists.denx.de/pipermail/u-boot/2024-March/549611.html -Sumit > I have runtime tested this series on following devices: > - 96boards Rock960 > - Khadas Edge Captain > - Pine64 PineBook Pro > - Pine64 RockPro64 > - Radxa ROCK 4C+ > - Radxa ROCK 4SE > - Radxa ROCK Pi 4A > - Radxa ROCK Pi 4B+ > > This series depends on the following series: > - Enable booting from SPI flash on ROCK Pi 4 [1] > - rockchip: spl: Cache boot source id for later use [2] > > A copy of this series and all its depends can be found at [3] > > [1] https://patchwork.ozlabs.org/cover/1912469/ > [2] https://patchwork.ozlabs.org/cover/1915071/ > [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1 > > Jonas Karlman (31): > rockchip: rk3399-gru: Fix max SPL size on bob and kevin > rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr > rockchip: rk3399: Sort imply statements alphabetically > rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation > rockchip: rk3399: Enable random generator on all boards > rockchip: rk3399: Imply support for GbE PHY > rockchip: rk3399: Enable DT overlay support on all boards > rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options > rockchip: rk3399: Add a default spl-boot-order prop > rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC > clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC > clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock > clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock > clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support > rockchip: rk3399: Sync soc device tree from linux v6.8 > rockchip: rk3399-gru: Sync device tree from linux v6.8 > rockchip: rk3399-puma: Sync DT from linux v6.8 > rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 > rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 > rockchip: rk3399-leez: Sync device tree from linux v6.8 > rockchip: rk3399-evb: Sync device tree from linux v6.8 > rockchip: rk3399-firefly: Sync device tree from linux v6.8 > rockchip: rk3399-orangepi: Sync device tree from linux v6.8 > rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 > rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 > rockchip: rk3399-rock960: Sync device tree from linux v6.8 > rockchip: rk3399-khadas: Sync device tree from linux v6.8 > rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 > rockchip: rk3399-rockpro64: Sync device tree from linux v6.8 > rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8 > rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8 > > arch/arm/dts/rk3288-vmarc-som.dtsi| 48 +++ > arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - > arch/arm/dts/rk3399-eaidk-610.dts | 3 +- > arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +- > arch/arm/dts/rk3399-evb.dts | 3 +- > arch/arm/dts/rk3399-ficus-u-boot.dtsi | 10 +- > arch/arm/dts/rk3399-ficus.dts | 4 + > arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 - > arch/arm/dts/rk3399-firefly.dts | 17 +- > arch/arm/dts/rk3399-gru-bob.dts | 8 +- > arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++- > arch/arm/dts/rk3399-gru-kevin.dts | 3 +- > arch/arm/dts/rk3399-gru-u-boot.dtsi | 34 ++- > arch/arm/dts/rk3399-gru.dtsi | 52 +++- > arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 + > arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 7 +- > arch/arm/dts/rk3399-khadas-edge-v.dts | 4 + > arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +- > arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 - > arch/arm/dts/rk3399-leez-p710.dts | 8 +- > arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- > arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +--- > arch/arm/dts/rk3399-nanopi-m4b.dts| 2 +- > arch/arm/dts/rk3399-nanopi-r4s.dts| 4 +- > arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 18 +- > arch/arm/dts/rk3399-nanopi4.dtsi | 7 +- > arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- > arch/arm/dts/rk3399-opp.dtsi | 6 +- >
Re: [PATCH v5 15/16] qcom_defconfig: enable USB
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote: > > Enable support for the DWC3 USB controller and required dependencies for > Qualcomm boards, specifically the DB845c: > * IOMMU / SMMU > * USB high-speed PHYs > * Mass storage and ACM gadgets > > Signed-off-by: Caleb Connolly > --- > configs/qcom_defconfig | 52 > -- > 1 file changed, 29 insertions(+), 23 deletions(-) > Reviewed-by: Sumit Garg -Sumit > diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig > index 8c4402e8f780..1abb57345ff1 100644 > --- a/configs/qcom_defconfig > +++ b/configs/qcom_defconfig > @@ -17,10 +17,16 @@ CONFIG_LOG_MAX_LEVEL=9 > CONFIG_LOG_DEFAULT_LEVEL=4 > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > CONFIG_CMD_BOOTMENU=y > +CONFIG_CMD_EEPROM=y > +CONFIG_SYS_I2C_EEPROM_BUS=2 > +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 > +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 > +# CONFIG_CMD_BIND is not set > CONFIG_CMD_CLK=y > CONFIG_CMD_GPIO=y > +CONFIG_CMD_I2C=y > CONFIG_CMD_MMC=y > CONFIG_CMD_UFS=y > CONFIG_CMD_USB=y > CONFIG_CMD_CAT=y > @@ -32,20 +38,39 @@ CONFIG_CLK=y > CONFIG_CLK_QCOM_QCS404=y > CONFIG_CLK_QCOM_SDM845=y > CONFIG_MSM_GPIO=y > CONFIG_QCOM_PMIC_GPIO=y > +CONFIG_DM_I2C=y > +CONFIG_SYS_I2C_QUP=y > +CONFIG_I2C_MUX=y > CONFIG_DM_KEYBOARD=y > CONFIG_BUTTON_KEYBOARD=y > +CONFIG_IOMMU=y > +CONFIG_QCOM_HYP_SMMU=y > +CONFIG_MISC=y > +CONFIG_NVMEM=y > +CONFIG_I2C_EEPROM=y > CONFIG_MMC_HS200_SUPPORT=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ADMA=y > CONFIG_MMC_SDHCI_MSM=y > +CONFIG_PHY_MICREL=y > +CONFIG_PHY_MICREL_KSZ90X1=y > +CONFIG_DM_MDIO=y > +CONFIG_DM_ETH_PHY=y > +CONFIG_DWC_ETH_QOS=y > +CONFIG_DWC_ETH_QOS_QCOM=y > +CONFIG_RGMII=y > CONFIG_PHY=y > +CONFIG_PHY_QCOM_QUSB2=y > +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y > CONFIG_PINCTRL=y > CONFIG_PINCTRL_QCOM_QCS404=y > CONFIG_PINCTRL_QCOM_SDM845=y > CONFIG_DM_PMIC=y > CONFIG_PMIC_QCOM=y > +CONFIG_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > CONFIG_SCSI=y > CONFIG_MSM_SERIAL=y > CONFIG_MSM_GENI_SERIAL=y > CONFIG_SPMI_MSM=y > @@ -54,8 +79,12 @@ CONFIG_SYSINFO_SMBIOS=y > CONFIG_USB=y > CONFIG_USB_XHCI_HCD=y > CONFIG_USB_XHCI_DWC3=y > CONFIG_USB_DWC3=y > +CONFIG_USB_DWC3_GENERIC=y > +CONFIG_USB_GADGET=y > +CONFIG_USB_GADGET_DOWNLOAD=y > +CONFIG_USB_FUNCTION_MASS_STORAGE=y > CONFIG_UFS=y > CONFIG_VIDEO=y > # CONFIG_VIDEO_FONT_8X16 is not set > CONFIG_VIDEO_FONT_16X32=y > @@ -64,27 +93,4 @@ CONFIG_NO_FB_CLEAR=y > CONFIG_VIDEO_SIMPLE=y > CONFIG_HEXDUMP=y > # CONFIG_GENERATE_SMBIOS_TABLE is not set > CONFIG_LMB_MAX_REGIONS=64 > -CONFIG_CMD_DHCP=y > -CONFIG_CMD_EEPROM=y > -CONFIG_CMD_I2C=y > -CONFIG_CMD_PING=y > -CONFIG_DM_ETH=y > -CONFIG_DM_ETH_PHY=y > -CONFIG_DM_MDIO=y > -CONFIG_DWC_ETH_QOS=y > -CONFIG_DWC_ETH_QOS_QCOM=y > -CONFIG_RGMII=y > -CONFIG_PHY_MICREL=y > -CONFIG_PHY_MICREL_KSZ90X1=y > -CONFIG_MISC=y > -CONFIG_NVMEM=y > -CONFIG_DM_I2C=y > -CONFIG_I2C_SUPPORT=y > -CONFIG_I2C_MUX=y > -CONFIG_I2C_EEPROM=y > -CONFIG_SYS_I2C=y > -CONFIG_SYS_I2C_QUP=y > -CONFIG_SYS_I2C_EEPROM_BUS=2 > -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 > -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 > > -- > 2.44.0 >
Re: [PATCH v5 14/16] qcom_defconfig: enable livetree
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote: > > Qualcomm FDTs are on the larger size, and with the addition of DT > modifications during board_init() it makes sense to enable OF_LIVE > globally. The cost of building the tree should be offset by the > increased efficiency at which we can walk it. > > Some rough measurements with CONFIG_BOOTSTAGE suggests that this might > add 0.1-0.2ms to the boot-to-console time. However the reset-to-reset > timer difference is in the range of 0.5ms so this could just be noise. > > Suffice to say, no significant slow down. > > Reviewed-by: Neil Armstrong > Signed-off-by: Caleb Connolly > --- > configs/qcom_defconfig | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Sumit Garg -Sumit > diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig > index cbc612b44bd9..8c4402e8f780 100644 > --- a/configs/qcom_defconfig > +++ b/configs/qcom_defconfig > @@ -25,8 +25,9 @@ CONFIG_CMD_UFS=y > CONFIG_CMD_USB=y > CONFIG_CMD_CAT=y > CONFIG_CMD_BMP=y > CONFIG_CMD_LOG=y > +CONFIG_OF_LIVE=y > CONFIG_BUTTON_QCOM_PMIC=y > CONFIG_CLK=y > CONFIG_CLK_QCOM_QCS404=y > CONFIG_CLK_QCOM_SDM845=y > > -- > 2.44.0 >
Re: [PATCH v5 13/16] dts: sdm845-db845c: add u-boot fixups
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> The USB VBUS supply for the type-A port is enabled via a GPIO regulator.
> This is incorrectly modelled in Linux where only the PCIe dependency is
> expressed. The correct way to handle this will be through a
> usb-connector node, but for now we'll just mark the regulator as
> always-on so that it will be enabled automatically during boot.
>
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/dts/sdm845-db845c-u-boot.dtsi | 9 +
> 1 file changed, 9 insertions(+)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi
> b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
> new file mode 100644
> index ..906f9faa5451
> --- /dev/null
> +++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/* Needed for Linux to boot from USB, otherwise if PCIe driver is not in
> initramfs
> + * the VBUS supply will never get turned on.
> + *
> https://lore.kernel.org/linux-arm-msm/20240320122515.3243711-1-caleb.conno...@linaro.org/
> + */
> +_3p3v_dual {
> + regulator-always-on;
> +};
>
> --
> 2.44.0
>
Re: [PATCH v5 12/16] mach-snapdragon: call regulators_enable_boot_on()
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> Make sure we power on any boot-on or always-on regulators. These are
> used for peripherals like USB on some platforms.
>
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/mach-snapdragon/board.c | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/mach-snapdragon/board.c
> b/arch/arm/mach-snapdragon/board.c
> index 65e4c61e866a..3d5994c87886 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -15,8 +15,9 @@
> #include
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> #include
> @@ -160,8 +161,9 @@ void __weak qcom_board_init(void)
> }
>
> int board_init(void)
> {
> + regulators_enable_boot_on(false);
> show_psci_version();
> qcom_of_fixup_nodes();
> qcom_board_init();
> return 0;
>
> --
> 2.44.0
>
Re: [PATCH v5 11/16] mach-snapdragon: fixup power-domains
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> We don't support the RPM(h)PD power domains in U-Boot, and we don't need
> to - the necessary resources are on, and we aren't going to enter any
> low power modes.
>
> We could try using a no-op device, but this requires adding a compatible
> for every platform, and just pollutes the driver model. So instead let's
> just remove every "power-domains" property that references the RPM(h)pd
> power controller. This takes <1ms as we're using OF_LIVE.
>
> Of note, this only applies to drivers which are loading post-relocation.
> Drivers loaded pre-reloc that reference the rpm(h)pd still need
> DM_FLAG_DEFAULT_PD_CTRL_OFF in their flags.
>
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/mach-snapdragon/of_fixup.c | 32 ++++
> 1 file changed, 32 insertions(+)
>
Acked-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/mach-snapdragon/of_fixup.c
> b/arch/arm/mach-snapdragon/of_fixup.c
> index 4fdfed2dff16..3f7ac227bd09 100644
> --- a/arch/arm/mach-snapdragon/of_fixup.c
> +++ b/arch/arm/mach-snapdragon/of_fixup.c
> @@ -21,8 +21,9 @@
> #include
> #include
> #include
> #include
> +#include
> #include
>
> /* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3
> * USB controllers. Rather than requiring source level DT changes, we fix up
> @@ -109,8 +110,38 @@ static void fixup_usb_nodes(void)
> log_warning("Failed to fixup node %s: %d\n",
> glue_np->name, ret);
> }
> }
>
> +/* Remove all references to the rpmhpd device */
> +static void fixup_power_domains(void)
> +{
> + struct device_node *pd = NULL, *np = NULL;
> + struct property *prop;
> + const __be32 *val;
> +
> + /* All Qualcomm platforms name the rpm(h)pd "power-controller" */
> + for_each_of_allnodes(pd) {
> + if (pd->name && !strcmp("power-controller", pd->name))
> + break;
> + }
> +
> + /* Sanity check that this is indeed a power domain controller */
> + if (!of_find_property(pd, "#power-domain-cells", NULL)) {
> + log_err("Found power-controller but it doesn't have
> #power-domain-cells\n");
> + return;
> + }
> +
> + /* Remove all references to the power domain controller */
> + for_each_of_allnodes(np) {
> + if (!(prop = of_find_property(np, "power-domains", NULL)))
> + continue;
> +
> + val = prop->value;
> + if (val[0] == cpu_to_fdt32(pd->phandle))
> + of_remove_property(np, prop);
> + }
> +}
> +
> #define time_call(func, ...) \
> do { \
> u64 start = timer_get_us(); \
> func(__VA_ARGS__); \
> @@ -119,5 +150,6 @@ static void fixup_usb_nodes(void)
>
> void qcom_of_fixup_nodes(void)
> {
> time_call(fixup_usb_nodes);
> + time_call(fixup_power_domains);
> }
>
> --
> 2.44.0
>
Re: [PATCH v5 10/16] mach-snapdragon: fixup USB nodes
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> We don't support USB super-speed in U-Boot yet, we lack the SS PHY
> drivers, however from my testing even with a PHY driver there seem to be
> other issues when talking to super-speed peripherals.
>
> In pursuit of maintaining upstream DT compatibility, and simplifying
> porting for new devices, let's implement the DT fixups necessary to
> configure USB in high-speed only mode at runtime. The pattern is
> identical for all Qualcomm boards that use the Synaptics DWC3
> controller:
>
> * Add an additional property on the Qualcomm wrapper node
> * Remove the super-speed phy phandle and phy-name entries.
>
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/mach-snapdragon/Makefile| 1 +
> arch/arm/mach-snapdragon/board.c | 3 +
> arch/arm/mach-snapdragon/of_fixup.c | 123
> +++
> arch/arm/mach-snapdragon/qcom-priv.h | 20 ++
> 4 files changed, 147 insertions(+)
>
Acked-by: Sumit Garg
-Sumit
> diff --git a/arch/arm/mach-snapdragon/Makefile
> b/arch/arm/mach-snapdragon/Makefile
> index 857171e593da..7a4495c8108f 100644
> --- a/arch/arm/mach-snapdragon/Makefile
> +++ b/arch/arm/mach-snapdragon/Makefile
> @@ -2,4 +2,5 @@
> #
> # (C) Copyright 2015 Mateusz Kulikowski
>
> obj-y += board.o
> +obj-$(CONFIG_OF_LIVE) += of_fixup.o
> diff --git a/arch/arm/mach-snapdragon/board.c
> b/arch/arm/mach-snapdragon/board.c
> index 6f762fc948bf..65e4c61e866a 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -27,8 +27,10 @@
> #include
> #include
> #include
>
> +#include "qcom-priv.h"
> +
> DECLARE_GLOBAL_DATA_PTR;
>
> static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
>
> @@ -159,8 +161,9 @@ void __weak qcom_board_init(void)
>
> int board_init(void)
> {
> show_psci_version();
> + qcom_of_fixup_nodes();
> qcom_board_init();
> return 0;
> }
>
> diff --git a/arch/arm/mach-snapdragon/of_fixup.c
> b/arch/arm/mach-snapdragon/of_fixup.c
> new file mode 100644
> index ..4fdfed2dff16
> --- /dev/null
> +++ b/arch/arm/mach-snapdragon/of_fixup.c
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * OF_LIVE devicetree fixup.
> + *
> + * This file implements runtime fixups for Qualcomm DT to improve
> + * compatibility with U-Boot. This includes adjusting the USB nodes
> + * to only use USB high-speed, as well as remapping volume buttons
> + * to behave as up/down for navigating U-Boot.
> + *
> + * We use OF_LIVE for this rather than early FDT fixup for a couple
> + * of reasons: it has a much nicer API, is most likely more efficient,
> + * and our changes are only applied to U-Boot. This allows us to use a
> + * DT designed for Linux, run U-Boot with a modified version, and then
> + * boot Linux with the original FDT.
> + *
> + * Copyright (c) 2024 Linaro Ltd.
> + * Author: Caleb Connolly
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3
> + * USB controllers. Rather than requiring source level DT changes, we fix up
> + * DT here. This improves compatibility with upstream DT and simplifies the
> + * porting process for new devices.
> + */
> +static int fixup_qcom_dwc3(struct device_node *glue_np)
> +{
> + struct device_node *dwc3;
> + int ret, len, hsphy_idx = 1;
> + const __be32 *phandles;
> + const char *second_phy_name;
> +
> + debug("Fixing up %s\n", glue_np->name);
> +
> + /* Tell the glue driver to configure the wrapper for high-speed only
> operation */
> + ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL);
> + if (ret) {
> + log_err("Failed to add property
> 'qcom,select-utmi-as-pipe-clk': %d\n", ret);
> + return ret;
> + }
> +
> + /* Find the DWC3 node itself */
> + dwc3 = of_find_compatible_node(glue_np, NULL, "snps,dwc3");
> + if (!dwc3) {
> + log_err("Failed to find dwc3 node\n");
> + return -ENOENT;
> + }
> +
> + phandles = of_get_property(dwc3, "phys", );
> + len /= sizeof(*phandles);
> + if (len == 1) {
> + log_debug("Only one phy, not a superspeed controller\n");
> + return 0;
> + }
> +
> + /* Figure out if the superspeed phy is present and if so then which
> phy
Re: [PATCH v5 03/16] phy: qcom: Add SNPS femto v2 USB HS phy
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> From: Bhupesh Sharma
>
> Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy"
> driver, notable the SM8250 SoC which will gain U-Boot support in
> upcoming patches.
>
> Introduce a driver based on the Linux driver.
>
> Signed-off-by: Bhupesh Sharma
> [code cleanup, align symbol names with Linux, switch to clk/reset_bulk APIs]
> Signed-off-by: Caleb Connolly
> ---
> drivers/phy/qcom/Kconfig | 8 ++
> drivers/phy/qcom/Makefile | 1 +
> drivers/phy/qcom/phy-qcom-snps-femto-v2.c | 207
> ++
> 3 files changed, 216 insertions(+)
>
> diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
> index 361dfb6e1126..b9fe608c2798 100644
> --- a/drivers/phy/qcom/Kconfig
> +++ b/drivers/phy/qcom/Kconfig
> @@ -18,8 +18,16 @@ config PHY_QCOM_QUSB2
> help
> Enable this to support the Super-Speed USB transceiver on various
> Qualcomm chipsets.
>
> +config PHY_QCOM_USB_SNPS_FEMTO_V2
> + tristate "Qualcomm SNPS FEMTO USB HS PHY v2"
> + depends on PHY && ARCH_SNAPDRAGON
> + help
> + Enable this to support the Qualcomm Synopsys DesignWare Core 7nm
> + High-Speed PHY driver. This driver supports the Hi-Speed PHY which
> + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
> +
> config PHY_QCOM_USB_HS_28NM
> tristate "Qualcomm 28nm High-Speed PHY"
> depends on PHY && ARCH_SNAPDRAGON
> help
> diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
> index f6af985666a4..5f4db4a53788 100644
> --- a/drivers/phy/qcom/Makefile
> +++ b/drivers/phy/qcom/Makefile
> @@ -1,5 +1,6 @@
> obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
> obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
> obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
> +obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o
> obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
> obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
> diff --git a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
> b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
> new file mode 100644
> index ..58eb01972402
> --- /dev/null
> +++ b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
> @@ -0,0 +1,207 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + * Copyright (C) 2023 Bhupesh Sharma
> + *
> + * Based on Linux driver
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
> +#define SLEEPM BIT(0)
> +#define OPMODE_MASK GENMASK(4, 3)
> +#define OPMODE_NORMAL (0x00)
> +#define OPMODE_NONDRIVING BIT(3)
> +#define TERMSEL BIT(5)
> +
> +#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
> +#define POR BIT(1)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
> +#define SIDDQ BIT(2)
> +#define RETENABLEN BIT(3)
> +#define FSEL_MASK GENMASK(6, 4)
> +#define FSEL_DEFAULT (0x3 << 4)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
> +#define VBUSVLDEXTSEL0 BIT(4)
> +#define PLLBTUNE BIT(5)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
> +#define VREGBYPASS BIT(0)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
> +#define VBUSVLDEXT0 BIT(0)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
> +#define USB2_AUTO_RESUME BIT(0)
> +#define USB2_SUSPEND_N BIT(2)
> +#define USB2_SUSPEND_N_SEL BIT(3)
> +
> +#define USB2_PHY_USB_PHY_CFG0 (0x94)
> +#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
> +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
> +
> +#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
> +#define REFCLK_SEL_MASK GENMASK(1, 0)
> +#define REFCLK_SEL_DEFAULT (0x2 << 0)
> +
> +struct qcom_snps_hsphy {
> + void __iomem *base;
> + struct clk_bulk clks;
> + struct reset_ctl_bulk resets;
> +};
> +
> +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
> + u32 mask, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl_relaxed(base + offset);
> +
> + reg &= ~mask;
> + reg |= val & mask;
> + writel_relaxed(reg, base + offset);
> +
> + /* Ensure above write is completed */
> + readl_relaxed(base + offset);
It looks like you have missed addressing comments related to this API.
Again, why do we need this special handling in U-Boot? Why not just
clrsetbits_le32()?
-Sumit
> +}
> +
> +static int qcom_snps_hsphy_usb_init(struct phy *phy)
> +{
> + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev);
> +
> + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0,
> + UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
> + UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
> +
Re: [PATCH v5 02/16] phy: qcom: add Qualcomm QUSB2 USB PHY driver
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote: > > From: Bhupesh Sharma > > The Snapdragon 845 and several other Qualcomm SoCs feature this > USB high-speed phy. Add a driver for it based on the Linux driver, with > support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain > support in U-Boot in future patches. > > Signed-off-by: Bhupesh Sharma > [code cleanup, switch to clk_bulk] > Signed-off-by: Caleb Connolly > --- > drivers/phy/qcom/Kconfig | 7 + > drivers/phy/qcom/Makefile | 1 + > drivers/phy/qcom/phy-qcom-qusb2.c | 429 > ++ > 3 files changed, 437 insertions(+) > Acked-by: Sumit Garg -Sumit > diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig > index f4ca174805a4..361dfb6e1126 100644 > --- a/drivers/phy/qcom/Kconfig > +++ b/drivers/phy/qcom/Kconfig > @@ -11,8 +11,15 @@ config PHY_QCOM_IPQ4019_USB > depends on PHY && ARCH_IPQ40XX > help > Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. > > +config PHY_QCOM_QUSB2 > + tristate "Qualcomm USB QUSB2 PHY driver" > + depends on PHY && ARCH_SNAPDRAGON > + help > + Enable this to support the Super-Speed USB transceiver on various > + Qualcomm chipsets. > + > config PHY_QCOM_USB_HS_28NM > tristate "Qualcomm 28nm High-Speed PHY" > depends on PHY && ARCH_SNAPDRAGON > help > diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile > index 2113f178c0c7..f6af985666a4 100644 > --- a/drivers/phy/qcom/Makefile > +++ b/drivers/phy/qcom/Makefile > @@ -1,4 +1,5 @@ > obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o > obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o > +obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o > obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o > obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o > diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c > b/drivers/phy/qcom/phy-qcom-qusb2.c > new file mode 100644 > index ..c91ba18c4ab1 > --- /dev/null > +++ b/drivers/phy/qcom/phy-qcom-qusb2.c > @@ -0,0 +1,429 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2023 Bhupesh Sharma > + * > + * Based on Linux driver > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define QUSB2PHY_PLL 0x0 > +#define QUSB2PHY_PLL_TEST 0x04 > +#define CLK_REF_SEL BIT(7) > + > +#define QUSB2PHY_PLL_TUNE 0x08 > +#define QUSB2PHY_PLL_USER_CTL1 0x0c > +#define QUSB2PHY_PLL_USER_CTL2 0x10 > +#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c > +#define QUSB2PHY_PLL_PWR_CTRL 0x18 > + > +/* QUSB2PHY_PLL_STATUS register bits */ > +#define PLL_LOCKED BIT(5) > + > +/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ > +#define CORE_READY_STATUS BIT(0) > + > +/* QUSB2PHY_PORT_POWERDOWN register bits */ > +#define CLAMP_N_EN BIT(5) > +#define FREEZIO_N BIT(1) > +#define POWER_DOWN BIT(0) > + > +/* QUSB2PHY_PWR_CTRL1 register bits */ > +#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) > +#define PWR_CTRL1_CLAMP_N_EN BIT(1) > + > +#define QUSB2PHY_REFCLK_ENABLE BIT(0) > + > +#define PHY_CLK_SCHEME_SEL BIT(0) > + > +/* QUSB2PHY_INTR_CTRL register bits */ > +#define DMSE_INTR_HIGH_SEL BIT(4) > +#define DPSE_INTR_HIGH_SEL BIT(3) > +#define CHG_DET_INTR_EN BIT(2) > +#define DMSE_INTR_EN BIT(1) > +#define DPSE_INTR_EN BIT(0) > + > +/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ > +#define CORE_PLL_EN_FROM_RESET BIT(4) > +#define CORE_RESET BIT(5) > +#define CORE_RESET_MUX BIT(6) > + > +/* QUSB2PHY_IMP_CTRL1 register bits */ > +#define IMP_RES_OFFSET_MASK GENMASK(5, 0) > +#define IMP_RES_OFFSET_SHIFT 0x0 > + > +/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ > +#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) > +#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 > + > +/* QUSB2PHY_CHG_CONTROL_2 register bits */ > +#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) > +#define CHG_CTRL2_OFFSET_SHIFT 0x4 > + > +/* QUSB2PHY_PORT_TUNE1 register bits */ > +#define HSTX_TRIM_MASK GENMASK(7, 4) > +#define HSTX_TRIM_SHIFT 0x4 > +#define PREEMPH_WIDTH_HALF_BIT BIT(2) > +#define PREEMPHASIS_EN_MASK GENMASK(1, 0) > +#define PREEMPHASIS_EN_SHIFT 0x0 > + > +/* QUSB2PHY_PORT_TUNE2 register bits */ > +#define HSDISC_TRIM_MASK GENMASK(1, 0) > +#define HSDISC_TRIM_SHIFT 0x0 > + > +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 > +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c > +#define QUSB2PHY_PLL_CMODE 0x2c > +#define QUSB2PHY_PLL_LOCK_DELAY 0x184 > +#d
Re: [PATCH v2] arm: dts: kirkwood: Enable upstream DT on Kirkwood boards
od.dtsi and
> dts/upstream/src/arm/marvell/kirkwood.dtsi differ
> Files arch/arm/dts/kirkwood-synology.dtsi and
> dts/upstream/src/arm/marvell/kirkwood-synology.dtsi differ
>
> 3. DTS files that are newer in upstream (safe to take with regression test)
>
> Files arch/arm/dts/kirkwood-nsa310s.dts and
> dts/upstream/src/arm/marvell/kirkwood-nsa310s.dts differ
>
> 4. DTSI files that have additional PCI-related bindings in upstream (safe to
> take with regression test)
>
> Files arch/arm/dts/kirkwood-6192.dtsi and
> dts/upstream/src/arm/marvell/kirkwood-6192.dtsi differ
> Files arch/arm/dts/kirkwood-6281.dtsi and
> dts/upstream/src/arm/marvell/kirkwood-6281.dtsi differ
> Files arch/arm/dts/kirkwood-98dx4122.dtsi and
> dts/upstream/src/arm/marvell/kirkwood-98dx4122.dtsi differ
>
> 5. DTSI files that will need new or modified -u-boot.dtsi
>
> Files arch/arm/dts/kirkwood-dreamplug.dts and
> dts/upstream/src/arm/marvell/kirkwood-dreamplug.dts differ
> Files arch/arm/dts/kirkwood-lsxl.dtsi and
> dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi differ
> Files arch/arm/dts/kirkwood-nsa3x0-common.dtsi and
> dts/upstream/src/arm/marvell/kirkwood-nsa3x0-common.dtsi differ
>
> So these u-boot.dtsi files need to be created/modified so we can use upstream
> DTS/DTSI:
>
> modified: arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi
> modified: arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi
>
> new file: arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi
> new file: arch/arm/dts/kirkwood-nsa325-u-boot.dtsi
>
> I've regression tested this patch with the Zyxel NSA325 (Kirkwood 88F6282)
> and Zyxel NSA310S (Kirkwood 88F6281). The Zyxel NSA325 board has a
> USB 3.0 controller attached to the PCIe bus. And the Zyxel NSA310S
> has an extensive overhaul in bindings and styles in upstream DTS version.
>
> Signed-off-by: Tony Dinh
> ---
>
> Changes in v2:
> Remove unnecessary redefined OF_UPSTREAM and use "imply OF_UPSTREAM" for
> KW88F6281 and KW88F6192 SoCs.
Acked-by: Sumit Garg
-Sumit
>
> arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi | 7 +++
> arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi | 6 --
> arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi | 6 --
> arch/arm/dts/kirkwood-nsa325-u-boot.dtsi| 7 +++
> arch/arm/mach-kirkwood/Kconfig | 2 ++
> configs/SBx81LIFKW_defconfig| 1 +
> configs/SBx81LIFXCAT_defconfig | 1 +
> configs/d2net_v2_defconfig | 2 +-
> configs/dns325_defconfig| 2 +-
> configs/dockstar_defconfig | 2 +-
> configs/dreamplug_defconfig | 2 +-
> configs/ds109_defconfig | 2 +-
> configs/goflexhome_defconfig| 2 +-
> configs/guruplug_defconfig | 2 +-
> configs/ib62x0_defconfig| 2 +-
> configs/iconnect_defconfig | 2 +-
> configs/inetspace_v2_defconfig | 2 +-
> configs/lschlv2_defconfig | 2 +-
> configs/lsxhl_defconfig | 2 +-
> configs/nas220_defconfig| 2 +-
> configs/net2big_v2_defconfig| 2 +-
> configs/netspace_lite_v2_defconfig | 2 +-
> configs/netspace_max_v2_defconfig | 2 +-
> configs/netspace_mini_v2_defconfig | 2 +-
> configs/netspace_v2_defconfig | 2 +-
> configs/nsa310s_defconfig | 2 +-
> configs/nsa325_defconfig| 2 +-
> configs/openrd_base_defconfig | 2 +-
> configs/openrd_client_defconfig | 2 +-
> configs/openrd_ultimate_defconfig | 2 +-
> configs/pogo_e02_defconfig | 2 +-
> configs/pogo_v4_defconfig | 2 +-
> configs/sheevaplug_defconfig| 2 +-
> 33 files changed, 52 insertions(+), 30 deletions(-)
> create mode 100644 arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi
> create mode 100644 arch/arm/dts/kirkwood-nsa325-u-boot.dtsi
>
> diff --git a/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi
> b/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi
> new file mode 100644
> index 00..59f19a211f
> --- /dev/null
> +++ b/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi
> @@ -0,0 +1,7 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/ {
> + aliases {
> + spi0 =
> + };
> +};
> diff --git a/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi
> b/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi
> index 7fc2d7d3b4..cf33ff822e 100644
> --- a/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi
> +++ b/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi
> @@ -1,7 +1,9 @@
> // SPDX-License-Identifier: GPL
Re: [PATCH 5/6] Makefile: tune the include order
On Wed, 27 Mar 2024 at 19:01, Peng Fan wrote: > > > Subject: Re: [PATCH 5/6] Makefile: tune the include order > > > > Hi Peng, > > > > On Wed, 27 Mar 2024 at 18:41, Peng Fan (OSS) > > wrote: > > > > > > From: Peng Fan > > > > > > For OF_UPSTREAM support, the U-Boot headers under dt-bindings/ maybe > > > different with OF_UPSTREAM headers. So let OF_UPSTREAM headers be > > > included first when migrating to OF_UPSTREAM. > > > > No, please don't do that. The current include order gives preference to the > > U- > > Boot headers under dt-bindings/ such that we don't break platforms which > > haven't converted to OF_UPSTREAM. > > > > So while migrating to OF_UPSTREAM, you should just drop redundant > > headers under dt-bindings/ instead. > > But while in the middle that some boards using OF_UPSTREAM, some not, > we could not drop that. That's the real reason why we should try to migrate to OF_UPSTREAM at SoC level rather than at board level. If a particular board isn't supported upstream then they can opt out for the time being. > > I could sync the dt-bindings header first to avoid break anyway. Once you do that sync then there won't be any reason to keep headers under dt-bindings/. -Sumit > > Regards, > Peng. > > > > > -Sumit > > > > > > > > Signed-off-by: Peng Fan > > > --- > > > Makefile | 6 +++--- > > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > > > diff --git a/Makefile b/Makefile > > > index b80924241ec..b9c2d896c2e 100644 > > > --- a/Makefile > > > +++ b/Makefile > > > @@ -827,6 +827,7 @@ KBUILD_HOSTCFLAGS += $(if > > > $(CONFIG_TOOLS_DEBUG),-g) # Use UBOOTINCLUDE when you must > > reference the include/ directory. > > > # Needed to be compatible with the O= option > > > UBOOTINCLUDE:= \ > > > + -I$(srctree)/dts/upstream/include \ > > > -Iinclude \ > > > $(if $(KBUILD_SRC), -I$(srctree)/include) \ > > > $(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \ > > > @@ -835,8 +836,7 @@ UBOOTINCLUDE:= \ > > > -I$(srctree)/arch/arm/thumb1/include), \ > > > -I$(srctree)/arch/arm/thumb1/include)) \ > > > -I$(srctree)/arch/$(ARCH)/include \ > > > - -include $(srctree)/include/linux/kconfig.h \ > > > - -I$(srctree)/dts/upstream/include > > > + -include $(srctree)/include/linux/kconfig.h > > > > > > NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) > > > -print-file-name=include) > > > > > > @@ -907,7 +907,7 @@ ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) > > > PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a else ifndef > > > CONFIG_CC_IS_CLANG -PLATFORM_LIBGCC := -L $(shell dirname `$(CC) > > > $(c_flags) -print-libgcc-file-name`) -lgcc > > > +PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) > > > +-print-libgcc-file-name`) > > > endif > > > endif > > > PLATFORM_LIBS += $(PLATFORM_LIBGCC) > > > > > > -- > > > 2.35.3 > > >
Re: [PATCH 5/6] Makefile: tune the include order
Hi Peng, On Wed, 27 Mar 2024 at 18:41, Peng Fan (OSS) wrote: > > From: Peng Fan > > For OF_UPSTREAM support, the U-Boot headers under dt-bindings/ maybe > different with OF_UPSTREAM headers. So let OF_UPSTREAM headers be > included first when migrating to OF_UPSTREAM. No, please don't do that. The current include order gives preference to the U-Boot headers under dt-bindings/ such that we don't break platforms which haven't converted to OF_UPSTREAM. So while migrating to OF_UPSTREAM, you should just drop redundant headers under dt-bindings/ instead. -Sumit > > Signed-off-by: Peng Fan > --- > Makefile | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/Makefile b/Makefile > index b80924241ec..b9c2d896c2e 100644 > --- a/Makefile > +++ b/Makefile > @@ -827,6 +827,7 @@ KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g) > # Use UBOOTINCLUDE when you must reference the include/ directory. > # Needed to be compatible with the O= option > UBOOTINCLUDE:= \ > + -I$(srctree)/dts/upstream/include \ > -Iinclude \ > $(if $(KBUILD_SRC), -I$(srctree)/include) \ > $(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \ > @@ -835,8 +836,7 @@ UBOOTINCLUDE:= \ > -I$(srctree)/arch/arm/thumb1/include), \ > -I$(srctree)/arch/arm/thumb1/include)) \ > -I$(srctree)/arch/$(ARCH)/include \ > - -include $(srctree)/include/linux/kconfig.h \ > - -I$(srctree)/dts/upstream/include > + -include $(srctree)/include/linux/kconfig.h > > NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include) > > @@ -907,7 +907,7 @@ ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) > PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a > else > ifndef CONFIG_CC_IS_CLANG > -PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) > -print-libgcc-file-name`) -lgcc > +PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) > -print-libgcc-file-name`) > endif > endif > PLATFORM_LIBS += $(PLATFORM_LIBGCC) > > -- > 2.35.3 >
Re: [PATCH] arm: dts: kirkwood: Enable upstream DT on Kirkwood boards
Hi Tony, On Fri, 22 Mar 2024 at 07:48, Tony Dinh wrote: > > Enable OF_UPSTREAM to use upstream DT and add marvell/ prefix to the > DEFAULT_DEVICE_TREE for Kirkwood boards. And so we can directly build > DTBs from dts/upstream/src/arm/marvell, and including *-u-boot.dtsi > files from arch/arm/dts/ directory. > > Background: > > Hi Stefan, > Hi Michael, > > I did a survey and we currently have 28 Kirkwood boards. Using some > commands and filters, here are the finding. > > git grep -li arch_kirkwood configs | xargs grep DEVICE_TREE | cut -d '"' -f2 > | xargs -n1 sh -c 'diff -qs arch/arm/dts/$1.dts > dts/upstream/src/arm/marvell/$1.dts' sh | grep differ > > diff: dts/upstream/src/arm/marvell/kirkwood-atl-sbx81lifkw.dts: No such file > or directory > diff: dts/upstream/src/arm/marvell/kirkwood-atl-sbx81lifxcat.dts: No such > file or directory > > Files arch/arm/dts/kirkwood-dockstar.dts and > dts/upstream/src/arm/marvell/kirkwood-dockstar.dts differ > Files arch/arm/dts/kirkwood-dreamplug.dts and > dts/upstream/src/arm/marvell/kirkwood-dreamplug.dts differ > Files arch/arm/dts/kirkwood-goflexnet.dts and > dts/upstream/src/arm/marvell/kirkwood-goflexnet.dts differ > Files arch/arm/dts/kirkwood-guruplug-server-plus.dts and > dts/upstream/src/arm/marvell/kirkwood-guruplug-server-plus.dts differ > Files arch/arm/dts/kirkwood-iconnect.dts and > dts/upstream/src/arm/marvell/kirkwood-iconnect.dts differ > Files arch/arm/dts/kirkwood-net2big.dts and > dts/upstream/src/arm/marvell/kirkwood-net2big.dts differ > Files arch/arm/dts/kirkwood-ns2max.dts and > dts/upstream/src/arm/marvell/kirkwood-ns2max.dts differ > Files arch/arm/dts/kirkwood-ns2mini.dts and > dts/upstream/src/arm/marvell/kirkwood-ns2mini.dts differ > Files arch/arm/dts/kirkwood-nsa310s.dts and > dts/upstream/src/arm/marvell/kirkwood-nsa310s.dts differ > Files arch/arm/dts/kirkwood-nsa325.dts and > dts/upstream/src/arm/marvell/kirkwood-nsa325.dts differ > Files arch/arm/dts/kirkwood-openrd-client.dts and > dts/upstream/src/arm/marvell/kirkwood-openrd-client.dts differ > > diff -qrbu arch/arm/dts/ dts/upstream/src/arm/marvell/ | grep kirkwood | grep > ".dtsi " > > Files arch/arm/dts/kirkwood-6192.dtsi and > dts/upstream/src/arm/marvell/kirkwood-6192.dtsi differ > Files arch/arm/dts/kirkwood-6281.dtsi and > dts/upstream/src/arm/marvell/kirkwood-6281.dtsi differ > Files arch/arm/dts/kirkwood-98dx4122.dtsi and > dts/upstream/src/arm/marvell/kirkwood-98dx4122.dtsi differ > Files arch/arm/dts/kirkwood-dnskw.dtsi and > dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi differ > Files arch/arm/dts/kirkwood.dtsi and > dts/upstream/src/arm/marvell/kirkwood.dtsi differ > Files arch/arm/dts/kirkwood-lsxl.dtsi and > dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi differ > Files arch/arm/dts/kirkwood-nsa3x0-common.dtsi and > dts/upstream/src/arm/marvell/kirkwood-nsa3x0-common.dtsi differ > Files arch/arm/dts/kirkwood-synology.dtsi and > dts/upstream/src/arm/marvell/kirkwood-synology.dtsi differ > > And after reviewing these differences, the following are my observation. > > OF_LIST is not used in these Kirkwood boards. > > 1. Boards that have only u-boot DTS that should be opt-out for now with > "#CONFIG_OF_UPSTREAM is not set" > > diff: dts/upstream/src/arm/marvell/kirkwood-atl-sbx81lifkw.dts: No such file > or directory > diff: dts/upstream/src/arm/marvell/kirkwood-atl-sbx81lifxcat.dts: No such > file or directory > > 2. DTS and DTSI files that have only cosmetic, style, or binding changes > (safe to take) > > Files arch/arm/dts/kirkwood-dockstar.dts and > dts/upstream/src/arm/marvell/kirkwood-dockstar.dts differ > Files arch/arm/dts/kirkwood-goflexnet.dts and > dts/upstream/src/arm/marvell/kirkwood-goflexnet.dts differ > Files arch/arm/dts/kirkwood-guruplug-server-plus.dts and > dts/upstream/src/arm/marvell/kirkwood-guruplug-server-plus.dts differ > Files arch/arm/dts/kirkwood-iconnect.dts and > dts/upstream/src/arm/marvell/kirkwood-iconnect.dts differ > Files arch/arm/dts/kirkwood-net2big.dts and > dts/upstream/src/arm/marvell/kirkwood-net2big.dts differ > Files arch/arm/dts/kirkwood-ns2max.dts and > dts/upstream/src/arm/marvell/kirkwood-ns2max.dts differ > Files arch/arm/dts/kirkwood-ns2mini.dts and > dts/upstream/src/arm/marvell/kirkwood-ns2mini.dts differ > Files arch/arm/dts/kirkwood-nsa325.dts and > dts/upstream/src/arm/marvell/kirkwood-nsa325.dts differ > Files arch/arm/dts/kirkwood-openrd-client.dts and > dts/upstream/src/arm/marvell/kirkwood-openrd-client.dts differ > > Files arch/arm/dts/kirkwood-dnskw.dtsi and > dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi differ > Files arch/arm/dts/kirkwood.dtsi and > dts/upstream/src/arm/marvell/kirkwood.dtsi differ > Files arch/arm/dts/kirkwood-synology.dtsi and > dts/upstream/src/arm/marvell/kirkwood-synology.dtsi differ > > 3. DTS files that are newer in upstream (safe to take with regression test) > > Files arch/arm/dts/kirkwood-nsa310s.dts and >
Re: [PATCH] configs: imx8mp_beacon: Enable PCIe NVMe drives
On Wed, 27 Mar 2024 at 02:55, Adam Ford wrote: > > The baseboard supports and NVMe drives via the PCIe slot. This > requires a few extra config options to be enabled. > > The NVMe can be enumerated with the following commands: > > u-boot=> pci enum > PCIE-0: Link up (Gen1-x1, Bus0) > u-boot=> nvme scan > u-boot=> nvme info > Device 0: Vendor: 0x15b7 Rev: 20120022 Prod: 184960441105 > Type: Hard Disk > Capacity: 122104.3 MB = 119.2 GB (250069680 x 512) > u-boot=> > > Signed-off-by: Adam Ford Reviewed-by: Sumit Garg -Sumit > --- > Depends on: > https://patchwork.ozlabs.org/project/uboot/patch/20240326202439.46707-4-aford...@gmail.com/ > > diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig > index 0ae8c9645a..fe1678d8ae 100644 > --- a/configs/imx8mp_beacon_defconfig > +++ b/configs/imx8mp_beacon_defconfig > @@ -15,6 +15,7 @@ CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-beacon-kit" > CONFIG_SPL_TEXT_BASE=0x92 > CONFIG_TARGET_IMX8MP_BEACON=y > +CONFIG_DM_RESET=y > CONFIG_SYS_MONITOR_LEN=524288 > CONFIG_SPL_MMC=y > CONFIG_SPL_SERIAL=y > @@ -27,6 +28,7 @@ CONFIG_ARMV8_SET_SMPEN=y > CONFIG_ARMV8_EA_EL3_FIRST=y > CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 > CONFIG_SYS_LOAD_ADDR=0x4048 > +CONFIG_PCI=y > # CONFIG_ANDROID_BOOT_IMAGE is not set > CONFIG_FIT=y > CONFIG_FIT_EXTERNAL_OFFSET=0x3000 > @@ -65,6 +67,7 @@ CONFIG_CMD_FUSE=y > CONFIG_CMD_GPIO=y > CONFIG_CMD_I2C=y > CONFIG_CMD_MMC=y > +CONFIG_CMD_PCI=y > CONFIG_CMD_USB=y > CONFIG_CMD_USB_SDP=y > CONFIG_CMD_USB_MASS_STORAGE=y > @@ -118,8 +121,11 @@ CONFIG_DWC_ETH_QOS_IMX=y > CONFIG_FEC_MXC=y > CONFIG_RGMII=y > CONFIG_MII=y > +CONFIG_NVME_PCI=y > +CONFIG_PCIE_DW_IMX=y > CONFIG_PHY=y > CONFIG_PHY_IMX8MQ_USB=y > +CONFIG_PHY_IMX8M_PCIE=y > CONFIG_PINCTRL=y > CONFIG_SPL_PINCTRL=y > CONFIG_PINCTRL_IMX8M=y > -- > 2.43.0 >
Re: [PATCH] ARM: dts: renesas: Switch to using upstream DT
On Mon, 25 Mar 2024 at 13:48, Marek Vasut wrote: > > Enable OF_UPSTREAM to use upstream DT and add renesas/ prefix to the > DEFAULT_DEVICE_TREE and OF_LIST. And thereby directly build DTB from > dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ > directory. > > The configuration update has been done using the following script: > ``` > sed -i '/^CONFIG_DEFAULT_DEVICE_TREE/ s@="@/@' `git grep -li renesas > configs` > sed -i '/^CONFIG_OF_LIST/ s@r8a@renesas/&@g' `git grep -li renesas configs` > ``` > > The RZN1 Snarc board does not seem to have a matching Linux kernel > DT counterpart, this is currently not switched to OF upstream. > > Signed-off-by: Marek Vasut > --- > Cc: Adam Ford > Cc: Biju Das > Cc: Lad Prabhakar > Cc: Paul Barker > Cc: Ralph Siemsen > Cc: Sumit Garg > Cc: Tom Rini > --- > arch/arm/Kconfig | 1 + > configs/alt_defconfig| 2 +- > configs/blanche_defconfig| 2 +- > configs/gose_defconfig | 2 +- > configs/grpeach_defconfig| 2 +- > configs/koelsch_defconfig| 2 +- > configs/lager_defconfig | 2 +- > configs/porter_defconfig | 2 +- > configs/rzn1_snarc_defconfig | 1 + > configs/silk_defconfig | 2 +- > configs/stout_defconfig | 2 +- > 11 files changed, 11 insertions(+), 9 deletions(-) > Reviewed-by: Sumit Garg -Sumit > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index a0842e19330..ab8f30f1142 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1068,6 +1068,7 @@ config ARCH_RENESAS > imply BOARD_EARLY_INIT_F > imply CMD_DM > imply FAT_WRITE > + imply OF_UPSTREAM > imply SYS_THUMB_BUILD > imply ARCH_MISC_INIT if DISPLAY_CPUINFO > > diff --git a/configs/alt_defconfig b/configs/alt_defconfig > index 06e9e11f297..c9ca22cbe8f 100644 > --- a/configs/alt_defconfig > +++ b/configs/alt_defconfig > @@ -16,7 +16,7 @@ CONFIG_ENV_SIZE=0x4 > CONFIG_ENV_OFFSET=0xC > CONFIG_ENV_SECT_SIZE=0x4 > CONFIG_DM_GPIO=y > -CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt" > +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7794-alt" > CONFIG_SPL_TEXT_BASE=0xe630 > CONFIG_ARCH_RENESAS_BOARD_STRING="Alt" > CONFIG_R8A7794=y > diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig > index c392055e5a7..a2823a614a5 100644 > --- a/configs/blanche_defconfig > +++ b/configs/blanche_defconfig > @@ -12,7 +12,7 @@ CONFIG_ENV_SIZE=0x4 > CONFIG_ENV_OFFSET=0x4 > CONFIG_ENV_SECT_SIZE=0x4 > CONFIG_DM_GPIO=y > -CONFIG_DEFAULT_DEVICE_TREE="r8a7792-blanche" > +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7792-blanche" > CONFIG_ARCH_RENESAS_BOARD_STRING="Blanche" > CONFIG_R8A7792=y > CONFIG_TARGET_BLANCHE=y > diff --git a/configs/gose_defconfig b/configs/gose_defconfig > index 35edc677c48..0f76ae147ef 100644 > --- a/configs/gose_defconfig > +++ b/configs/gose_defconfig > @@ -16,7 +16,7 @@ CONFIG_ENV_SIZE=0x4 > CONFIG_ENV_OFFSET=0xC > CONFIG_ENV_SECT_SIZE=0x4 > CONFIG_DM_GPIO=y > -CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose" > +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7793-gose" > CONFIG_SPL_TEXT_BASE=0xe630 > CONFIG_ARCH_RENESAS_BOARD_STRING="Gose" > CONFIG_R8A7793=y > diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig > index 0c581b634a2..70a80088bfb 100644 > --- a/configs/grpeach_defconfig > +++ b/configs/grpeach_defconfig > @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x1 > CONFIG_ENV_OFFSET=0x8 > CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > -CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach" > +CONFIG_DEFAULT_DEVICE_TREE="renesas/r7s72100-gr-peach" > CONFIG_RZA1=y > CONFIG_OF_LIBFDT_OVERLAY=y > CONFIG_SYS_MONITOR_LEN=524288 > diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig > index ad411b45141..a912e58cf4d 100644 > --- a/configs/koelsch_defconfig > +++ b/configs/koelsch_defconfig > @@ -16,7 +16,7 @@ CONFIG_ENV_SIZE=0x4 > CONFIG_ENV_OFFSET=0xC > CONFIG_ENV_SECT_SIZE=0x4 > CONFIG_DM_GPIO=y > -CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch" > +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7791-koelsch" > CONFIG_SPL_TEXT_BASE=0xe630 > CONFIG_ARCH_RENESAS_BOARD_STRING="Koelsch" > CONFIG_R8A7791=y > diff --git a/configs/lager_defconfig b/configs/lager_defconfig > index f60d4db5ec2..03f29b8849b 100644 > --- a/configs/lager_defconfig > +++ b/configs/lager_defconfig > @@ -16,7 +16,7 @@ CONFIG_ENV_SIZE=0x4 > CONFIG_ENV_OFFSET=0xC > CONFIG_ENV_SECT_SIZE=0x4000
Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
On Fri, 22 Mar 2024 at 00:47, Marek Vasut wrote:
>
> On 3/21/24 6:46 AM, Sumit Garg wrote:
> > On Thu, 21 Mar 2024 at 11:06, Marek Vasut wrote:
> >>
> >> On 3/15/24 11:41 AM, Sumit Garg wrote:
> >>> On Fri, 15 Mar 2024 at 14:53, Marek Vasut wrote:
> >>>>
> >>>> On 3/15/24 6:31 AM, Sumit Garg wrote:
> >>>>> On Thu, 14 Mar 2024 at 09:45, Marek Vasut wrote:
> >>>>>>
> >>>>>> On 3/12/24 8:03 AM, Sumit Garg wrote:
> >>>>>>> power_domain_on/off() isn't refcounted and power domain bus shouldn't
> >>>>>>> be
> >>>>>>> turned off for a single peripheral domain as it would negatively
> >>>>>>> affect
> >>>>>>> other peripheral domains. So lets just skip turning off bus power
> >>>>>>> domain.
> >>>>>>
> >>>>>> What exactly is the issue and how did you trigger it ?
> >>>>>>
> >>>>>> Details please.
> >>>>>
> >>>>> I suppose the issue can be triggered via the "=> usb start => usb
> >>>>> stop" sequence where one of the USB controllers is configured in
> >>>>> peripheral mode.
> >>>>
> >>>> 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
> >>>> is more extensive ?
> >>>>
> >>>> Please, write down the necessary steps to reproduce this problem, and
> >>>> what happens when that problem occurs.
> >>>
> >>> After digging in more, it looks like dev_power_domain_off() is never
> >>> (U-Boot life-cycle) invoked for USB controller devices derived from
> >>> DT. So this USB power domain sequence is never reachable.
> >>
> >> The imx8mp_hsiomix_off() is never called on 'usb stop' command ?
> >>
> >
> > Yeah, that's the case.
> >
> >> But then why would the 'usb start ; usb stop' test break power domain
> >> state here ?
> >
> > It won't break with current implementation, earlier I made this
> > assumption that 'usb stop' turns down the power domain.
>
> So, maybe I am a little confused, what is this patch solving then ?
>
It isn't actually solving anything since there isn't a need for
refcount for PD bus since power domain off isn't exercised during the
lifecycle of U-Boot. Hence, I dropped it.
> >>> BTW, dev_power_domain_on() is invoked when USB controller devices are
> >>> added based on DT.
> >>
> >> I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
> >> just before Linux boots .
> >>
> >> [...]
> >>
> >>>>>> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
> >>>>>
> >>>>> Sure I can do that but do you think the current approach can have any
> >>>>> side effects?
> >>>>
> >>>> Bus domain not getting cycled (which can leave it in some odd state),
> >>>> and increased power consumption if the next stage doesn't turn the
> >>>> domain off.
> >>>
> >>> Given above, would you like me to drop power domain off path entirely
> >>> here?
> >>
> >> Can the series go in without this patch ?
> >
> > Okay let me drop this patch.
>
> We can fix whatever it is that needs to be fixed in a smaller follow up
> series.
Sure, see below.
>
> >>> I think if people are concerned about power consumption then it
> >>> should be implemented properly in U-Boot to remove all the DT based
> >>> devices before passing on control to the next stage.
> >>
> >> I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
> >> just before Linux boots (esp. at that point), so if you do not power off
> >> the bus domain before booting Linux, you may hand over a device which
> >> was not fully power cycled.
> >
> > Unfortunately that's the current situation I see. IMO, the better
> > solution would be to just remove all the DT devices before passing on
> > control to Linux. That should automatically power off devices.
>
> Doesn't CONFIG_DM_DEVICE_REMOVE=y do something like that already ?
I just did simple experiment via following diff:
diff --git a/drivers/power/domain/imx8mp-hsiomix.c
b/drivers/power/domain/imx8mp-hsiomix.c
index 6188a04c45e..0ddcd39923a 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -101,6 +101,7 @@ static int imx8mp_hsiomix_set(struct power_domain
*power_domain, bool power_on)
if (gpr_reg0_bits)
setbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
} else {
+ while(1);
if (gpr_reg0_bits)
clrbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
The boot doesn't hang suggesting that CONFIG_DM_DEVICE_REMOVE=y isn't
effective to remove any DT devices. It can for sure be another
followup series to make it effective.
-Sumit
Re: [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
On Fri, 22 Mar 2024 at 00:47, Marek Vasut wrote:
>
> On 3/21/24 1:40 PM, Sumit Garg wrote:
> > On Thu, 14 Mar 2024 at 09:46, Marek Vasut wrote:
> >>
> >> On 3/12/24 8:03 AM, Sumit Garg wrote:
> >>> Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
> >>> PHY initialization moved to this standalone PHY driver.
> >>>
> >>> Inspired from counterpart Linux kernel v6.8-rc3 driver:
> >>> drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
> >>> reference commit 7559e7572c03 ("phy: Explicitly include correct DT
> >>> includes").
> >>
> >> [...]
> >>
> >>> +static int imx8_pcie_phy_probe(struct udevice *dev)
> >>> +{
> >>> + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
> >>> + ofnode gpr;
> >>> + int ret = 0;
> >>> +
> >>> + imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
> >>> + imx8_phy->base = dev_read_addr(dev);
> >>> + if (!imx8_phy->base)
> >>> + return -EINVAL;
> >>> +
> >>> + /* get PHY refclk pad mode */
> >>> + dev_read_u32(dev, "fsl,refclk-pad-mode",
> >>> _phy->refclk_pad_mode);
> >>> +
> >>> + imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
> >>> +
> >>> "fsl,tx-deemph-gen1",
> >>> + 0);
> >>> + imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
> >>> +
> >>> "fsl,tx-deemph-gen2",
> >>> + 0);
> >>> + imx8_phy->clkreq_unused = dev_read_bool(dev,
> >>> "fsl,clkreq-unsupported");
> >>> +
> >>> + /* Grab GPR config register range */
> >>> + gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
> >>> + if (ofnode_equal(gpr, ofnode_null())) {
> >>> + dev_err(dev, "unable to find GPR node\n");
> >>> + return -ENODEV;
> >>> + }
> >>> +
> >>> + imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
> >>> + if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> >>> + dev_err(dev, "unable to find iomuxc registers\n");
> >>> + return PTR_ERR(imx8_phy->iomuxc_gpr);
> >>> + }
> >>
> >> syscon_regmap_lookup_by_compatible() should simplify these two steps ^ .
> >>
> >
> > After a close look, that API isn't supported by U-Boot yet. So I will
> > keep the existing implementation with your review tag. I hope that's
> > fine with you.
>
> Oh, uh, I had a local patch from previous round of PCIe experiments, I
> just sent it out, you are on CC. Can you do a follow up fix once this
> series V4 is in ?
Sure I can do that as a followup once your patch is merged.
-Sumit
[PATCH v4 04/11] imx8mp: power-domain: Add PCIe support
Add support for GPCv2 power domains and clock handling for PCIe and
PCIe PHY.
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Reviewed-by: Marek Vasut
Signed-off-by: Sumit Garg
---
drivers/power/domain/imx8mp-hsiomix.c | 117 +-
1 file changed, 79 insertions(+), 38 deletions(-)
diff --git a/drivers/power/domain/imx8mp-hsiomix.c
b/drivers/power/domain/imx8mp-hsiomix.c
index e2d772c5ec7..d3b0c1146ce 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -16,48 +16,85 @@
#define GPR_REG0 0x0
#define PCIE_CLOCK_MODULE_EN BIT(0)
#define USB_CLOCK_MODULE_EN BIT(1)
+#define PCIE_PHY_APB_RST BIT(4)
+#define PCIE_PHY_INIT_RST BIT(5)
struct imx8mp_hsiomix_priv {
void __iomem *base;
struct clk clk_usb;
+ struct clk clk_pcie;
struct power_domain pd_bus;
struct power_domain pd_usb;
+ struct power_domain pd_pcie;
struct power_domain pd_usb_phy1;
struct power_domain pd_usb_phy2;
+ struct power_domain pd_pcie_phy;
};
-static int imx8mp_hsiomix_on(struct power_domain *power_domain)
+static int imx8mp_hsiomix_set(struct power_domain *power_domain, bool power_on)
{
struct udevice *dev = power_domain->dev;
struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
- struct power_domain *domain;
+ struct power_domain *domain = NULL;
+ struct clk *clk = NULL;
+ u32 gpr_reg0_bits = 0;
int ret;
- ret = power_domain_on(>pd_bus);
- if (ret)
- return ret;
-
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) {
+ switch (power_domain->id) {
+ case IMX8MP_HSIOBLK_PD_USB:
domain = >pd_usb;
- } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) {
+ clk = >clk_usb;
+ gpr_reg0_bits |= USB_CLOCK_MODULE_EN;
+ break;
+ case IMX8MP_HSIOBLK_PD_USB_PHY1:
domain = >pd_usb_phy1;
- } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) {
+ break;
+ case IMX8MP_HSIOBLK_PD_USB_PHY2:
domain = >pd_usb_phy2;
- } else {
- ret = -EINVAL;
- goto err_pd;
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE:
+ domain = >pd_pcie;
+ clk = >clk_pcie;
+ gpr_reg0_bits |= PCIE_CLOCK_MODULE_EN;
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE_PHY:
+ domain = >pd_pcie_phy;
+ /* Bits to deassert PCIe PHY reset */
+ gpr_reg0_bits |= PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST;
+ break;
+ default:
+ dev_err(dev, "unknown power domain id: %ld\n",
+ power_domain->id);
+ return -EINVAL;
}
- ret = power_domain_on(domain);
- if (ret)
- goto err_pd;
+ if (power_on) {
+ ret = power_domain_on(>pd_bus);
+ if (ret)
+ return ret;
- ret = clk_enable(>clk_usb);
- if (ret)
- goto err_clk;
+ ret = power_domain_on(domain);
+ if (ret)
+ goto err_pd;
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
- setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
+ if (clk) {
+ ret = clk_enable(clk);
+ if (ret)
+ goto err_clk;
+ }
+
+ if (gpr_reg0_bits)
+ setbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
+ } else {
+ if (gpr_reg0_bits)
+ clrbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
+
+ if (clk)
+ clk_disable(clk);
+
+ power_domain_off(domain);
+ power_domain_off(>pd_bus);
+ }
return 0;
@@ -68,26 +105,14 @@ err_pd:
return ret;
}
-static int imx8mp_hsiomix_off(struct power_domain *power_domain)
+static int imx8mp_hsiomix_on(struct power_domain *power_domain)
{
- struct udevice *dev = power_domain->dev;
- struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
-
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
- clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
-
- clk_disable(>clk_usb);
-
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
- power_domain_off(>pd_usb);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1)
- power_domain_off(>pd_usb_phy1);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2)
- power_domain_off(>pd_usb_phy2);
-
- power_domain_off(>pd_bus);
+ r
[PATCH v4 11/11] MAINTAINERS: Add entry for PCIe DWC IMX driver
Add myself as maintainer for PCIe DWC IMX driver support. Acked-by: Marek Vasut Signed-off-by: Sumit Garg --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8b316c8550e..83fd68e3f39 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1371,6 +1371,12 @@ M: Simon Glass S: Maintained F: tools/patman/ +PCIe DWC IMX +M: Sumit Garg +S: Maintained +F: drivers/pci/pcie_dw_imx.c +F: drivers/phy/phy-imx8m-pcie.c + PCI Endpoint M: Ramon Fried S: Maintained -- 2.34.1
[PATCH v4 10/11] imx8mp_venice_defconfig: Enable PCIe/NVMe support
From: Tim Harvey Enable PCIe/NVMe support. Also, enable the reset, regmap and syscon drivers which are a prerequisite for PCIe support. Signed-off-by: Tim Harvey [SG: rebased to next branch tip] Signed-off-by: Sumit Garg --- configs/imx8mp_venice_defconfig | 8 1 file changed, 8 insertions(+) diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 501ccb0ba8f..6e4addc7728 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-venice-gw71xx-2x" CONFIG_SPL_TEXT_BASE=0x92 CONFIG_TARGET_IMX8MP_VENICE=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -21,6 +22,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 CONFIG_SYS_LOAD_ADDR=0x4048 +CONFIG_PCI=y CONFIG_SYS_MEMTEST_START=0x4000 CONFIG_SYS_MEMTEST_END=0x8000 CONFIG_FIT=y @@ -63,6 +65,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y @@ -84,6 +87,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y CONFIG_GPIO_HOG=y @@ -112,7 +117,10 @@ CONFIG_FEC_MXC=y CONFIG_KSZ9477=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -- 2.34.1
[PATCH v4 09/11] verdin-imx8mp_defconfig: Enable PCIe/NVMe support
Enable PCIe/NVMe support. Also, enable the reset driver which is a prerequisite for PCIe support. Acked-by: Francesco Dolcini Tested-by: Marcel Ziswiler Signed-off-by: Sumit Garg --- configs/verdin-imx8mp_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 7ac5e65642c..b6194404baa 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx8mp-verdin-wifi-dev" CONFIG_SPL_TEXT_BASE=0x92 CONFIG_TARGET_VERDIN_IMX8MP=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -26,6 +27,7 @@ CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 CONFIG_SYS_LOAD_ADDR=0x4820 +CONFIG_PCI=y CONFIG_SYS_MEMTEST_START=0x4000 CONFIG_SYS_MEMTEST_END=0x8000 CONFIG_REMAKE_ELF=y @@ -76,6 +78,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_READ=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -145,8 +148,11 @@ CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y CONFIG_PHY=y CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -- 2.34.1
[PATCH v4 08/11] pcie_imx: Update header to describe it as a legacy driver
Since now we have the modern pcie_dw_imx.c driver for iMX SoCs, encourage people to switch to that for any further new iMX SoC support or even for the older iMX6 SoCs too. Suggested-by: Peter Robinson Signed-off-by: Sumit Garg --- drivers/pci/pcie_imx.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 4a18b0e0910..78f2c7d6bcd 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -7,6 +7,14 @@ * Based on upstream Linux kernel driver: * pci-imx6.c: Sean Cross * pcie-designware.c: Jingoo Han + * + * This is a legacy PCIe iMX driver kept to support older iMX6 SoCs. It is + * rather tied to quite old port of pcie-designware driver from Linux which + * suffices only iMX6 specific needs. But now we have modern PCIe iMX driver + * (drivers/pci/pcie_dw_imx.c) utilizing all the common DWC specific bits from + * (drivers/pci/pcie_dw_common.*). So you are encouraged to add any further iMX + * SoC support there or even better if you posses older iMX6 SoCs then switch + * those too in order to have a single modern PCIe iMX driver. */ #include -- 2.34.1
[PATCH v4 07/11] pci: Add DW PCIe controller support for iMX8MP SoC
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Reviewed-by: Marek Vasut
Signed-off-by: Sumit Garg
---
drivers/pci/Kconfig | 11 ++
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_imx.c | 338 ++
3 files changed, 350 insertions(+)
create mode 100644 drivers/pci/pcie_dw_imx.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 463ec47eb92..8d02ab82ad9 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -413,4 +413,15 @@ config PCIE_STARFIVE_JH7110
Say Y here if you want to enable PLDA XpressRich PCIe controller
support on StarFive JH7110 SoC.
+config PCIE_DW_IMX
+ bool "i.MX DW PCIe controller support"
+ depends on ARCH_IMX8M
+ select PCIE_DW_COMMON
+ select DM_REGULATOR
+ select REGMAP
+ select SYSCON
+ help
+ Say Y here if you want to enable DW PCIe controller support on
+ iMX SoCs.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 72ef8b4bc77..2927c519129 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
+obj-$(CONFIG_PCIE_DW_IMX) += pcie_dw_imx.o
diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
new file mode 100644
index 000..a2ee228224b
--- /dev/null
+++ b/drivers/pci/pcie_dw_imx.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Linaro Ltd.
+ *
+ * Author: Sumit Garg
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie_dw_common.h"
+
+#define PCIE_LINK_CAPABILITY 0x7c
+#define TARGET_LINK_SPEED_MASK 0xf
+#define LINK_SPEED_GEN_1 0x1
+#define LINK_SPEED_GEN_2 0x2
+#define LINK_SPEED_GEN_3 0x3
+
+#define PCIE_MISC_CONTROL_1_OFF0x8bc
+#define PCIE_DBI_RO_WR_EN BIT(0)
+
+#define PCIE_PORT_DEBUG0 0x728
+#define PCIE_PORT_DEBUG1 0x72c
+#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
+#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
+
+#define PCIE_LINK_UP_TIMEOUT_MS100
+
+#define IOMUXC_GPR14_OFFSET0x38
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDEBIT(11)
+
+struct pcie_dw_imx {
+ /* Must be first member of the struct */
+ struct pcie_dw dw;
+ struct regmap *iomuxc_gpr;
+ struct clk_bulk clks;
+ struct gpio_descreset_gpio;
+ struct reset_ctlapps_reset;
+ struct phy phy;
+ struct udevice *vpcie;
+};
+
+static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
+{
+ dw_pcie_dbi_write_enable(>dw, true);
+
+ clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CAPABILITY,
+ TARGET_LINK_SPEED_MASK, cap_speed);
+
+ dw_pcie_dbi_write_enable(>dw, false);
+}
+
+static void imx_pcie_ltssm_enable(struct pcie_dw_imx *priv)
+{
+ reset_deassert(>apps_reset);
+}
+
+static void imx_pcie_ltssm_disable(struct pcie_dw_imx *priv)
+{
+ reset_assert(>apps_reset);
+}
+
+static bool is_link_up(u32 val)
+{
+ return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
+ (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
+}
+
+static int wait_link_up(struct pcie_dw_imx *priv)
+{
+ u32 val;
+
+ return readl_poll_sleep_timeout(priv->dw.dbi_base + PCIE_PORT_DEBUG1,
+ val, is_link_up(val), 1, 10);
+}
+
+static int pcie_link_up(struct pcie_dw_imx *priv, u32 cap_speed)
+{
+ int ret;
+
+ /* DW pre link configurations */
+ pcie_dw_configure(priv, cap_speed);
+
+ /* Initiate link training */
+ imx_pcie_ltssm_enable(priv);
+
+ /* Check that link was established */
+ ret = wait_link_up(priv);
+
[PATCH v4 06/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy: Explicitly include correct DT
includes").
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Reviewed-by: Marek Vasut
Signed-off-by: Sumit Garg
---
drivers/phy/Kconfig | 11 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-imx8m-pcie.c | 283 +++
3 files changed, 295 insertions(+)
create mode 100644 drivers/phy/phy-imx8m-pcie.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 60138beca49..8f767877e73 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -284,6 +284,17 @@ config PHY_IMX8MQ_USB
help
Support the USB3.0 PHY in NXP i.MX8MQ or i.MX8MP SoC
+config PHY_IMX8M_PCIE
+ bool "NXP i.MX8MM/i.MX8MP PCIe PHY Driver"
+ depends on PHY
+ depends on IMX8MM || IMX8MP
+ select REGMAP
+ select SYSCON
+ help
+ Support the PCIe PHY in NXP i.MX8MM or i.MX8MP SoC
+
+ This PHY is found on i.MX8M devices supporting PCIe.
+
config PHY_XILINX_ZYNQMP
tristate "Xilinx ZynqMP PHY driver"
depends on PHY && ARCH_ZYNQMP
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 2e8723186c0..7a2b764492b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
+obj-$(CONFIG_PHY_IMX8M_PCIE) += phy-imx8m-pcie.o
obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
obj-y += cadence/
obj-y += ti/
diff --git a/drivers/phy/phy-imx8m-pcie.c b/drivers/phy/phy-imx8m-pcie.c
new file mode 100644
index 000..2418388cb3c
--- /dev/null
+++ b/drivers/phy/phy-imx8m-pcie.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Linaro Ltd.
+ *
+ * Derived from Linux counterpart driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define IMX8MM_PCIE_PHY_CMN_REG061 0x184
+#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0)
+#define IMX8MM_PCIE_PHY_CMN_REG062 0x188
+#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3)
+#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C
+#define AUX_PLL_REFCLK_SEL_SYS_PLLGENMASK(7, 6)
+#define IMX8MM_PCIE_PHY_CMN_REG064 0x190
+#define ANA_AUX_RX_TX_SEL_TX BIT(7)
+#define ANA_AUX_RX_TERM_GND_ENBIT(3)
+#define ANA_AUX_TX_TERM BIT(2)
+#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
+#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
+#define ANA_AUX_TX_LVLGENMASK(3, 0)
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
+#define PCIE_PHY_TRSV_REG5 0x414
+#define PCIE_PHY_TRSV_REG6 0x418
+
+#define IMX8MM_GPR_PCIE_REF_CLK_SELGENMASK(25, 24)
+#define IMX8MM_GPR_PCIE_REF_CLK_PLLFIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL,
0x3)
+#define IMX8MM_GPR_PCIE_REF_CLK_EXTFIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL,
0x2)
+#define IMX8MM_GPR_PCIE_AUX_EN BIT(19)
+#define IMX8MM_GPR_PCIE_CMN_RSTBIT(18)
+#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17)
+#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
+#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDEBIT(9)
+
+#define IOMUXC_GPR14_OFFSET0x38
+
+enum imx8_pcie_phy_type {
+ IMX8MM,
+ IMX8MP,
+};
+
+struct imx8_pcie_phy_drvdata {
+ const char*gpr;
+ enumimx8_pcie_phy_type variant;
+};
+
+struct imx8_pcie_phy {
+ ulong base;
+ struct clk hsio_clk;
+ struct regmap *iomuxc_gpr;
+ struct reset_ctlperst;
+ struct reset_ctlreset;
+ u32 refclk_pad_mode;
+ u32 tx_deemph_gen1;
+ u32 tx_deemph_gen2;
+ boolclkreq_unused;
+ const struct imx8_pcie_phy_drvdata *drvdata;
+};
+
+static int imx8_pcie_phy_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, pad_mode;
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev);
+
+ pad_mode = imx8_phy->refclk_pad_mode;
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ reset_assert(_phy->reset);
+
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_ph
[PATCH v4 05/11] imx8mp: power-domain: Expose high performance PLL clock
Expose the high performance PLL as clock framework clock, so the
PCIe PHY can use it when there is no external refclock provided.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver
reference commit 7476ddfd36ac ("pmdomain: imx8mp-blk-ctrl: Convert to
platform remove callback returning void").
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Reviewed-by: Marek Vasut
Signed-off-by: Sumit Garg
---
drivers/power/domain/imx8mp-hsiomix.c | 77 +++
1 file changed, 77 insertions(+)
diff --git a/drivers/power/domain/imx8mp-hsiomix.c
b/drivers/power/domain/imx8mp-hsiomix.c
index d3b0c1146ce..6188a04c45e 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -6,9 +6,15 @@
#include
#include
#include
+#include
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
#include
#include
@@ -18,6 +24,15 @@
#define USB_CLOCK_MODULE_EN BIT(1)
#define PCIE_PHY_APB_RST BIT(4)
#define PCIE_PHY_INIT_RST BIT(5)
+#define GPR_REG1 0x4
+#define PLL_LOCK BIT(13)
+#define GPR_REG2 0x8
+#define P_PLL_MASKGENMASK(5, 0)
+#define M_PLL_MASKGENMASK(15, 6)
+#define S_PLL_MASKGENMASK(18, 16)
+#define GPR_REG3 0xc
+#define PLL_CKE BIT(17)
+#define PLL_RST BIT(31)
struct imx8mp_hsiomix_priv {
void __iomem *base;
@@ -123,6 +138,67 @@ static int imx8mp_hsiomix_of_xlate(struct power_domain
*power_domain,
return 0;
}
+static int hsio_pll_clk_enable(struct clk *clk)
+{
+ void *base = (void *)dev_get_driver_data(clk->dev);
+ u32 val;
+ int ret;
+
+ /* Setup HSIO PLL as 100 MHz output clock */
+ clrsetbits_le32(base + GPR_REG2,
+ P_PLL_MASK | M_PLL_MASK | S_PLL_MASK,
+ FIELD_PREP(P_PLL_MASK, 12) |
+ FIELD_PREP(M_PLL_MASK, 800) |
+ FIELD_PREP(S_PLL_MASK, 4));
+
+ /* de-assert PLL reset */
+ setbits_le32(base + GPR_REG3, PLL_RST);
+
+ /* enable PLL */
+ setbits_le32(base + GPR_REG3, PLL_CKE);
+
+ /* Check if PLL is locked */
+ ret = readl_poll_sleep_timeout(base + GPR_REG1, val,
+ val & PLL_LOCK, 10, 10);
+ if (ret)
+ dev_err(clk->dev, "failed to lock HSIO PLL\n");
+
+ return ret;
+}
+
+static int hsio_pll_clk_disable(struct clk *clk)
+{
+ void *base = (void *)dev_get_driver_data(clk->dev);
+
+ clrbits_le32(base + GPR_REG3, PLL_CKE | PLL_RST);
+
+ return 0;
+}
+
+static const struct clk_ops hsio_pll_clk_ops = {
+ .enable = hsio_pll_clk_enable,
+ .disable = hsio_pll_clk_disable,
+};
+
+U_BOOT_DRIVER(hsio_pll) = {
+ .name = "hsio-pll",
+ .id = UCLASS_CLK,
+ .ops = _pll_clk_ops,
+};
+
+int imx8mp_hsiomix_bind(struct udevice *dev)
+{
+ struct driver *drv;
+
+ drv = lists_driver_lookup_name("hsio-pll");
+ if (!drv)
+ return -ENOENT;
+
+ return device_bind_with_driver_data(dev, drv, "hsio-pll",
+ (ulong)dev_read_addr_ptr(dev),
+ dev_ofnode(dev), NULL);
+}
+
static int imx8mp_hsiomix_probe(struct udevice *dev)
{
struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
@@ -193,6 +269,7 @@ U_BOOT_DRIVER(imx8mp_hsiomix) = {
.id = UCLASS_POWER_DOMAIN,
.of_match = imx8mp_hsiomix_ids,
.probe = imx8mp_hsiomix_probe,
+ .bind = imx8mp_hsiomix_bind,
.priv_auto = sizeof(struct imx8mp_hsiomix_priv),
.ops= _hsiomix_ops,
};
--
2.34.1
[PATCH v4 03/11] reset: imx: Add support for i.MX8MP reset controller
Add support for i.MX8MP reset controller, it has same reset IP inside
as the other iMX7 and iMX8M variants but with different module layout.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/reset/reset-imx7.c. Use last Linux kernel driver reference
commit bad8a8afe19f ("reset: Explicitly include correct DT includes").
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Reviewed-by: Marek Vasut
Signed-off-by: Sumit Garg
---
drivers/reset/reset-imx7.c | 101 +
1 file changed, 101 insertions(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index ca703466605..a3b3132f2fa 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -252,6 +253,102 @@ static int imx8mq_reset_assert(struct reset_ctl *rst)
return 0;
}
+enum imx8mp_src_registers {
+ SRC_SUPERMIX_RCR= 0x0018,
+ SRC_AUDIOMIX_RCR= 0x001c,
+ SRC_MLMIX_RCR = 0x0028,
+ SRC_GPU2D_RCR = 0x0038,
+ SRC_GPU3D_RCR = 0x003c,
+ SRC_VPU_G1_RCR = 0x0048,
+ SRC_VPU_G2_RCR = 0x004c,
+ SRC_VPUVC8KE_RCR= 0x0050,
+ SRC_NOC_RCR = 0x0054,
+};
+
+static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
+ [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
+ [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
+ [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
+ [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
+ [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
+ [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
+ [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
+ [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
+ [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
+ [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
+ [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
+ [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
+ [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
+ [IMX8MP_RESET_A53_SOC_DBG_RESET]= { SRC_A53RCR0, BIT(20) },
+ [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
+ [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
+ [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
+ [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
+ [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
+ [IMX8MP_RESET_PCIEPHY_PERST]= { SRC_PCIEPHY_RCR, BIT(3) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_EN]= { SRC_PCIEPHY_RCR, BIT(6) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
+ [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
+ [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU_RESET]= { SRC_GPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_RESET]= { SRC_VPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
+ [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
+ [IMX8MP_RESET_NOC_RESET]= { SRC_NOC_RCR, BIT(0) },
+};
+
+static int imx8mp_reset_set(struct reset_ctl *rst, bool assert)
+{
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
+ unsigned int bit, value;
+
+ if (rst->id >= IMX8MP_RESET_NUM)
+ return -EINVAL;
+
+ bit = imx8mp_src_signals[rst->id].bit;
+ value = assert ? bit : 0;
+
+ switch (rst->id) {
+ case IMX8MP_RESET_PCIEPHY:
+ /*
+* wait for more than 10us to release phy g_rst and
+* btnrst
+*/
+ if (!assert)
+ udelay(10);
+
[PATCH v4 02/11] reset: imx: Refactor driver to simplify function names
imx7_reset_{deassert/assert}_imx* are a bit more confusing when compared
with imx*_reset_{deassert/assert}. So refactor driver to use function
names easier to understand. This shouldn't affect the functionality
though.
Suggested-by: Marek Vasut
Reviewed-by: Marek Vasut
Signed-off-by: Sumit Garg
---
drivers/reset/reset-imx7.c | 42 +++---
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index eaef2cc2cdf..ca703466605 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -14,7 +14,7 @@
#include
#include
-struct imx7_reset_priv {
+struct imx_reset_priv {
void __iomem *base;
struct reset_ops ops;
};
@@ -64,9 +64,9 @@ static const struct imx7_src_signal
imx7_src_signals[IMX7_RESET_NUM] = {
[IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
};
-static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
+static int imx7_reset_deassert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx7_src_signals;
u32 val;
@@ -95,9 +95,9 @@ static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
return 0;
}
-static int imx7_reset_assert_imx7(struct reset_ctl *rst)
+static int imx7_reset_assert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx7_src_signals;
u32 val;
@@ -185,9 +185,9 @@ static const struct imx7_src_signal
imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
[IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
};
-static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst)
+static int imx8mq_reset_deassert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx8mq_src_signals;
u32 val;
@@ -223,9 +223,9 @@ static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst)
return 0;
}
-static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
+static int imx8mq_reset_assert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx8mq_src_signals;
u32 val;
@@ -252,21 +252,21 @@ static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
return 0;
}
-static int imx7_reset_assert(struct reset_ctl *rst)
+static int imx_reset_assert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
return priv->ops.rst_assert(rst);
}
-static int imx7_reset_deassert(struct reset_ctl *rst)
+static int imx_reset_deassert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
return priv->ops.rst_deassert(rst);
}
static const struct reset_ops imx7_reset_reset_ops = {
- .rst_assert = imx7_reset_assert,
- .rst_deassert = imx7_reset_deassert,
+ .rst_assert = imx_reset_assert,
+ .rst_deassert = imx_reset_deassert,
};
static const struct udevice_id imx7_reset_ids[] = {
@@ -277,18 +277,18 @@ static const struct udevice_id imx7_reset_ids[] = {
static int imx7_reset_probe(struct udevice *dev)
{
- struct imx7_reset_priv *priv = dev_get_priv(dev);
+ struct imx_reset_priv *priv = dev_get_priv(dev);
priv->base = dev_remap_addr(dev);
if (!priv->base)
return -ENOMEM;
if (device_is_compatible(dev, "fsl,imx8mq-src")) {
- priv->ops.rst_assert = imx7_reset_assert_imx8mq;
- priv->ops.rst_deassert = imx7_reset_deassert_imx8mq;
+ priv->ops.rst_assert = imx8mq_reset_assert;
+ priv->ops.rst_deassert = imx8mq_reset_deassert;
} else if (device_is_compatible(dev, "fsl,imx7d-src")) {
- priv->ops.rst_assert = imx7_reset_assert_imx7;
- priv->ops.rst_deassert = imx7_reset_deassert_imx7;
+ priv->ops.rst_assert = imx7_reset_assert;
+ priv->ops.rst_deassert = imx7_reset_deassert;
}
return 0;
@@ -300,5 +300,5 @@ U_BOOT_DRIVER(imx7_reset) = {
.of_match = imx7_reset_ids,
.ops = _reset_reset_ops,
.probe = imx7_reset_probe,
- .priv_auto = sizeof(struct imx7_reset_priv),
+ .priv_auto = sizeof(struct imx_reset_priv),
};
--
2.34.1
[PATCH v4 01/11] clk: imx8mp: Add support for PCIe clocks
Add support for PCIe clocks required to enable PCIe support on
iMX8MP SoC.
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Reviewed-by: Marek Vasut
Signed-off-by: Sumit Garg
---
drivers/clk/imx/clk-imx8mp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a21a3ce34bb..7dfc829df2c 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -62,6 +62,10 @@ static const char *imx8mp_dram_apb_sels[] =
{"clock-osc-24m", "sys_pll2_200m", "
"sys_pll1_160m", "sys_pll1_800m",
"sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out",
};
+static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m",
"sys_pll2_200m", "sys_pll2_50m",
+ "sys_pll3_out",
"sys_pll2_100m", "sys_pll1_80m",
+ "sys_pll1_160m",
"sys_pll1_200m", };
+
static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out",
"video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
@@ -272,6 +276,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt",
imx8mp_dram_alt_sels, base + 0xa000));
clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb",
imx8mp_dram_apb_sels, base + 0xa080));
+ clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux",
imx8mp_pcie_aux_sels, base + 0xa400));
clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels,
base + 0xa480));
clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels,
base + 0xa500));
clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos",
imx8mp_enet_qos_sels, base + 0xa880));
@@ -322,6 +327,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2",
base + 0x4180, 0));
clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3",
base + 0x4190, 0));
clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4",
base + 0x41a0, 0));
+ clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux",
base + 0x4250, 0));
clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1",
base + 0x4280, 0));
clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2",
base + 0x4290, 0));
clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3",
base + 0x42a0, 0));
--
2.34.1
[PATCH v4 00/11] imx8mp: Enable PCIe/NVMe support
pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
rather tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Testing with this patch-set included:
Verdin iMX8MP # pci enum
PCIE-0: Link up (Gen1-x1, Bus0)
Verdin iMX8MP #
Verdin iMX8MP # nvme scan
Verdin iMX8MP #
Verdin iMX8MP # nvme info
Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000720
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Verdin iMX8MP #
Verdin iMX8MP # load nvme 0 $loadaddr
Changes in v4:
- Incorporated misc comments from Marek and added his review tag.
- Dropped patch #4 (imx8mp: power-domain: Don't power off pd_bus)
since power domain off path is never excercised for DT based devices.
- Added patch#8 as suggested by Peter to describe older pcie_imx.c
driver as legacy one.
Changes in v3:
- Rebased on top of U-Boot next.
- Incorporated misc. updates to commit messages.
- New patch#2 to refactor reset driver function names.
- Patch#3: Refactored further for better code reuse.
- New patch#4 to fix refcount issue with power domain bus.
- Patch#5: Refactored further for better code reuse.
- Patch#7 & #8: Added dependency on REGMAP and SYSCON. Also, added
support for vpcie-supply regulator.
- Patch#7 & #8: Added error paths and .remove callback.
- New patch#10 to enable PCIe/NVMe for imx8mp_venice*.
Changes in v2:
- Renamed PCIe IMX driver pcie_dw_imx8.c -> pcie_dw_imx.c.
- Added myself as maintainer for PCIe DWC IMX driver support.
- Incorporated various code and commit message improvement suggestions
from Marek, thanks.
- Patch#3: Gate PCIe and USB clocks behind corresponding power domain
IDs.
- Patch#4: Expose HSIO PLL clocks as a regular clock driver instead
similar to what Linux kernel does.
- Patch#7: Picked up tags.
Sumit Garg (10):
clk: imx8mp: Add support for PCIe clocks
reset: imx: Refactor driver to simplify function names
reset: imx: Add support for i.MX8MP reset controller
imx8mp: power-domain: Add PCIe support
imx8mp: power-domain: Expose high performance PLL clock
phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
pci: Add DW PCIe controller support for iMX8MP SoC
pcie_imx: Update header to describe it as a legacy driver
verdin-imx8mp_defconfig: Enable PCIe/NVMe support
MAINTAINERS: Add entry for PCIe DWC IMX driver
Tim Harvey (1):
imx8mp_venice_defconfig: Enable PCIe/NVMe support
MAINTAINERS | 6 +
configs/imx8mp_venice_defconfig | 8 +
configs/verdin-imx8mp_defconfig | 6 +
drivers/clk/imx/clk-imx8mp.c | 6 +
drivers/pci/Kconfig | 11 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_imx.c | 338 ++
drivers/pci/pcie_imx.c| 8 +
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-imx8m-pcie.c | 283 +
drivers/power/domain/imx8mp-hsiomix.c | 190 ---
drivers/reset/reset-imx7.c| 143 +--
13 files changed, 955 insertions(+), 57 deletions(-)
create mode 100644 drivers/pci/pcie_dw_imx.c
create mode 100644 drivers/phy/phy-imx8m-pcie.c
--
2.34.1
Re: [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
On Thu, 14 Mar 2024 at 09:46, Marek Vasut wrote:
>
> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
> > PHY initialization moved to this standalone PHY driver.
> >
> > Inspired from counterpart Linux kernel v6.8-rc3 driver:
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
> > reference commit 7559e7572c03 ("phy: Explicitly include correct DT
> > includes").
>
> [...]
>
> > +static int imx8_pcie_phy_probe(struct udevice *dev)
> > +{
> > + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
> > + ofnode gpr;
> > + int ret = 0;
> > +
> > + imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
> > + imx8_phy->base = dev_read_addr(dev);
> > + if (!imx8_phy->base)
> > + return -EINVAL;
> > +
> > + /* get PHY refclk pad mode */
> > + dev_read_u32(dev, "fsl,refclk-pad-mode", _phy->refclk_pad_mode);
> > +
> > + imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
> > + "fsl,tx-deemph-gen1",
> > + 0);
> > + imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
> > + "fsl,tx-deemph-gen2",
> > + 0);
> > + imx8_phy->clkreq_unused = dev_read_bool(dev,
> > "fsl,clkreq-unsupported");
> > +
> > + /* Grab GPR config register range */
> > + gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
> > + if (ofnode_equal(gpr, ofnode_null())) {
> > + dev_err(dev, "unable to find GPR node\n");
> > + return -ENODEV;
> > + }
> > +
> > + imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
> > + if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> > + dev_err(dev, "unable to find iomuxc registers\n");
> > + return PTR_ERR(imx8_phy->iomuxc_gpr);
> > + }
>
> syscon_regmap_lookup_by_compatible() should simplify these two steps ^ .
>
After a close look, that API isn't supported by U-Boot yet. So I will
keep the existing implementation with your review tag. I hope that's
fine with you.
-Sumit
> With that fixed:
>
> Reviewed-by: Marek Vasut
>
> [...]
Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
On Thu, 21 Mar 2024 at 11:06, Marek Vasut wrote: > > On 3/15/24 11:41 AM, Sumit Garg wrote: > > On Fri, 15 Mar 2024 at 14:53, Marek Vasut wrote: > >> > >> On 3/15/24 6:31 AM, Sumit Garg wrote: > >>> On Thu, 14 Mar 2024 at 09:45, Marek Vasut wrote: > >>>> > >>>> On 3/12/24 8:03 AM, Sumit Garg wrote: > >>>>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be > >>>>> turned off for a single peripheral domain as it would negatively affect > >>>>> other peripheral domains. So lets just skip turning off bus power > >>>>> domain. > >>>> > >>>> What exactly is the issue and how did you trigger it ? > >>>> > >>>> Details please. > >>> > >>> I suppose the issue can be triggered via the "=> usb start => usb > >>> stop" sequence where one of the USB controllers is configured in > >>> peripheral mode. > >> > >> 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case > >> is more extensive ? > >> > >> Please, write down the necessary steps to reproduce this problem, and > >> what happens when that problem occurs. > > > > After digging in more, it looks like dev_power_domain_off() is never > > (U-Boot life-cycle) invoked for USB controller devices derived from > > DT. So this USB power domain sequence is never reachable. > > The imx8mp_hsiomix_off() is never called on 'usb stop' command ? > Yeah, that's the case. > But then why would the 'usb start ; usb stop' test break power domain > state here ? It won't break with current implementation, earlier I made this assumption that 'usb stop' turns down the power domain. > > > BTW, dev_power_domain_on() is invoked when USB controller devices are > > added based on DT. > > I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or > just before Linux boots . > > [...] > > >>>> Why not add counter into imx8mp_hsiomix_priv structure in this driver ? > >>> > >>> Sure I can do that but do you think the current approach can have any > >>> side effects? > >> > >> Bus domain not getting cycled (which can leave it in some odd state), > >> and increased power consumption if the next stage doesn't turn the > >> domain off. > > > > Given above, would you like me to drop power domain off path entirely > > here? > > Can the series go in without this patch ? Okay let me drop this patch. > > > I think if people are concerned about power consumption then it > > should be implemented properly in U-Boot to remove all the DT based > > devices before passing on control to the next stage. > > I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or > just before Linux boots (esp. at that point), so if you do not power off > the bus domain before booting Linux, you may hand over a device which > was not fully power cycled. Unfortunately that's the current situation I see. IMO, the better solution would be to just remove all the DT devices before passing on control to Linux. That should automatically power off devices. > > And sorry for the delay, I was a bit busy. No worries. -Sumit
Re: [PATCH v3 12/14] dts: sdm845-db845c: add u-boot fixups
On Wed, 20 Mar 2024 at 18:04, Caleb Connolly wrote: > > > > On 20/03/2024 12:33, Caleb Connolly wrote: > > > > > > On 19/03/2024 13:55, Sumit Garg wrote: > >> On Tue, 19 Mar 2024 at 17:52, Caleb Connolly > >> wrote: > >>> > >>> The USB VBUS supply for the type-A port is enabled via a GPIO regulator. > >>> This is incorrectly modelled in Linux where only the PCIe dependency is > >>> expressed. > >> > >> Can we send a fix for the Linux kernel DTS to correctly model it? We > >> can then later get rid of this modification once that is accepted. > > > > I spoke to Bjorn about this and apparently the correct way to model this > > will be to have a usb-connector node with a vbus-supply property. There > > is some work underway in Linux to support this kind of thing already. > > > > In the mean time he suggested to just make the regulator always-on, so I > > sent a patch to do that [1]. I actually hit this issue when booting from > > USB as the PCIe drivers aren't available in the initramfs, so USB never > > turns on, and the always-on hack fixes that. > > > > In the mean time, we'll still need this vbus-supply reference as U-Boot > > doesn't automatically probe regulators. > Try adding regulators_enable_boot_on() to the common board code. With that there shouldn't be any need for this vbus-supply reference. > oh, forgot the link! > > [1]: > https://lore.kernel.org/linux-arm-msm/20240320122515.3243711-1-caleb.conno...@linaro.org/ -Sumit
Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
Gentle ping..
On Fri, 15 Mar 2024 at 16:11, Sumit Garg wrote:
>
> On Fri, 15 Mar 2024 at 14:53, Marek Vasut wrote:
> >
> > On 3/15/24 6:31 AM, Sumit Garg wrote:
> > > On Thu, 14 Mar 2024 at 09:45, Marek Vasut wrote:
> > >>
> > >> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > >>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
> > >>> turned off for a single peripheral domain as it would negatively affect
> > >>> other peripheral domains. So lets just skip turning off bus power
> > >>> domain.
> > >>
> > >> What exactly is the issue and how did you trigger it ?
> > >>
> > >> Details please.
> > >
> > > I suppose the issue can be triggered via the "=> usb start => usb
> > > stop" sequence where one of the USB controllers is configured in
> > > peripheral mode.
> >
> > 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
> > is more extensive ?
> >
> > Please, write down the necessary steps to reproduce this problem, and
> > what happens when that problem occurs.
>
> After digging in more, it looks like dev_power_domain_off() is never
> (U-Boot life-cycle) invoked for USB controller devices derived from
> DT. So this USB power domain sequence is never reachable.
>
> BTW, dev_power_domain_on() is invoked when USB controller devices are
> added based on DT.
>
> >
> > >>> Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
> > >>> Signed-off-by: Sumit Garg
> > >>> ---
> > >>>drivers/power/domain/imx8mp-hsiomix.c | 6 +-
> > >>>1 file changed, 1 insertion(+), 5 deletions(-)
> > >>>
> > >>> diff --git a/drivers/power/domain/imx8mp-hsiomix.c
> > >>> b/drivers/power/domain/imx8mp-hsiomix.c
> > >>> index e2d772c5ec7..448746432a2 100644
> > >>> --- a/drivers/power/domain/imx8mp-hsiomix.c
> > >>> +++ b/drivers/power/domain/imx8mp-hsiomix.c
> > >>> @@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain
> > >>> *power_domain)
> > >>>
> > >>>ret = power_domain_on(domain);
> > >>>if (ret)
> > >>> - goto err_pd;
> > >>> + return ret;
> > >>>
> > >>>ret = clk_enable(>clk_usb);
> > >>>if (ret)
> > >>> @@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain
> > >>> *power_domain)
> > >>>
> > >>>err_clk:
> > >>>power_domain_off(domain);
> > >>> -err_pd:
> > >>> - power_domain_off(>pd_bus);
> > >>>return ret;
> > >>
> > >> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
> > >
> > > Sure I can do that but do you think the current approach can have any
> > > side effects?
> >
> > Bus domain not getting cycled (which can leave it in some odd state),
> > and increased power consumption if the next stage doesn't turn the
> > domain off.
>
> Given above, would you like me to drop power domain off path entirely
> here? I think if people are concerned about power consumption then it
> should be implemented properly in U-Boot to remove all the DT based
> devices before passing on control to the next stage.
How would you like me to proceed here?
-Sumit
Re: [PATCH v3 09/14] serial: msm-geni: support livetree
On Tue, 19 Mar 2024 at 17:52, Caleb Connolly wrote:
>
> When using OF_LIVE, the debug UART driver won't be probed if it's a
> subnode of the geni-se-qup controller. Add a NOP driver for the
> controller to correctly discover its child nodes.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> drivers/serial/serial_msm_geni.c | 13 +
> 1 file changed, 13 insertions(+)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/drivers/serial/serial_msm_geni.c
> b/drivers/serial/serial_msm_geni.c
> index 4aa0bc8c72bc..5260474fb9a4 100644
> --- a/drivers/serial/serial_msm_geni.c
> +++ b/drivers/serial/serial_msm_geni.c
> @@ -605,8 +605,21 @@ U_BOOT_DRIVER(serial_msm_geni) = {
> .ops = _serial_ops,
> .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
> };
>
> +static const struct udevice_id geniqup_ids[] = {
> + { .compatible = "qcom,geni-se-qup" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(geni_se_qup) = {
> + .name = "geni-se-qup",
> + .id = UCLASS_NOP,
> + .of_match = geniqup_ids,
> + .bind = dm_scan_fdt_dev,
> + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
> +};
> +
> #ifdef CONFIG_DEBUG_UART_MSM_GENI
>
> static struct msm_serial_data init_serial_data = {
> .base = CONFIG_VAL(DEBUG_UART_BASE)
>
> --
> 2.44.0
>
