Re: [U-Boot] [PATCH V2 1/2] GPIO: Tegra2: add GPIO driver for Tegra2
On Thu, Jun 2, 2011 at 2:34 PM, Wolfgang Denk w...@denx.de wrote: Dear Tom Warren, In message BANLkTi=w1u7q+w-vkrycq-wb50e7edf...@mail.gmail.com you wrote: Let me double-check. IIRC, one (cmd_gpio) didn't apply since it was from another SoC and didn't have the commands we use on Tegra, and the other (where the driver should go) ended with Mike saying i'm not sure sweating the location of the driver is important, so I've left it with the other GPIO drivers. What I'm referring to is the lots of duplicated code part. Actually, if you do a kompare between cmd_gpio.c and tegra2_gpio.c, there's virtually no 'duplicated' code, just 2 different implementations of do_gpio, with different args and parsing of params, etc. I use info, port, input and output, and cmd_gpio uses input, set, clear and toggle. Since cmd_gpio.c isn't built, it's not duplicating any code in the U-Boot binary, space-wise. So there's no advantage to using it instead of my own driver's cmd parser. Note that the PCA953x GPIO driver also does it's own cmd parsing in do_pca953x(). Tom Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Computers are not intelligent. They only think they are. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] mmc: Tegra2: SD/MMC driver for Seaboard - eMMC on SDMMC4, SDIO on SDMMC3
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra2/clk_rst.h |5 +
arch/arm/include/asm/arch-tegra2/pinmux.h |6 +
board/nvidia/common/board.c| 147
board/nvidia/common/board.h|1 +
drivers/mmc/Makefile |1 +
drivers/mmc/tegra2_mmc.c | 510
drivers/mmc/tegra2_mmc.h | 81 +
7 files changed, 751 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/tegra2_mmc.c
create mode 100644 drivers/mmc/tegra2_mmc.h
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h
b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index bd8ad2c..36e27b5 100644
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -191,4 +191,9 @@ struct clk_rst_ctlr {
#define CPCON (1 8)
+#define SWR_SDMMC4_RST (1 15)
+#define CLK_ENB_SDMMC4 (1 15)
+#define SWR_SDMMC3_RST (1 5)
+#define CLK_ENB_SDMMC3 (1 5)
+
#endif /* CLK_RST_H */
diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h
b/arch/arm/include/asm/arch-tegra2/pinmux.h
index 8b4bd8d..cce936d 100644
--- a/arch/arm/include/asm/arch-tegra2/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra2/pinmux.h
@@ -51,5 +51,11 @@ struct pmux_tri_ctlr {
#define Z_GMC (1 29)
#define Z_IRRX (1 20)
#define Z_IRTX (1 19)
+#define Z_GMA (1 28)
+#define Z_GME (1 0)
+#define Z_ATB (1 1)
+#define Z_SDB (1 15)
+#define Z_SDC (1 1)
+#define Z_SDD (1 2)
#endif /* PINMUX_H */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 3d6c248..627e061 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -32,6 +32,10 @@
#include asm/arch/uart.h
#include board.h
+#ifdef CONFIG_TEGRA2_MMC
+#include mmc.h
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
const struct tegra2_sysinfo sysinfo = {
@@ -171,6 +175,116 @@ static void pin_mux_uart(void)
}
/*
+ * Routine: clock_init_mmc
+ * Description: init the PLL and clocks for the SDMMC controllers
+ */
+static void clock_init_mmc(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* Do the SDMMC resets/clock enables */
+
+ /* Assert Reset to SDMMC4 */
+ reg = readl(clkrst-crc_rst_dev_l);
+ reg |= SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 1 */
+ writel(reg, clkrst-crc_rst_dev_l);
+
+ /* Enable clk to SDMMC4 */
+ reg = readl(clkrst-crc_clk_out_enb_l);
+ reg |= CLK_ENB_SDMMC4; /* CLK_ENB_SDMMC4 = 1 */
+ writel(reg, clkrst-crc_clk_out_enb_l);
+
+ /* Enable pllp_out0 to SDMMC4 */
+ reg = readl(clkrst-crc_clk_src_sdmmc4);
+ reg = 0x3F00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
+ reg |= (10 1); /* n-1, 11-1 shl 1 */
+ writel(reg, clkrst-crc_clk_src_sdmmc4);
+
+ /*
+* As per the Tegra2 TRM, section 5.3.4:
+* 'Wait 2 us for the clock to flush through the pipe/logic'
+*/
+ udelay(2);
+
+ /* De-assert reset to SDMMC4 */
+ reg = readl(clkrst-crc_rst_dev_l);
+ reg = ~SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 0 */
+ writel(reg, clkrst-crc_rst_dev_l);
+
+ /* Assert Reset to SDMMC3 */
+ reg = readl(clkrst-crc_rst_dev_u);
+ reg |= SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 1 */
+ writel(reg, clkrst-crc_rst_dev_u);
+
+ /* Enable clk to SDMMC3 */
+ reg = readl(clkrst-crc_clk_out_enb_u);
+ reg |= CLK_ENB_SDMMC3; /* CLK_ENB_SDMMC3 = 1 */
+ writel(reg, clkrst-crc_clk_out_enb_u);
+
+ /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
+ reg = readl(clkrst-crc_clk_src_sdmmc3);
+ reg = 0x3F00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
+ reg |= (10 1); /* n-1, 11-1 shl 1 */
+ writel(reg, clkrst-crc_clk_src_sdmmc3);
+
+ /* wait for 2us */
+ udelay(2);
+
+ /* De-assert reset to SDMMC3 */
+ reg = readl(clkrst-crc_rst_dev_u);
+ reg = ~SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 0 */
+ writel(reg, clkrst-crc_rst_dev_u);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+ struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 reg;
+
+ /* SDMMC4 */
+ /* config 2, x8 on 2nd set of pins */
+ reg = readl(pmt-pmt_ctl_a);
+ reg |= (3 16); /* ATB_SEL [17:16] = 11 SDIO4 */
+ writel(reg, pmt-pmt_ctl_a);
+ reg = readl(pmt-pmt_ctl_b);
+ reg |= (3 0);/* GMA_SEL [1:0] = 11 SDIO4 */
+ writel(reg, pmt-pmt_ctl_b);
+ reg = readl(pmt-pmt_ctl_d);
+ reg |= (3 0
[U-Boot] [PATCH 2/2] mmc: Tegra2: Enable SD/MMC driver for Seaboard and Harmony
Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/harmony.h | 11 +++ include/configs/seaboard.h | 11 +++ 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 34bd899..89e4911 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -47,4 +47,15 @@ #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA2_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 06ce3e2..7d29144 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -41,4 +41,15 @@ #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA2_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #endif /* __CONFIG_H */ -- 1.7.5.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: Tegra2: Add SPI driver for SPIFLASH on Seaboard
On Mon, May 2, 2011 at 4:16 PM, Mike Frysinger vap...@gentoo.org wrote: On Monday, May 02, 2011 19:06:51 Tom Warren wrote: Seaboard has a touchscreen on SPI1, but U-Boot doesn't care about that. fwiw, u-boot has splash screen support -mike Thanks, Mike. I'm talking touchscreen support. We'll be submitting LCD support for Tegra2 at a later date, so splash screens can be shown by ODMs, etc. Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: Tegra2: Add SPI driver for SPIFLASH on Seaboard
Mike,
On Fri, Apr 29, 2011 at 4:21 PM, Mike Frysinger vap...@gentoo.org wrote:
On Thursday, April 28, 2011 10:55:13 Tom Warren wrote:
Signed-off-by: Tom Warren twar...@nvidia.com
---
This patch adds support for the SPIFLASH peripheral on Tegra2 (SPI 1).
Probe, erase, read and write are all supported, as well as low-level
SPI commands via 'sspi'.
Note that, at this time, only Seaboard has a SPI flash part (Winbond).
With this code, I've written U-Boot to SPI from within U-Boot, and
booted the system from that SPI image (boot sel jumpers must be set
to SPI [1000], and the UART ENABLE jumper must be set to GPIO CTRL).
so this is a driver for a SPI bus, and the board you're working on just
happens to have some SPI flashes connected to it ? then the SPIFLASH part
is irrelevant, as is the board in question. please remove references to both
and just refer to this as a SPI driver for Tegra2 processors.
No, there are 4 general purpose SPI interfaces in Tegra2 (SLINK), and
1 dedicated SPI FLASH controller. From the Tegra2 TRM:
The Serial Flash interface (SFLASH) Controller interfaces Tegra 2 to
SPI-capable devices such as Flash
memories and ADC/DAC devices. Tegra 2 supports only master mode of SPI
operation on this interface.
This interface is specifically intended for serial flash and similar
devices. For a general purpose SPI
interface, use the SLINK serial interface.
The register sets are similar, but not identical.
As to the board reference, it's in my comments so people wishing to
use this will know that only Seaboard is available w/a SPI chip -
there's no provision for that on the Harmony board.
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
if the only thing that uses this is the spi driver, then please put this in
drivers/spi/tegra2_spi.h
Will do.
+#define SPI_CMD_GO (1 30)
dont put a tab after the #define
OK. I'll fix 'em up.
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
this change needs to be split out into a dedicated one
-
this new line should not be deleted
+#if defined(CONFIG_CMD_SPI)
+#include spi.h
+#endif
no need to protect the inclusion. just always include it.
OK.
#endif
-
#if defined(CONFIG_CMD_NAND)
nor should this newline be deleted
puts (NAND: );
nand_init(); /* go init the NAND */
#endif
-
+#if defined(CONFIG_CMD_SPI)
nor this newline
I'm going to remove these changes from arm/lib/board.c and move
spi_init() to our common board file (nvidia/common/board.c.
+int spi_claim_bus(struct spi_slave *slave)
+{
+ /* Move bulk of spi_init code here? */
yes, so do that
OK, I'll look into that.
+void spi_release_bus(struct spi_slave *slave)
+{
this func should be disabling the spi bus
OK, I'll look into that, too.
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr
*)NV_PA_APB_MISC_BASE;
+ struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE;
+ u32 val;
+
+ /*
+ * Delay here to clean up comms - spurious chars seen around SPI xfers.
+ * Fine-tune later.
+ */
+ udelay(1000);
fine tune now ?
The comment went in during development, and the 1000 values is the
final fine-tuned value (1ms). So I'll change the comment.
+ /*
+ * On Seaboard, MOSI/MISO are shared w/UART.
+ * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity.
+ * Enable UART later (cs_deactivate) so we can use it for U-Boot comms.
+ */
+ gpio_direction_output(UART_DISABLE_GPIO, 1);
board specific issues shouldnt be in a processor driver.
Please explain what you mean by a processor driver. This does need an
ifdef, so any future board that doesn't have Seaboard's defiency of a
muxed SPIFLASH/UART won't have to mess with a GPIO, but for Seaboard,
we have to dynamically change GPIO_PI3 every SPI transaction to ensure
UART spew can continue (in DEBUG builds, etc.).
+ int numBytes = (bitlen + 7) / 8;
no camel case. use num_bytes.
Sure, will do. This came over from the driver I ported from.
+ for (i = 0; i bytes; ++i) {
+ ((u8 *)din)[i] = (tmpdin
24);
create a dedicated pointer and deference that. casts on the lhs are poor
style.
Again, this was in the driver source I used as a porting reference.
I'll change it.
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
this should be split out into a dedicated patch
OK.
Thanks,
Tom
-mike
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] GPIO: Tegra2: add GPIO driver for Seaboard and Harmony
Mike, On Fri, Apr 29, 2011 at 4:22 PM, Mike Frysinger vap...@gentoo.org wrote: same as the SPI patch, if this is a driver for GPIO hardware on a processor, then it should be labeled as such. do not mention specific boards. OK. I'll change the comments. changes that update board config headers to enable the new driver should be split out into a dedicated patch. Will do. Thanks, Tom -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 0/2] GPIO: Tegra2: add GPIO driver for Tegra2
This patchset adds a GPIO driver for Tegra2 SoC, and enables it for all boards Changes in V2: - use 'gpio_pin' enum in gpio.h (Simon Glass review request) - change 'GPIO_PORT8' to 'GPIO_FULLPORT' (Simon Glass request) - change 'offset' to 'pin' globally - enable GPIO for all boards (tegra2-common.h) Tom Warren (2): GPIO: Tegra2: add GPIO driver for Tegra2 arm: Tegra2: GPIO: enable GPIO for Tegra2 boards arch/arm/include/asm/arch-tegra2/gpio.h | 244 - drivers/gpio/Makefile |1 + drivers/gpio/tegra2_gpio.c | 299 +++ include/configs/tegra2-common.h |2 + 4 files changed, 539 insertions(+), 7 deletions(-) create mode 100644 drivers/gpio/tegra2_gpio.c -- 1.7.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 1/2] GPIO: Tegra2: add GPIO driver for Tegra2
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes in V2:
- use 'gpio_pin' enum in gpio.h (Simon Glass review request)
- change 'GPIO_PORT8' to 'GPIO_FULLPORT' (Simon Glass request)
- change 'offset' to 'pin' globally
arch/arm/include/asm/arch-tegra2/gpio.h | 244 -
drivers/gpio/Makefile |1 +
drivers/gpio/tegra2_gpio.c | 299 +++
3 files changed, 537 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpio/tegra2_gpio.c
diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h
b/arch/arm/include/asm/arch-tegra2/gpio.h
index 0fb8f0d..e55305a 100644
--- a/arch/arm/include/asm/arch-tegra2/gpio.h
+++ b/arch/arm/include/asm/arch-tegra2/gpio.h
@@ -45,15 +45,245 @@ struct gpio_ctlr {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-#define GPIO_BANK(x) ((x) 5)
-#define GPIO_PORT(x) (((x) 3) 0x3)
-#define GPIO_BIT(x)((x) 0x7)
+#define GPIO_BANK(x) ((x) 5)
+#define GPIO_PORT(x) (((x) 3) 0x3)
+#define GPIO_FULLPORT(x) ((x) 3)
+#define GPIO_BIT(x)((x) 0x7)
+
+enum gpio_pin {
+ GPIO_PA0 = 0, /* pin 0 */
+ GPIO_PA1,
+ GPIO_PA2,
+ GPIO_PA3,
+ GPIO_PA4,
+ GPIO_PA5,
+ GPIO_PA6,
+ GPIO_PA7,
+ GPIO_PB0, /* pin 8 */
+ GPIO_PB1,
+ GPIO_PB2,
+ GPIO_PB3,
+ GPIO_PB4,
+ GPIO_PB5,
+ GPIO_PB6,
+ GPIO_PB7,
+ GPIO_PC0, /* pin 16 */
+ GPIO_PC1,
+ GPIO_PC2,
+ GPIO_PC3,
+ GPIO_PC4,
+ GPIO_PC5,
+ GPIO_PC6,
+ GPIO_PC7,
+ GPIO_PD0, /* pin 24 */
+ GPIO_PD1,
+ GPIO_PD2,
+ GPIO_PD3,
+ GPIO_PD4,
+ GPIO_PD5,
+ GPIO_PD6,
+ GPIO_PD7,
+ GPIO_PE0, /* pin 32 */
+ GPIO_PE1,
+ GPIO_PE2,
+ GPIO_PE3,
+ GPIO_PE4,
+ GPIO_PE5,
+ GPIO_PE6,
+ GPIO_PE7,
+ GPIO_PF0, /* pin 40 */
+ GPIO_PF1,
+ GPIO_PF2,
+ GPIO_PF3,
+ GPIO_PF4,
+ GPIO_PF5,
+ GPIO_PF6,
+ GPIO_PF7,
+ GPIO_PG0, /* pin 48 */
+ GPIO_PG1,
+ GPIO_PG2,
+ GPIO_PG3,
+ GPIO_PG4,
+ GPIO_PG5,
+ GPIO_PG6,
+ GPIO_PG7,
+ GPIO_PH0, /* pin 56 */
+ GPIO_PH1,
+ GPIO_PH2,
+ GPIO_PH3,
+ GPIO_PH4,
+ GPIO_PH5,
+ GPIO_PH6,
+ GPIO_PH7,
+ GPIO_PI0, /* pin 64 */
+ GPIO_PI1,
+ GPIO_PI2,
+ GPIO_PI3,
+ GPIO_PI4,
+ GPIO_PI5,
+ GPIO_PI6,
+ GPIO_PI7,
+ GPIO_PJ0, /* pin 72 */
+ GPIO_PJ1,
+ GPIO_PJ2,
+ GPIO_PJ3,
+ GPIO_PJ4,
+ GPIO_PJ5,
+ GPIO_PJ6,
+ GPIO_PJ7,
+ GPIO_PK0, /* pin 80 */
+ GPIO_PK1,
+ GPIO_PK2,
+ GPIO_PK3,
+ GPIO_PK4,
+ GPIO_PK5,
+ GPIO_PK6,
+ GPIO_PK7,
+ GPIO_PL0, /* pin 88 */
+ GPIO_PL1,
+ GPIO_PL2,
+ GPIO_PL3,
+ GPIO_PL4,
+ GPIO_PL5,
+ GPIO_PL6,
+ GPIO_PL7,
+ GPIO_PM0, /* pin 96 */
+ GPIO_PM1,
+ GPIO_PM2,
+ GPIO_PM3,
+ GPIO_PM4,
+ GPIO_PM5,
+ GPIO_PM6,
+ GPIO_PM7,
+ GPIO_PN0, /* pin 104 */
+ GPIO_PN1,
+ GPIO_PN2,
+ GPIO_PN3,
+ GPIO_PN4,
+ GPIO_PN5,
+ GPIO_PN6,
+ GPIO_PN7,
+ GPIO_PO0, /* pin 112 */
+ GPIO_PO1,
+ GPIO_PO2,
+ GPIO_PO3,
+ GPIO_PO4,
+ GPIO_PO5,
+ GPIO_PO6,
+ GPIO_PO7,
+ GPIO_PP0, /* pin 120 */
+ GPIO_PP1,
+ GPIO_PP2,
+ GPIO_PP3,
+ GPIO_PP4,
+ GPIO_PP5,
+ GPIO_PP6,
+ GPIO_PP7,
+ GPIO_PQ0, /* pin 128 */
+ GPIO_PQ1,
+ GPIO_PQ2,
+ GPIO_PQ3,
+ GPIO_PQ4,
+ GPIO_PQ5,
+ GPIO_PQ6,
+ GPIO_PQ7,
+ GPIO_PR0, /* pin 136 */
+ GPIO_PR1,
+ GPIO_PR2,
+ GPIO_PR3,
+ GPIO_PR4,
+ GPIO_PR5,
+ GPIO_PR6,
+ GPIO_PR7,
+ GPIO_PS0, /* pin 144 */
+ GPIO_PS1,
+ GPIO_PS2,
+ GPIO_PS3,
+ GPIO_PS4,
+ GPIO_PS5,
+ GPIO_PS6,
+ GPIO_PS7,
+ GPIO_PT0, /* pin 152 */
+ GPIO_PT1,
+ GPIO_PT2,
+ GPIO_PT3,
+ GPIO_PT4,
+ GPIO_PT5,
+ GPIO_PT6,
+ GPIO_PT7,
+ GPIO_PU0, /* pin 160 */
+ GPIO_PU1,
+ GPIO_PU2,
+ GPIO_PU3,
+ GPIO_PU4,
+ GPIO_PU5,
+ GPIO_PU6,
+ GPIO_PU7,
+ GPIO_PV0, /* pin 168 */
+ GPIO_PV1,
+ GPIO_PV2,
+ GPIO_PV3,
+ GPIO_PV4,
+ GPIO_PV5,
+ GPIO_PV6,
+ GPIO_PV7,
+ GPIO_PW0, /* pin 176 */
+ GPIO_PW1,
+ GPIO_PW2,
+ GPIO_PW3,
+ GPIO_PW4,
+ GPIO_PW5,
+ GPIO_PW6,
+ GPIO_PW7,
+ GPIO_PX0, /* pin 184 */
+ GPIO_PX1
[U-Boot] [PATCH V2 2/2] arm: Tegra2: GPIO: enable GPIO for Tegra2 boards
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes in V2: - enable GPIO for all boards (tegra2-common.h) include/configs/tegra2-common.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index febce35..5260d1f 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -160,4 +160,6 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) +#define CONFIG_TEGRA2_GPIO +#define CONFIG_CMD_TEGRA2_GPIO_INFO #endif /* __TEGRA2_COMMON_H */ -- 1.7.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: Tegra2: Add SPI driver for SPIFLASH on Seaboard
Mike,
On Mon, May 2, 2011 at 2:26 PM, Mike Frysinger vap...@gentoo.org wrote:
On Monday, May 02, 2011 11:33:24 Tom Warren wrote:
On Fri, Apr 29, 2011 at 4:21 PM, Mike Frysinger wrote:
On Thursday, April 28, 2011 10:55:13 Tom Warren wrote:
This patch adds support for the SPIFLASH peripheral on Tegra2 (SPI 1).
Probe, erase, read and write are all supported, as well as low-level
SPI commands via 'sspi'.
Note that, at this time, only Seaboard has a SPI flash part (Winbond).
With this code, I've written U-Boot to SPI from within U-Boot, and
booted the system from that SPI image (boot sel jumpers must be set
to SPI [1000], and the UART ENABLE jumper must be set to GPIO CTRL).
so this is a driver for a SPI bus, and the board you're working on just
happens to have some SPI flashes connected to it ? then the SPIFLASH
part is irrelevant, as is the board in question. please remove
references to both and just refer to this as a SPI driver for Tegra2
processors.
No, there are 4 general purpose SPI interfaces in Tegra2 (SLINK), and
1 dedicated SPI FLASH controller. From the Tegra2 TRM:
The Serial Flash interface (SFLASH) Controller interfaces Tegra 2 to
SPI-capable devices such as Flash
memories and ADC/DAC devices. Tegra 2 supports only master mode of SPI
operation on this interface.
This interface is specifically intended for serial flash and similar
devices. For a general purpose SPI
interface, use the SLINK serial interface.
The register sets are similar, but not identical.
do you plan on writing a driver for the SLINK logic ? would it be a new file,
or would you keep the two integrated ? if diff files, i'd name this one
tegra2_sflash_spi.c. if you keep them merged, then tegra2_spi.c is fine.
No plan to write SLINK drivers for U-Boot. Seaboard has a touchscreen
on SPI1, but U-Boot doesn't care about that.
So I'll keep it tegra2_spi.c for now.
As to the board reference, it's in my comments so people wishing to
use this will know that only Seaboard is available w/a SPI chip -
there's no provision for that on the Harmony board.
generally, processor drivers are not concerned with board issues. if you want
to document board-specific issues somewhere, add a doc/README.boardname.
Good idea. I'll gen one up for Seaboard.
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
+#if defined(CONFIG_CMD_SPI)
I'm going to remove these changes from arm/lib/board.c and move
spi_init() to our common board file (nvidia/common/board.c.
i dont think you want to do this. other than the style changes, and needing a
sep changeset, having the arm board.c file call spi_init() is desirable.
OK. I'll fix up arm board.c with your comments in mind and put it in a
separate patch.
+ * On Seaboard, MOSI/MISO are shared w/UART.
+ * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI
activity.
+ * Enable UART later (cs_deactivate) so we can use it
for U-Boot comms.
+ gpio_direction_output(UART_DISABLE_GPIO, 1);
board specific issues shouldnt be in a processor driver.
Please explain what you mean by a processor driver.
you're writing a driver for the Tegra2 SoC. that is the only thing this
driver should be doing. that means no board-specific logic is allowed.
This does need an
ifdef, so any future board that doesn't have Seaboard's defiency of a
muxed SPIFLASH/UART won't have to mess with a GPIO, but for Seaboard,
we have to dynamically change GPIO_PI3 every SPI transaction to ensure
UART spew can continue (in DEBUG builds, etc.).
right, this is a board-specific issue. thus it doesnt belong in a driver that
is only concerned with the Tegra2 SoC.
what you could do is:
void spi_init_common(void) { ... only tegra2 code ... }
void spi_init(void) __attribute__((weak, alias(spi_init_common)));
and then in the seaboard directory, add:
void spi_init(void)
{
... do random gpio/portmux stuff ...
spi_init_common();
}
or another style would be to:
extern void spi_board_init(void) __weak;
void spi_init(void)
{
if (spi_board_init())
spi_board_init();
... only tegra2 code ...
}
and then in the seaboard directory, add:
void spi_board_init(void)
{
... do random gpio/portmux stuff ...
}
I'll try out these ideas. Thanks.
Tom
-mike
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 1/2] GPIO: Tegra2: add GPIO driver for Tegra2
Mike, On Mon, May 2, 2011 at 4:15 PM, Mike Frysinger vap...@gentoo.org wrote: On Monday, May 02, 2011 18:45:47 Tom Warren wrote: +U_BOOT_CMD( + gpio, 5, 1, do_gpio, looks to me like you're duplicating a lot of code that already exists in common/cmd_gpio.c -mike Possible - this was ported from another GPIO driver back in v2009.11 days. I'll take a look at cmd_gpio.c. Thanks, Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] spi: Tegra2: Add SPI driver for SPIFLASH on Seaboard
Signed-off-by: Tom Warren twar...@nvidia.com
---
This patch adds support for the SPIFLASH peripheral on Tegra2 (SPI 1).
Probe, erase, read and write are all supported, as well as low-level
SPI commands via 'sspi'.
Note that, at this time, only Seaboard has a SPI flash part (Winbond).
With this code, I've written U-Boot to SPI from within U-Boot, and
booted the system from that SPI image (boot sel jumpers must be set
to SPI [1000], and the UART ENABLE jumper must be set to GPIO CTRL).
arch/arm/include/asm/arch-tegra2/tegra2_spi.h | 79 ++
arch/arm/lib/board.c | 10 +-
drivers/spi/Makefile |1 +
drivers/spi/tegra2_spi.c | 335 +
include/configs/seaboard.h| 10 +
5 files changed, 432 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2_spi.h
create mode 100644 drivers/spi/tegra2_spi.c
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
new file mode 100644
index 000..5ab2a2a
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
@@ -0,0 +1,79 @@
+/*
+ * NVIDIA Tegra2 SPI-FLASH controller
+ *
+ * Copyright 2010-2011 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_SPI_H_
+#define _TEGRA2_SPI_H_
+
+#include asm/types.h
+
+#define TEGRA2_SPI_BASE0x7000C380
+
+struct spi_tegra {
+ u32 command;/* SPI_COMMAND_0 register */
+ u32 status; /* SPI_STATUS_0 register */
+ u32 rx_cmp; /* SPI_RX_CMP_0 register */
+ u32 dma_ctl;/* SPI_DMA_CTL_0 register */
+ u32 tx_fifo;/* SPI_TX_FIFO_0 register */
+ u32 rsvd[3];/* offsets 0x14 to 0x1F reserved */
+ u32 rx_fifo;/* SPI_RX_FIFO_0 register */
+
+};
+
+#defineSPI_CMD_GO (1 30)
+#defineSPI_CMD_ACTIVE_SCLK (1 26)
+#defineSPI_CMD_CK_SDA (1 21)
+#defineSPI_CMD_ACTIVE_SDA (1 18)
+#defineSPI_CMD_CS_POL (1 16)
+#defineSPI_CMD_TXEN(1 15)
+#defineSPI_CMD_RXEN(1 14)
+#defineSPI_CMD_CS_VAL (1 13)
+#defineSPI_CMD_CS_SOFT (1 12)
+#defineSPI_CMD_CS_DELAY(1 9)
+#defineSPI_CMD_CS3_EN (1 8)
+#defineSPI_CMD_CS2_EN (1 7)
+#defineSPI_CMD_CS1_EN (1 6)
+#defineSPI_CMD_CS0_EN (1 5)
+#defineSPI_CMD_BIT_LENGTH (1 4)
+#defineSPI_CMD_BIT_LENGTH_MASK 0x001F
+
+#defineSPI_STAT_BSY(1 31)
+#defineSPI_STAT_RDY(1 30)
+#defineSPI_STAT_RXF_FLUSH (1 29)
+#defineSPI_STAT_TXF_FLUSH (1 28)
+#defineSPI_STAT_RXF_UNR(1 27)
+#defineSPI_STAT_TXF_OVF(1 26)
+#defineSPI_STAT_RXF_EMPTY (1 25)
+#defineSPI_STAT_RXF_FULL (1 24)
+#defineSPI_STAT_TXF_EMPTY (1 23)
+#defineSPI_STAT_TXF_FULL (1 22)
+#defineSPI_STAT_SEL_TXRX_N (1 16)
+#defineSPI_STAT_CUR_BLKCNT (1 15)
+
+#define SWR_SPI1_RST (1 11)
+#define CLK_ENB_SPI1 (1 11)
+#define GMD_SEL_SFLASH (3 30)
+#define GMC_SEL_SFLASH (3 2)
+#define Z_LSPI (1 0)
+
+#endif /* _TEGRA2_SPI_H_ */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index dc46e21..feb2e6b 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -60,7 +60,9 @@
#ifdef CONFIG_DRIVER_LAN91C96
#include ../drivers/net/lan91c96.h
#endif
-
+#if defined(CONFIG_CMD_SPI)
+#include spi.h
+#endif
DECLARE_GLOBAL_DATA_PTR;
ulong monitor_flash_len;
@@ -506,12 +508,14 @@ void board_init_r (gd_t *id, ulong dest_addr)
hang ();
}
#endif
-
#if defined(CONFIG_CMD_NAND)
puts (NAND: );
nand_init();/* go init the NAND */
#endif
-
+#if defined(CONFIG_CMD_SPI)
+ puts(SPI: );
+ spi_init();
+#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
#endif
diff --git a/drivers/spi/Makefile b/drivers/spi
Re: [U-Boot] [PATCH] GPIO: Tegra2: add GPIO driver for Seaboard and Harmony
On Mon, Apr 18, 2011 at 2:11 PM, Tom Warren twarren.nvi...@gmail.com wrote: Signed-off-by: Tom Warren twar...@nvidia.com --- arch/arm/include/asm/arch-tegra2/gpio.h | 236 - drivers/gpio/Makefile | 1 + drivers/gpio/tegra2_gpio.c | 301 +++ include/configs/harmony.h | 3 + include/configs/seaboard.h | 3 + 5 files changed, 540 insertions(+), 4 deletions(-) snip Can someone please review this? We need it for the (just posted) SPI driver on Seaboard. Thanks! Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] GPIO: Tegra2: add GPIO driver for Seaboard and Harmony
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra2/gpio.h | 236 -
drivers/gpio/Makefile |1 +
drivers/gpio/tegra2_gpio.c | 301 +++
include/configs/harmony.h |3 +
include/configs/seaboard.h |3 +
5 files changed, 540 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpio/tegra2_gpio.c
diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h
b/arch/arm/include/asm/arch-tegra2/gpio.h
index 0fb8f0d..0d7d7f8 100644
--- a/arch/arm/include/asm/arch-tegra2/gpio.h
+++ b/arch/arm/include/asm/arch-tegra2/gpio.h
@@ -47,13 +47,241 @@ struct gpio_ctlr {
#define GPIO_BANK(x) ((x) 5)
#define GPIO_PORT(x) (((x) 3) 0x3)
+#define GPIO_PORT8(x) ((x) 3)
#define GPIO_BIT(x)((x) 0x7)
+#define GPIO_PA00 /* port A (0), pin 0 */
+#define GPIO_PA11
+#define GPIO_PA22
+#define GPIO_PA33
+#define GPIO_PA44
+#define GPIO_PA55
+#define GPIO_PA66
+#define GPIO_PA77
+#define GPIO_PB08
+#define GPIO_PB19
+#define GPIO_PB210
+#define GPIO_PB311
+#define GPIO_PB412
+#define GPIO_PB513
+#define GPIO_PB614
+#define GPIO_PB715
+#define GPIO_PC016
+#define GPIO_PC117
+#define GPIO_PC218
+#define GPIO_PC319
+#define GPIO_PC420
+#define GPIO_PC521
+#define GPIO_PC622
+#define GPIO_PC723
+#define GPIO_PD024
+#define GPIO_PD125
+#define GPIO_PD226
+#define GPIO_PD327
+#define GPIO_PD428
+#define GPIO_PD529
+#define GPIO_PD630
+#define GPIO_PD731
+#define GPIO_PE032
+#define GPIO_PE133
+#define GPIO_PE234
+#define GPIO_PE335
+#define GPIO_PE436
+#define GPIO_PE537
+#define GPIO_PE638
+#define GPIO_PE739
+#define GPIO_PF040
+#define GPIO_PF141
+#define GPIO_PF242
+#define GPIO_PF343
+#define GPIO_PF444
+#define GPIO_PF545
+#define GPIO_PF646
+#define GPIO_PF747
+#define GPIO_PG048
+#define GPIO_PG149
+#define GPIO_PG250
+#define GPIO_PG351
+#define GPIO_PG452
+#define GPIO_PG553
+#define GPIO_PG654
+#define GPIO_PG755
+#define GPIO_PH056
+#define GPIO_PH157
+#define GPIO_PH258
+#define GPIO_PH359
+#define GPIO_PH460
+#define GPIO_PH561
+#define GPIO_PH662
+#define GPIO_PH763
+#define GPIO_PI064
+#define GPIO_PI165
+#define GPIO_PI266
+#define GPIO_PI367
+#define GPIO_PI468
+#define GPIO_PI569
+#define GPIO_PI670
+#define GPIO_PI771
+#define GPIO_PJ072
+#define GPIO_PJ173
+#define GPIO_PJ274
+#define GPIO_PJ375
+#define GPIO_PJ476
+#define GPIO_PJ577
+#define GPIO_PJ678
+#define GPIO_PJ779
+#define GPIO_PK080
+#define GPIO_PK181
+#define GPIO_PK282
+#define GPIO_PK383
+#define GPIO_PK484
+#define GPIO_PK585
+#define GPIO_PK686
+#define GPIO_PK787
+#define GPIO_PL088
+#define GPIO_PL189
+#define GPIO_PL290
+#define GPIO_PL391
+#define GPIO_PL492
+#define GPIO_PL593
+#define GPIO_PL694
+#define GPIO_PL795
+#define GPIO_PM096
+#define GPIO_PM197
+#define GPIO_PM298
+#define GPIO_PM399
+#define GPIO_PM4100
+#define GPIO_PM5101
+#define GPIO_PM6102
+#define GPIO_PM7103
+#define GPIO_PN0104
+#define GPIO_PN1105
+#define GPIO_PN2106
+#define GPIO_PN3107
+#define GPIO_PN4108
+#define GPIO_PN5109
+#define GPIO_PN6110
+#define GPIO_PN7111
+#define GPIO_PO0112
+#define GPIO_PO1113
+#define GPIO_PO2114
+#define GPIO_PO3115
+#define GPIO_PO4116
+#define GPIO_PO5117
+#define GPIO_PO6118
+#define GPIO_PO7119
+#define GPIO_PP0120
+#define GPIO_PP1121
+#define GPIO_PP2122
+#define GPIO_PP3123
+#define GPIO_PP4124
+#define GPIO_PP5125
+#define GPIO_PP6126
+#define GPIO_PP7127
+#define GPIO_PQ0128
+#define GPIO_PQ1129
+#define GPIO_PQ2130
+#define GPIO_PQ3131
+#define GPIO_PQ4132
+#define GPIO_PQ5133
+#define GPIO_PQ6134
+#define GPIO_PQ7135
+#define GPIO_PR0136
+#define GPIO_PR1137
+#define GPIO_PR2138
+#define GPIO_PR3139
+#define GPIO_PR4140
+#define GPIO_PR5141
+#define GPIO_PR6142
+#define GPIO_PR7143
+#define GPIO_PS0144
+#define GPIO_PS1145
+#define GPIO_PS2146
+#define GPIO_PS3147
+#define GPIO_PS4148
+#define GPIO_PS5149
+#define GPIO_PS6150
+#define GPIO_PS7151
+#define GPIO_PT0152
+#define GPIO_PT1153
+#define GPIO_PT2154
+#define GPIO_PT3155
+#define GPIO_PT4156
+#define GPIO_PT5157
+#define GPIO_PT6158
+#define GPIO_PT7159
+#define GPIO_PU0160
+#define GPIO_PU1161
+#define GPIO_PU2162
+#define GPIO_PU3163
+#define GPIO_PU4164
+#define GPIO_PU5165
+#define GPIO_PU6166
+#define GPIO_PU7167
+#define GPIO_PV0
[U-Boot] [PATCH V2 1/3] arm: Tegra2: Add missing PLLX init
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/cpu/armv7/tegra2/ap20.c | 29
arch/arm/include/asm/arch-tegra2/clk_rst.h |6 +++-
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index d3e6797..60dd5df 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -32,6 +32,32 @@
u32 s_first_boot = 1;
+void init_pllx(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* If PLLX is already enabled, just return */
+ reg = readl(clkrst-crc_pllx_base);
+ if (reg PLL_ENABLE)
+ return;
+
+ /* Set PLLX_MISC */
+ reg = CPCON;/* CPCON[11:8] = 0001 */
+ writel(reg, clkrst-crc_pllx_misc);
+
+ /* Use 12MHz clock here */
+ reg = (PLL_BYPASS | PLL_DIVM);
+ reg |= (1000 8); /* DIVN = 0x3E8 */
+ writel(reg, clkrst-crc_pllx_base);
+
+ reg |= PLL_ENABLE;
+ writel(reg, clkrst-crc_pllx_base);
+
+ reg = ~PLL_BYPASS;
+ writel(reg, clkrst-crc_pllx_base);
+}
+
static void enable_cpu_clock(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
@@ -47,6 +73,9 @@ static void enable_cpu_clock(int enable)
*/
if (enable) {
+ /* Initialize PLLX */
+ init_pllx();
+
/* Wait until all clocks are stable */
udelay(PLL_STABILIZATION_DELAY);
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h
b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index d67a5d7..bd8ad2c 100644
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -160,8 +160,8 @@ struct clk_rst_ctlr {
#define PLL_DIVP (1 20) /* post divider, b22:20 */
#define PLL_DIVM 0x0C/* input divider, b4:0 */
-#define SWR_UARTD_RST (1 2)
-#define CLK_ENB_UARTD (1 2)
+#define SWR_UARTD_RST (1 1)
+#define CLK_ENB_UARTD (1 1)
#define SWR_UARTA_RST (1 6)
#define CLK_ENB_UARTA (1 6)
@@ -189,4 +189,6 @@ struct clk_rst_ctlr {
#define CPU0_CLK_STP (1 8)
#define CPU1_CLK_STP (1 9)
+#define CPCON (1 8)
+
#endif /* CLK_RST_H */
--
1.7.4.3
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 0/3] Fix hang when loading U-Boot from SPI or NAND
This series of patches fixes a hang seen when loading U-Boot from SPI or NAND on Seaboard and Harmony due to a missing PLLX init. It also corrects a UARTD bit error in clk_rst.h, and adds rudimentary GPIO support so that the UART on Seaboard can be used by U-Boot (UARTD SPIFLASH are muxed, and the default POR setting is for SPI access, so GPIO_PI3 has to be driven low to enable serial console I/O over UARTD). Harmony has no SPIFLASH, so the issue doesn't exist there. With these changes, I can write U-Boot to SPI on Seaboard and boot with it to the U-Boot cmd prompt. This should also apply to loading from NAND on Seaboard and Harmony - testing to follow. Changes in V2: - Change 2nd patch's description to 'Add basic GPIO definitions' - Add more descriptive comment for CPCON use in init_pllx Tom Warren (3): arm: Tegra2: Add missing PLLX init arm: Tegra2: GPIO: Add basic GPIO definitions arm: Tegra2: Move clk/mux init to board_early_init_f, add GPIO init arch/arm/cpu/armv7/tegra2/ap20.c | 29 ++ arch/arm/include/asm/arch-tegra2/clk_rst.h |6 ++- arch/arm/include/asm/arch-tegra2/gpio.h| 59 arch/arm/include/asm/arch-tegra2/tegra2.h |1 + board/nvidia/common/board.c| 32 ++- board/nvidia/common/board.h|4 ++ board/nvidia/harmony/Makefile |1 + board/nvidia/harmony/harmony.c | 34 board/nvidia/seaboard/Makefile |1 + board/nvidia/seaboard/seaboard.c | 52 10 files changed, 206 insertions(+), 13 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h create mode 100644 board/nvidia/harmony/harmony.c create mode 100644 board/nvidia/seaboard/seaboard.c -- 1.7.4.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 2/3] arm: Tegra2: GPIO: Add basic GPIO definitions
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra2/gpio.h | 59 +
arch/arm/include/asm/arch-tegra2/tegra2.h |1 +
2 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h
diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h
b/arch/arm/include/asm/arch-tegra2/gpio.h
new file mode 100644
index 000..0fb8f0d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/gpio.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_GPIO_H_
+#define _TEGRA2_GPIO_H_
+
+/*
+ * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* The number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* The number of banks */
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#define GPIO_BANK(x) ((x) 5)
+#define GPIO_PORT(x) (((x) 3) 0x3)
+#define GPIO_BIT(x)((x) 0x7)
+
+/*
+ * GPIO_PI3 = Port I = 8, bit = 3.
+ * Seaboard: used for UART/SPI selection
+ * Harmony: not used
+ */
+#define GPIO_PI3 ((8 3) | 3)
+
+#endif /* TEGRA2_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h
b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 7b0f5cc..742a75a 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -30,6 +30,7 @@
#define NV_PA_TMRUS_BASE 0x60005010
#define NV_PA_CLK_RST_BASE 0x60006000
#define NV_PA_FLOW_BASE0x60007000
+#define NV_PA_GPIO_BASE0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE0x7000
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
--
1.7.4.3
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 3/3] arm: Tegra2: Move clk/mux init to board_early_init_f, add GPIO init
Signed-off-by: Tom Warren twar...@nvidia.com
---
board/nvidia/common/board.c | 32 +++
board/nvidia/common/board.h |4 +++
board/nvidia/harmony/Makefile|1 +
board/nvidia/harmony/harmony.c | 34
board/nvidia/seaboard/Makefile |1 +
board/nvidia/seaboard/seaboard.c | 52 ++
6 files changed, 113 insertions(+), 11 deletions(-)
create mode 100644 board/nvidia/harmony/harmony.c
create mode 100644 board/nvidia/seaboard/seaboard.c
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 5edd70f..3d6c248 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -41,7 +41,16 @@ const struct tegra2_sysinfo sysinfo = {
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
- debug(Board Early Init\n);
+ /* Initialize periph clocks */
+ clock_init();
+
+ /* Initialize periph pinmuxes */
+ pinmux_init();
+
+ /* Initialize periph GPIOs */
+ gpio_init();
+
+ /* Init UART, scratch regs, and start CPU */
tegra2_start();
return 0;
}
@@ -64,10 +73,10 @@ int timer_init(void)
static void clock_init_uart(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- static int pllp_init_done;
u32 reg;
- if (!pllp_init_done) {
+ reg = readl(clkrst-crc_pllp_base);
+ if (!(reg PLL_BASE_OVRRIDE)) {
/* Override pllp setup for 216MHz operation. */
reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) 8) | PLL_DIVM);
@@ -78,8 +87,6 @@ static void clock_init_uart(void)
reg = ~PLL_BYPASS;
writel(reg, clkrst-crc_pllp_base);
-
- pllp_init_done++;
}
/* Now do the UART reset/clock enable */
@@ -182,6 +189,15 @@ void pinmux_init(void)
}
/*
+ * Routine: gpio_init
+ * Description: Do individual peripheral GPIO configs
+ */
+void gpio_init(void)
+{
+ gpio_config_uart();
+}
+
+/*
* Routine: board_init
* Description: Early hardware init.
*/
@@ -192,11 +208,5 @@ int board_init(void)
/* board id for Linux */
gd-bd-bi_arch_number = CONFIG_MACH_TYPE;
- /* Initialize peripheral clocks */
- clock_init();
-
- /* Initialize periph pinmuxes */
- pinmux_init();
-
return 0;
}
diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h
index 47c7885..350bc57 100644
--- a/board/nvidia/common/board.h
+++ b/board/nvidia/common/board.h
@@ -25,5 +25,9 @@
#define _BOARD_H_
void tegra2_start(void);
+void clock_init(void);
+void pinmux_init(void);
+void gpio_init(void);
+void gpio_config_uart(void);
#endif /* BOARD_H */
diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
index 3a146cb..9fb6b57 100644
--- a/board/nvidia/harmony/Makefile
+++ b/board/nvidia/harmony/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
COBJS += ../common/board.o
SRCS := $(COBJS:.o=.c)
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
new file mode 100644
index 000..f1ab050
--- /dev/null
+++ b/board/nvidia/harmony/harmony.c
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/tegra2.h
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on Harmony - no conflict w/SPI.
+ */
+void gpio_config_uart(void)
+{
+}
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
index 3a146cb..9fb6b57 100644
--- a/board/nvidia/seaboard/Makefile
+++ b/board/nvidia/seaboard/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
COBJS += ../common/board.o
SRCS := $(COBJS:.o=.c)
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
new file mode 100644
index 000..4b9a8f3
--- /dev/null
+++ b/board/nvidia/seaboard/seaboard.c
@@ -0,0 +1,52
[U-Boot] [PATCH V5] arm: Tegra2: add support for A9 CPU init
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Remove returns in void functions
- Move inline assembly code to .S file
- Simplify some if/else code, break out common code
- Minimize the use of local vars
- Inline some single-instance functions
- Remove TRUE/FALSE define, use 1/0 instead
- Replace memset of mem-mapped regs w/loop of writel's
Changes for V3:
- Fix C-style comments in lowlevel_init.S cache_configure
Changes for V4:
- Move cold_boot() from C to assembly
- Fix spacing in cache_configure
Changes for V5:
- Add a timeout and printf msg if CPU never powers up
- Remove redundant is_cpu_powered in start_cpu
arch/arm/cpu/armv7/start.S | 12 +
arch/arm/cpu/armv7/tegra2/Makefile |2 +-
arch/arm/cpu/armv7/tegra2/ap20.c | 329
arch/arm/cpu/armv7/tegra2/ap20.h | 104 +
arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 94
arch/arm/include/asm/arch-tegra2/clk_rst.h | 27 +++
arch/arm/include/asm/arch-tegra2/pmc.h |8 +
arch/arm/include/asm/arch-tegra2/scu.h | 43
arch/arm/include/asm/arch-tegra2/tegra2.h |8 +
board/nvidia/common/board.c| 10 +
board/nvidia/common/board.h| 29 +++
include/configs/harmony.h |1 +
include/configs/seaboard.h |1 +
include/configs/tegra2-common.h|2 +
14 files changed, 669 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.c
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.h
create mode 100644 arch/arm/include/asm/arch-tegra2/scu.h
create mode 100644 board/nvidia/common/board.h
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index d83d501..bef0a6d 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,6 +70,18 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TEGRA2
+/*
+ * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
+ * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
+ * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
+ * to pick up its reset vector, which points here.
+ */
+.globl _armboot_start
+_armboot_start:
+.word _start
+#endif
+
/*
* These are defined in the board-specific linker script.
*/
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile
b/arch/arm/cpu/armv7/tegra2/Makefile
index 687c887..f1ea915 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS := board.o sys_info.o timer.o
+COBJS := ap20.o board.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
new file mode 100644
index 000..d3e6797
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -0,0 +1,329 @@
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation www.nvidia.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include ap20.h
+#include asm/io.h
+#include asm/arch/tegra2.h
+#include asm/arch/clk_rst.h
+#include asm/arch/pmc.h
+#include asm/arch/pinmux.h
+#include asm/arch/scu.h
+#include common.h
+
+u32 s_first_boot = 1;
+
+static void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg, clk;
+
+ /*
+* NOTE:
+* Regardless of whether the request is to enable or disable the CPU
+* clock, every processor in the CPU complex except the master (CPU 0)
+* will have it's clock stopped because the AVP only talks to the
+* master. The AVP does not know (nor does it need to know) that there
+* are multiple processors in the CPU complex.
+*/
+
+ if (enable) {
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ writel(CCLK_BURST_POLICY, clkrst-crc_cclk_brst_pol
[U-Boot] [PATCH 0/3] Fix hang when loading U-Boot from SPI or NAND
This series of patches fixes a hang seen when loading U-Boot from SPI or NAND on Seaboard and Harmony due to a missing PLLX init. It also corrects a UARTD bit error in clk_rst.h, and adds rudimentary GPIO support so that the UART on Seaboard can be used by U-Boot (UARTD SPIFLASH are muxed, and the default POR setting is for SPI access, so GPIO_PI3 has to be driven low to enable serial console I/O over UARTD). Harmony has no SPIFLASH, so the issue doesn't exist there. With these changes, I can write U-Boot to SPI on Seaboard and boot with it to the U-Boot cmd prompt. This should also apply to loading from NAND on Seaboard and Harmony - testing to follow. Tom Warren (3): arm: Tegra2: Add missing PLLX init arm: Tegra2: GPIO: Add basic GPIO functionality arm: Tegra2: Move clk/mux init to board_early_init_f, add GPIO init arch/arm/cpu/armv7/tegra2/ap20.c | 29 ++ arch/arm/include/asm/arch-tegra2/clk_rst.h |6 ++- arch/arm/include/asm/arch-tegra2/gpio.h| 59 arch/arm/include/asm/arch-tegra2/tegra2.h |1 + board/nvidia/common/board.c| 32 ++- board/nvidia/common/board.h|4 ++ board/nvidia/harmony/Makefile |1 + board/nvidia/harmony/harmony.c | 34 board/nvidia/seaboard/Makefile |1 + board/nvidia/seaboard/seaboard.c | 52 10 files changed, 206 insertions(+), 13 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h create mode 100644 board/nvidia/harmony/harmony.c create mode 100644 board/nvidia/seaboard/seaboard.c -- 1.7.4.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] arm: Tegra2: Add missing PLLX init
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/cpu/armv7/tegra2/ap20.c | 29
arch/arm/include/asm/arch-tegra2/clk_rst.h |6 +++-
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index 075341e..ed4 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -32,6 +32,32 @@
u32 s_first_boot = 1;
+void init_pllx(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* If PLLX is already enabled, just return */
+ reg = readl(clkrst-crc_pllx_base);
+ if (reg PLL_ENABLE)
+ return;
+
+ /* Set PLLX_MISC */
+ reg = CPCON;/* CPCON = 0001 */
+ writel(reg, clkrst-crc_pllx_misc);
+
+ /* Use 12MHz clock here */
+ reg = (PLL_BYPASS | PLL_DIVM);
+ reg |= (1000 8); /* DIVN = 0x3E8 */
+ writel(reg, clkrst-crc_pllx_base);
+
+ reg |= PLL_ENABLE;
+ writel(reg, clkrst-crc_pllx_base);
+
+ reg = ~PLL_BYPASS;
+ writel(reg, clkrst-crc_pllx_base);
+}
+
static void enable_cpu_clock(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
@@ -47,6 +73,9 @@ static void enable_cpu_clock(int enable)
*/
if (enable) {
+ /* Initialize PLLX */
+ init_pllx();
+
/* Wait until all clocks are stable */
udelay(PLL_STABILIZATION_DELAY);
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h
b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index d67a5d7..bd8ad2c 100644
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -160,8 +160,8 @@ struct clk_rst_ctlr {
#define PLL_DIVP (1 20) /* post divider, b22:20 */
#define PLL_DIVM 0x0C/* input divider, b4:0 */
-#define SWR_UARTD_RST (1 2)
-#define CLK_ENB_UARTD (1 2)
+#define SWR_UARTD_RST (1 1)
+#define CLK_ENB_UARTD (1 1)
#define SWR_UARTA_RST (1 6)
#define CLK_ENB_UARTA (1 6)
@@ -189,4 +189,6 @@ struct clk_rst_ctlr {
#define CPU0_CLK_STP (1 8)
#define CPU1_CLK_STP (1 9)
+#define CPCON (1 8)
+
#endif /* CLK_RST_H */
--
1.7.4.3
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] arm: Tegra2: GPIO: Add basic GPIO functionality
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra2/gpio.h | 59 +
arch/arm/include/asm/arch-tegra2/tegra2.h |1 +
2 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h
diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h
b/arch/arm/include/asm/arch-tegra2/gpio.h
new file mode 100644
index 000..0fb8f0d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/gpio.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_GPIO_H_
+#define _TEGRA2_GPIO_H_
+
+/*
+ * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* The number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* The number of banks */
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#define GPIO_BANK(x) ((x) 5)
+#define GPIO_PORT(x) (((x) 3) 0x3)
+#define GPIO_BIT(x)((x) 0x7)
+
+/*
+ * GPIO_PI3 = Port I = 8, bit = 3.
+ * Seaboard: used for UART/SPI selection
+ * Harmony: not used
+ */
+#define GPIO_PI3 ((8 3) | 3)
+
+#endif /* TEGRA2_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h
b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 7b0f5cc..742a75a 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -30,6 +30,7 @@
#define NV_PA_TMRUS_BASE 0x60005010
#define NV_PA_CLK_RST_BASE 0x60006000
#define NV_PA_FLOW_BASE0x60007000
+#define NV_PA_GPIO_BASE0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE0x7000
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
--
1.7.4.3
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] arm: Tegra2: Move clk/mux init to board_early_init_f, add GPIO init
Signed-off-by: Tom Warren twar...@nvidia.com
---
board/nvidia/common/board.c | 32 +++
board/nvidia/common/board.h |4 +++
board/nvidia/harmony/Makefile|1 +
board/nvidia/harmony/harmony.c | 34
board/nvidia/seaboard/Makefile |1 +
board/nvidia/seaboard/seaboard.c | 52 ++
6 files changed, 113 insertions(+), 11 deletions(-)
create mode 100644 board/nvidia/harmony/harmony.c
create mode 100644 board/nvidia/seaboard/seaboard.c
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 5edd70f..3d6c248 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -41,7 +41,16 @@ const struct tegra2_sysinfo sysinfo = {
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
- debug(Board Early Init\n);
+ /* Initialize periph clocks */
+ clock_init();
+
+ /* Initialize periph pinmuxes */
+ pinmux_init();
+
+ /* Initialize periph GPIOs */
+ gpio_init();
+
+ /* Init UART, scratch regs, and start CPU */
tegra2_start();
return 0;
}
@@ -64,10 +73,10 @@ int timer_init(void)
static void clock_init_uart(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- static int pllp_init_done;
u32 reg;
- if (!pllp_init_done) {
+ reg = readl(clkrst-crc_pllp_base);
+ if (!(reg PLL_BASE_OVRRIDE)) {
/* Override pllp setup for 216MHz operation. */
reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) 8) | PLL_DIVM);
@@ -78,8 +87,6 @@ static void clock_init_uart(void)
reg = ~PLL_BYPASS;
writel(reg, clkrst-crc_pllp_base);
-
- pllp_init_done++;
}
/* Now do the UART reset/clock enable */
@@ -182,6 +189,15 @@ void pinmux_init(void)
}
/*
+ * Routine: gpio_init
+ * Description: Do individual peripheral GPIO configs
+ */
+void gpio_init(void)
+{
+ gpio_config_uart();
+}
+
+/*
* Routine: board_init
* Description: Early hardware init.
*/
@@ -192,11 +208,5 @@ int board_init(void)
/* board id for Linux */
gd-bd-bi_arch_number = CONFIG_MACH_TYPE;
- /* Initialize peripheral clocks */
- clock_init();
-
- /* Initialize periph pinmuxes */
- pinmux_init();
-
return 0;
}
diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h
index 47c7885..350bc57 100644
--- a/board/nvidia/common/board.h
+++ b/board/nvidia/common/board.h
@@ -25,5 +25,9 @@
#define _BOARD_H_
void tegra2_start(void);
+void clock_init(void);
+void pinmux_init(void);
+void gpio_init(void);
+void gpio_config_uart(void);
#endif /* BOARD_H */
diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
index 3a146cb..9fb6b57 100644
--- a/board/nvidia/harmony/Makefile
+++ b/board/nvidia/harmony/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
COBJS += ../common/board.o
SRCS := $(COBJS:.o=.c)
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
new file mode 100644
index 000..f1ab050
--- /dev/null
+++ b/board/nvidia/harmony/harmony.c
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/tegra2.h
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on Harmony - no conflict w/SPI.
+ */
+void gpio_config_uart(void)
+{
+}
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
index 3a146cb..9fb6b57 100644
--- a/board/nvidia/seaboard/Makefile
+++ b/board/nvidia/seaboard/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
COBJS += ../common/board.o
SRCS := $(COBJS:.o=.c)
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
new file mode 100644
index 000..4b9a8f3
--- /dev/null
+++ b/board/nvidia/seaboard/seaboard.c
@@ -0,0 +1,52
Re: [U-Boot] [PATCH V4] arm: Tegra2: add support for A9 CPU init
Albert,
On Wed, Apr 13, 2011 at 1:09 PM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Le 12/04/2011 23:02, Tom Warren a écrit :
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c
b/arch/arm/cpu/armv7/tegra2/ap20.c
new file mode 100644
index 000..075341e
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -0,0 +1,325 @@
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporationwww.nvidia.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include ap20.h
+#includeasm/io.h
+#includeasm/arch/tegra2.h
+#includeasm/arch/clk_rst.h
+#includeasm/arch/pmc.h
+#includeasm/arch/pinmux.h
+#includeasm/arch/scu.h
+#includecommon.h
+
+u32 s_first_boot = 1;
+
+static void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE;
+ u32 reg, clk;
+
+ /*
+ * NOTE:
+ * Regardless of whether the request is to enable or disable the
CPU
+ * clock, every processor in the CPU complex except the master
(CPU 0)
+ * will have it's clock stopped because the AVP only talks to the
+ * master. The AVP does not know (nor does it need to know) that
there
+ * are multiple processors in the CPU complex.
+ */
+
+ if (enable) {
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ writel(CCLK_BURST_POLICY,clkrst-crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER,clkrst-crc_super_cclk_div);
+ }
+
+ /* Fetch the register containing the main CPU complex clock enable
*/
+ reg = readl(clkrst-crc_clk_out_enb_l);
+ reg |= CLK_ENB_CPU;
+
+ /*
+ * Read the register containing the individual CPU clock enables
and
+ * always stop the clock to CPU 1.
+ */
+ clk = readl(clkrst-crc_clk_cpu_cmplx);
+ clk |= CPU1_CLK_STP;
+
+ if (enable) {
+ /* Unstop the CPU clock */
+ clk= ~CPU0_CLK_STP;
+ } else {
+ /* Stop the CPU clock */
+ clk |= CPU0_CLK_STP;
+ }
+
+ writel(clk,clkrst-crc_clk_cpu_cmplx);
+ writel(reg,clkrst-crc_clk_out_enb_l);
+}
+
+static int is_cpu_powered(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ return (readl(pmc-pmc_pwrgate_status) CPU_PWRED) ? 1 : 0;
+}
+
+static void remove_cpu_io_clamps(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ /* Remove the clamps on the CPU I/O signals */
+ reg = readl(pmc-pmc_remove_clamping);
+ reg |= CPU_CLMP;
+ writel(reg,pmc-pmc_remove_clamping);
+
+ /* Give I/O signals time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+}
+
+static void powerup_cpu(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ if (!is_cpu_powered()) {
+ /* Toggle the CPU power state (OFF - ON) */
+ reg = readl(pmc-pmc_pwrgate_toggle);
+ reg= PARTID_CP;
+ reg |= START_CP;
+ writel(reg,pmc-pmc_pwrgate_toggle);
+
+ /* Wait for the power to come up */
+ while (!is_cpu_powered())
+ ; /* Do nothing */
What if power never comes up?
Then the system is hung. I can put a printf here, if you'd like.
+ /*
+ * Remove the I/O clamps from CPU power partition.
+ * Recommended only on a Warm boot, if the CPU partition
gets
+ * power gated. Shouldn't cause any harm when called after
a
+ * cold boot according to HW, probably just redundant.
+ */
+ remove_cpu_io_clamps();
+ }
+}
+
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ reg = readl(pmc-pmc_cntrl);
+ reg |= CPUPWRREQ_OE;
+ writel(reg,pmc-pmc_cntrl);
+
+ /*
+ * The TI PMU65861C needs a 3.75ms delay between enabling
Re: [U-Boot] [PATCH 1/3] arm: Tegra2: Add missing PLLX init
CPCON (Charge Pump Control) is a 4-bit field, bits 11:8. The default value is 0001. I'll change the comment to /* CPCON [11:8] = 0001 */ On Wed, Apr 13, 2011 at 1:12 PM, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Le 13/04/2011 22:07, Tom Warren a écrit : + reg = CPCON; /* CPCON = 0001 */ +#define CPCON (1 8) Which one is the correct value? 0001 or 0x100? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] arm: Tegra2: GPIO: Add basic GPIO functionality
Albert,
On Wed, Apr 13, 2011 at 1:14 PM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Tom,
Le 13/04/2011 22:07, Tom Warren a écrit :
Signed-off-by: Tom Warrentwar...@nvidia.com
---
arch/arm/include/asm/arch-tegra2/gpio.h | 59
+
arch/arm/include/asm/arch-tegra2/tegra2.h | 1 +
2 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h
diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h
b/arch/arm/include/asm/arch-tegra2/gpio.h
new file mode 100644
index 000..0fb8f0d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/gpio.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_GPIO_H_
+#define _TEGRA2_GPIO_H_
+
+/*
+ * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4
ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* The number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* The number of banks */
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#define GPIO_BANK(x) ((x) 5)
+#define GPIO_PORT(x) (((x) 3) 0x3)
+#define GPIO_BIT(x) ((x) 0x7)
+
+/*
+ * GPIO_PI3 = Port I = 8, bit = 3.
+ * Seaboard: used for UART/SPI selection
+ * Harmony: not used
+ */
+#define GPIO_PI3 ((8 3) | 3)
+
+#endif /* TEGRA2_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h
b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 7b0f5cc..742a75a 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -30,6 +30,7 @@
#define NV_PA_TMRUS_BASE 0x60005010
#define NV_PA_CLK_RST_BASE 0x60006000
#define NV_PA_FLOW_BASE 0x60007000
+#define NV_PA_GPIO_BASE 0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x7000
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
These are header files only, and they do not even contain function-like
macros, so where is the functionality exactly?
In the next patch (3/3) - the macros are used in seaboard.c to drive
the UART_DISABLE GPIO low to enable the UART in U-Boot POST.
Amicalement,
--
Albert.
Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4] arm: Tegra2: add support for A9 CPU init
Albert,
On Wed, Apr 13, 2011 at 1:30 PM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Tom,
Le 13/04/2011 22:21, Tom Warren a écrit :
+
+ /* Wait for the power to come up */
+ while (!is_cpu_powered())
+ ; /* Do nothing */
What if power never comes up?
Then the system is hung. I can put a printf here, if you'd like.
Is the system hung? Can it really not proceed to the prompt? Anyway, at
least, yes, a printf would be welcome.
It's hung because it's looping on the while ;. While it's possible we
could limp along on the AVP only, that's not a viable config, and I
don't know what a partially enabled CPU complex is going to do -
interrupt storm, memory corruption, etc. I'll just put in a printf for
the failure case. Thanks.
+ /*
+ * Remove the I/O clamps from CPU power partition.
+ * Recommended only on a Warm boot, if the CPU partition
gets
+ * power gated. Shouldn't cause any harm when called
after
a
+ * cold boot according to HW, probably just redundant.
+ */
+ remove_cpu_io_clamps();
+ }
+}
+
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ reg = readl(pmc-pmc_cntrl);
+ reg |= CPUPWRREQ_OE;
+ writel(reg,pmc-pmc_cntrl);
+
+ /*
+ * The TI PMU65861C needs a 3.75ms delay between enabling
+ * the power rail and enabling the CPU clock. This delay
+ * between SM1EN and SM1 is for switching time + the ramp
+ * up of the voltage to the CPU (VDD_CPU from PMU).
+ */
+ udelay(3750);
+}
+
+static void reset_A9_cpu(int reset)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE;
+ u32 reg, cpu;
+
+ /*
+ * NOTE: Regardless of whether the request is to hold the CPU in
reset
+ * or take it out of reset, every processor in the CPU
complex
+ * except the master (CPU 0) will be held in reset because
the
+ * AVP only talks to the master. The AVP does not know
that
there
+ * are multiple processors in the CPU complex.
+ */
+
+ /* Hold CPU 1 in reset */
+ cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1;
+ writel(cpu,clkrst-crc_cpu_cmplx_set);
+
+ reg = readl(clkrst-crc_rst_dev_l);
+ if (reset) {
+ /* Now place CPU0 into reset */
+ cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0;
+ writel(cpu,clkrst-crc_cpu_cmplx_set);
+
+ /* Enable master CPU reset */
+ reg |= SWR_CPU_RST;
+ } else {
+ /* Take CPU0 out of reset */
+ cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0;
+ writel(cpu,clkrst-crc_cpu_cmplx_clr);
+
+ /* Disable master CPU reset */
+ reg= ~SWR_CPU_RST;
+ }
+
+ writel(reg,clkrst-crc_rst_dev_l);
+}
+
+static void clock_enable_coresight(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE;
+ u32 rst, clk, src;
+
+ rst = readl(clkrst-crc_rst_dev_u);
+ clk = readl(clkrst-crc_clk_out_enb_u);
+
+ if (enable) {
+ rst= ~SWR_CSITE_RST;
+ clk |= CLK_ENB_CSITE;
+ } else {
+ rst |= SWR_CSITE_RST;
+ clk= ~CLK_ENB_CSITE;
+ }
+
+ writel(clk,clkrst-crc_clk_out_enb_u);
+ writel(rst,clkrst-crc_rst_dev_u);
+
+ if (enable) {
+ /*
+ * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it
down
by
+ * 1.5, giving an effective frequency of 144MHz.
+ * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
+ * (bits 7:0), so 0001b == 1.5 (n+1 + .5)
+ */
+ src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
+ writel(src,clkrst-crc_clk_src_csite);
+
+ /* Unlock the CPU CoreSight interfaces */
+ rst = 0xC5ACCE55;
+ writel(rst, CSITE_CPU_DBG0_LAR);
+ writel(rst, CSITE_CPU_DBG1_LAR);
+ }
+}
+
+void start_cpu(u32 reset_vector)
+{
+ /* Enable VDD_CPU */
+ enable_cpu_power_rail();
+
+ /* Hold the CPUs in reset */
+ reset_A9_cpu(1);
+
+ /* Disable the CPU clock */
+ enable_cpu_clock(0);
+
+ /* Enable CoreSight */
+ clock_enable_coresight(1);
+
+ /*
+ * Set the entry point for CPU execution from reset,
+ * if it's a non-zero value.
+ */
+ if (reset_vector)
+ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+ /* Enable the CPU clock
Re: [U-Boot] [PATCH 2/3] arm: Tegra2: GPIO: Add basic GPIO functionality
Albert,
On Wed, Apr 13, 2011 at 1:31 PM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Tom,
Le 13/04/2011 22:26, Tom Warren a écrit :
Albert,
On Wed, Apr 13, 2011 at 1:14 PM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Tom,
Le 13/04/2011 22:07, Tom Warren a écrit :
Signed-off-by: Tom Warrentwar...@nvidia.com
---
arch/arm/include/asm/arch-tegra2/gpio.h | 59
+
arch/arm/include/asm/arch-tegra2/tegra2.h | 1 +
2 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h
diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h
b/arch/arm/include/asm/arch-tegra2/gpio.h
new file mode 100644
index 000..0fb8f0d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/gpio.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_GPIO_H_
+#define _TEGRA2_GPIO_H_
+
+/*
+ * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4
ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* The number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* The number of banks */
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#define GPIO_BANK(x) ((x) 5)
+#define GPIO_PORT(x) (((x) 3) 0x3)
+#define GPIO_BIT(x) ((x) 0x7)
+
+/*
+ * GPIO_PI3 = Port I = 8, bit = 3.
+ * Seaboard: used for UART/SPI selection
+ * Harmony: not used
+ */
+#define GPIO_PI3 ((8 3) | 3)
+
+#endif /* TEGRA2_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h
b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 7b0f5cc..742a75a 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -30,6 +30,7 @@
#define NV_PA_TMRUS_BASE 0x60005010
#define NV_PA_CLK_RST_BASE 0x60006000
#define NV_PA_FLOW_BASE 0x60007000
+#define NV_PA_GPIO_BASE 0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x7000
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
These are header files only, and they do not even contain function-like
macros, so where is the functionality exactly?
In the next patch (3/3) - the macros are used in seaboard.c to drive
the UART_DISABLE GPIO low to enable the UART in U-Boot POST.
Could you just rename the patch Add basic GPIO definitions then?
Sure, no problem. Thanks.
Amicalement,
--
Albert.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V4] arm: Tegra2: add support for A9 CPU init
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Remove returns in void functions
- Move inline assembly code to .S file
- Simplify some if/else code, break out common code
- Minimize the use of local vars
- Inline some single-instance functions
- Remove TRUE/FALSE define, use 1/0 instead
- Replace memset of mem-mapped regs w/loop of writel's
Changes for V3:
- Fix C-style comments in lowlevel_init.S cache_configure
Changes for V4:
- Move cold_boot() from C to assembly
- Fix spacing in cache_configure
arch/arm/cpu/armv7/start.S | 12 +
arch/arm/cpu/armv7/tegra2/Makefile |2 +-
arch/arm/cpu/armv7/tegra2/ap20.c | 325
arch/arm/cpu/armv7/tegra2/ap20.h | 104 +
arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 94
arch/arm/include/asm/arch-tegra2/clk_rst.h | 27 +++
arch/arm/include/asm/arch-tegra2/pmc.h |8 +
arch/arm/include/asm/arch-tegra2/scu.h | 43
arch/arm/include/asm/arch-tegra2/tegra2.h |8 +
board/nvidia/common/board.c| 10 +
board/nvidia/common/board.h| 29 +++
include/configs/harmony.h |1 +
include/configs/seaboard.h |3 +-
include/configs/tegra2-common.h|2 +
14 files changed, 666 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.c
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.h
create mode 100644 arch/arm/include/asm/arch-tegra2/scu.h
create mode 100644 board/nvidia/common/board.h
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index cb4f92f..4b36693 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,6 +70,18 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TEGRA2
+/*
+ * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
+ * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
+ * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
+ * to pick up its reset vector, which points here.
+ */
+.globl _armboot_start
+_armboot_start:
+.word _start
+#endif
+
/*
* These are defined in the board-specific linker script.
*/
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile
b/arch/arm/cpu/armv7/tegra2/Makefile
index 687c887..f1ea915 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS := board.o sys_info.o timer.o
+COBJS := ap20.o board.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
new file mode 100644
index 000..075341e
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -0,0 +1,325 @@
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation www.nvidia.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include ap20.h
+#include asm/io.h
+#include asm/arch/tegra2.h
+#include asm/arch/clk_rst.h
+#include asm/arch/pmc.h
+#include asm/arch/pinmux.h
+#include asm/arch/scu.h
+#include common.h
+
+u32 s_first_boot = 1;
+
+static void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg, clk;
+
+ /*
+* NOTE:
+* Regardless of whether the request is to enable or disable the CPU
+* clock, every processor in the CPU complex except the master (CPU 0)
+* will have it's clock stopped because the AVP only talks to the
+* master. The AVP does not know (nor does it need to know) that there
+* are multiple processors in the CPU complex.
+*/
+
+ if (enable) {
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ writel(CCLK_BURST_POLICY, clkrst-crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, clkrst-crc_super_cclk_div);
+ }
+
+ /* Fetch the register containing the main
Re: [U-Boot] [PATCH] arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update
Albert, On Sun, Mar 27, 2011 at 9:22 AM, Albert ARIBAUD albert.arib...@free.fr wrote: Le 24/03/2011 16:08, Tom Warren a écrit : Albert, On Thu, Mar 24, 2011 at 7:27 AM, Albert ARIBAUDalbert.arib...@free.fr wrote: Le 22/03/2011 20:27, Tom Warren a écrit : Albert, On Wed, Feb 23, 2011 at 1:45 PM, Albert ARIBAUDalbert.arib...@free.fr wrote: Le 23/02/2011 21:03, Tom Warren a écrit : OK, I'm an idiot. I see now that I needed to add -n to format-patch to add the numbering to the [PATCH] header. Sorry for the noise - resending now with the corrected patchset. Tom Actually, for a single patch, you don't need to generate numbers, nor a cover letter (the 0/N message). Is the current patch OK as is? It's a simple one-line change. I guess so. As soon as I get confirmation from Wolfgang that board patches can go through any tree, I'll apply it as a bugfix to master. Great. Thanks! Applied to u-boot-arm/master. Also, I saw your 'patches pending before release?' message. Have my Tegra 'A9 CPU' patches been applied to arm master? I'm still a little confused about the timing of the merge window vs. the release, and I'm not sure if the full set of Tegra patches will be in the next release. Sorry, I can't get them in in the upcoming release as I barely have time to sort the pull req for today, but I'll get them on u-boot-arm/master as soon as I can after that, so they'll be available on the ARM tree until the following release, where they'll move to the mainline one. Excellent - that's all I can ask. Thanks! Tom Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2] arm: Tegra2: add support for A9 CPU init
Peter,
On Fri, Mar 25, 2011 at 9:02 AM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
Things look pretty good. Minor comments/questions below.
snip
+/*
+ * TBD: Move cold_boot() to assembly file.
+ * Values/offsets of the table vars make this difficult.
+ */
+
+void cold_boot(void)
+{
+ asm volatile(
+ msr cpsr_c, #0xD3 \n
+ /*
+ * Check current processor: CPU or AVP?
+ * If CPU, go to CPU boot code, else continue on AVP path.
+ */
+ mov r0, %0 \n
+ ldrb r2, [r0, %1] \n
+ /* are we the CPU? */
+ cmp r2, %2 \n
+ mov sp, %3 \n
+ /* yep, we are the CPU */
+ bxeq %4 \n
+
+ /* AVP initialization follows this path */
+ mov sp, %5 \n
+ /* Init and start CPU */
+ b startup_cpu \n
+ :
+ : i(NV_PA_PG_UP_BASE),
+ i(PG_UP_TAG_0),
+ r(proc_tag),
+ r(cpu_boot_stack),
+ r(_armboot_start),
+ r(avp_boot_stack)
+ : r0, r2, cc, lr
+ );
+}
What errors did you encounter when this was in the assembly file? It'd
be nice to put it there now. Likely it will never get fixed if it
doesn't implemented correctly off the bat. If you post the errors
perhaps someone on the list can provide insight.
I didn't capture a log of the errors when I was trying to put the
cold_boot code into lowlevel_init.S. But I saw fixup errors and
undefined constant errors, all related to the #defines (NV_PG_UP_BASE,
avp/cpu_boot_stack, etc.) and how the compiler/assembler references
indirect and relative constants.
Note that this code works perfectly as-is, so there's no pressing need
to move it to assembly now, except for a cosmetic/procedural one. I'd
rather get this accepted into mainline, so I can move on to the
eMMC/SPI/USB drivers so people can use the code to boot an OS on our
(many) Tegra2 boards coming to market RSN.
If some ARM / gcc assembly wizard wants to attempt moving this code to
a .S file, I welcome the help - I may even attack it at a later date,
when I've got more bandwidth. But it isn't a priority for me right
now, unless someone on the list adamantly opposes the code as-s. But
I'd expect anyone with that strong an opinion about to be able to fix
it, or at least attempt it and see why I decided to defer moving it to
assembly for now.
snip
+.globl startup_cpu
+startup_cpu:
+ @ Initialize the AVP, clocks, and memory controller
+ @ SDRAM is guaranteed to be on at this point
+
+ ldr r0, =cold_boot @ R0 = reset vector for CPU
+ bl start_cpu @ start the CPU
+
+ @ Transfer control to the AVP code */
+ bl halt_avp
+
+ @ Should never get here
+_loop_forever2:
+ b _loop_forever2
+
+.globl cache_configure
+cache_configure:
+ stmdb r13!,{r14}
+@ /* invalidate instruction cache */
It looks like there's a combination of comment forms @, @ */, and @ /*
*/. Is there a reason not to use the normal /* */ universally?
No, just dross left over from moving the inline assembly from .c to
.S. The rest of lowlevel_init.S uses @ for comments, so I tried to
stick with that. I'l fix it, thanks.
Best,
Peter
Thanks,
Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3] arm: Tegra2: add support for A9 CPU init
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Remove returns in void functions
- Move inline assembly code to .S file
- Simplify some if/else code, break out common code
- Minimize the use of local vars
- Inline some single-instance functions
- Remove TRUE/FALSE define, use 1/0 instead
- Replace memset of mem-mapped regs w/loop of writel's
Changes for V3:
- Fix C-style comments in lowlevel_init.S cache_configure
arch/arm/cpu/armv7/start.S | 12 +
arch/arm/cpu/armv7/tegra2/Makefile |2 +-
arch/arm/cpu/armv7/tegra2/ap20.c | 366
arch/arm/cpu/armv7/tegra2/ap20.h | 105
arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 70 ++
arch/arm/include/asm/arch-tegra2/clk_rst.h | 27 ++
arch/arm/include/asm/arch-tegra2/pmc.h |8 +
arch/arm/include/asm/arch-tegra2/scu.h | 43
arch/arm/include/asm/arch-tegra2/tegra2.h |5 +
board/nvidia/common/board.c| 10 +
board/nvidia/common/board.h| 29 +++
include/configs/harmony.h |1 +
include/configs/seaboard.h |3 +-
include/configs/tegra2-common.h|2 +
14 files changed, 681 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.c
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.h
create mode 100644 arch/arm/include/asm/arch-tegra2/scu.h
create mode 100644 board/nvidia/common/board.h
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index cb4f92f..4b36693 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,6 +70,18 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TEGRA2
+/*
+ * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
+ * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
+ * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
+ * to pick up its reset vector, which points here.
+ */
+.globl _armboot_start
+_armboot_start:
+.word _start
+#endif
+
/*
* These are defined in the board-specific linker script.
*/
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile
b/arch/arm/cpu/armv7/tegra2/Makefile
index 687c887..f1ea915 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS := board.o sys_info.o timer.o
+COBJS := ap20.o board.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
new file mode 100644
index 000..d0ad41f
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -0,0 +1,366 @@
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation www.nvidia.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include ap20.h
+#include asm/io.h
+#include asm/arch/tegra2.h
+#include asm/arch/clk_rst.h
+#include asm/arch/pmc.h
+#include asm/arch/pinmux.h
+#include asm/arch/scu.h
+#include common.h
+
+u32 s_first_boot = 1;
+
+static void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg, clk;
+
+ /*
+* NOTE:
+* Regardless of whether the request is to enable or disable the CPU
+* clock, every processor in the CPU complex except the master (CPU 0)
+* will have it's clock stopped because the AVP only talks to the
+* master. The AVP does not know (nor does it need to know) that there
+* are multiple processors in the CPU complex.
+*/
+
+ if (enable) {
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ writel(CCLK_BURST_POLICY, clkrst-crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, clkrst-crc_super_cclk_div);
+ }
+
+ /* Fetch the register containing the main CPU complex clock enable */
+ reg = readl(clkrst-crc_clk_out_enb_l);
+ reg |= CLK_ENB_CPU
Re: [U-Boot] [PATCH V2] arm: Tegra2: add support for A9 CPU init
Peter,
On Fri, Mar 25, 2011 at 10:22 AM, Peter Tyser pty...@xes-inc.com wrote:
On Fri, 2011-03-25 at 09:16 -0700, Tom Warren wrote:
Peter,
On Fri, Mar 25, 2011 at 9:02 AM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
Things look pretty good. Minor comments/questions below.
snip
+/*
+ * TBD: Move cold_boot() to assembly file.
+ * Values/offsets of the table vars make this difficult.
+ */
+
+void cold_boot(void)
+{
+ asm volatile(
+ msr cpsr_c, #0xD3 \n
+ /*
+ * Check current processor: CPU or AVP?
+ * If CPU, go to CPU boot code, else continue on AVP path.
+ */
+ mov r0, %0 \n
+ ldrb r2, [r0, %1] \n
+ /* are we the CPU? */
+ cmp r2, %2 \n
+ mov sp, %3 \n
+ /* yep, we are the CPU */
+ bxeq %4 \n
+
+ /* AVP initialization follows this path */
+ mov sp, %5 \n
+ /* Init and start CPU */
+ b startup_cpu \n
+ :
+ : i(NV_PA_PG_UP_BASE),
+ i(PG_UP_TAG_0),
+ r(proc_tag),
+ r(cpu_boot_stack),
+ r(_armboot_start),
+ r(avp_boot_stack)
+ : r0, r2, cc, lr
+ );
+}
What errors did you encounter when this was in the assembly file? It'd
be nice to put it there now. Likely it will never get fixed if it
doesn't implemented correctly off the bat. If you post the errors
perhaps someone on the list can provide insight.
I didn't capture a log of the errors when I was trying to put the
cold_boot code into lowlevel_init.S. But I saw fixup errors and
undefined constant errors, all related to the #defines (NV_PG_UP_BASE,
avp/cpu_boot_stack, etc.) and how the compiler/assembler references
indirect and relative constants.
Note that this code works perfectly as-is, so there's no pressing need
to move it to assembly now, except for a cosmetic/procedural one. I'd
rather get this accepted into mainline, so I can move on to the
eMMC/SPI/USB drivers so people can use the code to boot an OS on our
(many) Tegra2 boards coming to market RSN.
If some ARM / gcc assembly wizard wants to attempt moving this code to
a .S file, I welcome the help - I may even attack it at a later date,
when I've got more bandwidth. But it isn't a priority for me right
now, unless someone on the list adamantly opposes the code as-s. But
I'd expect anyone with that strong an opinion about to be able to fix
it, or at least attempt it and see why I decided to defer moving it to
assembly for now.
I understand your perspective, but why not spend the extra 30 minutes
and do it the right way? Passing the buck to someone else who cares
about maintaining high quality code isn't the right thing to do in my
opinion. This patch isn't going to make it into the upcoming release,
so it won't gate the other eMMC/SPI/USB drivers you want to add. The
bar to get code into open source project generally is higher than it
works - it has to adhere to the project's design principles and
guidelines. U-Boot already needs cleanup as is without adding more
cruft. Solving this small issue now results in cleaner code, less
headache down the road, and shouldn't take long. As usual, I'm not the
maintainer, so its just my $0.02.
FWIW, I spent _far_ more than 30 minutes on this .. close to a full
day of frustration/banging my head against the wall. I have other
priorities besides upstreaming Tegra2 U-Boot support, and I can't
justify spending days on this. As I originally stated, I'm no expert
in the intricacies of ARM asm programming - my expertise is in x86
CPUs, and hit a wall with this port to assembly.
I'm not passing the buck, and while I agree that this code is not the
cleanest I've seen, I don't think I'm pushing low-quality code here.
It's 8 lines of embedded assembly, plus a table. Looking at what the C
compiler produces in assembly, it's twice as long, pushes some of the
tabled values on the stack and then pulls them back into registers,
and is, IMHO, harder to understand. I could just cut-and-paste the
compiler output into lowlevel_init.S, and add some comments, but is
that really any better? Is the goal to get clean, understandable
code, or messier, harder to parse code in the right files?
As to adhering to U-Boot's design principles and guidelines, could you
point me to the section on embedded assembly in C files? I don't
remember seeing a specific section on that topic, don't see it under
U-Boot Coding Style, nor in the Linux coding guidelines, and I'd like
to reference it for future use.
For now, I'm going to let this percolate, as I have other fish to fry.
Thanks for your input,
Tom
Best,
Peter
___
U-Boot mailing list
U
Re: [U-Boot] [PATCH] arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update
Albert, On Thu, Mar 24, 2011 at 7:27 AM, Albert ARIBAUD albert.arib...@free.fr wrote: Le 22/03/2011 20:27, Tom Warren a écrit : Albert, On Wed, Feb 23, 2011 at 1:45 PM, Albert ARIBAUDalbert.arib...@free.fr wrote: Le 23/02/2011 21:03, Tom Warren a écrit : OK, I'm an idiot. I see now that I needed to add -n to format-patch to add the numbering to the [PATCH] header. Sorry for the noise - resending now with the corrected patchset. Tom Actually, for a single patch, you don't need to generate numbers, nor a cover letter (the 0/N message). Is the current patch OK as is? It's a simple one-line change. I guess so. As soon as I get confirmation from Wolfgang that board patches can go through any tree, I'll apply it as a bugfix to master. Great. Thanks! Also, I saw your 'patches pending before release?' message. Have my Tegra 'A9 CPU' patches been applied to arm master? I'm still a little confused about the timing of the merge window vs. the release, and I'm not sure if the full set of Tegra patches will be in the next release. Thanks, Tom Thanks, Tom Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Tegra2: add support for A9 CPU init
Peter, On Thu, Mar 17, 2011 at 7:32 AM, Peter Tyser pty...@xes-inc.com wrote: Hi Tom, + /* Is PLL-X already running? */ + reg = readl(clkrst-crc_pllx_base); + if (reg PLL_ENABLE) + return; + + /* Do PLLX init if it isn't running, but BootROM sets it, so TBD */ +} The above function looks incorrect. What looks incorrect? It checks to see if the PLL is already running/enabled, and returns if it is. Tegra2 mask ROM (BootROM) currently always sets PLLX, so this will always return, but the comment is there for future chips that may not set up PLLX. It looks like a function that does a read of a value it doesn't care about, does an unnecessary comparison, and then returns either way, without doing anything:) If/when you want to do future stuff with the PLL-X, code should be added then - as is it doesn't do anything and is confusing. The general policy of U-Boot is not to add dead code. OK, so not really incorrect, just unnecessary. Agreed - again a vestigial leftover from our in-house code. I'll remove it. Unnecessary/misleading/dead code is inherently not correct:) snip +#include asm/types.h + +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif These shouldn't be added here. They should be somewhere common, or shouldn't be used (my preference). I would think they'd be in the ARM tree somewhere, but I couldn't find them so I added 'em here. My preference is to use TRUE/FALSE - it carries more context than 1/0 to me. If you prefer to use TRUE/FALSE, they should be moved into a common location so everywhere uses the same, once-defined definition. Their definitions are already littered over a few files, which would ideally be cleaned up. Perhaps moving all definitions into include/common.h, or somewhere similar would work. Others may have opinions about TRUE/FALSE vs 1/0 - it seems like TRUE/FALSE aren't generally used. I don't want to pollute all builds by adding to include/common.h. I'll try to find a more central header in my own tree. My point is that there are already 32 definitions of TRUE/FALSE - adding a 33rd doesn't seem like a good thing to do. I view a 33rd identical definition as polluting the code more than 1 common definition that most people won't generally use. Its not my decision, but I assume the powers that be would recommend one of: - Not using TRUE/FALSE since using non-zero values and 0 are widely accepted as TRUE/FALSE. I think using TRUE/FALSE makes the code harder to understand and more open to bugs. Eg for other code that interacts with your code, or someone reviewing your code, they either have to either assume you defined TRUE as 1, FALSE as 0, or import your definitions. Anyway, I view their use as another layer of unnecessary abstraction with very little benefit. I've removed both the defines and the use of TRUE/FALSE in ap20.* - there were only a few instances. - Consolidating the definition of TRUE/FALSE. Wolfgang, do you have a preference about how TRUE/FALSE are generally used/defined? Best, Peter Thanks, Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Tegra2: add support for A9 CPU init
Allesandro, On Thu, Mar 17, 2011 at 8:30 AM, Alessandro Rubini rubini-l...@gnudd.com wrote: It looks like most of your uses are standalone functions that would function just fine on their own. Is there a reason you prefer to have them in a C-file instead of in an assembly file? Just laziness ;) I'll move these to a new .S file in the next patchset. Actually, writing assembly-only C functions is difficul and error-pronet. I've seen you use r0 and other registers esplicitly, but this is not allowed in general. I once wasted some hours in tracking why a non-submitted port of u-boot was not working with a newer compiler. The problem was just that: the new compiler was inlining a void(void) function; the asm used r0 and r1 explicitly, which worked over a function call but was corrupting data when inlined by the newer and more optimizing compiler. I've moved most of the in-line assembly to lowlevel_init.S. However, the cold_boot() code proved difficult - I got fixup errors, undefined constants, etc. I've cleaned it up a bit, but left it in ap20.c, using the %vars - again, replacing them with the actual values caused errors that I couldn't resolve. Maybe someone else on the list can help to port this code to the assembly file - I'm not expert enough in gcc/as and ARM to do it. New patch to follow RSN. While your functions are currently not inlined (or, like cold_boot, they may be inlined in a place where no register needs to be preserved), another user may move them to a context where the semantics are different, for another board or another boot loader. If they are in a .S files, they will only be called by bl and you know the rules for register allocation appy. Besides, a _real_ lazy programmer avoids the extra quotes and \n in the code :) /alessandro Thanks for your insight, Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2] arm: Tegra2: add support for A9 CPU init
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Remove returns in void functions
- Move inline assembly code to .S file
- Simplify some if/else code, break out common code
- Minimize the use of local vars
- Inline some single-instance functions
- Remove TRUE/FALSE define, use 1/0 instead
- Replace memset of mem-mapped regs w/loop of writel's
arch/arm/cpu/armv7/start.S | 12 +
arch/arm/cpu/armv7/tegra2/Makefile |2 +-
arch/arm/cpu/armv7/tegra2/ap20.c | 366
arch/arm/cpu/armv7/tegra2/ap20.h | 105
arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 70 ++
arch/arm/include/asm/arch-tegra2/clk_rst.h | 27 ++
arch/arm/include/asm/arch-tegra2/pmc.h |8 +
arch/arm/include/asm/arch-tegra2/scu.h | 43
arch/arm/include/asm/arch-tegra2/tegra2.h |5 +
board/nvidia/common/board.c| 10 +
board/nvidia/common/board.h| 29 +++
include/configs/harmony.h |1 +
include/configs/seaboard.h |3 +-
include/configs/tegra2-common.h|2 +
14 files changed, 681 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.c
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.h
create mode 100644 arch/arm/include/asm/arch-tegra2/scu.h
create mode 100644 board/nvidia/common/board.h
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index cb4f92f..4b36693 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,6 +70,18 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TEGRA2
+/*
+ * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
+ * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
+ * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
+ * to pick up its reset vector, which points here.
+ */
+.globl _armboot_start
+_armboot_start:
+.word _start
+#endif
+
/*
* These are defined in the board-specific linker script.
*/
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile
b/arch/arm/cpu/armv7/tegra2/Makefile
index 687c887..f1ea915 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS := board.o sys_info.o timer.o
+COBJS := ap20.o board.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
new file mode 100644
index 000..d0ad41f
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -0,0 +1,366 @@
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation www.nvidia.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include ap20.h
+#include asm/io.h
+#include asm/arch/tegra2.h
+#include asm/arch/clk_rst.h
+#include asm/arch/pmc.h
+#include asm/arch/pinmux.h
+#include asm/arch/scu.h
+#include common.h
+
+u32 s_first_boot = 1;
+
+static void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg, clk;
+
+ /*
+* NOTE:
+* Regardless of whether the request is to enable or disable the CPU
+* clock, every processor in the CPU complex except the master (CPU 0)
+* will have it's clock stopped because the AVP only talks to the
+* master. The AVP does not know (nor does it need to know) that there
+* are multiple processors in the CPU complex.
+*/
+
+ if (enable) {
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ writel(CCLK_BURST_POLICY, clkrst-crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, clkrst-crc_super_cclk_div);
+ }
+
+ /* Fetch the register containing the main CPU complex clock enable */
+ reg = readl(clkrst-crc_clk_out_enb_l);
+ reg |= CLK_ENB_CPU;
+
+ /*
+* Read the register containing the individual CPU clock
Re: [U-Boot] [PATCH] arm: Tegra2: add support for A9 CPU init
Albert,
On Sun, Mar 13, 2011 at 10:46 AM, Albert ARIBAUD albert.arib...@free.fr wrote:
Le 16/02/2011 21:26, Tom Warren a écrit :
Signed-off-by: Tom Warrentwar...@nvidia.com
---
arch/arm/cpu/armv7/start.S | 6 +
arch/arm/cpu/armv7/tegra2/Makefile | 2 +-
arch/arm/cpu/armv7/tegra2/ap20.c | 490
This one has an extra empty line at end of file.
Thanks - I'll remove it.
+void cold_boot(void)
+{
+ asm volatile(
+
+ msr cpsr_c, #0xd3 \n
+ /*
+ * Check current processor: CPU or AVP?
+ * If AVP, go to AVP boot code, else continue on.
+ */
+ mov r0, %0 \n
+ ldrb r2, [r0, %1] \n
+ /* are we the CPU? */
+ cmp r2, %2 \n
+ mov sp, %3 \n
+ /* leave in some symbols for release debugging */
+ mov r3, %6 \n
+ str r3, [sp, #-4]! \n
+ str r3, [sp, #-4]! \n
+ /* yep, we are the CPU */
+ bxeq %4 \n
+ /* AVP Initialization follows this path */
+ mov sp, %5 \n
+ /* leave in some symbols for release debugging */
+ mov r3, %6 \n
+ str r3, [sp, #-4]! \n
+ str r3, [sp, #-4]! \n
+
+ /* Init and Start CPU */
+ b startup_cpu \n
+ :
+ : i(NV_PA_PG_UP_BASE),
If I'm not mistaken, NV_PA_PG_UP_BASE could be used just as well directly in
the asm statement instead of via %0 and i(), as anyway the asm will be
preprocessed and the macro will turn to a number. That would simplify the
asm instruction as a whole and make the asm statement more understandable
(also applies to other macros used similarly).
Yeah, this code came this way from our bringup group for out in-house
bootloader, and it's always been confusing.
I'll try to simplify it when I incorporate Peter's critiques. Thanks.
Apart from that, I must admit I don't know the Tegra2/A9 well enough to
comment further.
amicalement,
Amicalement,
--
Albert.
Thanks for the input,
Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Tegra2: add support for A9 CPU init
Peter,
On Mon, Mar 14, 2011 at 8:33 AM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
I'm not too familiar with the architecture, so many comments are
aesthetic. It would be a good idea to run the patch through
checkpatch.pl too.
I run checkpatch on every submission. Only 1 warning was generated
(about an extern), and no errors.
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 684f2d2..50a1725 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,6 +70,12 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TEGRA2
+.globl _armboot_start
+_armboot_start:
+ .word _start
+#endif
+
It'd be good to add a comment about what's going on above, and why its
tegra2-specific. Eg why is it needed?
Tegra uses 2 separate CPUs - the AVP (ARM7TDI) and the dual-core A9. A
bootloader first runs on the AVP and sets things up for the CPU
complex to take over.
The CPU complex jumps here during it's init phase/boot (from it's
reset vector). It needs a dereferenced jump to the _start code in
start.S (which in turn chains to the reset code).
I'll add a comment about this in the next patch.
snip
+static void init_pll_x(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE;
+ u32 reg;
The spaces in front of reg can be removed. Ditto for all
functions/variables.
Not sure what you mean, here, Peter. There are no spaces here in my
ap20.c file, just tabs.
Please clarify.
+ /* Is PLL-X already running? */
+ reg = readl(clkrst-crc_pllx_base);
+ if (reg PLL_ENABLE)
+ return;
+
+ /* Do PLLX init if it isn't running, but BootROM sets it, so TBD */
+}
The above function looks incorrect.
What looks incorrect? It checks to see if the PLL is already
running/enabled, and returns if it is.
Tegra2 mask ROM (BootROM) currently always sets PLLX, so this will
always return, but the comment is there for future chips that may not
set up PLLX.
+static void set_cpu_reset_vector(u32 vector)
+{
+ writel(vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+}
Is it worth breaking this out into its own function? The define names
make it pretty clear what is being done, and its only called from 1
location.
I can move the writel() to the called location and remove this func.
+static void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE;
+ u32 reg, clk;
+
+ /*
+ * NOTE:
+ * Regardless of whether the request is to enable or disable the CPU
+ * clock, every processor in the CPU complex except the master (CPU 0)
+ * will have it's clock stopped because the AVP only talks to the
+ * master. The AVP does not know (nor does it need to know) that there
+ * are multiple processors in the CPU complex.
+ */
+
+ /* Need to initialize PLLX? */
+ if (enable) {
+ /* Initialize PLL */
+ init_pll_x();
+
+ /* Wait until stable */
+ udelay(NVBOOT_CLOCKS_PLL_STABILIZATION_DELAY);
+
+ reg = CCLK_BURST_POLICY;
+ writel(reg, clkrst-crc_cclk_brst_pol);
It'd look cleaner to not set reg for each access, just use the define
directly. I'd personally use less temporary variables in general and
only use them when it made the code cleaner and easier to understand.
Will do. This code was ported from our orignal, in-house bootloader,
so it's going to be a bit hairy.
+ reg = SUPER_CCLK_DIVIDER;
+ writel(reg, clkrst-crc_super_cclk_div);
+ }
+
+ /* Fetch the register containing the main CPU complex clock enable */
+ reg = readl(clkrst-crc_clk_out_enb_l);
Is this read necessary? You overwrite reg unconditionally below.
Yeah, I saw that and did a rewrite a week or two ago, but was waiting
to incorporate into the next patch to get everything in one place.
+ /*
+ * Read the register containing the individual CPU clock enables and
+ * always stop the clock to CPU 1.
+ */
+ clk = readl(clkrst-crc_clk_cpu_cmplx);
+ clk |= CPU1_CLK_STP;
+
+ if (enable) {
+ /* Enable the CPU clock */
+ reg = readl(clkrst-crc_clk_out_enb_l);
+ reg |= CLK_ENB_CPU;
+ clk = readl(clkrst-crc_clk_cpu_cmplx);
+ clk = ~CPU0_CLK_STP;
+ } else {
+ /* Disable the CPU clock */
+ reg = readl(clkrst-crc_clk_out_enb_l);
+ reg |= CLK_ENB_CPU;
+ clk = readl(clkrst-crc_clk_cpu_cmplx);
+ clk |= CPU0_CLK_STP;
+ }
For if/elses that share common code, the common code should be broken
out. eg above only the one-line |=/= operations should be conditional.
Yep, already done as part of the previous cleanup. Just need to put it
into the full patchset #2.
+ writel(clk, clkrst-crc_clk_cpu_cmplx);
+
Re: [U-Boot] [PATCH] arm: Tegra2: add support for A9 CPU init
Peter,
On Mon, Mar 14, 2011 at 3:20 PM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
snip
+static void init_pll_x(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST
_BASE;
+ u32 reg;
The spaces in front of reg can be removed. Ditto for all
functions/variables.
Not sure what you mean, here, Peter. There are no spaces here in my
ap20.c file, just tabs.
Please clarify.
My email client converted to spaces I was referring to the u32 reg;
above. I think it should be u32spacereg instead of u32tabreg.
Other places in this patch spaces are used (eg in enable_cpu_clock, and
in the struct declaration above), so at a minimum the tabs/spaces should
be changed to be consistent, and typespacename seems cleanest to
me.
I see. I can change to typespacename globally, no problem.
+ /* Is PLL-X already running? */
+ reg = readl(clkrst-crc_pllx_base);
+ if (reg PLL_ENABLE)
+ return;
+
+ /* Do PLLX init if it isn't running, but BootROM sets it, so TBD */
+}
The above function looks incorrect.
What looks incorrect? It checks to see if the PLL is already
running/enabled, and returns if it is.
Tegra2 mask ROM (BootROM) currently always sets PLLX, so this will
always return, but the comment is there for future chips that may not
set up PLLX.
It looks like a function that does a read of a value it doesn't care
about, does an unnecessary comparison, and then returns either way,
without doing anything:) If/when you want to do future stuff with the
PLL-X, code should be added then - as is it doesn't do anything and is
confusing. The general policy of U-Boot is not to add dead code.
OK, so not really incorrect, just unnecessary. Agreed - again a
vestigial leftover from our in-house code. I'll remove it.
snip
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ reg = readl(pmc-pmc_cntrl);
+ reg |= CPUPWRREQ_OE;
+ writel(reg, pmc-pmc_cntrl);
+
+ /* Delay to allow for stable power (CPU_PWR_REQ - VDD_CPU from
PMU) */
+ udelay(3750);
Ditto for description.
Ditto on why the delay? In this case, I did find a reference to the
time needed between the request from the chipset to the PMU, hence the
comment.
It'd be nice mention that reference in the comment. For those designing
boards around your chips, during debug they will look through the
initialization code and wonder I wonder if we need to delay longer, or
I'm not using the same power supply sequencer, I wonder if this might
be a problem. If you more explicitly state where the delay came from,
or what the delay specifically accomplishes, it saves others from having
to guess and investigate.
OK, I'll expand the comment.
+}
+
+static void reset_A9_cpu(int reset)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE;
+ u32 reg, cpu;
+
+ /*
+ * NOTE: Regardless of whether the request is to hold the CPU in
reset
+ * or take it out of reset, every processor in the CPU complex
+ * except the master (CPU 0) will be held in reset because the
+ * AVP only talks to the master. The AVP does not know that
there
+ * are multiple processors in the CPU complex.
+ */
+
+ /* Hold CPU 1 in reset */
+ cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1;
+ writel(cpu, clkrst-crc_cpu_cmplx_set);
The cpu variable can be removed.
It could be, sure. But it makes the line longer, 80 chars, and hence
it would have to be broken into two lines.
Actually, now that I look at the code again, it appears that 'cpu'
later should be OR'd with the SET_/CLR_DBGRESET0, etc. bits, depending
on the state of 'reset'.
I'll give it a rewrite for the next patch.
Its a matter of preference, but is acceptable either way. I think:
+ writel(SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1,
+ clkrst-crc_cpu_cmplx_set);
makes it clearer what is going on. Setting 'cpu', then writing would
imply to me that 'cpu' has some additional purpose, or is being used
later. If you restructure the code, this comment will likely be moot.
snip
+ if (enable) {
+ /*
+ * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down
by
+ * 1.5, giving an effective frequency of 144MHz.
+ * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
+ * (bits 7:0), so 0001b == 1.5 (n+1 + .5)
+ */
+ src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
+ writel(src, clkrst-crc_clk_src_csite);
+
+ /* Unlock the CPU CoreSight interfaces */
+ rst = 0xC5ACCE55;
What's this number? Is there a define that could be used instead?
Sure, I can add a #define. Some magic
Re: [U-Boot] [PATCH] arm: Tegra2: add support for A9 CPU init
Albert, On Tue, Feb 22, 2011 at 4:57 PM, Albert ARIBAUD albert.arib...@free.fr wrote: Hi Tom, Le 23/02/2011 00:41, Tom Warren a écrit : Anyone willing to review this? I'd like to get it pulled in to Albert's arm repo ASAP. I should be able to review it during the week-end--not before, sorry. Any chance you can give this some bandwidth? I'd like to get it into the arm tree. As far as I know, it should still apply, but let me know if I need to rebase it against next (or master). Thanks, Tom Note however that since this is not a bugfix and it came after the merge window closed, it would go to u-boot-arm/next, not /master; it will go to u-boot-arm/master after the the upcoming release (and then to u-boot/master when the next merge window closes). Thanks, Tom Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Tegra2: add support for A9 CPU init
Albert, On Tue, Feb 22, 2011 at 4:57 PM, Albert ARIBAUD albert.arib...@free.fr wrote: Hi Tom, Le 23/02/2011 00:41, Tom Warren a écrit : Anyone willing to review this? I'd like to get it pulled in to Albert's arm repo ASAP. I should be able to review it during the week-end--not before, sorry. Thank you. That would be fine - no rush. Note however that since this is not a bugfix and it came after the merge window closed, it would go to u-boot-arm/next, not /master; it will go to u-boot-arm/master after the the upcoming release (and then to u-boot/master when the next merge window closes). Understood. Just wanted an ACK, etc. so I can sign off on the CPU work and move on to the drivers. Thanks, Tom Amicalement, -- Albert. Thanks for your help, Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Tegra2 Seaboard: Fix mach_type to match mach-type.h update
Seaboard build stopped working due to Sandeep's recent mach-types.h update to match the Linux kernel. Change Seaboard to use MACH_TYPE_SEABOARD. Tom Warren (1): arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update include/configs/seaboard.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update
Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/seaboard.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index fd87560..59eef56 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -37,7 +37,7 @@ #define CONFIG_TEGRA2_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD +#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #endif /* __CONFIG_H */ -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Tegra2 Seaboard: Fix mach_type to match mach-type.h update
Seaboard build stopped working due to Sandeep's recent mach-types.h update to match the Linux kernel. Change Seaboard to use MACH_TYPE_SEABOARD. Tom Warren (1): arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update include/configs/seaboard.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update
OK, I'm an idiot. I see now that I needed to add -n to format-patch to add the numbering to the [PATCH] header. Sorry for the noise - resending now with the corrected patchset. Tom On Wed, Feb 23, 2011 at 12:54 PM, Tom Warren twarren.nvi...@gmail.com wrote: Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/seaboard.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index fd87560..59eef56 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -37,7 +37,7 @@ #define CONFIG_TEGRA2_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD +#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #endif /* __CONFIG_H */ -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update
Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/seaboard.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index fd87560..59eef56 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -37,7 +37,7 @@ #define CONFIG_TEGRA2_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD +#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #endif /* __CONFIG_H */ -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/1] Tegra2 Seaboard: Fix mach_type to match mach-type.h update
Seaboard build stopped working due to Sandeep's recent mach-types.h update to match the Linux kernel. Change Seaboard to use MACH_TYPE_SEABOARD. Tom Warren (1): arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update include/configs/seaboard.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update
Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/seaboard.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index fd87560..59eef56 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -37,7 +37,7 @@ #define CONFIG_TEGRA2_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD +#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #endif /* __CONFIG_H */ -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Tegra2: add support for A9 CPU init
Anyone willing to review this? I'd like to get it pulled in to
Albert's arm repo ASAP.
Thanks,
Tom
On Wed, Feb 16, 2011 at 1:26 PM, Tom Warren twarren.nvi...@gmail.com wrote:
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/cpu/armv7/start.S | 6 +
arch/arm/cpu/armv7/tegra2/Makefile | 2 +-
arch/arm/cpu/armv7/tegra2/ap20.c | 490
arch/arm/cpu/armv7/tegra2/ap20.h | 105 ++
arch/arm/include/asm/arch-tegra2/clk_rst.h | 27 ++
arch/arm/include/asm/arch-tegra2/pmc.h | 8 +
arch/arm/include/asm/arch-tegra2/scu.h | 43 +++
arch/arm/include/asm/arch-tegra2/tegra2.h | 5 +
board/nvidia/common/board.c | 10 +
board/nvidia/common/board.h | 29 ++
include/configs/harmony.h | 1 +
include/configs/seaboard.h | 1 +
include/configs/tegra2-common.h | 2 +
13 files changed, 728 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.c
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.h
create mode 100644 arch/arm/include/asm/arch-tegra2/scu.h
create mode 100644 board/nvidia/common/board.h
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 684f2d2..50a1725 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,6 +70,12 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TEGRA2
+.globl _armboot_start
+_armboot_start:
+ .word _start
+#endif
+
/*
* These are defined in the board-specific linker script.
*/
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile
b/arch/arm/cpu/armv7/tegra2/Makefile
index 687c887..f1ea915 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS := board.o sys_info.o timer.o
+COBJS := ap20.o board.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c
b/arch/arm/cpu/armv7/tegra2/ap20.c
new file mode 100644
index 000..89d0d5e
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -0,0 +1,490 @@
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation www.nvidia.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include ap20.h
+#include asm/io.h
+#include asm/arch/tegra2.h
+#include asm/arch/clk_rst.h
+#include asm/arch/pmc.h
+#include asm/arch/pinmux.h
+#include asm/arch/scu.h
+#include common.h
+
+static void init_pll_x(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* Is PLL-X already running? */
+ reg = readl(clkrst-crc_pllx_base);
+ if (reg PLL_ENABLE)
+ return;
+
+ /* Do PLLX init if it isn't running, but BootROM sets it, so TBD */
+}
+
+static void set_cpu_reset_vector(u32 vector)
+{
+ writel(vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+}
+
+static void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE;
+ u32 reg, clk;
+
+ /*
+ * NOTE:
+ * Regardless of whether the request is to enable or disable the CPU
+ * clock, every processor in the CPU complex except the master (CPU 0)
+ * will have it's clock stopped because the AVP only talks to the
+ * master. The AVP does not know (nor does it need to know) that there
+ * are multiple processors in the CPU complex.
+ */
+
+ /* Need to initialize PLLX? */
+ if (enable) {
+ /* Initialize PLL */
+ init_pll_x();
+
+ /* Wait until stable */
+ udelay(NVBOOT_CLOCKS_PLL_STABILIZATION_DELAY);
+
+ reg = CCLK_BURST_POLICY;
+ writel(reg, clkrst-crc_cclk_brst_pol);
+
+ reg = SUPER_CCLK_DIVIDER;
+ writel(reg, clkrst-crc_super_cclk_div);
+ }
+
+ /* Fetch the register
[U-Boot] [PATCH] Add A9 CPU complex support
This patch adds code to initialize the A9 dual CPU complex in the Tegra2 SoC. The code is run on the AVP first to set up the A9 and Coresight clocks, then the AVP is halted, the A9 CPU is brought out of reset, and the code executes again on the CPU, but down a slightly different path. Normal POST then proceeds using the A9 CPU. Tom Warren (1): arm: Tegra2: add support for A9 CPU init arch/arm/cpu/armv7/start.S |6 + arch/arm/cpu/armv7/tegra2/Makefile |2 +- arch/arm/cpu/armv7/tegra2/ap20.c | 490 arch/arm/cpu/armv7/tegra2/ap20.h | 105 ++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 27 ++ arch/arm/include/asm/arch-tegra2/pmc.h |8 + arch/arm/include/asm/arch-tegra2/scu.h | 43 +++ arch/arm/include/asm/arch-tegra2/tegra2.h |5 + board/nvidia/common/board.c| 10 + board/nvidia/common/board.h| 29 ++ include/configs/harmony.h |1 + include/configs/seaboard.h |1 + include/configs/tegra2-common.h|2 + 13 files changed, 728 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.c create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.h create mode 100644 arch/arm/include/asm/arch-tegra2/scu.h create mode 100644 board/nvidia/common/board.h -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: Tegra2: add support for A9 CPU init
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/cpu/armv7/start.S |6 +
arch/arm/cpu/armv7/tegra2/Makefile |2 +-
arch/arm/cpu/armv7/tegra2/ap20.c | 490
arch/arm/cpu/armv7/tegra2/ap20.h | 105 ++
arch/arm/include/asm/arch-tegra2/clk_rst.h | 27 ++
arch/arm/include/asm/arch-tegra2/pmc.h |8 +
arch/arm/include/asm/arch-tegra2/scu.h | 43 +++
arch/arm/include/asm/arch-tegra2/tegra2.h |5 +
board/nvidia/common/board.c| 10 +
board/nvidia/common/board.h| 29 ++
include/configs/harmony.h |1 +
include/configs/seaboard.h |1 +
include/configs/tegra2-common.h|2 +
13 files changed, 728 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.c
create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.h
create mode 100644 arch/arm/include/asm/arch-tegra2/scu.h
create mode 100644 board/nvidia/common/board.h
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 684f2d2..50a1725 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,6 +70,12 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TEGRA2
+.globl _armboot_start
+_armboot_start:
+.word _start
+#endif
+
/*
* These are defined in the board-specific linker script.
*/
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile
b/arch/arm/cpu/armv7/tegra2/Makefile
index 687c887..f1ea915 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS := board.o sys_info.o timer.o
+COBJS := ap20.o board.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
new file mode 100644
index 000..89d0d5e
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -0,0 +1,490 @@
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation www.nvidia.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include ap20.h
+#include asm/io.h
+#include asm/arch/tegra2.h
+#include asm/arch/clk_rst.h
+#include asm/arch/pmc.h
+#include asm/arch/pinmux.h
+#include asm/arch/scu.h
+#include common.h
+
+static void init_pll_x(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* Is PLL-X already running? */
+ reg = readl(clkrst-crc_pllx_base);
+ if (reg PLL_ENABLE)
+ return;
+
+ /* Do PLLX init if it isn't running, but BootROM sets it, so TBD */
+}
+
+static void set_cpu_reset_vector(u32 vector)
+{
+ writel(vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+}
+
+static void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg, clk;
+
+ /*
+* NOTE:
+* Regardless of whether the request is to enable or disable the CPU
+* clock, every processor in the CPU complex except the master (CPU 0)
+* will have it's clock stopped because the AVP only talks to the
+* master. The AVP does not know (nor does it need to know) that there
+* are multiple processors in the CPU complex.
+*/
+
+ /* Need to initialize PLLX? */
+ if (enable) {
+ /* Initialize PLL */
+ init_pll_x();
+
+ /* Wait until stable */
+ udelay(NVBOOT_CLOCKS_PLL_STABILIZATION_DELAY);
+
+ reg = CCLK_BURST_POLICY;
+ writel(reg, clkrst-crc_cclk_brst_pol);
+
+ reg = SUPER_CCLK_DIVIDER;
+ writel(reg, clkrst-crc_super_cclk_div);
+ }
+
+ /* Fetch the register containing the main CPU complex clock enable */
+ reg = readl(clkrst-crc_clk_out_enb_l);
+
+ /*
+* Read the register containing the individual CPU clock enables and
+* always stop the clock to CPU 1.
+*/
+ clk = readl(clkrst-crc_clk_cpu_cmplx);
+ clk |= CPU1_CLK_STP
Re: [U-Boot] ARM: NVIDIA Tegra2 SoC support, running/flashing on Harmony
Marcel, On Sun, Feb 13, 2011 at 12:08 PM, Anton Staaf robot...@chromium.org wrote: Hi Marcel, I think your best bet right now is to use the nvflash tool provided in the Chromium chroot. That's what the burn-u-boot script uses (by the way, that script recently changed to write_tegra_bios (I know, bad name), and will probably change again to something like cros_write_firmware). That script and associated files in the Harmony overlay for Chromium OS src/overlay/overlay-variant-tegra2-dev-board knows how to write to the NAND on the Harmony. -Anton On Fri, Feb 11, 2011 at 12:56 AM, mar...@ziswiler.com mar...@ziswiler.com wrote: Hi Tom I am working with NVIDIA Harmony board and have chromium U-Boot 2009.11 working on it nicely after just changing the TEXT_BASE in board/tegra2/harmony/config.mk from 0x00e08000 to 0x00108000 as outlined in the NVIDIA developer forum. Now I saw your recent work on mainlining basic NVIDIA Tegra2 SoC support which is currently only available in the ARM U-Boot custodian tree at git://git.denx.de/u-boot-arm.git. I can compile it fine for Harmony but I have not figured out how one could get this one flashed onto the board. Can you quickly outline what tool you are using (e.g. vibrante burnflash, fastboot, nvflash or chromium burn-u-boot) and what the exact parameters thereof (e.g. load addresses and such) are? Thanks for your help! Cheers Marcel You can follow Anton's instructions above. I'm using OpenOCD and a JTAG board during the early stages to load my U-Boot images into RAM on Harmony and Seaboard. Once I get to the nand/spi/mmc drivers, I'll start testing with nvflash to ensure that the system is boot-strappable. Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V6 0/4] Add basic NVIDIA Tegra2 SoC support
Albert, On Fri, Feb 4, 2011 at 11:50 PM, Albert ARIBAUD albert.arib...@free.fr wrote: Le 02/02/2011 19:44, Albert ARIBAUD a écrit : Le 02/02/2011 18:06, Tom Warren a écrit : Mike, On Wed, Feb 2, 2011 at 12:57 AM, Mike Rapoportm...@compulab.co.il wrote: On 02/02/11 02:09, Tom Warren wrote: I haven't seen any new feedback on this version (V6) of the patchset since it was posted. Wolfgang, Mike, Peter, et al - are you happy with the current patch? I'm Ok with the current patch. Thanks, Mike. Appreciate your help. If so, when can I expect it to be pushed? Who has to push/accept/apply the patch? Wolfgang, or the ARM custodian? That would be me. Wolfgang, since the V1 patch series predates the merge window close and you have not yet pulled in my request, do you accept that I take these patches in and re-send a pull request? Seeing as rc1 is out with my previous pull request pulled in: Patchset applied to u-boot-arm (with trivial merge to boards.cfg), will send a new pull request today for rc2. Amicalement, -- Albert. Thank you. Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V6 0/4] Add basic NVIDIA Tegra2 SoC support
Mike, On Wed, Feb 2, 2011 at 12:57 AM, Mike Rapoport m...@compulab.co.il wrote: On 02/02/11 02:09, Tom Warren wrote: I haven't seen any new feedback on this version (V6) of the patchset since it was posted. Wolfgang, Mike, Peter, et al - are you happy with the current patch? I'm Ok with the current patch. Thanks, Mike. Appreciate your help. If so, when can I expect it to be pushed? Who has to push/accept/apply the patch? Wolfgang, or the ARM custodian? Thanks. Thanks, Tom On Thu, Jan 27, 2011 at 1:58 PM, Tom Warren twarren.nvi...@gmail.com wrote: This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. Changes for V2: - Coding style cleanup - Remove mach-types.h change; wait for ARM kernel sync-up - Move serial driver changes to separate patch - Use board/nvidia/ instead of /board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 register/bit defines in UART init - Change nv-common.h config file to tegra2-common.h Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Changes for V4: - Use address of HW structs (pmc, etc.) in readl/writel - Remove empty lines, fix mixed case hex #s comments in header(s) - Move board/nvidia/common/board.c UART code header to arch/arm/cpu/armv7/tegra2/ - Declare internal functions as static in UART code Changes for V5: - Move arch/arm/cpu/armv7/uart.c board.h to drivers/serial and rename to serial_tegra2.c - Remove use of uart_num UART_A/D in serial_tegra2, simplify code Changes for V6: - Fix uart.c add delete in previous patchset - Move pinmux clock init code to common board file as per review - Use #if defined() where possible in config files/UART code - Drop all typedef and volatile struct declarations in header files Tom Warren (4): arm: Tegra2: Add basic NVIDIA Tegra2 SoC support serial: Add Tegra2 serial port support arm: Tegra2: Add support for NVIDIA Harmony board arm: Tegra2: Add support for NVIDIA Seaboard board MAINTAINERS | 5 + arch/arm/cpu/armv7/tegra2/Makefile | 48 +++ arch/arm/cpu/armv7/tegra2/board.c | 88 arch/arm/cpu/armv7/tegra2/config.mk | 28 arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 65 + arch/arm/cpu/armv7/tegra2/sys_info.c | 35 + arch/arm/cpu/armv7/tegra2/timer.c | 122 arch/arm/include/asm/arch-tegra2/clk_rst.h | 165 ++ arch/arm/include/asm/arch-tegra2/pinmux.h | 55 arch/arm/include/asm/arch-tegra2/pmc.h | 124 + arch/arm/include/asm/arch-tegra2/sys_proto.h | 35 + arch/arm/include/asm/arch-tegra2/tegra2.h | 49 +++ arch/arm/include/asm/arch-tegra2/uart.h | 47 ++ board/nvidia/common/board.c | 193 ++ board/nvidia/harmony/Makefile | 50 +++ board/nvidia/seaboard/Makefile | 50 +++ boards.cfg | 2 + common/serial.c | 3 +- drivers/serial/Makefile | 1 + drivers/serial/serial_tegra2.c | 77 ++ drivers/serial/serial_tegra2.h | 29 include/configs/harmony.h | 49 +++ include/configs/seaboard.h | 43 ++ include/configs/tegra2-common.h | 160 + include/serial.h | 3 +- 25 files changed, 1524 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c create mode 100644 board/nvidia/harmony/Makefile create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 drivers/serial/serial_tegra2.c
Re: [U-Boot] [Patch V6 0/4] Add basic NVIDIA Tegra2 SoC support
I haven't seen any new feedback on this version (V6) of the patchset since it was posted. Wolfgang, Mike, Peter, et al - are you happy with the current patch? If so, when can I expect it to be pushed? Thanks, Tom On Thu, Jan 27, 2011 at 1:58 PM, Tom Warren twarren.nvi...@gmail.com wrote: This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. Changes for V2: - Coding style cleanup - Remove mach-types.h change; wait for ARM kernel sync-up - Move serial driver changes to separate patch - Use board/nvidia/ instead of /board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 register/bit defines in UART init - Change nv-common.h config file to tegra2-common.h Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Changes for V4: - Use address of HW structs (pmc, etc.) in readl/writel - Remove empty lines, fix mixed case hex #s comments in header(s) - Move board/nvidia/common/board.c UART code header to arch/arm/cpu/armv7/tegra2/ - Declare internal functions as static in UART code Changes for V5: - Move arch/arm/cpu/armv7/uart.c board.h to drivers/serial and rename to serial_tegra2.c - Remove use of uart_num UART_A/D in serial_tegra2, simplify code Changes for V6: - Fix uart.c add delete in previous patchset - Move pinmux clock init code to common board file as per review - Use #if defined() where possible in config files/UART code - Drop all typedef and volatile struct declarations in header files Tom Warren (4): arm: Tegra2: Add basic NVIDIA Tegra2 SoC support serial: Add Tegra2 serial port support arm: Tegra2: Add support for NVIDIA Harmony board arm: Tegra2: Add support for NVIDIA Seaboard board MAINTAINERS | 5 + arch/arm/cpu/armv7/tegra2/Makefile | 48 +++ arch/arm/cpu/armv7/tegra2/board.c | 88 arch/arm/cpu/armv7/tegra2/config.mk | 28 arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 65 + arch/arm/cpu/armv7/tegra2/sys_info.c | 35 + arch/arm/cpu/armv7/tegra2/timer.c | 122 arch/arm/include/asm/arch-tegra2/clk_rst.h | 165 ++ arch/arm/include/asm/arch-tegra2/pinmux.h | 55 arch/arm/include/asm/arch-tegra2/pmc.h | 124 + arch/arm/include/asm/arch-tegra2/sys_proto.h | 35 + arch/arm/include/asm/arch-tegra2/tegra2.h | 49 +++ arch/arm/include/asm/arch-tegra2/uart.h | 47 ++ board/nvidia/common/board.c | 193 ++ board/nvidia/harmony/Makefile | 50 +++ board/nvidia/seaboard/Makefile | 50 +++ boards.cfg | 2 + common/serial.c | 3 +- drivers/serial/Makefile | 1 + drivers/serial/serial_tegra2.c | 77 ++ drivers/serial/serial_tegra2.h | 29 include/configs/harmony.h | 49 +++ include/configs/seaboard.h | 43 ++ include/configs/tegra2-common.h | 160 + include/serial.h | 3 +- 25 files changed, 1524 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c create mode 100644 board/nvidia/harmony/Makefile create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 drivers/serial/serial_tegra2.c create mode 100644 drivers/serial/serial_tegra2.h create mode 100644 include/configs/harmony.h create mode 100644 include/configs/seaboard.h create mode 100644 include/configs/tegra2-common.h -- 1.7.3.5 ___ U-Boot
Re: [U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support
Mike, On Thu, Jan 27, 2011 at 12:41 AM, Mike Rapoport m...@compulab.co.il wrote: Tom, On 01/26/11 19:05, Tom Warren wrote: Mike, On Wed, Jan 26, 2011 at 1:13 AM, Mike Rapoport m...@compulab.co.il wrote: My point was that pin muxing belongs to the board code rather than to the driver. Driver should just assume that pins are configured elsewhere and it does not need to deal with pin muxing at all. I understand that point - sorry if I wasn't clear. No objection to having pinmux code in board files. Moreover, I'd prefer to see pinmux_board_init or something similar that configures all the pins at once rather than collection of pinmux_init_uart, pinmux_init_sdmmc, pinmux_init_gmi etc that will grow as more drivers are added. I see a couple of reasons not to do it that way. First, I don't know at this time what all the pinmux settings will be, since I haven't ported all the periph driver code yet. It's vastly different from what's acceptable in U-Boot, and will all need significant rewrite. It'd take me a week to gather all that info, and I'm not at full BW on this project (one of 4 on my plate right now). Second, I've been chastised before for including code/features in this initial patchset that aren't needed or used. I'm trying to keep the code as simple as possible to make it easier on reviewers and get through the review in as short a time as possible. This has already dragged on far longer than I thought it would. I'm willing to change the pinmux code to make it as generic as possible, but only if there's a consensus on the list that it has to be that way to get accepted pushed. I'm Ok with pinmux_init_uart in the board code for now. I think that the generic pinmux functionality can be added afterwards. Great. My main goal is to get the baseline Tegra2 support in upstream U-Boot. I'm happy to refine the pinmux approach in the next patchset. Either a generic pinmux as you propose, or a set of weak pinmux configs that can be overridden by another board design, etc. as Peter proposes. Thanks, Tom -- Sincerely yours, Mike. Thanks, Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V6 0/4] Add basic NVIDIA Tegra2 SoC support
This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. Changes for V2: - Coding style cleanup - Remove mach-types.h change; wait for ARM kernel sync-up - Move serial driver changes to separate patch - Use board/nvidia/ instead of /board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 register/bit defines in UART init - Change nv-common.h config file to tegra2-common.h Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Changes for V4: - Use address of HW structs (pmc, etc.) in readl/writel - Remove empty lines, fix mixed case hex #s comments in header(s) - Move board/nvidia/common/board.c UART code header to arch/arm/cpu/armv7/tegra2/ - Declare internal functions as static in UART code Changes for V5: - Move arch/arm/cpu/armv7/uart.c board.h to drivers/serial and rename to serial_tegra2.c - Remove use of uart_num UART_A/D in serial_tegra2, simplify code Changes for V6: - Fix uart.c add delete in previous patchset - Move pinmux clock init code to common board file as per review - Use #if defined() where possible in config files/UART code - Drop all typedef and volatile struct declarations in header files Tom Warren (4): arm: Tegra2: Add basic NVIDIA Tegra2 SoC support serial: Add Tegra2 serial port support arm: Tegra2: Add support for NVIDIA Harmony board arm: Tegra2: Add support for NVIDIA Seaboard board MAINTAINERS |5 + arch/arm/cpu/armv7/tegra2/Makefile | 48 +++ arch/arm/cpu/armv7/tegra2/board.c| 88 arch/arm/cpu/armv7/tegra2/config.mk | 28 arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 65 + arch/arm/cpu/armv7/tegra2/sys_info.c | 35 + arch/arm/cpu/armv7/tegra2/timer.c| 122 arch/arm/include/asm/arch-tegra2/clk_rst.h | 165 ++ arch/arm/include/asm/arch-tegra2/pinmux.h| 55 arch/arm/include/asm/arch-tegra2/pmc.h | 124 + arch/arm/include/asm/arch-tegra2/sys_proto.h | 35 + arch/arm/include/asm/arch-tegra2/tegra2.h| 49 +++ arch/arm/include/asm/arch-tegra2/uart.h | 47 ++ board/nvidia/common/board.c | 193 ++ board/nvidia/harmony/Makefile| 50 +++ board/nvidia/seaboard/Makefile | 50 +++ boards.cfg |2 + common/serial.c |3 +- drivers/serial/Makefile |1 + drivers/serial/serial_tegra2.c | 77 ++ drivers/serial/serial_tegra2.h | 29 include/configs/harmony.h| 49 +++ include/configs/seaboard.h | 43 ++ include/configs/tegra2-common.h | 160 + include/serial.h |3 +- 25 files changed, 1524 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c create mode 100644 board/nvidia/harmony/Makefile create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 drivers/serial/serial_tegra2.c create mode 100644 drivers/serial/serial_tegra2.h create mode 100644 include/configs/harmony.h create mode 100644 include/configs/seaboard.h create mode 100644 include/configs/tegra2-common.h -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V6 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Coding style cleanup - Move serial driver changes to separate patch - Use board/nvidia instead of board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 registers/bit defines in UART init Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Changes for V4: - Use address of HW structs (pmc, etc.) in readl/writel - Remove empty lines, fix mixed case hex #s comments in header(s) - Move board/nvidia/common/board.c UART code header to arch/arm/cpu/armv7/tegra2/ - Declare internal functions as static in UART code Changes for V6: - Fix uart.c add delete in previous patchset - Move pinmux clock init code to common board file as per review - Use #if defined() where possible in config files/UART code - Drop all typedef and volatile struct declarations in header files arch/arm/cpu/armv7/tegra2/Makefile | 48 +++ arch/arm/cpu/armv7/tegra2/board.c| 88 arch/arm/cpu/armv7/tegra2/config.mk | 28 arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 65 + arch/arm/cpu/armv7/tegra2/sys_info.c | 35 + arch/arm/cpu/armv7/tegra2/timer.c| 122 arch/arm/include/asm/arch-tegra2/clk_rst.h | 165 ++ arch/arm/include/asm/arch-tegra2/pinmux.h| 55 arch/arm/include/asm/arch-tegra2/pmc.h | 124 + arch/arm/include/asm/arch-tegra2/sys_proto.h | 35 + arch/arm/include/asm/arch-tegra2/tegra2.h| 49 +++ arch/arm/include/asm/arch-tegra2/uart.h | 47 ++ board/nvidia/common/board.c | 193 ++ 13 files changed, 1054 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile new file mode 100644 index 000..687c887 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010,2011 Nvidia Corporation. +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS := board.o sys_info.o timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all:$(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c new file mode 100644 index 000..9061d18 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2
[U-Boot] [Patch V6 2/4] serial: Add Tegra2 serial port support
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Move serial driver to separate patch
Changes for V5:
- Move arch/arm/cpu/armv7/uart.c board.h to drivers/serial and
rename to serial_tegra2.c
- Remove use of uart_num UART_A/D in serial_tegra2, simplify code
Changes for V6:
- Fix uart.c add delete in previous patchset
- Move pinmux clock init code to common board file as per review
- Use #if defined() where possible in config files/UART code
common/serial.c|3 +-
drivers/serial/Makefile|1 +
drivers/serial/serial_tegra2.c | 77
drivers/serial/serial_tegra2.h | 29 +++
include/serial.h |3 +-
5 files changed, 111 insertions(+), 2 deletions(-)
create mode 100644 drivers/serial/serial_tegra2.c
create mode 100644 drivers/serial/serial_tegra2.h
diff --git a/common/serial.c b/common/serial.c
index 051ae4e..8ebf9a5 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void)
#elif defined(CONFIG_4xx) \
|| defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \
|| defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \
- || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520)
+ || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) \
+ || defined(CONFIG_TEGRA2)
#if defined(CONFIG_CONS_INDEX) defined(CONFIG_SYS_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return eserial1_device;
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 7d221fc..5a6011e 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -55,6 +55,7 @@ COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_TEGRA2) += serial_tegra2.o
COBJS-$(CONFIG_USB_TTY) += usbtty.o
COBJS := $(sort $(COBJS-y))
diff --git a/drivers/serial/serial_tegra2.c b/drivers/serial/serial_tegra2.c
new file mode 100644
index 000..8ff34ea
--- /dev/null
+++ b/drivers/serial/serial_tegra2.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include ns16550.h
+#include asm/io.h
+#include asm/arch/tegra2.h
+#include serial_tegra2.h
+
+static void setup_uart(struct uart_ctlr *u)
+{
+ u32 reg;
+
+ /* Prepare the divisor value */
+ reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16;
+
+ /* Set up UART parameters */
+ writel(UART_LCR_DLAB, u-uart_lcr);
+ writel(reg, u-uart_thr_dlab_0);
+ writel(0, u-uart_ier_dlab_0);
+ writel(0, u-uart_lcr);/* clear DLAB */
+ writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \
+ UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), u-uart_iir_fcr);
+ writel(0, u-uart_ier_dlab_0);
+ writel(UART_LCR_WLS_8, u-uart_lcr); /* 8N1 */
+ writel(UART_MCR_RTS, u-uart_mcr);
+ writel(0, u-uart_msr);
+ writel(0, u-uart_spr);
+ writel(0, u-uart_irda_csr);
+ writel(0, u-uart_asr);
+ writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), u-uart_iir_fcr);
+
+ /* Flush any old characters out of the RX FIFO */
+ reg = readl(u-uart_lsr);
+
+ while (reg UART_LSR_DR) {
+ reg = readl(u-uart_thr_dlab_0);
+ reg = readl(u-uart_lsr);
+ }
+}
+
+/*
+ * Routine: uart_init
+ * Description: init the UART clocks, muxes, and baudrate/parity/etc.
+ */
+void uart_init(void)
+{
+ struct uart_ctlr *uart = (struct uart_ctlr *)NV_PA_APB_UARTD_BASE;
+#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
+ setup_uart(uart);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
+ uart = (struct uart_ctlr *)NV_PA_APB_UARTA_BASE;
+
+ setup_uart(uart);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
+}
diff --git a/drivers/serial/serial_tegra2.h b/drivers/serial/serial_tegra2.h
new file mode 100644
index 000..5704800
--- /dev/null
+++ b
[U-Boot] [Patch V6 3/4] arm: Tegra2: Add support for NVIDIA Harmony board
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Use board/nvidia/ instead of /board/tegra - Change nv-common.h config file to tegra2-common.h Changes for V6: - Use #if defined() where possible in config files/UART code MAINTAINERS |4 + board/nvidia/harmony/Makefile | 50 boards.cfg |1 + include/configs/harmony.h | 49 include/configs/tegra2-common.h | 160 +++ 5 files changed, 264 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/harmony/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/tegra2-common.h diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..b5cff19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -841,6 +841,10 @@ Prafulla Wadaskar prafu...@marvell.com rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Tom Warren twar...@nvidia.com + + harmony Tegra2 (ARM7 A9 Dual Core) + Matthias Weisser weiss...@arcor.de jadecpu ARM926EJS (MB86R01 SoC) diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/harmony/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index 94b8745..ee7c4b7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -122,6 +122,7 @@ omap4_panda arm armv7 panda ti omap4_sdp4430arm armv7 sdp4430 ti omap4 s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx +harmony arm armv7 harmony nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/harmony.h b/include/configs/harmony.h new file mode 100644 index 000..d004f31 --- /dev/null +++ b/include/configs/harmony.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (Harmony) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Harmony + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI
[U-Boot] [Patch V6 4/4] arm: Tegra2: Add support for NVIDIA Seaboard board
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Remove mach-types.h change; wait for ARM kernel sync-up - Use board/nvidia instead of board/tegra Changes for V6: - Use #if defined() where possible in config files/UART code MAINTAINERS|1 + board/nvidia/seaboard/Makefile | 50 boards.cfg |1 + include/configs/seaboard.h | 43 ++ 4 files changed, 95 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 include/configs/seaboard.h diff --git a/MAINTAINERS b/MAINTAINERS index b5cff19..f4795d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -844,6 +844,7 @@ Prafulla Wadaskar prafu...@marvell.com Tom Warren twar...@nvidia.com harmony Tegra2 (ARM7 A9 Dual Core) + seaboardTegra2 (ARM7 A9 Dual Core) Matthias Weisser weiss...@arcor.de diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/seaboard/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index ee7c4b7..3c4c249 100644 --- a/boards.cfg +++ b/boards.cfg @@ -123,6 +123,7 @@ omap4_sdp4430arm armv7 sdp4430 ti s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx harmony arm armv7 harmony nvidia tegra2 +seaboard arm armv7 seaboard nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h new file mode 100644 index 000..fd87560 --- /dev/null +++ b/include/configs/seaboard.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (SeaBoard) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Seaboard + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTD_BASE + +#define CONFIG_MACH_TYPE
Re: [U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support
Mike,
On Wed, Jan 26, 2011 at 1:13 AM, Mike Rapoport m...@compulab.co.il wrote:
On 01/26/11 00:24, Peter Tyser wrote:
As I've already pointed out (1) this covers only one possibility of
UART pin
muxing options. I agree that it makes sense when this is a part of the
board-specific code. However, forcing specific pins configuration in
the generic
driver seems problematic to me, even if most Tegra2 boards use the same
configuration.
As a side note, I'd prefer to have all the pin multiplexing defined in
one place
in board file rather than scattered among different drivers.
Alright. I'd like to get this wrapped up and accepted before the merge
window
closes so I can get on with the important bits (drivers, etc.). What
would you like
here? A generic function like 'pinmux_set_config(reg, val, bit)' that
lives in the board
files and gets called from the driver code with specifics of that
board's/drivers pinmux
config? Or do you see the pinmux code living entirely in the board
files, and being done
as part of board init? That's where it was before, BTW.
I think that the pinmux code should live entirely in the board file and
performed as part of board init. The drivers than can assume that the
pins are
configured properly.
OK. I'll move the clock/pinmux init code into armv7/tegra/board.c
(since it's SoC-centric),
and call it during board_init().
Actually, I think it makes more sense to move pinmux_init_uart and
clock_init_uart to board/nvidia/common/board.c.
These routines are more board-specific than SoC-specific - they depend
on how the UART is routed on a board.
Let me do that gen up a new patchset.
You previously mentioned that To date, all of our Tegra boards use
these pinmux options for both UARTs. If a board vendor chooses to use
different pinmuxes, then they can override these funcs in their board
files, or use their own code triggered by their own defines. But
according to our HW guys, the vast majority will use these pins
If the vast majority of boards really will use the same pinmuxing, it
would be nice to provide that common muxing as a default which can be
overridden. Perhaps moving pinmux_init_uart() and uart_clock_init()
into armv7/tegra/*, and making them weak functions would make everyone
happy.
My point was that pin muxing belongs to the board code rather than to the
driver. Driver should just assume that pins are configured elsewhere and it
does
not need to deal with pin muxing at all.
I understand that point - sorry if I wasn't clear. No objection to
having pinmux code in board files.
Moreover, I'd prefer to see pinmux_board_init or something similar that
configures all the pins at once rather than collection of pinmux_init_uart,
pinmux_init_sdmmc, pinmux_init_gmi etc that will grow as more drivers are
added.
I see a couple of reasons not to do it that way. First, I don't know
at this time what all the pinmux settings will be, since I haven't
ported all the periph driver code yet. It's vastly different from
what's acceptable in U-Boot, and will all need significant rewrite.
It'd take me a week to gather all that info, and I'm not at full BW on
this project (one of 4 on my plate right now).
Second, I've been chastised before for including code/features in this
initial patchset that aren't needed or used. I'm trying to keep the
code as simple as possible to make it easier on reviewers and get
through the review in as short a time as possible. This has already
dragged on far longer than I thought it would.
I'm willing to change the pinmux code to make it as generic as
possible, but only if there's a consensus on the list that it has to
be that way to get accepted pushed.
Or could you make default defines that board's could override as needed?
eg in pin_mux_uart():
#ifndef CONFIG_TEGRA2_PMT_CTLC_MASK
#define CONFIG_TEGRA2_PMC_CTLC_MASK 0xfff0
#endif
#ifndef CONFIG_TEGRA2_PMT_TRI_A_MASK
#define CONFIG_TEGRA2_PMC_TRI_A_MASK ~(Z_IRRX | Z_IRTX)
#endif
pin_mux_uart() {
reg = readl(pmt-pmt_ctl_c);
reg = CONFIG_TEGRA2_PMT_CTLC_MASK;
writel(reg, pmt-pmt_ctl_c);
reg = readl(pmt-pmt_tri_a);
reg = CONFIG_TEGRA2_PMC_TRI_A_MASK;
writel(reg, pmt-pmt_tri_a);
}
Or make the functions table driven so each board would define a
pinmux/clock configuration table?
I think its worthwhile to try and reduce duplicated code whenever
possible.
Best,
Peter
--
Sincerely yours,
Mike.
Thanks,
Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support
Mike,
On Tue, Jan 25, 2011 at 1:11 AM, Mike Rapoport m...@compulab.co.il wrote:
On 01/22/11 01:06, Tom Warren wrote:
Signed-off-by: Tom Warren twar...@nvidia.com
---
[ snip ]
+/*
+ * Routine: pin_mux_uart
+ * Description: setup the pin muxes/tristate values for a UART
+ */
+static void pin_mux_uart(void)
+{
+ pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 reg;
+
+#if CONFIG_TEGRA2_ENABLE_UARTA
+ reg = readl(pmt-pmt_ctl_c);
+ reg = 0xFFF0; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
+ writel(reg, pmt-pmt_ctl_c);
+
+ reg = readl(pmt-pmt_tri_a);
+ reg = ~Z_IRRX; /* Z_IRRX = normal (0) */
+ reg = ~Z_IRTX; /* Z_IRTX = normal (0) */
+ writel(reg, pmt-pmt_tri_a);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+ reg = readl(pmt-pmt_ctl_b);
+ reg = 0xFFF3; /* GMC_SEL [3:2] = 00, UARTD */
+ writel(reg, pmt-pmt_ctl_b);
+
+ reg = readl(pmt-pmt_tri_a);
+ reg = ~Z_GMC; /* Z_GMC = normal (0) */
+ writel(reg, pmt-pmt_tri_a);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
As I've already pointed out (1) this covers only one possibility of UART pin
muxing options. I agree that it makes sense when this is a part of the
board-specific code. However, forcing specific pins configuration in the
generic
driver seems problematic to me, even if most Tegra2 boards use the same
configuration.
As a side note, I'd prefer to have all the pin multiplexing defined in one
place
in board file rather than scattered among different drivers.
Alright. I'd like to get this wrapped up and accepted before the merge window
closes so I can get on with the important bits (drivers, etc.). What
would you like
here? A generic function like 'pinmux_set_config(reg, val, bit)' that
lives in the board
files and gets called from the driver code with specifics of that
board's/drivers pinmux
config? Or do you see the pinmux code living entirely in the board
files, and being done
as part of board init? That's where it was before, BTW.
If there are examples that you approve of in any extant U-Boot code (omap,
ti91, davinci, etc.), please point them out. I'd really like to
finalize this patch series.
(1) http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/92887/focus=93233
--
Sincerely yours,
Mike.
Thanks,
Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support
Mike,
On Tue, Jan 25, 2011 at 2:12 PM, Mike Rapoport m...@compulab.co.il wrote:
On 01/25/11 18:50, Tom Warren wrote:
Mike,
On Tue, Jan 25, 2011 at 1:11 AM, Mike Rapoport m...@compulab.co.il wrote:
On 01/22/11 01:06, Tom Warren wrote:
Signed-off-by: Tom Warren twar...@nvidia.com
---
[ snip ]
+/*
+ * Routine: pin_mux_uart
+ * Description: setup the pin muxes/tristate values for a UART
+ */
+static void pin_mux_uart(void)
+{
+ pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 reg;
+
+#if CONFIG_TEGRA2_ENABLE_UARTA
+ reg = readl(pmt-pmt_ctl_c);
+ reg = 0xFFF0; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA
*/
+ writel(reg, pmt-pmt_ctl_c);
+
+ reg = readl(pmt-pmt_tri_a);
+ reg = ~Z_IRRX; /* Z_IRRX = normal (0) */
+ reg = ~Z_IRTX; /* Z_IRTX = normal (0) */
+ writel(reg, pmt-pmt_tri_a);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+ reg = readl(pmt-pmt_ctl_b);
+ reg = 0xFFF3; /* GMC_SEL [3:2] = 00, UARTD */
+ writel(reg, pmt-pmt_ctl_b);
+
+ reg = readl(pmt-pmt_tri_a);
+ reg = ~Z_GMC; /* Z_GMC = normal (0) */
+ writel(reg, pmt-pmt_tri_a);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
As I've already pointed out (1) this covers only one possibility of UART pin
muxing options. I agree that it makes sense when this is a part of the
board-specific code. However, forcing specific pins configuration in the
generic
driver seems problematic to me, even if most Tegra2 boards use the same
configuration.
As a side note, I'd prefer to have all the pin multiplexing defined in one
place
in board file rather than scattered among different drivers.
Alright. I'd like to get this wrapped up and accepted before the merge window
closes so I can get on with the important bits (drivers, etc.). What
would you like
here? A generic function like 'pinmux_set_config(reg, val, bit)' that
lives in the board
files and gets called from the driver code with specifics of that
board's/drivers pinmux
config? Or do you see the pinmux code living entirely in the board
files, and being done
as part of board init? That's where it was before, BTW.
I think that the pinmux code should live entirely in the board file and
performed as part of board init. The drivers than can assume that the pins are
configured properly.
OK. I'll move the clock/pinmux init code into armv7/tegra/board.c
(since it's SoC-centric),
and call it during board_init().
If there are examples that you approve of in any extant U-Boot code (omap,
ti91, davinci, etc.), please point them out. I'd really like to
finalize this patch series.
I think OMAP is a good example. There's set_muxconf_regs function in each
board
file that is responsible for configuration of all the pins.
I'll take a look. Thanks.
(1) http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/92887/focus=93233
--
Sincerely yours,
Mike.
Thanks,
Tom
--
Sincerely yours,
Mike.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support
Mike et al,
On Tue, Jan 25, 2011 at 2:37 PM, Tom Warren twarren.nvi...@gmail.com wrote:
Mike,
On Tue, Jan 25, 2011 at 2:12 PM, Mike Rapoport m...@compulab.co.il wrote:
On 01/25/11 18:50, Tom Warren wrote:
Mike,
On Tue, Jan 25, 2011 at 1:11 AM, Mike Rapoport m...@compulab.co.il wrote:
On 01/22/11 01:06, Tom Warren wrote:
Signed-off-by: Tom Warren twar...@nvidia.com
---
[ snip ]
+/*
+ * Routine: pin_mux_uart
+ * Description: setup the pin muxes/tristate values for a UART
+ */
+static void pin_mux_uart(void)
+{
+ pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 reg;
+
+#if CONFIG_TEGRA2_ENABLE_UARTA
+ reg = readl(pmt-pmt_ctl_c);
+ reg = 0xFFF0; /* IRRX_/IRTX_SEL [19:16] = 00
UARTA */
+ writel(reg, pmt-pmt_ctl_c);
+
+ reg = readl(pmt-pmt_tri_a);
+ reg = ~Z_IRRX; /* Z_IRRX = normal (0) */
+ reg = ~Z_IRTX; /* Z_IRTX = normal (0) */
+ writel(reg, pmt-pmt_tri_a);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+ reg = readl(pmt-pmt_ctl_b);
+ reg = 0xFFF3; /* GMC_SEL [3:2] = 00, UARTD */
+ writel(reg, pmt-pmt_ctl_b);
+
+ reg = readl(pmt-pmt_tri_a);
+ reg = ~Z_GMC; /* Z_GMC = normal (0) */
+ writel(reg, pmt-pmt_tri_a);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
As I've already pointed out (1) this covers only one possibility of UART
pin
muxing options. I agree that it makes sense when this is a part of the
board-specific code. However, forcing specific pins configuration in the
generic
driver seems problematic to me, even if most Tegra2 boards use the same
configuration.
As a side note, I'd prefer to have all the pin multiplexing defined in one
place
in board file rather than scattered among different drivers.
Alright. I'd like to get this wrapped up and accepted before the merge
window
closes so I can get on with the important bits (drivers, etc.). What
would you like
here? A generic function like 'pinmux_set_config(reg, val, bit)' that
lives in the board
files and gets called from the driver code with specifics of that
board's/drivers pinmux
config? Or do you see the pinmux code living entirely in the board
files, and being done
as part of board init? That's where it was before, BTW.
I think that the pinmux code should live entirely in the board file and
performed as part of board init. The drivers than can assume that the pins
are
configured properly.
OK. I'll move the clock/pinmux init code into armv7/tegra/board.c
(since it's SoC-centric),
and call it during board_init().
Actually, I think it makes more sense to move pinmux_init_uart and
clock_init_uart to board/nvidia/common/board.c.
These routines are more board-specific than SoC-specific - they depend
on how the UART is routed on a board.
Let me do that gen up a new patchset.
If there are examples that you approve of in any extant U-Boot code (omap,
ti91, davinci, etc.), please point them out. I'd really like to
finalize this patch series.
I think OMAP is a good example. There's set_muxconf_regs function in each
board
file that is responsible for configuration of all the pins.
I'll take a look. Thanks.
(1)
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/92887/focus=93233
--
Sincerely yours,
Mike.
Thanks,
Tom
--
Sincerely yours,
Mike.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Mike,
On Mon, Jan 24, 2011 at 4:55 AM, Mike Rapoport m...@compulab.co.il wrote:
On 01/19/11 23:19, Tom Warren wrote:
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Coding style cleanup
- Move serial driver changes to separate patch
- Use board/nvidia/ instead of /board/tegra
- Remove TRUE/FALSE defines
- Use standard NS16550 register/bit defines in UART init
Changes for V3:
- Use I/O accessors for Tegra2 HW MMIO register access
- Allow conditional compile of UARTA/UARTD code to save space
arch/arm/cpu/armv7/tegra2/Makefile | 48 +
arch/arm/cpu/armv7/tegra2/board.c | 91 ++
arch/arm/cpu/armv7/tegra2/config.mk | 28 +++
arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 66 +++
arch/arm/cpu/armv7/tegra2/sys_info.c | 35
arch/arm/cpu/armv7/tegra2/timer.c | 122 +
arch/arm/include/asm/arch-tegra2/clk_rst.h | 155
arch/arm/include/asm/arch-tegra2/pinmux.h | 52 ++
arch/arm/include/asm/arch-tegra2/pmc.h | 125 +
arch/arm/include/asm/arch-tegra2/sys_proto.h | 33
arch/arm/include/asm/arch-tegra2/tegra2.h | 49 +
arch/arm/include/asm/arch-tegra2/uart.h | 45 +
board/nvidia/common/board.c | 249
++
board/nvidia/common/board.h | 57 ++
14 files changed, 1155 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile
create mode 100644 arch/arm/cpu/armv7/tegra2/board.c
create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk
create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S
create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c
create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c
create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h
create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h
create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h
create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h
create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h
create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h
create mode 100644 board/nvidia/common/board.c
create mode 100644 board/nvidia/common/board.h
[ snip ]
+ */
+
+#ifndef _CLK_RST_H_
+#define _CLK_RST_H_
+
+/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
+
+typedef volatile struct clk_rst_ctlr {
Is it necessary to use the structure to map the clocks and reset controller?
Wouldn't be better to port Linux implementation of Tegra2 clocks to U-Boot as
well?
Besides, since you're using I/O accessors anyway, the struct can replaces with
base address and offset definitions.
I asked Wolfgang to pre-review the original patch, and this is what he
said about original
base+offset register access code:
Wolfgang We do not allow this in U-Boot. Please turn all offset
tables into C structs, and
Wolfgang create a set of I/O accessor functions (or macros) as needed
to provide the needed
Wolfgang memory barriers on your architecture.
Using structs seems like a natural way to map HW MMIO regs, and is
done throughout U-Boot.
The structs are already written, contain just the members needed for
U-Boot (to a large degree),
and as Wolfgang has said in the past, U-Boot is not Linux, so I see no
reason to bring in the
Linux Tegra2 structs for any of these HW blocks. When I start posting
the drivers (SPI, USB,
etc.), then it might make sense to use (copy w/edits) the Linux data
structs, etc.
+ uint crc_rst_src; /* _RST_SOURCE_0, 0x00*/
+ uint crc_rst_dev_l; /* _RST_DEVICES_L_0, 0x04*/
+ uint crc_rst_dev_h; /* _RST_DEVICES_H_0, 0x08*/
+ uint crc_rst_dev_u; /* _RST_DEVICES_U_0, 0x0C*/
+ uint crc_clk_out_enb_l; /* _CLK_OUT_ENB_L_0, 0x10*/
+ uint crc_clk_out_enb_h; /* _CLK_OUT_ENB_H_0, 0x14*/
[ snip ]
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
+
+typedef volatile struct pinmux_tri_ctlr {
The same comment is valid also for the pin multiplexing registers...
+ uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
+ uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
+ uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
+
+#ifndef _PMC_H_
+#define _PMC_H_
+
+/* Power Management Controller (APBDEV_PMC_) registers */
+
+typedef volatile struct pmc_ctlr {
And for the PMC registers as well.
+ uint pmc_cntrl; /* _CNTRL_0, offset 00 */
+ uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
+ uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
+ uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
+ uint pmc_wake_lvl
Re: [U-Boot] [PATCH v3 3/4] arm: Tegra2: Add support for NVIDIA Harmony board
Mike, On Mon, Jan 24, 2011 at 4:58 AM, Mike Rapoport m...@compulab.co.il wrote: On 01/19/11 23:19, Tom Warren wrote: Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Use board/nvidia/ instead of /board/tegra - Change nv-common.h config file to tegra2-common.h MAINTAINERS | 4 + board/nvidia/harmony/Makefile | 50 boards.cfg | 1 + include/configs/harmony.h | 48 include/configs/tegra2-common.h | 160 +++ What about board/nvidia/harmony/harmony.c? There is no harmony.c file currently - that was whittled down in previous patch edits. It'll be brought back in future patches as features are added that are board-specific. 5 files changed, 263 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/harmony/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/tegra2-common.h diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..b5cff19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -841,6 +841,10 @@ Prafulla Wadaskar prafu...@marvell.com rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Tom Warren twar...@nvidia.com + + harmony Tegra2 (ARM7 A9 Dual Core) + Matthias Weisser weiss...@arcor.de jadecpu ARM926EJS (MB86R01 SoC) diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/harmony/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index 94b8745..ee7c4b7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -122,6 +122,7 @@ omap4_panda arm armv7 panda ti omap4_sdp4430 arm armv7 sdp4430 ti omap4 s5p_goni arm armv7 goni samsung s5pc1xx smdkc100 arm armv7 smdkc100 samsung s5pc1xx +harmony arm armv7 harmony nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/harmony.h b/include/configs/harmony.h new file mode 100644 index 000..7d8f27a --- /dev/null +++ b/include/configs/harmony.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef
Re: [U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support
Peter,
On Fri, Jan 21, 2011 at 4:46 PM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
On Fri, 2011-01-21 at 16:06 -0700, Tom Warren wrote:
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Move serial driver to separate patch
Changes for V5:
- Move arch/arm/cpu/armv7/uart.c board.h to drivers/serial and
rename to serial_tegra2.c
- Remove use of uart_num UART_A/D in serial_tegra2, simplify code
arch/arm/cpu/armv7/tegra2/Makefile | 2 +-
arch/arm/cpu/armv7/tegra2/board.c | 2 +-
arch/arm/cpu/armv7/tegra2/board.h | 58 --
arch/arm/cpu/armv7/tegra2/uart.c | 216
common/serial.c | 3 +-
drivers/serial/Makefile | 1 +
drivers/serial/serial_tegra2.c | 205 ++
drivers/serial/serial_tegra2.h | 49
include/serial.h | 3 +-
9 files changed, 261 insertions(+), 278 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/tegra2/board.h
delete mode 100644 arch/arm/cpu/armv7/tegra2/uart.c
create mode 100644 drivers/serial/serial_tegra2.c
create mode 100644 drivers/serial/serial_tegra2.h
It looks like arch/arm/cpu/armv7/tegra2/board.h and
arch/arm/cpu/armv7/tegra2/uart.c are added in the first patch, then
moved in this patch. It'd be ideal to just add them once in the proper
location.
On a side note, if you pass git format-patch the -M and -C options it
will make pretty diffs that only show what lines changed during a move.
In the case that you do move files in the future its nice to use those
options to ease review.
I'll use those options in the future (thanks!) to keep things cleaner.
Hopefully we can just go with this set of patches so I can get to the
other, more interesting code (drivers, A9 CPU init, etc.).
snip
+void uart_init(void)
+{
+ /* Init each UART - there may be more than 1 on a board/build */
+#if (CONFIG_TEGRA2_ENABLE_UARTA)
+ init_uart();
+#endif
+#if (CONFIG_TEGRA2_ENABLE_UARTD)
+ init_uart();
+#endif
+}
How about:
#if defined(CONFIG_TEGRA2_ENABLE_UARTA) || defined(CONFIG_TEGRA2_ENABLE_UARTD)
init_uart();
#endif
That won't work for a board like Harmony where the developer wants
both UARTs active, since uart_init is only called once.
Best,
Peter
Thanks,
Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support
Peter,
On Mon, Jan 24, 2011 at 10:51 AM, Peter Tyser pty...@xes-inc.com wrote:
snip
It looks like arch/arm/cpu/armv7/tegra2/board.h and
arch/arm/cpu/armv7/tegra2/uart.c are added in the first patch, then
moved in this patch. It'd be ideal to just add them once in the proper
location.
On a side note, if you pass git format-patch the -M and -C options it
will make pretty diffs that only show what lines changed during a move.
In the case that you do move files in the future its nice to use those
options to ease review.
I'll use those options in the future (thanks!) to keep things cleaner.
Hopefully we can just go with this set of patches so I can get to the
other, more interesting code (drivers, A9 CPU init, etc.).
Its up to the ARM maintainer and Wolfgang to decide if adding code in
one patch just to move it around in the 2nd is acceptable. I'm guess it
won't be acceptable since its considered bad form, and its unclear
what patch in this series contains what functionality. Eg this isn't
really meant to Add Tegra2 serial port support, it moves existing
serial port code around? And more? Its not really just adding serial
port support as the patch title states in any case.
I see what you're talking about now - I've got uart.c in 2 patch files - created
in 0001 and then moved in 0002. My bad - that wasn't the intent, just what
happened when I applied my V4 patches to a new branch to get the V5 patchset
built. I'll fix it and resubmit.
As to 0002 not adding serial port support for Tegra2, that's all it does - adds
TEGRA2 defines to serial.h/serial.c for the eserial* tables, and then adds
code to turn on Tegra2-specific UART HW. If I remove any mention of uart.c
in patch 0001 (add basic Tegra2 support), then does patch 0002 make
sense to you?
snip
+void uart_init(void)
+{
+ /* Init each UART - there may be more than 1 on a board/build */
+#if (CONFIG_TEGRA2_ENABLE_UARTA)
+ init_uart();
+#endif
+#if (CONFIG_TEGRA2_ENABLE_UARTD)
+ init_uart();
+#endif
+}
How about:
#if defined(CONFIG_TEGRA2_ENABLE_UARTA) ||
defined(CONFIG_TEGRA2_ENABLE_UARTD)
init_uart();
#endif
That won't work for a board like Harmony where the developer wants
both UARTs active, since uart_init is only called once.
Why should init_uart() be called two times? It looks to initialize both
ports, meaning it should only be called once, right?
Correct, again (need more coffee!) Your if defined construct wouldn't work
as written, though, because CONFIG_TEGRA2_ENABLE_UARTx is always
defined (as 0 or 1). I'd have to rework it.
Also, just noticed:
+static void init_uart(void)
+{
+#if CONFIG_TEGRA2_ENABLE_UARTA
+ uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTA_BASE;
+
+ uart_clock_init();
+
+ /* Enable UARTA - uses config 0 */
+ pin_mux_uart();
+
+ setup_uart(uart);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+ uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTD_BASE;
+
Have you compiled with both UARTA and UARTD enabled? Redeclaring 'uart'
in the middle of the function should throw an error or warning.
I'd tested with both enabled earlier, but maybe not since the rewrite.
I'll check resubmit.
+ uart_clock_init();
+
+ /* Enable UARTD - uses config 0 */
+ pin_mux_uart();
+
+ setup_uart(uart);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+}
Best,
Peter
Thanks, again, for your thoroughness!
Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Wolfgang ( Mike), On Mon, Jan 24, 2011 at 12:00 PM, Wolfgang Denk w...@denx.de wrote: Dear Tom Warren, In message AANLkTinoK+s5OivHAyLg10Z=gwzkccujwjdykssfg...@mail.gmail.com you wrote: ... +#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) +#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) +#define NV_PA_PMC_BASE 0x7000E400 what is the purpose of NV_PA prefix here? NV_Physical_Address - a base address of a HW block (Power Management Cntrlr, etc.) Well, the NV_ part is not needed, right? True. I can remove it, but why? It designates this as a NVIDIA-specific define. I see the same thing in AT91, OMAP, NetARM, DaVinci, IMX files, etc. etc. Best regards, Wolfgang Denk Thanks, Tom -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Writing a book is like washing an elephant: there's no good place to begin or end, and it's hard to keep track of what you've already covered. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support
Peter,
On Mon, Jan 24, 2011 at 12:14 PM, Peter Tyser pty...@xes-inc.com wrote:
snip
I see what you're talking about now - I've got uart.c in 2 patch files -
created
in 0001 and then moved in 0002. My bad - that wasn't the intent, just what
happened when I applied my V4 patches to a new branch to get the V5 patchset
built. I'll fix it and resubmit.
As to 0002 not adding serial port support for Tegra2, that's all it does -
adds
TEGRA2 defines to serial.h/serial.c for the eserial* tables, and then adds
code to turn on Tegra2-specific UART HW. If I remove any mention of uart.c
in patch 0001 (add basic Tegra2 support), then does patch 0002 make
sense to you?
Yeah, that'd make more sense. Patch 2 would just contain:
common/serial.c | 3 +-
drivers/serial/Makefile | 1 +
drivers/serial/serial_tegra2.c | 205 ++
drivers/serial/serial_tegra2.h | 49
include/serial.h | 3 +-
Exactly what I was thinking. I'll try to get it right in patch V6.
snip
+void uart_init(void)
+{
+ /* Init each UART - there may be more than 1 on a board/build */
+#if (CONFIG_TEGRA2_ENABLE_UARTA)
+ init_uart();
+#endif
+#if (CONFIG_TEGRA2_ENABLE_UARTD)
+ init_uart();
+#endif
+}
How about:
#if defined(CONFIG_TEGRA2_ENABLE_UARTA) ||
defined(CONFIG_TEGRA2_ENABLE_UARTD)
init_uart();
#endif
That won't work for a board like Harmony where the developer wants
both UARTs active, since uart_init is only called once.
Why should init_uart() be called two times? It looks to initialize both
ports, meaning it should only be called once, right?
Correct, again (need more coffee!) Your if defined construct wouldn't work
as written, though, because CONFIG_TEGRA2_ENABLE_UARTx is always
defined (as 0 or 1). I'd have to rework it.
You could also just get rid of uart_init() altogether and rename
init_uart() to uart_init(). That would get rid of some idefs and
simplify the flow.
Yeah, I saw that as I was cleaning up the indentation reworking the
code to compile
with both UARTs defined. I'll get rid of uart_init (renamed to
init_uart). Thanks.
Best,
Peter
Thanks,
Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Minkyu, On Fri, Jan 21, 2011 at 1:16 AM, Minkyu Kang proms...@gmail.com wrote: Dear Tom Warren, On 21 January 2011 09:42, Tom Warren twarren.nvi...@gmail.com wrote: diff --git a/arch/arm/cpu/armv7/tegra2/uart.c b/arch/arm/cpu/armv7/tegra2/uart.c new file mode 100644 index 000..5e60bd8 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/uart.c How about move it to drivers/serial/ ? There's Tegra-specific code in there (clocks, PLLs and pinmuxes). And why don't you use serial multi interface? CONFIG_SERIAL_MULTI is enabled in the config files. Thanks Minkyu Kang Thank you, Tom -- from. prom. www.promsoft.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
seedshope, (?)
On Fri, Jan 21, 2011 at 9:35 AM, seedshope bocui...@gmail.com wrote:
On 01/21/2011 08:42 AM, Tom Warren wrote:
+
+enum {
+ UART_A = 1,
+ UART_B,
+ UART_C,
+ UART_D,
+ UART_E
+};
+
+#endif /* _BOARD_H_ */
snip
+
+#if CONFIG_TEGRA2_ENABLE_UARTA
+ if (uart_num == UART_A) {
Why you need get the parameters uart_num, I think if you want to use
CONFIG_TEGRA2_ENABLE_UARTA,
You only defined CONFIG_TEGRA2_ENABLE_UARTA in include/configs/seaboard.h
or include/configs/tegra2-common.h.
OK, makes sense. I'll move uart.c/board.h to drivers/serial as
serial_tegra2.[ch] and remove
all mention of UART_[A-E] and uart_num. Thanks.
Here, The code formats may be as following:
#ifdef CONFIG_SERIAL1
..
#elif defined(CONFIG_SERIAL2)
..
#else
..
#endif
Some configs / builds can have both UARTs active, so each
#ifdef/#endif pair is needed.
Thanks
seedshope
Thanks for the feedback
Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Move serial driver to separate patch
Changes for V5:
- Move arch/arm/cpu/armv7/uart.c board.h to drivers/serial and
rename to serial_tegra2.c
- Remove use of uart_num UART_A/D in serial_tegra2, simplify code
arch/arm/cpu/armv7/tegra2/Makefile |2 +-
arch/arm/cpu/armv7/tegra2/board.c |2 +-
arch/arm/cpu/armv7/tegra2/board.h | 58 --
arch/arm/cpu/armv7/tegra2/uart.c | 216
common/serial.c|3 +-
drivers/serial/Makefile|1 +
drivers/serial/serial_tegra2.c | 205 ++
drivers/serial/serial_tegra2.h | 49
include/serial.h |3 +-
9 files changed, 261 insertions(+), 278 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/tegra2/board.h
delete mode 100644 arch/arm/cpu/armv7/tegra2/uart.c
create mode 100644 drivers/serial/serial_tegra2.c
create mode 100644 drivers/serial/serial_tegra2.h
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile
b/arch/arm/cpu/armv7/tegra2/Makefile
index f5b657b..687c887 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS := board.o sys_info.o timer.o uart.o
+COBJS := board.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/board.c
b/arch/arm/cpu/armv7/tegra2/board.c
index 816a8cd..1e92d98 100644
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -25,7 +25,7 @@
#include asm/io.h
#include asm/arch/sys_proto.h
#include asm/arch/tegra2.h
-#include board.h
+#include asm/arch/pmc.h
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/cpu/armv7/tegra2/board.h
b/arch/arm/cpu/armv7/tegra2/board.h
deleted file mode 100644
index f8f09c0..000
--- a/arch/arm/cpu/armv7/tegra2/board.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation www.nvidia.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-#include asm/arch/clk_rst.h
-#include asm/arch/pinmux.h
-#include asm/arch/pmc.h
-#include asm/arch/uart.h
-
-#define NVRM_PLLP_FIXED_FREQ_KHZ 216000
-#define NV_DEFAULT_DEBUG_BAUD 115200
-
-#define PLL_BYPASS (1 31)
-#define PLL_ENABLE (1 30)
-#define PLL_BASE_OVRRIDE (1 28)
-#define PLL_DIVP (1 20) /* post divider, b22:20 */
-#define PLL_DIVM 0x0C/* input divider, b4:0 */
-
-#define SWR_UARTD_RST (1 2)
-#define CLK_ENB_UARTD (1 2)
-#define SWR_UARTA_RST (1 6)
-#define CLK_ENB_UARTA (1 6)
-
-#define Z_GMC (1 29)
-#define Z_IRRX (1 20)
-#define Z_IRTX (1 19)
-
-enum {
- UART_A = 1,
- UART_B,
- UART_C,
- UART_D,
- UART_E
-};
-
-#endif /* _BOARD_H_ */
diff --git a/arch/arm/cpu/armv7/tegra2/uart.c b/arch/arm/cpu/armv7/tegra2/uart.c
deleted file mode 100644
index 5e60bd8..000
--- a/arch/arm/cpu/armv7/tegra2/uart.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation www.nvidia.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA
[U-Boot] [PATCH V5 0/4] Add basic NVIDIA Tegra2 SoC support
This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. Changes for V2: - Coding style cleanup - Remove mach-types.h change; wait for ARM kernel sync-up - Move serial driver changes to separate patch - Use board/nvidia/ instead of /board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 register/bit defines in UART init - Change nv-common.h config file to tegra2-common.h Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Changes for V4: - Use address of HW structs (pmc, etc.) in readl/writel - Remove empty lines, fix mixed case hex #s comments in header(s) - Move board/nvidia/common/board.c UART code header to arch/arm/cpu/armv7/tegra2/ - Declare internal functions as static in UART code Changes for V5: - Move arch/arm/cpu/armv7/uart.c board.h to drivers/serial and rename to serial_tegra2.c - Remove use of uart_num UART_A/D in serial_tegra2, simplify code Tom Warren (4): arm: Tegra2: Add basic NVIDIA Tegra2 SoC support serial: Add Tegra2 serial port support arm: Tegra2: Add support for NVIDIA Harmony board arm: Tegra2: Add support for NVIDIA Seaboard board MAINTAINERS |5 + arch/arm/cpu/armv7/tegra2/Makefile | 48 ++ arch/arm/cpu/armv7/tegra2/board.c| 91 arch/arm/cpu/armv7/tegra2/config.mk | 28 arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 65 arch/arm/cpu/armv7/tegra2/sys_info.c | 35 + arch/arm/cpu/armv7/tegra2/timer.c| 122 +++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 154 +++ arch/arm/include/asm/arch-tegra2/pinmux.h| 51 +++ arch/arm/include/asm/arch-tegra2/pmc.h | 124 arch/arm/include/asm/arch-tegra2/sys_proto.h | 33 arch/arm/include/asm/arch-tegra2/tegra2.h| 49 ++ arch/arm/include/asm/arch-tegra2/uart.h | 44 ++ board/nvidia/common/board.c | 57 +++ board/nvidia/harmony/Makefile| 50 +++ board/nvidia/seaboard/Makefile | 50 +++ boards.cfg |2 + common/serial.c |3 +- drivers/serial/Makefile |1 + drivers/serial/serial_tegra2.c | 205 ++ drivers/serial/serial_tegra2.h | 49 ++ include/configs/harmony.h| 48 ++ include/configs/seaboard.h | 44 ++ include/configs/tegra2-common.h | 160 include/serial.h |3 +- 25 files changed, 1519 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c create mode 100644 board/nvidia/harmony/Makefile create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 drivers/serial/serial_tegra2.c create mode 100644 drivers/serial/serial_tegra2.h create mode 100644 include/configs/harmony.h create mode 100644 include/configs/seaboard.h create mode 100644 include/configs/tegra2-common.h -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V5 4/4] arm: Tegra2: Add support for NVIDIA Seaboard board
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Remove mach-types.h change; wait for ARM kernel sync-up - Use board/nvidia instead of board/tegra MAINTAINERS|1 + board/nvidia/seaboard/Makefile | 50 boards.cfg |1 + include/configs/seaboard.h | 44 +++ 4 files changed, 96 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 include/configs/seaboard.h diff --git a/MAINTAINERS b/MAINTAINERS index b5cff19..f4795d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -844,6 +844,7 @@ Prafulla Wadaskar prafu...@marvell.com Tom Warren twar...@nvidia.com harmony Tegra2 (ARM7 A9 Dual Core) + seaboardTegra2 (ARM7 A9 Dual Core) Matthias Weisser weiss...@arcor.de diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/seaboard/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index ee7c4b7..3c4c249 100644 --- a/boards.cfg +++ b/boards.cfg @@ -123,6 +123,7 @@ omap4_sdp4430arm armv7 sdp4430 ti s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx harmony arm armv7 harmony nvidia tegra2 +seaboard arm armv7 seaboard nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h new file mode 100644 index 000..98d82d6 --- /dev/null +++ b/include/configs/seaboard.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (SeaBoard) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Seaboard + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTA 0 +#define CONFIG_TEGRA2_ENABLE_UARTD 1 +#define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTD_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD +#define CONFIG_SYS_BOARD_ODMDATA
[U-Boot] [PATCH V5 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Coding style cleanup - Move serial driver changes to separate patch - Use board/nvidia instead of board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 registers/bit defines in UART init Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Changes for V4: - Use address of HW structs (pmc, etc.) in readl/writel - Remove empty lines, fix mixed case hex #s comments in header(s) - Move board/nvidia/common/board.c UART code header to arch/arm/cpu/armv7/tegra2/ - Declare internal functions as static in UART code arch/arm/cpu/armv7/tegra2/Makefile | 48 ++ arch/arm/cpu/armv7/tegra2/board.c| 91 +++ arch/arm/cpu/armv7/tegra2/board.h| 58 +++ arch/arm/cpu/armv7/tegra2/config.mk | 28 arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 65 arch/arm/cpu/armv7/tegra2/sys_info.c | 35 arch/arm/cpu/armv7/tegra2/timer.c| 122 +++ arch/arm/cpu/armv7/tegra2/uart.c | 216 ++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 154 ++ arch/arm/include/asm/arch-tegra2/pinmux.h| 51 ++ arch/arm/include/asm/arch-tegra2/pmc.h | 124 +++ arch/arm/include/asm/arch-tegra2/sys_proto.h | 33 arch/arm/include/asm/arch-tegra2/tegra2.h| 49 ++ arch/arm/include/asm/arch-tegra2/uart.h | 44 ++ board/nvidia/common/board.c | 57 +++ 15 files changed, 1175 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/board.h create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/cpu/armv7/tegra2/uart.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile new file mode 100644 index 000..f5b657b --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010,2011 Nvidia Corporation. +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS := board.o sys_info.o timer.o uart.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all:$(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c new file mode 100644 index 000..816a8cd --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version
[U-Boot] [PATCH V5 3/4] arm: Tegra2: Add support for NVIDIA Harmony board
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Use board/nvidia/ instead of /board/tegra - Change nv-common.h config file to tegra2-common.h MAINTAINERS |4 + board/nvidia/harmony/Makefile | 50 boards.cfg |1 + include/configs/harmony.h | 48 include/configs/tegra2-common.h | 160 +++ 5 files changed, 263 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/harmony/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/tegra2-common.h diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..b5cff19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -841,6 +841,10 @@ Prafulla Wadaskar prafu...@marvell.com rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Tom Warren twar...@nvidia.com + + harmony Tegra2 (ARM7 A9 Dual Core) + Matthias Weisser weiss...@arcor.de jadecpu ARM926EJS (MB86R01 SoC) diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/harmony/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index 94b8745..ee7c4b7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -122,6 +122,7 @@ omap4_panda arm armv7 panda ti omap4_sdp4430arm armv7 sdp4430 ti omap4 s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx +harmony arm armv7 harmony nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/harmony.h b/include/configs/harmony.h new file mode 100644 index 000..7d8f27a --- /dev/null +++ b/include/configs/harmony.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (Harmony) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Harmony + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTD 1 +#define CONFIG_TEGRA2_ENABLE_UARTA 0
Re: [U-Boot] [PATCH v3 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
On Wed, Jan 19, 2011 at 5:04 PM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
Some last minutes nits:
It looks like some of the new functions can be declared statically.
It'd be nice to do so where possible.
Which functions, Peter? Please point them out specifically, thanks.
snip
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
@@ -0,0 +1,66 @@
+/*
+ * Board specific setup info
This is CPU-specific code, correct?
Yes - I'll change the comment.
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include config.h
+#include version.h
+
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file
+
+.global invalidate_dcache
+invalidate_dcache:
+ mov pc, lr
+
+
+ .align 5
+.global reset_cpu
+reset_cpu:
+ ldr r1, rstctl @ get addr for global reset
+ @ reg
+ ldr r3, [r1]
+ orr r3, r3, #0x10
+ str r3, [r1] @ force reset
+ mov r0, r0
+_loop_forever:
+ b _loop_forever
+rstctl:
+ .word PRM_RSTCTRL
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp]
+ mov ip, lr
+ bl s_init @ go setup pll, mux memory
+ ldr ip, [sp]
+ mov lr, ip
+
+ mov pc, lr @ back to arch calling code
+
+ @ the literal pools origin
+ .ltorg
+
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
diff --git a/arch/arm/cpu/armv7/tegra2/sys_info.c
b/arch/arm/cpu/armv7/tegra2/sys_info.c
new file mode 100644
index 000..6d11dc1
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/sys_info.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/* Print CPU information */
+int print_cpuinfo(void)
+{
+ puts(TEGRA2\n);
+
+ /* TBD: Add printf of major/minor rev info, stepping, etc. */
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/armv7/tegra2/timer.c
b/arch/arm/cpu/armv7/tegra2/timer.c
new file mode 100644
index 000..858af0f
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/timer.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff r-woodru...@ti.com
+ * Syed Moahmmed Khasim kha...@ti.com
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Marius Groeger mgroe...@sysgo.de
+ * Alex Zuepke a...@sysgo.de
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, ga...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or
Re: [U-Boot] [PATCH v3 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Graeme,
On Wed, Jan 19, 2011 at 5:20 PM, Graeme Russ graeme.r...@gmail.com wrote:
On Thu, Jan 20, 2011 at 8:19 AM, Tom Warren twarren.nvi...@gmail.com wrote:
+
+/*
+ * Routine: uart_clock_init
+ * Description: init the PLL and clock for the UART in uart_num
+ */
+void uart_clock_init(int uart_num)
+{
+ clk_rst_ctlr *const clkrst = (clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ static int pllp_init_done;
+ u32 reg;
+
+ if (!pllp_init_done) {
+
+ /* Override pllp setup for 216MHz operation. */
+ reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
+ reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) 8) | PLL_DIVM);
+ writel(reg, clkrst-crc_pllp_base);
+
+ reg |= PLL_ENABLE;
+ writel(reg, clkrst-crc_pllp_base);
Is this correct? Should it not be writel(reg, clkrst-crc_pllp_base);
Well, the PLLs, UART and device clocks that I'm writing all seem to work OK.
I'll take a look at the ARM asm code generated, but you are probably right.
But shouldn't the compiler have complained if I wasn't passing the
struct address?
Similarly for other readl()'s and writel()'s
Regards,
Graeme
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Wolfgang, On Thu, Jan 20, 2011 at 1:40 AM, Wolfgang Denk w...@denx.de wrote: Dear Tom Warren, In message 1295471986-2395-2-git-send-email-twar...@nvidia.com you wrote: Signed-off-by: Tom Warren twar...@nvidia.com checkpatch.pl reports: total: 6 errors, 12 warnings, 1155 lines checked /tmp/patch has style problems, please review. Please clean up. I run checkpatch.pl (v 0.31) on every patch before I submit it, and I did see 12 warnings but no errors. The warnings were minor - new typedefs and volatile structs. Could you please provide the text of the checkpatch.pl output so I can see what the errors might be? Thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Where shall I begin, please your Majesty? he asked. Begin at the beginning, the King said, gravely, and go on till you come to the end: then stop. - Alice's Adventures in Wonderland, Lewis Carroll ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V4 2/4] serial: Add Tegra2 serial port support
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Move serial driver to separate patch common/serial.c |3 ++- include/serial.h |3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/common/serial.c b/common/serial.c index 051ae4e..8ebf9a5 100644 --- a/common/serial.c +++ b/common/serial.c @@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void) #elif defined(CONFIG_4xx) \ || defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \ || defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \ - || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) + || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) \ + || defined(CONFIG_TEGRA2) #if defined(CONFIG_CONS_INDEX) defined(CONFIG_SYS_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return eserial1_device; diff --git a/include/serial.h b/include/serial.h index 15ab73c..f21d961 100644 --- a/include/serial.h +++ b/include/serial.h @@ -27,7 +27,8 @@ extern struct serial_device * default_serial_console (void); defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ -defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) +defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ +defined(CONFIG_TEGRA2) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V4 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Coding style cleanup - Move serial driver changes to separate patch - Use board/nvidia instead of board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 registers/bit defines in UART init Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Changes for V4: - Use address of HW structs (pmc, etc.) in readl/writel - Remove empty lines, fix mixed case hex #s comments in header(s) - Move board/nvidia/common/board.c UART code header to arch/arm/cpu/armv7/tegra2/ - Declare internal functions as static in UART code arch/arm/cpu/armv7/tegra2/Makefile | 48 ++ arch/arm/cpu/armv7/tegra2/board.c| 91 +++ arch/arm/cpu/armv7/tegra2/board.h| 58 +++ arch/arm/cpu/armv7/tegra2/config.mk | 28 arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 65 arch/arm/cpu/armv7/tegra2/sys_info.c | 35 arch/arm/cpu/armv7/tegra2/timer.c| 122 +++ arch/arm/cpu/armv7/tegra2/uart.c | 216 ++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 154 ++ arch/arm/include/asm/arch-tegra2/pinmux.h| 51 ++ arch/arm/include/asm/arch-tegra2/pmc.h | 124 +++ arch/arm/include/asm/arch-tegra2/sys_proto.h | 33 arch/arm/include/asm/arch-tegra2/tegra2.h| 49 ++ arch/arm/include/asm/arch-tegra2/uart.h | 44 ++ board/nvidia/common/board.c | 57 +++ 15 files changed, 1175 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/board.h create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/cpu/armv7/tegra2/uart.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile new file mode 100644 index 000..f5b657b --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010,2011 Nvidia Corporation. +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS := board.o sys_info.o timer.o uart.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all:$(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c new file mode 100644 index 000..816a8cd --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version
[U-Boot] [PATCH V4 3/4] arm: Tegra2: Add support for NVIDIA Harmony board
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Use board/nvidia/ instead of /board/tegra - Change nv-common.h config file to tegra2-common.h MAINTAINERS |4 + board/nvidia/harmony/Makefile | 50 boards.cfg |1 + include/configs/harmony.h | 48 include/configs/tegra2-common.h | 160 +++ 5 files changed, 263 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/harmony/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/tegra2-common.h diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..b5cff19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -841,6 +841,10 @@ Prafulla Wadaskar prafu...@marvell.com rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Tom Warren twar...@nvidia.com + + harmony Tegra2 (ARM7 A9 Dual Core) + Matthias Weisser weiss...@arcor.de jadecpu ARM926EJS (MB86R01 SoC) diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/harmony/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index 94b8745..ee7c4b7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -122,6 +122,7 @@ omap4_panda arm armv7 panda ti omap4_sdp4430arm armv7 sdp4430 ti omap4 s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx +harmony arm armv7 harmony nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/harmony.h b/include/configs/harmony.h new file mode 100644 index 000..7d8f27a --- /dev/null +++ b/include/configs/harmony.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (Harmony) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Harmony + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTD 1 +#define CONFIG_TEGRA2_ENABLE_UARTA 0
[U-Boot] [PATCH V4 4/4] arm: Tegra2: Add support for NVIDIA Seaboard board
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Remove mach-types.h change; wait for ARM kernel sync-up - Use board/nvidia instead of board/tegra MAINTAINERS|1 + board/nvidia/seaboard/Makefile | 50 boards.cfg |1 + include/configs/seaboard.h | 44 +++ 4 files changed, 96 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 include/configs/seaboard.h diff --git a/MAINTAINERS b/MAINTAINERS index b5cff19..f4795d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -844,6 +844,7 @@ Prafulla Wadaskar prafu...@marvell.com Tom Warren twar...@nvidia.com harmony Tegra2 (ARM7 A9 Dual Core) + seaboardTegra2 (ARM7 A9 Dual Core) Matthias Weisser weiss...@arcor.de diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/seaboard/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index ee7c4b7..3c4c249 100644 --- a/boards.cfg +++ b/boards.cfg @@ -123,6 +123,7 @@ omap4_sdp4430arm armv7 sdp4430 ti s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx harmony arm armv7 harmony nvidia tegra2 +seaboard arm armv7 seaboard nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h new file mode 100644 index 000..98d82d6 --- /dev/null +++ b/include/configs/seaboard.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (SeaBoard) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Seaboard + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTA 0 +#define CONFIG_TEGRA2_ENABLE_UARTD 1 +#define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTD_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD +#define CONFIG_SYS_BOARD_ODMDATA
[U-Boot] [PATCH V4 0/4] Add basic NVIDIA Tegra2 SoC support
This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. Changes for V2: - Coding style cleanup - Remove mach-types.h change; wait for ARM kernel sync-up - Move serial driver changes to separate patch - Use board/nvidia/ instead of /board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 register/bit defines in UART init - Change nv-common.h config file to tegra2-common.h Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Changes for V4: - Use address of HW structs (pmc, etc.) in readl/writel - Remove empty lines, fix mixed case hex #s comments in header(s) - Move board/nvidia/common/board.c UART code header to arch/arm/cpu/armv7/tegra2/ - Declare internal functions as static in UART code Tom Warren (4): arm: Tegra2: Add basic NVIDIA Tegra2 SoC support serial: Add Tegra2 serial port support arm: Tegra2: Add support for NVIDIA Harmony board arm: Tegra2: Add support for NVIDIA Seaboard board MAINTAINERS |5 + arch/arm/cpu/armv7/tegra2/Makefile | 48 ++ arch/arm/cpu/armv7/tegra2/board.c| 91 +++ arch/arm/cpu/armv7/tegra2/board.h| 58 +++ arch/arm/cpu/armv7/tegra2/config.mk | 28 arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 65 arch/arm/cpu/armv7/tegra2/sys_info.c | 35 arch/arm/cpu/armv7/tegra2/timer.c| 122 +++ arch/arm/cpu/armv7/tegra2/uart.c | 216 ++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 154 ++ arch/arm/include/asm/arch-tegra2/pinmux.h| 51 ++ arch/arm/include/asm/arch-tegra2/pmc.h | 124 +++ arch/arm/include/asm/arch-tegra2/sys_proto.h | 33 arch/arm/include/asm/arch-tegra2/tegra2.h| 49 ++ arch/arm/include/asm/arch-tegra2/uart.h | 44 ++ board/nvidia/common/board.c | 57 +++ board/nvidia/harmony/Makefile| 50 ++ board/nvidia/seaboard/Makefile | 50 ++ boards.cfg |2 + common/serial.c |3 +- include/configs/harmony.h| 48 ++ include/configs/seaboard.h | 44 ++ include/configs/tegra2-common.h | 160 +++ include/serial.h |3 +- 24 files changed, 1538 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/board.h create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/cpu/armv7/tegra2/uart.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c create mode 100644 board/nvidia/harmony/Makefile create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/seaboard.h create mode 100644 include/configs/tegra2-common.h -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4 V2] Add basic NVIDIA Tegra2 SoC support
Wolfgang, On Mon, Jan 17, 2011 at 4:27 PM, Wolfgang Denk w...@denx.de wrote: Dear Tom Warren, In message AANLkTi=f-14jnam_dy5c1sgtt0nmqm-pnok6gdg4d...@mail.gmail.com you wrote: 1) IO access functions - I pre-reviewed my patch series with Wolfgang (to hopefully catch any blatant errors and smooth the process) and he indicated that C structs and I/O accessor funcs or macros were preferred to my base+offset original code. I don't think I said preferred. I apologize if I really should have been unclear. Fact is, the use of I/O accessors is mandatory for any new code going in. Sorry, I misunderstood what really constituted I/O accessors. Fixed in V3 (coming soon). Since the ARM is 32-bit, and all of our registers are I/O mapped, it made sense just to cast the necessary HW mem-mapped regs as volatile structs and access the members directly. Works well, is easy to read understand, etc. Let me know (with examples, if possible) how I can make it better. It does NOT make sense. Please read the linux/Documentation/volatile-considered-harmful.txt document, and see recent dicussion in the ARM: Avoid compiler optimization for usages of readb, writeb and friends. thread about what happens when you use just volatile pointers. 2) Compiling out support for UARTA or UARTD - didn't seem necessary - size isn't an issue at this point with Tegra2 U-Boot, Maybe you don't care, but we do. Please see http://www.denx.de/wiki/U-Boot/DesignPrinciples, item 5 Done in V3 patch. I was going to respond to your review w/a direct, inline reply, but I thought it better to get the V2 patch out there before the weekend (we're off for MLK, as well). I'm under some pressure to get a baseline Tegra2 patchset in before the merge window closes. I'll be sure to respond to each issue directly on the list in the future, though. Please also make sure to maintain a changelog of in each of your patches (see second bullet in http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions). OK. I added a V2/V3 changelog to each patch. Hope I got it right. New patchset incoming. Best regards, Wolfgang Denk Thanks for your patience, Tom -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de IMPORTANT NOTICE TO PURCHASERS: The Entire Physical Universe, Inclu- ding This Product, May One Day Collapse Back into an Infinitesimally Small Space. Should Another Universe Subsequently Re-emerge, the Existence of This Product in That Universe Cannot Be Guaranteed. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 0/4] Add basic NVIDIA Tegra2 SoC support
This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. Changes for V2: - Coding style cleanup - Remove mach-types.h change; wait for ARM kernel sync-up - Move serial driver changes to separate patch - Use board/nvidia/ instead of /board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 register/bit defines in UART init - Change nv-common.h config file to tegra2-common.h Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Tom Warren (4): arm: Tegra2: Add basic NVIDIA Tegra2 SoC support serial: Add Tegra2 serial port support arm: Tegra2: Add support for NVIDIA Harmony board arm: Tegra2: Add support for NVIDIA Seaboard board MAINTAINERS |5 + arch/arm/cpu/armv7/tegra2/Makefile | 48 + arch/arm/cpu/armv7/tegra2/board.c| 91 ++ arch/arm/cpu/armv7/tegra2/config.mk | 28 +++ arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 66 +++ arch/arm/cpu/armv7/tegra2/sys_info.c | 35 arch/arm/cpu/armv7/tegra2/timer.c| 122 + arch/arm/include/asm/arch-tegra2/clk_rst.h | 155 arch/arm/include/asm/arch-tegra2/pinmux.h| 52 ++ arch/arm/include/asm/arch-tegra2/pmc.h | 125 + arch/arm/include/asm/arch-tegra2/sys_proto.h | 33 arch/arm/include/asm/arch-tegra2/tegra2.h| 49 + arch/arm/include/asm/arch-tegra2/uart.h | 45 + board/nvidia/common/board.c | 249 ++ board/nvidia/common/board.h | 57 ++ board/nvidia/harmony/Makefile| 50 + board/nvidia/seaboard/Makefile | 50 + boards.cfg |2 + common/serial.c |3 +- include/configs/harmony.h| 48 + include/configs/seaboard.h | 44 + include/configs/tegra2-common.h | 160 + include/serial.h |3 +- 23 files changed, 1518 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c create mode 100644 board/nvidia/common/board.h create mode 100644 board/nvidia/harmony/Makefile create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/seaboard.h create mode 100644 include/configs/tegra2-common.h -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/4] serial: Add Tegra2 serial port support
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Move serial driver changes to separate patch common/serial.c |3 ++- include/serial.h |3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/common/serial.c b/common/serial.c index 051ae4e..8ebf9a5 100644 --- a/common/serial.c +++ b/common/serial.c @@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void) #elif defined(CONFIG_4xx) \ || defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \ || defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \ - || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) + || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) \ + || defined(CONFIG_TEGRA2) #if defined(CONFIG_CONS_INDEX) defined(CONFIG_SYS_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return eserial1_device; diff --git a/include/serial.h b/include/serial.h index 15ab73c..f21d961 100644 --- a/include/serial.h +++ b/include/serial.h @@ -27,7 +27,8 @@ extern struct serial_device * default_serial_console (void); defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ -defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) +defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ +defined(CONFIG_TEGRA2) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Coding style cleanup - Move serial driver changes to separate patch - Use board/nvidia/ instead of /board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 register/bit defines in UART init Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space arch/arm/cpu/armv7/tegra2/Makefile | 48 + arch/arm/cpu/armv7/tegra2/board.c| 91 ++ arch/arm/cpu/armv7/tegra2/config.mk | 28 +++ arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 66 +++ arch/arm/cpu/armv7/tegra2/sys_info.c | 35 arch/arm/cpu/armv7/tegra2/timer.c| 122 + arch/arm/include/asm/arch-tegra2/clk_rst.h | 155 arch/arm/include/asm/arch-tegra2/pinmux.h| 52 ++ arch/arm/include/asm/arch-tegra2/pmc.h | 125 + arch/arm/include/asm/arch-tegra2/sys_proto.h | 33 arch/arm/include/asm/arch-tegra2/tegra2.h| 49 + arch/arm/include/asm/arch-tegra2/uart.h | 45 + board/nvidia/common/board.c | 249 ++ board/nvidia/common/board.h | 57 ++ 14 files changed, 1155 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c create mode 100644 board/nvidia/common/board.h diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile new file mode 100644 index 000..75fba0b --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010,2011 Nvidia Corporation. +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS := sys_info.o board.o timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all:$(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c new file mode 100644 index 000..1e92d98 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include
[U-Boot] [PATCH v3 4/4] arm: Tegra2: Add support for NVIDIA Seaboard board
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Remove mach-types.h change; wait for ARM kernel sync-up - Use board/nvidia/ instead of /board/tegra MAINTAINERS|1 + board/nvidia/seaboard/Makefile | 50 boards.cfg |1 + include/configs/seaboard.h | 44 +++ 4 files changed, 96 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 include/configs/seaboard.h diff --git a/MAINTAINERS b/MAINTAINERS index b5cff19..f4795d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -844,6 +844,7 @@ Prafulla Wadaskar prafu...@marvell.com Tom Warren twar...@nvidia.com harmony Tegra2 (ARM7 A9 Dual Core) + seaboardTegra2 (ARM7 A9 Dual Core) Matthias Weisser weiss...@arcor.de diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/seaboard/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index ee7c4b7..3c4c249 100644 --- a/boards.cfg +++ b/boards.cfg @@ -123,6 +123,7 @@ omap4_sdp4430arm armv7 sdp4430 ti s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx harmony arm armv7 harmony nvidia tegra2 +seaboard arm armv7 seaboard nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h new file mode 100644 index 000..98d82d6 --- /dev/null +++ b/include/configs/seaboard.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (SeaBoard) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Seaboard + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTA 0 +#define CONFIG_TEGRA2_ENABLE_UARTD 1 +#define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTD_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD +#define CONFIG_SYS_BOARD_ODMDATA
[U-Boot] [PATCH v3 3/4] arm: Tegra2: Add support for NVIDIA Harmony board
Signed-off-by: Tom Warren twar...@nvidia.com --- Changes for V2: - Use board/nvidia/ instead of /board/tegra - Change nv-common.h config file to tegra2-common.h MAINTAINERS |4 + board/nvidia/harmony/Makefile | 50 boards.cfg |1 + include/configs/harmony.h | 48 include/configs/tegra2-common.h | 160 +++ 5 files changed, 263 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/harmony/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/tegra2-common.h diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..b5cff19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -841,6 +841,10 @@ Prafulla Wadaskar prafu...@marvell.com rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Tom Warren twar...@nvidia.com + + harmony Tegra2 (ARM7 A9 Dual Core) + Matthias Weisser weiss...@arcor.de jadecpu ARM926EJS (MB86R01 SoC) diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/harmony/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index 94b8745..ee7c4b7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -122,6 +122,7 @@ omap4_panda arm armv7 panda ti omap4_sdp4430arm armv7 sdp4430 ti omap4 s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx +harmony arm armv7 harmony nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/harmony.h b/include/configs/harmony.h new file mode 100644 index 000..7d8f27a --- /dev/null +++ b/include/configs/harmony.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (Harmony) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Harmony + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTD 1 +#define CONFIG_TEGRA2_ENABLE_UARTA 0
[U-Boot] [PATCH 0/4 V2] Add basic NVIDIA Tegra2 SoC support
This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. V2: Make changes based on feedback from Peter Tyser and Sandeep Paulraj. Tom Warren (4): arm: Tegra2: Add basic NVIDIA Tegra2 SoC support serial: Add Tegra2 serial port support arm: Tegra2: Add support for NVIDIA Harmony board arm: Tegra2: Add support for NVIDIA Seaboard board MAINTAINERS |5 + arch/arm/cpu/armv7/tegra2/Makefile | 48 ++ arch/arm/cpu/armv7/tegra2/board.c| 91 ++ arch/arm/cpu/armv7/tegra2/config.mk | 28 +++ arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 66 +++ arch/arm/cpu/armv7/tegra2/sys_info.c | 35 arch/arm/cpu/armv7/tegra2/timer.c| 122 + arch/arm/include/asm/arch-tegra2/clk_rst.h | 155 + arch/arm/include/asm/arch-tegra2/pinmux.h| 52 ++ arch/arm/include/asm/arch-tegra2/pmc.h | 125 ++ arch/arm/include/asm/arch-tegra2/sys_proto.h | 33 arch/arm/include/asm/arch-tegra2/tegra2.h| 49 ++ arch/arm/include/asm/arch-tegra2/uart.h | 45 + board/nvidia/common/board.c | 234 ++ board/nvidia/common/board.h | 57 +++ board/nvidia/harmony/Makefile| 50 ++ board/nvidia/seaboard/Makefile | 50 ++ boards.cfg |2 + common/serial.c |3 +- include/configs/harmony.h| 48 ++ include/configs/seaboard.h | 43 + include/configs/tegra2-common.h | 160 ++ include/serial.h |3 +- 23 files changed, 1502 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c create mode 100644 board/nvidia/common/board.h create mode 100644 board/nvidia/harmony/Makefile create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/seaboard.h create mode 100644 include/configs/tegra2-common.h -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4 V2] arm: Tegra2: Add support for NVIDIA Harmony board
Basic support for the NVIDIA Harmony board. U-Boot will load and respond to serial console commands with this patch. Further peripheral support (USB, SD/MMC, NAND, etc.) to follow. Signed-off-by: Tom Warren twar...@nvidia.com --- MAINTAINERS |4 + board/nvidia/harmony/Makefile | 50 boards.cfg |1 + include/configs/harmony.h | 48 include/configs/tegra2-common.h | 160 +++ 5 files changed, 263 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/harmony/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/tegra2-common.h diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..b5cff19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -841,6 +841,10 @@ Prafulla Wadaskar prafu...@marvell.com rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Tom Warren twar...@nvidia.com + + harmony Tegra2 (ARM7 A9 Dual Core) + Matthias Weisser weiss...@arcor.de jadecpu ARM926EJS (MB86R01 SoC) diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/harmony/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index 94b8745..ee7c4b7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -122,6 +122,7 @@ omap4_panda arm armv7 panda ti omap4_sdp4430arm armv7 sdp4430 ti omap4 s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx +harmony arm armv7 harmony nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/harmony.h b/include/configs/harmony.h new file mode 100644 index 000..7d8f27a --- /dev/null +++ b/include/configs/harmony.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (Harmony) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Harmony + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define
[U-Boot] [PATCH 4/4 V2] arm: Tegra2: Add support for NVIDIA Seaboard board
Basic support for the NVIDIA Seaboard board. U-Boot will load and respond to serial console commands with this patch. Further peripheral support (USB, SD/MMC, SPI, etc.) to follow. Signed-off-by: Tom Warren twar...@nvidia.com --- MAINTAINERS|1 + board/nvidia/seaboard/Makefile | 50 boards.cfg |1 + include/configs/seaboard.h | 43 ++ 4 files changed, 95 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 include/configs/seaboard.h diff --git a/MAINTAINERS b/MAINTAINERS index b5cff19..f4795d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -844,6 +844,7 @@ Prafulla Wadaskar prafu...@marvell.com Tom Warren twar...@nvidia.com harmony Tegra2 (ARM7 A9 Dual Core) + seaboardTegra2 (ARM7 A9 Dual Core) Matthias Weisser weiss...@arcor.de diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile new file mode 100644 index 000..3a146cb --- /dev/null +++ b/board/nvidia/seaboard/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation www.nvidia.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS += ../common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/boards.cfg b/boards.cfg index ee7c4b7..3c4c249 100644 --- a/boards.cfg +++ b/boards.cfg @@ -123,6 +123,7 @@ omap4_sdp4430arm armv7 sdp4430 ti s5p_goni arm armv7 goni samsungs5pc1xx smdkc100 arm armv7 smdkc100 samsungs5pc1xx harmony arm armv7 harmony nvidia tegra2 +seaboard arm armv7 seaboard nvidia tegra2 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h new file mode 100644 index 000..ee3ae25 --- /dev/null +++ b/include/configs/seaboard.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h +#include tegra2-common.h + +/* High-level configuration options */ +#define TEGRA2_SYSMEM mem=384M@0M nvmem=128M@384M mem=512M@512M +#define V_PROMPT Tegra2 (SeaBoard) # +#define CONFIG_TEGRA2_BOARD_STRING NVIDIA Seaboard + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTD 1 +#define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTD_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD +#define
[U-Boot] [PATCH 1/4 V2] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Add basic support for NVIDIA Tegra2 SoC chipset
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/cpu/armv7/tegra2/Makefile | 48 ++
arch/arm/cpu/armv7/tegra2/board.c| 91 ++
arch/arm/cpu/armv7/tegra2/config.mk | 28 +++
arch/arm/cpu/armv7/tegra2/lowlevel_init.S| 66 +++
arch/arm/cpu/armv7/tegra2/sys_info.c | 35
arch/arm/cpu/armv7/tegra2/timer.c| 122 +
arch/arm/include/asm/arch-tegra2/clk_rst.h | 155 +
arch/arm/include/asm/arch-tegra2/pinmux.h| 52 ++
arch/arm/include/asm/arch-tegra2/pmc.h | 125 ++
arch/arm/include/asm/arch-tegra2/sys_proto.h | 33
arch/arm/include/asm/arch-tegra2/tegra2.h| 49 ++
arch/arm/include/asm/arch-tegra2/uart.h | 45 +
board/nvidia/common/board.c | 234 ++
board/nvidia/common/board.h | 57 +++
14 files changed, 1140 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile
create mode 100644 arch/arm/cpu/armv7/tegra2/board.c
create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk
create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S
create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c
create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c
create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h
create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h
create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h
create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h
create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h
create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h
create mode 100644 board/nvidia/common/board.c
create mode 100644 board/nvidia/common/board.h
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile
b/arch/arm/cpu/armv7/tegra2/Makefile
new file mode 100644
index 000..75fba0b
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+SOBJS := lowlevel_init.o
+COBJS := sys_info.o board.o timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:$(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/armv7/tegra2/board.c
b/arch/arm/cpu/armv7/tegra2/board.c
new file mode 100644
index 000..e180f05
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/sys_proto.h
+#include asm/arch/tegra2.h
+#include asm/arch/pmc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
+ * so we are using this value to identify memory size.
+ */
+
+static unsigned int query_sdram_size(void)
+{
+ pmc_ctlr *const pmc
[U-Boot] [PATCH 2/4 V2] serial: Add Tegra2 serial port support
Enable support for serial output on Tegra2 builds Signed-off-by: Tom Warren twar...@nvidia.com --- common/serial.c |3 ++- include/serial.h |3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/common/serial.c b/common/serial.c index 051ae4e..8ebf9a5 100644 --- a/common/serial.c +++ b/common/serial.c @@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void) #elif defined(CONFIG_4xx) \ || defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \ || defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \ - || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) + || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) \ + || defined(CONFIG_TEGRA2) #if defined(CONFIG_CONS_INDEX) defined(CONFIG_SYS_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return eserial1_device; diff --git a/include/serial.h b/include/serial.h index 15ab73c..f21d961 100644 --- a/include/serial.h +++ b/include/serial.h @@ -27,7 +27,8 @@ extern struct serial_device * default_serial_console (void); defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ -defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) +defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ +defined(CONFIG_TEGRA2) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4 V2] Add basic NVIDIA Tegra2 SoC support
On Fri, Jan 14, 2011 at 12:59 PM, Peter Tyser pty...@xes-inc.com wrote: Hi Tom, On Fri, 2011-01-14 at 10:11 -0700, Tom Warren wrote: This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. V2: Make changes based on feedback from Peter Tyser and Sandeep Paulraj. If you didn't use all the feedback to the original patches, you should state explicitly what you changed here, or respond to the original comment email as to why they weren't made. For example, I see you didn't make the suggested change to use IO access functions, or allow compiling out of support for UARTA and UARTD. That should be made clear somewhere (and the logic of why the changes weren't made) so that those reviewing the patches know what changed between v1 and v2 and why. As is its unclear why the v1 comments weren't implemented, so they also apply to this series. Peter, Sorry, since this is my first patch series to U-Boot upstream, I'm still learning the proper etiquette. Let me respond here rather than in the patch comments since there are only 2 unchanged areas WRT comments. 1) IO access functions - I pre-reviewed my patch series with Wolfgang (to hopefully catch any blatant errors and smooth the process) and he indicated that C structs and I/O accessor funcs or macros were preferred to my base+offset original code. Since the ARM is 32-bit, and all of our registers are I/O mapped, it made sense just to cast the necessary HW mem-mapped regs as volatile structs and access the members directly. Works well, is easy to read understand, etc. Let me know (with examples, if possible) how I can make it better. 2) Compiling out support for UARTA or UARTD - didn't seem necessary - size isn't an issue at this point with Tegra2 U-Boot, and some boards (Harmony, for example) are populated w/hardware for both UARTA and UARTD, and can have both on at U-Boot runtime (perhaps for debug out to UARTA whilst normal console I/O goes to UARTD), so I chose to leave the init code for both intact. Plus I've never liked code with too many unnecessary ifdef's - makes it less readable, IMO. I was going to respond to your review w/a direct, inline reply, but I thought it better to get the V2 patch out there before the weekend (we're off for MLK, as well). I'm under some pressure to get a baseline Tegra2 patchset in before the merge window closes. I'll be sure to respond to each issue directly on the list in the future, though. Thanks for the thorough review, Tom Best, Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4 V2] Add basic NVIDIA Tegra2 SoC support
On Fri, Jan 14, 2011 at 2:36 PM, Peter Tyser pty...@xes-inc.com wrote: On Fri, 2011-01-14 at 13:41 -0700, Tom Warren wrote: On Fri, Jan 14, 2011 at 12:59 PM, Peter Tyser pty...@xes-inc.com wrote: Hi Tom, On Fri, 2011-01-14 at 10:11 -0700, Tom Warren wrote: This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. V2: Make changes based on feedback from Peter Tyser and Sandeep Paulraj. If you didn't use all the feedback to the original patches, you should state explicitly what you changed here, or respond to the original comment email as to why they weren't made. For example, I see you didn't make the suggested change to use IO access functions, or allow compiling out of support for UARTA and UARTD. That should be made clear somewhere (and the logic of why the changes weren't made) so that those reviewing the patches know what changed between v1 and v2 and why. As is its unclear why the v1 comments weren't implemented, so they also apply to this series. Peter, Sorry, since this is my first patch series to U-Boot upstream, I'm still learning the proper etiquette. Let me respond here rather than in the patch comments since there are only 2 unchanged areas WRT comments. No worries. I'm glad to see you're pushing your changes upstream. 1) IO access functions - I pre-reviewed my patch series with Wolfgang (to hopefully catch any blatant errors and smooth the process) and he indicated that C structs and I/O accessor funcs or macros were preferred to my base+offset original code. Since the ARM is 32-bit, and all of our registers are I/O mapped, it made sense just to cast the necessary HW mem-mapped regs as volatile structs and access the members directly. Works well, is easy to read understand, etc. Let me know (with examples, if possible) how I can make it better. Both Linux and U-Boot recommend using IO access functions instead pointer accesses, at least in PPC-land, and even for memory mapped registers. I'm not too familiar with ARM, but assume they have the same recommendation. If pointers are used, some CPUs may optimize the access order, thus causing problems. Using IO accessors also ensures that the code is portable. Even if the Tegra doesn't re-order accesses, a driver you write for use in a Tegra could be used on other CPUs that do. eg: http://www.mail-archive.com/u-boot@lists.denx.de/msg18435.html http://lists.denx.de/pipermail/u-boot/2007-December/027595.html It looks like other ARM processors use IO accessors too, eg the recent armada CPU: arch/arm/cpu/arm926ejs/armada100/* A grep of writel in arch/arm shows a number of references. Similarly in the Linux code in arch/arm. So instead of, say uart-lcr = 0, you'd prefer writel(0, uart-lcr), where writel = __arch_putl(v, a) = (*(volatile unsigned int *)(a) = (v))? Is that different enough from 'uart-lcr = 0' to warrant the change? Does it add some HW barriers or forced read-before-write that the 'volatile' struct doesn't? I've done a ton of embedded work, but all in x86 asm (and C) on PCs, so pardon my ignorance questions. ARM maintainers, feel free to chime in if you have comments. 2) Compiling out support for UARTA or UARTD - didn't seem necessary - size isn't an issue at this point with Tegra2 U-Boot, and some boards (Harmony, for example) are populated w/hardware for both UARTA and UARTD, and can have both on at U-Boot runtime (perhaps for debug out to UARTA whilst normal console I/O goes to UARTD), so I chose to leave the init code for both intact. Plus I've never liked code with too many unnecessary ifdef's - makes it less readable, IMO. Yeah, this is grey - I see both sides of the coin. U-Boot generally strives to be as small as possible. You may use a large flash on your eval boards and not care about space, but other system designers may place as small of flash as possible to save cost. It looked like UART_A-UART_E were also going to be supported at some time, which is quite a chunk of code. You also already are defining which serial ports are available at compile time via CONFIG_TEGRA2_ENABLE_UARTA and CONFIG_TEGRA2_ENABLE_UARTD. Anyway, I don't really care much which way you go, just wanted to make sure you were making a conscious decision to not add the ifdefs. As conscious I get before noon. ;) I was going to respond to your review w/a direct, inline reply, but I thought it better to get the V2 patch out there before the weekend (we're off for MLK, as well). I'm under some pressure to get a baseline Tegra2 patchset in before the merge window closes. I'll be sure to respond to each issue directly on the list in the future, though. As long as you initially submit your patches during the merge
