[PATCH v2 1/1] arch: arm: Program GIC LPI configuration table
From: Bharat Kumar Reddy Gooty Programs the following: 1. Redistributor PROCBASER configuration table (which is common for all redistributors) 2. Redistributor pending table (PENDBASER), for all the available redistributors. Signed-off-by: Bharat Kumar Reddy Gooty Signed-off-by: Vladimir Olovyannikov --- arch/arm/Kconfig | 10 +++ arch/arm/include/asm/gic-v3.h | 134 ++ arch/arm/lib/Makefile | 1 + arch/arm/lib/gic-v3-its.c | 100 + 4 files changed, 245 insertions(+) create mode 100644 arch/arm/include/asm/gic-v3.h create mode 100644 arch/arm/lib/gic-v3-its.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f96841c777..c0b45df9d0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -61,6 +61,16 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE endif endif +config GIC_V3_ITS + bool "ARM GICV3 ITS" + help + ARM GICV3 Interrupt translation service (ITS). + Basic support for programming locality specific peripheral + interrupts (LPI) configuration tables and enable LPI tables. + LPI configuration table can be used by u-boot or Linux. + ARM GICV3 has limitation, once the LPI table is enabled, LPI + configuration table can not be re-programmed, unless GICV3 reset. + config STATIC_RELA bool default y if ARM64 && !POSITION_INDEPENDENT diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h new file mode 100644 index 00..ac6c9e7013 --- /dev/null +++ b/arch/arm/include/asm/gic-v3.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom. + */ + +#ifndef __GIC_V3_H__ +#define __GIC_V3_H__ + +#define GICR_CTLR_ENABLE_LPIS BIT(0) +#define GICR_CTLR_RWP BIT(3) + +#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0x) + +#define GICR_WAKER_PROCESSORSLEEP BIT(1) +#define GICR_WAKER_CHILDRENASLEEP BIT(2) + +#define GIC_BASER_CACHE_NCNB 0ULL +#define GIC_BASER_CACHE_SAMEASINNER0ULL +#define GIC_BASER_CACHE_NC 1ULL +#define GIC_BASER_CACHE_RAWT 2ULL +#define GIC_BASER_CACHE_RAWB 3ULL +#define GIC_BASER_CACHE_WAWT 4ULL +#define GIC_BASER_CACHE_WAWB 5ULL +#define GIC_BASER_CACHE_RAWAWT 6ULL +#define GIC_BASER_CACHE_RAWAWB 7ULL +#define GIC_BASER_CACHE_MASK 7ULL +#define GIC_BASER_NONSHAREABLE 0ULL +#define GIC_BASER_INNERSHAREABLE 1ULL +#define GIC_BASER_OUTERSHAREABLE 2ULL +#define GIC_BASER_SHAREABILITY_MASK3ULL + +#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ + (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) + +#define GIC_BASER_SHAREABILITY(reg, type) \ + (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) + +/* encode a size field of width @w containing @n - 1 units */ +#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) &\ +GENMASK_ULL(((w) - 1), 0)) + +#define GICR_PROPBASER_SHAREABILITY_SHIFT (10) +#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT(7) +#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT(56) +#define GICR_PROPBASER_SHAREABILITY_MASK \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) +#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) +#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) +#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK + +#define GICR_PROPBASER_INNERSHAREABLE \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, INNERSHAREABLE) + +#define GICR_PROPBASER_NCNB\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NCNB) +#define GICR_PROPBASER_NC \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NC) +#define GICR_PROPBASER_RAWT\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWT) +#define GICR_PROPBASER_RAWB\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWB) +#define GICR_PROPBASER_WAWT\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWT) +#define GICR_PROPBASER_WAWB\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWB) +#define GICR_PROPBASER_RAWAWT \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWT) +#define GICR_PROPBASER_RAWAWB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWB) + +#define GICR_PROPBASER_IDBITS_MASK (0x1f) +#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) +#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) + +#define GICR_PENDBASER_SHAREABILITY_SHIFT (10) +#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT(7) +#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT(56) +#define GICR_PENDBASER_SHAR
RE: [PATCH 1/1] arch: arm: Program GIC LPI configuration table
> -Original Message- > From: Tom Rini > Sent: Friday, December 6, 2019 11:02 AM > > On Wed, Dec 04, 2019 at 09:14:02PM -0800, Vladimir Olovyannikov wrote: > > > From: Bharat Kumar Reddy Gooty > > > > Programs the following: > > 1. Redistributor PROCBASER configuration table (which is common for > > all redistributors) 2. Redistributor pending table (PENDBASER), for > > all the available redistributors. > > > > Signed-off-by: Bharat Kumar Reddy Gooty > > > Signed-off-by: Vladimir Olovyannikov > > > > --- > > arch/arm/Kconfig | 11 +++ > > arch/arm/include/asm/gic-v3.h | 134 > ++ > > arch/arm/lib/Makefile | 3 + > > arch/arm/lib/gic-v3-its.c | 100 + > > 4 files changed, 248 insertions(+) > > create mode 100644 arch/arm/include/asm/gic-v3.h create mode 100644 > > arch/arm/lib/gic-v3-its.c > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > f96841c777..cf46aa867d 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -61,6 +61,17 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE endif > endif > > > > +config GIC_V3_ITS > > + bool "ARM GICV3 ITS" > > + default n > > Note that n is the default, we can drop this. > > > diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index > > 9de9a9acee..942ed1c73a 100644 > > --- a/arch/arm/lib/Makefile > > +++ b/arch/arm/lib/Makefile > > @@ -52,6 +52,9 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += ccn504.o ifneq > > ($(CONFIG_GICV2)$(CONFIG_GICV3),) > > obj-y += gic_64.o > > endif > > +ifdef CONFIG_GIC_V3_ITS > > +obj-y += gic-v3-its.o > > +endif > > obj-y += interrupts_64.o > > else > > obj-y += interrupts.o > > This part of the Makefile can be tricky to read. We should be able to use the > normal formation of 'obj-$(CONFIG_GIC_V3_ITS)' in this spot in the file as we > don't have other difficult to express concisely in make constraints around. > > Other than that, please make sure the code is checkpatch clean, I don't have > any commentary on the implementation itself but I gather it's tested on your > end. Thanks! > Thank you for review Tom, These will be addressed in the next patch ver. Vladimir > -- > Tom
[PATCH 1/1] drivers: net: add Broadcom bnxt driver for supported platforms
From: Suresh Channappa
Add bnxt L2 driver support.
This driver is used by several Broadcom iProc platforms.
Signed-off-by: Suresh Channappa
Signed-off-by: Vladimir Olovyannikov
---
drivers/net/Kconfig |1 +
drivers/net/Makefile|1 +
drivers/net/bnxt/Kconfig|8 +
drivers/net/bnxt/Makefile |5 +
drivers/net/bnxt/bnxt.c | 2202 +++
drivers/net/bnxt/bnxt.h | 403 +++
drivers/net/bnxt/bnxt_dbg.h | 538 +
drivers/net/bnxt/bnxt_hsi.h | 889 ++
drivers/net/bnxt/bnxt_ver.h | 22 +
drivers/net/bnxt/pci_ids.h | 17 +
10 files changed, 4086 insertions(+)
create mode 100644 drivers/net/bnxt/Kconfig
create mode 100644 drivers/net/bnxt/Makefile
create mode 100644 drivers/net/bnxt/bnxt.c
create mode 100644 drivers/net/bnxt/bnxt.h
create mode 100644 drivers/net/bnxt/bnxt_dbg.h
create mode 100644 drivers/net/bnxt/bnxt_hsi.h
create mode 100644 drivers/net/bnxt/bnxt_ver.h
create mode 100644 drivers/net/bnxt/pci_ids.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4182897d89..3c136eeaa7 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,6 +1,7 @@
source "drivers/net/phy/Kconfig"
source "drivers/net/pfe_eth/Kconfig"
source "drivers/net/fsl-mc/Kconfig"
+source "drivers/net/bnxt/Kconfig"
config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 30991834ec..7b26cf9f2c 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -3,6 +3,7 @@
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+obj-$(CONFIG_BNXT_ETH) += bnxt/
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
obj-$(CONFIG_AG7XXX) += ag7xxx.o
obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
diff --git a/drivers/net/bnxt/Kconfig b/drivers/net/bnxt/Kconfig
new file mode 100644
index 00..0805f6e53d
--- /dev/null
+++ b/drivers/net/bnxt/Kconfig
@@ -0,0 +1,8 @@
+config BNXT_ETH
+ bool "BNXT PCI support"
+ depends on DM_ETH && DM_PCI
+ help
+ This driver implements support for
+ Broadcom pcie BCM57320 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb
+ RDMA Ethernet Controller (bnxt pci controller).
+ The controller is used on Broadcom iProc platforms.
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
new file mode 100644
index 00..6ba101b44c
--- /dev/null
+++ b/drivers/net/bnxt/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2019 Broadcom.
+
+# Broadcom nxe Ethernet driver
+obj-y += bnxt.o
\ No newline at end of file
diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c
new file mode 100644
index 00..45199083b1
--- /dev/null
+++ b/drivers/net/bnxt/bnxt.c
@@ -0,0 +1,2202 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "bnxt.h"
+#include "bnxt_dbg.h"
+#include "pci_ids.h"
+
+static void print_mac(u8 *mac, u8 flag);
+static const char banner[] = DRV_MODULE_DESC " v" UBOOT_MODULE_VER ",";
+static const char fw_ver[] = " FW v";
+
+static void display_banner(struct bnxt *bp)
+{
+ int i;
+
+ printf(banner);
+ printf(fw_ver);
+ printf("%d.%d.", bp->fw_maj, bp->fw_min);
+ printf("%d.%d\n", bp->fw_bld, bp->fw_rsvd);
+ printf("ETH MAC: ");
+ for (i = 0; i < ETH_ALEN; i++) {
+ printf("%02x", bp->mac_set[i]);
+ if (i != (ETH_ALEN - 1))
+ printf(":");
+ }
+
+ printf(", Port(%d), PF(%d)\n", bp->port_idx, bp->ordinal_value);
+}
+
+/* Broadcom ethernet driver PCI APIs. */
+static void bnxt_bring_pci(struct bnxt *bp)
+{
+ u16 cmd_reg = 0;
+
+ pci_read_word16(bp->pdev, PCI_VENDOR_ID, >vendor_id);
+ pci_read_word16(bp->pdev, PCI_DEVICE_ID, >device_id);
+ pci_read_word16(bp->pdev,
+ PCI_SUBSYSTEM_VENDOR_ID,
+ >subsystem_vendor);
+ pci_read_word16(bp->pdev, PCI_SUBSYSTEM_ID, >subsystem_device);
+ pci_read_word16(bp->pdev, PCI_COMMAND, >cmd_reg);
+ pci_read_byte(bp->pdev, PCICFG_ME_REGISTER, >pf_num);
+ pci_read_byte(bp->pdev, PCI_INTERRUPT_LINE, >irq);
+ bp->bar0 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ bp->bar1 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
+ bp->bar2 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
+ cmd_reg = bp->cmd_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ cmd_reg |= PCI_COMMAND_INTX_DI
[PATCH 1/1] arch: arm: Program GIC LPI configuration table
From: Bharat Kumar Reddy Gooty Programs the following: 1. Redistributor PROCBASER configuration table (which is common for all redistributors) 2. Redistributor pending table (PENDBASER), for all the available redistributors. Signed-off-by: Bharat Kumar Reddy Gooty Signed-off-by: Vladimir Olovyannikov --- arch/arm/Kconfig | 11 +++ arch/arm/include/asm/gic-v3.h | 134 ++ arch/arm/lib/Makefile | 3 + arch/arm/lib/gic-v3-its.c | 100 + 4 files changed, 248 insertions(+) create mode 100644 arch/arm/include/asm/gic-v3.h create mode 100644 arch/arm/lib/gic-v3-its.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f96841c777..cf46aa867d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -61,6 +61,17 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE endif endif +config GIC_V3_ITS + bool "ARM GICV3 ITS" + default n + help + ARM GICV3 Interrupt translation service (ITS). + Basic support for programming locality specific peripheral + interrupts (LPI) configuration tables and enable LPI tables. + LPI configuration table can be used by u-boot or Linux. + ARM GICV3 has limitation, once the LPI table is enabled, LPI + configuration table can not be re-programmed, unless GICV3 reset. + config STATIC_RELA bool default y if ARM64 && !POSITION_INDEPENDENT diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h new file mode 100644 index 00..ac6c9e7013 --- /dev/null +++ b/arch/arm/include/asm/gic-v3.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom. + */ + +#ifndef __GIC_V3_H__ +#define __GIC_V3_H__ + +#define GICR_CTLR_ENABLE_LPIS BIT(0) +#define GICR_CTLR_RWP BIT(3) + +#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0x) + +#define GICR_WAKER_PROCESSORSLEEP BIT(1) +#define GICR_WAKER_CHILDRENASLEEP BIT(2) + +#define GIC_BASER_CACHE_NCNB 0ULL +#define GIC_BASER_CACHE_SAMEASINNER0ULL +#define GIC_BASER_CACHE_NC 1ULL +#define GIC_BASER_CACHE_RAWT 2ULL +#define GIC_BASER_CACHE_RAWB 3ULL +#define GIC_BASER_CACHE_WAWT 4ULL +#define GIC_BASER_CACHE_WAWB 5ULL +#define GIC_BASER_CACHE_RAWAWT 6ULL +#define GIC_BASER_CACHE_RAWAWB 7ULL +#define GIC_BASER_CACHE_MASK 7ULL +#define GIC_BASER_NONSHAREABLE 0ULL +#define GIC_BASER_INNERSHAREABLE 1ULL +#define GIC_BASER_OUTERSHAREABLE 2ULL +#define GIC_BASER_SHAREABILITY_MASK3ULL + +#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ + (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) + +#define GIC_BASER_SHAREABILITY(reg, type) \ + (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) + +/* encode a size field of width @w containing @n - 1 units */ +#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) &\ +GENMASK_ULL(((w) - 1), 0)) + +#define GICR_PROPBASER_SHAREABILITY_SHIFT (10) +#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT(7) +#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT(56) +#define GICR_PROPBASER_SHAREABILITY_MASK \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) +#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) +#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) +#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK + +#define GICR_PROPBASER_INNERSHAREABLE \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, INNERSHAREABLE) + +#define GICR_PROPBASER_NCNB\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NCNB) +#define GICR_PROPBASER_NC \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NC) +#define GICR_PROPBASER_RAWT\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWT) +#define GICR_PROPBASER_RAWB\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWB) +#define GICR_PROPBASER_WAWT\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWT) +#define GICR_PROPBASER_WAWB\ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWB) +#define GICR_PROPBASER_RAWAWT \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWT) +#define GICR_PROPBASER_RAWAWB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWB) + +#define GICR_PROPBASER_IDBITS_MASK (0x1f) +#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) +#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) + +#define GICR_PENDBASER_SHAREABILITY_SHIFT (10) +#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT(7) +#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT
[U-Boot] [PATCH v3 1/2] dt-bindings: Documentation on BRCM xHCI controller
From: Bharat Kumar Reddy Gooty
DT bindings document for Broadcom xHCI controller.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
---
.../devicetree/bindings/usb/brcm,generic-xhci.txt| 12
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
diff --git a/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
b/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
new file mode 100644
index 00..621b99c9f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
@@ -0,0 +1,12 @@
+Broadcom USB xHCI Controller
+
+Required properties:
+ - compatible: "brcm,generic-xhci"
+ - reg: Base address and length of the standard xHCI register set
+
+Example:
+
+ xhci0: usb@68501000 {
+ compatible = "brcm,generic-xhci";
+ reg = <0x68501000 0x1000>;
+ };
--
2.17.1
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[U-Boot] [PATCH v3 2/2] drivers: usb: host: Add BRCM xHCI driver
From: Bharat Kumar Reddy Gooty
Base driver for Broadcom xHCI controllers
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
---
drivers/usb/host/Kconfig | 8 +++
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-brcm.c | 105 +++
3 files changed, 114 insertions(+)
create mode 100644 drivers/usb/host/xhci-brcm.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0987ff25b1..94ac969058 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -88,6 +88,14 @@ config USB_XHCI_FSL
depends on !SPL_NO_USB
help
Enables support for the on-chip xHCI controller on NXP Layerscape
SoCs.
+
+config USB_XHCI_BRCM
+ bool "Broadcom USB3 Host XHCI controller"
+ depends on DM_USB
+ help
+ USB controller based on the Broadcom USB3 IP Core.
+ Supports USB2/3 functionality.
+
endif # USB_XHCI_HCD
config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7feeff679c..b62f346094 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
+obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o
obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
diff --git a/drivers/usb/host/xhci-brcm.c b/drivers/usb/host/xhci-brcm.c
new file mode 100644
index 00..c53c93209e
--- /dev/null
+++ b/drivers/usb/host/xhci-brcm.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Broadcom.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "xhci.h"
+
+#define DRD2U3H_XHC_REGS_AXIWRA0xC08
+#define DRD2U3H_XHC_REGS_AXIRDA0xC0C
+
+#define USBAXI_AWCACHE 0xF
+#define USBAXI_ARCACHE 0xF
+#define USBAXI_AWPROT 0x8
+#define USBAXI_ARPROT 0x8
+#define USBAXIWR_SA_VAL((USBAXI_AWCACHE << 4) | USBAXI_AWPROT)
+#define USBAXIWR_SA_MASK 0xFF
+#define USBAXIWR_UA_VAL(((USBAXI_AWCACHE << 4) |
USBAXI_AWPROT) << 16)
+#define USBAXIWR_UA_MASK (0xFF << 16)
+#define USBAXIRD_SA_VAL((USBAXI_ARCACHE << 4) | USBAXI_ARPROT)
+#define USBAXIRD_SA_MASK 0xFF
+#define USBAXIRD_UA_VAL(((USBAXI_ARCACHE << 4) |
USBAXI_ARPROT) << 16)
+#define USBAXIRD_UA_MASK (0xFF << 16)
+
+struct brcm_xhci_platdata {
+ unsigned int arcache;
+ unsigned int awcache;
+};
+
+static int xhci_brcm_probe(struct udevice *dev)
+{
+ struct xhci_hccr *hcd;
+ struct xhci_hcor *hcor;
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ uintptr_t hc_base;
+ int len, ret = 0;
+
+ if (!plat) {
+ dev_err(dev, "Can't get xHCI Plat data\n");
+ return -ENOMEM;
+ }
+
+ hcd = dev_read_addr_ptr(dev);
+ if (!hcd) {
+ dev_err(dev, "Can't get the xHCI register base address\n");
+ return -ENXIO;
+ }
+
+ hc_base = (uintptr_t)hcd;
+ len = HC_LENGTH(xhci_readl(>cr_capbase));
+ hcor = (struct xhci_hcor *)(hc_base + len);
+
+ /* Save the default values of AXI read and write attributes */
+ plat->awcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIWRA);
+ plat->arcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIRDA);
+
+ /* Enable AXI read and write attributes. */
+ clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIWRA),
+ (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+ (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+ clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIRDA),
+ (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+ (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+ ret = xhci_register(dev, hcd, hcor);
+ if (ret)
+ dev_err(dev, "Failed to register xHCI\n");
+
+ return ret;
+}
+
+static int xhci_brcm_deregister(struct udevice *dev)
+{
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ uintptr_t hc_base;
+
+ hc_base = (uintptr_t)dev_read_addr(dev);
+
+ /* Restore the default values for AXI read and write attributes */
+ writel(plat->awcache, hc_base + DRD2U3H_XHC_REGS_AXIWRA);
+ writel(plat->arcache, hc_base + DRD2U3H_XHC_REGS_AXIRDA);
+
+ return xhci_deregister(dev);
+}
+
+static const struct udevice_id xhci_brcm_ids[] = {
+ { .compatible = "brcm,generic-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_brcm",
+ .id = UCLASS_USB,
+
[U-Boot] [PATCH v3 0/2] Add Broadcom XHCI driver for iproc platforms
This patchset adds Broadcom XHCI driver for iproc platforms. This USB controller is based on the Broadcom USB3 IP Core. Supports USB2/3 functionality. Bharat Kumar Reddy Gooty (2): dt-bindings: Documentation on BRCM xHCI controller drivers: usb: host: Add BRCM xHCI driver .../bindings/usb/brcm,generic-xhci.txt| 12 ++ drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-brcm.c | 105 ++ 4 files changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt create mode 100644 drivers/usb/host/xhci-brcm.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/2] dt-bindings: Documentation on BRCM xHCI controller
From: Bharat Kumar Reddy Gooty
DT bindings document for Broadcom xHCI controller.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
---
.../devicetree/bindings/usb/brcm,generic-xhci.txt| 12
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
diff --git a/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
b/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
new file mode 100644
index 00..621b99c9f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
@@ -0,0 +1,12 @@
+Broadcom USB xHCI Controller
+
+Required properties:
+ - compatible: "brcm,generic-xhci"
+ - reg: Base address and length of the standard xHCI register set
+
+Example:
+
+ xhci0: usb@68501000 {
+ compatible = "brcm,generic-xhci";
+ reg = <0x68501000 0x1000>;
+ };
--
2.17.1
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[U-Boot] [PATCH v3 2/2] drivers: usb: host: Add BRCM xHCI driver
From: Bharat Kumar Reddy Gooty
Base driver for Broadcom xHCI controllers
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
---
drivers/usb/host/Kconfig | 8 +++
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-brcm.c | 105 +++
3 files changed, 114 insertions(+)
create mode 100644 drivers/usb/host/xhci-brcm.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0987ff25b1..94ac969058 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -88,6 +88,14 @@ config USB_XHCI_FSL
depends on !SPL_NO_USB
help
Enables support for the on-chip xHCI controller on NXP Layerscape
SoCs.
+
+config USB_XHCI_BRCM
+ bool "Broadcom USB3 Host XHCI controller"
+ depends on DM_USB
+ help
+ USB controller based on the Broadcom USB3 IP Core.
+ Supports USB2/3 functionality.
+
endif # USB_XHCI_HCD
config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7feeff679c..b62f346094 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
+obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o
obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
diff --git a/drivers/usb/host/xhci-brcm.c b/drivers/usb/host/xhci-brcm.c
new file mode 100644
index 00..c53c93209e
--- /dev/null
+++ b/drivers/usb/host/xhci-brcm.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Broadcom.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "xhci.h"
+
+#define DRD2U3H_XHC_REGS_AXIWRA0xC08
+#define DRD2U3H_XHC_REGS_AXIRDA0xC0C
+
+#define USBAXI_AWCACHE 0xF
+#define USBAXI_ARCACHE 0xF
+#define USBAXI_AWPROT 0x8
+#define USBAXI_ARPROT 0x8
+#define USBAXIWR_SA_VAL((USBAXI_AWCACHE << 4) | USBAXI_AWPROT)
+#define USBAXIWR_SA_MASK 0xFF
+#define USBAXIWR_UA_VAL(((USBAXI_AWCACHE << 4) |
USBAXI_AWPROT) << 16)
+#define USBAXIWR_UA_MASK (0xFF << 16)
+#define USBAXIRD_SA_VAL((USBAXI_ARCACHE << 4) | USBAXI_ARPROT)
+#define USBAXIRD_SA_MASK 0xFF
+#define USBAXIRD_UA_VAL(((USBAXI_ARCACHE << 4) |
USBAXI_ARPROT) << 16)
+#define USBAXIRD_UA_MASK (0xFF << 16)
+
+struct brcm_xhci_platdata {
+ unsigned int arcache;
+ unsigned int awcache;
+};
+
+static int xhci_brcm_probe(struct udevice *dev)
+{
+ struct xhci_hccr *hcd;
+ struct xhci_hcor *hcor;
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ uintptr_t hc_base;
+ int len, ret = 0;
+
+ if (!plat) {
+ dev_err(dev, "Can't get xHCI Plat data\n");
+ return -ENOMEM;
+ }
+
+ hcd = dev_read_addr_ptr(dev);
+ if (!hcd) {
+ dev_err(dev, "Can't get the xHCI register base address\n");
+ return -ENXIO;
+ }
+
+ hc_base = (uintptr_t)hcd;
+ len = HC_LENGTH(xhci_readl(>cr_capbase));
+ hcor = (struct xhci_hcor *)(hc_base + len);
+
+ /* Save the default values of AXI read and write attributes */
+ plat->awcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIWRA);
+ plat->arcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIRDA);
+
+ /* Enable AXI read and write attributes. */
+ clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIWRA),
+ (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+ (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+ clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIRDA),
+ (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+ (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+ ret = xhci_register(dev, hcd, hcor);
+ if (ret)
+ dev_err(dev, "Failed to register xHCI\n");
+
+ return ret;
+}
+
+static int xhci_brcm_deregister(struct udevice *dev)
+{
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ uintptr_t hc_base;
+
+ hc_base = (uintptr_t)dev_read_addr(dev);
+
+ /* Restore the default values for AXI read and write attributes */
+ writel(plat->awcache, hc_base + DRD2U3H_XHC_REGS_AXIWRA);
+ writel(plat->arcache, hc_base + DRD2U3H_XHC_REGS_AXIRDA);
+
+ return xhci_deregister(dev);
+}
+
+static const struct udevice_id xhci_brcm_ids[] = {
+ { .compatible = "brcm,generic-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_brcm",
+ .id = UCLASS_USB,
+
[U-Boot] [PATCH v2 0/2] Add Broadcom XHCI driver for iproc platforms
This patchset adds Broadcom XHCI driver for iproc platforms. This USB controller is based on the Broadcom USB3 IP Core. Supports USB2/3 functionality. Bharat Kumar Reddy Gooty (2): dt-bindings: Documentation on BRCM xHCI controller drivers: usb: host: Add BRCM xHCI driver .../bindings/usb/brcm,generic-xhci.txt| 12 ++ drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-brcm.c | 105 ++ 4 files changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt create mode 100644 drivers/usb/host/xhci-brcm.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] drivers: usb: host: Add BRCM xHCI driver
> -Original Message- > From: Marek Vasut > Sent: Tuesday, November 26, 2019 10:22 AM [...] > On 11/26/19 7:18 PM, Vladimir Olovyannikov wrote: > [...] > > + /* Enable AXI read and write attributes. */ > > + clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIWRA), > > Here is another extra parenthesis ;-) > > > + (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK), > > + (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL)); > > + clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIRDA), > > + (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK), > > + (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL)); > > There is a lot of them ^ Please fix those, otherwise it's good. Thanks for the catch. Will be addressed in patch v3. > > [..] ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] drivers: usb: host: Add BRCM xHCI driver
From: Bharat Kumar Reddy Gooty
Base driver for Broadcom xHCI controllers
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
---
drivers/usb/host/Kconfig | 8 +++
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-brcm.c | 105 +++
3 files changed, 114 insertions(+)
create mode 100644 drivers/usb/host/xhci-brcm.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0987ff25b1..94ac969058 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -88,6 +88,14 @@ config USB_XHCI_FSL
depends on !SPL_NO_USB
help
Enables support for the on-chip xHCI controller on NXP Layerscape
SoCs.
+
+config USB_XHCI_BRCM
+ bool "Broadcom USB3 Host XHCI controller"
+ depends on DM_USB
+ help
+ USB controller based on the Broadcom USB3 IP Core.
+ Supports USB2/3 functionality.
+
endif # USB_XHCI_HCD
config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7feeff679c..b62f346094 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
+obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o
obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
diff --git a/drivers/usb/host/xhci-brcm.c b/drivers/usb/host/xhci-brcm.c
new file mode 100644
index 00..c53c93209e
--- /dev/null
+++ b/drivers/usb/host/xhci-brcm.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Broadcom.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "xhci.h"
+
+#define DRD2U3H_XHC_REGS_AXIWRA0xC08
+#define DRD2U3H_XHC_REGS_AXIRDA0xC0C
+
+#define USBAXI_AWCACHE 0xF
+#define USBAXI_ARCACHE 0xF
+#define USBAXI_AWPROT 0x8
+#define USBAXI_ARPROT 0x8
+#define USBAXIWR_SA_VAL((USBAXI_AWCACHE << 4) | USBAXI_AWPROT)
+#define USBAXIWR_SA_MASK 0xFF
+#define USBAXIWR_UA_VAL(((USBAXI_AWCACHE << 4) |
USBAXI_AWPROT) << 16)
+#define USBAXIWR_UA_MASK (0xFF << 16)
+#define USBAXIRD_SA_VAL((USBAXI_ARCACHE << 4) | USBAXI_ARPROT)
+#define USBAXIRD_SA_MASK 0xFF
+#define USBAXIRD_UA_VAL(((USBAXI_ARCACHE << 4) |
USBAXI_ARPROT) << 16)
+#define USBAXIRD_UA_MASK (0xFF << 16)
+
+struct brcm_xhci_platdata {
+ unsigned int arcache;
+ unsigned int awcache;
+};
+
+static int xhci_brcm_probe(struct udevice *dev)
+{
+ struct xhci_hccr *hcd;
+ struct xhci_hcor *hcor;
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ uintptr_t hc_base;
+ int len, ret = 0;
+
+ if (!plat) {
+ dev_err(dev, "Can't get xHCI Plat data\n");
+ return -ENOMEM;
+ }
+
+ hcd = dev_read_addr_ptr(dev);
+ if (!hcd) {
+ dev_err(dev, "Can't get the xHCI register base address\n");
+ return -ENXIO;
+ }
+
+ hc_base = (uintptr_t)hcd;
+ len = HC_LENGTH(xhci_readl(>cr_capbase));
+ hcor = (struct xhci_hcor *)(hc_base + len);
+
+ /* Save the default values of AXI read and write attributes */
+ plat->awcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIWRA);
+ plat->arcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIRDA);
+
+ /* Enable AXI read and write attributes. */
+ clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIWRA),
+ (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+ (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+ clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIRDA),
+ (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+ (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+ ret = xhci_register(dev, hcd, hcor);
+ if (ret)
+ dev_err(dev, "Failed to register xHCI\n");
+
+ return ret;
+}
+
+static int xhci_brcm_deregister(struct udevice *dev)
+{
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ uintptr_t hc_base;
+
+ hc_base = (uintptr_t)dev_read_addr(dev);
+
+ /* Restore the default values for AXI read and write attributes */
+ writel(plat->awcache, hc_base + DRD2U3H_XHC_REGS_AXIWRA);
+ writel(plat->arcache, hc_base + DRD2U3H_XHC_REGS_AXIRDA);
+
+ return xhci_deregister(dev);
+}
+
+static const struct udevice_id xhci_brcm_ids[] = {
+ { .compatible = "brcm,generic-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_brcm",
+ .id = UCLASS_USB,
+
[U-Boot] [PATCH v2 1/2] dt-bindings: Documentation on BRCM xHCI controller
From: Bharat Kumar Reddy Gooty
DT bindings document for Broadcom xHCI controller.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
---
.../devicetree/bindings/usb/brcm,generic-xhci.txt| 12
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
diff --git a/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
b/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
new file mode 100644
index 00..621b99c9f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
@@ -0,0 +1,12 @@
+Broadcom USB xHCI Controller
+
+Required properties:
+ - compatible: "brcm,generic-xhci"
+ - reg: Base address and length of the standard xHCI register set
+
+Example:
+
+ xhci0: usb@68501000 {
+ compatible = "brcm,generic-xhci";
+ reg = <0x68501000 0x1000>;
+ };
--
2.17.1
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[U-Boot] [PATCH v2 0/2] Add Broadcom XHCI driver for iproc platforms
This patchset adds Broadcom XHCI driver for iproc platforms. This USB controller is based on the Broadcom USB3 IP Core. Supports USB2/3 functionality. Bharat Kumar Reddy Gooty (2): dt-bindings: Documentation on BRCM xHCI controller drivers: usb: host: Add BRCM xHCI driver .../bindings/usb/brcm,generic-xhci.txt| 12 ++ drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-brcm.c | 105 ++ 4 files changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt create mode 100644 drivers/usb/host/xhci-brcm.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] drivers: usb: host: Add BRCM xHCI driver
HI Marek,
> On 11/23/19 12:31 AM, Vladimir Olovyannikov wrote:
> [...]
>
> > +#define USBAXI_AWCACHE 0xF
> > +#define USBAXI_ARCACHE 0xF
> > +#define USBAXI_AWPROT 0x8
> > +#define USBAXI_ARPROT 0x8
> > +#define USBAXIWR_SA_VAL((USBAXI_AWCACHE << 4 |
> USBAXI_AWPROT) << 0)
>
> Are the parenthesis correct here ?
> Might make sense to rewrite it as ((AWCACHE << 4) | AWPROT)
>
> > +#define USBAXIWR_SA_MASK (0xff)
>
> Here the parenthesis are not needed.
>
> > +#define USBAXIWR_UA_VAL((USBAXI_AWCACHE << 4 |
> USBAXI_AWPROT) << 16)
> > +#define USBAXIWR_UA_MASK ((0xff) << 16)
> > +#define USBAXIRD_SA_VAL((USBAXI_ARCACHE << 4 |
> USBAXI_ARPROT) << 0)
> > +#define USBAXIRD_SA_MASK (0xff)
> > +#define USBAXIRD_UA_VAL((USBAXI_ARCACHE << 4 |
> USBAXI_ARPROT) << 16)
> > +#define USBAXIRD_UA_MASK ((0xff) << 16)
> > +
> > +struct brcm_xhci_platdata {
> > + unsigned int arcache;
> > + unsigned int awcache;
> > +};
> > +
> > +static int xhci_brcm_probe(struct udevice *dev) {
> > + struct xhci_hccr *hcd;
> > + struct xhci_hcor *hcor;
> > + struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
> > + int len, ret = 0;
> > +
> > + if (!plat) {
> > + dev_err(dev, "Can't get xHCI Plat data\n");
> > + return -ENOMEM;
> > + }
> > +
> > + hcd = dev_read_addr_ptr(dev);
> > + if (!hcd) {
> > + dev_err(dev, "Can't get the xHCI register base address\n");
> > + return -ENXIO;
> > + }
> > +
> > + len = HC_LENGTH(xhci_readl(&(hcd)->cr_capbase));
> > + hcor = (struct xhci_hcor *)((uintptr_t)hcd + len);
>
> Please clean up the extraneous parenthesis ^
>
> > + /* Save the default values of AXI read and write attributes */
> > + plat->awcache = readl((uintptr_t)hcd +
> DRD2U3H_XHC_REGS_AXIWRA);
> > + plat->arcache = readl((uintptr_t)hcd +
> DRD2U3H_XHC_REGS_AXIRDA);
> > +
> > + /* Enable AXI read and write attributes. */
> > + clrsetbits_le32(((uintptr_t)hcd + DRD2U3H_XHC_REGS_AXIWRA),
> > + (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
> > + (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
> > + clrsetbits_le32(((uintptr_t)hcd + DRD2U3H_XHC_REGS_AXIRDA),
> > + (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
> > + (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
> > +
> > + ret = xhci_register(dev, hcd, hcor);
> > + if (ret)
> > + dev_err(dev, "Failed to register xHCI\n");
> > +
> > + return ret;
> > +}
> > +
> > +static int xhci_brcm_deregister(struct udevice *dev) {
> > + struct xhci_hccr *hcd;
> > + struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
> > +
> > + hcd = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
> > +
> > + /* Restore the default values for AXI read and write attributes */
> > + writel(plat->awcache, ((uintptr_t)hcd +
> DRD2U3H_XHC_REGS_AXIWRA));
> > + writel(plat->arcache, ((uintptr_t)hcd +
> DRD2U3H_XHC_REGS_AXIRDA));
>
> Here too.
>
> Looks good otherwise, thanks.
Thanks for review Marek,
Issues will be resolved with the next patch set.
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[U-Boot] [PATCH 1/2] dt-bindings: Documentation on BRCM xHCI controller
From: Bharat Kumar Reddy Gooty
DT bindings document for Broadcom xHCI controller.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
---
.../devicetree/bindings/usb/brcm,generic-xhci.txt| 12
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
diff --git a/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
b/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
new file mode 100644
index 00..621b99c9f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt
@@ -0,0 +1,12 @@
+Broadcom USB xHCI Controller
+
+Required properties:
+ - compatible: "brcm,generic-xhci"
+ - reg: Base address and length of the standard xHCI register set
+
+Example:
+
+ xhci0: usb@68501000 {
+ compatible = "brcm,generic-xhci";
+ reg = <0x68501000 0x1000>;
+ };
--
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[U-Boot] [PATCH 2/2] drivers: usb: host: Add BRCM xHCI driver
From: Bharat Kumar Reddy Gooty
Base driver for Broadcom xHCI controllers
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
---
drivers/usb/host/Kconfig | 8 +++
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-brcm.c | 103 +++
3 files changed, 112 insertions(+)
create mode 100644 drivers/usb/host/xhci-brcm.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0987ff25b1..94ac969058 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -88,6 +88,14 @@ config USB_XHCI_FSL
depends on !SPL_NO_USB
help
Enables support for the on-chip xHCI controller on NXP Layerscape
SoCs.
+
+config USB_XHCI_BRCM
+ bool "Broadcom USB3 Host XHCI controller"
+ depends on DM_USB
+ help
+ USB controller based on the Broadcom USB3 IP Core.
+ Supports USB2/3 functionality.
+
endif # USB_XHCI_HCD
config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7feeff679c..b62f346094 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
+obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o
obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
diff --git a/drivers/usb/host/xhci-brcm.c b/drivers/usb/host/xhci-brcm.c
new file mode 100644
index 00..84ec95f804
--- /dev/null
+++ b/drivers/usb/host/xhci-brcm.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "xhci.h"
+
+#define DRD2U3H_XHC_REGS_AXIWRA0xC08
+#define DRD2U3H_XHC_REGS_AXIRDA0xC0C
+
+#define USBAXI_AWCACHE 0xF
+#define USBAXI_ARCACHE 0xF
+#define USBAXI_AWPROT 0x8
+#define USBAXI_ARPROT 0x8
+#define USBAXIWR_SA_VAL((USBAXI_AWCACHE << 4 | USBAXI_AWPROT)
<< 0)
+#define USBAXIWR_SA_MASK (0xff)
+#define USBAXIWR_UA_VAL((USBAXI_AWCACHE << 4 | USBAXI_AWPROT)
<< 16)
+#define USBAXIWR_UA_MASK ((0xff) << 16)
+#define USBAXIRD_SA_VAL((USBAXI_ARCACHE << 4 | USBAXI_ARPROT)
<< 0)
+#define USBAXIRD_SA_MASK (0xff)
+#define USBAXIRD_UA_VAL((USBAXI_ARCACHE << 4 | USBAXI_ARPROT)
<< 16)
+#define USBAXIRD_UA_MASK ((0xff) << 16)
+
+struct brcm_xhci_platdata {
+ unsigned int arcache;
+ unsigned int awcache;
+};
+
+static int xhci_brcm_probe(struct udevice *dev)
+{
+ struct xhci_hccr *hcd;
+ struct xhci_hcor *hcor;
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ int len, ret = 0;
+
+ if (!plat) {
+ dev_err(dev, "Can't get xHCI Plat data\n");
+ return -ENOMEM;
+ }
+
+ hcd = dev_read_addr_ptr(dev);
+ if (!hcd) {
+ dev_err(dev, "Can't get the xHCI register base address\n");
+ return -ENXIO;
+ }
+
+ len = HC_LENGTH(xhci_readl(&(hcd)->cr_capbase));
+ hcor = (struct xhci_hcor *)((uintptr_t)hcd + len);
+
+ /* Save the default values of AXI read and write attributes */
+ plat->awcache = readl((uintptr_t)hcd + DRD2U3H_XHC_REGS_AXIWRA);
+ plat->arcache = readl((uintptr_t)hcd + DRD2U3H_XHC_REGS_AXIRDA);
+
+ /* Enable AXI read and write attributes. */
+ clrsetbits_le32(((uintptr_t)hcd + DRD2U3H_XHC_REGS_AXIWRA),
+ (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+ (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+ clrsetbits_le32(((uintptr_t)hcd + DRD2U3H_XHC_REGS_AXIRDA),
+ (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+ (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+ ret = xhci_register(dev, hcd, hcor);
+ if (ret)
+ dev_err(dev, "Failed to register xHCI\n");
+
+ return ret;
+}
+
+static int xhci_brcm_deregister(struct udevice *dev)
+{
+ struct xhci_hccr *hcd;
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+
+ hcd = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
+
+ /* Restore the default values for AXI read and write attributes */
+ writel(plat->awcache, ((uintptr_t)hcd + DRD2U3H_XHC_REGS_AXIWRA));
+ writel(plat->arcache, ((uintptr_t)hcd + DRD2U3H_XHC_REGS_AXIRDA));
+
+ return xhci_deregister(dev);
+}
+
+static const struct udevice_id xhci_brcm_ids[] = {
+ { .compatible = "brcm,generic-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_brcm",
+ .id
[U-Boot] [PATCH 0/2] Add Broadcom XHCI driver for iproc platforms
This patchset adds Broadcom XHCI driver for iproc platforms This USB controller is based on the Broadcom USB3 IP Core. Supports USB2/3 functionality. Bharat Kumar Reddy Gooty (2): dt-bindings: Documentation on BRCM xHCI controller drivers: usb: host: Add BRCM xHCI driver .../bindings/usb/brcm,generic-xhci.txt| 12 ++ drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-brcm.c | 103 ++ 4 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/brcm,generic-xhci.txt create mode 100644 drivers/usb/host/xhci-brcm.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] dt-bindings: documentation on sp805(DM) iproc driver
From: Pramod Kumar
DT documentation for sp805 DM wdt Broadcom iproc driver
used by iproc-based socs.
Signed-off-by: Pramod Kumar
Signed-off-by: Vladimir Olovyannikov
---
.../devicetree/bindings/watchdog/sp805-wdt_dm.txt | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt_dm.txt
diff --git a/Documentation/devicetree/bindings/watchdog/sp805-wdt_dm.txt
b/Documentation/devicetree/bindings/watchdog/sp805-wdt_dm.txt
new file mode 100644
index 00..34b677fd64
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/sp805-wdt_dm.txt
@@ -0,0 +1,15 @@
+sp805 is an ARM Watchdog Timer (WDT) Controller (DM)
+
+Required properties:
+-compatible : Should be arm,sp805-wdt
+-reg : Base address and size of the watchdog timer registers.
+-clk-mhz : Watchdog clock in mhz
+timeout-msec : Watchdog timer expire value in msec
+
+Example:
+ wdt0: watchdog@c {
+ compatible = "arm,sp805-wdt";
+ reg = <0x000c 0x1000>;
+ clk-mhz = <1250>;
+ timeout-msec = <6>;
+ };
--
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[U-Boot] [PATCH 2/2] drivers: watchdog: Add brcm iproc sp805 watchdog driver
From: Pramod Kumar
Add sp805 watchdog driver for Broadcom iproc socs (DM).
Signed-off-by: Pramod Kumar
Signed-off-by: Vladimir Olovyannikov
---
drivers/watchdog/Kconfig| 10 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/sp805_wdt_dm.c | 181
3 files changed, 192 insertions(+)
create mode 100644 drivers/watchdog/sp805_wdt_dm.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 8c16d69d33..74a5319467 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -40,6 +40,16 @@ config OMAP_WATCHDOG
help
Say Y here to enable the OMAP3+ watchdog driver.
+config SP805_WATCHDOG
+ bool "Enable ARM SP805 watchdog driver (DM)"
+ depends on WDT
+ imply WATCHDOG
+ help
+ Say Y here to enable the sp805 watchdog (DM)
+
+ This provides basic infrastructure to support sp805 watchdog
+ hardware; driver model.
+
config ULP_WATCHDOG
bool "i.MX7ULP watchdog"
help
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 955caef815..aacabf1f2e 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_SP805_WATCHDOG) += sp805_iproc_dm.o
obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o
obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
diff --git a/drivers/watchdog/sp805_wdt_dm.c b/drivers/watchdog/sp805_wdt_dm.c
new file mode 100644
index 00..56d0e77080
--- /dev/null
+++ b/drivers/watchdog/sp805_wdt_dm.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Broadcom.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* SP805 register offset */
+#define SP805_WDOG_LOAD_OFF0x000
+#define SP805_WDOG_CTR_OFF 0x008
+#define SP805_WDOG_CLR_OFF 0x00c
+#define SP805_WDOG_LOCK_OFF0xc00
+
+/* Magic word to unlock the wd registers */
+#define WDOG_UNLOCK_KEY0x1ACCE551
+
+/* Register field definitions */
+#define SP805_CTR_RESENBIT(1)
+#define SP805_CTR_INTENBIT(0)
+
+struct sp805_wdt_platdata {
+ void __iomem *regs;
+ u32 timeout_msec;
+ u32 clk_mhz;
+};
+
+/* Inline register access functions */
+
+static inline void sp805_write_wdog_load(void __iomem *base, u32 value)
+{
+ writel(value, base + SP805_WDOG_LOAD_OFF);
+}
+
+static inline void sp805_write_wdog_ctrl(void __iomem *base, u32 value)
+{
+ writel(value, base + SP805_WDOG_CTR_OFF);
+}
+
+static inline void sp805_write_wdog_lock(void __iomem *base, u32 value)
+{
+ writel(value, base + SP805_WDOG_LOCK_OFF);
+}
+
+static inline void sp805_write_wdog_kick(void __iomem *base, u32 value)
+{
+ writel(value, base + SP805_WDOG_CLR_OFF);
+}
+
+static u32 msec_to_ticks(struct udevice *dev)
+{
+ u32 timeout_msec;
+ u32 msec;
+ struct sp805_wdt_platdata *pd = dev_get_platdata(dev);
+
+ timeout_msec = env_get_ulong("wdt_timeout_msec", 16, 0);
+ if (timeout_msec) {
+ dev_dbg(dev, "Overriding timeout :%u\n", timeout_msec);
+ msec = timeout_msec;
+ } else {
+ msec = pd->timeout_msec;
+ }
+
+ timeout_msec = (msec / 2) * (pd->clk_mhz / 1000);
+
+ dev_dbg(dev, "ticks :%u\n", timeout_msec);
+
+ return timeout_msec;
+}
+
+static int sp805_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct sp805_wdt_platdata *pd = dev_get_platdata(dev);
+
+ sp805_write_wdog_lock(pd->regs, WDOG_UNLOCK_KEY);
+ sp805_write_wdog_load(pd->regs, 0);
+ sp805_write_wdog_lock(pd->regs, 0);
+
+ return 0;
+}
+
+static int sp805_wdt_reset(struct udevice *dev)
+{
+ struct sp805_wdt_platdata *pd = dev_get_platdata(dev);
+ u32 ticks;
+
+ ticks = msec_to_ticks(dev);
+
+ sp805_write_wdog_lock(pd->regs, WDOG_UNLOCK_KEY);
+ sp805_write_wdog_load(pd->regs, ticks);
+ sp805_write_wdog_lock(pd->regs, 0);
+
+ dev_dbg(dev, "%s ", __func__);
+
+ return 0;
+}
+
+static int sp805_wdt_stop(struct udevice *dev)
+{
+ struct sp805_wdt_platdata *pd = dev_get_platdata(dev);
+
+ sp805_write_wdog_lock(pd->regs, WDOG_UNLOCK_KEY);
+ sp805_write_wdog_ctrl(pd->regs, 0);
+
+ dev_dbg(dev, "Watchdog disabled!\n");
+
+ return 0;
+}
+
+static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct sp805_wdt_platdata *pd = dev_get_platdata(dev);
+ u32 ticks;
+
+ ticks = msec_to_ti
[U-Boot] [PATCH 0/2] Add SP805 driver for iproc platforms (DM)
This patchset adds driver-model based SP805 watchdog driver for Broadcom iProc platforms Pramod Kumar (2): dt-bindings: documentation on sp805(DM) iproc driver drivers: watchdog: Add brcm iproc sp805 watchdog driver .../bindings/watchdog/sp805-wdt_dm.txt| 15 ++ drivers/watchdog/Kconfig | 10 + drivers/watchdog/Makefile | 1 + drivers/watchdog/sp805_wdt_dm.c | 181 ++ 4 files changed, 207 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt_dm.txt create mode 100644 drivers/watchdog/sp805_wdt_dm.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] drivers: mmc: rpmb: Use R1 response
From: Bharat Kumar Reddy Gooty
If the host has Broken R1B, use only R1 response type.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
---
drivers/mmc/rpmb.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c
index 33371fe562..ee6dbe30db 100644
--- a/drivers/mmc/rpmb.c
+++ b/drivers/mmc/rpmb.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include "mmc_private.h"
@@ -91,6 +92,7 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct
s_rpmb *s,
{
struct mmc_cmd cmd = {0};
struct mmc_data data;
+ struct sdhci_host *host = mmc->priv;
int ret;
ret = mmc_set_blockcount(mmc, count, is_rel_write);
@@ -105,6 +107,9 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct
s_rpmb *s,
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_R1;
+ if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
+ cmd.resp_type = MMC_RSP_R1;
+
data.src = (const char *)s;
data.blocks = 1;
data.blocksize = MMC_MAX_BLOCK_LEN;
--
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[U-Boot] [PATCH 1/2] drivers: spi: Add commands for Micron SPI
Add commands for dual and quad SPI transfers on Micon SPI.
Signed-off-by: Corneliu Doban
Signed-off-by: Vladimir Olovyannikov
---
include/spi.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/spi.h b/include/spi.h
index 6fbb4336ce..ae36835e95 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,6 +30,10 @@
#define SPI_RX_SLOWBIT(11) /* receive with 1 wire slow */
#define SPI_RX_DUALBIT(12) /* receive with 2 wires */
#define SPI_RX_QUADBIT(13) /* receive with 4 wires */
+#define SPI_RX_4X BIT(14) /*
+* addr on 1 wire
+* data on 4 wires
+*/
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -115,6 +119,8 @@ struct spi_slave {
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
#define SPI_XFER_MMAP BIT(2) /* Memory Mapped start */
#define SPI_XFER_MMAP_END BIT(3) /* Memory Mapped End */
+#define SPI_XFER_DUAL BIT(30)
+#define SPI_XFER_QUAD BIT(31)
};
/**
--
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[U-Boot] [PATCH 2/2] drivers: spi: Add brcm iproc spi driver
From: Shreesha Rajashekar Add iproc spi/qspi driver for Broadcom iproc architecture based soc's. Signed-off-by: Shreesha Rajashekar Signed-off-by: Bharat Kumar Reddy Gooty Signed-off-by: Rayagonda Kokatanur Signed-off-by: Vladimir Olovyannikov --- drivers/spi/Kconfig | 26 + drivers/spi/Makefile |4 + drivers/spi/iproc_qspi.c | 1161 ++ drivers/spi/iproc_qspi.h | 47 ++ drivers/spi/iproc_spi.c | 71 +++ 5 files changed, 1309 insertions(+) create mode 100644 drivers/spi/iproc_qspi.c create mode 100644 drivers/spi/iproc_qspi.h create mode 100644 drivers/spi/iproc_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8588866489..b18f26d61a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -405,6 +405,32 @@ config DAVINCI_SPI help Enable the Davinci SPI driver +config IPROC_SPI + bool "SPI support for iproc soc's" + help + This selects the iproc SPI controller. + The controller is used in iProc SoCs. + +config IPROC_PL022_SPI + bool "ARM PL022 SPI driver" + select IPROC_SPI + help + Enable the ARM PL022 (SPI) driver for iproc architecture soc's. + +config IPROC_QSPI + bool "QSPI driver for BCM iProc QSPI Controller" + select IPROC_SPI + help + This selects the BCM iProc QSPI controller. + This driver support spi flash single, quad and memory reads. + +config BCM_IPROC_USE_BSPI + bool "Broadcom BSPI driver for fast read" + depends on IPROC_QSPI + help + This selects the BCM BSPI driver for fast read mode. + Enable this mode if flash(nand/nor) supports. + config SH_SPI bool "SuperH SPI driver" depends on DEPRECATED diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ae4f2958f8..2388bc6e93 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -32,6 +32,10 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o +ifndef CONFIG_DM_SPI +obj-$(CONFIG_IPROC_SPI) += iproc_spi.o +endif +obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c new file mode 100644 index 00..20ca94d4f3 --- /dev/null +++ b/drivers/spi/iproc_qspi.c @@ -0,0 +1,1161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 Broadcom. + */ + +#include +#include +#include +#include +#include +#include +#include "iproc_qspi.h" + +#define QSPI_AXI_CLK17500 /* 175MHz */ + +/* default SCK frequency, unit: HZ */ +#define QSPI_DEF_SCK_FREQ 5000 + +#ifndef CONFIG_DM_SPI +/* Configurations */ +#ifndef IPROC_QSPI_BUS +#error IPROC_QSPI_BUS not defined +#endif /* !IPROC_QSPI_BUS */ +#ifndef IPROC_QSPI_CS +#error CONFIG_IPROC_QSPI_CS not defined +#endif /* !IPROC_QSPI_CS */ +#endif +#define QSPI_WAIT_TIMEOUT_MS200U /* msec */ + +/* Chip attributes */ +#define QSPI_REG_BASE IPROC_QSPI_BASE_REG +#define CRU_CONTROL_REG IPROC_QSPI_CRU_CONTROL_REG +#define SPBR_MIN8U +#define SPBR_MAX255U +#define NUM_TXRAM 32U +#define NUM_RXRAM 32U +#define NUM_CDRAM 16U + +#define CDRAM_PCS0 2 +#define CDRAM_CONT BIT(7) +#define CDRAM_BITS_EN BIT(6) +#define CDRAM_QUAD_MODE BIT(8) +#define CDRAM_RBIT_INPUTBIT(10) + +#define MSPI_SPEBIT(6) +#define MSPI_CONT_AFTER_CMD BIT(7) + +/* + * Register fields + */ +#define MSPI_SPCR0_MSB_BITS_8 0x0020 +#define BSPI_RAF_CONTROL_START_MASK 0x0001 +#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x0001 +#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x0002 +#define BSPI_BITS_PER_PHASE_ADDR_MARK 0x0001 +#define BSPI_BITS_PER_CYCLE_DATA_SHIFT 0 +#define BSPI_BITS_PER_CYCLE_ADDR_SHIFT 16 +#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT 3 +#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT 1 +#define BSPI_STRAP_OVERRIDE_SHIFT 0 + +/* + * Flash opcode and parameters + */ +#define OPCODE_RDSR 0x05 +#define OPCODE_FAST_READ0x0B +#define OPCODE_DUAL_READ0x3b +#define OPCODE_QUAD_READ0x6b +#define OPCODE_EN4B 0xB7 +#define OPCODE_EX4B 0xE9 +#define OPCODE_BRWR 0x17 + +/* + * Che
[U-Boot] [PATCH 0/2] Add Broadcom SPI driver
This patchset: - adds Broadcom SPI driver for iproc-based platforms and - extends Micron SPI commands for dual and quad SPI transfers on Micon SPI. Shreesha Rajashekar (1): drivers: spi: Add brcm iproc spi driver Corneliu Doban (1): drivers: spi: Add commands for Micron SPI drivers/spi/Kconfig | 26 + drivers/spi/Makefile |4 + drivers/spi/iproc_qspi.c | 1161 ++ drivers/spi/iproc_qspi.h | 47 ++ drivers/spi/iproc_spi.c | 71 +++ include/spi.h|6 + 6 files changed, 1315 insertions(+) create mode 100644 drivers/spi/iproc_qspi.c create mode 100644 drivers/spi/iproc_qspi.h create mode 100644 drivers/spi/iproc_spi.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] arm: cpu: armv8: add support for arm psci reset2.
From: Rajesh Ravi
Current U-Boot has only support for psci reset.
Adding support for arm psci reset2 allows passing of reset level
and other platform sepcific parameters like strap settings
to lowlevel psci implementation.
Signed-off-by: Rajesh Ravi
Signed-off-by: Vladimir Olovyannikov
---
arch/arm/cpu/armv8/fwcall.c | 16
arch/arm/include/asm/psci.h | 4
arch/arm/include/asm/system.h | 1 +
3 files changed, 21 insertions(+)
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index b0aca1b72a..cbd35b7f4a 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -98,6 +98,22 @@ void __noreturn psci_system_reset(void)
;
}
+void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
+ regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
+ regs.regs[2] = cookie;
+ if (use_smc_for_psci)
+ smc_call();
+ else
+ hvc_call();
+
+ while (1)
+ ;
+}
+
void __noreturn psci_system_off(void)
{
struct pt_regs regs;
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 95f18e8cbc..3ddcd95a26 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -64,6 +64,7 @@
#define ARM_PSCI_0_2_FN64_AFFINITY_INFOARM_PSCI_0_2_FN64(4)
#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5)
#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7)
+#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2ARM_PSCI_0_2_FN64(18)
/* PSCI 1.0 interface */
#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
@@ -90,6 +91,9 @@
#define PSCI_AFFINITY_LEVEL_OFF1
#define PSCI_AFFINITY_LEVEL_ON_PENDING 2
+#define PSCI_RESET2_TYPE_VENDOR_SHIFT 31
+#define PSCI_RESET2_TYPE_VENDOR
BIT(PSCI_RESET2_TYPE_VENDOR_SHIFT)
+
#ifndef __ASSEMBLY__
#include
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index a1a5e35ef6..81ccead112 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -254,6 +254,7 @@ void mmu_change_region_attr(phys_addr_t start, size_t size,
u64 attrs);
void smc_call(struct pt_regs *args);
void __noreturn psci_system_reset(void);
+void __noreturn psci_system_reset2(u32 reset_level, u32 cookie);
void __noreturn psci_system_off(void);
#ifdef CONFIG_ARMV8_PSCI
--
2.17.1
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[U-Boot] [PATCH 2/3] pinctrl: pinctrl-single: Add request api
From: Rayagonda Kokatanur
Add pinctrl_ops->request api to configure pctrl pad register
to configure in gpio mode.
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Vladimir Olovyannikov
---
drivers/pinctrl/pinctrl-single.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 6c6a33e4c5..2dcc131513 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -136,6 +136,35 @@ static int single_configure_bits(struct udevice *dev,
}
return 0;
}
+
+static int single_request(struct udevice *dev, int pin, int flags)
+{
+ struct single_pdata *pdata = dev->platdata;
+ struct single_gpiofunc_range *frange = NULL;
+ struct list_head *pos, *tmp;
+ int mux_bytes = 0;
+ u32 data;
+
+ if (!pdata->mask)
+ return -ENOTSUPP;
+
+ list_for_each_safe(pos, tmp, >gpiofuncs) {
+ frange = list_entry(pos, struct single_gpiofunc_range, node);
+ if ((pin >= frange->offset + frange->npins) ||
+ pin < frange->offset)
+ continue;
+
+ mux_bytes = pdata->width / BITS_PER_BYTE;
+ data = pdata->read(pdata->base + pin * mux_bytes);
+ data &= ~pdata->mask;
+ data |= frange->gpiofunc;
+ pdata->write(data, pdata->base + pin * mux_bytes);
+ break;
+ }
+
+ return 0;
+}
+
static int single_set_state(struct udevice *dev,
struct udevice *config)
{
@@ -235,6 +264,7 @@ static int single_ofdata_to_platdata(struct udevice *dev)
const struct pinctrl_ops single_pinctrl_ops = {
.set_state = single_set_state,
+ .request = single_request,
};
static const struct udevice_id single_pinctrl_match[] = {
--
2.17.1
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[U-Boot] [PATCH 1/3] pinctrl: pinctrl-single: Handle different register width
From: Rayagonda Kokatanur
Add support to use different register read/write api's
based on register width.
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Vladimir Olovyannikov
---
drivers/pinctrl/pinctrl-single.c | 111 ++-
1 file changed, 80 insertions(+), 31 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 1dfc97dcea..6c6a33e4c5 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -11,12 +11,23 @@
DECLARE_GLOBAL_DATA_PTR;
+/**
+ * struct single_pdata - pinctrl device instance
+ * @base first configuration register
+ * @offset index of last configuration register
+ * @mask configuration-value mask bits
+ * @width configuration register bit width
+ * @read register read function to use
+ * @write register write function to use
+ */
struct single_pdata {
- fdt_addr_t base;/* first configuration register */
- int offset; /* index of last configuration register */
- u32 mask; /* configuration-value mask bits */
- int width; /* configuration register bit width */
+ void __iomem *base;
+ int offset;
+ u32 mask;
+ int width;
bool bits_per_mux;
+ u32 (*read)(void __iomem *reg);
+ void (*write)(u32 val, void __iomem *reg);
};
struct single_fdt_pin_cfg {
@@ -30,6 +41,36 @@ struct single_fdt_bits_cfg {
fdt32_t mask; /* configuration register mask */
};
+static u32 __maybe_unused single_readb(void __iomem *reg)
+{
+ return readb(reg);
+}
+
+static u32 __maybe_unused single_readw(void __iomem *reg)
+{
+ return readw(reg);
+}
+
+static u32 __maybe_unused single_readl(void __iomem *reg)
+{
+ return readl(reg);
+}
+
+static void __maybe_unused single_writeb(u32 val, void __iomem *reg)
+{
+ writeb(val, reg);
+}
+
+static void __maybe_unused single_writew(u32 val, void __iomem *reg)
+{
+ writew(val, reg);
+}
+
+static void __maybe_unused single_writel(u32 val, void __iomem *reg)
+{
+ writel(val, reg);
+}
+
/**
* single_configure_pins() - Configure pins based on FDT data
*
@@ -55,24 +96,15 @@ static int single_configure_pins(struct udevice *dev,
for (n = 0; n < count; n++, pins++) {
reg = fdt32_to_cpu(pins->reg);
- if ((reg < 0) || (reg > pdata->offset)) {
+ if (reg > pdata->offset) {
dev_dbg(dev, " invalid register offset 0x%pa\n", );
continue;
}
- reg += pdata->base;
+ reg += (phys_addr_t)pdata->base;
val = fdt32_to_cpu(pins->val) & pdata->mask;
- switch (pdata->width) {
- case 16:
- writew((readw(reg) & ~pdata->mask) | val, reg);
- break;
- case 32:
- writel((readl(reg) & ~pdata->mask) | val, reg);
- break;
- default:
- dev_warn(dev, "unsupported register width %i\n",
-pdata->width);
- continue;
- }
+ val |= pdata->read((void __iomem *)reg) & ~pdata->mask;
+ pdata->write(val, (void __iomem *)reg);
+
dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", , val);
}
return 0;
@@ -97,19 +129,9 @@ static int single_configure_bits(struct udevice *dev,
mask = fdt32_to_cpu(pins->mask);
val = fdt32_to_cpu(pins->val) & mask;
+ val |= pdata->read((void __iomem *)reg) & ~mask;
+ pdata->write(val, (void __iomem *)reg);
- switch (pdata->width) {
- case 16:
- writew((readw(reg) & ~mask) | val, reg);
- break;
- case 32:
- writel((readl(reg) & ~mask) | val, reg);
- break;
- default:
- dev_warn(dev, "unsupported register width %i\n",
-pdata->width);
- continue;
- }
dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", , val);
}
return 0;
@@ -153,6 +175,32 @@ static int single_set_state(struct udevice *dev,
return len;
}
+static int single_probe(struct udevice *dev)
+{
+ struct single_pdata *pdata = dev->platdata;
+
+ switch (pdata->width) {
+ case 8:
+ pdata->read = single_readb;
+ pdata->write = single_writeb;
+ break;
+ case 16:
+ pdata->read = single_readw;
+ pdata->wr
[U-Boot] [PATCH 3/3] pinctrl: pinctrl-single: Parse gpio details from dt
From: Rayagonda Kokatanur
Parse different gpio properties from dt as part of probe
function. This detail is required to enable pinctrl pad.
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Vladimir Olovyannikov
---
drivers/pinctrl/pinctrl-single.c | 61 +++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 2dcc131513..449e8a2bfe 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -5,18 +5,35 @@
#include
#include
+#include
#include
#include
#include
DECLARE_GLOBAL_DATA_PTR;
+/**
+ * struct single_gpiofunc_range - pin ranges with same mux value of gpio fun
+ * @offset:offset base of pins
+ * @npins: number pins with the same mux value of gpio function
+ * @gpiofunc: mux value of gpio function
+ * @node: list node
+ */
+struct single_gpiofunc_range {
+ u32 offset;
+ u32 npins;
+ u32 gpiofunc;
+ struct list_head node;
+};
+
/**
* struct single_pdata - pinctrl device instance
* @base first configuration register
* @offset index of last configuration register
* @mask configuration-value mask bits
* @width configuration register bit width
+ * @mutex mutex protecting the list
+ * @gpiofuncs list of gpio functions
* @read register read function to use
* @write register write function to use
*/
@@ -26,6 +43,8 @@ struct single_pdata {
u32 mask;
int width;
bool bits_per_mux;
+ struct mutex mutex;
+ struct list_head gpiofuncs;
u32 (*read)(void __iomem *reg);
void (*write)(u32 val, void __iomem *reg);
};
@@ -204,9 +223,42 @@ static int single_set_state(struct udevice *dev,
return len;
}
+static int single_add_gpio_func(struct udevice *dev,
+ struct single_pdata *pdata)
+{
+ const char *propname = "pinctrl-single,gpio-range";
+ const char *cellname = "#pinctrl-single,gpio-range-cells";
+ struct single_gpiofunc_range *range;
+ struct ofnode_phandle_args gpiospec;
+ int ret, i;
+
+ for (i = 0; ; i++) {
+ ret = ofnode_parse_phandle_with_args(dev->node, propname,
+cellname, 0, i, );
+ /* Do not treat it as error. Only treat it as end condition. */
+ if (ret) {
+ ret = 0;
+ break;
+ }
+ range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL);
+ if (!range) {
+ ret = -ENOMEM;
+ break;
+ }
+ range->offset = gpiospec.args[0];
+ range->npins = gpiospec.args[1];
+ range->gpiofunc = gpiospec.args[2];
+ mutex_lock(>mutex);
+ list_add_tail(>node, >gpiofuncs);
+ mutex_unlock(>mutex);
+ }
+ return ret;
+}
+
static int single_probe(struct udevice *dev)
{
struct single_pdata *pdata = dev->platdata;
+ int ret;
switch (pdata->width) {
case 8:
@@ -227,7 +279,14 @@ static int single_probe(struct udevice *dev)
return -EINVAL;
}
- return 0;
+ mutex_init(>mutex);
+ INIT_LIST_HEAD(>gpiofuncs);
+
+ ret = single_add_gpio_func(dev, pdata);
+ if (ret < 0)
+ dev_err(dev, "%s: Failed to add gpio functions\n", __func__);
+
+ return ret;
}
static int single_ofdata_to_platdata(struct udevice *dev)
--
2.17.1
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[U-Boot] [PATCH 0/3] Extend pinctrl-single driver with APIs
This patch set adds APIs for pinctrl-single driver. 1. Support to use different register read/write api's based on register width. 2. pinctrl_ops->request api to configure pctrl pad register in gpio mode. 3. Parse different gpio properties from dt as part of the probe function. This is required to enable pinctrl pad. Rayagonda Kokatanur (3): pinctrl: pinctrl-single: Handle different register width pinctrl: pinctrl-single: Add request api pinctrl: pinctrl-single: Parse gpio details from dt drivers/pinctrl/pinctrl-single.c | 200 ++- 1 file changed, 169 insertions(+), 31 deletions(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/3] drivers: pci: Fix Host bridge bus number issue
From: Srinath Mannam
Add changes to fix bus number of host bridge is set with device
sequence number issue.
All devices are managed using device sequence number. For PCIe,
devices enabled in DTS are added under PCIE_CLASS with consecutive
device sequence numbers to scan all pcie devices in sequence using
device sequence number. If a device is a bridge then it will enumerate
all endpoints in that bridge, and give sequence numbers in that order.
However, the parent device is a root bridge.
The solution is all bus numbers are device sequence number minus
root bridge sequence number. This way, every root bridge and its
downstream EPs bus numbers start from 0.
So root bridges are different hierarchy of bus numbers.
Signed-off-by: Srinath Mannam
Signed-off-by: Vladimir Olovyannikov
---
drivers/pci/pci-uclass.c | 8 +---
drivers/pci/pci_auto.c | 6 +-
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 896cb6b23a..eb7a01fd55 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -47,8 +47,9 @@ pci_dev_t dm_pci_get_bdf(struct udevice *dev)
{
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
struct udevice *bus = dev->parent;
+ struct udevice *ctrl = pci_get_controller(dev);
- return PCI_ADD_BUS(bus->seq, pplat->devfn);
+ return PCI_ADD_BUS(bus->seq - ctrl->seq, pplat->devfn);
}
/**
@@ -760,11 +761,12 @@ int pci_bind_bus_devices(struct udevice *bus)
pci_dev_t bdf, end;
bool found_multi;
int ret;
+ struct udevice *ctrl = pci_get_controller(bus);
found_multi = false;
- end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
+ end = PCI_BDF(bus->seq - ctrl->seq, PCI_MAX_PCI_DEVICES - 1,
PCI_MAX_PCI_FUNCTIONS - 1);
- for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
+ for (bdf = PCI_BDF(bus->seq - ctrl->seq, 0, 0); bdf <= end;
bdf += PCI_BDF(0, 0, 1)) {
struct pci_child_platdata *pplat;
struct udevice *dev;
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 28667bde8d..42bf51fef2 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -176,8 +176,12 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev,
int sub_bus)
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
struct udevice *ctlr = pci_get_controller(dev);
+ struct udevice *parent = dev->parent;
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
+ if (!parent)
+ return;
+
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
pci_io = ctlr_hose->pci_io;
@@ -188,7 +192,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev,
int sub_bus)
/* Configure bus number registers */
dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
-PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq);
+parent->seq - ctlr->seq);
dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq);
dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
--
2.17.1
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[U-Boot] [PATCH 3/3] drivers: pci: pci-uclass: Get PCI dma regions support
From: Srinath Mannam
Add API to parse dma-regions given in PCIe host controller
DT node.
Signed-off-by: Srinath Mannam
Signed-off-by: Vladimir Olovyannikov
---
drivers/pci/pci-uclass.c | 41
include/pci.h| 2 ++
2 files changed, 43 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index eb7a01fd55..ddc2d5cf2c 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1166,6 +1166,47 @@ ulong pci_conv_size_to_32(ulong old, ulong value, uint
offset,
return value;
}
+int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int
index)
+{
+ int pci_addr_cells, addr_cells, size_cells;
+ int cells_per_record;
+ const u32 *prop;
+ int len;
+ int i = 0;
+
+ prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", );
+ if (!prop) {
+ dev_err(dev, "%s: Cannot decode dma-ranges\n", __func__);
+ return -EINVAL;
+ }
+
+ pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
+ addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
+ size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
+
+ /* PCI addresses are always 3-cells */
+ len /= sizeof(u32);
+ cells_per_record = pci_addr_cells + addr_cells + size_cells;
+ debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
+ cells_per_record);
+
+ while (len) {
+ memp->bus_start = fdtdec_get_number(prop + 1, 2);
+ prop += pci_addr_cells;
+ memp->phys_start = fdtdec_get_number(prop, addr_cells);
+ prop += addr_cells;
+ memp->size = fdtdec_get_number(prop, size_cells);
+ prop += size_cells;
+
+ if (i == index)
+ return 0;
+ i++;
+ len -= cells_per_record;
+ }
+
+ return -EINVAL;
+}
+
int pci_get_regions(struct udevice *dev, struct pci_region **iop,
struct pci_region **memp, struct pci_region **prefp)
{
diff --git a/include/pci.h b/include/pci.h
index ff59ac0e69..ef55f54ea5 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1284,6 +1284,8 @@ struct udevice *pci_get_controller(struct udevice *dev);
int pci_get_regions(struct udevice *dev, struct pci_region **iop,
struct pci_region **memp, struct pci_region **prefp);
+int
+pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index);
/**
* dm_pci_write_bar32() - Write the address of a BAR
*
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/3] Introduce APIs for multi PCIe host controller platforms
This patch set contains proposed API changes to the pci uclass for multi PCIe host controller platforms. 1. Add changes to fix bus number of a host bridge Differentiate bus numbers hierarchy for root bridges. All bus numbers are device sequence numbers minus root bridge sequence number. This way, every root bridge and its downstream EPs bus numbers start from 0. Thus, root bridges are different hierarchy of bus numbers. 2. Get next device fail with driver probe fail In Multi PCIe host controller platforms, if one PCIe host driver probe fails for any reason, the next PCIe host controller device pointer should be tried with its driver probe. Instead, currently the code simply stops enumeration. Add the feature described above. 3. Add ability to parse dma-regions given in PCIe host controller's DT node. Srinath Mannam (3): drivers: pci: Fix Host bridge bus number issue drivers: core: uclass: Get next device fail with driver probe fail drivers: pci: pci-uclass: Get PCI dma regions support drivers/core/uclass.c| 2 +- drivers/pci/pci-uclass.c | 49 +--- drivers/pci/pci_auto.c | 6 - include/pci.h| 2 ++ 4 files changed, 54 insertions(+), 5 deletions(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/3] drivers: core: uclass: Get next device fail with driver probe fail
From: Srinath Mannam Add changes to fix get next device failed if driver probe failed issue. In Multi PCIe host controller platforms, if one PCIe host driver probe failed with any reason then it stops to find next PCIe host controller device pointer to call its driver probe. Signed-off-by: Srinath Mannam Signed-off-by: Vladimir Olovyannikov --- drivers/core/uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index c520ef113a..ab50f8f6db 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -442,7 +442,7 @@ int uclass_get_device_tail(struct udevice *dev, int ret, struct udevice **devp) assert(dev); ret = device_probe(dev); if (ret) - return ret; + dev_dbg(dev, "%s device_probe failed\n", __func__); *devp = dev; -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] drivers: pcie: Add Broadcom IPROC PCIe driver
From: Srinath Mannam
Add support of IPROC PCIe driver for Broadcom Iproc SoCs.
Signed-off-by: Srinath Mannam
Signed-off-by: Vladimir Olovyannikov
---
drivers/pci/Kconfig |6 +
drivers/pci/Makefile |1 +
drivers/pci/pcie_iproc.c | 1238 ++
3 files changed, 1245 insertions(+)
create mode 100644 drivers/pci/pcie_iproc.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 13603b9d57..0adc28623c 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -75,6 +75,12 @@ config PCIE_FSL
PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
This driver does not support SRIO_PCIE_BOOT feature.
+config PCIE_IPROC
+ bool "Broadcom Iproc PCIe driver"
+ depends on DM_PCI
+ help
+ Say Y here if you want to enable Broadcom iProc PCIe controller.
+
config PCI_MPC85XX
bool "MPC85XX PowerPC PCI support"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 219473aa79..49192ad923 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_SH4_PCI) += pci_sh4.o
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
+obj-$(CONFIG_PCIE_IPROC) += pcie_iproc.o
obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c
new file mode 100644
index 00..9410f32a61
--- /dev/null
+++ b/drivers/pci/pcie_iproc.c
@@ -0,0 +1,1238 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IPROC PCIe driver for Broadcom Iproc SoCs
+ * Copyright (C) Broadcom, 2019
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define EP_PERST_SOURCE_SELECT_SHIFT 2
+#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
+#define EP_MODE_SURVIVE_PERST_SHIFT 1
+#define EP_MODE_SURVIVE_PERSTBIT(EP_MODE_SURVIVE_PERST_SHIFT)
+#define RC_PCIE_RST_OUTPUT_SHIFT 0
+#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
+
+#define CFG_IND_ADDR_MASK0x1ffc
+
+#define CFG_ADDR_BUS_NUM_SHIFT 20
+#define CFG_ADDR_BUS_NUM_MASK0x0ff0
+#define CFG_ADDR_DEV_NUM_SHIFT 15
+#define CFG_ADDR_DEV_NUM_MASK0x000f8000
+#define CFG_ADDR_FUNC_NUM_SHIFT 12
+#define CFG_ADDR_FUNC_NUM_MASK 0x7000
+#define CFG_ADDR_REG_NUM_SHIFT 2
+#define CFG_ADDR_REG_NUM_MASK0x0ffc
+#define CFG_ADDR_CFG_TYPE_SHIFT 0
+#define CFG_ADDR_CFG_TYPE_MASK 0x0003
+
+#define IPROC_PCI_PM_CAP 0x48
+#define IPROC_PCI_PM_CAP_MASK0x
+#define IPROC_PCI_EXP_CAP0xac
+
+#define IPROC_PCIE_REG_INVALID 0x
+
+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
+#define PCI_EXP_RTCTL28 /* Root Control */
+/* CRS Software Visibility capability */
+#define PCI_EXP_RTCAP_CRSVIS 0x0001
+
+#define PCI_EXP_LNKSTA 18 /* Link Status */
+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
+
+#define PCIE_PHYLINKUP_SHIFT 3
+#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
+#define PCIE_DL_ACTIVE_SHIFT 2
+#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
+
+/* derive the enum index of the outbound/inbound mapping registers */
+#define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
+
+/*
+ * Maximum number of outbound mapping window sizes that can be supported by any
+ * OARR/OMAP mapping pair
+ */
+#define MAX_NUM_OB_WINDOW_SIZES 4
+
+#define OARR_VALID_SHIFT 0
+#define OARR_VALID BIT(OARR_VALID_SHIFT)
+#define OARR_SIZE_CFG_SHIFT 1
+
+/*
+ * Maximum number of inbound mapping region sizes that can be supported by an
+ * IARR
+ */
+#define MAX_NUM_IB_REGION_SIZES 9
+
+#define IMAP_VALID_SHIFT 0
+#define IMAP_VALID BIT(IMAP_VALID_SHIFT)
+
+#define APB_ERR_EN_SHIFT 0
+#define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
+/*
+ * iProc PCIe host registers
+ */
+enum iproc_pcie_reg {
+ /* clock/reset signal control */
+ IPROC_PCIE_CLK_CTRL = 0,
+
+ /*
+* To allow MSI to be steered to an external MSI controller (e.g., ARM
+* GICv3 ITS)
+*/
+ IPROC_PCIE_MSI_GIC_MODE,
+
+ /*
+* IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the
+* window where the MSI posted writes are written, for the writes to be
+* interpreted as MSI writes.
+*/
+ IPROC_PCIE_MSI_BASE_ADDR,
+ IPROC_PCIE_MSI_WINDOW_SIZE,
+
+ /*
+* To hold the address of the register where the MSI writes are
+* programed. When ARM GICv3 ITS is used, this should be programmed
+
[U-Boot] [PATCH 1/1] cmd: gpt: Enumerate partitions and save info into an U-Boot variable
From: Corneliu Doban
Add enumeration of gpt partitions and saving this information into
U-Boot variables.
Signed-off-by: Corneliu Doban
Signed-off-by: Vladimir Olovyannikov
---
cmd/gpt.c | 95 +++
1 file changed, 95 insertions(+)
diff --git a/cmd/gpt.c b/cmd/gpt.c
index 0c4349f4b2..061ffaa757 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -2,6 +2,8 @@
/*
* cmd_gpt.c -- GPT (GUID Partition Table) handling command
*
+ * Copyright (C) 2019 Broadcom
+ * author: Corneliu Doban
* Copyright (C) 2015
* Lukasz Majewski
*
@@ -804,6 +806,88 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc,
char *subcomm,
}
#endif
+/*
+ * Enumerate partition names into environment variable.
+ */
+static int gpt_enumerate(struct blk_desc *blk_dev_desc)
+{
+ disk_partition_t pinfo;
+ struct part_driver *first_drv =
+ ll_entry_start(struct part_driver, part_driver);
+ const int n_drvs = ll_entry_count(struct part_driver, part_driver);
+ struct part_driver *part_drv;
+ char part_list[2048];
+
+ part_list[0] = 0;
+
+ for (part_drv = first_drv; part_drv != first_drv + n_drvs; part_drv++) {
+ int ret;
+ int i;
+
+ for (i = 1; i < part_drv->max_entries; i++) {
+ ret = part_drv->get_info(blk_dev_desc, i, );
+ if (ret != 0) {
+ /* no more entries in table */
+ break;
+ }
+ strcat(part_list, (const char *)pinfo.name);
+ strcat(part_list, " ");
+ }
+ }
+ if (strlen(part_list) > 0)
+ part_list[strlen(part_list) - 1] = 0;
+ debug("setenv gpt_partition_list %s\n", part_list);
+ env_set("gpt_partition_list", part_list);
+ return 0;
+}
+
+/*
+ * Dynamically setup environment variables for name, index, offset and size
+ * for partition in GPT table after running "gpt setenv" for a partition name.
+ * gpt_partition_name, gpt_partition_entry, gpt_partition_addr and
+ * gpt_partition_size environment variables will be set.
+ */
+static int gpt_setenv(struct blk_desc *blk_dev_desc, const char *name)
+{
+ disk_partition_t pinfo;
+ struct part_driver *first_drv =
+ ll_entry_start(struct part_driver, part_driver);
+ const int n_drvs = ll_entry_count(struct part_driver, part_driver);
+ struct part_driver *part_drv;
+ char buf[32];
+
+ for (part_drv = first_drv; part_drv != first_drv + n_drvs; part_drv++) {
+ int ret;
+ int i;
+
+ for (i = 1; i < part_drv->max_entries; i++) {
+ ret = part_drv->get_info(blk_dev_desc, i, );
+
+ if (ret != 0) {
+ /* no more entries in table */
+ break;
+ }
+ if (strcmp(name, (const char *)pinfo.name) == 0) {
+ /* match found, setup environment variables */
+ sprintf(buf, LBAF, pinfo.start);
+ debug("setenv gpt_partition_addr %s\n", buf);
+ env_set("gpt_partition_addr", buf);
+ sprintf(buf, LBAF, pinfo.size);
+ debug("setenv gpt_partition_size %s\n", buf);
+ env_set("gpt_partition_size", buf);
+ sprintf(buf, "%d", i);
+ debug("setenv gpt_partition_entry %s\n", buf);
+ env_set("gpt_partition_entry", buf);
+ sprintf(buf, "%s", pinfo.name);
+ debug("setenv gpt_partition_name %s\n", buf);
+ env_set("gpt_partition_name", buf);
+ return 0;
+ }
+ }
+ }
+ return -1;
+}
+
/**
* do_gpt(): Perform GPT operations
*
@@ -855,6 +939,10 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
(strcmp(argv[1], "rename") == 0)) {
ret = do_rename_gpt_parts(blk_dev_desc, argv[1], argv[4],
argv[5]);
#endif
+ } else if ((strcmp(argv[1], "setenv") == 0)) {
+ ret = gpt_setenv(blk_dev_desc, argv[4]);
+ } else if ((strcmp(argv[1], "enumerate") == 0)) {
+ ret = gpt_enumerate(blk_dev_desc);
} else {
return CMD_RET_USAGE;
}
@@ -897,4 +985,11 @@ U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt,
" gpt swap mmc 0 foo bar\n"
[U-Boot] [PATCH 1/1] drivers: i2c: Add brcm iproc I2C driver support
From: Arjun Jyothi Add I2C driver support for Broadcom iproc-based socs. Signed-off-by: Arjun Jyothi Signed-off-by: Rayagonda Kokatanur Signed-off-by: Sheetal Tigadoli Signed-off-by: Vladimir Olovyannikov --- drivers/i2c/Kconfig | 623 drivers/i2c/Makefile| 2 +- drivers/i2c/iproc_i2c.c | 765 drivers/i2c/iproc_i2c.h | 356 +++ 4 files changed, 1437 insertions(+), 309 deletions(-) create mode 100644 drivers/i2c/iproc_i2c.c create mode 100644 drivers/i2c/iproc_i2c.h diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 03d2fed341..7a80971b12 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -5,454 +5,461 @@ menu "I2C support" config DM_I2C - bool "Enable Driver Model for I2C drivers" - depends on DM - help - Enable driver model for I2C. The I2C uclass interface: probe, read, - write and speed, is implemented with the bus drivers operations, - which provide methods for bus setting and data transfer. Each chip - device (bus child) info is kept as parent platdata. The interface - is defined in include/i2c.h. +bool "Enable Driver Model for I2C drivers" +depends on DM +help + Enable driver model for I2C. The I2C uclass interface: probe, read, + write and speed, is implemented with the bus drivers operations, + which provide methods for bus setting and data transfer. Each chip + device (bus child) info is kept as parent platdata. The interface + is defined in include/i2c.h. config I2C_CROS_EC_TUNNEL - tristate "Chrome OS EC tunnel I2C bus" - depends on CROS_EC - help - This provides an I2C bus that will tunnel i2c commands through to - the other side of the Chrome OS EC to the I2C bus connected there. - This will work whatever the interface used to talk to the EC (SPI, - I2C or LPC). Some Chromebooks use this when the hardware design - does not allow direct access to the main PMIC from the AP. +tristate "Chrome OS EC tunnel I2C bus" +depends on CROS_EC +help + This provides an I2C bus that will tunnel i2c commands through to + the other side of the Chrome OS EC to the I2C bus connected there. + This will work whatever the interface used to talk to the EC (SPI, + I2C or LPC). Some Chromebooks use this when the hardware design + does not allow direct access to the main PMIC from the AP. config I2C_CROS_EC_LDO - bool "Provide access to LDOs on the Chrome OS EC" - depends on CROS_EC - ---help--- - On many Chromebooks the main PMIC is inaccessible to the AP. This is - often dealt with by using an I2C pass-through interface provided by - the EC. On some unfortunate models (e.g. Spring) the pass-through - is not available, and an LDO message is available instead. This - option enables a driver which provides very basic access to those - regulators, via the EC. We implement this as an I2C bus which - emulates just the TPS65090 messages we know about. This is done to - avoid duplicating the logic in the TPS65090 regulator driver for - enabling/disabling an LDO. +bool "Provide access to LDOs on the Chrome OS EC" +depends on CROS_EC +---help--- +On many Chromebooks the main PMIC is inaccessible to the AP. This is +often dealt with by using an I2C pass-through interface provided by +the EC. On some unfortunate models (e.g. Spring) the pass-through +is not available, and an LDO message is available instead. This +option enables a driver which provides very basic access to those +regulators, via the EC. We implement this as an I2C bus which +emulates just the TPS65090 messages we know about. This is done to +avoid duplicating the logic in the TPS65090 regulator driver for +enabling/disabling an LDO. config I2C_SET_DEFAULT_BUS_NUM - bool "Set default I2C bus number" - depends on DM_I2C - help - Set default number of I2C bus to be accessed. This option provides - behaviour similar to old (i.e. pre DM) I2C bus driver. +bool "Set default I2C bus number" +depends on DM_I2C +help + Set default number of I2C bus to be accessed. This option provides + behaviour similar to old (i.e. pre DM) I2C bus driver. config I2C_DEFAULT_BUS_NUMBER - hex "I2C default bus number" - depends on I2C_SET_DEFAULT_BUS_NUM - default 0x0 - help - Number of default I2C bus to use +hex "I2C default bus number" +depends on I2C_SET_DEFAULT_BUS_NUM +default 0x0 +help + Number of default I2C bus to use config DM_I2C_GPIO - bool "Enable Driver Model for software emulated I2C bus driver&
[U-Boot] [PATCH 1/1] drivers: gpio: Add common Broadcom iproc gpio driver
From: Sheetal Tigadoli
Add common iproc gpio driver for Broadcom's iProc based SoCs
Signed-off-by: Sheetal Tigadoli
Signed-off-by: Vladimir Olovyannikov
---
drivers/gpio/Kconfig | 10 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/iproc_gpio.c | 258 ++
3 files changed, 269 insertions(+)
create mode 100644 drivers/gpio/iproc_gpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c1ad5d64a3..5f289844a8 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -102,6 +102,16 @@ config HSDK_CREG_GPIO
help
This driver supports CREG GPIOs on Synopsys HSDK SOC.
+config IPROC_GPIO
+ bool "Broadcom iProc GPIO driver(without pinconf)"
+ default n
+ help
+ The Broadcom iProc based SoCs- Cygnus, NS2, NSP and Stingray, use
+ same GPIO Controller IP hence this driver could be used for all.
+
+ The Broadcom iProc based SoCs have multiple GPIO controllers and only
+ the always-ON GPIO controller (CRMU/AON) is supported by this driver.
+
config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ccc49e2eb0..c6f8c87584 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
+obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o
obj-$(CONFIG_KIRKWOOD_GPIO)+= kw_gpio.o
obj-$(CONFIG_KONA_GPIO)+= kona_gpio.o
obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o
diff --git a/drivers/gpio/iproc_gpio.c b/drivers/gpio/iproc_gpio.c
new file mode 100644
index 00..ca6287d7f5
--- /dev/null
+++ b/drivers/gpio/iproc_gpio.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Broadcom
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * There are five GPIO bank register. Each bank can configure max of 32 gpios.
+ * BANK0 - gpios 0 to 31
+ * BANK1 - gpios 32 to 63
+ * BANK2 - gpios 64 to 95
+ * BANK3 - gpios 96 to 127
+ * BANK4 - gpios 128 to 150
+ *
+ * Offset difference between consecutive bank register is 0x200
+ */
+#define IPROC_GPIO_PER_BANK 32
+#define IPROC_GPIO_SHIFT(n) ((n) % IPROC_GPIO_PER_BANK)
+#define IPROC_GPIO_BANK_OFFSET(n) (0x200 * ((n) / IPROC_GPIO_PER_BANK))
+#define IPROC_GPIO_REG(pin, reg)(IPROC_GPIO_BANK_OFFSET(pin) + (reg))
+
+#define IPROC_GPIO_DATA_IN_OFFSET 0x00
+#define IPROC_GPIO_DATA_OUT_OFFSET 0x04
+#define IPROC_GPIO_OUT_EN_OFFSET0x08
+
+struct iproc_gpio_pctrl_map {
+ u32 gpio_pin;
+ u32 pctrl_pin;
+ u32 npins;
+ struct list_head node;
+};
+
+struct iproc_gpio_platdata {
+ struct udevice *pinctrl_dev;
+ struct list_head gpiomap;
+ /* register base for this bank */
+ void __iomem *base;
+ char *name;
+ u32 ngpios;
+};
+
+/**
+ * iproc_gpio_set_bit - set or clear one bit (corresponding to the GPIO pin)
+ * in a iproc GPIO register
+ *
+ * @iproc_gpio: Iproc GPIO device
+ * @reg: register offset
+ * @gpio: GPIO pin
+ * @set: set or clear
+ */
+static inline void iproc_gpio_set_bit(struct iproc_gpio_platdata *plat,
+ u32 reg,
+ u32 gpio, bool set)
+{
+ u32 offset = IPROC_GPIO_REG(gpio, reg);
+ u32 shift = IPROC_GPIO_SHIFT(gpio);
+ u32 val;
+
+ val = readl(plat->base + offset);
+ if (set)
+ val |= BIT(shift);
+ else
+ val &= ~BIT(shift);
+ writel(val, plat->base + offset);
+}
+
+static inline bool iproc_gpio_get_bit(struct iproc_gpio_platdata *plat,
+ u32 reg,
+ u32 gpio)
+{
+ u32 offset = IPROC_GPIO_REG(gpio, reg);
+ u32 shift = IPROC_GPIO_SHIFT(gpio);
+
+ return !!(readl(plat->base + offset) & BIT(shift));
+}
+
+static u32 iproc_get_pctrl_from_gpio(struct iproc_gpio_platdata *plat, u32
gpio)
+{
+ struct iproc_gpio_pctrl_map *range = NULL;
+ struct list_head *pos, *tmp;
+ u32 ret = 0;
+
+ list_for_each_safe(pos, tmp, >gpiomap) {
+ range = list_entry(pos, struct iproc_gpio_pctrl_map, node);
+ if (gpio == range->gpio_pin ||
+ (gpio < (range->gpio_pin + range->npins))) {
+ ret = (range->pctrl_pin + (gpio - range->gpio_pin));
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int iproc_get_gpio_pctrl_mapping(struct udevice *dev)
+{
+ struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+ struct iproc_gpio_pctrl_map *range = NULL;
+ struct fdtd
Re: [U-Boot] [PATCH v1 1/1] cmd: adding malloc, math, and strcmp commands to u-boot
Hi Tom,
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Tuesday, November 19, 2019 12:38 PM
> To: Vladimir Olovyannikov
> Cc: u-boot@lists.denx.de; Suji Velupiallai
;
> Heinrich Schuchardt
> Subject: Re: [U-Boot] [PATCH v1 1/1] cmd: adding malloc, math, and
strcmp
> commands to u-boot
>
> On Mon, Nov 18, 2019 at 04:26:30PM -0800, Vladimir Olovyannikov wrote:
>
> > cmd: adding malloc, math, and strcmp u-boot commands.
> > - malloc supports allocation of heap memory and free allocated memory
> > via u-boot command line.
>
> Can you expand on how this is used in a script? I'm not sure I see that
> exactly.
I am upstreaming the new bcm platform. Here is an excerpt from the script
which uses
these:
#define SD_UPDATE \
"sd_update="\
"if malloc tmp 2000; then "\
"else "\
"echo [sd_update] malloc 2000 bytes ** FAILED **;"\
"exit;"\
"fi;"\
"if fatload mmc ${sd_device_number} ${tmp} "\
"${sd_update_prefix}.sd-update; then "\
"else "\
"echo [sd_update] fatload ${sd_update_prefix}.sd-update "\
"** FAILED **;"\
"exit;"\
"fi;"\
"if source ${tmp}; then "\
"else "\
"echo [sd_update] Executing script ** FAILED **;"\
"exit;"\
"fi;"\
"if free tmp; then "\
"else " \
"echo [sd_update] free 2000 bytes ** FAILED **;"\
"exit;"\
"fi \0"
;
"if math add filesize filesize 1FF; then "\
"else "\
"echo [mmc_flash_image_rsa] math add command ** FAILED
**;"\
"exit;"\
"fi;"\
"if math div fileblocks filesize 200; then "\
"else "\
"echo [mmc_flash_image_rsa] math div command ** FAILED
**;"\
"exit;"\
"fi;"\
> Also:
> > +config CMD_MALLOC
> > + bool "malloc"
> > + default y
> > + help
> > + Supports allocation of heap memory and free allocated memory
> commands.
> > + These commands are used by u-boot scripts.
> > +
> > +config CMD_MATH
> > + bool "math"
> > + default y
> > + help
> > + Provides math commands such as add, sub, mul, div, shift,
> > + convert decimal to hex functionalities to be available in the
script.
>
> First, why do we need this, rather than using setexpr ?
I agree, the platform needs to use setexpr as it contains all math
operations.
>
> > +
> > config CMD_SOURCE
> > bool "source"
> > default y
> > @@ -1301,6 +1315,13 @@ config CMD_SETEXPR
> > Also supports loading the value at a memory location into a
variable.
> > If CONFIG_REGEX is enabled, setexpr also supports a gsub
function.
> >
> > +config CMD_STRCMP
> > + bool "strcmp"
> > + default y
> > + help
> > + Provides string compare command feature to u-boot scripts.
>
> Second, new commands must not default to y, but they should be enabled
> on sandbox and new test.py tests added for them. Thanks!
OK, thank you.
Is there an example/doc on how to enable these on sandbox and to provide
tests?
Vladimir
>
> --
> Tom
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Re: [U-Boot] [PATCH v1 1/1] cmd: adding malloc, math, and strcmp commands to u-boot
Hi Simon,
Thank you for reviewing. I will split the patch as you suggested, and
resubmit.
Vladimir
> -Original Message-
> From: Simon Glass [mailto:s...@chromium.org]
> Sent: Monday, November 18, 2019 5:21 PM
> To: Vladimir Olovyannikov
> Cc: U-Boot Mailing List ; Heinrich Schuchardt
> ; Suji Velupiallai
> Subject: Re: [PATCH v1 1/1] cmd: adding malloc, math, and strcmp commands
> to u-boot
>
> Hi Vladimir,
>
> On Mon, 18 Nov 2019 at 16:27, Vladimir Olovyannikov
> wrote:
> >
> > cmd: adding malloc, math, and strcmp u-boot commands.
>
> U-Boot
>
> > - malloc supports allocation of heap memory and free allocated memory
> > via u-boot command line.
>
> U-Boot (please fix globally)
>
> > - mathprovides math commands such as "add", "sub", "mul", "div",
> > "shift", ability to convert dec->hex.
> > - strcmp provides string compare command feature for a script.
> >
> > All these commands are introduced to be used in u-boot scripts.
> >
> > Signed-off-by: Suji Velupiallai
> > Signed-off-by: Vladimir Olovyannikov
> >
> > ---
> > cmd/Kconfig | 21 ++
> > cmd/Makefile | 4 +++
> > cmd/malloc.c | 54
> > cmd/math.c | 78
>
> > cmd/strcmp.c | 28 +++
> > 5 files changed, 185 insertions(+)
> > create mode 100644 cmd/malloc.c
> > create mode 100644 cmd/math.c
> > create mode 100644 cmd/strcmp.c
> >
> > diff --git a/cmd/Kconfig b/cmd/Kconfig index cf982ff65e..f11903fe3d
> > 100644
> > --- a/cmd/Kconfig
> > +++ b/cmd/Kconfig
> > @@ -1286,6 +1286,20 @@ config CMD_ITEST
> > help
> > Return true/false on integer compare.
> >
> > +config CMD_MALLOC
> > + bool "malloc"
> > + default y
> > + help
> > + Supports allocation of heap memory and free allocated memory
> commands.
> > + These commands are used by u-boot scripts.
> > +
> > +config CMD_MATH
> > + bool "math"
> > + default y
> > + help
> > + Provides math commands such as add, sub, mul, div, shift,
> > + convert decimal to hex functionalities to be available in the
> > script.
> > +
> > config CMD_SOURCE
> > bool "source"
> > default y
> > @@ -1301,6 +1315,13 @@ config CMD_SETEXPR
> > Also supports loading the value at a memory location into a
> > variable.
> > If CONFIG_REGEX is enabled, setexpr also supports a gsub
> > function.
>
> I think this would be better as three patches.
>
> >
> > +config CMD_STRCMP
> > + bool "strcmp"
> > + default y
> > + help
> > + Provides string compare command feature to u-boot scripts.
>
> U-Boot
>
> > +
> > +
> > endmenu
> >
> > menu "Android support commands"
> > diff --git a/cmd/Makefile b/cmd/Makefile index 2d723ea0f0..942d60a0a2
> > 100644
> > --- a/cmd/Makefile
> > +++ b/cmd/Makefile
> > @@ -164,6 +164,10 @@ obj-$(CONFIG_CMD_GPT) += gpt.o
> > obj-$(CONFIG_CMD_ETHSW) += ethsw.o
> > obj-$(CONFIG_CMD_AXI) += axi.o
> >
> > +obj-$(CONFIG_CMD_MALLOC) += malloc.o
> > +obj-$(CONFIG_CMD_MATH) += math.o
> > +obj-$(CONFIG_CMD_STRCMP) += strcmp.o
> > +
> > # Power
> > obj-$(CONFIG_CMD_PMIC) += pmic.o
> > obj-$(CONFIG_CMD_REGULATOR) += regulator.o diff --git a/cmd/malloc.c
> > b/cmd/malloc.c new file mode 100644 index 00..e11e030a59
> > --- /dev/null
> > +++ b/cmd/malloc.c
> > @@ -0,0 +1,54 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 Broadcom
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +static unsigned long get_value(const char *val)
>
> Needs a comment
>
> > +{
> > + char *env = env_get((char *)val);
> > +
> > + if (env)
> > + return simple_strtoul(env, NULL, 16);
> > + else
> > + return simple_strtoul(val, NULL, 16); }
> > +
> > +static int do_malloc(cmd_tbl_t *cmdtp, int flag, int argc, char
> > +*const argv[]) {
> > + char numberbuf[32];
> > + void *mem;
>
> const?
>
> > +
> > + if (argc <
[U-Boot] [PATCH 2/2] common: Add DDR error logging (ELOG) support for Broadcom boards
From: Sheetal Tigadoli
Allow ELOG to use DDR for logging.
Signed-off-by: Sheetal Tigadoli
Signed-off-by: Vladimir Olovyannikov
---
common/Kconfig | 8
common/Makefile| 1 +
common/bcm_elog.c | 49 ++
common/console.c | 22 +
include/bcm_elog.h | 37 ++
5 files changed, 117 insertions(+)
create mode 100644 common/bcm_elog.c
create mode 100644 include/bcm_elog.h
diff --git a/common/Kconfig b/common/Kconfig
index d9ecf79e0a..f78296ec63 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -632,6 +632,14 @@ config SYS_STDIO_DEREGISTER
removed (for example a USB keyboard) then this option can be
enabled to ensure this is handled correctly.
+config BCM_ELOG
+ bool "Broadcom error logging support"
+ default n
+ help
+ Enables broadcom error logging support to be used with brcm
+ platforms, say Y to this option to enable the logging support.
+ If unsure, say N.
+
endmenu
menu "Logging"
diff --git a/common/Makefile b/common/Makefile
index 302d8beaf3..5f1338f281 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -95,6 +95,7 @@ else
obj-$(CONFIG_SPL_SERIAL_SUPPORT) += console.o
endif
else
+obj-$(CONFIG_BCM_ELOG) += bcm_elog.o
obj-y += console.o
endif # CONFIG_SPL_BUILD
diff --git a/common/bcm_elog.c b/common/bcm_elog.c
new file mode 100644
index 00..9f51636b24
--- /dev/null
+++ b/common/bcm_elog.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Broadcom
+ */
+
+#include
+
+/* Log one character */
+int log2ddr(const char ch)
+{
+ u32 offset, len;
+ uintptr_t base = BCM_ELOG_UBOOT_BASE;
+
+ offset = readl(base + BCM_ELOG_OFF_OFFSET);
+ len = readl(base + BCM_ELOG_LEN_OFFSET);
+ writeb(ch, base + offset);
+ offset++;
+
+ /* log buffer is now full and need to wrap around */
+ if (offset >= BCM_ELOG_UBOOT_SIZE)
+ offset = BCM_ELOG_HEADER_LEN;
+
+ /* only increment length when log buffer is not full */
+ if (len < BCM_ELOG_UBOOT_SIZE - BCM_ELOG_HEADER_LEN)
+ len++;
+
+ writel(offset, base + BCM_ELOG_OFF_OFFSET);
+ writel(len, base + BCM_ELOG_LEN_OFFSET);
+
+ return 0;
+}
+
+/* Routine to initialize error logging */
+void bcm_elog_init(uintptr_t base, u32 size)
+{
+ u32 val;
+
+ /*
+* If a valid signature is found, it means logging is already
+* initialize. In this case, we should not re-initialize the entry
+* header in the designated memory
+*/
+ val = readl(base + BCM_ELOG_SIG_OFFSET);
+ if (val != BCM_ELOG_SIG_VAL) {
+ writel(base + BCM_ELOG_SIG_OFFSET, BCM_ELOG_SIG_VAL);
+ writel(base + BCM_ELOG_OFF_OFFSET, BCM_ELOG_HEADER_LEN);
+ writel(base + BCM_ELOG_LEN_OFFSET, 0);
+ }
+}
diff --git a/common/console.c b/common/console.c
index 168ba60d0d..25ebd6e431 100644
--- a/common/console.c
+++ b/common/console.c
@@ -20,6 +20,10 @@
#include
#include
+#ifdef CONFIG_BCM_ELOG
+#include
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
static int on_console(const char *name, const char *value, enum env_op op,
@@ -536,6 +540,9 @@ void putc(const char c)
if (!gd->have_console)
return pre_console_putc(c);
+#ifdef CONFIG_BCM_ELOG
+ log2ddr(c);
+#endif
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
fputc(stdout, c);
@@ -587,6 +594,17 @@ void puts(const char *s)
if (!gd->have_console)
return pre_console_puts(s);
+#ifdef CONFIG_BCM_ELOG
+ {
+ const char *tmp = s;
+
+ while (*tmp) {
+ int c = *tmp++;
+
+ log2ddr(c);
+ }
+ }
+#endif
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
fputs(stdout, s);
@@ -776,6 +794,10 @@ int console_init_f(void)
print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT1_SERIAL);
+#ifdef CONFIG_BCM_ELOG
+ bcm_elog_init(BCM_ELOG_UBOOT_BASE, BCM_ELOG_UBOOT_SIZE);
+#endif
+
return 0;
}
diff --git a/include/bcm_elog.h b/include/bcm_elog.h
new file mode 100644
index 00..62352bf5a3
--- /dev/null
+++ b/include/bcm_elog.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Broadcom
+ *
+ */
+
+#ifndef __BCM_ELOG_H__
+#define __BCM_ELOG_H__
+
+#include
+#include
+
+/* Default AP error logging base address */
+#ifndef ELOG_AP_UART_LOG_BASE
+#define ELOG_AP_UART_LOG_BASE 0x8f11
+#endif
+
+/* Reserve 16K to store error logs */
+#define BCM_ELOG_UBOOT_BASEELOG_AP_UART_LOG_BASE
+#define BCM_ELOG_UBOOT_SIZE0x4000
+
+/* error logging signature */
+#define BCM_ELOG_SIG_OFFSET0x0
[U-Boot] [PATCH 1/2] cmd: bcm: logsetup: Add Broadcom error log setup command
Some Broadcom platforms have ability to record event logs
by SCP.
Add a logsetup command which is used to perform initial
configuration of this log and move the command to
bcm/ directory to be used for Broadcom-specific
U-boot commands.
Signed-off-by: Vladimir Olovyannikov
---
cmd/Kconfig| 2 +
cmd/Makefile | 2 +
cmd/bcm/Kconfig| 12 ++
cmd/bcm/Makefile | 4 +
cmd/bcm/elog.h | 64 +++
cmd/bcm/logsetup.c | 433 +
6 files changed, 517 insertions(+)
create mode 100644 cmd/bcm/Kconfig
create mode 100644 cmd/bcm/Makefile
create mode 100644 cmd/bcm/elog.h
create mode 100644 cmd/bcm/logsetup.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index cf982ff65e..c13998887f 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2119,4 +2119,6 @@ config CMD_UBIFS
help
UBIFS is a file system for flash devices which works on top of UBI.
+source cmd/bcm/Kconfig
+
endmenu
diff --git a/cmd/Makefile b/cmd/Makefile
index 2d723ea0f0..ae38bea901 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -183,6 +183,8 @@ endif # !CONFIG_SPL_BUILD
# core command
obj-y += nvedit.o
+obj-$(CONFIG_CMD_BCM_EXT_UTILS) += bcm/
+
obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/
filechk_data_gz = (echo "static const char data_gz[] ="; cat $< |
scripts/bin2c; echo ";")
diff --git a/cmd/bcm/Kconfig b/cmd/bcm/Kconfig
new file mode 100644
index 00..189a45004e
--- /dev/null
+++ b/cmd/bcm/Kconfig
@@ -0,0 +1,12 @@
+menu "Broadcom Extended Utilities"
+
+config CMD_BCM_LOGSETUP
+ bool "Command to setup logging on Broadcom boards"
+ depends on TARGET_BCMNS3
+ default n
+ help
+ Support specific log setup on Broadcom SoCs. This command
+ allows checking if logging support is present, and update
+ log sections.
+
+endmenu
diff --git a/cmd/bcm/Makefile b/cmd/bcm/Makefile
new file mode 100644
index 00..c5ae924ea0
--- /dev/null
+++ b/cmd/bcm/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2019 Broadcom
+
+obj-$(CONFIG_CMD_BCM_LOGSETUP) += logsetup.o
diff --git a/cmd/bcm/elog.h b/cmd/bcm/elog.h
new file mode 100644
index 00..51317ac578
--- /dev/null
+++ b/cmd/bcm/elog.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom
+ */
+
+#ifndef __ELOG_H__
+#define __ELOG_H__
+
+#define GLOBAL_META_HDR_SIG0x45524c47
+#define MAX_REC_COUNT 13
+#define MAX_REC_FORMAT 1
+#define MAX_SRC_TYPE 3
+#define MAX_NVM_TYPE 3
+/* A special type. Use defaults specified in CRMU config */
+#define NVM_DEFAULT0xff
+
+/* Max. number of cmd parameters per elog spec */
+#define PARAM_COUNT3
+
+#define REC_DESC_LENGTH8
+
+enum {
+ LOG_SETUP_CMD_VALIDATE_META,
+ LOG_SETUP_CMD_WRITE_META,
+ LOG_SETUP_CMD_ERASE,
+ LOG_SETUP_CMD_READ,
+ LOG_SETUP_CMD_CHECK
+};
+
+#pragma pack(push, 1)
+
+struct meta_record {
+ u8 record_type;
+ u8 record_format;
+ u8 src_mem_type;
+ u8 alt_src_mem_type;
+ u8 nvm_type;
+ char rec_desc[REC_DESC_LENGTH];
+ u64 src_mem_addr;
+ u64 alt_src_mem_addr;
+ u64 rec_addr;
+ u32 rec_size;
+ u32 sector_size;
+ u8 padding[3];
+};
+
+struct global_header {
+ u32 signature;
+ u32 sector_size;
+ u8 revision;
+ u8 rec_count;
+ u16 padding;
+};
+
+struct log_setup {
+ u32 cmd;
+ u32 params[PARAM_COUNT];
+ u32 result;
+ u32 ret_code;
+};
+
+#pragma pack(pop)
+
+#endif
diff --git a/cmd/bcm/logsetup.c b/cmd/bcm/logsetup.c
new file mode 100644
index 00..220518f884
--- /dev/null
+++ b/cmd/bcm/logsetup.c
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom
+ */
+
+/*
+ * Create a binary file ready to be flashed
+ * as a global meta for logging, from a source file.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "elog.h"
+
+#define FILE_LINE_BUF_SIZE 1024
+#define GLOBAL_PARAM_COUNT 3
+#define REC_PARAM_COUNT11
+
+#define GLOBAL_NAME"GLOBAL"
+#define RECORD_NAME"RECORD"
+
+#define MCU_IPC_MCU_CMD_ELOG_SETUP 0x84
+/* SPI write operations can be slow */
+#define DEFAULT_TIMEOUT_MS 1
+
+#define MCU_IPC_CMD_DONE_MASK 0x8000
+#define MCU_IPC_CMD_REPLY_MASK 0x3fff
+#define MCU_IPC_CMD_REPLY_SHIFT16
+
+#define MIN_ARGS_COUNT 3
+#define MAX_ARGS_COUNT 5
+#define SEP_STR","
+#define SUPPORTED_CMD "-s"
+#define CHK_HDR_CMD"-c"
+
+enum {
+ PARAM_GLOBAL,
+ PARAM_REC
+};
+
+static uintptr_t crmu_mbox0_address;
+
+/*
+ * Send a logging command to MCU patch for execution.
+ *
+ * Parameters:
+ * cmd:
[U-Boot] [PATCH INTERNAL v1 0/2] Add error logging support for Broadcom boards
Some Broadcom platforms have ability to record event/error logs (ELOGs) by SCP. This patch series adds such support: 1. logsetup command which is used to perform initial setup of ELOG. 2. Add support to use DDR as a runtime ELOG storage Sheetal Tigadoli (1): common: Add DDR error logging (ELOG) support for Broadcom boards Vladimir Olovyannikov (1): cmd: bcm: logsetup: Add Broadcom error log setup command cmd/Kconfig| 2 + cmd/Makefile | 2 + cmd/bcm/Kconfig| 12 ++ cmd/bcm/Makefile | 4 + cmd/bcm/elog.h | 64 +++ cmd/bcm/logsetup.c | 433 + common/Kconfig | 8 + common/Makefile| 1 + common/bcm_elog.c | 49 + common/console.c | 22 +++ include/bcm_elog.h | 37 11 files changed, 634 insertions(+) create mode 100644 cmd/bcm/Kconfig create mode 100644 cmd/bcm/Makefile create mode 100644 cmd/bcm/elog.h create mode 100644 cmd/bcm/logsetup.c create mode 100644 common/bcm_elog.c create mode 100644 include/bcm_elog.h -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 1/1] cmd: pxe: Fix bootm argument count
From: Abhishek Shah
pxe command parses the init ramfs address(through initrd lable in
pxe config file), but is not passing it to bootm command as argument
as bootm_argc count is not increased.
Signed-off-by: Abhishek Shah
Signed-off-by: Vladimir Olovyannikov
---
cmd/pxe.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/pxe.c b/cmd/pxe.c
index 2059975446..768e50aba6 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -663,6 +663,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label
*label)
strncpy(bootm_argv[2], env_get("ramdisk_addr_r"), 18);
strcat(bootm_argv[2], ":");
strncat(bootm_argv[2], env_get("filesize"), 9);
+ bootm_argc = 3;
}
if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) {
--
2.17.1
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[U-Boot] [PATCH v1 1/1] cmd: adding malloc, math, and strcmp commands to u-boot
cmd: adding malloc, math, and strcmp u-boot commands.
- malloc supports allocation of heap memory and free allocated memory
via u-boot command line.
- mathprovides math commands such as "add", "sub", "mul", "div",
"shift", ability to convert dec->hex.
- strcmp provides string compare command feature for a script.
All these commands are introduced to be used in u-boot scripts.
Signed-off-by: Suji Velupiallai
Signed-off-by: Vladimir Olovyannikov
---
cmd/Kconfig | 21 ++
cmd/Makefile | 4 +++
cmd/malloc.c | 54
cmd/math.c | 78
cmd/strcmp.c | 28 +++
5 files changed, 185 insertions(+)
create mode 100644 cmd/malloc.c
create mode 100644 cmd/math.c
create mode 100644 cmd/strcmp.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index cf982ff65e..f11903fe3d 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1286,6 +1286,20 @@ config CMD_ITEST
help
Return true/false on integer compare.
+config CMD_MALLOC
+ bool "malloc"
+ default y
+ help
+ Supports allocation of heap memory and free allocated memory commands.
+ These commands are used by u-boot scripts.
+
+config CMD_MATH
+ bool "math"
+ default y
+ help
+ Provides math commands such as add, sub, mul, div, shift,
+ convert decimal to hex functionalities to be available in the script.
+
config CMD_SOURCE
bool "source"
default y
@@ -1301,6 +1315,13 @@ config CMD_SETEXPR
Also supports loading the value at a memory location into a variable.
If CONFIG_REGEX is enabled, setexpr also supports a gsub function.
+config CMD_STRCMP
+ bool "strcmp"
+ default y
+ help
+ Provides string compare command feature to u-boot scripts.
+
+
endmenu
menu "Android support commands"
diff --git a/cmd/Makefile b/cmd/Makefile
index 2d723ea0f0..942d60a0a2 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -164,6 +164,10 @@ obj-$(CONFIG_CMD_GPT) += gpt.o
obj-$(CONFIG_CMD_ETHSW) += ethsw.o
obj-$(CONFIG_CMD_AXI) += axi.o
+obj-$(CONFIG_CMD_MALLOC) += malloc.o
+obj-$(CONFIG_CMD_MATH) += math.o
+obj-$(CONFIG_CMD_STRCMP) += strcmp.o
+
# Power
obj-$(CONFIG_CMD_PMIC) += pmic.o
obj-$(CONFIG_CMD_REGULATOR) += regulator.o
diff --git a/cmd/malloc.c b/cmd/malloc.c
new file mode 100644
index 00..e11e030a59
--- /dev/null
+++ b/cmd/malloc.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static unsigned long get_value(const char *val)
+{
+ char *env = env_get((char *)val);
+
+ if (env)
+ return simple_strtoul(env, NULL, 16);
+ else
+ return simple_strtoul(val, NULL, 16);
+}
+
+static int do_malloc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ char numberbuf[32];
+ void *mem;
+
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
+ mem = memalign(ARCH_DMA_MINALIGN, get_value(argv[2]));
+ if (mem) {
+ sprintf(numberbuf, "%08x", (unsigned int)mem);
+ env_set(argv[1], numberbuf);
+ return 0;
+ }
+ return -EINVAL;
+}
+
+static int do_free(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ free((void *)get_value(argv[1]));
+ env_set(argv[1], "");
+ return 0;
+}
+
+U_BOOT_CMD(malloc, 3, 0, do_malloc,
+ "Allocate memory from u-boot heap and store pointer in environment
variable.",
+ "target size\n");
+
+U_BOOT_CMD(free, 2, 0, do_free,
+ "Release memory from u-boot heap at target.", "target\n");
diff --git a/cmd/math.c b/cmd/math.c
new file mode 100644
index 00..17de5ef70b
--- /dev/null
+++ b/cmd/math.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2017 Broadcom
+ */
+
+#include
+#include
+#include
+
+unsigned long long simple_strtoull(const char *cp, char **endp,
+ unsigned int base);
+
+static unsigned long long get_value(const char *val)
+{
+ char *env = env_get((char *)val);
+
+ if (env)
+ return simple_strtoull(env, NULL, 16);
+ else
+ return simple_strtoull(val, NULL, 16);
+}
+
+static unsigned long long get_value_base10(const char *val)
+{
+ char *env = env_get((char *)val);
+
+ if (env)
+ return simple_strtoull(env, NULL, 10);
+ else
+ return simple_strtoull(val, NULL, 10);
+}
+
+/*
+ * Top level addenv command
+ */
+#define IS_MATH_CMD(cmd, args) ((strcmp(argv[1], cmd) == 0) && \
+
