[PATCH v2 2/2] arm: imx9: Call imx9_probe_mu for DM post in board_r
This event callback imx9_probe_mu needs to be called in board_r
as well, because many ELE APIs depending on this MU probed
Signed-off-by: Ye Li
---
No changes in v2
arch/arm/mach-imx/imx9/soc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f06339f..15e87b8 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -622,6 +622,7 @@ int imx9_probe_mu(void)
return 0;
}
EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu);
int timer_init(void)
{
--
2.7.4
[PATCH v2 1/2] arm: imx9: Correct imx9_probe_mu prototype
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
Changes in v2:
Fix imx93_var_som and phycore_imx93 as well
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
board/phytec/phycore_imx93/spl.c| 2 +-
board/variscite/imx93_var_som/spl.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/mu.h
b/arch/arm/include/asm/arch-imx9/mu.h
index b860499..649b8a6 100644
--- a/arch/arm/include/asm/arch-imx9/mu.h
+++ b/arch/arm/include/asm/arch-imx9/mu.h
@@ -8,6 +8,6 @@
#include
-int imx9_probe_mu(void *ctx, struct event *event);
+int imx9_probe_mu(void);
#endif
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 2fd5559..7331a20 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init Sentinel API\n");
} else {
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 16303fc..f03bfee 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -122,7 +122,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
diff --git a/board/variscite/imx93_var_som/spl.c
b/board/variscite/imx93_var_som/spl.c
index 36e1721..71f346c 100644
--- a/board/variscite/imx93_var_som/spl.c
+++ b/board/variscite/imx93_var_som/spl.c
@@ -121,7 +121,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
--
2.7.4
[PATCH v2] arm: imx9: Correct imx9_probe_mu prototype
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
Changes in v2:
Fix imx93_var_som and phycore_imx93 as well
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
board/phytec/phycore_imx93/spl.c| 2 +-
board/variscite/imx93_var_som/spl.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/mu.h
b/arch/arm/include/asm/arch-imx9/mu.h
index b860499..649b8a6 100644
--- a/arch/arm/include/asm/arch-imx9/mu.h
+++ b/arch/arm/include/asm/arch-imx9/mu.h
@@ -8,6 +8,6 @@
#include
-int imx9_probe_mu(void *ctx, struct event *event);
+int imx9_probe_mu(void);
#endif
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 2fd5559..7331a20 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init Sentinel API\n");
} else {
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 16303fc..f03bfee 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -122,7 +122,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
diff --git a/board/variscite/imx93_var_som/spl.c
b/board/variscite/imx93_var_som/spl.c
index 36e1721..71f346c 100644
--- a/board/variscite/imx93_var_som/spl.c
+++ b/board/variscite/imx93_var_som/spl.c
@@ -121,7 +121,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
--
2.7.4
[PATCH] net: fec_mxc: Avoid enable regulator failure
Change to regulator_set_enable_if_allowed to avoid enable failure,
in case same phy supply shared by multiple FEC controllers.
Signed-off-by: Ye Li
---
drivers/net/fec_mxc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ac93767..90af18f 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1310,7 +1310,7 @@ static int fecmxc_probe(struct udevice *dev)
#ifdef CONFIG_DM_REGULATOR
if (priv->phy_supply) {
- ret = regulator_set_enable(priv->phy_supply, true);
+ ret = regulator_set_enable_if_allowed(priv->phy_supply, true);
if (ret) {
printf("%s: Error enabling phy supply\n", dev->name);
return ret;
--
2.7.4
[PATCH] arm: imx: Fix incorrect return value
The spl_spi_get_uboot_offs weak function is defined unsigned int.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/image-container.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/image-container.c
b/arch/arm/mach-imx/image-container.c
index c9455fe..35da0ae 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -262,7 +262,7 @@ static int get_imageset_end(void *dev, int dev_type)
}
#ifdef CONFIG_SPL_SPI_LOAD
-unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash)
+unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
{
int end;
--
2.7.4
[PATCH] thermal: imx_tmu: Fix TMU error on iMX8MQ
imx_tmu_arch_init does not implement for iMX8MQ, error is returned
Signed-off-by: Ye Li
---
drivers/thermal/imx_tmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index 4721cfb..ca775e5 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -402,6 +402,7 @@ static inline void imx_tmu_mx8mp_init(struct udevice *dev)
{ }
#endif
static inline void imx_tmu_mx93_init(struct udevice *dev) { }
+static inline void imx_tmu_mx8mq_init(struct udevice *dev) { }
static void imx_tmu_arch_init(struct udevice *dev)
{
@@ -411,6 +412,8 @@ static void imx_tmu_arch_init(struct udevice *dev)
imx_tmu_mx8mp_init(dev);
else if (is_imx93())
imx_tmu_mx93_init(dev);
+ else if (is_imx8mq())
+ imx_tmu_mx8mq_init(dev);
else
dev_err(dev, "Unsupported SoC, TMU calibration not loaded!\n");
}
--
2.7.4
[PATCH] arm: imx9: Fix MMU map table overlap
The size for flexspi AHB buffer space is wrong, so correct it.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx9/soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 15e87b8..2117489 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -262,7 +262,7 @@ static struct mm_region imx93_mem_map[] = {
/* Flexible Serial Peripheral Interface */
.virt = 0x2800UL,
.phys = 0x2800UL,
- .size = 0x3000UL,
+ .size = 0x0800UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
--
2.7.4
[PATCH 2/2] arm: imx9: Call imx9_probe_mu for DM post in board_r
This event callback imx9_probe_mu needs to be called in board_r
as well, because many ELE APIs depending on this MU probed
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx9/soc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f06339f..15e87b8 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -622,6 +622,7 @@ int imx9_probe_mu(void)
return 0;
}
EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu);
int timer_init(void)
{
--
2.7.4
[PATCH 1/2] arm: imx9: Correct imx9_probe_mu prototype
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/mu.h
b/arch/arm/include/asm/arch-imx9/mu.h
index b860499..649b8a6 100644
--- a/arch/arm/include/asm/arch-imx9/mu.h
+++ b/arch/arm/include/asm/arch-imx9/mu.h
@@ -8,6 +8,6 @@
#include
-int imx9_probe_mu(void *ctx, struct event *event);
+int imx9_probe_mu(void);
#endif
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 2fd5559..7331a20 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init Sentinel API\n");
} else {
--
2.7.4
[PATCH] arm: imx: imx8m: Enable the SError exception
To work with commit 2f3c920(imx8m: workaround ROM serror), we need to enable the SError exception and install vector in SPL. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8m/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 67da198..88ef732 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -11,14 +11,17 @@ config IMX8MQ bool select IMX8M select CLK_IMX8MQ + select ARMV8_SPL_EXCEPTION_VECTORS config IMX8MM bool select IMX8M + select ARMV8_SPL_EXCEPTION_VECTORS config IMX8MN bool select IMX8M + select ARMV8_SPL_EXCEPTION_VECTORS config IMX8MP bool -- 2.7.4
RE: [EXT] AW: FIELD_RETURN on i.MX8MNANOLPD4 EVK
Hi Thomas, It is due to ARMV8_SPL_EXCEPTION_VECTORS not enabled by default in upstream. I will send a patch Best regards, Ye Li > -Original Message- > From: Thomas Schaefer > Sent: Thursday, January 11, 2024 9:40 PM > To: Ye Li ; Peng Fan (OSS) ; > 'u-boot@lists.denx.de' > Cc: Peng Fan > Subject: [EXT] AW: FIELD_RETURN on i.MX8MNANOLPD4 EVK > > Caution: This is an external email. Please take care when clicking links or > opening attachments. When in doubt, report the message using the 'Report this > email' button > > > Hi Ye, > > Yes, I can boot SPL without signature. I also added some debug messages to my > build and I can see that SPL can load u-boot proper via USB until 'Jumping to > U-Boot' message in board_init_r function (common/spl/spl.c) > > Actually this looks like the SError problem caused by errata ERR050350 which > has been worked around in patch 2f3c92060dcd. But that patch is currently > active in u-boot and so I don't understand what the problem is here in this > case. > > Best regards, > Thomas > > -Ursprüngliche Nachricht- > Von: Ye Li > Gesendet: Donnerstag, 11. Januar 2024 05:09 > An: Peng Fan (OSS) ; Thomas Schaefer > ; 'u-boot@lists.denx.de' > > Cc: Peng Fan > Betreff: RE: FIELD_RETURN on i.MX8MNANOLPD4 EVK > > [You don't often get email from ye...@nxp.com. Learn why this is important at > https://aka.ms/LearnAboutSenderIdentification ] > > I think there is no particular SW support needed for FIELD_RETURN on 8MN. > From what you described, you have moved the part from closed to > FIELD_RETURN. So are you able to boot into SPL without signature? > > Best regards, > Ye Li > > -Original Message- > > From: Peng Fan (OSS) > > Sent: Thursday, January 11, 2024 11:51 AM > > To: Thomas Schäfer ; 'u-boot@lists.denx.de' > > ; Ye Li > > Cc: Peng Fan > > Subject: Re: FIELD_RETURN on i.MX8MNANOLPD4 EVK > > > > +Ye > > > > 在 1/9/2024 4:52 PM, Thomas Schaefer 写道: > > > Hi all, > > > > > > We are trying to enable FIELD RETURN on the NXP i.MX8MNano LPD4 EVK > > board. > > > > > > We enabled Secure Boot in u-boot in the first step. After checking > > > proper > > execution of a signed bootloader image we closed the board blowing the > > SEC_CONFIG fuse. > > > > > > In the next step we created the board specific signature with UID of > > > the CPU > > included to remove the FIELD RETURN lock. After that we were able to > > blow the FIELD_RETURN fuse with 'fuse prog 8 3 0x1' command. But now, > > the board cannot boot any more, it will hang after execution of the SPL > bootloader part. > > > > > > We can observe this behavior with both signed and unsigned > > > bootloader > > images. > > > > > > Is the FIELD_RETURN feature for the i.MX8MNano supported with u-boot > > v2024.01? > > > > > > Best regards, > > > Thomas > > > > > > > > > Thomas Schäfer > > > SW Design Engineer > > > > > > thomas.schae...@kontron.com > > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww > > > %2F=05%7C02%7Cye.li%40nxp.com%7C060b2d6efc44474f6b6308dc1 > 2aad3c > > > > 8%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6384057721301942 > 54%7C > > > > Unknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6 > Ik > > > > 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C=TH13JrjA5cjqAeIfRAvx > 2Ss1l > > > 4iHQ7Yvbs%2FuQyKrY%2BQ%3D=0 > > > .kontron.com%2F=05%7C02%7Cthomas.schaefer%40kontron.com%7 > C7eb38 > > > > f57a0304f030f2f08dc125b1c74%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0 > %7 > > > > C0%7C638405429733492095%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj > AwMDAi > > > > LCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C > ata > > > > =nOuWb2NSpPBRl5FaV8xa5MiQZ%2FzE7z8F%2FC2Rfv%2F7yzo%3D= > 0 > > > > > > > > > > > > > > > Kontron Europe GmbH > > > Heinrich-Barth-Straße 1-1a | 66115 Saarbrücken | Germany
RE: FIELD_RETURN on i.MX8MNANOLPD4 EVK
I think there is no particular SW support needed for FIELD_RETURN on 8MN. From what you described, you have moved the part from closed to FIELD_RETURN. So are you able to boot into SPL without signature? Best regards, Ye Li > -Original Message- > From: Peng Fan (OSS) > Sent: Thursday, January 11, 2024 11:51 AM > To: Thomas Schäfer ; 'u-boot@lists.denx.de' > ; Ye Li > Cc: Peng Fan > Subject: Re: FIELD_RETURN on i.MX8MNANOLPD4 EVK > > +Ye > > 在 1/9/2024 4:52 PM, Thomas Schaefer 写道: > > Hi all, > > > > We are trying to enable FIELD RETURN on the NXP i.MX8MNano LPD4 EVK > board. > > > > We enabled Secure Boot in u-boot in the first step. After checking proper > execution of a signed bootloader image we closed the board blowing the > SEC_CONFIG fuse. > > > > In the next step we created the board specific signature with UID of the CPU > included to remove the FIELD RETURN lock. After that we were able to blow > the FIELD_RETURN fuse with 'fuse prog 8 3 0x1' command. But now, the board > cannot boot any more, it will hang after execution of the SPL bootloader part. > > > > We can observe this behavior with both signed and unsigned bootloader > images. > > > > Is the FIELD_RETURN feature for the i.MX8MNano supported with u-boot > v2024.01? > > > > Best regards, > > Thomas > > > > > > Thomas Schäfer > > SW Design Engineer > > > > thomas.schae...@kontron.com > > www.kontron.com > > > > > > > > > > Kontron Europe GmbH > > Heinrich-Barth-Straße 1-1a | 66115 Saarbrücken | Germany
RE: [EXT] Re: [PATCH v2] mmc: fsl_esdhc: Do not set UHS_CAPS based on CONFIG_MMC_UHS_SUPPORT
_SD1_DATA3 0x5a
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
Best regards,
Ye Li
> > ---
> > Changes since v1:
> > - Remove setting UHS_CAPS completely.
> >
> > drivers/mmc/fsl_esdhc_imx.c | 7 ---
> > 1 file changed, 7 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
> > index 66caf683f7..5e7d9f41b6 100644
> > --- a/drivers/mmc/fsl_esdhc_imx.c
> > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > @@ -1258,13 +1258,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv
> > *priv,
> > esdhc_write32(>tuning_ctrl, val);
> > }
> >
> > - /*
> > - * UHS doesn't have explicit ESDHC flags, so if it's
> > - * not supported, disable it in config.
> > - */
> > - if (CONFIG_IS_ENABLED(MMC_UHS_SUPPORT))
> > - cfg->host_caps |= UHS_CAPS;
>
> I am afraid this just workaround the issue you met. Actually in
> drivers/mmc/mmc, if your card not support UHS_CAPS, the caps will remove the
> UHS_CAPS.
>
> 1762 /* Restrict card's capabilities by what the host can do */
> 1763 caps = card_caps & mmc->host_caps;
> 1764
> 1765 if (!uhs_en)
> 1766 caps &= ~UHS_CAPS;
>
> So would you please dump the card_caps, then we find a proper fix?
>
> Thanks,
> Peng.
>
> > -
> > if (CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)) {
> > if (priv->flags & ESDHC_FLAG_HS200)
> > cfg->host_caps |=
> MMC_CAP(MMC_HS_200);
[PATCH] power: pmic: Add NXP PCA9451A PMIC support
PCA9451A uses similar BUCKs and LDO regulators as PCA9450B/C but
has LDO2 and LDO3 removed. So reuse pca9450 PMIC and regulator driver
and add new type for PCA9451A.
Signed-off-by: Ye Li
---
drivers/power/pmic/pca9450.c | 1 +
drivers/power/regulator/pca9450.c | 11 ++-
include/power/pca9450.h | 1 +
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c
index a186edc..3c4f520 100644
--- a/drivers/power/pmic/pca9450.c
+++ b/drivers/power/pmic/pca9450.c
@@ -111,6 +111,7 @@ static const struct udevice_id pca9450_ids[] = {
{ .compatible = "nxp,pca9450a", .data = NXP_CHIP_TYPE_PCA9450A, },
{ .compatible = "nxp,pca9450b", .data = NXP_CHIP_TYPE_PCA9450BC, },
{ .compatible = "nxp,pca9450c", .data = NXP_CHIP_TYPE_PCA9450BC, },
+ { .compatible = "nxp,pca9451a", .data = NXP_CHIP_TYPE_PCA9451A, },
{ }
};
diff --git a/drivers/power/regulator/pca9450.c
b/drivers/power/regulator/pca9450.c
index fe18693..7ca20d1 100644
--- a/drivers/power/regulator/pca9450.c
+++ b/drivers/power/regulator/pca9450.c
@@ -276,7 +276,8 @@ static int pca9450_regulator_probe(struct udevice *dev)
type = dev_get_driver_data(dev_get_parent(dev));
- if (type != NXP_CHIP_TYPE_PCA9450A && type != NXP_CHIP_TYPE_PCA9450BC) {
+ if (type != NXP_CHIP_TYPE_PCA9450A && type != NXP_CHIP_TYPE_PCA9450BC &&
+ type != NXP_CHIP_TYPE_PCA9451A) {
debug("Unknown PMIC type\n");
return -EINVAL;
}
@@ -291,6 +292,14 @@ static int pca9450_regulator_probe(struct udevice *dev)
continue;
}
+ /* PCA9451A uses BUCK3 in dual-phase and don't have LDO2 and
LDO3 */
+ if (type == NXP_CHIP_TYPE_PCA9451A &&
+ (!strcmp(pca9450_reg_data[i].name, "BUCK3") ||
+ !strcmp(pca9450_reg_data[i].name, "LDO2") ||
+ !strcmp(pca9450_reg_data[i].name, "LDO3"))) {
+ continue;
+ }
+
*plat = pca9450_reg_data[i];
return 0;
diff --git a/include/power/pca9450.h b/include/power/pca9450.h
index fa0405fc..f6d546f 100644
--- a/include/power/pca9450.h
+++ b/include/power/pca9450.h
@@ -59,6 +59,7 @@ int power_pca9450_init(unsigned char bus, unsigned char addr);
enum {
NXP_CHIP_TYPE_PCA9450A = 0,
NXP_CHIP_TYPE_PCA9450BC,
+ NXP_CHIP_TYPE_PCA9451A,
NXP_CHIP_TYPE_AMOUNT
};
--
2.7.4
[PATCH] imx: spl_imx_romapi: Get and print boot stage
Get and print boot stage through ROM API in SPL
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 7 +++
arch/arm/mach-imx/spl_imx_romapi.c| 22 +-
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index dd0d3f2..d70d8bb 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -170,6 +170,13 @@ enum boot_dev_type_e {
BT_DEV_TYPE_INVALID = 0xFF
};
+enum boot_stage_type {
+ BT_STAGE_PRIMARY = 0x6,
+ BT_STAGE_SECONDARY = 0x9,
+ BT_STAGE_RECOVERY = 0xa,
+ BT_STAGE_USB = 0x5,
+};
+
#define QUERY_ROM_VER 1
#define QUERY_BT_DEV 2
#define QUERY_PAGE_SZ 3
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c
b/arch/arm/mach-imx/spl_imx_romapi.c
index aa5d23a..830d5d1 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -341,15 +341,35 @@ int board_return_to_bootrom(struct spl_image_info
*spl_image,
struct spl_boot_device *bootdev)
{
int ret;
- u32 boot;
+ u32 boot, bstage;
ret = rom_api_query_boot_infor(QUERY_BT_DEV, );
+ ret |= rom_api_query_boot_infor(QUERY_BT_STAGE, );
if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n");
return -1;
}
+ printf("Boot Stage: ");
+
+ switch (bstage) {
+ case BT_STAGE_PRIMARY:
+ printf("Primary boot\n");
+ break;
+ case BT_STAGE_SECONDARY:
+ printf("Secondary boot\n");
+ break;
+ case BT_STAGE_RECOVERY:
+ printf("Recovery boot\n");
+ break;
+ case BT_STAGE_USB:
+ printf("USB boot\n");
+ break;
+ default:
+ printf("Unknow (0x%x)\n", bstage);
+ }
+
if (is_boot_from_stream_device(boot))
return spl_romapi_load_image_stream(spl_image, bootdev);
--
2.7.4
[PATCH 22/23] imx8ulp_evk: disable overflow of port0 for LPAV
From: Peng Fan
Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow
With overflow set, we see some issue that A35 may not able to get enough
bandwidth and A35 will report hrtimer takes too much time, workqueue
lockup. With overflow cleared, the issues are gone.
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
board/freescale/imx8ulp_evk/lpddr4_timing.c | 2 +-
board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c
b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index e9edb87..6d28053 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -396,7 +396,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0608e0, 0x30f0f },/* 568 */
{ 0x2e0608e4, 0x }, /* 569 */
{ 0x2e0608e8, 0x32070f0f }, /* 570 */
- { 0x2e0608ec, 0x1320001 }, /* 571 */
+ { 0x2e0608ec, 0x132 }, /* 571 */
{ 0x2e0608f0, 0x13200 },/* 572 */
{ 0x2e0608f4, 0x132 }, /* 573 */
{ 0x2e0608fc, 0x1b1b }, /* 575 */
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
index 9728a25..7945760 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
@@ -395,7 +395,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0608e0, 0x30f0f },/* 568 */
{ 0x2e0608e4, 0x }, /* 569 */
{ 0x2e0608e8, 0x32070f0f }, /* 570 */
- { 0x2e0608ec, 0x1320001 }, /* 571 */
+ { 0x2e0608ec, 0x132 }, /* 571 */
{ 0x2e0608f0, 0x13200 },/* 572 */
{ 0x2e0608f4, 0x132 }, /* 573 */
{ 0x2e0608fc, 0x1d1b }, /* 575 */
--
2.7.4
[PATCH 23/23] imx8ulp_evk: Clear data at fdt_addr_r before booting kernel
When using dual boot mode, the DDR won't be reset when APD power off
or reboot. It has possibility that obsolete fdt data existing on
fdt_addr_r address. Then even nothing in EFI partitions, the distro boot
still continue to parse fdt and get uboot crashed.
Clear the data at fdt_addr_r, so the fdt header check in above case
will not pass.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
board/freescale/imx8ulp_evk/imx8ulp_evk.c | 8
1 file changed, 8 insertions(+)
diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
index b58f143..dd04d59 100644
--- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
@@ -121,8 +121,16 @@ int board_early_init_f(void)
int board_late_init(void)
{
+ ulong addr;
+
#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC)
board_late_mmc_env_init();
#endif
+
+ /* clear fdtaddr to avoid obsolete data */
+ addr = env_get_hex("fdt_addr_r", 0);
+ if (addr)
+ memset((void *)addr, 0, 0x400);
+
return 0;
}
--
2.7.4
[PATCH 21/23] imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun
To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.
Signed-off-by: Ye Li
Acked-by: Peng Fan
---
board/freescale/imx8ulp_evk/lpddr4_timing.c | 4 ++--
board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c
b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index 1878ca5..e9edb87 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -198,8 +198,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0604c8, 0x8000f00 }, /* 306 */
{ 0x2e0604cc, 0xa08 }, /* 307 */
{ 0x2e0604d0, 0x1010101 }, /* 308 */
- { 0x2e0604d4, 0x102 }, /* 309 */
- { 0x2e0604d8, 0x404 }, /* 310 */
+ { 0x2e0604d4, 0x01000102 }, /* 309 */
+ { 0x2e0604d8, 0x0101 }, /* 310 */
{ 0x2e0604dc, 0x40400 },/* 311 */
{ 0x2e0604e0, 0x404 }, /* 312 */
{ 0x2e0604e4, 0x400 }, /* 313 */
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
index e48cb96..9728a25 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
@@ -197,8 +197,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0604c8, 0x8000f00 }, /* 306 */
{ 0x2e0604cc, 0xa08 }, /* 307 */
{ 0x2e0604d0, 0x1010101 }, /* 308 */
- { 0x2e0604d4, 0x102 }, /* 309 */
- { 0x2e0604d8, 0x404 }, /* 310 */
+ { 0x2e0604d4, 0x01000102 }, /* 309 */
+ { 0x2e0604d8, 0x0101 }, /* 310 */
{ 0x2e0604dc, 0x40400 },/* 311 */
{ 0x2e0604e0, 0x404 }, /* 312 */
{ 0x2e0604e4, 0x400 }, /* 313 */
--
2.7.4
[PATCH 17/23] misc: fuse: Lock 8ULP ECC-protected fuse when programming
The ECC fuse on 8ULP can't be written twice. If any user did it, the
ECC value would be wrong then cause accessing problem to the fuse.
The patch will lock the ECC fuse word to avoid this problem.
For iMX9, the OTP controller automatically prevents an ECC fuse word to
be written twice. So it does not need the setting.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
drivers/misc/sentinel/fuse.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index aa691d3..99342d3 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -60,6 +60,11 @@ struct fsb_map_entry fsb_mapping_table[] = {
{ 46, 8 },
};
+/* None ECC banks such like Redundancy or Bit protect */
+u32 nonecc_fuse_banks[] = {
+ 0, 1, 8, 12, 16, 22, 24, 25, 26, 27, 36, 41, 51, 56
+};
+
struct s400_map_entry s400_api_mapping_table[] = {
{ 1, 8 }, /* LOCK */
{ 2, 8 }, /* ECID */
@@ -280,11 +285,26 @@ int fuse_prog(u32 bank, u32 word, u32 val)
{
u32 res;
int ret;
+ bool lock = false;
if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
return -EINVAL;
- ret = ahab_write_fuse((bank * 8 + word), val, false, );
+ /* Lock 8ULP ECC fuse word, so second programming will return failure.
+* iMX9 OTP can protect ECC fuse, so not need it
+*/
+#if defined(CONFIG_IMX8ULP)
+ u32 i;
+ for (i = 0; i < ARRAY_SIZE(nonecc_fuse_banks); i++) {
+ if (nonecc_fuse_banks[i] == bank)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(nonecc_fuse_banks))
+ lock = true;
+#endif
+
+ ret = ahab_write_fuse((bank * 8 + word), val, lock, );
if (ret) {
printf("ahab write fuse failed %d, 0x%x\n", ret, res);
return ret;
--
2.7.4
[PATCH 18/23] ddr: imx: Update the ddr init flow on imx8ulp
From: Jacky Bai
Update the ddr init flow to support LPDDR3 and PLL bypass mode.
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
---
drivers/ddr/imx/imx8ulp/ddr_init.c | 55 +-
1 file changed, 43 insertions(+), 12 deletions(-)
diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c
b/drivers/ddr/imx/imx8ulp/ddr_init.c
index a5a9fd8..c362a2d 100644
--- a/drivers/ddr/imx/imx8ulp/ddr_init.c
+++ b/drivers/ddr/imx/imx8ulp/ddr_init.c
@@ -31,6 +31,7 @@
#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25)
#define DENALI_PHY_1624(DDR_PHY_BASE_ADDR + 4 * 1624)
+#define DENALI_PHY_1625(DDR_PHY_BASE_ADDR + 4 * 1625)
#define DENALI_PHY_1537(DDR_PHY_BASE_ADDR + 4 * 1537)
#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8)
#define PHY_FREQ_SEL_INDEX(X) ((X) << 16)
@@ -82,25 +83,39 @@ int ddr_calibration(unsigned int fsp_table[3])
u32 int_status_init, phy_freq_req, phy_freq_type;
u32 lock_0, lock_1, lock_2;
u32 freq_chg_pt, freq_chg_cnt;
+ u32 is_lpddr4 = 0;
if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) {
ddr_enable_pll_bypass();
freq_chg_cnt = 0;
freq_chg_pt = 0;
} else {
- reg_val = readl(DENALI_CTL_250);
- if (((reg_val >> 16) & 0x3) == 1)
- freq_chg_cnt = 2;
- else
- freq_chg_cnt = 3;
-
- reg_val = readl(DENALI_PI_12);
- if (reg_val == 0x3) {
- freq_chg_pt = 1;
- } else if (reg_val == 0x7) {
- freq_chg_pt = 2;
+ reg_val = (readl(DENALI_CTL_00)>>8)&0xf;
+ if(reg_val == 0x7) {
+ /* LPDDR3 type */
+ set_ddr_clk(fsp_table[1] >> 1);
+ freq_chg_cnt = 0;
+ freq_chg_pt = 0;
+ } else if(reg_val == 0xb) {
+ /* LPDDR4/4x type */
+ is_lpddr4 = 1;
+ reg_val = readl(DENALI_CTL_250);
+ if (((reg_val >> 16) & 0x3) == 1)
+ freq_chg_cnt = 2;
+ else
+ freq_chg_cnt = 3;
+
+ reg_val = readl(DENALI_PI_12);
+ if(reg_val == 0x3)
+ freq_chg_pt = 1;
+ else if(reg_val == 0x7)
+ freq_chg_pt = 2;
+ else {
+ printf("frequency map(0x%x) is wrong, please
check!\r\n", reg_val);
+ return -1;
+ }
} else {
- printf("frequency map(0x%x) is wrong, please
check!\r\n", reg_val);
+ printf("Incorrect DDR type configured!\r\n");
return -1;
}
}
@@ -179,6 +194,22 @@ int ddr_calibration(unsigned int fsp_table[3])
}
debug("De-Skew PLL is locked and ready\n");
+
+ /* Change LPDDR4 FREQ1 to bypass mode if it is lower than 200MHz */
+ if(is_lpddr4 && fsp_table[1] < 400) {
+ /* Set FREQ1 to bypass mode */
+ reg_val = PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(0);
+ writel(reg_val, DENALI_PHY_1537);
+
+ /* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
+ reg_val =readl(DENALI_PHY_1624) | 0x1;
+ writel(reg_val, DENALI_PHY_1624);
+
+ /* DENALI_PHY_1625: bypass mode in PHY PLL */
+ reg_val =readl(DENALI_PHY_1625) & ~0xf;
+ writel(reg_val, DENALI_PHY_1625);
+ }
+
return 0;
}
--
2.7.4
[PATCH 15/23] imx: sentinel: Update S400 API get info message structure
>From Sentinel FW v0.0.9-9df0f503, the response message of get info API
is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
With old structure, we get failure from sentinel due to the buffer
size can't fit with new response message. So update the API structure
to fix the issue.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index cb6e393..5582ff1 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -126,6 +126,8 @@ struct sentinel_get_info_data {
u32 uid[4];
u32 sha256_rom_patch[8];
u32 sha_fw[8];
+ u32 oem_srkh[16];
+ u32 state;
};
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
--
2.7.4
[PATCH 16/23] misc: fuse: Update fuse mapping for 8ULP S400 API
Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
the u-boot driver for the new mapping.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
Reviewed-by: Alice Guo
---
drivers/misc/sentinel/fuse.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index e2b6875..aa691d3 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -67,6 +67,16 @@ struct s400_map_entry s400_api_mapping_table[] = {
{ 15, 8 }, /* OEM SRK HASH */
{ 23, 1, 4, 2 }, /* OTFAD */
{ 25, 8 }, /* Test config2 */
+ { 26, 8 }, /* PMU */
+ { 27, 8 }, /* Test flow/USB */
+ { 32, 8 }, /* GP1 */
+ { 33, 8 }, /* GP2 */
+ { 34, 8 }, /* GP3 */
+ { 35, 8 }, /* GP4 */
+ { 36, 8 }, /* GP5 */
+ { 49, 8 }, /* GP8 */
+ { 50, 8 }, /* GP9 */
+ { 51, 8 }, /* GP10 */
};
#elif defined(CONFIG_ARCH_IMX9)
#define FSB_OTP_SHADOW 0x8000
--
2.7.4
[PATCH 20/23] imx8ulp_evk: Change to use DDR driver
Remove the DDR initialization codes from board and enable the iMX8ULP
DDR driver.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/Kconfig | 1 +
board/freescale/imx8ulp_evk/Makefile | 2 +-
board/freescale/imx8ulp_evk/ddr_init.c | 207 -
3 files changed, 2 insertions(+), 208 deletions(-)
delete mode 100644 board/freescale/imx8ulp_evk/ddr_init.c
diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig
b/arch/arm/mach-imx/imx8ulp/Kconfig
index bbdeaac..c1c1aa0 100644
--- a/arch/arm/mach-imx/imx8ulp/Kconfig
+++ b/arch/arm/mach-imx/imx8ulp/Kconfig
@@ -20,6 +20,7 @@ config TARGET_IMX8ULP_EVK
bool "imx8ulp_evk"
select IMX8ULP
select SUPPORT_SPL
+ select IMX8ULP_DRAM
endchoice
diff --git a/board/freescale/imx8ulp_evk/Makefile
b/board/freescale/imx8ulp_evk/Makefile
index b6ca238..1cf148a 100644
--- a/board/freescale/imx8ulp_evk/Makefile
+++ b/board/freescale/imx8ulp_evk/Makefile
@@ -3,7 +3,7 @@
obj-y += imx8ulp_evk.o
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o ddr_init.o
+obj-y += spl.o
ifdef CONFIG_IMX8ULP_ND_MODE
obj-y += lpddr4_timing_264.o
else
diff --git a/board/freescale/imx8ulp_evk/ddr_init.c
b/board/freescale/imx8ulp_evk/ddr_init.c
deleted file mode 100644
index f4238d2..000
--- a/board/freescale/imx8ulp_evk/ddr_init.c
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Copyright 2021 NXP
- */
-#include
-#include
-#include
-#include
-#include
-
-#define DENALI_CTL_00 (DDR_CTL_BASE_ADDR)
-#define CTL_START 0x1
-
-#define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3)
-#define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197)
-#define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250)
-#define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251)
-#define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266)
-#define DFI_INIT_COMPLETE 0x2
-
-#define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614)
-#define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615)
-
-#define DENALI_PI_00 (DDR_PI_BASE_ADDR)
-#define PI_START 0x1
-
-#define DENALI_PI_04 (DDR_PI_BASE_ADDR + 4 * 4)
-#define DENALI_PI_11 (DDR_PI_BASE_ADDR + 4 * 11)
-#define DENALI_PI_12 (DDR_PI_BASE_ADDR + 4 * 12)
-#define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23)
-#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25)
-
-#define DENALI_PHY_1624(DDR_PHY_BASE_ADDR + 4 * 1624)
-#define DENALI_PHY_1537(DDR_PHY_BASE_ADDR + 4 * 1537)
-#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8)
-#define PHY_FREQ_SEL_INDEX(X) ((X) << 16)
-
-#define DENALI_PHY_1547(DDR_PHY_BASE_ADDR + 4 * 1547)
-#define DENALI_PHY_1555(DDR_PHY_BASE_ADDR + 4 * 1555)
-#define DENALI_PHY_1564(DDR_PHY_BASE_ADDR + 4 * 1564)
-#define DENALI_PHY_1565(DDR_PHY_BASE_ADDR + 4 * 1565)
-
-int ddr_calibration(unsigned int fsp_table[3])
-{
- u32 reg_val;
- u32 int_status_init, phy_freq_req, phy_freq_type;
- u32 lock_0, lock_1, lock_2;
- u32 freq_chg_pt, freq_chg_cnt;
-
- reg_val = readl(DENALI_CTL_250);
- if (((reg_val >> 16) & 0x3) == 1)
- freq_chg_cnt = 2;
- else
- freq_chg_cnt = 3;
-
- reg_val = readl(DENALI_PI_12);
- if (reg_val == 0x3) {
- freq_chg_pt = 1;
- } else if (reg_val == 0x7) {
- freq_chg_pt = 2;
- } else {
- printf("frequency map(0x%x) is wrong, please check!\r\n",
reg_val);
- return -1;
- }
-
- debug("%s\n", __func__);
-
- /* Assert PI_START parameter and then assert START parameter in
Controller. */
- reg_val = readl(DENALI_PI_00) | PI_START;
- writel(reg_val, DENALI_PI_00);
-
- reg_val = readl(DENALI_CTL_00) | CTL_START;
- writel(reg_val, DENALI_CTL_00);
-
- /* Poll for init_done_bit in Controller interrupt status register
(INT_STATUS_INIT) */
- do {
- if (!freq_chg_cnt) {
- int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff;
- /* DDR subsystem is ready for traffic. */
- if (int_status_init & DFI_INIT_COMPLETE) {
- printf("complete\n");
- break;
- }
- }
-
- /*
-* During leveling, PHY will request for freq change and SoC
clock
-* logic should provide requested frequency, Polling SIM
LPDDR_CTRL2
-* Bit phy_freq_chg_req until be 1'b1
-*/
- reg_val = readl(AVD_SIM_LPDDR_CTRL2);
- phy_freq_req = (reg_val >> 7) & 0x1;
-
- if (phy_freq_req) {
-
[PATCH 14/23] imx: imx8ulp: Update clocks to meet max rate restrictions
Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency
restrictions. Detail clock rate changes in the patch:
PLL3 PFD2: 389M -> 324M
PLL3 PFD3: 336M -> 389M
PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD)
PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD)
PLL4 PFD0: 792M -> 594M
PLL4 PFD2: 792M -> 316.8M
NIC_AP:96M (ND) -> 192M, 48M (LD) -> 96M
NIC_LPAV: 198 (ND) -> 192M, 99M (LD) -> 96M
USDHC0:PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD)
USDHC1:PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
USDHC2:PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/cgc.c | 71 +--
arch/arm/mach-imx/imx8ulp/clock.c | 50 +++
2 files changed, 57 insertions(+), 64 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index 104109e..d2fadb4 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -136,42 +136,34 @@ void cgc1_pll3_init(ulong freq)
clrbits_le32(_regs->pll3div_vco, BIT(7));
clrbits_le32(_regs->pll3pfdcfg, 0x3F);
-
- if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
- setbits_le32(_regs->pll3pfdcfg, 25 << 0);
- clrsetbits_le32(_regs->nicclk, GENMASK(26, 21), 3 << 21);
/* 195M */
- } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
- setbits_le32(_regs->pll3pfdcfg, 21 << 0);
- clrsetbits_le32(_regs->nicclk, GENMASK(26, 21), 1 << 21);
/* 231M */
- } else {
- setbits_le32(_regs->pll3pfdcfg, 30 << 0); /* 324M */
- }
-
+ setbits_le32(_regs->pll3pfdcfg, 30 << 0); /* PFD0 324M */
clrbits_le32(_regs->pll3pfdcfg, BIT(7));
while (!(readl(_regs->pll3pfdcfg) & BIT(6)))
;
clrbits_le32(_regs->pll3pfdcfg, 0x3F << 8);
- setbits_le32(_regs->pll3pfdcfg, 25 << 8);
+ setbits_le32(_regs->pll3pfdcfg, 25 << 8); /* PFD1 389M */
clrbits_le32(_regs->pll3pfdcfg, BIT(15));
while (!(readl(_regs->pll3pfdcfg) & BIT(14)))
;
clrbits_le32(_regs->pll3pfdcfg, 0x3F << 16);
- setbits_le32(_regs->pll3pfdcfg, 25 << 16);
+ setbits_le32(_regs->pll3pfdcfg, 30 << 16); /* PFD2 324M */
clrbits_le32(_regs->pll3pfdcfg, BIT(23));
while (!(readl(_regs->pll3pfdcfg) & BIT(22)))
;
clrbits_le32(_regs->pll3pfdcfg, 0x3F << 24);
- setbits_le32(_regs->pll3pfdcfg, 29 << 24);
+ setbits_le32(_regs->pll3pfdcfg, 25 << 24); /* PFD3 389M */
clrbits_le32(_regs->pll3pfdcfg, BIT(31));
while (!(readl(_regs->pll3pfdcfg) & BIT(30)))
;
clrbits_le32(_regs->pll3div_pfd0, 0x3f3f3f3f);
- clrbits_le32(_regs->pll3div_pfd1, 0x3f3f3f3f);
-
+ if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) ||
IS_ENABLED(CONFIG_IMX8ULP_ND_MODE))
+ clrsetbits_le32(_regs->pll3div_pfd1, 0x3f3f3f3f,
0x0301); /* Set PFD3 DIV1 to 194M, PFD3 DIV2 to 97M */
+ else
+ clrsetbits_le32(_regs->pll3div_pfd1, 0x3f3f3f3f,
0x0100); /* Set PFD3 DIV1 to 389M, PFD3 DIV2 to 194M */
clrbits_le32(_regs->pll3div_pfd0, BIT(7));
clrbits_le32(_regs->pll3div_pfd0, BIT(15));
clrbits_le32(_regs->pll3div_pfd0, BIT(23));
@@ -182,6 +174,17 @@ void cgc1_pll3_init(ulong freq)
clrbits_le32(_regs->pll3div_pfd1, BIT(23));
clrbits_le32(_regs->pll3div_pfd1, BIT(31));
+ /* NIC_AP:
+* OD source PLL3 PFD0, 324M
+* ND source FRO192, 192M
+* LD source FRO192, 96M
+ */
+ if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+ clrsetbits_le32(_regs->nicclk, GENMASK(26, 21), 1 << 21);
+ } else {
+ clrbits_le32(_regs->nicclk, GENMASK(26, 21));
+ }
+
if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) &&
!IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
/* nicclk select pll3 pfd0 */
clrsetbits_le32(_regs->nicclk, GENMASK(29, 28), BIT(28));
@@ -222,20 +225,9 @@ void cgc2_pll4_init(bool pll4_reset)
/* Enable all 4 PFDs */
setbits_le32(_regs->pll4pfdcfg, 18 << 0); /* 528 */
- if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
- setbits_le32(_regs->pll4pfdcfg, 24 << 8);
- /* 99Mhz for NIC_LPAV */
- clrsetbits_le32(_regs->niclpavclk, GENMASK(26, 21), 3 <<
21);
- } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
- setbits_le32(_regs->pll4pfdcfg, 24 << 8);
- /* 198Mhz for NIC_LPAV */
- clrsetbits_le32(_regs->niclpavclk, GENMASK(26, 21), 1 <<
21);
- } else {
-
[PATCH 19/23] imx8ulp_evk: Update the DDR timing
From: Jacky Bai
Update the dram timing to support PLL bypass mode
for F1.
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
---
board/freescale/imx8ulp_evk/lpddr4_timing.c | 204 ++--
1 file changed, 102 insertions(+), 102 deletions(-)
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c
b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index 0924099..1878ca5 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -2,7 +2,7 @@
/*
* Copyright 2021 NXP
*
- * Generated code from MX8M_DDR_tool
+ * Generated code from MX8ULP_DDR_tool
*
*/
@@ -16,10 +16,10 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e06002c, 0x17702 },/* 11 */
{ 0x2e060030, 0x5 },/* 12 */
{ 0x2e060034, 0x61 }, /* 13 */
- { 0x2e060038, 0xce3f }, /* 14 */
- { 0x2e06003c, 0x80e70 },/* 15 */
+ { 0x2e060038, 0x4b00 }, /* 14 */
+ { 0x2e06003c, 0x2edfa },/* 15 */
{ 0x2e060040, 0x5 },/* 16 */
- { 0x2e060044, 0x210 }, /* 17 */
+ { 0x2e060044, 0xc0 }, /* 17 */
{ 0x2e060048, 0x19c7d },/* 18 */
{ 0x2e06004c, 0x101cdf }, /* 19 */
{ 0x2e060050, 0x5 },/* 20 */
@@ -31,56 +31,56 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e060068, 0xa },/* 26 */
{ 0x2e06006c, 0x19 }, /* 27 */
{ 0x2e060078, 0x2020200 }, /* 30 */
- { 0x2e06007c, 0x160b }, /* 31 */
+ { 0x2e06007c, 0x1604 }, /* 31 */
{ 0x2e060090, 0x10 }, /* 36 */
{ 0x2e0600a4, 0x40c040c }, /* 41 */
{ 0x2e0600a8, 0x8040614 }, /* 42 */
{ 0x2e0600ac, 0x604 }, /* 43 */
{ 0x2e0600b0, 0x3090003 }, /* 44 */
{ 0x2e0600b4, 0x40002 },/* 45 */
- { 0x2e0600b8, 0xc0011 },/* 46 */
- { 0x2e0600bc, 0xb0509 },/* 47 */
+ { 0x2e0600b8, 0x50008 },/* 46 */
+ { 0x2e0600bc, 0x40309 },/* 47 */
{ 0x2e0600c0, 0x2106 }, /* 48 */
{ 0x2e0600c4, 0xa090017 }, /* 49 */
{ 0x2e0600c8, 0x8200016 }, /* 50 */
{ 0x2e0600cc, 0xa0a }, /* 51 */
{ 0x2e0600d0, 0x4000694 }, /* 52 */
{ 0x2e0600d4, 0xa0a0804 }, /* 53 */
- { 0x2e0600d8, 0x4002432 }, /* 54 */
+ { 0x2e0600d8, 0x4000d29 }, /* 54 */
{ 0x2e0600dc, 0xa0a0804 }, /* 55 */
{ 0x2e0600e0, 0x4004864 }, /* 56 */
{ 0x2e0600e4, 0x2030404 }, /* 57 */
- { 0x2e0600e8, 0x5040400 }, /* 58 */
- { 0x2e0600ec, 0x80b0a06 }, /* 59 */
+ { 0x2e0600e8, 0x4040400 }, /* 58 */
+ { 0x2e0600ec, 0x80b0a04 }, /* 59 */
{ 0x2e0600f0, 0x7010100 }, /* 60 */
- { 0x2e0600f4, 0x4150b },/* 61 */
+ { 0x2e0600f4, 0x41507 },/* 61 */
{ 0x2e0600fc, 0x101 }, /* 63 */
{ 0x2e060100, 0x100 }, /* 64 */
{ 0x2e060104, 0xe0403 },/* 65 */
{ 0x2e060108, 0xb3 }, /* 66 */
- { 0x2e06010c, 0x4a }, /* 67 */
- { 0x2e060110, 0x3fd }, /* 68 */
+ { 0x2e06010c, 0x1b }, /* 67 */
+ { 0x2e060110, 0x16e }, /* 68 */
{ 0x2e060114, 0x94 }, /* 69 */
{ 0x2e060118, 0x803 }, /* 70 */
{ 0x2e06011c, 0x5 },/* 71 */
{ 0x2e060120, 0x7 },/* 72 */
- { 0x2e060124, 0x25000f }, /* 73 */
- { 0x2e060128, 0x4a0078 }, /* 74 */
+ { 0x2e060124, 0xe000f },/* 73 */
+ { 0x2e060128, 0x4a0026 }, /* 74 */
{ 0x2e06012c, 0x4000f9 }, /* 75 */
{ 0x2e060130, 0x120103 }, /* 76 */
{ 0x2e060134, 0x50005 },/* 77 */
- { 0x2e060138, 0x8070005 }, /* 78 */
+ { 0x2e060138, 0x7070005 }, /* 78 */
{ 0x2e06013c, 0x505010d }, /* 79 */
{ 0x2e060140, 0x101030a }, /* 80 */
{ 0x2e060144, 0x30a0505 }, /* 81 */
{ 0x2e060148, 0x5050101 }, /* 82 */
{ 0x2e06014c, 0x1030a },/* 83 */
{ 0x2e060150, 0xe000e },/* 84 */
- { 0x2e060154, 0x4c004c }, /* 85 */
+ { 0x2e060154, 0x1c001c }, /* 85 */
{ 0x2e060158, 0x980098 }, /* 86 */
{ 0x2e06015c, 0x3050505 }, /* 87 */
{ 0x2e060160, 0x3010403 }, /* 88 */
- { 0x2e060164, 0x4050505 }, /* 89 */
+ { 0x2e060164, 0x3050505 }, /* 89 */
{ 0x2e060168, 0x3010403 }, /* 90 */
{ 0x2e06016c, 0x8050505 }, /* 91 */
{ 0x2e060170, 0x3010403 }, /* 92 */
@@ -101,12 +101,12 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0601b4, 0x2cc0 }, /* 109 */
{ 0x2e0601b8, 0x2cc0 }, /* 110 */
{ 0x2e0601c0, 0x4e5 }, /* 112 */
- { 0x2e0601c4, 0xff40 }, /* 113 */
- { 0x2e0601c8, 0xff40 }, /* 114 */
- { 0x2e0601cc, 0xff40 }, /* 115 */
- { 0x2e0601d0, 0xff40 }, /* 116
[PATCH 10/23] imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers
At present, in cgc1_pll3_init we don't set the pll3pfd div values, just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2 to 1 and pfd2div1 to 3. This finally causes some clocks' rate decreased, for example USDHC. So clear the PLL3DIV_PFD dividers to get correct rate. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/cgc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index d240aba..104109e 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -169,6 +169,9 @@ void cgc1_pll3_init(ulong freq) while (!(readl(_regs->pll3pfdcfg) & BIT(30))) ; + clrbits_le32(_regs->pll3div_pfd0, 0x3f3f3f3f); + clrbits_le32(_regs->pll3div_pfd1, 0x3f3f3f3f); + clrbits_le32(_regs->pll3div_pfd0, BIT(7)); clrbits_le32(_regs->pll3div_pfd0, BIT(15)); clrbits_le32(_regs->pll3div_pfd0, BIT(23)); -- 2.7.4
[PATCH 08/23] ddr: imx8ulp: Change DRAM timing save area to 0x20055000
To align with ARM trusted firmware's change, adjust DRAM timing save area to new position 0x20055000. So we can release the space since 0x2006c000 for the NOBITS region of ARM trusted firmware Signed-off-by: Ye Li Reviewed-by: Jacky Bai --- drivers/ddr/imx/imx8ulp/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig index 4284886..5448c33 100644 --- a/drivers/ddr/imx/imx8ulp/Kconfig +++ b/drivers/ddr/imx/imx8ulp/Kconfig @@ -13,6 +13,6 @@ config SAVED_DRAM_TIMING_BASE help The DRAM config timing data need to be saved into sram for low power use. - default 0x2006c000 + default 0x20055000 endmenu -- 2.7.4
[PATCH 09/23] imx: imx8ulp: Reconfigure MRC3 for SRAM0 access
Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
buffer and SPL container loading buffer, need to reconfigure MRC3.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/rdc.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 8551bf6..472b13b 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -276,6 +276,21 @@ void xrdc_init_mda(void)
void xrdc_init_mrc(void)
{
+ /* Re-config MRC3 for SRAM0 in case protected by S400 */
+ xrdc_config_mrc_w0_w1(3, 0, 0x2201, 0x1);
+ xrdc_config_mrc_dx_perm(3, 0, 0, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 1, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 4, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 5, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 6, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 7, 1);
+ xrdc_config_mrc_w3_w4(3, 0, 0x0, 0x8FFF);
+
+ /* Clear other 3 regions of MRC3 to invalid */
+ xrdc_config_mrc_w3_w4(3, 1, 0x0, 0x0);
+ xrdc_config_mrc_w3_w4(3, 2, 0x0, 0x0);
+ xrdc_config_mrc_w3_w4(3, 3, 0x0, 0x0);
+
/* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
xrdc_config_mrc_w0_w1(4, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
xrdc_config_mrc_dx_perm(4, 0, 1, 1);
--
2.7.4
[PATCH 07/23] imx: imx8ulp: configure XRDC for DRAM access from S400
Need to add DRAM access permission for S400, as S400 needs to access it When SPL calls image authentication Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/rdc.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index d664437..8551bf6 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -286,6 +286,11 @@ void xrdc_init_mrc(void) xrdc_config_mrc_dx_perm(5, 0, 1, 1); xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x8FFF); + /* Set MRC6 for DDR access from Sentinel */ + xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); + xrdc_config_mrc_dx_perm(6, 0, 4, 1); + xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x8FFF); + /* The MRC8 is for SRAM1 */ xrdc_config_mrc_w0_w1(8, 0, 0x2100, 0x1); /* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */ -- 2.7.4
[PATCH 02/23] imx: imx8ulp: Get chip revision from Sentinel
In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 1 +
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 +
arch/arm/mach-imx/imx8ulp/soc.c | 32 ---
board/freescale/imx8ulp_evk/spl.c | 10 +++--
4 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index f5a2968..a038cc1 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -10,6 +10,7 @@
#include
#include
+#define SRAM0_BASE 0x2201
#define PBRIDGE0_BASE 0x2800
#define CMC0_RBASE 0x28025000
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index a7869fb..ff49c62 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -15,4 +15,5 @@ void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
int m33_image_handshake(ulong timeout_ms);
+int imx8ulp_dm_post_init(void);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 3498cf9..9b12d3d 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -70,9 +70,18 @@ int mmc_get_env_dev(void)
}
#endif
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+ gd->arch.soc_rev = info->soc;
+ gd->arch.lifecycle = info->lc;
+ memcpy((void *)>arch.uid, >uid, 4 * sizeof(u32));
+}
+
u32 get_cpu_rev(void)
{
- return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
+ u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+
+ return (MXC_CPU_IMX8ULP << 12) | (CHIP_REV_1_0 + rev);
}
enum bt_mode get_boot_mode(void)
@@ -670,10 +679,12 @@ int arch_cpu_init(void)
return 0;
}
-static int imx8ulp_check_mu(void *ctx, struct event *event)
+int imx8ulp_dm_post_init(void)
{
struct udevice *devp;
int ret;
+ u32 res;
+ struct sentinel_get_info_data *info = (struct sentinel_get_info_data
*)SRAM0_BASE;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(imx8ulp_mu), );
if (ret) {
@@ -681,9 +692,24 @@ static int imx8ulp_check_mu(void *ctx, struct event *event)
return ret;
}
+ ret = ahab_get_info(info, );
+ if (ret) {
+ printf("ahab_get_info failed %d\n", ret);
+ /* fallback to A0.1 revision */
+ memset((void *)info, 0, sizeof(struct sentinel_get_info_data));
+ info->soc = 0xa84d;
+ }
+
+ set_cpu_info(info);
+
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu);
+
+static int imx8ulp_evt_dm_post_init(void *ctx, struct event *event)
+{
+ return imx8ulp_dm_post_init();
+}
+EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_evt_dm_post_init);
#if defined(CONFIG_SPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
diff --git a/board/freescale/imx8ulp_evk/spl.c
b/board/freescale/imx8ulp_evk/spl.c
index e672f6e..2a96bd0 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -77,16 +77,12 @@ void display_ele_fw_version(void)
void spl_board_init(void)
{
- struct udevice *dev;
u32 res;
int ret;
- uclass_find_first_device(UCLASS_MISC, );
-
- for (; dev; uclass_find_next_device()) {
- if (device_probe(dev))
- continue;
- }
+ ret = imx8ulp_dm_post_init();
+ if (ret)
+ return;
board_early_init_f();
--
2.7.4
[PATCH 13/23] imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only
This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting. So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.
We have to configure necessary PDAC and MSC for SPL before DDR
initialization.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/rdc.h | 1 +
arch/arm/mach-imx/imx8ulp/rdc.c | 41 +
board/freescale/imx8ulp_evk/spl.c | 8 ---
3 files changed, 47 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/rdc.h
b/arch/arm/include/asm/arch-imx8ulp/rdc.h
index 9746375..5d555c4 100644
--- a/arch/arm/include/asm/arch-imx8ulp/rdc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/rdc.h
@@ -23,5 +23,6 @@ int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32
addr_start, u32 addr_en
void xrdc_init_mda(void);
void xrdc_init_mrc(void);
+void xrdc_init_pdac_msc(void);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 472b13b..50b097b 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -181,6 +181,25 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32
perm)
return 0;
}
+int xrdc_config_msc(u32 msc, u32 index, u32 dom, u32 perm)
+{
+ ulong w0_addr;
+ u32 val;
+
+ if (msc > 2)
+ return -EINVAL;
+
+ w0_addr = XRDC_ADDR + 0x4000 + 0x400 * msc + 0x8 * index;
+
+ val = readl(w0_addr);
+ writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr);
+
+ val = readl(w0_addr + 4);
+ writel(val | BIT(31), w0_addr + 4);
+
+ return 0;
+}
+
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x2702UL;
@@ -325,6 +344,28 @@ void xrdc_init_mrc(void)
xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x8FFF);
}
+void xrdc_init_pdac_msc(void)
+{
+ /* Init LPAV PDAC and MSC for DDR init */
+ xrdc_config_pdac(5, 36, 6, 0x7); /* CMC2*/
+ xrdc_config_pdac(5, 36, 7, 0x7);
+ xrdc_config_pdac(5, 37, 6, 0x7); /* SIM2 */
+ xrdc_config_pdac(5, 37, 7, 0x7);
+ xrdc_config_pdac(5, 38, 6, 0x7); /* CGC2 */
+ xrdc_config_pdac(5, 38, 7, 0x7);
+ xrdc_config_pdac(5, 39, 6, 0x7); /* PCC5 */
+ xrdc_config_pdac(5, 39, 7, 0x7);
+
+ xrdc_config_msc(0, 0, 6, 0x7); /* GPIOE */
+ xrdc_config_msc(0, 0, 7, 0x7);
+ xrdc_config_msc(0, 1, 6, 0x7); /* GPIOF */
+ xrdc_config_msc(0, 1, 7, 0x7);
+ xrdc_config_msc(1, 0, 6, 0x7); /* GPIOD */
+ xrdc_config_msc(1, 0, 7, 0x7);
+ xrdc_config_msc(2, 6, 6, 0x7); /* DDR controller */
+ xrdc_config_msc(2, 6, 7, 0x7);
+}
+
int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool
sec_access)
{
struct trdc *trdc_base = (struct trdc *)0x28031000U;
diff --git a/board/freescale/imx8ulp_evk/spl.c
b/board/freescale/imx8ulp_evk/spl.c
index 2a96bd0..a0dad5f 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -104,9 +104,6 @@ void spl_board_init(void)
clock_init_late();
- /* DDR initialization */
- spl_dram_init();
-
/* This must place after upower init, so access to MDA and MRC are
valid */
/* Init XRDC MDA */
xrdc_init_mda();
@@ -114,6 +111,11 @@ void spl_board_init(void)
/* Init XRDC MRC for VIDEO, DSP domains */
xrdc_init_mrc();
+ xrdc_init_pdac_msc();
+
+ /* DDR initialization */
+ spl_dram_init();
+
/* Call it after PS16 power up */
set_lpav_qos();
--
2.7.4
[PATCH 12/23] imx: imx8ulp: upower: make code cleaner
From: Peng Fan
To clean the upower codes by aligning codes format, check err_code
and add detail bits list for the memory magic number
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 90 +++
1 file changed, 78 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index 370685e..fcb02ed 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -129,6 +129,7 @@ int upower_init(void)
u32 fw_major, fw_minor, fw_vfixes;
u32 soc_id;
int status;
+ enum upwr_resp err_code;
u32 swton;
u64 memon;
@@ -165,22 +166,86 @@ int upower_init(void)
if (ret)
printf("Turn on switches fail %d\n", ret);
else
- printf("Turn on switches ok\n");
+ printf("Turning on switches...\n");
+
upower_wait_resp();
- ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, _val, 1000);
+ ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, _code, _val,
1000);
if (ret != UPWR_REQ_OK)
- printf("Failure %d\n", ret);
+ printf("Turn on switches faliure %d, err_code %d, ret_val
0x%x\n", ret, err_code, ret_val);
+ else
+ printf("Turn on switches ok\n");
- memon = 0x3CUL;
- ret = upwr_pwm_power_on(NULL, (const u32 *), NULL);
+ /*
+* Ascending Order -> bit [0:54)
+* CA35 Core 0 L1 cache
+* CA35 Core 1 L1 cache
+* L2 Cache 0
+* L2 Cache 1
+* L2 Cache victim/tag
+* CAAM Secure RAM
+* DMA1 RAM
+* FlexSPI2 FIFO, Buffer
+* SRAM0
+* AD ROM
+* USB0 TX/RX RAM
+* uSDHC0 FIFO RAM
+* uSDHC1 FIFO RAM
+* uSDHC2 FIFO and USB1 TX/RX RAM
+* GIC RAM
+* ENET TX FIXO
+* Reserved(Brainshift)
+* DCNano Tile2Linear and RGB Correction
+* DCNano Cursor and FIFO
+* EPDC LUT
+* EPDC FIFO
+* DMA2 RAM
+* GPU2D RAM Group 1
+* GPU2D RAM Group 2
+* GPU3D RAM Group 1
+* GPU3D RAM Group 2
+* HIFI4 Caches, IRAM, DRAM
+* ISI Buffers
+* MIPI-CSI FIFO
+* MIPI-DSI FIFO
+* PXP Caches, Buffers
+* SRAM1
+* Casper RAM
+* DMA0 RAM
+* FlexCAN RAM
+* FlexSPI0 FIFO, Buffer
+* FlexSPI1 FIFO, Buffer
+* CM33 Cache
+* PowerQuad RAM
+* ETF RAM
+* Sentinel PKC, Data RAM1, Inst RAM0/1
+* Sentinel ROM
+* uPower IRAM/DRAM
+* uPower ROM
+* CM33 ROM
+* SSRAM Partition 0
+* SSRAM Partition 1
+* SSRAM Partition 2,3,4
+* SSRAM Partition 5
+* SSRAM Partition 6
+* SSRAM Partition 7_a(128KB)
+* SSRAM Partition 7_b(64KB)
+* SSRAM Partition 7_c(64KB)
+* Sentinel Data RAM0, Inst RAM2
+*/
+ /* MIPI-CSI FIFO BIT28 not set */
+ memon = 0x3FEFFCUL;
+ ret = upwr_pwm_power_on(NULL, (const uint32_t *), NULL);
if (ret)
printf("Turn on memories fail %d\n", ret);
else
- printf("Turn on memories ok\n");
+ printf("Turning on memories...\n");
+
upower_wait_resp();
- ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, _val, 1000);
+ ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, _code, _val,
1000);
if (ret != UPWR_REQ_OK)
- printf("Failure %d\n", ret);
+ printf("Turn on memories faliure %d, err_code %d, ret_val
0x%x\n", ret, err_code, ret_val);
+ else
+ printf("Turn on memories ok\n");
mdelay(1);
@@ -188,13 +253,14 @@ int upower_init(void)
if (ret)
printf("Clear DDR retention fail %d\n", ret);
else
- printf("Clear DDR retention ok\n");
+ printf("Clearing DDR retention...\n");
upower_wait_resp();
-
- ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, NULL, _val, 1000);
+ ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, _code, _val,
1000);
if (ret != UPWR_REQ_OK)
- printf("Failure %d\n", ret);
+ printf("Clear DDR retention fail %d, err_code %d, ret_val
0x%x\n", ret, err_code, ret_val);
+ else
+ printf("Clear DDR retention ok\n");
return 0;
}
--
2.7.4
[PATCH 11/23] imx: imx8ulp: upower: replace magic number with macro
From: Peng Fan
The swton indicates the logic switch, magic number 0xfff80 is hard
to understand, so use macro.
Some board design may not have MIPI_CSI voltage input connected per
data sheet. In that case, the upower power on API may dead loop mu to wait
response, however there is no response. So remove MIPI_CSI here, let
linux power domain driver to runtime enable the power domain.
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index b6811d5..370685e 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -11,6 +11,25 @@
#include "upower_api.h"
#define UPOWER_AP_MU1_ADDR 0x2928
+
+#define PS_RTD BIT(0)
+#define PS_DSP BIT(1)
+#define PS_A35_0 BIT(2)
+#define PS_A35_1 BIT(3)
+#define PS_L2 BIT(4)
+#define PS_FAST_NICBIT(5)
+#define PS_APD_PERIPH BIT(6)
+#define PS_GPU3D BIT(7)
+#define PS_HIFI4 BIT(8)
+#define PS_DDR GENMASK(12, 9)
+#define PS_PXP_EPDCBIT(13)
+#define PS_MIPI_DSIBIT(14)
+#define PS_MIPI_CSIBIT(15)
+#define PS_NIC_LPAVBIT(16)
+#define PS_FUSION_AO BIT(17)
+#define PS_FUSEBIT(18)
+#define PS_UPOWER BIT(19)
+
static struct mu_type *muptr = (struct mu_type *)UPOWER_AP_MU1_ADDR;
void upower_wait_resp(void)
@@ -140,7 +159,8 @@ int upower_init(void)
}
} while (0);
- swton = 0xfff80;
+ swton = PS_UPOWER | PS_FUSE | PS_FUSION_AO | PS_NIC_LPAV | PS_PXP_EPDC
| PS_DDR |
+ PS_HIFI4 | PS_GPU3D | PS_MIPI_DSI;
ret = upwr_pwm_power_on(, NULL, NULL);
if (ret)
printf("Turn on switches fail %d\n", ret);
--
2.7.4
[PATCH 06/23] imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.
The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.
The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.
Signed-off-by: Ye Li
Reviewed-by: Jacky Bai
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 +
arch/arm/include/asm/global_data.h| 3 +
arch/arm/mach-imx/imx8ulp/soc.c | 104 ++
board/freescale/imx8ulp_evk/imx8ulp_evk.c | 8 +-
4 files changed, 93 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index ff49c62..5bbae21 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -14,6 +14,7 @@ int xrdc_config_pdac_openacc(u32 bridge, u32 index);
void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
+bool is_m33_handshake_necessary(void);
int m33_image_handshake(ulong timeout_ms);
int imx8ulp_dm_post_init(void);
#endif
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 9e746e3..8698783 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -97,6 +97,9 @@ struct arch_global_data {
u32 uid[4];
#endif
+#ifdef CONFIG_ARCH_IMX8ULP
+ bool m33_handshake_done;
+#endif
};
#include
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 0d7858a..8424332 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -104,14 +104,70 @@ enum bt_mode get_boot_mode(void)
bool m33_image_booted(void)
{
- u32 gp6;
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ u32 gp6 = 0;
+
+ /* DGO_GP6 */
+ gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
+ if (gp6 & BIT(5))
+ return true;
+
+ return false;
+ } else {
+ u32 gpr0 = readl(SIM1_BASE_ADDR);
+ if (gpr0 & BIT(0))
+ return true;
+
+ return false;
+ }
+}
+
+bool rdc_enabled_in_boot(void)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ u32 val = 0;
+ int ret;
+ bool rdc_en = true; /* Default assume DBD_EN is set */
+
+ /* Read DBD_EN fuse */
+ ret = fuse_read(8, 1, );
+ if (!ret)
+ rdc_en = !!(val & 0x200); /* only A1 part uses DBD_EN,
so check DBD_EN new place*/
+
+ return rdc_en;
+ } else {
+ u32 gpr0 = readl(SIM1_BASE_ADDR);
+ if (gpr0 & 0x2)
+ return true;
+
+ return false;
+ }
+}
+
+static void spl_pass_boot_info(void)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ bool m33_booted = m33_image_booted();
+ bool rdc_en = rdc_enabled_in_boot();
+ u32 val = 0;
- /* DGO_GP6 */
- gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
- if (gp6 & BIT(5))
- return true;
+ if (m33_booted)
+ val |= 0x1;
- return false;
+ if (rdc_en)
+ val |= 0x2;
+
+ writel(val, SIM1_BASE_ADDR);
+ }
+}
+
+bool is_m33_handshake_necessary(void)
+{
+ /* Only need handshake in u-boot */
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ return (m33_image_booted() || rdc_enabled_in_boot());
+ else
+ return false;
}
int m33_image_handshake(ulong timeout_ms)
@@ -661,10 +717,6 @@ void set_lpav_qos(void)
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
- u32 val = 0;
- int ret;
- bool rdc_en = true; /* Default assume DBD_EN is set */
-
/* Enable System Reset Interrupt using WDOG_AD */
setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
/* Clear AD_PERIPH Power switch domain out of reset interrupt
flag */
@@ -681,31 +733,51 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
- /* Read DBD_EN fuse */
- ret = fuse_read(8, 1, );
- if (!ret)
- rdc_en = !!(val & 0x4000);
-
if (get_boot_mode() == SINGLE_BOOT)
lpav_configure(false);
else
[PATCH 04/23] imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD
iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/rdc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 6d2adcf..d664437 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -276,6 +276,16 @@ void xrdc_init_mda(void)
void xrdc_init_mrc(void)
{
+ /* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
+ xrdc_config_mrc_w0_w1(4, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+ xrdc_config_mrc_dx_perm(4, 0, 1, 1);
+ xrdc_config_mrc_dx_perm(4, 0, 7, 1);
+ xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x8FFF);
+
+ xrdc_config_mrc_w0_w1(5, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+ xrdc_config_mrc_dx_perm(5, 0, 1, 1);
+ xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x8FFF);
+
/* The MRC8 is for SRAM1 */
xrdc_config_mrc_w0_w1(8, 0, 0x2100, 0x1);
/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access
*/
--
2.7.4
[PATCH 03/23] imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part
Since A1 ROM has fixed the ROM API eMMC issue, we should only use
the workaround for A0.1 part. Add a SOC revision check.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 9b12d3d..4370399 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -761,7 +761,8 @@ int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;
u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
{
/* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp
workaround */
- if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC &&
card_emmc_is_boot_part_en())
+ if (is_soc_rev(CHIP_REV_1_0) && ((rom_bt_dev >> 16) & 0xff) ==
BT_DEV_TYPE_MMC &&
+ card_emmc_is_boot_part_en())
image_offset = 0;
return image_offset;
--
2.7.4
[PATCH 05/23] imx: imx8ulp: Remove the TRDC configure from A35
As M33 is responsible for TRDC configuration, the settings for A35
nonsecure world access and DMA0 access are moved to M33 image.
So remove the codes to release TRDC and configure it. Just keep
the configurations for reference.
Signed-off-by: Ye Li
Reviewed-by: Jacky Bai
---
arch/arm/mach-imx/imx8ulp/soc.c | 63 +
1 file changed, 45 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 4370399..0d7858a 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -556,33 +556,65 @@ static void set_core0_reset_vector(u32 entry)
setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
}
-static int trdc_set_access(void)
+/* Not used now */
+int trdc_set_access(void)
{
/*
* TRDC mgr + 4 MBC + 2 MRC.
-* S400 should already configure when release RDC
-* A35 only map non-secure region for pbridge0 and 1, set sec_access to
false
*/
- trdc_mbc_set_access(2, 7, 0, 49, false);
- trdc_mbc_set_access(2, 7, 0, 50, false);
- trdc_mbc_set_access(2, 7, 0, 51, false);
- trdc_mbc_set_access(2, 7, 0, 52, false);
- trdc_mbc_set_access(2, 7, 0, 53, false);
- trdc_mbc_set_access(2, 7, 0, 54, false);
-
- /* CGC0: PBridge0 slot 47 */
+ trdc_mbc_set_access(2, 7, 0, 49, true);
+ trdc_mbc_set_access(2, 7, 0, 50, true);
+ trdc_mbc_set_access(2, 7, 0, 51, true);
+ trdc_mbc_set_access(2, 7, 0, 52, true);
+ trdc_mbc_set_access(2, 7, 0, 53, true);
+ trdc_mbc_set_access(2, 7, 0, 54, true);
+
+ /* 0x1fff8000 used for resource table by remoteproc */
+ trdc_mbc_set_access(0, 7, 2, 31, false);
+
+ /* CGC0: PBridge0 slot 47 and PCC0 slot 48 */
trdc_mbc_set_access(2, 7, 0, 47, false);
+ trdc_mbc_set_access(2, 7, 0, 48, false);
+
+ /* PCC1 */
+ trdc_mbc_set_access(2, 7, 1, 17, false);
+ trdc_mbc_set_access(2, 7, 1, 34, false);
/* Iomuxc0: : PBridge1 slot 33 */
trdc_mbc_set_access(2, 7, 1, 33, false);
/* flexspi0 */
+ trdc_mbc_set_access(2, 7, 0, 57, false);
trdc_mrc_region_set_access(0, 7, 0x0400, 0x0c00, false);
/* tpm0: PBridge1 slot 21 */
trdc_mbc_set_access(2, 7, 1, 21, false);
/* lpi2c0: PBridge1 slot 24 */
trdc_mbc_set_access(2, 7, 1, 24, false);
+
+ /* Allow M33 to access TRDC MGR */
+ trdc_mbc_set_access(2, 6, 0, 49, true);
+ trdc_mbc_set_access(2, 6, 0, 50, true);
+ trdc_mbc_set_access(2, 6, 0, 51, true);
+ trdc_mbc_set_access(2, 6, 0, 52, true);
+ trdc_mbc_set_access(2, 6, 0, 53, true);
+ trdc_mbc_set_access(2, 6, 0, 54, true);
+
+ /* Set SAI0 for eDMA 0, NS */
+ trdc_mbc_set_access(2, 0, 1, 28, false);
+
+ /* Set SSRAM for eDMA0 access */
+ trdc_mbc_set_access(0, 0, 2, 0, false);
+ trdc_mbc_set_access(0, 0, 2, 1, false);
+ trdc_mbc_set_access(0, 0, 2, 2, false);
+ trdc_mbc_set_access(0, 0, 2, 3, false);
+ trdc_mbc_set_access(0, 0, 2, 4, false);
+ trdc_mbc_set_access(0, 0, 2, 5, false);
+ trdc_mbc_set_access(0, 0, 2, 6, false);
+ trdc_mbc_set_access(0, 0, 2, 7, false);
+
+ writel(0x80a0, 0x28031840);
+
return 0;
}
@@ -654,15 +686,10 @@ int arch_cpu_init(void)
if (!ret)
rdc_en = !!(val & 0x4000);
- if (get_boot_mode() == SINGLE_BOOT) {
- if (rdc_en)
- release_rdc(RDC_TRDC);
-
- trdc_set_access();
+ if (get_boot_mode() == SINGLE_BOOT)
lpav_configure(false);
- } else {
+ else
lpav_configure(true);
- }
/* Release xrdc, then allow A35 to write SRAM2 */
if (rdc_en)
--
2.7.4
[PATCH 01/23] imx: imx8ulp: Fix MU device probe failure
Since latest DTS has added multiple MU nodes, using compatible
string to find the device node is not proper. It finds the first
node with the compatible string matched even the node is disabled.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/soc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 5d95fb8..3498cf9 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -673,11 +673,9 @@ int arch_cpu_init(void)
static int imx8ulp_check_mu(void *ctx, struct event *event)
{
struct udevice *devp;
- int node, ret;
-
- node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"fsl,imx8ulp-mu");
+ int ret;
- ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, );
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(imx8ulp_mu), );
if (ret) {
printf("could not get S400 mu %d\n", ret);
return ret;
--
2.7.4
[PATCH 00/23] Add i.MX8ULP A1 revision support
The patch set is used to support i.MX8ULP A1 revision. It includes below changes: a) XRDC/TRDC are enabled by default on A1 via DBD_EN fuse programmed. So necessary changes for XRDC setting are added. And TRDC is totally moved to RTD. A handshake is added to sync with RTD for the XRDC and TRDC setting completion. b) S400 API update and fuse update c) DDR timing and driver update d) clock setting update to match max rate restriction e) uPower API update and code clean Jacky Bai (2): ddr: imx: Update the ddr init flow on imx8ulp imx8ulp_evk: Update the DDR timing Peng Fan (3): imx: imx8ulp: upower: replace magic number with macro imx: imx8ulp: upower: make code cleaner imx8ulp_evk: disable overflow of port0 for LPAV Ye Li (18): imx: imx8ulp: Fix MU device probe failure imx: imx8ulp: Get chip revision from Sentinel imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD imx: imx8ulp: Remove the TRDC configure from A35 imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion imx: imx8ulp: configure XRDC for DRAM access from S400 ddr: imx8ulp: Change DRAM timing save area to 0x20055000 imx: imx8ulp: Reconfigure MRC3 for SRAM0 access imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only imx: imx8ulp: Update clocks to meet max rate restrictions imx: sentinel: Update S400 API get info message structure misc: fuse: Update fuse mapping for 8ULP S400 API misc: fuse: Lock 8ULP ECC-protected fuse when programming imx8ulp_evk: Change to use DDR driver imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun imx8ulp_evk: Clear data at fdt_addr_r before booting kernel arch/arm/include/asm/arch-imx8ulp/imx-regs.h| 1 + arch/arm/include/asm/arch-imx8ulp/rdc.h | 1 + arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 + arch/arm/include/asm/global_data.h | 3 + arch/arm/include/asm/mach-imx/s400_api.h| 2 + arch/arm/mach-imx/imx8ulp/Kconfig | 1 + arch/arm/mach-imx/imx8ulp/cgc.c | 70 arch/arm/mach-imx/imx8ulp/clock.c | 50 +++--- arch/arm/mach-imx/imx8ulp/rdc.c | 71 arch/arm/mach-imx/imx8ulp/soc.c | 208 ++- arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 112 +++-- board/freescale/imx8ulp_evk/Makefile| 2 +- board/freescale/imx8ulp_evk/ddr_init.c | 207 --- board/freescale/imx8ulp_evk/imx8ulp_evk.c | 16 +- board/freescale/imx8ulp_evk/lpddr4_timing.c | 210 board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 6 +- board/freescale/imx8ulp_evk/spl.c | 18 +- drivers/ddr/imx/imx8ulp/Kconfig | 2 +- drivers/ddr/imx/imx8ulp/ddr_init.c | 55 +-- drivers/misc/sentinel/fuse.c| 32 +++- 20 files changed, 605 insertions(+), 464 deletions(-) delete mode 100644 board/freescale/imx8ulp_evk/ddr_init.c -- 2.7.4
[PATCH] watchdog: ulp_wdog: only compile the code of DM driver when CONFIG_WDT=y
From: Alice Guo
DM watchdog timer driver and non-DM driver exist in ulp_wdog.c at the
same time. Add a compilation restriction that only compile the DM driver
part when CONFIG_WDT=y.
Signed-off-by: Alice Guo
Reviewed-by: Ye Li
---
drivers/watchdog/ulp_wdog.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index e081054..8f8182d 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -164,6 +164,7 @@ void reset_cpu(void)
while (1);
}
+#if CONFIG_IS_ENABLED(WDT)
static int ulp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
struct ulp_wdt_priv *priv = dev_get_priv(dev);
@@ -222,3 +223,4 @@ U_BOOT_DRIVER(ulp_wdt) = {
.probe = ulp_wdt_probe,
.ops= _wdt_ops,
};
+#endif
--
2.7.4
[PATCH] env: mmc: Fix offset issue for env save
Fix the issue in commit 46c9016 (env: mcc: Drop unnecessary #ifdefs)
If CONFIG_SYS_REDUNDAND_ENVIRONMENT is not defined, the offset value
becomes undetermined, so write env to unexpected offset.
Signed-off-by: Ye Li
---
env/mmc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/env/mmc.c b/env/mmc.c
index 8576141..5b01f65 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -273,11 +273,11 @@ static int env_mmc_save(void)
if (ret)
goto fini;
}
+ }
- if (mmc_get_env_addr(mmc, copy, )) {
- ret = 1;
- goto fini;
- }
+ if (mmc_get_env_addr(mmc, copy, )) {
+ ret = 1;
+ goto fini;
}
printf("Writing to %sMMC(%d)... ", copy ? "redundant " : "", dev);
--
2.7.4
[PATCH 6/6] imx: ele_ahab: Remove OEM Secure World Closed print
The OEM Secure World Closed is not a valid lifecycle on iMX8ULP/iMX9.
So remove it from lifecycle print.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/ele_ahab.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 58b6542..99fc540 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -429,9 +429,6 @@ static void display_life_cycle(u32 lc)
case 0x8:
printf("OEM Open\n\n");
break;
- case 0x10:
- printf("OEM Secure World Closed\n\n");
- break;
case 0x20:
printf("OEM closed\n\n");
break;
--
2.7.4
[PATCH 5/6] imx: ele_ahab: confirm lifecycle before closing the part
Before moving the lifecycle to OEM closed, confirm the lifecycle is
OEM open, otherwise cancel to move forward the lifecycle.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/ele_ahab.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index da8c99b..58b6542 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -474,10 +474,20 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag,
int argc,
{
int err;
u32 resp;
+ u32 lc;
if (!confirm_close())
return -EACCES;
+ lc = readl(FSB_BASE_ADDR + 0x41c);
+ lc &= 0x3ff;
+
+ if (lc != 0x8) {
+ puts("Current lifecycle is NOT OEM open, can't move to OEM
closed\n");
+ display_life_cycle(lc);
+ return -EPERM;
+ }
+
err = ahab_forward_lifecycle(8, );
if (err != 0) {
printf("Error in forward lifecycle to OEM closed\n");
--
2.7.4
[PATCH 3/6] imx: ahab: Move imx9 and imx8ulp AHAB support together
Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since
both of them use same sentinel ELE APIs
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 2 +
arch/arm/include/asm/arch-imx9/imx-regs.h| 2 +
arch/arm/mach-imx/Makefile | 4 +
arch/arm/mach-imx/ele_ahab.c | 579 ++
arch/arm/mach-imx/imx8ulp/ahab.c | 345
arch/arm/mach-imx/imx9/Makefile | 1 -
arch/arm/mach-imx/imx9/ahab.c| 580 ---
7 files changed, 587 insertions(+), 926 deletions(-)
create mode 100644 arch/arm/mach-imx/ele_ahab.c
delete mode 100644 arch/arm/mach-imx/imx8ulp/ahab.c
delete mode 100644 arch/arm/mach-imx/imx9/ahab.c
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index 723bab5..f5a2968 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -62,6 +62,8 @@
#define FEC_QUIRK_ENET_MAC
+#define IMG_CONTAINER_BASE (0x2201UL)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index f575805..065fd1f 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -40,6 +40,8 @@
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+#define IMG_CONTAINER_BASE (0x8000UL)
+
#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASKGENMASK(3, 1)
#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 61b4f4f..4469826 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -77,6 +77,10 @@ ifeq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o parse-container.o
endif
+ifeq ($(SOC),$(filter $(SOC),imx8ulp imx9))
+obj-$(CONFIG_AHAB_BOOT) += ele_ahab.o
+endif
+
PLUGIN = board/$(BOARDDIR)/plugin
ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
new file mode 100644
index 000..da8c99b
--- /dev/null
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xUL)
+
+#define AHAB_MAX_EVENTS 8
+
+static char *ele_ipc_str[] = {
+ "IPC = MU RTD (0x1)\n",
+ "IPC = MU APD (0x2)\n",
+ "IPC = INVALID\n",
+ NULL
+};
+
+static char *ele_status_str[] = {
+ "STA = ELE_SUCCESS_IND (0xD6)\n",
+ "STA = ELE_FAILURE_IND (0x29)\n",
+ "STA = INVALID\n",
+ NULL
+};
+
+static char *ele_cmd_str[] = {
+ "CMD = ELE_PING_REQ (0x01)\n",
+ "CMD = ELE_FW_AUTH_REQ (0x02)\n",
+ "CMD = ELE_RESTART_RST_TIMER_REQ (0x04)\n",
+ "CMD = ELE_DUMP_DEBUG_BUFFER_REQ (0x21)\n",
+ "CMD = ELE_OEM_CNTN_AUTH_REQ (0x87)\n",
+ "CMD = ELE_VERIFY_IMAGE_REQ (0x88)\n",
+ "CMD = ELE_RELEASE_CONTAINER_REQ (0x89)\n",
+ "CMD = ELE_WRITE_SECURE_FUSE_REQ (0x91)\n",
+ "CMD = ELE_FWD_LIFECYCLE_UP_REQ (0x95)\n",
+ "CMD = ELE_READ_FUSE_REQ (0x97)\n",
+ "CMD = ELE_GET_FW_VERSION_REQ (0x9D)\n",
+ "CMD = ELE_RET_LIFECYCLE_UP_REQ (0xA0)\n",
+ "CMD = ELE_GET_EVENTS_REQ (0xA2)\n",
+ "CMD = ELE_ENABLE_PATCH_REQ (0xC3)\n",
+ "CMD = ELE_RELEASE_RDC_REQ (0xC4)\n",
+ "CMD = ELE_GET_FW_STATUS_REQ (0xC5)\n",
+ "CMD = ELE_ENABLE_OTFAD_REQ (0xC6)\n",
+ "CMD = ELE_RESET_REQ (0xC7)\n",
+ "CMD = ELE_UPDATE_OTP_CLKDIV_REQ (0xD0)\n",
+ "CMD = ELE_POWER_DOWN_REQ (0xD1)\n",
+ "CMD = ELE_ENABLE_APC_REQ (0xD2)\n",
+ "CMD = ELE_ENABLE_RTC_REQ (0xD3)\n",
+ "CMD = ELE_DEEP_POWER_DOWN_REQ (0xD4)\n",
+ "CMD = ELE_STOP_RST_TIMER_REQ (0xD5)\n",
+ "CMD = ELE_WRITE_FUSE_REQ (0xD6)\n",
+ "CMD = ELE_RELEASE_CAAM_REQ (0xD7)\n",
+ "CMD = ELE_RESET_A35_CTX_REQ (0xD8)\n",
+ "CMD = ELE_MOVE_TO_UNSECURED_REQ (0xD9)\n",
+ "CMD = ELE_GET_INFO_REQ (0xDA)\n",
+ "CMD = ELE_ATTEST_REQ (0xDB)\n",
+ "CMD = ELE_RELEASE_PATCH_REQ (0xDC)\n
[PATCH 4/6] misc: sentinel: s400_api: Use new command request definitions
Remove legacy command definitions, change to use new ELE_xxx command
request.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 15 ---
arch/arm/mach-imx/imx8ulp/rdc.c | 2 +-
arch/arm/mach-imx/imx9/trdc.c| 2 +-
drivers/misc/sentinel/s400_api.c | 28 ++--
4 files changed, 16 insertions(+), 31 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index c87a7c1..5582ff1 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -109,21 +109,6 @@
#define ELE_SUCCESS_IND (0xD6)
#define ELE_FAILURE_IND (0x29)
-#define AHAB_LOG_CID0x21
-#define AHAB_AUTH_OEM_CTNR_CID 0x87
-#define AHAB_VERIFY_IMG_CID 0x88
-#define AHAB_RELEASE_CTNR_CID 0x89
-#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91
-#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
-#define AHAB_READ_FUSE_REQ_CID 0x97
-#define AHAB_GET_FW_VERSION_CID0x9D
-#define AHAB_GET_EVENTS_REQ_CID 0xA2
-#define AHAB_RELEASE_RDC_REQ_CID 0xC4
-#define AHAB_GET_FW_STATUS_CID 0xC5
-#define AHAB_WRITE_FUSE_REQ_CID0xD6
-#define AHAB_CAAM_RELEASE_CID 0xD7
-#define AHAB_GET_INFO_CID 0xDA
-
#define S400_MAX_MSG 255U
struct sentinel_msg {
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 56df111..50b097b 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -210,7 +210,7 @@ int release_rdc(enum rdc_type type)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
- msg.command = AHAB_RELEASE_RDC_REQ_CID;
+ msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
mu_hal_init(s_mu_base);
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index 3f37ce7..e05c704 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -339,7 +339,7 @@ int release_rdc(u8 xrdc)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
- msg.command = AHAB_RELEASE_RDC_REQ_CID;
+ msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */
mu_hal_init(s_mu_base);
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index c6b4ef5..6c0d0b3 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -29,7 +29,7 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
- msg.command = AHAB_RELEASE_RDC_REQ_CID;
+ msg.command = ELE_RELEASE_RDC_REQ;
switch (xrdc) {
case 0:
msg.data[0] = (0x74 << 8) | core_id;
@@ -74,7 +74,7 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 3;
- msg.command = AHAB_AUTH_OEM_CTNR_CID;
+ msg.command = ELE_OEM_CNTN_AUTH_REQ;
msg.data[0] = upper_32_bits(ctnr_addr);
msg.data[1] = lower_32_bits(ctnr_addr);
@@ -104,7 +104,7 @@ int ahab_release_container(u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 1;
- msg.command = AHAB_RELEASE_CTNR_CID;
+ msg.command = ELE_RELEASE_CONTAINER_REQ;
ret = misc_call(dev, false, , size, , size);
if (ret)
@@ -132,7 +132,7 @@ int ahab_verify_image(u32 img_id, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
- msg.command = AHAB_VERIFY_IMG_CID;
+ msg.command = ELE_VERIFY_IMAGE_REQ;
msg.data[0] = 1 << img_id;
ret = misc_call(dev, false, , size, , size);
@@ -161,7 +161,7 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
- msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID;
+ msg.command = ELE_FWD_LIFECYCLE_UP_REQ;
msg.data[0] = life_cycle;
ret = misc_call(dev, false, , size, , size);
@@ -201,7 +201,7 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32
fuse_num, u32 *respo
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
- msg.command = AHAB_READ_FUSE_REQ_CID;
+ msg.command = ELE_READ_FUSE_REQ;
msg.data[0] = fuse_id;
ret = misc_call(dev, false, , size, , size);
@@ -238,7 +238,7 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock,
u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 3;
- msg.command = AHAB_WRITE_FUSE_REQ_CID;
+ msg.command = ELE_WRITE_FUSE_REQ;
msg.data[0] = (32 << 16) | (fuse_id << 5);
if (loc
[PATCH 2/6] imx93: ahab: Get and decode AHAB events
For ahab_status command, support to get and decode AHAB events Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/mach-imx/s400_api.h | 99 +++ arch/arm/mach-imx/imx9/ahab.c| 286 --- 2 files changed, 359 insertions(+), 26 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h index 79539b7..c87a7c1 100644 --- a/arch/arm/include/asm/mach-imx/s400_api.h +++ b/arch/arm/include/asm/mach-imx/s400_api.h @@ -10,6 +10,105 @@ #define AHAB_CMD_TAG0x17 #define AHAB_RESP_TAG 0xe1 +/* ELE commands */ +#define ELE_PING_REQ (0x01) +#define ELE_FW_AUTH_REQ (0x02) +#define ELE_RESTART_RST_TIMER_REQ (0x04) +#define ELE_DUMP_DEBUG_BUFFER_REQ (0x21) +#define ELE_OEM_CNTN_AUTH_REQ (0x87) +#define ELE_VERIFY_IMAGE_REQ (0x88) +#define ELE_RELEASE_CONTAINER_REQ (0x89) +#define ELE_WRITE_SECURE_FUSE_REQ (0x91) +#define ELE_FWD_LIFECYCLE_UP_REQ (0x95) +#define ELE_READ_FUSE_REQ (0x97) +#define ELE_GET_FW_VERSION_REQ (0x9D) +#define ELE_RET_LIFECYCLE_UP_REQ (0xA0) +#define ELE_GET_EVENTS_REQ (0xA2) +#define ELE_ENABLE_PATCH_REQ (0xC3) +#define ELE_RELEASE_RDC_REQ (0xC4) +#define ELE_GET_FW_STATUS_REQ (0xC5) +#define ELE_ENABLE_OTFAD_REQ (0xC6) +#define ELE_RESET_REQ (0xC7) +#define ELE_UPDATE_OTP_CLKDIV_REQ (0xD0) +#define ELE_POWER_DOWN_REQ (0xD1) +#define ELE_ENABLE_APC_REQ (0xD2) +#define ELE_ENABLE_RTC_REQ (0xD3) +#define ELE_DEEP_POWER_DOWN_REQ (0xD4) +#define ELE_STOP_RST_TIMER_REQ (0xD5) +#define ELE_WRITE_FUSE_REQ (0xD6) +#define ELE_RELEASE_CAAM_REQ (0xD7) +#define ELE_RESET_A35_CTX_REQ (0xD8) +#define ELE_MOVE_TO_UNSECURED_REQ (0xD9) +#define ELE_GET_INFO_REQ (0xDA) +#define ELE_ATTEST_REQ (0xDB) +#define ELE_RELEASE_PATCH_REQ (0xDC) +#define ELE_OTP_SEQ_SWITH_REQ (0xDD) + +/* ELE failure indications */ +#define ELE_ROM_PING_FAILURE_IND (0x0A) +#define ELE_FW_PING_FAILURE_IND (0x1A) +#define ELE_BAD_SIGNATURE_FAILURE_IND (0xF0) +#define ELE_BAD_HASH_FAILURE_IND (0xF1) +#define ELE_INVALID_LIFECYCLE_IND (0xF2) +#define ELE_PERMISSION_DENIED_FAILURE_IND (0xF3) +#define ELE_INVALID_MESSAGE_FAILURE_IND (0xF4) +#define ELE_BAD_VALUE_FAILURE_IND (0xF5) +#define ELE_BAD_FUSE_ID_FAILURE_IND (0xF6) +#define ELE_BAD_CONTAINER_FAILURE_IND (0xF7) +#define ELE_BAD_VERSION_FAILURE_IND (0xF8) +#define ELE_INVALID_KEY_FAILURE_IND (0xF9) +#define ELE_BAD_KEY_HASH_FAILURE_IND (0xFA) +#define ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB) +#define ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC) +#define ELE_BAD_UID_FAILURE_IND (0xFD) +#define ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE) +#define ELE_MUST_SIGNED_FAILURE_IND (0xE0) +#define ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE) +#define ELE_BAD_SRK_SET_FAILURE_IND (0xEF) +#define ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6) +#define ELE_WRONG_SIZE_FAILURE_IND (0xA7) +#define ELE_ENCRYPTION_FAILURE_IND (0xA8) +#define ELE_DECRYPTION_FAILURE_IND (0xA9) +#define ELE_OTP_PROGFAIL_FAILURE_IND (0xAA) +#define ELE_OTP_LOCKED_FAILURE_IND (0xAB) +#define ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD) +#define ELE_TIME_OUT_FAILURE_IND (0xB0) +#define ELE_BAD_PAYLOAD_FAILURE_IND (0xB1) +#define ELE_WRONG_ADDRESS_FAILURE_IND (0xB4) +#define ELE_DMA_FAILURE_IND (0xB5) +#define ELE_DISABLED_FEATURE_FAILURE_IND (0xB6) +#define ELE_MUST_ATTEST_FAILURE_IND (0xB7) +#define ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8) +#define ELE_CRC_ERROR_IND (0xB9) +#define ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB) +#define ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC) +#define ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD) +#define ELE_LOCKED_REG_FAILURE_IND (0xBE) +#define ELE_BAD_ID_FAILURE_IND (0xBF) +#define ELE_INVALID_OPERATION_FAILURE_IND (0xC0) +#define ELE_NON_SECURE_STATE_FAILURE_IND (0xC1) +#define ELE_MSG_TRUNCATED_IND (0xC2) +#define ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3) +#define ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4) +#define ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5) +#define ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6) +#define ELE_CORRUPTED_SRK_FAILURE_IND (0xD0) +#define ELE_OUT_OF_MEMORY_IND (0xD1) +#define ELE_CSTM_FAILURE_IND (0xCF) +#define ELE_OLD_VERSION_FAILURE_IND (0xCE) +#define ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD) +#define ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB) +#define ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC) +#define ELE_ABORT_IND (0xFF) + +/* ELE IPC identifier */ +#define ELE_IPC_MU_RTD (0x1) +#define ELE_IPC_MU_APD (0x2) + +/* ELE Status*/ +#define ELE_SUCCESS_IND (0xD6) +#define ELE_FAILURE_IND (0x29) + #define AHAB_LOG_CID0x21 #define AHAB_AUTH_OEM_CTNR_CID 0x87 #define AHAB_VERIFY_IMG_CID 0x88 diff --git a/arch/arm/mach-imx/imx9/ahab.c b/arch/arm/mach-imx/imx9/ahab.c index 6aa9496..ac69975 100644 --- a/arch/arm/mach-imx/imx9/ahab.c +++ b/arch/arm/mach-imx/imx9/ahab.c @@ -22,36 +22,239 @@ DECLARE_GLOBAL_DATA_PTR; #define IMG_CONTAINER_BASE (0x8000UL) #define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xUL) -#define AHAB_NO_AUTHENTICATION_IND
[PATCH 1/6] misc: sentinel: s400_api: Add get_events API
Add get_events API to retrieve any singular events that has occurred
since the FW has started from sentinel
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 ++
drivers/misc/sentinel/s400_api.c | 45
2 files changed, 47 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index 4819f20..79539b7 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -18,6 +18,7 @@
#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
#define AHAB_READ_FUSE_REQ_CID 0x97
#define AHAB_GET_FW_VERSION_CID0x9D
+#define AHAB_GET_EVENTS_REQ_CID 0xA2
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
#define AHAB_GET_FW_STATUS_CID 0xC5
#define AHAB_WRITE_FUSE_REQ_CID0xD6
@@ -58,5 +59,6 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
int ahab_get_fw_status(u32 *status, u32 *response);
int ahab_release_m33_trout(void);
+int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response);
#endif
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 65032f7..c6b4ef5 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -445,3 +445,48 @@ int ahab_release_m33_trout(void)
return ret;
}
+
+int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
+ int ret, i = 0;
+ u32 actual_events;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ if (!events || !events_cnt || *events_cnt == 0) {
+ printf("Invalid parameters for %s\n", __func__);
+ return -EINVAL;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_GET_EVENTS_REQ_CID;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ if (!ret) {
+ actual_events = msg.data[1] & 0x;
+ if (*events_cnt < actual_events)
+ actual_events = *events_cnt;
+
+ for (; i < actual_events; i++)
+ events[i] = msg.data[i + 2];
+
+ *events_cnt = actual_events;
+ }
+
+ return ret;
+}
--
2.7.4
Re: [EXT] Re: [PATCH] ARM: dts: imx8mm-evk: Fix wrong PMIC device for new EVK board
Hi Marcel, On Tue, 2023-01-17 at 09:16 +, Marcel Ziswiler wrote: > Caution: EXT Email > > Hi Ye Li > > On Tue, 2023-01-17 at 13:34 +0800, Ye Li wrote: > > > > In commit 48ddafd (imx8mm_evk: Switch to new imx8mm evk board), > > the iMX8MM EVK support was updated to new EVK board which is > > using PCA9450A PMIC. > > But the commit 24a7a3c (imx8mm: synchronise device tree with linux) > > changed DTS node back to legacy PMIC which is not aligned with > > SPL codes and defconfig, then cause SPL boot failure. > Please note that I even mentioned this back in the day [1], however, > neither NXP nor anybody else reacted in > any way. > > The correct way would be, of course, to update this in Linux and > subsequently re-syncing with U-Boot. Do you at > least plan to properly update this on the Linux side as well? > Yes, we will upstream this to kernel. I also notice another break on 8ULP EVK which causes no any log. Fix has sent out. Best regards, Ye Li > Thanks! > > [1] https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2 > Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Fcover%2F20220721132748.1052 > 244-1- > marcel%40ziswiler.com%2F=05%7C01%7Cye.li%40nxp.com%7Cd979241c65a > d4161f80a08daf86b833f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63 > 8095437885252506%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoi > V2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C=y1w4PE3% > 2BKoJ%2Beskp%2Bjx54BYq5bLI6SjlUPwTXWUnEB4%3D=0 > > [snip] > > Cheers > > Marcel
[PATCH] ARM: dts: imx8ulp-evk: Fix iomuxc issue
The property fsl,mux_mask is deleted by commit ed7bda5 (imx8ulp:
synchronise device tree with linux). This causes the pinctrl
driver not work on 8ULP, so fail to print any log.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index ad264f2..7acdb4a 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -26,6 +26,7 @@
{
u-boot,dm-spl;
+ fsl,mux_mask = <0xf00>;
};
_lpuart5 {
--
2.7.4
[PATCH] ARM: dts: imx8mm-evk: Fix wrong PMIC device for new EVK board
In commit 48ddafd (imx8mm_evk: Switch to new imx8mm evk board),
the iMX8MM EVK support was updated to new EVK board which is
using PCA9450A PMIC.
But the commit 24a7a3c (imx8mm: synchronise device tree with linux)
changed DTS node back to legacy PMIC which is not aligned with
SPL codes and defconfig, then cause SPL boot failure.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +-
arch/arm/dts/imx8mm-evk.dtsi| 127 +++-
2 files changed, 68 insertions(+), 63 deletions(-)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index d82428f..951017b 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -121,11 +121,11 @@
u-boot,dm-spl;
};
-&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+&{/soc@0/bus@3080/i2c@30a2/pca9450@25} {
u-boot,dm-spl;
};
-&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+&{/soc@0/bus@3080/i2c@30a2/pca9450@25/regulators} {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 7d6317d..766e29a 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -183,115 +183,120 @@
pinctrl-0 = <_i2c1>;
status = "okay";
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
+ pmic: pca9450@25 {
+ reg = <0x25>;
+ compatible = "nxp,pca9450a";
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
pinctrl-0 = <_pmic>;
- interrupt-parent = <>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
-
- #clock-cells = <0>;
- clocks = <_32k 0>;
- clock-output-names = "clk-32k-out";
+ gpio_intr = < 3 GPIO_ACTIVE_LOW>;
regulators {
- buck1_reg: BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <70>;
- regulator-max-microvolt = <130>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9450,pmic-buck2-uses-i2c-dvs;
+ /* Run/Standby voltage */
+ pca9450,pmic-buck2-dvs-voltage = <95>, <85>;
+
+ buck1_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "buck1";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
- regulator-ramp-delay = <1250>;
+ regulator-ramp-delay = <3125>;
};
- buck2_reg: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <70>;
- regulator-max-microvolt = <130>;
+ buck2_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "buck2";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <100>;
- rohm,dvs-idle-voltage = <90>;
+ regulator-ramp-delay = <3125>;
};
- buck3_reg: BUCK3 {
- // BUCK5 in datasheet
- regulator-name = "buck3";
- regulator-min-microvolt = <70>;
- regulator-max-microvolt = <135>;
+ buck3_reg: regulator@2 {
+ reg = <2>;
+ regulator-compatible = "buck3";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-
Re: [EXT] [PATCH] clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock
On Fri, 2022-04-01 at 03:17 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX
> domain.
>
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> ---
> drivers/clk/imx/clk-imx8mp.c | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-
> imx8mp.c
> index c77500bcce0..1aca30d2f71 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -76,6 +76,10 @@ static const char *imx8mp_a53_sels[] = {"clock-
> osc-24m", "arm_pll_out", "sys_pll
> "sys_pll2_1000m",
> "sys_pll1_800m", "sys_pll1_400m",
> "audio_pll1_out",
> "sys_pll3_out", };
>
> +static const char *imx8mp_hsio_axi_sels[] = {"clock-osc-24m",
> "sys_pll2_500m", "sys_pll1_800m",
> +"sys_pll2_100m",
> "sys_pll2_200m", "clk_ext2",
> +"clk_ext4",
> "audio_pll2_out", };
> +
> static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m",
> "sys_pll2_333m", "sys_pll1_800m",
> "sys_pll2_250m",
> "sys_pll2_1000m", "audio_pll1_out",
> "video_pll1_out",
> "sys_pll1_100m",};
> @@ -156,6 +160,14 @@ static const char *imx8mp_uart4_sels[] =
> {"clock-osc-24m", "sys_pll1_80m", "sys_
> "sys_pll2_100m",
> "sys_pll3_out", "clk_ext2",
> "clk_ext3",
> "audio_pll2_out", };
>
> +static const char *imx8mp_usb_core_ref_sels[] = {"clock-osc-24m",
> "sys_pll1_100m", "sys_pll1_40m",
> +"sys_pll2_100m",
> "sys_pll2_200m", "clk_ext2",
> +"clk_ext3",
> "audio_pll2_out", };
> +
> +static const char *imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m",
> "sys_pll1_100m", "sys_pll1_40m",
> + "sys_pll2_100m",
> "sys_pll2_200m", "clk_ext2",
> + "clk_ext3",
> "audio_pll2_out", };
> +
> static const char *imx8mp_gic_sels[] = {"clock-osc-24m",
> "sys_pll2_200m", "sys_pll1_40m",
> "sys_pll2_100m",
> "sys_pll1_800m",
> "sys_pll2_500m", "clk_ext4",
> "audio_pll2_out" };
> @@ -324,6 +336,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
> clk_dm(IMX8MP_SYS_PLL2_500M,
> imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
> clk_dm(IMX8MP_SYS_PLL2_1000M,
> imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
>
> + clk_dm(IMX8MP_CLK_24M, imx_clk_fixed_factor("clock-osc-24m",
> "osc_24m", 1, 1));
osc_24m is an fixed-rate clock device. no need to register it again.
Just using below codes to get the device probed, then assign id to it.
struct clk osc_24m_clk;
ret = clk_get_by_name(dev, "osc_24m", _24m_clk);
if (ret)
return ret;
clk_dm(IMX8MP_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
Best regards,
Ye Li
> +
> base = dev_read_addr_ptr(dev);
> if (!base)
> return -EINVAL;
> @@ -332,6 +346,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
> clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg",
> "arm_a53_src", base + 0x8000, 28));
> clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div",
> "arm_a53_cg", base + 0x8000, 0, 3));
>
> + clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi",
> imx8mp_hsio_axi_sels, base + 0x8380));
> clk_dm(IMX8MP_CLK_MAIN_AXI,
> imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base +
> 0x8800));
> clk_dm(IMX8MP_CLK_ENET_AXI,
> imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base +
> 0x8880));
> clk_dm(IMX8MP_CLK_NAND_USDHC_BUS,
> imx8m_clk_composit
[PATCH v2] mtd: rawnand: mxs_nand: Fix use_minimum_ecc for spl driver
Because mxs_nand_spl driver does not support DM, to use the minimum ECC layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC. Signed-off-by: Ye Li Reviewed-by: Han Xu --- Changes in v2: - Use IS_ENABLED to replace #ifdef drivers/mtd/nand/raw/mxs_nand.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index ee5d7fd..0c4e559 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1380,6 +1380,9 @@ int mxs_nand_init_spl(struct nand_chip *nand) else nand_info->max_ecc_strength_supported = 40; + if (IS_ENABLED(CONFIG_NAND_MXS_USE_MINIMUM_ECC)) + nand_info->use_minimum_ecc = true; + err = mxs_nand_alloc_buffers(nand_info); if (err) return err; -- 2.7.4
Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset
On Thu, 2022-03-31 at 00:27 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/29/22 11:56, Ye Li wrote:
>
> Hi,
>
> >
> > >
> > > >
> > > > But once you want to upgrade the
> > > > flash.bin, flexspi configurations will also be erased due to
> > > > the
> > > > block
> > > > size. Then you have to reprogram the configurations with
> > > > flash.bin.
> > > > So most of our customers add the flexspi configurations to
> > > > flash.bin
> > > > head. They don't use so called one image for both SD and
> > > > flexspi.
> > > There are no upstream users of flexspi right now, see above.
> > >
> > > >
> > > >
> > > > As the spl_romapi_get_uboot_base is defined to weak. It is
> > > > better
> > > > to
> > > > overwrite this function for your particular usage.
> > > I would much rather prefer to have one flash.bin which works on
> > > both
> > > SD
> > > card and FlexSPI, on all iMX8M, that is far less confusing. And
> > > since
> > > there are no upstream users of flexspi boot so far, this is how
> > > it
> > > can
> > > still be implemented, consistently.
> > I can think out 3 drawbacks using this one flash.bin for flexspi:
> >
> > 1. The flexspi configuration header will be erased when you update
> > the
> > flash.bin to flexspi device. In a common usage, this header will
> > combine with flash.bin to a final boot image which is not same with
> > SD.
> This is not correct.
>
> If you need to update only the flash.bin in SPI NOR without rewriting
> the FCFB header, use 'sf update' with 0x1000 start address:
> dhcp ${loadaddr} 192.168.1.1:flash.bin && \
> sf update ${loadaddr} 0x1000 ${filesize}
>
> If you need to update both the flash.bin and generate the FCFB, use
> the
> aforementioned script with sf update using 0x0 start address, i.e.:
> dhcp ${loadaddr} 192.168.1.1:flash.bin ; \
> \
> setexpr sfaddr ${loadaddr} - 0x1000 ; \
> \
> base ${sfaddr} ; \
> mw 0 0 0x400 ; \
> mw 0x400 0x42464346 ; \
> mw 0x404 0x5601 ; \
> mw 0x40c 00030300 ; \
> mw 0x444 0x00020101 ; \
> mw 0x450 0x1000 ; \
> mw 0x480 0x0818040b ; \
> mw 0x484 0x24043008 ; \
> mw 0x5c0 0x100 ; \
> mw 0x5c4 0x1 ; \
> base 0 ; \
> \
> setexpr filesize ${filesize} + 0x1000 ; \
> \
> sf probe && sf update ${sfaddr} 0 ${filesize}
>
> >
> > 2. How can users update u-boot.itb only if using this one
> > flash.bin?
> Write u-boot.itb to offset 0x59000 in SPI NOR:
> => sf update ${loadaddr} 0x59000 ${filesize}
>
> That 0x59000 is ( imx8mp-u-boot.dtsi /imx-boot/blob-ext@2/offset =
> <0x58000>) + (the SPI NOR flash.bin offset = 0x1000) = 0x59000
>
> >
> > With the same offset of SD, it causes the u-boot.itb locates at a
> > offset not block aligned.
> 0x59000 is both 4 kiB and 512 Byte aligned .
4KB is not a erase block size supported by all NOR flash. You should
use 64KB which is default to all.
Same for #1 drawback, 0x1000 offset can't satify the erase block size.
so every time your update flash.bin will need to update flash
configuration header as well, why not combine them together.
>
> >
> > 3. Not all iMX8M can support this one flash.bin. 8MM and 8MQ have
> > different IVT. Their flexspi IVT can't work for SD/eMMC.
> What's the difference ? Looking at the MX8MM RM rev.3, FlexSPI boot
> looks very much the same.
>
No. The IVT structures are same but the base used by the fields in IVT
is changed. So you can't use one image for flexspi and SD, it will fail
to boot.
Another thing is the from imx8mm-u-boot.dtsi. the offset is 0x57c00. it
even does not align with 4KB.
binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x57c00>;
type = "blob-ext";
};
Best regards,
Ye Li
> (we have no MX8MQ/MX8MM boards which boot from FlexSPI either).
>
> ...
>
> I still believe it is better (=less confusing for users) to have one
> unified flash.bin for all boot media.
Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset
On Tue, 2022-03-29 at 11:01 +0200, Marek Vasut wrote: > Caution: EXT Email > > On 3/29/22 04:49, Ye Li wrote: > > Hi, > > > > > > > > > > > > > > If you change the ROM API driver, that will break our design. > > > > You > > > > can > > > > try to overwrite spl_romapi_get_uboot_base for your board only. > > > Since there are no users which boot from flexspi upstream, this > > > design > > > can still be fixed such that it does not require different > > > flash.bin > > > for > > > different boot media, but rather one flash.bin works on all boot > > > media. > > > I think that is much better. > > Your flash.bin can work on flexspi because you manually program the > > flexspi configurations header. > Sure, the header content is described in the MX8MP RM Rev. 1 06/2021 > "6.1.5.3.1 FlexSPI Configuration Block", this has nothing to do with > this patch. > > > > > But once you want to upgrade the > > flash.bin, flexspi configurations will also be erased due to the > > block > > size. Then you have to reprogram the configurations with flash.bin. > > So most of our customers add the flexspi configurations to > > flash.bin > > head. They don't use so called one image for both SD and flexspi. > There are no upstream users of flexspi right now, see above. > > > > > As the spl_romapi_get_uboot_base is defined to weak. It is better > > to > > overwrite this function for your particular usage. > I would much rather prefer to have one flash.bin which works on both > SD > card and FlexSPI, on all iMX8M, that is far less confusing. And since > there are no upstream users of flexspi boot so far, this is how it > can > still be implemented, consistently. I can think out 3 drawbacks using this one flash.bin for flexspi: 1. The flexspi configuration header will be erased when you update the flash.bin to flexspi device. In a common usage, this header will combine with flash.bin to a final boot image which is not same with SD. 2. How can users update u-boot.itb only if using this one flash.bin? With the same offset of SD, it causes the u-boot.itb locates at a offset not block aligned. 3. Not all iMX8M can support this one flash.bin. 8MM and 8MQ have different IVT. Their flexspi IVT can't work for SD/eMMC. Best regards, Ye Li > > If downstream wants to have multiple flash.bin, one for each boot > media, > that's up to downstream. > > [...]
[PATCH] mtd: rawnand: mxs_nand: Fix use_minimum_ecc for spl driver
Because mxs_nand_spl driver does not support DM, to use the minimum ECC layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC. Signed-off-by: Ye Li --- drivers/mtd/nand/raw/mxs_nand.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index ee5d7fd..28e189a 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1380,6 +1380,10 @@ int mxs_nand_init_spl(struct nand_chip *nand) else nand_info->max_ecc_strength_supported = 40; +#ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC + nand_info->use_minimum_ecc = true; +#endif + err = mxs_nand_alloc_buffers(nand_info); if (err) return err; -- 2.7.4
Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset
On Mon, 2022-03-28 at 16:54 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/28/22 08:54, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> [...]
>
> >
> > >
> > > >
> > > > 2. Update the u-boot.itb offset in imx8mp-u-boot.dtsi, set the
> > > > offset
> > > > to 0x5f000. The previous offset 0x58000 is for SD, calculated
> > > > by
> > > > 0x6 - 0x8000 (32KB image offset).
> > > >
> > > > uboot: blob-ext@2 {
> > > > filename = "u-boot.itb";
> > > > offset = <0x5f000>;
> > > > };
> > > But that breaks booting from SD card for me ?
> > Do you want to use one flash.bin for both SD and flexspi?
> Yes, the board I use can boot from SD/eMMC/FlexSPI. I don't want to
> build multiple confusing "flash.bin" files, one for each boot media.
>
> >
> > When first introduced 8m support by imx8mimage.c, we expected the
> > u-
> > boot.itb at same device offset (0x6) on SD/emmc and flexspi.
> > The
> > imx8mimage will calculate the offset inside the flash.bin
> > automatically
> > according to different IVT offset. The ROMAPI driver also works
> > correspondingly.
> > After using binman, the u-boot.itb offset inside the flash.bin has
> > to
> > be manually set in this DTS node. To follow the original design,
> > this
> > offset should be different. That's why I asked to update this dts
> > node
> > for flexspi.
> This does imply that there are currently no users that boot from
> flexspi
> in upstream U-Boot, because such users would have to manually modify
> both arch/arm/dts/imx8m?-u-boot.dtsi and board/*/imximage.cfg to
> generate suitable flash.bin which can be started from FlexSPI.
>
> Also, git grep confirms that there are no users:
>
> u-boot$ git grep BOOT_FROM.*fspi
> doc/imx/mkimage/imx8image.txt:BOOT_FROM
> [sd|emmc_fastboot|fspi|nand_4k|nand_8k|nand_16k] [sector_size]
>
> >
> > If you change the ROM API driver, that will break our design. You
> > can
> > try to overwrite spl_romapi_get_uboot_base for your board only.
> Since there are no users which boot from flexspi upstream, this
> design
> can still be fixed such that it does not require different flash.bin
> for
> different boot media, but rather one flash.bin works on all boot
> media.
> I think that is much better.
Your flash.bin can work on flexspi because you manually program the
flexspi configurations header. But once you want to upgrade the
flash.bin, flexspi configurations will also be erased due to the block
size. Then you have to reprogram the configurations with flash.bin.
So most of our customers add the flexspi configurations to flash.bin
head. They don't use so called one image for both SD and flexspi.
As the spl_romapi_get_uboot_base is defined to weak. It is better to
overwrite this function for your particular usage.
Best regards,
Ye Li
>
> [...]
[PATCH] mtd: nand: mxs_nand_spl: Remove the page aligned access
The mxs_nand_spl driver can support to read from page unaligned offset,
so don't need to set bl_len to ask spl_load_simple_fit to handle
the page unaligned access.
Actually spl_load_simple_fit has two parts of reading:
spl_simple_fit_read and spl_load_fit_image.
The spl_load_fit_image can handle the page unaligned offset,
but the spl_simple_fit_read can't do it. spl_simple_fit_read requires
the FIT location at page aligned offset.
Hence, remove the nand_get_mtd overwrite function from mxs_nand_spl
to use page unaligned read by driver.
Signed-off-by: Ye Li
---
drivers/mtd/nand/raw/mxs_nand_spl.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c
b/drivers/mtd/nand/raw/mxs_nand_spl.c
index 9e0b8afb..59a67ee 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -283,11 +283,6 @@ int nand_spl_load_image(uint32_t offs, unsigned int size,
void *buf)
return 0;
}
-struct mtd_info *nand_get_mtd(void)
-{
- return mtd;
-}
-
int nand_default_bbt(struct mtd_info *mtd)
{
return 0;
--
2.7.4
[PATCH] usb_hub: Set DM_FLAG_DEFAULT_PD_CTRL_OFF to usb_hub driver
Because usb_hub uses same device tree node with USB controller device,
when probe and remove usb_hub, it will call the power domain control of
USB controller device.
This is not expected, because power domain control implmentation may not
have count when the power domain is dedicated for USB controller. So once
removed usb_hub, the power domain is power off before removing USB controller.
Signed-off-by: Ye Li
---
common/usb_hub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index ba11a18..990993a 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -950,7 +950,7 @@ U_BOOT_DRIVER(usb_generic_hub) = {
.name = "usb_hub",
.id = UCLASS_USB_HUB,
.of_match = usb_hub_ids,
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
+ .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
UCLASS_DRIVER(usb_hub) = {
--
2.7.4
Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset
Hi Marek,
On Wed, 2022-03-23 at 22:16 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/23/22 03:42, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> >
> > >
> > > >
> > > > >
> > > > > diff --git a/arch/arm/mach-imx/spl_imx_romapi.c
> > > > > b/arch/arm/mach-
> > > > > imx/spl_imx_romapi.c
> > > > > index d827de375a6..c47f5a6bdb4 100644
> > > > > --- a/arch/arm/mach-imx/spl_imx_romapi.c
> > > > > +++ b/arch/arm/mach-imx/spl_imx_romapi.c
> > > > > @@ -38,14 +38,8 @@ ulong spl_romapi_raw_seekable_read(u32
> > > > > offset,
> > > > > u32
> > > > > size, void *buf)
> > > > >
> > > > > ulong __weak spl_romapi_get_uboot_base(u32 image_offset,
> > > > > u32
> > > > > rom_bt_dev)
> > > > > {
> > > > > - u32 offset;
> > > > > -
> > > > > - if (((rom_bt_dev >> 16) & 0xff)
> > > > > == BT_DEV_TYPE_FLEXSPINOR)
> > > > > - offset =
> > > > > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
> > > > > *
> > > > > 512;
> > > > > - else
> > > > > - offset = image_offset +
> > > > > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;
> > > > > -
> > > > > - return offset;
> > > > > + return image_offset +
> > > > > + (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> > > > > 512 -
> > > > > 0x8000);
> > > > > }
> > > > The change is problematic to flexspi.
> > > Yes, I need this change to get boot from flexspi working on
> > > i.MX8MP,
> > > without this change writing flash.bin to flexspi results in
> > > unbootable
> > > system.
> > >
> > To support boot from flexspi, please try another two changes.
> > 1. Modify board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg, set
> > "BOOT_FROM" to "fspi". (This change is unnecessary on 8MP after
> > switch to binman)
> I already use binman and I need to be able to boot from both SD and
> FlexSPI, with this patch I can do just that.
>
> >
> > 2. Update the u-boot.itb offset in imx8mp-u-boot.dtsi, set the
> > offset
> > to 0x5f000. The previous offset 0x58000 is for SD, calculated by
> > 0x6 - 0x8000 (32KB image offset).
> >
> > uboot: blob-ext@2 {
> > filename = "u-boot.itb";
> > offset = <0x5f000>;
> > };
> But that breaks booting from SD card for me ?
Do you want to use one flash.bin for both SD and flexspi?
When first introduced 8m support by imx8mimage.c, we expected the u-
boot.itb at same device offset (0x6) on SD/emmc and flexspi. The
imx8mimage will calculate the offset inside the flash.bin automatically
according to different IVT offset. The ROMAPI driver also works
correspondingly.
After using binman, the u-boot.itb offset inside the flash.bin has to
be manually set in this DTS node. To follow the original design, this
offset should be different. That's why I asked to update this dts node
for flexspi.
If you change the ROM API driver, that will break our design. You can
try to overwrite spl_romapi_get_uboot_base for your board only.
Best regards,
Ye Li
Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset
Hi Marek,
On Mon, 2022-03-21 at 15:59 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/21/22 04:35, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> >
> > >
> > > diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-
> > > imx/spl_imx_romapi.c
> > > index d827de375a6..c47f5a6bdb4 100644
> > > --- a/arch/arm/mach-imx/spl_imx_romapi.c
> > > +++ b/arch/arm/mach-imx/spl_imx_romapi.c
> > > @@ -38,14 +38,8 @@ ulong spl_romapi_raw_seekable_read(u32 offset,
> > > u32
> > > size, void *buf)
> > >
> > > ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32
> > > rom_bt_dev)
> > > {
> > > - u32 offset;
> > > -
> > > - if (((rom_bt_dev >> 16) & 0xff)
> > > == BT_DEV_TYPE_FLEXSPINOR)
> > > - offset = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
> > > *
> > > 512;
> > > - else
> > > - offset = image_offset +
> > > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;
> > > -
> > > - return offset;
> > > + return image_offset +
> > > + (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 -
> > > 0x8000);
> > > }
> > The change is problematic to flexspi.
> Yes, I need this change to get boot from flexspi working on i.MX8MP,
> without this change writing flash.bin to flexspi results in
> unbootable
> system.
>
To support boot from flexspi, please try another two changes.
1. Modify board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg, set
"BOOT_FROM" to "fspi". (This change is unnecessary on 8MP after
switch to binman)
2. Update the u-boot.itb offset in imx8mp-u-boot.dtsi, set the offset
to 0x5f000. The previous offset 0x58000 is for SD, calculated by
0x6 - 0x8000 (32KB image offset).
uboot: blob-ext@2 {
filename = "u-boot.itb";
offset = <0x5f000>;
};
Best regards,
Ye Li
> >
> > Actually u-boot.itb is fixed at device offset 0x6 (= 512 *
> > 0x300)
> > for flexspi/emmc/sd.The case is the image_offset for emmc/sd may
> > vary according to the
> > primary boot or secondary boot and the eMMC user partition or boot
> > partition.
> >
> > If you changed to "image_offset +
> > (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000", the
> > address
> > for flexspi becomes 0x59000 (= 0x1000 + 0x6 - 0x8000)
> This is how I populate the FlexSPI on MX8MP:
>
> dhcp ${loadaddr} 192.168.1.1:flash.bin ; \
> \
> setexpr sfaddr ${loadaddr} - 0x1000 ; \
> \
> base ${sfaddr} ; \
> mw 0 0 0x400 ; \
> mw 0x400 0x42464346 ; \
> mw 0x404 0x5601 ; \
> mw 0x40c 00030300 ; \
> mw 0x444 0x00020101 ; \
> mw 0x450 0x1000 ; \
> mw 0x480 0x0818040b ; \
> mw 0x484 0x24043008 ; \
> mw 0x5c0 0x100 ; \
> mw 0x5c4 0x1 ; \
> base 0 ; \
> \
> setexpr filesize ${filesize} + 0x1000 ; \
> \
> sf probe && sf update ${sfaddr} 0 ${filesize}
Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset
Hi Marek,
On Wed, 2022-03-09 at 17:09 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> The FlexSPI NOR boot offset does not require any special handling,
> the image_offset is correct in either case (0x1000 for FlexSPI NOR
> and 0x8000 for SD/eMMC) and the offset of u-boot.itb from the start
> of flash.bin is always 0x58000 on MX8MN/MX8MP, which matches the
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000 in case
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300, which is always the
> case on MX8MN/MX8MP.
>
> The CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is really overloaded in
> case of the MX8MN/MX8MP, but fixing that needs additional plumbing.
>
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> ---
> arch/arm/mach-imx/spl_imx_romapi.c | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-
> imx/spl_imx_romapi.c
> index d827de375a6..c47f5a6bdb4 100644
> --- a/arch/arm/mach-imx/spl_imx_romapi.c
> +++ b/arch/arm/mach-imx/spl_imx_romapi.c
> @@ -38,14 +38,8 @@ ulong spl_romapi_raw_seekable_read(u32 offset, u32
> size, void *buf)
>
> ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32
> rom_bt_dev)
> {
> - u32 offset;
> -
> - if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_FLEXSPINOR)
> - offset = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> 512;
> - else
> - offset = image_offset +
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;
> -
> - return offset;
> + return image_offset +
> + (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 -
> 0x8000);
> }
The change is problematic to flexspi.
Actually u-boot.itb is fixed at device offset 0x6 (= 512 * 0x300)
for flexspi/emmc/sd.The case is the image_offset for emmc/sd may vary according
to the
primary boot or secondary boot and the eMMC user partition or boot
partition.
If you changed to "image_offset +
(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000", the address
for flexspi becomes 0x59000 (= 0x1000 + 0x6 - 0x8000)
Best regards,
Ye Li
>
> static int is_boot_from_stream_device(u32 boot)
> --
> 2.34.1
>
Re: [EXT] Re: [PATCH] imx: Revert "imx: mx6ull: fix REFTOP_VBGADJ setting" and fix comments
Hi Michael,
On Fri, 2022-03-11 at 15:01 +0100, Dario Binacchi wrote:
> Caution: EXT Email
>
> Hi,
>
> On Fri, Mar 11, 2022 at 1:26 PM Ye Li wrote:
> >
> >
> > Hi Michael,
> >
> > On Fri, 2022-03-11 at 08:57 +0100, Michael Nazzareno Trimarchi
> > wrote:
> > >
> > > Caution: EXT Email
> > >
> > > Hi
> > >
> > > On Tue, Mar 8, 2022 at 7:42 AM Ye Li wrote:
> > > >
> > > >
> > > >
> > > > The change in commit c1af358 (imx: mx6ull: fix REFTOP_VBGADJ
> > > > setting)
> > > > is not correct. According to latest i.MX6ULL fuse table,
> > > > the REFTOP_TRIM[2:0] fuse is defined as below. So the previous
> > > > codes
> > > > are correct, only need to fix the comments.
> > > >
> > > > Set the REFTOP_VBGADJ field in PMU_MISC0 register based on the
> > > > REFTOP_TRIM fuse:
> > > > '000" - set REFTOP_VBGADJ[2:0] to 3'b000
> > > > '001" - set REFTOP_VBGADJ[2:0] to 3'b001
> > > > '010" - set REFTOP_VBGADJ[2:0] to 3'b010
> > > > '011" - set REFTOP_VBGADJ[2:0] to 3'b011
> > > > '100" - set REFTOP_VBGADJ[2:0] to 3'b100
> > > > '101" - set REFTOP_VBGADJ[2:0] to 3'b101
> > > > '110" - set REFTOP_VBGADJ[2:0] to 3'b110
> > > > '111" - set REFTOP_VBGADJ[2:0] to 3'b111
> > > >
> > > > Signed-off-by: Ye Li
> > > > ---
> > > > arch/arm/mach-imx/mx6/soc.c | 20 +---
> > > > 1 file changed, 9 insertions(+), 11 deletions(-)
> > > >
> > > > diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-
> > > > imx/mx6/soc.c
> > > > index 03d8fd7..bb7dc42 100644
> > > > --- a/arch/arm/mach-imx/mx6/soc.c
> > > > +++ b/arch/arm/mach-imx/mx6/soc.c
> > > > @@ -394,23 +394,21 @@ static void init_bandgap(void)
> > > > /*
> > > > * On i.MX6ULL,we need to set VBGADJ bits according to
> > > > the
> > > > * REFTOP_TRIM[3:0] in fuse table
> > > > -* 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
> > > > -* 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
> > > > -* 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
> > > > -* 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
> > > > -* 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
> > > > -* 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
> > > > -* 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
> > > > -* 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
> > > > +* 000 - set REFTOP_VBGADJ[2:0] to 3'b000
> > > > +* 001 - set REFTOP_VBGADJ[2:0] to 3'b001
> > > > +* 010 - set REFTOP_VBGADJ[2:0] to 3'b010
> > > > +* 011 - set REFTOP_VBGADJ[2:0] to 3'b011
> > > > +* 100 - set REFTOP_VBGADJ[2:0] to 3'b100
> > > > +* 101 - set REFTOP_VBGADJ[2:0] to 3'b101
> > > > +* 110 - set REFTOP_VBGADJ[2:0] to 3'b110
> > > > +* 111 - set REFTOP_VBGADJ[2:0] to 3'b111
> > > > */
> > > > if (is_mx6ull()) {
> > > > - static const u32 map[] = {6, 1, 2, 3, 4, 5, 0,
> > > > 7};
> > > > -
> > > > val = readl(>mem0);
> > > > val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
> > > > val &= 0x7;
> > > >
> > > > - writel(map[val] <<
> > > > BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
> > > > + writel(val <<
> > > > BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
> > > > >ana_misc0_set);
> > > > }
> > > If this is the case. I have the impression there are a lot of
> > > cpus
> > > that have this fuse not set during manufacturing.
> > Most of iMX6 series don't need to program this fuse, but 6ull is a
> > exception due to different process used. if your 6ull don't have
> > the
> > fuse programmed, please contact NXP support team.
> >
> > >
> > > If this can happen if we have devices in the field already
> > > programmed
> > > that they do any temperature evaluation for thermal
> > > framework the calculation start to be different and they can have
Re: [EXT] Re: GPMI NAND Regression on i.MX6S
Hi Frieder, On Thu, 2022-03-17 at 09:06 +0100, Frieder Schrempf wrote: > Caution: EXT Email > > Hi Tim, > > Am 16.03.22 um 17:34 schrieb Tim Harvey: > > > > On Wed, Mar 16, 2022 at 7:09 AM Fabio Estevam > > wrote: > > > > > > > > > Adding Han Xu's NXP email on Cc. > > > > > > On Mon, Mar 14, 2022 at 10:31 AM Frieder Schrempf > > > wrote: > > > > > > > > > > > > Hello everyone, > > > > > > > > sorry to dig out an old thread, but the below patch which was > > > > applied > > > > upstream as 616f03dabacb causes a regression for me when trying > > > > to > > > > attach an UBI volume with U-Boot 2022.01 on a board with i.MX6 > > > > Solo and > > > > AMD/Spansion parallel NAND. > > > > > > > > The failure looks like this: > > > > > > > > ubi0: attaching mtd2 > > > > ubi0 error: ubi_io_read: error -74 (ECC error) while reading 64 > > > > bytes > > > > from PEB 0:0, read 64 bytes > > > > ubi0 error: ubi_io_read: error -74 (ECC error) while reading > > > > 2048 bytes > > > > from PEB 0:2048, read 2048 bytes > > > > ubi0 error: ubi_io_read: error -74 (ECC error) while reading 64 > > > > bytes > > > > from PEB 1:0, read 64 bytes > > > > ubi0 error: ubi_io_read: error -74 (ECC error) while reading > > > > 2048 bytes > > > > from PEB 1:2048, read 2048 bytes > > > > > > > > The NAND as reported by Linux is: > > > > > > > > nand: device found, Manufacturer ID: 0x01, Chip ID: 0xdc > > > > nand: AMD/Spansion S34ML04G1 > > > > nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB > > > > size: 64 > > > > > > > > A different revision of the same board with a different NAND > > > > from > > > > manufacturer ESMT doesn't show the issue: > > > > > > > > nand: device found, Manufacturer ID: 0xc8, Chip ID: 0xdc > > > > nand: ESMT NAND 512MiB 3,3V 8-bit > > > > nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB > > > > size: 64 > > > > > > > > When I revert the mentioned commit (see patch here: [1]), the > > > > UBI boot > > > > starts working again. > > > > > > > > Does anyone know what the problem is and how to properly solve > > > > it? > > > > > > > > Thanks for any help! > > > > Frieder > > > > > > > > [1] > > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F > > > > %2Fzerobin.net%2F%3F57a57a322bbdcf3c%23rZa3vHlWi%2BRxtRomoljtrn > > > > gqWwiv6v4Js%2F2LNfdV10o%3Ddata=04%7C01%7Cye.li%40nxp.com%7 > > > > Cee3b85ceee3d4ece78e108da07ed1e2c%7C686ea1d3bc2b4c6fa92cd99c5c3 > > > > 01635%7C0%7C0%7C637831012279864791%7CUnknown%7CTWFpbGZsb3d8eyJW > > > > IjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% > > > > 7C3000sdata=O6MzwCv9ClB8ZW7i3%2BV1RmOaviGqQRNa8L0uxE4M%2F% > > > > 2BI%3Dreserved=0 > > > > > > Frieder, > > > > I see the same issue here with IMX6Q/DL GPMI NAND. > > > > If I re-flash the ubi within U-Boot (tftpboot $loadaddr rootfs.ubi > > && > > nand erase.part rootfs && nand write $loadaddr rootfs $filesize) I > > find that U-Boot can attach and mount the ubi fine but Linux will > > have > > issues > Interesting! This sounds like U-Boot and Linux somehow diverge in how > they handle the ECC data in OOB. I'm pretty confident that Linux does > things "correctly" and U-Boot should match what Linux does in this > case. > > Does the patch (revert of 616f03dabacb) I mentioned before "solve" > the > issue for your case, too? > > @Han, Ye, Peng: As you signed-off the mentioned commit, do you have > any > ideas for a fix? The dt nand driver will check "fsl,legacy-bch-geometry" property to use legacy bch. If this can't work for you in case you don't use DM driver, I prefer adding a config to select the legacy bch not reverting the patch. Best regards, Ye Li > > Thanks > Frieder
[PATCH] imx8ulp: Disable SPL exception vector
Disable SPL exception vector which causes issue to ROM patch execution when SPL calling ROM API. Signed-off-by: Ye Li --- arch/arm/mach-imx/imx8ulp/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index 963fc93..d8b5ef7 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -2,7 +2,6 @@ if ARCH_IMX8ULP config IMX8ULP bool - select ARMV8_SPL_EXCEPTION_VECTORS config SYS_SOC default "imx8ulp" -- 2.7.4
Re: [EXT] Re: [PATCH] imx: Revert "imx: mx6ull: fix REFTOP_VBGADJ setting" and fix comments
Hi Michael,
On Fri, 2022-03-11 at 08:57 +0100, Michael Nazzareno Trimarchi wrote:
> Caution: EXT Email
>
> Hi
>
> On Tue, Mar 8, 2022 at 7:42 AM Ye Li wrote:
> >
> >
> > The change in commit c1af358 (imx: mx6ull: fix REFTOP_VBGADJ
> > setting)
> > is not correct. According to latest i.MX6ULL fuse table,
> > the REFTOP_TRIM[2:0] fuse is defined as below. So the previous
> > codes
> > are correct, only need to fix the comments.
> >
> > Set the REFTOP_VBGADJ field in PMU_MISC0 register based on the
> > REFTOP_TRIM fuse:
> > '000" - set REFTOP_VBGADJ[2:0] to 3'b000
> > '001" - set REFTOP_VBGADJ[2:0] to 3'b001
> > '010" - set REFTOP_VBGADJ[2:0] to 3'b010
> > '011" - set REFTOP_VBGADJ[2:0] to 3'b011
> > '100" - set REFTOP_VBGADJ[2:0] to 3'b100
> > '101" - set REFTOP_VBGADJ[2:0] to 3'b101
> > '110" - set REFTOP_VBGADJ[2:0] to 3'b110
> > '111" - set REFTOP_VBGADJ[2:0] to 3'b111
> >
> > Signed-off-by: Ye Li
> > ---
> > arch/arm/mach-imx/mx6/soc.c | 20 +---
> > 1 file changed, 9 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-
> > imx/mx6/soc.c
> > index 03d8fd7..bb7dc42 100644
> > --- a/arch/arm/mach-imx/mx6/soc.c
> > +++ b/arch/arm/mach-imx/mx6/soc.c
> > @@ -394,23 +394,21 @@ static void init_bandgap(void)
> > /*
> > * On i.MX6ULL,we need to set VBGADJ bits according to the
> > * REFTOP_TRIM[3:0] in fuse table
> > -* 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
> > -* 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
> > -* 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
> > -* 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
> > -* 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
> > -* 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
> > -* 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
> > -* 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
> > +* 000 - set REFTOP_VBGADJ[2:0] to 3'b000
> > +* 001 - set REFTOP_VBGADJ[2:0] to 3'b001
> > +* 010 - set REFTOP_VBGADJ[2:0] to 3'b010
> > +* 011 - set REFTOP_VBGADJ[2:0] to 3'b011
> > +* 100 - set REFTOP_VBGADJ[2:0] to 3'b100
> > +* 101 - set REFTOP_VBGADJ[2:0] to 3'b101
> > +* 110 - set REFTOP_VBGADJ[2:0] to 3'b110
> > +* 111 - set REFTOP_VBGADJ[2:0] to 3'b111
> > */
> > if (is_mx6ull()) {
> > - static const u32 map[] = {6, 1, 2, 3, 4, 5, 0, 7};
> > -
> > val = readl(>mem0);
> > val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
> > val &= 0x7;
> >
> > - writel(map[val] <<
> > BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
> > + writel(val <<
> > BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
> > >ana_misc0_set);
> > }
> If this is the case. I have the impression there are a lot of cpus
> that have this fuse not set during manufacturing.
Most of iMX6 series don't need to program this fuse, but 6ull is a
exception due to different process used. if your 6ull don't have the
fuse programmed, please contact NXP support team.
> If this can happen if we have devices in the field already programmed
> that they do any temperature evaluation for thermal
> framework the calculation start to be different and they can have
> impact on their device
I don't understand this.
Anyway, both NXP manufacturing and SW need to follow the fuse value
definition.
Best regards,
Ye Li
>
> Michael
>
> >
> > }
> > --
> > 2.7.4
> >
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.
> amarulasolutions.com%2Fdata=04%7C01%7Cye.li%40nxp.com%7C18373707
> 3bca4b167e1808da0334d5fc%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7
> C637825822708088241%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQI
> joiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=jZ0z1fFhG9
> %2BmQ7pB94C4RPEEwCg2IxMvhRluxs7HcQc%3Dreserved=0
[PATCH] imx: Revert "imx: mx6ull: fix REFTOP_VBGADJ setting" and fix comments
The change in commit c1af358 (imx: mx6ull: fix REFTOP_VBGADJ setting)
is not correct. According to latest i.MX6ULL fuse table,
the REFTOP_TRIM[2:0] fuse is defined as below. So the previous codes
are correct, only need to fix the comments.
Set the REFTOP_VBGADJ field in PMU_MISC0 register based on the
REFTOP_TRIM fuse:
'000" - set REFTOP_VBGADJ[2:0] to 3'b000
'001" - set REFTOP_VBGADJ[2:0] to 3'b001
'010" - set REFTOP_VBGADJ[2:0] to 3'b010
'011" - set REFTOP_VBGADJ[2:0] to 3'b011
'100" - set REFTOP_VBGADJ[2:0] to 3'b100
'101" - set REFTOP_VBGADJ[2:0] to 3'b101
'110" - set REFTOP_VBGADJ[2:0] to 3'b110
'111" - set REFTOP_VBGADJ[2:0] to 3'b111
Signed-off-by: Ye Li
---
arch/arm/mach-imx/mx6/soc.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 03d8fd7..bb7dc42 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -394,23 +394,21 @@ static void init_bandgap(void)
/*
* On i.MX6ULL,we need to set VBGADJ bits according to the
* REFTOP_TRIM[3:0] in fuse table
-* 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
-* 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
-* 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
-* 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
-* 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
-* 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
-* 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
-* 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
+* 000 - set REFTOP_VBGADJ[2:0] to 3'b000
+* 001 - set REFTOP_VBGADJ[2:0] to 3'b001
+* 010 - set REFTOP_VBGADJ[2:0] to 3'b010
+* 011 - set REFTOP_VBGADJ[2:0] to 3'b011
+* 100 - set REFTOP_VBGADJ[2:0] to 3'b100
+* 101 - set REFTOP_VBGADJ[2:0] to 3'b101
+* 110 - set REFTOP_VBGADJ[2:0] to 3'b110
+* 111 - set REFTOP_VBGADJ[2:0] to 3'b111
*/
if (is_mx6ull()) {
- static const u32 map[] = {6, 1, 2, 3, 4, 5, 0, 7};
-
val = readl(>mem0);
val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
val &= 0x7;
- writel(map[val] << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
+ writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
>ana_misc0_set);
}
}
--
2.7.4
Re: [EXT] [PATCH] crypto/fsl: Fallback to SW sha1/256 is misaligned buffers
On Fri, 2021-11-05 at 10:42 +0100, Christian Sørensen wrote:
> Caution: EXT Email
>
> Problem:
> With U-Boot 2021.10, we currently cannot load a fitImage on our imx7d
> board, due to misaligned buffers.
>
> Reason:
> Commit 92055e138f28 ("image: Drop if/elseif hash selection in
> calculate_hash()")
> changed the way the FIT were verified. Previously, SW sha1/256 were
> always
> used. Due to that commit, that can now be done in hardware.
> caam_hash requires both the input, pbuf, and output buffer, pout, to
> be
> aligned. E.g. for the kernel data, pbuf will be the data start
> address
> for the kernel. The data start address is dependent on how the FIT is
> constructed and what address the FIT is loaded to. I.e.; it is fairly
> likely that we have a case of pbuf to not be aligned. pout is even
> more
> likely to not be aligned since it is simply a stack variable declared
> in
> fit_image_check_hash in common/image-fit.c.
> So to rely upon both of these buffers to be aligned, makes errors
> fairly
> likely.
>
> Solution:
> I wont propose copying the entire input buffer due to its size, so
> instead
> just fallback to use the sw sha1/sha256 if buffers is misaligned.
>
> Signed-off-by: Christian Sørensen
> ---
>
> drivers/crypto/fsl/fsl_hash.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/crypto/fsl/fsl_hash.c
> b/drivers/crypto/fsl/fsl_hash.c
> index 8b5c26db07..48dd10883e 100644
> --- a/drivers/crypto/fsl/fsl_hash.c
> +++ b/drivers/crypto/fsl/fsl_hash.c
> @@ -16,6 +16,9 @@
> #include
> #include
> #include
> +#include
> +#include
> +#include
>
> #define CRYPTO_MAX_ALG_NAME80
> #define SHA1_DIGEST_SIZE20
> @@ -176,8 +179,12 @@ int caam_hash(const unsigned char *pbuf,
> unsigned int buf_len,
>
> if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) ||
> !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) {
> - puts("Error: Address arguments are not aligned\n");
> - return -EINVAL;
> + printf("Fallback to SW hash due to misaligned
> buffers\n");
> + if (algo == SHA1)
> + sha1_csum_wd(pbuf, buf_len, pout,
> CHUNKSZ_SHA1);
> + else
> + sha256_csum_wd(pbuf, buf_len, pout,
> CHUNKSZ_SHA256);
> + return 0;
How about adding “#ifdef CONFIG_SHA1” and “#ifdef CONFIG_SHA256” here
? Then it can depend on users’ selection to determine the fallback
Best regards,
Ye Li
> }
>
> size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
> --
> 2.25.1
>
Re: [PATCH v2 01/15] crypto/fsl: Add support for CAAM Job ring driver model
turn ret;
> }
>
> -static int instantiate_rng(u8 sec_idx, int gen_sk)
> +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int
> gen_sk)
> {
> u32 *desc;
> u32 rdsta_val;
> int ret = 0, sh_idx, size;
> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> *)SEC_ADDR(sec_idx);
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)>rng;
>
> @@ -554,9 +572,8 @@ static int instantiate_rng(u8 sec_idx, int
> gen_sk)
> return ret;
> }
>
> -static u8 get_rng_vid(uint8_t sec_idx)
> +static u8 get_rng_vid(ccsr_sec_t *sec)
> {
> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> u8 vid;
>
> if (caam_get_era() < 10) {
> @@ -574,9 +591,8 @@ static u8 get_rng_vid(uint8_t sec_idx)
> * By default, the TRNG runs for 200 clocks per sample;
> * 1200 clocks per sample generates better entropy.
> */
> -static void kick_trng(int ent_delay, uint8_t sec_idx)
> +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> {
> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> *)SEC_ADDR(sec_idx);
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)>rng;
> u32 val;
> @@ -603,10 +619,9 @@ static void kick_trng(int ent_delay, uint8_t
> sec_idx)
> sec_clrbits32(>rtmctl, RTMCTL_PRGM);
> }
>
> -static int rng_init(uint8_t sec_idx)
> +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> {
> int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> *)SEC_ADDR(sec_idx);
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)>rng;
> u32 inst_handles;
> @@ -624,7 +639,7 @@ static int rng_init(uint8_t sec_idx)
> * the TRNG parameters.
> */
> if (!inst_handles) {
> - kick_trng(ent_delay, sec_idx);
> + kick_trng(ent_delay, sec);
> ent_delay += 400;
> }
> /*
> @@ -634,7 +649,7 @@ static int rng_init(uint8_t sec_idx)
> * interval, leading to a sucessful initialization
> of
> * the RNG.
> */
> - ret = instantiate_rng(sec_idx, gen_sk);
> + ret = instantiate_rng(sec_idx, sec, gen_sk);
> } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
> if (ret) {
> printf("SEC%u: Failed to instantiate RNG\n",
> sec_idx);
> @@ -647,12 +662,25 @@ static int rng_init(uint8_t sec_idx)
> return ret;
> }
> #endif
> +
> int sec_init_idx(uint8_t sec_idx)
> {
> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> - uint32_t mcr = sec_in32(>mcfgr);
> int ret = 0;
> -
> + struct caam_regs *caam;
> +#if CONFIG_IS_ENABLED(DM)
> + caam = dev_get_priv(caam_dev);
Need to check the caam_dev valid before using it
Best regards,
Ye Li
> +#else
> + caam_st.sec = (void *)SEC_ADDR(sec_idx);
> + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> + caam_st.jrid = 0;
> + caam = _st;
> +#endif
> +#ifndef CONFIG_ARCH_IMX8
> + ccsr_sec_t *sec = caam->sec;
> + uint32_t mcr = sec_in32(>mcfgr);
> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> + uint32_t jrdid_ms = 0;
> +#endif
> #ifdef CONFIG_FSL_CORENET
> uint32_t liodnr;
> uint32_t liodn_ns;
> @@ -682,6 +710,11 @@ int sec_init_idx(uint8_t sec_idx)
> mcr |= (1 << MCFGR_PS_SHIFT);
> #endif
> sec_out32(>mcfgr, mcr);
> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ |
> JRDID_MS_PRIM_DID;
> + sec_out32(>jrliodnr[caam->jrid].ms, jrdid_ms);
> +#endif
> + jr_reset();
>
> #ifdef CONFIG_FSL_CORENET
> #ifdef CONFIG_SPL_BUILD
> @@ -693,25 +726,26 @@ int sec_init_idx(uint8_t sec_idx)
> liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
> liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
>
> - liodnr = sec_in32(>jrliodnr[0].ls) &
> + liodnr = sec_in32(>jrliodnr[caam->jrid].ls) &
> ~(JRNSLIODN_MASK | JRSLIODN_MASK);
> liodnr = liodnr |
> (liodn_ns << JRNSLIODN_SHIFT) |
> (liodn_s << JRSLIODN_SHIFT);
> - sec_out32(>jrliodnr[0].ls, liodnr);
> + sec_out32(>jrliodnr[caam->jrid].ls, liodnr);
> #else
> - liodnr = sec_in32(>jrliodnr[0].ls);
> + liodnr = sec_in32(>jrliodnr[caam
Re: [PATCH v2 02/15] crypto/fsl: Add CAAM support for bkek, random number generation
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> added api and descriptor for blob key encryption key(bkek)
> generation.
> added api for random number generation.
>
> Signed-off-by: Gaurav Jain
> Signed-off-by: Ji Luo
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
> drivers/crypto/fsl/desc.h | 5 +++
> drivers/crypto/fsl/fsl_blob.c | 82
> +++
> drivers/crypto/fsl/jobdesc.c | 20 +++--
> drivers/crypto/fsl/jobdesc.h | 4 ++
> 4 files changed, 108 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
> index 5705c4f944..5958ebd3ac 100644
> --- a/drivers/crypto/fsl/desc.h
> +++ b/drivers/crypto/fsl/desc.h
> @@ -4,6 +4,7 @@
> * Definitions to support CAAM descriptor instruction generation
> *
> * Copyright 2008-2014 Freescale Semiconductor, Inc.
> + * Copyright 2021 NXP
> *
> * Based on desc.h file in linux drivers/crypto/caam
> */
> @@ -15,6 +16,7 @@
>
> #define KEY_BLOB_SIZE32
> #define MAC_SIZE 16
> +#define BKEK_SIZE32
>
> /* Max size of any CAAM descriptor in 32-bit words, inclusive of
> header */
> #define MAX_CAAM_DESCSIZE64
> @@ -463,6 +465,9 @@
> #define OP_PROTINFO_HASH_SHA384 0x0200
> #define OP_PROTINFO_HASH_SHA512 0x0280
>
> +/* PROTINFO fields for Blob Operations */
> +#define OP_PROTINFO_MKVB 0x0002
> +
> /* For non-protocol/alg-only op commands */
> #define OP_ALG_TYPE_SHIFT24
> #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT)
> diff --git a/drivers/crypto/fsl/fsl_blob.c
> b/drivers/crypto/fsl/fsl_blob.c
> index e8202cc569..e8bc009daf 100644
> --- a/drivers/crypto/fsl/fsl_blob.c
> +++ b/drivers/crypto/fsl/fsl_blob.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright 2014 Freescale Semiconductor, Inc.
> + * Copyright 2021 NXP
> *
> */
>
> @@ -152,6 +153,87 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst,
> u32 len)
> return ret;
> }
>
> +int derive_blob_kek(u8 *bkek_buf, u8 *key_mod, u32 key_sz)
> +{
> + int ret, size;
> + u32 *desc;
> +
> + if (!IS_ALIGNED((uintptr_t)bkek_buf, ARCH_DMA_MINALIGN) ||
> + !IS_ALIGNED((uintptr_t)key_mod, ARCH_DMA_MINALIGN)) {
> + puts("Error: derive_bkek: Address arguments are not
> aligned!\n");
> + return -EINVAL;
> + }
> +
> + printf("\nBlob key encryption key(bkek)\n");
> + desc = malloc_cache_aligned(sizeof(int) *
> MAX_CAAM_DESCSIZE);
> + if (!desc) {
> + printf("Not enough memory for descriptor
> allocation\n");
> + return -ENOMEM;
> + }
> +
> + size = ALIGN(key_sz, ARCH_DMA_MINALIGN);
> + flush_dcache_range((unsigned long)key_mod, (unsigned
> long)key_mod + size);
> +
> + /* construct blob key encryption key(bkek) derive descriptor
> */
> + inline_cnstr_jobdesc_derive_bkek(desc, bkek_buf, key_mod,
> key_sz);
> +
> + size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE,
> ARCH_DMA_MINALIGN);
> + flush_dcache_range((unsigned long)desc, (unsigned long)desc
> + size);
> + size = ALIGN(BKEK_SIZE, ARCH_DMA_MINALIGN);
> + invalidate_dcache_range((unsigned long)bkek_buf,
> + (unsigned long)bkek_buf + size);
> +
> + /* run descriptor */
> + ret = run_descriptor_jr(desc);
> + if (ret < 0) {
> + printf("Error: %s failed 0x%x\n", __func__, ret);
> + } else {
> + invalidate_dcache_range((unsigned long)bkek_buf,
> + (unsigned long)bkek_buf +
> size);
> + puts("derive bkek successful.\n");
> + }
> +
> + free(desc);
> + return ret;
> +}
> +
> +int hwrng_generate(u8 *dst, u32 len)
> +{
> + int ret, size;
> + u32 *desc;
> +
> + if (!IS_ALIGNED((uintptr_t)dst, ARCH_DMA_MINALIGN)) {
> + puts("Error: caam_hwrng_test: Address arguments are
> not aligned!\n");
> + return -EINVAL;
> + }
> +
> + printf("\nRNG generate\n");
> + desc = malloc_cache_aligned(sizeof(int) *
> MAX_CAAM_DESCSIZE);
> + if (!desc) {
> + printf("Not enough memory for descriptor
> allocation\n");
> + return -ENOMEM;
> + }
> +
> + inline_cnstr_jobdesc_rng(desc, dst, len);
> +
> + size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE,
> ARCH_DMA_MINALIGN);
> + flush_dcache_range((unsigned long)desc, (unsigned long)desc
> + siz
Re: [PATCH v2 09/15] crypto/fsl: i.MX8: Enable Job ring driver model in SPL and U-Boot.
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX8(QM/QXP) - added support for JR driver model.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain
> Signed-off-by: Horia Geantă
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
> arch/arm/Kconfig | 3 +++
> arch/arm/include/asm/arch-imx8/imx-regs.h | 5 -
> arch/arm/mach-imx/cmd_dek.c | 1 +
> arch/arm/mach-imx/imx8/Kconfig| 9 +
> arch/arm/mach-imx/imx8/cpu.c | 16 ++-
> board/freescale/imx8qm_mek/spl.c | 6 --
> board/freescale/imx8qxp_mek/spl.c | 6 --
> drivers/crypto/fsl/Kconfig| 2 +-
> drivers/crypto/fsl/jr.c | 24
> +++
> include/fsl_sec.h | 12 +---
> 10 files changed, 70 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index b3d11c1a0d..982b285e39 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -785,6 +785,9 @@ config ARCH_LPC32XX
> config ARCH_IMX8
> bool "NXP i.MX8 platform"
> select ARM64
> + select SYS_FSL_HAS_SEC
> + select SYS_FSL_SEC_COMPAT_4
> + select SYS_FSL_SEC_LE
> select DM
> select GPIO_EXTRA_HEADER
> select OF_CONTROL
> diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h
> b/arch/arm/include/asm/arch-imx8/imx-regs.h
> index ed6e05e556..2d64b0604b 100644
> --- a/arch/arm/include/asm/arch-imx8/imx-regs.h
> +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
> */
>
> #ifndef __ASM_ARCH_IMX8_REGS_H__
> @@ -47,4 +47,7 @@
> #define USB_BASE_ADDR0x5b0d
> #define USB_PHY0_BASE_ADDR 0x5b10
>
> +#define CONFIG_SYS_FSL_SEC_ADDR (0x3140)
> +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC1
> +
> #endif /* __ASM_ARCH_IMX8_REGS_H__ */
> diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-
> imx/cmd_dek.c
> index 89da89c51d..04c4b20a84 100644
> --- a/arch/arm/mach-imx/cmd_dek.c
> +++ b/arch/arm/mach-imx/cmd_dek.c
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-
> imx/imx8/Kconfig
> index b43739e5c6..9a20ebe84e 100644
> --- a/arch/arm/mach-imx/imx8/Kconfig
> +++ b/arch/arm/mach-imx/imx8/Kconfig
> @@ -8,6 +8,7 @@ config AHAB_BOOT
>
> config IMX8
> bool
> + select HAS_CAAM
>
> config MU_BASE_SPL
> hex "MU base address used in SPL"
> @@ -72,6 +73,10 @@ config TARGET_IMX8QM_MEK
> bool "Support i.MX8QM MEK board"
> select BOARD_LATE_INIT
> select IMX8QM
> + select FSL_CAAM
> + select FSL_BLOB
> + select ARCH_MISC_INIT
> + select SPL_CRYPTO if SPL
>
> config TARGET_CONGA_QMX8
> bool "Support congatec conga-QMX8 board"
> @@ -89,6 +94,10 @@ config TARGET_IMX8QXP_MEK
> bool "Support i.MX8QXP MEK board"
> select BOARD_LATE_INIT
> select IMX8QXP
> + select FSL_CAAM
> + select FSL_BLOB
> + select ARCH_MISC_INIT
> + select SPL_CRYPTO if SPL
>
> endchoice
>
> diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-
> imx/imx8/cpu.c
> index 02db322f51..86ced79bb7 100644
> --- a/arch/arm/mach-imx/imx8/cpu.c
> +++ b/arch/arm/mach-imx/imx8/cpu.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
> */
>
> #include
> @@ -89,6 +89,20 @@ int arch_cpu_init_dm(void)
> return 0;
> }
>
> +#if defined(CONFIG_ARCH_MISC_INIT)
> +int arch_misc_init(void)
> +{
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device_by_driver(UCLASS_MISC,
> DM_DRIVER_GET(caam_jr), );
> + if (ret)
> + printf("Failed to initialize %s: %d\n", dev->name,
> ret);
> +
> + return 0;
> +}
> +#endif
> +
> int print_bootinfo(void)
> {
> enum boot_device bt_dev = get_boot_device();
> diff --git a/board/freescale/imx8qm_mek/spl.c
> b/board/freescale/imx8qm_mek/spl.c
> index 944ba745c0..332a662dee 100644
> --- a/board/freescale/imx8qm_mek/spl.c
> +++ b/board/freescale/imx8qm_mek/spl.c
> @@ -1,7 +1,7 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
>
Re: [PATCH v2 08/15] i.MX8: Add crypto node in device tree
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.
>
> disabled use of JR1 in SPL and uboot, as JR1 is reserved
> for SECO FW.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
> arch/arm/dts/fsl-imx8dx.dtsi | 61
> +++-
> arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 -
> arch/arm/dts/fsl-imx8qm.dtsi | 61
> +++-
> arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 -
> 4 files changed, 186 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-
> imx8dx.dtsi
> index 7d95cf0b7d..63a56699b5 100644
> --- a/arch/arm/dts/fsl-imx8dx.dtsi
> +++ b/arch/arm/dts/fsl-imx8dx.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
> */
>
> #include
> @@ -261,6 +261,30 @@
> power-domains = <_dma>;
> };
> };
> +
> + pd_caam: PD_CAAM {
> + compatible = "nxp,imx8-pd";
> + reg = ;
> + #power-domain-cells = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pd_caam_jr1: PD_CAAM_JR1 {
> + reg = ;
> + #power-domain-cells = <0>;
> + power-domains = <_caam>;
> + };
> + pd_caam_jr2: PD_CAAM_JR2 {
> + reg = ;
> + #power-domain-cells = <0>;
> + power-domains = <_caam>;
> + };
> + pd_caam_jr3: PD_CAAM_JR3 {
> + reg = ;
> + #power-domain-cells = <0>;
> + power-domains = <_caam>;
> + };
> + };
> };
>
> i2c0: i2c@5a80 {
> @@ -609,6 +633,41 @@
> };
> };
> };
> +
> + crypto: caam@0x3140 {
> + compatible = "fsl,sec-v4.0";
> + reg = <0 0x3140 0 0x40>;
> + interrupts = ;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x3140 0x40>;
> + fsl,first-jr-index = <2>;
> + fsl,sec-era = <9>;
> +
> + sec_jr1: jr1@0x2 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x2 0x1000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <_caam_jr1>;
> + status = "disabled";
> + };
> +
> + sec_jr2: jr2@3 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x3 0x1000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <_caam_jr2>;
> + status = "okay";
> + };
> +
> + sec_jr3: jr3@4 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x4 0x1000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <_caam_jr3>;
> + status = "okay";
> + };
> + };
> };
>
> _0 {
> diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> index 9e0d264b71..a95209e141 100644
> --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
> */
>
> &{/imx8qm-pm} {
> @@ -80,6 +80,22 @@
> u-boot,dm-spl;
> };
>
> +_caam {
> + u-boot,dm-spl;
> +};
> +
> +_caam_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +_caam_jr2 {
> + u-boot,dm-spl;
> +};
> +
> +_caam_jr3 {
> + u-boot,dm-spl;
> +};
> +
> {
> u-boot,dm-spl;
> };
> @@ -126,3 +142,19 @@
> sd-uhs-sdr104;
> sd-uhs-ddr50;
> };
> +
> + {
> + u-boot,dm-spl;
> +};
> +
&g
Re: [PATCH v2 07/15] i.MX7ULP: Enable Job ring driver model in U-Boot.
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> added crypto node in device tree.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
> arch/arm/Kconfig | 2 +-
> arch/arm/dts/imx7ulp.dtsi| 24
> arch/arm/mach-imx/mx7ulp/Kconfig | 4
> arch/arm/mach-imx/mx7ulp/soc.c | 16
> 4 files changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index addd349e54..b3d11c1a0d 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -848,7 +848,7 @@ config ARCH_MX7ULP
> bool "NXP MX7ULP"
> select CPU_V7A
> select GPIO_EXTRA_HEADER
> - select SYS_FSL_HAS_SEC if IMX_HAB
> + select SYS_FSL_HAS_SEC
> select SYS_FSL_SEC_COMPAT_4
> select SYS_FSL_SEC_LE
> select ROM_UNIFIED_SECTIONS
> diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
> index 7bcd2cc346..494b9d98b2 100644
> --- a/arch/arm/dts/imx7ulp.dtsi
> +++ b/arch/arm/dts/imx7ulp.dtsi
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2015-2016 Freescale Semiconductor, Inc.
> + * Copyright 2021 NXP
> *
> * This program is free software; you can redistribute it and/or
> modify
> * it under the terms of the GNU General Public License version 2 as
> @@ -198,6 +199,29 @@
> };
> };
>
> + crypto: crypto@4024 {
> + compatible = "fsl,sec-v4.0";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x4024 0x1>;
> + ranges = <0 0x4024 0x1>;
> + clocks = < IMX7ULP_CLK_CAAM>,
> + < IMX7ULP_CLK_NIC1_BUS_DIV>;
> + clock-names = "aclk", "ipg";
> +
> + sec_jr0: jr@1000 {
> + compatible = "fsl,sec-v4.0-job-
> ring";
> + reg = <0x1000 0x1000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sec_jr1: jr@2000 {
> + compatible = "fsl,sec-v4.0-job-
> ring";
> + reg = <0x2000 0x1000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> tpm5: tpm@4026 {
> compatible = "fsl,imx7ulp-tpm";
> reg = <0x4026 0x1000>;
> diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-
> imx/mx7ulp/Kconfig
> index 2ffac9cf7c..0d9f8ffed9 100644
> --- a/arch/arm/mach-imx/mx7ulp/Kconfig
> +++ b/arch/arm/mach-imx/mx7ulp/Kconfig
> @@ -25,6 +25,10 @@ config TARGET_MX7ULP_EVK
> bool "Support mx7ulp EVK board"
> select MX7ULP
> select SYS_ARCH_TIMER
> + select FSL_CAAM
> + select FSL_BLOB
> + select MISC
> + select ARCH_MISC_INIT
>
> endchoice
>
> diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-
> imx/mx7ulp/soc.c
> index 320f24dd29..1cfc751bdc 100644
> --- a/arch/arm/mach-imx/mx7ulp/soc.c
> +++ b/arch/arm/mach-imx/mx7ulp/soc.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2021 NXP
> */
>
> #include
> @@ -14,6 +15,7 @@
> #include
> #include
> #include
> +#include
>
> #define PMC0_BASE_ADDR 0x410a1000
> #define PMC0_CTRL0x28
> @@ -79,6 +81,20 @@ int arch_cpu_init(void)
> return 0;
> }
>
> +#if defined(CONFIG_ARCH_MISC_INIT)
> +int arch_misc_init(void)
> +{
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device_by_driver(UCLASS_MISC,
> DM_DRIVER_GET(caam_jr), );
> + if (ret)
> + printf("Failed to initialize %s: %d\n", dev->name,
> ret);
> +
> + return 0;
> +}
> +#endif
> +
> #ifdef CONFIG_BOARD_POSTCLK_INIT
> int board_postclk_init(void)
> {
Re: [PATCH v2 06/15] i.MX7: Enable Job ring driver model in U-Boot.
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX7D - added support for JR driver model.
>
> removed sec_init() call, sec is initialized based on
> job ring information processed from device tree.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
> arch/arm/Kconfig | 2 +-
> arch/arm/mach-imx/mx7/Kconfig | 3 +++
> arch/arm/mach-imx/mx7/soc.c | 11 +++
> 3 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index af7aad3f9e..addd349e54 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -860,7 +860,7 @@ config ARCH_MX7
> select ARCH_MISC_INIT
> select CPU_V7A
> select GPIO_EXTRA_HEADER
> - select SYS_FSL_HAS_SEC if IMX_HAB
> + select SYS_FSL_HAS_SEC
> select SYS_FSL_SEC_COMPAT_4
> select SYS_FSL_SEC_LE
> imply BOARD_EARLY_INIT_F
> diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-
> imx/mx7/Kconfig
> index adedc01164..b82338e2cc 100644
> --- a/arch/arm/mach-imx/mx7/Kconfig
> +++ b/arch/arm/mach-imx/mx7/Kconfig
> @@ -60,6 +60,9 @@ config TARGET_MX7DSABRESD
> select DM_THERMAL
> select MX7D
> imply CMD_DM
> + select FSL_CAAM
> + select FSL_BLOB
> + select MISC
>
> config TARGET_PICO_IMX7D
> bool "pico-imx7d"
> diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-
> imx/mx7/soc.c
> index fda25ba66a..26b00bc93f 100644
> --- a/arch/arm/mach-imx/mx7/soc.c
> +++ b/arch/arm/mach-imx/mx7/soc.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + * Copyright 2021 NXP
> */
>
> #include
> @@ -18,7 +19,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
>
> @@ -336,6 +336,9 @@ int arch_cpu_init(void)
> #ifdef CONFIG_ARCH_MISC_INIT
> int arch_misc_init(void)
> {
> + struct udevice *dev;
> + int ret;
> +
> #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> if (is_mx7d())
> env_set("soc", "imx7d");
> @@ -343,9 +346,9 @@ int arch_misc_init(void)
> env_set("soc", "imx7s");
> #endif
>
> -#ifdef CONFIG_FSL_CAAM
> - sec_init();
> -#endif
> + ret = uclass_get_device_by_driver(UCLASS_MISC,
> DM_DRIVER_GET(caam_jr), );
> + if (ret)
> + printf("Failed to initialize %s: %d\n", dev->name,
> ret);
>
> return 0;
> }
Re: [PATCH v2 05/15] i.MX6: Enable Job ring driver model in U-Boot.
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX6(SX/UL) - added support for JR driver model.
>
> removed sec_init() call, sec is initialized based on
> job ring information processed from device tree.
>
> Signed-off-by: Gaurav Jain
> ---
> arch/arm/mach-imx/mx6/Kconfig | 8
> arch/arm/mach-imx/mx6/soc.c | 12
> 2 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-
> imx/mx6/Kconfig
> index 789a50d4e9..a7109bb512 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -378,6 +378,10 @@ config TARGET_MX6SXSABRESD
> select DM
> select DM_THERMAL
> select SUPPORT_SPL
> + select FSL_CAAM
> + select FSL_BLOB
> + select MISC
> + select ARCH_MISC_INIT
>
> config TARGET_MX6SXSABREAUTO
> bool "mx6sxsabreauto"
> @@ -405,6 +409,10 @@ config TARGET_MX6UL_14X14_EVK
> select DM_THERMAL
> select SUPPORT_SPL
> imply CMD_DM
> + select FSL_CAAM
> + select FSL_BLOB
> + select MISC
> + select ARCH_MISC_INIT
>
Can you also enable the JR driver for MX6SABREAUTO, MX6SABRESD and
MX6UL_9X9_EVK?
Best regards,
Ye Li
> config TARGET_MX6UL_ENGICAM
> bool "Support Engicam GEAM6UL/Is.IoT"
> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-
> imx/mx6/soc.c
> index aacfc854a2..fa6c3778bb 100644
> --- a/arch/arm/mach-imx/mx6/soc.c
> +++ b/arch/arm/mach-imx/mx6/soc.c
> @@ -4,6 +4,7 @@
> * Sascha Hauer, Pengutronix
> *
> * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + * Copyright 2021 NXP
> */
>
> #include
> @@ -23,7 +24,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
>
> @@ -734,9 +734,13 @@ static void setup_serial_number(void)
>
> int arch_misc_init(void)
> {
> -#ifdef CONFIG_FSL_CAAM
> - sec_init();
> -#endif
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device_by_driver(UCLASS_MISC,
> DM_DRIVER_GET(caam_jr), );
> + if (ret)
> + printf("Failed to initialize %s: %d\n", dev->name,
> ret);
> +
> setup_serial_number();
> return 0;
> }
Re: [PATCH v2 04/15] crypto/fsl: i.MX8M: Enable Job ring driver model in SPL and U-Boot.
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX8MM/MN/MP/MQ - added support for JR driver model.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
> arch/arm/Kconfig | 2 +-
> arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 +
> arch/arm/mach-imx/imx8m/Kconfig| 23
> ++
> arch/arm/mach-imx/imx8m/soc.c | 10 +-
> board/freescale/imx8mm_evk/spl.c | 9 -
> board/freescale/imx8mn_evk/spl.c | 8 ++--
> board/freescale/imx8mp_evk/spl.c | 13 ++--
> board/freescale/imx8mq_evk/spl.c | 9 +++--
> drivers/crypto/fsl/jr.c| 14 ++---
> scripts/config_whitelist.txt | 1 +
> 10 files changed, 78 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 2d59562665..af7aad3f9e 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -794,7 +794,7 @@ config ARCH_IMX8M
> bool "NXP i.MX8M platform"
> select ARM64
> select GPIO_EXTRA_HEADER
> - select SYS_FSL_HAS_SEC if IMX_HAB
> + select SYS_FSL_HAS_SEC
> select SYS_FSL_SEC_COMPAT_4
> select SYS_FSL_SEC_LE
> select DM
> diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
> b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> index b800da13a1..ff8de53f67 100644
> --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
> +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> @@ -72,6 +72,7 @@
> #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
> CONFIG_SYS_FSL_SEC_OFFSET)
> #define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
> +#define CONFIG_SYS_FSL_JR1_OFFSET (0x2000)
> #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
> CONFIG_SYS_FSL_JR0_OFFSET)
> #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-
> imx/imx8m/Kconfig
> index ccaf106be5..3fbdd5c233 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -38,6 +38,11 @@ config TARGET_IMX8MQ_EVK
> bool "imx8mq_evk"
> select IMX8MQ
> select IMX8M_LPDDR4
> + select FSL_CAAM
> + select FSL_BLOB
> + select MISC
> + select ARCH_MISC_INIT
> + select SPL_CRYPTO if SPL
>
> config TARGET_IMX8MQ_PHANBELL
> bool "imx8mq_phanbell"
> @@ -50,6 +55,11 @@ config TARGET_IMX8MM_EVK
> select IMX8MM
> select SUPPORT_SPL
> select IMX8M_LPDDR4
> + select FSL_CAAM
> + select FSL_BLOB
> + select MISC
> + select ARCH_MISC_INIT
> + select SPL_CRYPTO if SPL
>
> config TARGET_IMX8MM_ICORE_MX8MM
> bool "Engicam i.Core MX8M Mini SOM"
> @@ -81,6 +91,10 @@ config TARGET_IMX8MN_EVK
> select IMX8MN
> select SUPPORT_SPL
> select IMX8M_LPDDR4
> + select FSL_CAAM
> + select FSL_BLOB
> + select MISC
> + select SPL_CRYPTO if SPL
>
> config TARGET_IMX8MN_DDR4_EVK
> bool "imx8mn DDR4 EVK board"
> @@ -88,6 +102,10 @@ config TARGET_IMX8MN_DDR4_EVK
> select IMX8MN
> select SUPPORT_SPL
> select IMX8M_DDR4
> + select FSL_CAAM
> + select FSL_BLOB
> + select MISC
> + select SPL_CRYPTO if SPL
>
> config TARGET_IMX8MP_EVK
> bool "imx8mp LPDDR4 EVK board"
> @@ -95,6 +113,11 @@ config TARGET_IMX8MP_EVK
> select IMX8MP
> select SUPPORT_SPL
> select IMX8M_LPDDR4
> + select FSL_CAAM
> + select FSL_BLOB
> + select MISC
> + select ARCH_MISC_INIT
> + select SPL_CRYPTO if SPL
>
> config TARGET_PICO_IMX8MQ
> bool "Support Technexion Pico iMX8MQ"
> diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-
> imx/imx8m/soc.c
> index f2ddc834d4..0fe28f4971 100644
> --- a/arch/arm/mach-imx/imx8m/soc.c
> +++ b/arch/arm/mach-imx/imx8m/soc.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2017-2019 NXP
> + * Copyright 2017-2019, 2021 NXP
> *
> * Peng Fan
> */
> @@ -20,6 +20,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -1187,6 +1188,13 @@ static void acquire_buildinfo(void)
>
> int arch_misc_init(void)
> {
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device_by_driver(U
Re: [PATCH v2 03/15] i.MX8M: crypto: updated device tree for supporting DM in SPL
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> disabled use of JR0 in SPL and uboot, as JR0 is reserved
> for secure boot.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
> arch/arm/dts/imx8mm-evk-u-boot.dtsi | 18 +-
> arch/arm/dts/imx8mm.dtsi | 1 +
> arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 18 +-
> arch/arm/dts/imx8mn.dtsi | 1 +
> arch/arm/dts/imx8mp-evk-u-boot.dtsi | 18 +-
> arch/arm/dts/imx8mp.dtsi | 1 +
> arch/arm/dts/imx8mq.dtsi | 1 +
> 7 files changed, 55 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> index f200afac9f..3c2502cbba 100644
> --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2019, 2021 NXP
> */
>
> #include "imx8mm-u-boot.dtsi"
> @@ -72,6 +72,22 @@
> u-boot,dm-spl;
> };
>
> + {
> + u-boot,dm-spl;
> +};
> +
> +_jr0 {
> + u-boot,dm-spl;
> +};
> +
> +_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +_jr2 {
> + u-boot,dm-spl;
> +};
> +
> {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
> index b142b80734..00bf3a 100644
> --- a/arch/arm/dts/imx8mm.dtsi
> +++ b/arch/arm/dts/imx8mm.dtsi
> @@ -824,6 +824,7 @@
> compatible = "fsl,sec-v4.0-
> job-ring";
> reg = <0x1000 0x1000>;
> interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> sec_jr1: jr@2000 {
> diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> index 1d3844437d..b462d24eb2 100644
> --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2019, 2021 NXP
> */
>
> / {
> @@ -104,6 +104,22 @@
> u-boot,dm-spl;
> };
>
> + {
> + u-boot,dm-spl;
> +};
> +
> +_jr0 {
> + u-boot,dm-spl;
> +};
> +
> +_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +_jr2 {
> + u-boot,dm-spl;
> +};
> +
> {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
> index edcb415b53..1820a5af37 100644
> --- a/arch/arm/dts/imx8mn.dtsi
> +++ b/arch/arm/dts/imx8mn.dtsi
> @@ -822,6 +822,7 @@
> compatible = "fsl,sec-v4.0-
> job-ring";
> reg = <0x1000 0x1000>;
> interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> sec_jr1: jr@2000 {
> diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> index 2abcf1f03d..5415d5b617 100644
> --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2019, 2021 NXP
> */
>
> #include "imx8mp-u-boot.dtsi"
> @@ -67,6 +67,22 @@
> u-boot,dm-spl;
> };
>
> + {
> + u-boot,dm-spl;
> +};
> +
> +_jr0 {
> + u-boot,dm-spl;
> +};
> +
> +_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +_jr2 {
> + u-boot,dm-spl;
> +};
> +
> {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> index c2d51a46cb..57b01c3a57 100644
> --- a/arch/arm/dts/imx8mp.dtsi
> +++ b/arch/arm/dts/imx8mp.dtsi
> @@ -624,6 +624,7 @@
> compatible = "fsl,sec-v4.0-
> job-ring";
> reg = <0x1000 0x1000>;
> interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> sec_jr1: jr@2000 {
> diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
> index a44f729d0e..ecab44ca13 100644
> --- a/arch/arm/dts/imx8mq.dtsi
> +++ b/arch/arm/dts/imx8mq.dtsi
> @@ -955,6 +955,7 @@
> compatible = "fsl,sec-v4.0-
> job-ring";
> reg = <0x1000 0x1000>;
> interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> sec_jr1: jr@2000 {
[PATCH] mtd: nand: mxs_nand_spl: Add nand_spl_adjust_offset
Since the mxs_nand_spl has implemented adjust read offset in
nand_spl_load_image, so we don't need to check the bad block in
nand_spl_adjust_offset. Directly return the offset to continue
read by nand_spl_load_image.
Signed-off-by: Ye Li
---
drivers/mtd/nand/raw/mxs_nand_spl.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c
b/drivers/mtd/nand/raw/mxs_nand_spl.c
index 17f46ae..022c819 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -296,3 +296,8 @@ void nand_deselect(void)
{
}
+u32 nand_spl_adjust_offset(u32 sector, u32 offs)
+{
+ /* Handle the offset adjust in nand_spl_load_image,*/
+ return offs;
+}
--
2.7.4
[PATCH 2/2] mmc: fix device_remove when HS400_ES is enabled
HS400_ES is missed when down grade to HS mode during
device_remove the mmc device
Signed-off-by: Ye Li
---
drivers/mmc/mmc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index a1fd533..3cb6fda 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2092,14 +2092,16 @@ static int mmc_select_mode_and_width(struct mmc *mmc,
uint card_caps)
}
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
-CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
+CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
/*
* In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
* before doing anything else, since a transition from either of
* the HS200/HS400 mode directly to legacy mode is not supported.
*/
if (mmc->selected_mode == MMC_HS_200 ||
- mmc->selected_mode == MMC_HS_400)
+ mmc->selected_mode == MMC_HS_400 ||
+ mmc->selected_mode == MMC_HS_400_ES)
mmc_set_card_speed(mmc, MMC_HS, true);
else
#endif
@@ -2952,7 +2954,7 @@ int mmc_deinit(struct mmc *mmc)
return sd_select_mode_and_width(mmc, caps_filtered);
} else {
caps_filtered = mmc->card_caps &
- ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
+ ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) |
MMC_CAP(MMC_HS_400_ES));
return mmc_select_mode_and_width(mmc, caps_filtered);
}
--
2.7.4
[PATCH 1/2] mmc: fix switch issue with send_status disabled
When send_status is false or wait_dat0 is not supported, the switch
function should not send CMD13 but directly return.
Signed-off-by: Ye Li
---
drivers/mmc/mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 8078a89..a1fd533 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -823,7 +823,7 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index,
u8 value,
* capable of polling by using mmc_wait_dat0, then rely on waiting the
* stated timeout to be sufficient.
*/
- if (ret == -ENOSYS && !send_status) {
+ if (ret == -ENOSYS || !send_status) {
mdelay(timeout_ms);
return 0;
}
--
2.7.4
[PATCH] arm: imx8m: Fix pad DSE issue for i.MX8MM/MN/MP
According to 8MM/MN/MP reference manual, their pad registers only have 4 valid DSE values. And DSE2 and DSE4 are different with current definitions in iomux-v3.h. Fix the issue to align with manual. Signed-off-by: Ye Li Acked-by: Peng Fan --- arch/arm/include/asm/mach-imx/iomux-v3.h | 21 - 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 1de7093..9330a32 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -87,15 +87,6 @@ typedef u64 iomux_v3_cfg_t; #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) #ifdef CONFIG_IMX8M -#define PAD_CTL_DSE0 (0x0 << 0) -#define PAD_CTL_DSE1 (0x1 << 0) -#define PAD_CTL_DSE2 (0x2 << 0) -#define PAD_CTL_DSE3 (0x3 << 0) -#define PAD_CTL_DSE4 (0x4 << 0) -#define PAD_CTL_DSE5 (0x5 << 0) -#define PAD_CTL_DSE6 (0x6 << 0) -#define PAD_CTL_DSE7 (0x7 << 0) - #define PAD_CTL_FSEL0 (0x0 << 3) #define PAD_CTL_FSEL1 (0x1 << 3) #define PAD_CTL_FSEL2 (0x2 << 3) @@ -105,8 +96,20 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_PUE(0x1 << 6) #define PAD_CTL_HYS(0x1 << 7) #if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#define PAD_CTL_DSE1 (0x0 << 1) +#define PAD_CTL_DSE2 (0x2 << 1) +#define PAD_CTL_DSE4 (0x1 << 1) +#define PAD_CTL_DSE6 (0x3 << 1) #define PAD_CTL_PE (0x1 << 8) #else +#define PAD_CTL_DSE0 (0x0 << 0) +#define PAD_CTL_DSE1 (0x1 << 0) +#define PAD_CTL_DSE2 (0x2 << 0) +#define PAD_CTL_DSE3 (0x3 << 0) +#define PAD_CTL_DSE4 (0x4 << 0) +#define PAD_CTL_DSE5 (0x5 << 0) +#define PAD_CTL_DSE6 (0x6 << 0) +#define PAD_CTL_DSE7 (0x7 << 0) #define PAD_CTL_LVTTL (0x1 << 8) #endif -- 2.7.4
[PATCH] mmc: fsl_esdhc_imx: Fix clock disable issue
The SD clock disable is wrapped by MMC_SUPPORTS_TUNING. So it
only works when UHS is enabled. However, in SD initialization the
power cycle does not depends on UHS. But the power cycle needs
disable the SD clock before power down.
So this causes a problem when UHS is not enabled. Some cards can't
become ready (ACMD14 timeout) due to the clock is enabled during
power cycle.
Signed-off-by: Ye Li
Reviewed-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index aabf395..7b67972 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -971,7 +971,6 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
if (priv->clock != clock)
set_sysctl(priv, mmc, clock);
-#ifdef MMC_SUPPORTS_TUNING
if (mmc->clk_disable) {
#ifdef CONFIG_FSL_USDHC
esdhc_clrbits32(>vendorspec, VENDORSPEC_CKEN);
@@ -987,6 +986,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
#endif
}
+#ifdef MMC_SUPPORTS_TUNING
/*
* For HS400/HS400ES mode, make sure set the strobe dll in the
* target clock rate. So call esdhc_set_strobe_dll() after the
--
2.7.4
[PATCH] arm: dts: imx8mp: Delete default clocks for clock controller node
Since SPL has initialized clocks for bus and core. We don't need to
set the default clocks for clock controller node.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp-u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index d61346d..a6ede2e 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -18,6 +18,9 @@
{
u-boot,dm-spl;
u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
};
_32k {
--
2.7.4
[PATCH 7/7] imx8mp_evk: Enable the DWC EQoS iMX driver
Enable the EQoS i.MX driver in defconfig, also enable the PHYLIB to facilitate the case that only has FEC enabled. Signed-off-by: Ye Li --- configs/imx8mp_evk_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 2c6fc16..41e6b2f 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -72,9 +72,12 @@ CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y -- 2.7.4
[PATCH 6/7] imx8mp_evk: Delete noncached memory config
DWC EQOS driver has removed to use noncached memory, so delete the configuration from iMX8MP EVK head file. Signed-off-by: Ye Li --- include/configs/imx8mp_evk.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index a6569d5..59e50fe 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -49,9 +49,6 @@ #define FEC_QUIRK_ENET_MAC #define DWC_NET_PHYADDR1 -#ifdef CONFIG_DWC_ETH_QOS -#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ -#endif #define PHY_ANEG_TIMEOUT 2 -- 2.7.4
[PATCH 5/7] imx8mp_evk: Remove EQoS PHY reset codes
Since we uses the DTS and PHY reset gpio in EQoS driver to do the
reset, remove the duplicated codes from board file.
Signed-off-by: Ye Li
---
board/freescale/imx8mp_evk/imx8mp_evk.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
b/board/freescale/imx8mp_evk/imx8mp_evk.c
index bc4753c..62096c2 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -54,30 +54,11 @@ static void setup_fec(void)
setbits_le32(>gpr[1], BIT(22));
}
-#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
-static iomux_v3_cfg_t const eqos_rst_pads[] = {
- MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_eqos(void)
-{
- imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
-ARRAY_SIZE(eqos_rst_pads));
-
- gpio_request(EQOS_RST_PAD, "eqos_rst");
- gpio_direction_output(EQOS_RST_PAD, 0);
- mdelay(15);
- gpio_direction_output(EQOS_RST_PAD, 1);
- mdelay(100);
-}
-
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
- setup_iomux_eqos();
-
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(>gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
--
2.7.4
[PATCH 4/7] imx8mp_evk: Fix incorrect cascade for FEC and EQOS setup
The setup functions should be independent for two ethernet controllers
Signed-off-by: Ye Li
---
board/freescale/imx8mp_evk/imx8mp_evk.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
b/board/freescale/imx8mp_evk/imx8mp_evk.c
index 89cc17c..bc4753c 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -101,9 +101,10 @@ int board_init(void)
if (CONFIG_IS_ENABLED(FEC_MXC)) {
setup_fec();
+ }
- if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
- ret = setup_eqos();
+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) {
+ ret = setup_eqos();
}
return ret;
--
2.7.4
[PATCH 3/7] arm: dts: imx8mp-evk: Enable the EQoS ethernet port
i.MX8MP EVK has two ethernet ports. Add relevant nodes and properties
for EQoS port to the EVK DTS file.
In -u-boot.dtsi, change the u-boot eqos compatible string, add PHY
reset gpio and remove assigned clocks as not supported in CCF.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 13
arch/arm/dts/imx8mp-evk.dts | 40 +
2 files changed, 53 insertions(+)
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 2abcf1f..ab849eb 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -111,6 +111,19 @@
u-boot,dm-spl;
};
+ {
+ compatible = "fsl,imx-eqos";
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ reset-gpios = < 22 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <15000>;
+ reset-post-delay-us = <10>;
+};
+
{
phy-reset-gpios = < 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index b10dce8..f846d69 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -74,6 +74,26 @@
status = "okay";
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ eee-broken-1000t;
+ };
+ };
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_flexcan2>;
@@ -160,6 +180,26 @@
};
{
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0
0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1
0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2
0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3
0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
+ >;
+ };
+
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
--
2.7.4
[PATCH 2/7] arm: mach-imx: Allow to build mac.c for EQoS driver
i.MX8MP has one DWC EQoS controller, so allow to build mac.c when only this driver is enabled. Signed-off-by: Ye Li --- arch/arm/mach-imx/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 0ef2695..74a2a2a 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_FEC_MXC) += mac.o +obj-$(CONFIG_DWC_ETH_QOS) += mac.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_IMX_HAB) += hab.o obj-y += cpu.o -- 2.7.4
[PATCH 1/7] arm: mach-imx: Update MAC fuse for i.MX8MP
i.MX8MP has two ENET controllers, have to update the function to
enable loading two MAC addresses.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/mac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c
index 3b1496b..9bb63d2 100644
--- a/arch/arm/mach-imx/mac.c
+++ b/arch/arm/mach-imx/mac.c
@@ -31,7 +31,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET;
fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset);
- has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull();
+ has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
is_imx8mp();
if (has_second_mac && dev_id == 1) {
u32 value = readl(>mac_addr2);
--
2.7.4
Re: [EXT] [PATCH v1] imx: spl: fix imx8m secure boot
Hi Heiko,
On Mon, 2021-08-16 at 07:07 +0200, Heiko Schocher wrote:
> Caution: EXT Email
>
> inspired from NXP code:
> 719d665a87c6: ("MLK-20467 imx8m: Fix issue for booting signed image
> through uuu")
>
> fix loading FIT buffer address to fix position
> CONFIG_SYS_TEXT_BASE - CONFIG_FIT_EXTERNAL_OFFSET
>
> and fix secure boot on imx8m based boards. Problem was
> that FIT header and so IVT header too, was loaded to
> memallocated address. So the ivt header address coded
> in IVT itself does not fit with the real position.
>
> Signed-off-by: Heiko Schocher
>
>
> ---
> replaces Series:
> https://lists.denx.de/pipermail/u-boot/2021-August/457308.html
>
> @Tim: could you please test this version on your hardware?
>
> azure build:
> https://dev.azure.com/hs0298/hs/_build/results?buildId=71=result
> s
> (fetch error for rockchip, but this should be no problem for this
> patch. How do I restart one specific job on azure?)
>
> Works on sdcard and QSPI NOR boot on phycore-imx8mp board.
>
> arch/arm/mach-imx/spl.c | 11 +++
> common/spl/spl_fit.c| 7 ++-
> 2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
> index 36033d611c..6991d88dbf 100644
> --- a/arch/arm/mach-imx/spl.c
> +++ b/arch/arm/mach-imx/spl.c
> @@ -334,6 +334,17 @@ void board_spl_fit_post_load(const void *fit)
> }
> #endif
>
> +#if defined(CONFIG_FIT_EXTERNAL_OFFSET)
> +void *board_spl_fit_buffer_addr(ulong fit_size, int bl_len)
> +{
> + /*
> +* use fix position
> +* TEXT_BASE - FIT_EXTERNAL_OFFSET
> +*/
> + return (void *)((CONFIG_SYS_TEXT_BASE -
> CONFIG_FIT_EXTERNAL_OFFSET));
It looks odd to use CONFIG_FIT_EXTERNAL_OFFSET. This config is used
to designate the image offset inside the FIT. It is irrelevant here.
Please follow the patch 719d665a87c6: ("MLK-20467 imx8m: Fix issue for
booting signed image through uuu") to fix the issue, which also keep
the HAB block aligned.
Best regards,
Ye Li
> +}
> +#endif
> +
> #endif
>
> #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index f41abca0cc..a4337d3c88 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -538,6 +538,11 @@ static void *spl_get_fit_load_buffer(size_t
> size)
> return buf;
> }
>
> +__weak void *board_spl_fit_buffer_addr(ulong fit_size, int sectors,
> int bl_len)
> +{
> + return spl_get_fit_load_buffer(sectors * bl_len);
> +}
> +
> /*
> * Weak default function to allow customizing SPL fit loading for
> load-only
> * use cases by allowing to skip the parsing/processing of the FIT
> contents
> @@ -631,7 +636,7 @@ static int spl_simple_fit_read(struct
> spl_fit_info *ctx,
> * For FIT with external data, data is not loaded in this
> step.
> */
> sectors = get_aligned_image_size(info, size, 0);
> - buf = spl_get_fit_load_buffer(sectors * info->bl_len);
> + buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len);
>
> count = info->read(info, sector, sectors, buf);
> ctx->fit = buf;
> --
> 2.31.1
>
Re: [EXT] Re: [PATCH] Revert "arm: bootm: Disable LMB reservation for command line and board info on arm64"
Hi Marek,
On Sun, 2021-08-08 at 17:25 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 8/8/21 4:54 PM, Tom Rini wrote:
>
> [...]
>
> >
> > >
> > > >
> > > > I expect it was not simply because up
> > > > until rather recently we didn't have any checks for "don't
> > > > overwrite
> > > > specific areas of memory" other than right before firing off
> > > > the OS (and
> > > > modify whatever memory you want to modify is a feature not a
> > > > bug).
> > > The LMB has been around since forever though ?
> > Yes, LMB has been around since the PowerPC device tree days I
> > suspect (I
> > didn't dig that far back), but only used outside of the "don't
> > overwrite
> > the running U-Boot while we relocate device tree / initrd before
> > booting
> > OS" since 2018 or so.
> So, are we using LMB for two different things now ?
>
> >
> > >
> > > [...]
> > >
> > > >
> > > > >
> > > > > >
> > > > > > OK, so then there isn't a problem reverting this commit for
> > > > > > rcar?
> > > > > The revert will break the use case where the other CPUs are
> > > > > using memory
> > > > > above U-Boot, but have a look at the following branch, it
> > > > > should permit me
> > > > > to parametrize the arch_lmb_reserve() better and reserve the
> > > > > right memory
> > > > > areas per architecture/mach/board, and even clean the
> > > > > arch_lmb_reserve up
> > > > > further:
> > > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%
> > > > > 2F%2Fsource.denx.de%2Fu-boot%2Fcustodians%2Fu-boot-sh%2F-
> > > > > %2Ftree%2Flmb-
> > > > > v1data=04%7C01%7Cye.li%40nxp.com%7Cb9bda480d0494a9249c70
> > > > > 8d95a80c552%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6376
> > > > > 40331407737098%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLC
> > > > > JQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata
> > > > > =yhIbMHWZMjXy59BVDFVbY2owM7TNdWvk%2B3w2IHg78ok%3Dreserve
> > > > > d=0
> > > > > So yes, pick the revert and I'll submit the four patches for
> > > > > likely next
> > > > > release.
> > > > Thanks for explaining, I'll pick up the revert patch then.
> > > >
> > > > For your LMB tree, I like the initial approach but looking at
> > > > 528915c71762 ("imx: Fix potential lmb memory overwritten by
> > > > stack") I
> > > > think that shows the general "4K is enough for stack we hope"
> > > > is wrong,
> > > > and we should do 16K instead for everyone as the default. But
> > > > we can
> > > > discuss that more too once you post the whole series which
> > > > again, I
> > > > think is the right direction.
> > > The IMX thing is odd indeed and raises a bigger question -- what
> > > is the
> > > "right" amount of stack to reserve ?
> > It's a good question, yes. And some more details about what
> > exactly the
> > NXP folks were doing to hit that would also be nice.
> +CC Ye Li.
On i.MX8QM/QXP, we implement the ft_system_setup to update kernel FDT.
It needs larger stack size to parse the FDT to disable nodes if the
corresponding resources are not owned by A core.
When we enabled the initrd relocation in u-boot, it allocates a space
from LMB for initrd just before the SP reservation. The stack overflow
overwrites the initrd and cause kernel issue.
The size of stack reservation actually depends on the implementation.
There are lots of board or soc level functions in the boot sequence.
You can't predict how much stack is needed. So providing a way that can
adjust the size is useful.
Best regards,
Ye Li
Re: [EXT] Re: [PATCH v1 0/2] imx8m: fix secure boot
On Fri, 2021-08-06 at 08:39 +0200, Heiko Schocher wrote: > Caution: EXT Email > > Hello Peng, > > On 06.08.21 07:56, Peng Fan (OSS) wrote: > > > > > > > > On 2021/8/6 12:44, Heiko Schocher wrote: > > > > > > > > > This series fixes secure boot on imx8m based boards. Tim > > > also detected this issue and the patches fixed on his hardware > > > also the problem, see discussion here: > > > > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2 > > > Flists.denx.de%2Fpipermail%2Fu-boot%2F2021- > > > July%2F454351.htmldata=04%7C01%7Cye.li%40nxp.com%7C4e50cef1a > > > 559457dc78c08d958a4f5d9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C > > > 0%7C637638287788477666%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD > > > AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata > > > =Rcmml9Sg0hSc%2FE68Dzjcn0wce1xYSpQNfJ0wfT4Jork%3Dreserved=0 > > > > > > > > > Problem is that the IVT header gets loaded to a memallocated > > > buffer, but it needs to sit on memaddress coded in IVT header > > > itself. This patchseries adds a weak function > > > spl_load_simple_fit() > > > in common spl code, which does not change current code behaviour. > > > > > > Second patch than implements this weak function for imx based > > > boards (if no IVT header is found on address which is passed > > > to it, it does nothing). > > > > > > I am not sure if this is the best solution, but it fixes a real > > > bug, and may could be made clearer, if possible. > > NXP downstream dropped malloc, with > > buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len); > > > > And this will use previous fixed address. > Ah, okay, you mean: > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsou > rce.codeaurora.org%2Fexternal%2Fimx%2Fuboot- > imx%2Ftree%2Farch%2Farm%2Fmach- > imx%2Fspl.c%3Fh%3Dlf_v2021.04%23n334data=04%7C01%7Cye.li%40nxp.c > om%7C4e50cef1a559457dc78c08d958a4f5d9%7C686ea1d3bc2b4c6fa92cd99c5c301 > 635%7C0%7C0%7C637638287788487624%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w > LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sda > ta=prhVBpPvqD1CDGWi7tWcN5%2BzChBeSQzeIK%2FvhedGcfE%3Dreserved=0 > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsou > rce.codeaurora.org%2Fexternal%2Fimx%2Fuboot- > imx%2Ftree%2Fcommon%2Fspl%2Fspl_fit.c%3Fh%3Dlf_v2021.04%23n541da > ta=04%7C01%7Cye.li%40nxp.com%7C4e50cef1a559457dc78c08d958a4f5d9%7C686 > ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637638287788487624%7CUnknown% > 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJ > XVCI6Mn0%3D%7C1000sdata=J%2FH%2FBBtiMMl9G744CjjPESEUVCxmO%2Bg7%2 > BHVJsM1yKc4%3Dreserved=0 > > and > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsou > rce.codeaurora.org%2Fexternal%2Fimx%2Fuboot- > imx%2Ftree%2Fcommon%2Fspl%2Fspl_fit.c%3Fh%3Dlf_v2021.04%23n581da > ta=04%7C01%7Cye.li%40nxp.com%7C4e50cef1a559457dc78c08d958a4f5d9%7C686 > ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637638287788487624%7CUnknown% > 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJ > XVCI6Mn0%3D%7C1000sdata=WVZ6Az8kazKu%2BWzysM7%2B3u5XHOb6gtggwiCK > rewnI2o%3Dreserved=0 > > correct? Yes. correct. > > But I do not see, where ivt->self is used... or is per definiton > ivt->self equal to: > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsou > rce.codeaurora.org%2Fexternal%2Fimx%2Fuboot- > imx%2Ftree%2Farch%2Farm%2Fmach- > imx%2Fspl.c%3Fh%3Dlf_v2021.04%23n345data=04%7C01%7Cye.li%40nxp.c > om%7C4e50cef1a559457dc78c08d958a4f5d9%7C686ea1d3bc2b4c6fa92cd99c5c301 > 635%7C0%7C0%7C637638287788487624%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w > LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sda > ta=Fo5efFghnqsyUvtuykwVm68NvDnk%2Fb1hCoiuQW1JkiA%3Dreserved=0 > > ? > The fit buffer was used in SPL is a fit size related offset to u-boot base. In mkimage, we generate IVT following the same calculation. So we don't use ivt->self, this address is aligned between SPL and IVT. Your patch depends on IVT. But actually IVT is not necessary for non- secure boot. The board_spl_fit_size_align in mach-imx/spl.c is only defined for HAB enabled. So for non-secure boot, it does not include size for IVT. This will be an issue. Best regards, Ye Li > bye, > Heiko > > > > > > > Regards, > > Peng. > > > > > > > > > > > > > > Heiko Schocher (2): > > > spl_fit. add hook to make fixes after fit header is loaded > > > imx: spl: implement spl_load_simple_fit_fix_load > > > > > > arch/arm/mach-imx/spl.c | 33 + > > > common/spl/spl_fit.c| 11 +++ > > > include/spl.h | 8 > > > 3 files changed, 52 insertions(+) > > > > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
RE: [EXT] Re: [PATCH 1/9] net: eqos: Add PHY reset control for i.MX platform
Hi Stefano,
Ok. I will rebase the patches after the 8ULP is merged.
Best regards,
Ye Li
> -Original Message-
> From: Stefano Babic
> Sent: Saturday, July 17, 2021 8:54 PM
> To: Ye Li ; sba...@denx.de; u-boot@lists.denx.de; Peng Fan
> ; ma...@denx.de
> Cc: rfried@gmail.com; dl-uboot-imx ;
> s.are...@sensopart.de
> Subject: [EXT] Re: [PATCH 1/9] net: eqos: Add PHY reset control for i.MX
> platform
>
> Caution: EXT Email
>
> Hi Ye,
>
> series was completely lost on my side, I tried to check it today but it is
> obsolete
> now and conflicts with Peng's series for MX8ULP. So I drop it, yorry, you
> should
> rebase and post it again.
>
> Best regards,
> Stefano Babic
>
> On 19.02.21 08:07, Ye Li wrote:
> > Parse the "phy-reset-gpios", "phy-reset-post-delay" and
> > "phy-reset-duration" properties from eqos node to control the ethernet
> > PHY reset at driver probe.
> > Reset PHY once is enough that can reduce the time cost to get IP after
> > the first time.
> >
> > Signed-off-by: Ye Li
> > ---
> > drivers/net/dwc_eth_qos.c | 55
> +++
> > 1 file changed, 55 insertions(+)
> >
> > diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> > index e8242ca..14aafc6 100644
> > --- a/drivers/net/dwc_eth_qos.c
> > +++ b/drivers/net/dwc_eth_qos.c
> > @@ -303,6 +303,8 @@ struct eqos_priv {
> > struct eqos_tegra186_regs *tegra186_regs;
> > struct reset_ctl reset_ctl;
> > struct gpio_desc phy_reset_gpio;
> > + uint32_t reset_delay;
> > + uint32_t reset_post_delay;
> > struct clk clk_master_bus;
> > struct clk clk_rx;
> > struct clk clk_ptp_ref;
> > @@ -1880,6 +1882,7 @@ static int eqos_probe_resources_imx(struct
> udevice *dev)
> > {
> > struct eqos_priv *eqos = dev_get_priv(dev);
> > phy_interface_t interface;
> > + int ret = 0;
> >
> > debug("%s(dev=%p):\n", __func__, dev);
> >
> > @@ -1890,8 +1893,52 @@ static int eqos_probe_resources_imx(struct
> udevice *dev)
> > return -EINVAL;
> > }
> >
> > + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
> > +>phy_reset_gpio,
> > +GPIOD_IS_OUT |
> GPIOD_IS_OUT_ACTIVE);
> > + if (ret) {
> > + pr_debug("gpio_request_by_name(phy reset) failed: %d",
> ret);
> > + }
> > +
> > + if (dm_gpio_is_valid(>phy_reset_gpio)) {
> > + eqos->reset_delay = dev_read_u32_default(dev,
> "phy-reset-duration", 1);
> > + if (eqos->reset_delay > 1000) {
> > + pr_err("phy reset duration should be <=
> 1000ms\n");
> > + /* property value wrong, use default value */
> > + eqos->reset_delay = 1;
> > + }
> > +
> > + mdelay(eqos->reset_delay);
> > +
> > + eqos->reset_post_delay = dev_read_u32_default(dev,
> > +
> "phy-reset-post-delay",
> > + 0);
> > + if (eqos->reset_post_delay > 1000) {
> > + pr_err("phy reset post delay should be <=
> 1000ms\n");
> > + /* property value wrong, use default value */
> > + eqos->reset_post_delay = 0;
> > + }
> > +
> > + ret = dm_gpio_set_value(>phy_reset_gpio, 0);
> > + if (ret < 0) {
> > + pr_err("dm_gpio_set_value(phy_reset, deassert)
> failed: %d", ret);
> > + goto err_free_gpio_phy_reset;
> > + }
> > +
> > + if (eqos->reset_post_delay)
> > + mdelay(eqos->reset_post_delay);
> > + }
> > +
> > debug("%s: OK\n", __func__);
> > return 0;
> > +
> > +err_free_gpio_phy_reset:
> > + if (dm_gpio_is_valid(>phy_reset_gpio)) {
> > + dm_gpio_free(dev, >phy_reset_gpio);
> > + }
> > +
> > + debug("%s: returns %d\n", __func__, ret);
> > + return ret;
> > }
> >
> > static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
> > @@ -1951,6 +1998,14 @@ static int eqos_remove_resources_stm32(struct
> > udevice *dev)
> >
> > static int eqos_remove_resources_imx(struct udevice *dev)
> > {
> > + struct eqos_priv *eqos = dev_get_priv(dev);
> > +
> > + debug("%s(dev=%p):\n", __func__, dev);
> > + if (dm_gpio_is_valid(>phy_reset_gpio)) {
> > + dm_gpio_free(dev, >phy_reset_gpio);
> > + }
> > +
> > + debug("%s: OK\n", __func__);
> > return 0;
> > }
> >
> >
>
> --
>
> =
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
>
> =
RE: [EXT] Re: Problem on imx: add rom api support on imx8mn
Hi Michael,
> -Original Message-
> From: Michael Nazzareno Trimarchi
> Sent: Thursday, July 15, 2021 2:52 PM
> To: Peng Fan (OSS)
> Cc: Peng Fan ; U-Boot-Denx ;
> Stefano Babic ; Ye Li ; Fabio Estevam
> ; Jagan Teki
> Subject: [EXT] Re: Problem on imx: add rom api support on imx8mn
>
> Caution: EXT Email
>
> Hi
>
> On Thu, Jul 15, 2021 at 8:47 AM Peng Fan (OSS)
> wrote:
> >
> >
> >
> > On 2021/7/8 17:15, Michael Nazzareno Trimarchi wrote:
> > > Hi Peng
> > >
> > > On Thu, Jul 8, 2021 at 9:12 AM Peng Fan (OSS)
> wrote:
> > >>
> > >> On 2021/7/4 1:24, Michael Nazzareno Trimarchi wrote:
> > >>> Hi all
> > >>>
> > >>> I have some problems that I have understood and fixed but I can
> > >>> not explain. Right now I have on imx8mn that can boot from boot0
> > >>> or boot1 partition after remove a condition in the
> > >>> is_boot_from_stream_device
> > >>>
> > >>> This is a boot from mmcblk0boot0 with some debug
> > >>>
> > >>> U-Boot SPL 2020.04-5.4.70-2.3.2+gf3bcbdfc62 (Jul 03 2021 -
> > >>> 17:00:27 +) power_bd71837_init
> > >>> DDRINFO: start DRAM init
> > >>> DDRINFO: DRAM rate 1600MTS
> > >>> DDRINFO:ddrphy calibration done
> > >>> DDRINFO: ddrmix config done
> > >>> Normal Boot
> > >>> Trying to boot from BOOTROM
> > >>> ROM API interface 2 from boot 131073
> > >>>
> > >>> Interface is 2 MMC and boot is 131073 and according to this
> > >>>
> > >>> static int is_boot_from_stream_device(u32 boot)
> > >>> +{
> > >>> + u32 interface;
> > >>> +
> > >>> + interface = boot >> 16;
> > >>> + if (interface >= BT_DEV_TYPE_USB)
> > >>> + return 1;
> > >>> +
> > >>> + if (interface == BT_DEV_TYPE_MMC && (boot & 1))
> > >>> + return 1;
> > >>> +
> > >>> + return 0;
> > >>> +}
> > >>>
> > >>> means a stream interface but it does not boot.
> > >>>
> > >>> Boot from boot1 give 131072 that is boot1 this let device boot
> > >>> because
> > >>
> > >> Who gives 131073? Boot from boot1, you mean emmc boot partition0?
> > >>
> > >>> is_boot_from_stream_device is 0 and romapi use
> > >>> spl_romapi_load_image_seekable
> > >>>
> > >>> Remove boot & 1 condition let me boot from mmcblk0boot0 and
> > >>> mmcblk0boot1 without any problem
> > >>
> > >> Have you enabled emmc fastboot in fuse?
> > >>
> > >> boot & 1 is checking emmc fastboot. emmc fastboot mode is actually
> > >> stream device. If fastboot mode enabled, you need burn your
> > >> flash.bin into offset 0. Not 32KB offset.
> > >
> > > The offset is correct and the spl is starting on boot0 but then it
> > > should load the rest from
> > > boot0 block and not from usb. And why in case of boot1 the 1 is not
> > > present. I flash both on offset 0. Anyway I sent a patch
> >
> > I suspect you have eMMC fastboot enabled for boot0, but not for boot1.
>
> I think that was fuse this way
>
> # Alternative Boot ("Fast boot")
> # =>[BT_FUSE_SEL | eMMC boot | USDHC1 EMMC]
> FB: ucmd fuse prog -y 1 3 0x10002A00
> # =>[Fast boot | 8-bit DDR | MMC High speed | 1.8V | eMMC reset enable]
> FB: ucmd fuse prog -y 2 1 0x00E7
> # =>[Fast Boot Ack enable]
> FB: ucmd fuse prog -y 2 2 0x00000001
> # boot_bus_width: 2 (8-bit), reset_boot_bus_width: 0, boot_mode: 2 (use dual
> data rate (DDR))
> FB: ucmd mmc bootbus 0 2 0 2
> # boot_ack: 1, boot_partition: 1 (Boot partition 1), 7 (User area),
> partition_access: No access to boot partition (default)
> FB: ucmd mmc partconf 0 1 1 0
>
> How is it supposed to work in this case?
>
Above settings use the boot0 for fastboot. When you switch to boot1 for
fastboot, did you change the
partconf setting to "mmc partconf 0 1 2 0"?
If the ROM boots from emmc fastboot, it will set the bit0 to 1 to indicate the
fastboot. Since at this time, ROM
does not leave fastboot (just stop the clock), we should continue the stream
mode read in SPL for FIT image load.
So below checking is correct. If you continue the stream mode read, what
[PATCH v2] usb: ehci-hcd: Add IAA handshake for removing async QH
According to EHCI spec, software needs to do handshake with HC for
safely removing QH from async list. This handshake is implemented by
setting IAAD (Interrupt on Async Advance Doorbell) bit in USB_USBCMD
register and poll the IAA (Interrupt on Async Advance bit) in the
USB_USBSTS to ensure the HC has released all on-chip state that may
potentially reference one of the data structures just removed.
Current codes only check active status of the last QTD, but this can't
ensure the QH is released from HC. We can meet unrecoverable
"EHCI timed out on TD" errors when running UEFI SCT tests on USB disk.
The USB_ASYNCLISTADDR register is changed to a invalid address when the
issue happens. It is fixed after adding the IAA handshake.
Steps to reproduce the issue:
1. Build the UEFI SCT from https://github.com/tianocore/edk2-test
2. Build the EDK2 UEFI Shell from https://github.com/tianocore/edk2
3. Copy SCT files and Shell.efi to USB disk FAT partition
4. Load the Shell.efi from USB FAT, and run bootefi to execute it
5. After booting into Shell, enter the SCT directory and run "sct -a"
to execute all tests.
6. Tests run about 1 hour and stop with many EHCI timeout errors like
EHCI timed out on TD - token=0x801f8c80
Signed-off-by: Ye Li
---
Changes in v2:
- Remove unnecessary cast and parenthesis
- Abort the transfer when IAA cycle timeout
- Add steps to reproduce the issue
drivers/usb/host/ehci-hcd.c | 27 +++
drivers/usb/host/ehci.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 8933f60..ba75c27 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -346,6 +346,28 @@ static int ehci_disable_async(struct ehci_ctrl *ctrl)
return ret;
}
+static int ehci_iaa_cycle(struct ehci_ctrl *ctrl)
+{
+ u32 cmd, status;
+ int ret;
+
+ /* Enable Interrupt on Async Advance Doorbell. */
+ cmd = ehci_readl(>hcor->or_usbcmd);
+ cmd |= CMD_IAAD;
+ ehci_writel(>hcor->or_usbcmd, cmd);
+
+ ret = handshake(>hcor->or_usbsts, STS_IAA, STS_IAA,
+ 10 * 1000); /* 10ms timeout */
+ if (ret < 0)
+ printf("EHCI fail timeout STS_IAA set\n");
+
+ status = ehci_readl(>hcor->or_usbsts);
+ if (status & STS_IAA)
+ ehci_writel(>hcor->or_usbsts, STS_IAA);
+
+ return ret;
+}
+
static int
ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, struct devrequest *req)
@@ -631,6 +653,11 @@ ehci_submit_async(struct usb_device *dev, unsigned long
pipe, void *buffer,
flush_dcache_range((unsigned long)>qh_list,
ALIGN_END_ADDR(struct QH, >qh_list, 1));
+ /* Set IAAD, poll IAA */
+ ret = ehci_iaa_cycle(ctrl);
+ if (ret)
+ goto fail;
+
/*
* Invalidate the memory area occupied by buffer
* Don't try to fix the buffer alignment, if it isn't properly
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 8e07554..e9e6f2a5 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -44,6 +44,7 @@ struct ehci_hcor {
#define STS_ASS(1 << 15)
#defineSTS_PSS (1 << 14)
#define STS_HALT (1 << 12)
+#define STS_IAA(1 << 5)
uint32_t or_usbintr;
#define INTR_UE (1 << 0)/* USB interrupt enable */
#define INTR_UEE(1 << 1)/* USB error interrupt enable
*/
--
2.7.4
Re: [EXT] Re: [PATCH] usb: ehci-hcd: Add IAA handshake for removing async QH
Hi Marek,
On Tue, 2021-03-09 at 09:08 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/9/21 4:18 AM, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> [...]
>
> >
> > >
> > > >
> > > >
> > > > + 10 * 1000); /* 10ms timeout */
> > > > + if (ret < 0)
> > > > + printf("EHCI fail timeout STS_IAA set\n");
> > > Shouldn't there be some abort ^ if ret < 0 ?
> > > Also, add the return value into the printf, it is useful for
> > > debugging.
> > I don't think need to abort anything when ret < 0. The ret value is
> > very simple in handshake, when ret < 0, it must be -1.
> > Actually the codes refer the ehci_enable_async for the usage of
> > handshake.
> If the handshake timed out, that indicates a problem and that problem
> shouldn't be ignored, but rather propagated, no ? Maybe the entire
> ehci
> transfer should be aborted ?
>
I supposed the problem means QH does not advance, so next submit of
async transfer will have QTD timeout. But it is ok to abort transfer as
the error handling.
> [...]
>
> >
> > >
> > > >
> > > >
> > > > + ehci_writel(>hcor->or_usbsts, STS_IAA);
> > > > +
> > > > + return ret;
> > > > +}
> > > Is this a bugfix for this release or is this for next release ?
> > > We're in rc3 already, so I would suggest to be careful.
> > It is ok to add the fix for next release. From our tests, the issue
> > is
> > not very easy to reproduce by just using usb read/write. In
> > SCT, generally we need to run about 1 hour to see the issue.
> Can you add details on how to reproduce the issue into the commit
> message ? That would be highly helpful.
ok. I will add more.
Best regards,
Ye Li
Re: [EXT] Re: [PATCH] usb: ehci-hcd: Add IAA handshake for removing async QH
Hi Marek,
On Mon, 2021-03-08 at 09:50 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/8/21 4:35 AM, Ye Li wrote:
> [...]
> >
> > +static int ehci_iaa_cycle(struct ehci_ctrl *ctrl)
> > +{
> > + u32 cmd, status;
> > + int ret;
> > +
> > + /* Enable Interrupt on Async Advance Doorbell. */
> > + cmd = ehci_readl(>hcor->or_usbcmd);
> > + cmd |= CMD_IAAD;
> > + ehci_writel(>hcor->or_usbcmd, cmd);
> > +
> > + ret = handshake((uint32_t *)>hcor->or_usbsts, STS_IAA,
> > STS_IAA,
> Is the (uint32_t *) cast really needed ?
>
I will remove it in v2.
> >
> > + 10 * 1000); /* 10ms timeout */
> > + if (ret < 0)
> > + printf("EHCI fail timeout STS_IAA set\n");
> Shouldn't there be some abort ^ if ret < 0 ?
> Also, add the return value into the printf, it is useful for
> debugging.
I don't think need to abort anything when ret < 0. The ret value is
very simple in handshake, when ret < 0, it must be -1.
Actually the codes refer the ehci_enable_async for the usage of
handshake.
>
> >
> > + status = ehci_readl(>hcor->or_usbsts);
> > + if ((status & STS_IAA))
> Drop the double parenthesis here, one set of () is enough.
>
I will remove it v2.
> >
> > + ehci_writel(>hcor->or_usbsts, STS_IAA);
> > +
> > + return ret;
> > +}
> Is this a bugfix for this release or is this for next release ?
> We're in rc3 already, so I would suggest to be careful.
It is ok to add the fix for next release. From our tests, the issue is
not very easy to reproduce by just using usb read/write. In
SCT, generally we need to run about 1 hour to see the issue.
Best regards,
Ye Li
[PATCH] usb: ehci-hcd: Add IAA handshake for removing async QH
According to EHCI spec, software needs to do handshake with HC for
safely removing QH from async list. This handshake is implemented by
setting IAAD (Interrupt on Async Advance Doorbell) bit in USB_USBCMD
register and poll the IAA (Interrupt on Async Advance bit) in the
USB_USBSTS to ensure the HC has released all on-chip state that may
potentially reference one of the data structures just removed.
Current codes only check active status of the last QTD, but this can't
ensure the QH is released from HC. We can meet unrecoverable
"EHCI timed out on TD" errors when running SCT tests on USB disk. The
USB_ASYNCLISTADDR register is changed to a invalid address when the
issue happens. It is fixed after adding the IAA handshake.
Signed-off-by: Ye Li
---
drivers/usb/host/ehci-hcd.c | 25 +
drivers/usb/host/ehci.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 8933f60..b52a903 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -346,6 +346,28 @@ static int ehci_disable_async(struct ehci_ctrl *ctrl)
return ret;
}
+static int ehci_iaa_cycle(struct ehci_ctrl *ctrl)
+{
+ u32 cmd, status;
+ int ret;
+
+ /* Enable Interrupt on Async Advance Doorbell. */
+ cmd = ehci_readl(>hcor->or_usbcmd);
+ cmd |= CMD_IAAD;
+ ehci_writel(>hcor->or_usbcmd, cmd);
+
+ ret = handshake((uint32_t *)>hcor->or_usbsts, STS_IAA, STS_IAA,
+ 10 * 1000); /* 10ms timeout */
+ if (ret < 0)
+ printf("EHCI fail timeout STS_IAA set\n");
+
+ status = ehci_readl(>hcor->or_usbsts);
+ if ((status & STS_IAA))
+ ehci_writel(>hcor->or_usbsts, STS_IAA);
+
+ return ret;
+}
+
static int
ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, struct devrequest *req)
@@ -631,6 +653,9 @@ ehci_submit_async(struct usb_device *dev, unsigned long
pipe, void *buffer,
flush_dcache_range((unsigned long)>qh_list,
ALIGN_END_ADDR(struct QH, >qh_list, 1));
+ /* Set IAAD, poll IAA */
+ ehci_iaa_cycle(ctrl);
+
/*
* Invalidate the memory area occupied by buffer
* Don't try to fix the buffer alignment, if it isn't properly
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 8e07554..e9e6f2a5 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -44,6 +44,7 @@ struct ehci_hcor {
#define STS_ASS(1 << 15)
#defineSTS_PSS (1 << 14)
#define STS_HALT (1 << 12)
+#define STS_IAA(1 << 5)
uint32_t or_usbintr;
#define INTR_UE (1 << 0)/* USB interrupt enable */
#define INTR_UEE(1 << 1)/* USB error interrupt enable
*/
--
2.7.4
Re: [EXT] [PATCH] ARM: imx: Add OCRAM_S into iMX8M MMU tables
Hi Marek,
On Fri, 2021-02-26 at 13:44 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 2/26/21 8:15 AM, Ye Li wrote:
> >
> > Hi Marek,
> >
> > On Thu, 2021-02-25 at 21:52 +0100, Marek Vasut wrote:
> > >
> > > Caution: EXT Email
> > >
> > > The OCRAM_S is regular memory, just like the OCRAM, add it to the
> > > MMU
> > > tables so it can be used and cached.
> > >
> > > Signed-off-by: Marek Vasut
> > > Cc: Fabio Estevam
> > > Cc: Peng Fan
> > > Cc: Stefano Babic
> > > ---
> > > arch/arm/mach-imx/imx8m/soc.c | 7 +++
> > > 1 file changed, 7 insertions(+)
> > >
> > > diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-
> > > imx/imx8m/soc.c
> > > index 5456c10fb17..225e4e12500 100644
> > > --- a/arch/arm/mach-imx/imx8m/soc.c
> > > +++ b/arch/arm/mach-imx/imx8m/soc.c
> > > @@ -104,6 +104,13 @@ static struct mm_region imx8m_mem_map[] = {
> > > .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> > > PTE_BLOCK_NON_SHARE |
> > > PTE_BLOCK_PXN | PTE_BLOCK_UXN
> > > + }, {
> > > + /* OCRAM_S */
> > > + .virt = 0x18UL,
> > > + .phys = 0x18UL,
> > > + .size = 0x8000UL,
> > > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> > > +PTE_BLOCK_OUTER_SHARE
> > > }, {
> > > /* TCM */
> > > .virt = 0x7CUL,
> > > --
> > > 2.30.0
> > >
> > OCRAM_S is used by ATF and SPL to pass DDR CSR data.
> Where is this implemented ?
See below definition in drivers/ddr/imx/imx8m/Kconfig
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
help
after DRAM is trained, need to save the dram related timming
info into memory for low power use. OCRAM_S is used for this
purpose on i.MX8MM.
default 0x18
>
> >
> > It is better not
> > use it in u-boot to avoid any DDR issue.
> The MMU table entry does not trigger any IO to the OCRAM_S , it
> merely
> makes it cacheable .
>
That's fine to add a map, just remind to use it carefully since it
already used by ATF.
> >
> > And this imx8m_mem_map will be modified at runtime to get rid of
> > optee
> > memory. When OCRAM_S is added, the index used in enable_caches and
> > dram_init need update as well.
> I'm not sure I understand this. What kind of modification are you
> talking about ? The DRAM entry offset should be determined
> automatically, so there shouldn't be any need to hand-tune ad-hoc
> offsets.
You also need below change, the index for DRAM1 is used in codes to
help remove the OPTEE space from MMU table.
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -167,10 +167,10 @@ void enable_caches(void)
* please make sure that entry initial value matches
* imx8m_mem_map for DRAM1
*/
- int entry = 5;
+ int entry = 6;
u64 attrs = imx8m_mem_map[entry].attrs;
- while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
+ while (i < CONFIG_NR_DRAM_BANKS && entry < 9) {
if (gd->bd->bi_dram[i].start == 0)
break;
imx8m_mem_map[entry].phys = gd->bd-
>bi_dram[i].start;
@@ -212,7 +212,7 @@ int dram_init(void)
gd->ram_size = sdram_size;
/* also update the SDRAM size in the mem_map used externally */
- imx8m_mem_map[5].size = sdram_size;
+ imx8m_mem_map[6].size = sdram_size;
#ifdef PHYS_SDRAM_2_SIZE
gd->ram_size += PHYS_SDRAM_2_SIZE;
Best regards,
Ye Li
Re: [EXT] Re: [PATCH 4/4] imx8mq_evk: Enable the USB3.0 host port
Hi Fabio,
On Thu, 2021-02-25 at 10:49 -0300, Fabio Estevam wrote:
> Caution: EXT Email
>
> Hi Ye Li,
>
> On Thu, Feb 25, 2021 at 10:34 AM Ye Li wrote:
>
> >
> > Sure, I have tested it on 8mq evk. I can reproduce the two issues
> > you
> > met.
> > The first issue is caused by the ALIGN. The implementation of
> > standard
> > ALIGN requires the aligned size to be power of 2. But the ALIGN in
> > imx8mimage does not have this requirement. So below result is wrong
> > by
> > using the standard ALIGN. Your fix should be OK for this issue.
> Good, could you please reply to my ALIGN macro patch with your
> Tested-by tag then?
>
Replied it.
> >
> > For the second issue, I did not debug into it. But our vendor tree
> > also
> > uses off-on-delay-us in both u-boot and kernel. So it is likely
> > caused
> > by other change.
> Considering we are already at 2021.04-rc2, I think it would be safer
> to go with my patch that removes off-on-delay-us.
>
> What do you think?
>
> Thanks
My debug shows the issue is triggered by below commit:
commit 9098682200e6cca4b776638a51200dafa16f50fb
Author: Haibo Chen
Date: Tue Sep 22 18:11:43 2020 +0800
mmc: fsl_esdhc_imx: remove the 1ms delay before sending command
This 1ms delay before sending command already exist from the
beginning
of the fsl_esdhc driver added in year 2008. Now this driver has
been
split for two files: fsl_esdhc.c and fsl_esdhc_imx.c.
fsl_esdhc_imx.c
only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms
delay
before sending any command. So remove this 1ms, this will save a
lot
time if handling a large mmc data.
Signed-off-by: Haibo Chen
The first "go idle" command in mmc_get_op_cond seems not put SD card to
idle status, but if adding a delay before it (like 1ms delay), then
everything works. This commit removed 1ms delay in sending command, so
the issue is triggered. The root cause might be "startup-delay-us"
needed for this regulator to reach a threshold voltage for SD working.
Below change also can fix the issue.
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
_usdhc2_vmmc {
+ startup-delay-us = <1000>;
u-boot,off-on-delay-us = <2>;
};
@Haibo, Could you help looking into the issue. What's your opinion to
add the startup-delay-us or revert your commit?
Best regards,
Ye Li
