Re: [U-Boot] [PATCH] driver: spi: add spansion s25fs-s family protect/unprotect

2016-08-15 Thread Yunhui Cui 

On August 15, 2016 4:02 PM, Jagan Teki Wrote:
> On 15 August 2016 at 11:42, Yunhui Cui <b56...@freescale.com> wrote:
> > From: Yunhui Cui <yunhui@nxp.com>
> >
> > In order to support spansion s25fs512s flash protect/unprotect:
> >
> > [1] Fill callbak flash->lock/unlock/is_locked by spansion_lock/
> > unlock/is_locked.
> 
> Try to use existing lock code and add spansion on top of that.

[Yunhui] the spansion s25fs-s family cannot share the existing lock code, 
because it need some specific operations through SR1NV.thanks

> 
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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[U-Boot] [PATCH] driver: spi: add spansion s25fs-s family protect/unprotect

2016-08-15 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

In order to support spansion s25fs512s flash protect/unprotect:

[1] Fill callbak flash->lock/unlock/is_locked by spansion_lock/
unlock/is_locked.

[2] Achieve protect/unprotected by operating sr1nv, cr1nv.

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 drivers/mtd/spi/spi_flash.c | 195 
 1 file changed, 195 insertions(+)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 64d4e0f..446e6e3 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -839,6 +839,194 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t 
len)
 }
 #endif
 
+#if defined(CONFIG_SPI_FLASH_SPANSION)
+/*
+ * Return 1 if the entire region is locked, 0 otherwise
+ */
+static int spansion_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
+   u8 sr)
+{
+   loff_t lock_offs;
+   u64 lock_len;
+
+   stm_get_locked_range(flash, sr, _offs, _len);
+
+   return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
+}
+
+/*
+ * Check if a region of the flash is (completely) locked. See spansion_lock()
+ * for more info.
+ *
+ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
+ * negative on errors.
+ */
+int spansion_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
+{
+   u8 cmd[4];
+   u32 sr1nv_offset = 0x0;
+   u8 sr1nv;
+   int ret;
+
+   cmd[0] = CMD_SPANSION_RDAR;
+   cmd[1] = sr1nv_offset >> 16;
+   cmd[2] = sr1nv_offset >> 8;
+   cmd[3] = sr1nv_offset >> 0;
+
+   ret = spi_flash_cmd_read(flash->spi, cmd, 4, , 1);
+   if (ret)
+   return -EIO;
+
+   return spansion_is_locked_sr(flash, ofs, len, sr1nv);
+}
+
+/*
+ * Lock a region of the flash. Compatible with Spansion s25fs-s family flash.
+ * Supports only the block protection bits BP{0,1,2} in the Status Register-1
+ * Non-Volatile(SR1NV).
+ *
+ * Sample table portion for 64MB flash (S25FS512S):
+ * Configuration Register-1 Non-Volatile(CR1NV[5])== 0
+ *
+ *  |  BP2  |  BP1  |  BP0  |  Prot Length  | Protected Portion
+ *  
+ *  |   0   |   0   |   0   |  NONE  | NONE
+ *  |   0   |   0   |   1   |  1  MB | Upper 1/64
+ *  |   0   |   1   |   0   |  2  MB | Upper 1/32
+ *  |   0   |   1   |   1   |  4  MB | Upper 1/16
+ *  |   1   |   0   |   0   |  8  MB | Upper 1/8
+ *  |   1   |   0   |   1   |  16 MB | Upper 1/4
+ *  |   1   |   1   |   0   |  32 MB | Upper 1/2
+ *  |   1   |   1   |   1   |  64 MB | ALL
+ *
+ * When CR1NV[5] == 1, the Lower memory array are protected.
+ *
+ * Returns negative on errors, 0 on success.
+ */
+int spansion_lock(struct spi_flash *flash, u32 ofs, size_t len)
+{
+   u8 status_old, status_new;
+   u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+   u8 shift = ffs(mask) - 1, pow, val;
+   int ret;
+   u8 cmd[4];
+   u32 sr1nv_offset = 0x0;
+   u8 sr1nv;
+
+   cmd[0] = CMD_SPANSION_RDAR;
+   cmd[1] = sr1nv_offset >> 16;
+   cmd[2] = sr1nv_offset >> 8;
+   cmd[3] = sr1nv_offset >> 0;
+
+   ret = spi_flash_cmd_read(flash->spi, cmd, 4, , 1);
+   if (ret)
+   return -EIO;
+   status_old = sr1nv;
+
+   /* SPI NOR always locks to the end */
+   if (ofs + len != flash->size) {
+   /* Does combined region extend to end? */
+   if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
+ status_old))
+   return -EINVAL;
+   len = flash->size - ofs;
+   }
+
+   /*
+* Need smallest pow such that:
+*
+*   1 / (2^pow) <= (len / size)
+*
+* so (assuming power-of-2 size) we do:
+*
+*   pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
+*/
+   pow = ilog2(flash->size) - ilog2(len);
+   val = mask - (pow << shift);
+   if (val & ~mask)
+   return -EINVAL;
+
+   /* Don't "lock" with no region! */
+   if (!(val & mask))
+   return -EINVAL;
+
+   status_new = (status_old & ~mask) | val;
+
+   /* Only modify protection if it will not unlock other areas */
+   if ((status_new & mask) <= (status_old & mask))
+   return -EINVAL;
+
+   cmd[0] = CMD_SPANSION_WRAR;
+   ret = spi_flash_cmd_write(flash->spi, cmd, 4, _new, 1);
+   if (ret)
+   return -EIO;
+
+   return 0;
+}
+
+/*
+ * Unlock a region of the flash. See spansion_lock() for more info
+ *
+ * Returns negative on errors, 0 on success.
+ */
+int spansion_unlock(struct spi_flash *flash, u32 ofs, size_t len)
+{
+   uint8_t status_old, status_new;
+   u8 mask = SR_B

Re: [U-Boot] [PATCH v2] driver: spi: fsl-qspi: remove compile Warnings

2016-08-03 Thread Yunhui Cui 

Thanks a lot!

Yunhui

> -Original Message-
> From: york sun
> Sent: Wednesday, August 03, 2016 6:40 AM
> To: Yunhui Cui
> Cc: u-boot@lists.denx.de; Yunhui Cui
> Subject: Re: [PATCH v2] driver: spi: fsl-qspi: remove compile Warnings
> 
> On 07/12/2016 07:57 PM, Yunhui Cui wrote:
> > From: Yunhui Cui <yunhui@nxp.com>
> >
> > Warnins log:
> > drivers/spi/fsl_qspi.c: In function 'qspi_ahb_read':
> > drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of
> different size [-Wint-to-pointer-cast]
> >   memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
> >
> > Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> > ---
> >  drivers/spi/fsl_qspi.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> 
> Applied to fsl-qoriq master, awaiting upstream.
> Thanks.
> 
> York
> 

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Re: [U-Boot] [PATCH v3] driver: spi: fsl-qspi: disable AHB buffer prefetch

2016-07-20 Thread Yunhui Cui 

On Tuesday, July 12, 2016 11:06 AM Prabhakar Wrote
> 
> > -Original Message-
> > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Yunhui
> > Cui
> > Sent: Tuesday, July 12, 2016 8:20 AM
> > To: york sun <york@nxp.com>
> > Cc: Yunhui Cui <yunhui@nxp.com>; u-boot@lists.denx.de
> > Subject: [U-Boot] [PATCH v3] driver: spi: fsl-qspi: disable AHB buffer
> > prefetch
> >
> > From: Yunhui Cui <yunhui@nxp.com>
> >
> > Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data
> > We need this errata workaround when CONFIG_SYS_FSL_QSPI_AHB is enabled.
> >
> 
> Can we add slightly more details about workaround other than Just
> enabling CONFIG_SYS_FSL_QSPI_AHB.
> With this you can avoid details of workaround in code.
> 
[Yunhui] ok!

> Please add CONFIG_SYS_FSL_QSPI_AHB in README file

[Yunhui] why should we add it and how to add it ?

> 
> > Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> > ---
> 
> Patch revision history missing.
> 
> --prabhakar

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Re: [U-Boot] [PATCH] driver: spi: fsl-qspi: remove compile Warnings

2016-07-13 Thread Yunhui Cui 


On 07/12, 2016 11:12 PM York wrote:
> On 07/11/2016 09:08 PM, Yunhui Cui wrote:
> > From: Yunhui Cui <yunhui@nxp.com>
> >
> > Warnins log:
> > drivers/spi/fsl_qspi.c: In function 'qspi_ahb_read':
> > drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of
> different size [-Wint-to-pointer-cast]
> >memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
> >
> > Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> > ---
> >   drivers/spi/fsl_qspi.c | 4 +++-
> >   1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 75cbab2..6c69be4 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -386,6 +386,7 @@ static inline void qspi_ahb_read(struct
> fsl_qspi_priv *priv, u8 *rxbuf, int len)
> >   {
> > struct fsl_qspi_regs *regs = priv->regs;
> > u32 mcr_reg;
> > +   void *rx_addr = NULL;
> >
> > mcr_reg = qspi_read32(priv->flags, >mcr);
> >
> > @@ -393,8 +394,9 @@ static inline void qspi_ahb_read(struct
> fsl_qspi_priv *priv, u8 *rxbuf, int len)
> >  QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
> >  QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
> >
> > +   rx_addr += priv->cur_amba_base + priv->sf_addr;
> > /* Read out the data directly from the AHB buffer. */
> > -   memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
> > +   memcpy(rxbuf, rx_addr, len);
> >
> > qspi_write32(priv->flags, >mcr, mcr_reg);
> >   }
> >
> Would it be better to use (void *)(uintptr_t)(priv->cur_amba_base +
> priv->sf_addr)?
> 
> York
> 
[Yunhui] Thanks for your suggestions , I will update it in v2.

Thanks
Yunhui


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Re: [U-Boot] [PATCH v3] driver: spi: fsl-qspi: disable AHB buffer prefetch

2016-07-13 Thread Yunhui Cui 

On 07/12/2016 11:15 PM, York wrote:
> On 07/11/2016 08:00 PM, Yunhui Cui wrote:
> > From: Yunhui Cui <yunhui@nxp.com>
> >
> > Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data
> > We need this errata workaround when CONFIG_SYS_FSL_QSPI_AHB is enabled.
> >
> > Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> > ---
> >   drivers/spi/fsl_qspi.c | 12 +++-
> >   1 file changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 75cbab2..0354e20 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -438,13 +438,23 @@ static void qspi_enable_ddr_mode(struct
> fsl_qspi_priv *priv)
> >   static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
> >   {
> > struct fsl_qspi_regs *regs = priv->regs;
> > +   int rx_size = 0x80;
> 
> Wrap this with ifdef, or you will have compiling warning when the macro
> is not defined.
> 
> York

[Yunhui] Whether This macro defined or not, rx_size will be used, It seems that 
Wrap is not necessary and have no compiling warning. 

thanks.
Yunhui


> 
> 
> >
> > /* AHB configuration for access buffer 0/1/2 .*/
> > qspi_write32(priv->flags, >buf0cr,
> QSPI_BUFXCR_INVALID_MSTRID);
> > qspi_write32(priv->flags, >buf1cr,
> QSPI_BUFXCR_INVALID_MSTRID);
> > qspi_write32(priv->flags, >buf2cr,
> > QSPI_BUFXCR_INVALID_MSTRID);
> > +
> > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009282
> > +   /*A-009282: QuadSPI data pre-fetch can result in incorrect data
> > +*Workaround: Keep the read data size to 64 bits (8 Bytes), which
> > +*disables the prefetch on the AHB buffer,and prevents this issue
> > +*from occurring.
> > +   */
> > +   rx_size = 0x1;
> > +#endif
> > qspi_write32(priv->flags, >buf3cr, QSPI_BUF3CR_ALLMST_MASK |
> > -(0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
> > +(rx_size << QSPI_BUF3CR_ADATSZ_SHIFT));
> >
> > /* We only use the buffer3 */
> > qspi_write32(priv->flags, >buf0ind, 0);
> >

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[U-Boot] [PATCH v2] driver: spi: fsl-qspi: remove compile Warnings

2016-07-12 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of 
different size [-Wint-to-pointer-cast]
  memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 drivers/spi/fsl_qspi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 75cbab2..2144fca 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -386,6 +386,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv 
*priv, u8 *rxbuf, int len)
 {
struct fsl_qspi_regs *regs = priv->regs;
u32 mcr_reg;
+   void *rx_addr = NULL;
 
mcr_reg = qspi_read32(priv->flags, >mcr);
 
@@ -393,8 +394,9 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv 
*priv, u8 *rxbuf, int len)
 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 
+   rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
/* Read out the data directly from the AHB buffer. */
-   memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
+   memcpy(rxbuf, rx_addr, len);
 
qspi_write32(priv->flags, >mcr, mcr_reg);
 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] driver: spi: fsl-qspi: remove compile Warnings

2016-07-11 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of 
different size [-Wint-to-pointer-cast]
  memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 drivers/spi/fsl_qspi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 75cbab2..6c69be4 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -386,6 +386,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv 
*priv, u8 *rxbuf, int len)
 {
struct fsl_qspi_regs *regs = priv->regs;
u32 mcr_reg;
+   void *rx_addr = NULL;
 
mcr_reg = qspi_read32(priv->flags, >mcr);
 
@@ -393,8 +394,9 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv 
*priv, u8 *rxbuf, int len)
 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 
+   rx_addr += priv->cur_amba_base + priv->sf_addr;
/* Read out the data directly from the AHB buffer. */
-   memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
+   memcpy(rxbuf, rx_addr, len);
 
qspi_write32(priv->flags, >mcr, mcr_reg);
 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3] driver: spi: fsl-qspi: disable AHB buffer prefetch

2016-07-11 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data
We need this errata workaround when CONFIG_SYS_FSL_QSPI_AHB is enabled.

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 drivers/spi/fsl_qspi.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 75cbab2..0354e20 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -438,13 +438,23 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv 
*priv)
 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 {
struct fsl_qspi_regs *regs = priv->regs;
+   int rx_size = 0x80;
 
/* AHB configuration for access buffer 0/1/2 .*/
qspi_write32(priv->flags, >buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, >buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, >buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009282
+   /*A-009282: QuadSPI data pre-fetch can result in incorrect data
+*Workaround: Keep the read data size to 64 bits (8 Bytes), which
+*disables the prefetch on the AHB buffer,and prevents this issue
+*from occurring.
+   */
+   rx_size = 0x1;
+#endif
qspi_write32(priv->flags, >buf3cr, QSPI_BUF3CR_ALLMST_MASK |
-(0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
+(rx_size << QSPI_BUF3CR_ADATSZ_SHIFT));
 
/* We only use the buffer3 */
qspi_write32(priv->flags, >buf0ind, 0);
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v2] driver: fsl_qspi: disable AHB buffer prefetch

2016-07-11 Thread Yunhui Cui 

On 07/11, 2016, 11:17 PM, York Wrote:
> On 07/11/2016 12:49 AM, Yunhui Cui wrote:
> > From: Yunhui Cui <yunhui@nxp.com>
> >
> > Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data
> >
> > Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> > ---
> >   drivers/spi/fsl_qspi.c | 14 --
> >   1 file changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 75cbab2..99634db 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -438,14 +438,24 @@ static void qspi_enable_ddr_mode(struct
> fsl_qspi_priv *priv)
> >   static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
> >   {
> > struct fsl_qspi_regs *regs = priv->regs;
> > +   int rx_size = 0x80;
> >
> > /* AHB configuration for access buffer 0/1/2 .*/
> > qspi_write32(priv->flags, >buf0cr,
> QSPI_BUFXCR_INVALID_MSTRID);
> > qspi_write32(priv->flags, >buf1cr,
> QSPI_BUFXCR_INVALID_MSTRID);
> > qspi_write32(priv->flags, >buf2cr,
> QSPI_BUFXCR_INVALID_MSTRID);
> > -   qspi_write32(priv->flags, >buf3cr, QSPI_BUF3CR_ALLMST_MASK |
> > -(0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
> >
> > +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) \
> > +   || defined(CONFIG_LS1012A) || defined(CONFIG_LS102XA)
> > +   /*A-009282: QuadSPI data pre-fetch can result in incorrect data
> > +*Workaround: Keep the read data size to 64 bits (8 Bytes), which
> > +*disables the prefetch on the AHB buffer,and prevents this issue
> > +*from occurring.
> > +   */
> > +   rx_size = 0x1;
> > +#endif
> > +   qspi_write32(priv->flags, >buf3cr, QSPI_BUF3CR_ALLMST_MASK |
> > +(rx_size << QSPI_BUF3CR_ADATSZ_SHIFT));
> > /* We only use the buffer3 */
> > qspi_write32(priv->flags, >buf0ind, 0);
> > qspi_write32(priv->flags, >buf1ind, 0);
> >
> 
> Yunhui,
> 
> I suggested to use erratum macro, like CONFIG_SYS_FSL_ERRATUM_A009282.

[Yunhui] ok, I will update it in v3, thanks a lot.

> 
> York

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[U-Boot] [PATCH v2] driver: fsl_qspi: disable AHB buffer prefetch

2016-07-11 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 drivers/spi/fsl_qspi.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 75cbab2..99634db 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -438,14 +438,24 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv 
*priv)
 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 {
struct fsl_qspi_regs *regs = priv->regs;
+   int rx_size = 0x80;
 
/* AHB configuration for access buffer 0/1/2 .*/
qspi_write32(priv->flags, >buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, >buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, >buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
-   qspi_write32(priv->flags, >buf3cr, QSPI_BUF3CR_ALLMST_MASK |
-(0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
 
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) \
+   || defined(CONFIG_LS1012A) || defined(CONFIG_LS102XA)
+   /*A-009282: QuadSPI data pre-fetch can result in incorrect data
+*Workaround: Keep the read data size to 64 bits (8 Bytes), which
+*disables the prefetch on the AHB buffer,and prevents this issue
+*from occurring.
+   */
+   rx_size = 0x1;
+#endif
+   qspi_write32(priv->flags, >buf3cr, QSPI_BUF3CR_ALLMST_MASK |
+(rx_size << QSPI_BUF3CR_ADATSZ_SHIFT));
/* We only use the buffer3 */
qspi_write32(priv->flags, >buf0ind, 0);
qspi_write32(priv->flags, >buf1ind, 0);
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH] driver: fsl_qspi: disable AHB buffer prefetch

2016-07-11 Thread Yunhui Cui 


On 07/07/2016 10:55 PM, York wrote:
> On 07/07/2016 12:52 AM, Yunhui Cui wrote:
> >
> >> On 07/07/2016 1:01 AM, york sun wrote:
> >> On 07/03/2016 08:27 PM, Yunhui Cui wrote:
> >>> From: Yunhui Cui <yunhui@nxp.com>
> >>>
> >>> A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect
> >>> data
> >>> Affects: QuadSPI
> >>> Description: With AHB buffer prefetch enabled, the QuadSPI may
> >>> return incorrect data on the AHB interface. The buffer pre-fetch is
> >>> enabled if the fetch size as configured either in the LUT or in the
> >>> BUFxCR register is greater than 8 bytes.
> >>> Impact: Only 64 bit read allowed.
> >>> Workaround: Keep the read data size to 64 bits (8 Bytes), which
> >>> disables the prefetch on the AHB buffer, and prevents this issue
> >>> from occurring.
> >>>
> >>> Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> >>> ---
> >>>drivers/spi/fsl_qspi.c | 2 +-
> >>>1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> >>> 75cbab2..e0a002d 100644
> >>> --- a/drivers/spi/fsl_qspi.c
> >>> +++ b/drivers/spi/fsl_qspi.c
> >>> @@ -444,7 +444,7 @@ static void qspi_init_ahb_read(struct
> >>> fsl_qspi_priv
> >> *priv)
> >>>   qspi_write32(priv->flags, >buf1cr,
> >> QSPI_BUFXCR_INVALID_MSTRID);
> >>>   qspi_write32(priv->flags, >buf2cr,
> >> QSPI_BUFXCR_INVALID_MSTRID);
> >>>   qspi_write32(priv->flags, >buf3cr,
> QSPI_BUF3CR_ALLMST_MASK |
> >>> -  (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
> >>> +  (0x1 << QSPI_BUF3CR_ADATSZ_SHIFT));
> >>>
> >>>   /* We only use the buffer3 */
> >>>   qspi_write32(priv->flags, >buf0ind, 0);
> >>>
> >>
> >> Yunhui,
> >>
> >> We handle erratum workaround using macros in case the workaround has
> >> impact on other SoCs.
> >
> > [Yunhui] For now, all SoCs with Qspi module need this errata.
> 
> I still think it is better to gate the workaround with #ifdef in case we
> need to disable it for future SoCs. It will also be easier to locate the
> workaround code.

[Yunhui] ok, I will update it in v2, thanks.

> 
> >
> >> We also put the erratum information either in a
> >> README file, or inline comment. It will be easier to read the code
> later.
> >
> > [Yunhui] ok, I will add inline comment in next version.
> >
> >> You don't have to put the whole erratum description in the commit
> message,
> >> as long as it explains what this patch does and refer the erratum
> number
> >> somewhere in the message so we can search the git log.
> >>
> >> York
> >
> > [Yunhui] ok, I will update the commit message in next version.
> >
> 
> Thanks.
> 
> York
> 

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Re: [U-Boot] [PATCH] driver: fsl_qspi: disable AHB buffer prefetch

2016-07-07 Thread Yunhui Cui 

>On 07/07/2016 1:01 AM, york sun wrote: 
> On 07/03/2016 08:27 PM, Yunhui Cui wrote:
> > From: Yunhui Cui <yunhui@nxp.com>
> >
> > A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
> > Affects: QuadSPI
> > Description: With AHB buffer prefetch enabled, the QuadSPI may return
> > incorrect data on the AHB interface. The buffer pre-fetch is enabled
> > if the fetch size as configured either in the LUT or in the BUFxCR
> > register is greater than 8 bytes.
> > Impact: Only 64 bit read allowed.
> > Workaround: Keep the read data size to 64 bits (8 Bytes), which
> > disables the prefetch on the AHB buffer, and prevents this issue from
> > occurring.
> >
> > Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> > ---
> >   drivers/spi/fsl_qspi.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 75cbab2..e0a002d 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -444,7 +444,7 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv
> *priv)
> > qspi_write32(priv->flags, >buf1cr,
> QSPI_BUFXCR_INVALID_MSTRID);
> > qspi_write32(priv->flags, >buf2cr,
> QSPI_BUFXCR_INVALID_MSTRID);
> > qspi_write32(priv->flags, >buf3cr, QSPI_BUF3CR_ALLMST_MASK |
> > -(0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
> > +(0x1 << QSPI_BUF3CR_ADATSZ_SHIFT));
> >
> > /* We only use the buffer3 */
> > qspi_write32(priv->flags, >buf0ind, 0);
> >
> 
> Yunhui,
> 
> We handle erratum workaround using macros in case the workaround has
> impact on other SoCs.

[Yunhui] For now, all SoCs with Qspi module need this errata.

> We also put the erratum information either in a
> README file, or inline comment. It will be easier to read the code later.

[Yunhui] ok, I will add inline comment in next version.

> You don't have to put the whole erratum description in the commit message,
> as long as it explains what this patch does and refer the erratum number
> somewhere in the message so we can search the git log.
> 
> York

[Yunhui] ok, I will update the commit message in next version.

Thanks
Yunhui




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[U-Boot] [PATCH] driver: fsl_qspi: disable AHB buffer prefetch

2016-07-04 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
Affects: QuadSPI
Description: With AHB buffer prefetch enabled, the QuadSPI may return
incorrect data on the AHB interface. The buffer pre-fetch is enabled
if the fetch size as configured either in the LUT or in the BUFxCR register
is greater than 8 bytes.
Impact: Only 64 bit read allowed.
Workaround: Keep the read data size to 64 bits (8 Bytes), which disables
the prefetch on the AHB buffer,
and prevents this issue from occurring.

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 75cbab2..e0a002d 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -444,7 +444,7 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
qspi_write32(priv->flags, >buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, >buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, >buf3cr, QSPI_BUF3CR_ALLMST_MASK |
-(0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
+(0x1 << QSPI_BUF3CR_ADATSZ_SHIFT));
 
/* We only use the buffer3 */
qspi_write32(priv->flags, >buf0ind, 0);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v4] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-06-08 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

The SP805-WDT module on LS2080A and LS2085A, requires configuration
of PMU's PCTBENR register to enable watchdog counter decrement and
reset signal generation. In order not to affect the sp805wdt driver
frame, we enable the watchdog clk in advance.

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 15 +++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  1 +
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d939900..1ac1067 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -639,6 +639,10 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
+#ifdef CONFIG_LS2080A
+   u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+   u32 pmu_val;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 
@@ -653,6 +657,17 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A
+/*
+ * In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+pmu_val = in_le32(pctbenr);
+pmu_val |= 0xff;
+out_le32(pctbenr, pmu_val);
+#endif
+
/* Enable clock for timer
 * This is a global setting.
 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1d3b336..ba3b94d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_FSL_TIMER_ADDR  0x023d
 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B8)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-06-08 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

The SP805-WDT module on LS2080A and LS2085A, requires configuration
of PMU's PCTBENR register to enable watchdog counter decrement and
reset signal generation. In order not to affect the sp805wdt driver
frame, we enable the watchdog clk in advance.

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 12 
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d939900..79eb4dc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -639,6 +639,9 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
+#ifdef CONFIG_LS2080A
+   u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 
@@ -653,6 +656,15 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A
+   /*
+* In certain Layerscape SoCs, the clock for each core's
+* has an enable bit in the PMU Physical Core Time Base Enable
+* Register (PCTBENR), which allows the watchdog to operate.
+*/
+   setbits_le32(pctbenr, 0xff);
+#endif
+
/* Enable clock for timer
 * This is a global setting.
 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1d3b336..8121939 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_FSL_TIMER_ADDR  0x023d
 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B8)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v4] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-06-07 Thread Yunhui Cui 
On 06/07/2016 11:57 PM, York Sun wrote:
> On 06/07/2016 02:28 AM, Yunhui Cui wrote:
> > From: Yunhui Cui <yunhui@nxp.com>
> >
> > The SP805-WDT module on LS2080A and LS2085A, requires configuration of
> > PMU's PCTBENR register to enable watchdog counter decrement and reset
> > signal generation. In order not to affect the sp805wdt driver frame,
> > we enable the watchdog clk in advance.
> >
> > Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 15
> +++
> >  arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  1 +
> >  2 files changed, 16 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > index d939900..1ac1067 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > @@ -639,6 +639,10 @@ int timer_init(void)  #ifdef CONFIG_FSL_LSCH3
> > u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;  #endif
> > +#ifdef CONFIG_LS2080A
> > +   u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
> > +   u32 pmu_val;
> > +#endif
> >  #ifdef COUNTER_FREQUENCY_REAL
> > unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
> >
> > @@ -653,6 +657,17 @@ int timer_init(void)
> > out_le32(cltbenr, 0xf);
> >  #endif
> >
> > +#ifdef CONFIG_LS2080A
> > +/*
> > + * In certain Layerscape SoCs, the clock for each core's
> > + * has an enable bit in the PMU Physical Core Time Base Enable
> > + * Register (PCTBENR), which allows the watchdog to operate.
> > + */
> > +pmu_val = in_le32(pctbenr);
> > +pmu_val |= 0xff;
> > +out_le32(pctbenr, pmu_val);
> > +#endif
> > +
> 
> You could use setbits_le32() instead of three lines.
> Also inappropriate indentation.
> 
> York

OK,thanks for your review and suggestions, I will send v5 to update it.

Yunhui






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Re: [U-Boot] [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-06-07 Thread Yunhui Cui 
Hi York,

Thanks for your suggestions, and I moved the code into timer_init() and sent v4 
.

Best Regards,
Yunhui

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, May 17, 2016 11:44 PM
> To: Yunhui Cui; Yunhui Cui
> Cc: u-boot@lists.denx.de; Prabhakar Kushwaha
> Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable
> WDT
> 
> On 05/16/2016 08:28 PM, Yunhui Cui wrote:
> > Hi York,
> >
> >  I think you can move your code into timer_init() in cpu.c and follow
> the example of cltbenr.
> > [Yunhui] During the u_boot imamge compiled by using the
> ls2080ardb_defconfig bootup on ls2080ardb, timer_init() cannot be
> called ...
> >So maybe cannot move the code to timer_init().
> 
> 
> Yunhui,
> 
> First, please reply inline. This is how we do review in the mailing list.
> 
> Second, please check your code again. Function timer_init() must be
> called. You cannot get away from it. Otherwise, you don't have a general
> timer and all delay functions fail.
> 
> York
> 
> >
> >> -Original Message-
> >> From: York Sun [mailto:york@nxp.com]
> >> Sent: Tuesday, May 17, 2016 12:14 AM
> >> To: Yunhui Cui
> >> Cc: u-boot@lists.denx.de; Yunhui Cui; Prabhakar Kushwaha
> >> Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to
> >> enable WDT
> >>
> >> On 04/14/2016 08:57 PM, Yunhui Cui wrote:
> >>> From: Yunhui Cui <yunhui@nxp.com>
> >>>
> >>> The SP805-WDT module on LS2080A and LS2085A, requires configuration
> >>> of PMU's PCTBENR register to enable watchdog counter decrement and
> >>> reset signal generation. In order not to affect the sp805wdt driver
> >>> frame, we enable the watchdog clk in advance.
> >>>
> >>> Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> >>> ---
> >>>  arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 15
> +++
> >>>  arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 
> >>>  arch/arm/include/asm/arch-fsl-layerscape/soc.h|  1 +
> >>>  board/freescale/ls2080aqds/ls2080aqds.c   |  2 ++
> >>>  board/freescale/ls2080ardb/ls2080ardb.c   |  2 ++
> >>>  5 files changed, 24 insertions(+)
> >>>
> >>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> index 0cb0100..c36976d 100644
> >>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> @@ -42,6 +42,21 @@ bool soc_has_aiop(void)
> >>>   return false;
> >>>  }
> >>>
> >>> +#if defined(CONFIG_LS2080A)
> >>> +/*
> >>> + * In certain Layerscape SoCs, the clock for each core's watchdog
> >>> + * has an enable bit in the PMU Physical Core Time Base Enable
> >>> +Register
> >>> + * (PCTBENR), which allows the watchdog to operate.
> >>> + */
> >>> +void enable_watchdog_clk(void)
> >>> +{
> >>> + u32 pmu_val;
> >>> +
> >>> + pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
> >>> + *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
> >>> +0xff; } #endif
> >>> +
> >>>  #ifdef CONFIG_LS2080A
> >>>  /*
> >>>   * This erratum requires setting a value to eddrtqcr1 to diff --git
> >>> a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>> index 10d17b2..62e4f95 100644
> >>> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>> @@ -143,6 +143,10 @@
> >>>  #define CONFIG_ARM_ERRATA_829520
> >>>  #define CONFIG_ARM_ERRATA_833471
> >>>
> >>> +/* PMU-Physical Core Time Base Enable Register */
> >>> +#define FSL_PMU_REG_BASE 0x1E3
> >>> +#define FSL_PMU_PCTBENR_OFFSET   0x8A0
> >>> +
> >>>  #elif defined(CONFIG_LS1043A)
> >>>  #define CONFIG_MAX_CPUS  4
> >>>  #define CONFIG_SYS_CACHELINE_SIZE64
> >>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >>> b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >>> index 831d817..bd4a8f1 100644
> >>> --- a/arch/arm/include/asm/arch-fsl-layersc

Re: [U-Boot] [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-05-16 Thread Yunhui Cui 
Hi York,

 I think you can move your code into timer_init() in cpu.c and follow the 
example of cltbenr.
[Yunhui] During the u_boot imamge compiled by using the ls2080ardb_defconfig 
bootup on ls2080ardb, timer_init() cannot be called ...
   So maybe cannot move the code to timer_init().

Thanks
Yunhui

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, May 17, 2016 12:14 AM
> To: Yunhui Cui
> Cc: u-boot@lists.denx.de; Yunhui Cui; Prabhakar Kushwaha
> Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable
> WDT
> 
> On 04/14/2016 08:57 PM, Yunhui Cui wrote:
> > From: Yunhui Cui <yunhui@nxp.com>
> >
> > The SP805-WDT module on LS2080A and LS2085A, requires configuration of
> > PMU's PCTBENR register to enable watchdog counter decrement and reset
> > signal generation. In order not to affect the sp805wdt driver frame,
> > we enable the watchdog clk in advance.
> >
> > Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 15 +++
> >  arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 
> >  arch/arm/include/asm/arch-fsl-layerscape/soc.h|  1 +
> >  board/freescale/ls2080aqds/ls2080aqds.c   |  2 ++
> >  board/freescale/ls2080ardb/ls2080ardb.c   |  2 ++
> >  5 files changed, 24 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 0cb0100..c36976d 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -42,6 +42,21 @@ bool soc_has_aiop(void)
> > return false;
> >  }
> >
> > +#if defined(CONFIG_LS2080A)
> > +/*
> > + * In certain Layerscape SoCs, the clock for each core's watchdog
> > + * has an enable bit in the PMU Physical Core Time Base Enable
> > +Register
> > + * (PCTBENR), which allows the watchdog to operate.
> > + */
> > +void enable_watchdog_clk(void)
> > +{
> > +   u32 pmu_val;
> > +
> > +   pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
> > +   *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
> > +0xff; } #endif
> > +
> >  #ifdef CONFIG_LS2080A
> >  /*
> >   * This erratum requires setting a value to eddrtqcr1 to diff --git
> > a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > index 10d17b2..62e4f95 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > @@ -143,6 +143,10 @@
> >  #define CONFIG_ARM_ERRATA_829520
> >  #define CONFIG_ARM_ERRATA_833471
> >
> > +/* PMU-Physical Core Time Base Enable Register */
> > +#define FSL_PMU_REG_BASE   0x1E3
> > +#define FSL_PMU_PCTBENR_OFFSET 0x8A0
> > +
> >  #elif defined(CONFIG_LS1043A)
> >  #define CONFIG_MAX_CPUS4
> >  #define CONFIG_SYS_CACHELINE_SIZE  64
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> > index 831d817..bd4a8f1 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> > @@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);  #endif
> >
> >  void cpu_name(char *name);
> > +void enable_watchdog_clk(void);
> >  #ifdef CONFIG_SYS_FSL_ERRATUM_A009635  void erratum_a009635(void);
> > #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
> > b/board/freescale/ls2080aqds/ls2080aqds.c
> > index b3bd40a..c109349 100644
> > --- a/board/freescale/ls2080aqds/ls2080aqds.c
> > +++ b/board/freescale/ls2080aqds/ls2080aqds.c
> > @@ -213,6 +213,8 @@ int board_init(void)
> > select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
> > rtc_enable_32khz_output();
> >
> > +   enable_watchdog_clk();
> > +
> > return 0;
> >  }
> >
> > diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
> > b/board/freescale/ls2080ardb/ls2080ardb.c
> > index fb39af6..7872f1f 100644
> > --- a/board/freescale/ls2080ardb/ls2080ardb.c
> > +++ b/board/freescale/ls2080ardb/ls2080ardb.c
> > @@ -181,6 +181,8 @@ int board_init(void)
> > /* invert AQR405 IRQ pins polarity */
> > out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
> >
> > +   enable_watchdog_clk();
> > +
> > return 0;
> >  }
> >
> >
> Yunhui,
> 
> I think you can move your code into timer_init() in cpu.c and follow the
> example of cltbenr.
> 
> York
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[U-Boot] [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-04-15 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

The SP805-WDT module on LS2080A and LS2085A, requires configuration
of PMU's PCTBENR register to enable watchdog counter decrement and
reset signal generation. In order not to affect the sp805wdt driver
frame, we enable the watchdog clk in advance.

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 15 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 
 arch/arm/include/asm/arch-fsl-layerscape/soc.h|  1 +
 board/freescale/ls2080aqds/ls2080aqds.c   |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c   |  2 ++
 5 files changed, 24 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0cb0100..c36976d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+   u32 pmu_val;
+
+   pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+   *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val | 0xff;
+}
+#endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 10d17b2..62e4f95 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE   0x1E3
+#define FSL_PMU_PCTBENR_OFFSET 0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS4
 #define CONFIG_SYS_CACHELINE_SIZE  64
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 831d817..bd4a8f1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);
 #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 void erratum_a009635(void);
 #endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..c109349 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -213,6 +213,8 @@ int board_init(void)
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
rtc_enable_32khz_output();
 
+   enable_watchdog_clk();
+
return 0;
 }
 
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index fb39af6..7872f1f 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -181,6 +181,8 @@ int board_init(void)
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+   enable_watchdog_clk();
+
return 0;
 }
 
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v2] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-04-14 Thread Yunhui Cui 
Hi Stuart,

Thanks for your suggestions about the patch, I will update it in v3 version.

Thanks
Yunhui

-Original Message-
From: Stuart Yoder 
Sent: Friday, April 15, 2016 10:16 AM
To: Yunhui Cui
Cc: york sun; u-boot@lists.denx.de
Subject: RE: [U-Boot] [PATCH v2] armv8/ls2080a: configure PMU's PCTBENR to 
enable WDT



> -Original Message-
> From: Yunhui Cui
> Sent: Thursday, April 14, 2016 8:47 PM
> To: Stuart Yoder <stuart.yo...@nxp.com>
> Cc: york sun <york@nxp.com>; u-boot@lists.denx.de
> Subject: RE: [U-Boot] [PATCH v2] armv8/ls2080a: configure PMU's PCTBENR to 
> enable WDT
> 
> Hi Stuart,
> 
> 
> Yunhui, I thought that York recently sent patches to get rid of 
> CONFIG_LS2085A.
> [Yunhui] Only need add  #if defined(CONFIG_LS2080A) ?

Right.

> I think this is getting too specific and adds unnecessary details.
> What if we have A72 cores? ...as we will soon.  What about other SoCs? Just 
> say:
> 
>/*
> * In certain Layerscape SoCs, the clock for each core's watchdog
> * has an enable bit in the PMU Physical Core Time Base Enable Register
> * PCTBENR), which allows the watchdog to operate.

Looks like I missed an openening parenthesis in my suggestion.

Thanks,
Stuart
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Re: [U-Boot] [PATCH v2] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-04-14 Thread Yunhui Cui 
Hi Stuart,


Yunhui, I thought that York recently sent patches to get rid of CONFIG_LS2085A.
[Yunhui] Only need add  #if defined(CONFIG_LS2080A) ?


I think this is getting too specific and adds unnecessary details.
What if we have A72 cores? ...as we will soon.  What about other SoCs? Just say:

   /*
* In certain Layerscape SoCs, the clock for each core's watchdog
* has an enable bit in the PMU Physical Core Time Base Enable Register
* PCTBENR), which allows the watchdog to operate.
*/
[Yunhui] That's ok ,thanks!


Thanks 
Yunhui

-Original Message-
From: Stuart Yoder 
Sent: Friday, April 15, 2016 12:34 AM
To: Yunhui Cui
Cc: york sun; u-boot@lists.denx.de
Subject: RE: [U-Boot] [PATCH v2] armv8/ls2080a: configure PMU's PCTBENR to 
enable WDT



> -Original Message-
> From: Yunhui Cui <b56...@freescale.com>
> Date: Sun, Apr 10, 2016 at 9:37 PM
> Subject: [U-Boot] [PATCH v2] armv8/ls2080a: configure PMU's PCTBENR to 
> enable WDT
> To: york@nxp.com
> Cc: yunhui@nxp.com, u-boot@lists.denx.de
> 
> 
> From: Yunhui Cui <yunhui@nxp.com>
> 
> The SP805-WDT module on LS2080A and LS2085A, requires configuration of 
> PMU's PCTBENR register to enable watchdog counter decrement and reset 
> signal generation. In order not to affect the sp805wdt driver frame, 
> we enable the watchdog clk in advance.
> 
> Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 17 +
>  arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h|  1 +
>  board/freescale/ls2080aqds/ls2080aqds.c   |  2 ++
>  board/freescale/ls2080ardb/ls2080ardb.c   |  2 ++
>  5 files changed, 26 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index a76447e..e6f3566 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -17,6 +17,23 @@
>  #endif
> 
>  DECLARE_GLOBAL_DATA_PTR;
> +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)

Yunhui, I thought that York recently sent patches to get rid of CONFIG_LS2085A.

See the patch:
[PATCH v3] armv8: LS2080A: Consolidate LS2080A and LS2085A

> +/*
> + * There are eight SP805 watchdog units on ls2080a/ls2085a,So
> + * Set PMU-Physical Core Time Base Enable Register (PCTBENR)
> + * low eight bits to enable clocks to eight Cortext-A57 cores
> + * timebase, which allows the WDT counter to decrement and raise
> + * a reset request (if configured in the WDTCONTROL register).
> + */

I think this is getting too specific and adds unnecessary details.
What if we have A72 cores? ...as we will soon.  What about other SoCs? Just say:

   /*
* In certain Layerscape SoCs, the clock for each core's watchdog
* has an enable bit in the PMU Physical Core Time Base Enable Register
* PCTBENR), which allows the watchdog to operate.
*/

Thanks,
Stuart
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Re: [U-Boot] [PATCH] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-04-11 Thread Yunhui Cui 
Hi Bhupesh,

Thanks for your suggestions about the patch. I will update it in the next 
version.

Thanks
Yunhui

-Original Message-
From: Bhupesh Sharma 
Sent: Friday, April 08, 2016 11:17 PM
To: Yunhui Cui; york sun
Cc: Yunhui Cui; u-boot@lists.denx.de
Subject: RE: [U-Boot] [PATCH] armv8/ls2080a: configure PMU's PCTBENR to enable 
WDT

> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Yunhui 
> Cui
> Sent: Friday, April 08, 2016 3:57 PM
> To: york sun
> Cc: Yunhui Cui; u-boot@lists.denx.de
> Subject: [U-Boot] [PATCH] armv8/ls2080a: configure PMU's PCTBENR to 
> enable WDT
> 
> From: Yunhui Cui <yunhui@nxp.com>
> 
> The SP805-WDT module on LS2080A and LS2085A, requires configuration of 
> PMU's PCTBENR register to enable watchdog counter decrement and reset 
> signal generation. In order not to affect the sp805wdt driver frame, 
> we enable the watchdog clk in advance.
> 
> Signed-off-by: Yunhui Cui <yunhui@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 ++
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h |  1 +
>  board/freescale/ls2080aqds/ls2080aqds.c|  2 ++
>  board/freescale/ls2080ardb/ls2080ardb.c|  2 ++
>  4 files changed, 23 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index a76447e..06c950f 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -17,6 +17,24 @@
>  #endif
> 
>  DECLARE_GLOBAL_DATA_PTR;
> +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
> +/*
> + * Set the bit corresponding to our watchDog-id in the
> + * PMU-Physical Core Time Base Enable Register (PCTBENR)
> + * to allow the WDT counter to decrement and raise a reset
> + * request (if configured in the WDTCONTROL register).
> + */

This comment does not describe correctly the flow you are using in the function 
below.

> +void enable_watchdog_clk(void)
> +{
> + #define FSL_PMU_REG_BASE0x1E3
> + #define FSL_PMU_PCTBENR_OFFSET  0x8A0

Can we move the #define into a proper header file 
'arch/arm/include/asm/arch-fsl-layerscape/config.h':
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-fsl-layerscape/config.h;h=ceefe431fdcbd6aa3a176bc3631338c62d4bb976;hb=HEAD

Regards,
Bhupesh

> + u32 pmu_val;
> +
> + pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
> + *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
> 0xff;
> +} #endif
> +
> 
>  #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
>  /*
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> index 56989e1..32c9185 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> @@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);  #endif
> 
>  void cpu_name(char *name);
> +void enable_watchdog_clk(void);
>  #ifdef CONFIG_SYS_FSL_ERRATUM_A009635  void erratum_a009635(void);  
> #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
> b/board/freescale/ls2080aqds/ls2080aqds.c
> index e1a521d..8ebc96a 100644
> --- a/board/freescale/ls2080aqds/ls2080aqds.c
> +++ b/board/freescale/ls2080aqds/ls2080aqds.c
> @@ -213,6 +213,8 @@ int board_init(void)
>   select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
>   rtc_enable_32khz_output();
> 
> + enable_watchdog_clk();
> +
>   return 0;
>  }
> 
> diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
> b/board/freescale/ls2080ardb/ls2080ardb.c
> index 8201048..ad8324a 100644
> --- a/board/freescale/ls2080ardb/ls2080ardb.c
> +++ b/board/freescale/ls2080ardb/ls2080ardb.c
> @@ -181,6 +181,8 @@ int board_init(void)
>   /* invert AQR405 IRQ pins polarity */
>   out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
> 
> + enable_watchdog_clk();
> +
>   return 0;
>  }
> 
> --
> 2.1.0.27.g96db324
> 
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[U-Boot] [PATCH v2] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-04-11 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

The SP805-WDT module on LS2080A and LS2085A, requires configuration
of PMU's PCTBENR register to enable watchdog counter decrement and
reset signal generation. In order not to affect the sp805wdt driver
frame, we enable the watchdog clk in advance.

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 17 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 
 arch/arm/include/asm/arch-fsl-layerscape/soc.h|  1 +
 board/freescale/ls2080aqds/ls2080aqds.c   |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c   |  2 ++
 5 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index a76447e..e6f3566 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -17,6 +17,23 @@
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+/*
+ * There are eight SP805 watchdog units on ls2080a/ls2085a,So
+ * Set PMU-Physical Core Time Base Enable Register (PCTBENR)
+ * low eight bits to enable clocks to eight Cortext-A57 cores
+ * timebase, which allows the WDT counter to decrement and raise
+ * a reset request (if configured in the WDTCONTROL register).
+ */
+void enable_watchdog_clk(void)
+{
+   u32 pmu_val;
+
+   pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+   *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val | 0xff;
+}
+#endif
+
 
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
 /*
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index ceefe43..b9656d7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -148,6 +148,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE   0x1E3
+#define FSL_PMU_PCTBENR_OFFSET 0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS4
 #define CONFIG_SYS_CACHELINE_SIZE  64
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 56989e1..32c9185 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);
 #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 void erratum_a009635(void);
 #endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index e1a521d..8ebc96a 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -213,6 +213,8 @@ int board_init(void)
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
rtc_enable_32khz_output();
 
+   enable_watchdog_clk();
+
return 0;
 }
 
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index 8201048..ad8324a 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -181,6 +181,8 @@ int board_init(void)
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+   enable_watchdog_clk();
+
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

2016-04-08 Thread Yunhui Cui 
From: Yunhui Cui <yunhui@nxp.com>

The SP805-WDT module on LS2080A and LS2085A, requires configuration
of PMU's PCTBENR register to enable watchdog counter decrement and
reset signal generation. In order not to affect the sp805wdt driver
frame, we enable the watchdog clk in advance.

Signed-off-by: Yunhui Cui <yunhui@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c|  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c|  2 ++
 4 files changed, 23 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index a76447e..06c950f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -17,6 +17,24 @@
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+/*
+ * Set the bit corresponding to our watchDog-id in the
+ * PMU-Physical Core Time Base Enable Register (PCTBENR)
+ * to allow the WDT counter to decrement and raise a reset
+ * request (if configured in the WDTCONTROL register).
+ */
+void enable_watchdog_clk(void)
+{
+   #define FSL_PMU_REG_BASE0x1E3
+   #define FSL_PMU_PCTBENR_OFFSET  0x8A0
+   u32 pmu_val;
+
+   pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+   *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val | 0xff;
+}
+#endif
+
 
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
 /*
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 56989e1..32c9185 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);
 #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 void erratum_a009635(void);
 #endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index e1a521d..8ebc96a 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -213,6 +213,8 @@ int board_init(void)
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
rtc_enable_32khz_output();
 
+   enable_watchdog_clk();
+
return 0;
 }
 
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index 8201048..ad8324a 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -181,6 +181,8 @@ int board_init(void)
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+   enable_watchdog_clk();
+
return 0;
 }
 
-- 
2.1.0.27.g96db324

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