[PATCH v1 16/16] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
Booting Agilex and Stratix 10 with ATF support. SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The new boot flow with ATF support is as follow: SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux) U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE). ATF will occupy the address range starting from 0x1000. Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_atf_defconfig| 71 configs/socfpga_stratix10_atf_defconfig | 73 + 2 files changed, 144 insertions(+) create mode 100644 configs/socfpga_agilex_atf_defconfig create mode 100644 configs/socfpga_stratix10_atf_defconfig diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig new file mode 100644 index 00..4af1021809 --- /dev/null +++ b/configs/socfpga_agilex_atf_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x20 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="board/altera/soc64/fit_spl_atf.sh" +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon" +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig new file mode 100644 index 00..f50d5030fb --- /dev/null +++ b/configs/socfpga_stratix10_atf_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x20 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="board/altera/soc64/fit_spl_atf.sh" +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon" +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y -- 2.19.0
[PATCH v1 15/16] arm: socfpga: soc64: Skip handoff data access in SSBL
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 3da85791a1..049c5711a8 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -12,6 +12,7 @@
const struct cm_config * const cm_get_default_config(void)
{
+#ifdef CONFIG_SPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
@@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void)
} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
return cm_handoff_cfg;
}
-
+#endif
return NULL;
}
--
2.19.0
[PATCH v1 14/16] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
Since SSBL is running in DRAM, it shall setup the stack in DRAM instead of OCRAM which is occupied by SPL and handoff data. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index cb9bb21597..dadd21b0ba 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -40,9 +40,14 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE0 #define CONFIG_SYS_INIT_RAM_SIZE 0x4 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - S10_HANDOFF_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE \ + + 0x10) +#endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) -- 2.19.0
[PATCH v1 12/16] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 9a1dc2c0c8..f5fd9a14c2 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -8,11 +8,149 @@
#include
#include
#include
+#include
#include
+#include
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#define BITSTREAM_CHUNK_SIZE 0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ return -ETIMEDOUT; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ WATCHDOG_RESET();
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bitstream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, ARRAY_SIZE(res_buf));
+ if (!ret) {
+ for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(2);
+ }
+ WATCHDOG_RESET();
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+ u64 arg = 1;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, , 1, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bitstream(rbf_data, rbf_size);
+ if (ret) {
+ puts("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ puts("FPGA r
[PATCH v1 11/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index e5eb7f4aeb..79b8044aa0 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@
*/
#include
+#include
#include
#include
+#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,12 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, , 1, NULL, 0))
+ hang();
+#else
u32 reg;
if (enable) {
@@ -101,6 +110,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.19.0
[PATCH v1 13/16] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 18d44924e6..429444f069 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -398,6 +399,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -406,6 +410,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.19.0
[PATCH v1 10/16] net: designware: socfpga: Add ATF support for MAC driver
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
---
drivers/net/dwmac_socfpga.c | 43 +
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561dffa..0dd5a54405 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -17,7 +17,9 @@
#include
#include
+#include
#include
+#include
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
@@ -64,6 +66,35 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static int dwmac_socfpga_fw_setphy(struct udevice *dev, u32 modereg)
+{
+ struct ofnode_phandle_args pargs;
+ u64 args[2];
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
+1, 0, );
+ if (ret) {
+ dev_err(dev, "Failed to get syscon: %d\n", ret);
+ return ret;
+ }
+
+ if (pargs.args_count < 1) {
+ dev_err(dev, "No syscon args found\n");
+ return -EINVAL;
+ }
+
+ args[0] = ((u64)pargs.args[0] - SYSMGR_SOC64_EMAC0) >> 2;
+ args[1] = modereg;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0))
+ return -EIO;
+
+ return 0;
+}
+#endif
+
static int dwmac_socfpga_probe(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +102,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct reset_ctl_bulk reset_bulk;
int ret;
u32 modereg;
- u32 modemask;
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -97,9 +127,14 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ ret = dwmac_socfpga_fw_setphy(dev, modereg);
+ if (ret)
+ return ret;
+#else
+ clrsetbits_le32(pdata->phy_intf, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
+ pdata->reg_shift, modereg << pdata->reg_shift);
+#endif
reset_release_bulk(_bulk);
--
2.19.0
[PATCH v1 08/16] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services
This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang --- include/linux/intel-smc.h | 573 ++ 1 file changed, 573 insertions(+) create mode 100644 include/linux/intel-smc.h diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 00..fa7d1dff56 --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2018, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include +#include + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of kernel tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * value. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * FPGA configuration completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the FPGA configuration process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0x +#define INTEL_SIP_SMC_STATUS_OK0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_REG_ERROR0x5 +#define INTEL_SIP_SMC_RSU_ERROR0x7 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + *0 full reconfiguration. + *1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any completed + * block, otherwise zero value. + * a2: 6
[PATCH v1 06/16] arm: socfpga: Disable "spin-table" method for booting Linux
Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 26f2cf8e47..01f5a1fc41 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -79,7 +78,6 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select FPGA_INTEL_SDM_MAILBOX choice -- 2.19.0
[PATCH v1 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
---
drivers/mmc/socfpga_dw_mmc.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..a58ea472b9 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -13,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -46,6 +48,20 @@ static void socfpga_dwmci_reset(struct udevice *dev)
reset_deassert_bulk(_bulk);
}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static void socfpga_dwmci_fw_clksel(u32 sdmmc_mask)
+{
+ u64 args[2];
+
+ /* drvsel */
+ args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7;
+ /* smplsel */
+ args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7;
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0))
+ dev_err(host->dev, "SMC call failed in %s\n", __func__);
+}
+#endif
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
@@ -58,10 +74,14 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ socfpga_dwmci_fw_clksel(sdmmc_mask);
+#else
writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.19.0
[PATCH v1 05/16] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Makefile | 2 + arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 + 2 files changed, 78 insertions(+) create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543b20..c63162a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S new file mode 100644 index 00..612ea8a037 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include +#include +#include + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +wait_for_atf: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, slave_wait_atf + br x5 +slave_wait_atf: + branch_if_slave x0, wait_for_atf +#else + branch_if_slave x0, 1f +#endif + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + +#ifdef CONFIG_ARMV8_MULTIENTRY + branch_if_master x0, x1, 2f + + /* +* Slave should wait for master clearing spin table. +* This sync prevent slaves observing incorrect +* value of spin table and jumping to wrong place. +*/ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* +* All slaves will enter EL2 and optionally EL1. +*/ + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el2 + +lowlevel_in_el2: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el1 + +lowlevel_in_el1: +#endif + +#endif /* CONFIG_ARMV8_MULTIENTRY */ + +2: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) -- 2.19.0
[PATCH v1 07/16] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
arch/arm/mach-socfpga/smc_api.c | 56
3 files changed, 71 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/smc_api.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c63162a5c6..0b05283a7a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -72,6 +72,8 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
endif
+else
+obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h
b/arch/arm/mach-socfpga/include/mach/smc_api.h
new file mode 100644
index 00..bbefdd8dd9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smc_api.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _SMC_API_H_
+#define _SMC_API_H_
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf);
+
+#endif /* _SMC_API_H_ */
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
new file mode 100644
index 00..085daba162
--- /dev/null
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy([1], args, arg_len * sizeof(*args));
+
+ smc_call();
+
+ if (ret_arg)
+ memcpy(ret_arg, [1], ret_len * sizeof(*ret_arg));
+
+ return regs.regs[0];
+}
+
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf)
+{
+ int ret;
+ u64 args[6];
+ u64 resp[3];
+
+ args[0] = cmd;
+ args[1] = (u64)arg;
+ args[2] = len;
+ args[3] = urgent;
+ args[4] = (u64)resp_buf;
+ if (resp_buf_len)
+ args[5] = *resp_buf_len;
+ else
+ args[5] = 0;
+
+ ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
+resp, ARRAY_SIZE(resp));
+
+ if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+ if (!resp[0])
+ *resp_buf_len = resp[1];
+ }
+
+ return (int)resp[0];
+}
--
2.19.0
[PATCH v1 04/16] arm: socfpga: soc64: Load FIT image with ATF support
Instead of loading u-boot proper image (u-boot.img), SPL now loads FIT image (u-boot.itb) which includes u-boot proper, ATF and u-boot proper's DTB. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index fb5e2e8aaf..cb9bb21597 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -193,6 +193,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); - CONFIG_SYS_SPL_MALLOC_SIZE) /* SPL SDMMC boot support */ +#ifdef CONFIG_SPL_LOAD_FIT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.itb" +#else #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img" +#endif #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ -- 2.19.0
[PATCH v1 02/16] arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang
---
board/altera/soc64/fit_spl_atf.sh | 91 +++
1 file changed, 91 insertions(+)
create mode 100755 board/altera/soc64/fit_spl_atf.sh
diff --git a/board/altera/soc64/fit_spl_atf.sh
b/board/altera/soc64/fit_spl_atf.sh
new file mode 100755
index 00..482ca36f9b
--- /dev/null
+++ b/board/altera/soc64/fit_spl_atf.sh
@@ -0,0 +1,91 @@
+#!/bin/sh
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for Agilex boards with
+# U-Boot proper, ATF and device tree for U-Boot proper.
+#
+# usage: $0
+
+BL31="bl31.bin"
+if [ ! -f $BL31 ]; then
+ echo "BL31 file \"$BL31\" NOT found!" >&2
+ exit 1
+fi
+
+BL33="u-boot-nodtb.bin"
+if [ ! -f $BL33 ]; then
+ echo "BL33 file \"$BL33\" NOT found!" >&2
+ exit 1
+fi
+
+if [ -f "$1" ] ; then
+ DT_NAME="$1"
+else
+ echo "File not found: \"$1\"" >&2
+ exit 1
+fi
+
+cat << __PREAMBLE_EOF
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper, ATF bl31, U-Boot DTB";
+ #address-cells = <1>;
+
+__PREAMBLE_EOF
+
+cat << __IMAGES_EOF
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ data = /incbin/("$BL33");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0020>;
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("$BL31");
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x1000>;
+ entry = <0x1000>;
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat device-tree";
+ data = /incbin/("$DT_NAME");
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+__IMAGES_EOF
+
+cat << __CONFIGS_EOF
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+__CONFIGS_EOF
+
+cat << __END_EOF
+};
+__END_EOF
--
2.19.0
[PATCH v1 03/16] arm: socfpga: Add function for checking description from FIT image
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/board.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 340abf9305..7993c27646 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -13,7 +13,7 @@
#include
#include
#include
-
+#include
#include
#include
@@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.19.0
[PATCH v1 01/16] arm: socfpga: soc64: Remove CONFIG_OF_EMBED
CONFIG_OF_EMBED was primarily enabled to support the S10/Agilex spl hex file requirements. Since this option now produces a warning during build, and the spl hex can be created using alternate methods, CONFIG_OF_EMBED is no longer needed. Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_defconfig| 1 - configs/socfpga_stratix10_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index f45cdd18b3..feaab00249 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 20ffca89ad..e7c7550112 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -37,7 +37,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y -- 2.19.0
[PATCH v1 00/16] Enable ARM Trusted Firmware for U-Boot
Repost of the following patchs:
https://lists.denx.de/pipermail/u-boot/2020-March/402705.html
New U-boot flow with ARM Trusted Firmware (ATF) support:
SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
SPL loads the u-boot.itb which consist of:
1) u-boot-nodtb.bin (U-Boot Proper image)
2) u-boot.dtb (U-Boot Proper DTB)
3) bl31.bin (ATF-BL31 image)
Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
Now, U-Boot Proper is running in non-secure mode (EL2), it invokes
SMC/PSCI calls provided by ATF to perform COLD reset, System Manager
register accesses and mailbox communications with Secure Device Manager
(SDM).
Steps to build the U-Boot with ATF support:
1) Build U-Boot
2) Build ATF BL31
3) Copy ATF BL31 binary image into U-Boot's root folder
4) "make u-boot.itb" to generate u-boot.itb
These patchsets have dependency on:
arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
Rename Stratix10 FPGA driver and support Agilex
https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
SoCFPGA mailbox driver fixes and enhancements
https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
arm: socfpga: soc64: Initialize timer in SPL only
https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
arm: socfpga: soc64: Remove PHY interface setup from misc arch init
https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
Enable sysreset support for SoCFPGA SoC64 platforms
https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
Chee Hong Ang (16):
arm: socfpga: soc64: Remove CONFIG_OF_EMBED
arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
arm: socfpga: Add function for checking description from FIT image
arm: socfpga: soc64: Load FIT image with ATF support
arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
arm: socfpga: Disable "spin-table" method for booting Linux
arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
(64bits)
arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
services
mmc: dwmmc: socfpga: Add ATF support for MMC driver
net: designware: socfpga: Add ATF support for MAC driver
arm: socfpga: soc64: Add ATF support for Reset Manager driver
arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
mbox_reset_cold()
arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
arm: socfpga: soc64: Skip handoff data access in SSBL
configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
support
arch/arm/mach-socfpga/Kconfig | 2 -
arch/arm/mach-socfpga/Makefile| 4 +
arch/arm/mach-socfpga/board.c | 12 +-
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
arch/arm/mach-socfpga/reset_manager_s10.c | 10 +
arch/arm/mach-socfpga/smc_api.c | 56 ++
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
board/altera/soc64/fit_spl_atf.sh | 91 +++
...defconfig => socfpga_agilex_atf_defconfig} | 25 +-
configs/socfpga_agilex_defconfig | 1 -
...config => socfpga_stratix10_atf_defconfig} | 25 +-
configs/socfpga_stratix10_defconfig | 1 -
drivers/fpga/intel_sdm_mb.c | 139 +
drivers/mmc/socfpga_dw_mmc.c | 20 +
drivers/net/dwmac_socfpga.c | 43 +-
include/configs/socfpga_soc64_common.h| 9 +
include/linux/intel-smc.h | 573 ++
19 files changed, 1078 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S
create mode 100644 arch/arm/mach-socfpga/smc_api.c
create mode 100755 board/altera/soc64/fit_spl_atf.sh
copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig} (77%)
copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_atf_defconfig}
(80%)
create mode 100644 include/linux/intel-smc.h
--
2.19.0
[PATCH v1] arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
Don't invoke 'SYSTEM_RESET' PSCI function because PSCI function calls are not supported by u-boot running in EL3. Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_defconfig| 1 + configs/socfpga_stratix10_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index a08f66e248..feaab00249 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +# CONFIG_PSCI_RESET is not set CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 04e354f59e..e7c7550112 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" CONFIG_OPTIMIZE_INLINING=y CONFIG_SPL_OPTIMIZE_INLINING=y +# CONFIG_PSCI_RESET is not set CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" -- 2.19.0
[PATCH v1 5/5] arm: socfpga: mailbox: Add mailbox retry support
From: Ley Foon Tan
Resend mailbox command for 3 times with 2ms interval in between if
it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code.
Add a wrapper function mbox_send_cmd_common_retry() for retry, change
all the callers to use this wrapper function.
Signed-off-by: Ley Foon Tan
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 40 ++---
1 file changed, 31 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index a9ec818492..18d44924e6 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -296,11 +296,33 @@ static __always_inline int mbox_send_cmd_common(u8 id,
u32 cmd, u8 is_indirect,
return resp_err;
}
}
- };
+ }
return -EIO;
}
+static __always_inline int mbox_send_cmd_common_retry(u8 id, u32 cmd,
+ u8 is_indirect,
+ u32 len, u32 *arg,
+ u8 urgent,
+ u32 *resp_buf_len,
+ u32 *resp_buf)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ ret = mbox_send_cmd_common(id, cmd, is_indirect, len, arg,
+ urgent, resp_buf_len, resp_buf);
+ if (ret == MBOX_RESP_TIMEOUT || ret == MBOX_RESP_DEVICE_BUSY)
+ udelay(2000); /* wait for 2ms before resend */
+ else
+ break;
+ }
+
+ return ret;
+}
+
int mbox_init(void)
{
int ret;
@@ -395,10 +417,10 @@ static __always_inline int
mbox_get_fpga_config_status_common(u32 cmd)
int ret;
reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
- ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
- MBOX_CMD_DIRECT, 0, NULL, 0,
- _status_resp_len,
- reconfig_status_resp);
+ ret = mbox_send_cmd_common_retry(MBOX_ID_UBOOT, cmd,
+MBOX_CMD_DIRECT, 0, NULL, 0,
+_status_resp_len,
+reconfig_status_resp);
if (ret)
return ret;
@@ -438,16 +460,16 @@ int __secure mbox_get_fpga_config_status_psci(u32 cmd)
int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
{
- return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
- resp_buf_len, resp_buf);
+ return mbox_send_cmd_common_retry(id, cmd, is_indirect, len, arg,
+ urgent, resp_buf_len, resp_buf);
}
int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
u32 *arg, u8 urgent, u32 *resp_buf_len,
u32 *resp_buf)
{
- return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
- resp_buf_len, resp_buf);
+ return mbox_send_cmd_common_retry(id, cmd, is_indirect, len, arg,
+ urgent, resp_buf_len, resp_buf);
}
int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
--
2.19.0
[PATCH v1 1/5] arm: socfpga: mailbox: Refactor mailbox timeout event handling
Add miliseconds delay when waiting for mailbox event to happen
before timeout. This will ensure the timeout duration is predictive.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index f30e7f80a2..729d9b04fa 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -29,13 +29,14 @@ DECLARE_GLOBAL_DATA_PTR;
static __always_inline int mbox_polling_resp(u32 rout)
{
u32 rin;
- unsigned long i = ~0;
+ unsigned long i = 2000;
while (i) {
rin = MBOX_READL(MBOX_RIN);
if (rout != rin)
return 0;
+ udelay(1000);
i--;
}
@@ -176,11 +177,15 @@ static __always_inline int mbox_send_cmd_common(u8 id,
u32 cmd, u8 is_indirect,
MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
while (1) {
- ret = ~0;
+ ret = 1000;
/* Wait for doorbell from SDM */
- while (!MBOX_READL(MBOX_DOORBELL_FROM_SDM) && ret--)
- ;
+ do {
+ if (MBOX_READL(MBOX_DOORBELL_FROM_SDM))
+ break;
+ udelay(1000);
+ } while (--ret);
+
if (!ret)
return -ETIMEDOUT;
--
2.19.0
[PATCH v1 4/5] arm: socfpga: mailbox: Update mailbox response codes
From: Ley Foon Tan
Sync latest mailbox response codes from SDM firmware.
Signed-off-by: Ley Foon Tan
Signed-off-by: Chee Hong Ang
---
.../mach-socfpga/include/mach/mailbox_s10.h | 38 ++-
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index 55707ab9c5..4d783119ea 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -67,8 +67,42 @@ enum ALT_SDM_MBOX_RESP_CODE {
MBOX_RESP_UNKNOWN_BR = 2,
/* CMD code not recognized by firmware */
MBOX_RESP_UNKNOWN = 3,
- /* Indicates that the device is not configured */
- MBOX_RESP_NOT_CONFIGURED = 256,
+ /* Length setting is not a valid length for this CMD type */
+ MBOX_RESP_INVALID_LEN = 4,
+ /* Indirect setting is not valid for this CMD type */
+ MBOX_RESP_INVALID_INDIRECT_SETTING = 5,
+ /* HW source which is not allowed to send CMD type */
+ MBOX_RESP_CMD_INVALID_ON_SRC = 6,
+ /* Client with ID not associated with any running PR CMD tries to run
+* RECONFIG_DATA RECONFIG_STATUS and accessing QSPI / SDMMC using ID
+* without exclusive access
+*/
+ MBOX_RESP_CLIENT_ID_NO_MATCH = 8,
+ /* Address provided to the system is invalid (alignment, range
+* permission)
+*/
+ MBOX_RESP_INVALID_ADDR = 0x9,
+ /* Signature authentication failed */
+ MBOX_RESP_AUTH_FAIL = 0xA,
+ /* CMD timed out */
+ MBOX_RESP_TIMEOUT = 0xB,
+ /* HW (i.e. QSPI) is not ready (initialized or configured) */
+ MBOX_RESP_HW_NOT_RDY = 0xC,
+ /* Invalid license for IID registration */
+ MBOX_RESP_PUF_ACCCES_FAILED = 0x80,
+ MBOX_PUF_ENROLL_DISABLE = 0x81,
+ MBOX_RESP_PUF_ENROLL_FAIL = 0x82,
+ MBOX_RESP_PUF_RAM_TEST_FAIL = 0x83,
+ MBOX_RESP_ATTEST_CERT_GEN_FAIL = 0x84,
+ /* Operation not allowed under current security settings */
+ MBOX_RESP_NOT_ALLOWED_UNDER_SECURITY_SETTINGS = 0x85,
+ MBOX_RESP_PUF_TRNG_FAIL = 0x86,
+ MBOX_RESP_FUSE_ALREADY_BLOWN = 0x87,
+ MBOX_RESP_INVALID_SIGNATURE = 0x88,
+ MBOX_RESP_INVALID_HASH = 0x8b,
+ MBOX_RESP_INVALID_CERTIFICATE = 0x91,
+ /* Indicates that the device (FPGA or HPS) is not configured */
+ MBOX_RESP_NOT_CONFIGURED = 0x100,
/* Indicates that the device is busy */
MBOX_RESP_DEVICE_BUSY = 0x1FF,
/* Indicates that there is no valid response available */
--
2.19.0
[PATCH v1 0/5] SoCFPGA mailbox driver fixes and enhancements
Fixes: - Proper timeout implementation - Always read mailbox response data before returning mailbox status to caller Enhancement: - Auto retry on mailbox sending - Send large mailbox message Chee Hong Ang (3): arm: socfpga: mailbox: Refactor mailbox timeout event handling arm: socfpga: mailbox: Always read mailbox responses before returning status arm: socfpga: mailbox: Support sending large mailbox command Ley Foon Tan (2): arm: socfpga: mailbox: Update mailbox response codes arm: socfpga: mailbox: Add mailbox retry support .../mach-socfpga/include/mach/mailbox_s10.h | 38 +++- arch/arm/mach-socfpga/mailbox_s10.c | 172 -- 2 files changed, 156 insertions(+), 54 deletions(-) -- 2.19.0
[PATCH v1 3/5] arm: socfpga: mailbox: Support sending large mailbox command
Mailbox command which is too large to fit into the mailbox
FIFO command buffer can be sent to SDM in multiple parts.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 113 +++-
1 file changed, 78 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index e8a587f007..a9ec818492 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -43,41 +43,93 @@ static __always_inline int mbox_polling_resp(u32 rout)
return -ETIMEDOUT;
}
+static __always_inline int mbox_is_cmdbuf_full(u32 cin)
+{
+ return (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == MBOX_READL(MBOX_COUT));
+}
+
+static __always_inline int mbox_is_cmdbuf_empty(u32 cin)
+{
+ return (((MBOX_READL(MBOX_COUT) + 1) % MBOX_CMD_BUFFER_SIZE) == cin);
+}
+
+static __always_inline int mbox_wait_for_cmdbuf_empty(u32 cin)
+{
+ int timeout = 2000;
+
+ while (timeout) {
+ if (mbox_is_cmdbuf_empty(cin))
+ return 0;
+ udelay(1000);
+ timeout--;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static __always_inline int mbox_write_cmd_buffer(u32 *cin, u32 data,
+int *is_cmdbuf_overflow)
+{
+ int timeout = 1000;
+
+ while (timeout) {
+ if (mbox_is_cmdbuf_full(*cin)) {
+ if (is_cmdbuf_overflow &&
+ *is_cmdbuf_overflow == 0) {
+ /* Trigger SDM doorbell */
+ MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
+ *is_cmdbuf_overflow = 1;
+ }
+ udelay(1000);
+ } else {
+ /* write header to circular buffer */
+ MBOX_WRITE_CMD_BUF(data, (*cin)++);
+ *cin %= MBOX_CMD_BUFFER_SIZE;
+ MBOX_WRITEL(*cin, MBOX_CIN);
+ break;
+ }
+ timeout--;
+ }
+
+ if (!timeout)
+ return -ETIMEDOUT;
+
+ /* Wait for the SDM to drain the FIFO command buffer */
+ if (is_cmdbuf_overflow && *is_cmdbuf_overflow)
+ return mbox_wait_for_cmdbuf_empty(*cin);
+
+ return 0;
+}
+
/* Check for available slot and write to circular buffer.
* It also update command valid offset (cin) register.
*/
static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
u32 *arg)
{
- u32 cin;
- u32 cout;
- u32 i;
-
- cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
- cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
+ int i, ret;
+ int is_cmdbuf_overflow = 0;
+ u32 cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
- /* if command buffer is full or not enough free space
-* to fit the data. Note, len is in u32 unit.
-*/
- if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
- ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
-MBOX_CMD_BUFFER_SIZE) < (len + 1))
- return -ENOMEM;
-
- /* write header to circular buffer */
- MBOX_WRITE_CMD_BUF(header, cin++);
- /* wrapping around when it reach the buffer size */
- cin %= MBOX_CMD_BUFFER_SIZE;
+ ret = mbox_write_cmd_buffer(, header, _cmdbuf_overflow);
+ if (ret)
+ return ret;
/* write arguments */
for (i = 0; i < len; i++) {
- MBOX_WRITE_CMD_BUF(arg[i], cin++);
- /* wrapping around when it reach the buffer size */
- cin %= MBOX_CMD_BUFFER_SIZE;
+ is_cmdbuf_overflow = 0;
+ ret = mbox_write_cmd_buffer(, arg[i], _cmdbuf_overflow);
+ if (ret)
+ return ret;
}
- /* write command valid offset */
- MBOX_WRITEL(cin, MBOX_CIN);
+ /* If SDM doorbell is not triggered after the last data is
+* written into mailbox FIFO command buffer, trigger the
+* SDM doorbell again to ensure SDM able to read the remaining
+* data.
+*/
+ if (!is_cmdbuf_overflow)
+ MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
return 0;
}
@@ -90,10 +142,6 @@ static __always_inline int mbox_prepare_cmd_only(u8 id, u32
cmd,
u32 header;
int ret;
- /* Total length is command + argument length */
- if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
- return -EINVAL;
-
if (cmd > MBOX_MAX_CMD_INDEX)
return -EINVAL;
@@ -110,11 +158,7 @@ static __always_inline int mbox_send_cmd_only_common(u8
id, u32 cmd,
u8 is_indirect, u32 len,
[PATCH v1 2/5] arm: socfpga: mailbox: Always read mailbox responses before returning status
Mailbox driver should always check for the length of the response
and read the response data before returning the response status to
caller.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 729d9b04fa..e8a587f007 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -221,9 +221,7 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32
cmd, u8 is_indirect,
if ((MBOX_RESP_CLIENT_GET(resp) ==
MBOX_CLIENT_ID_UBOOT) &&
(MBOX_RESP_ID_GET(resp) == id)) {
- ret = MBOX_RESP_ERR_GET(resp);
- if (ret)
- return ret;
+ int resp_err = MBOX_RESP_ERR_GET(resp);
if (resp_buf_len) {
buf_len = *resp_buf_len;
@@ -252,7 +250,7 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32
cmd, u8 is_indirect,
buf_len--;
}
}
- return ret;
+ return resp_err;
}
}
};
--
2.19.0
[PATCH v3 1/1] Makefile: socfpga: Generate sfp file with 4 SPL images
Generate 'u-boot-splx4.sfp' which consist of 4 SPL images required for booting up Cyclone5/Arria10. By default, this 'u-boot-splx4.sfp' is generated without extra padding after each SPL image. For Cyclone5, 'u-boot-splx4.sfp' contains: 4 x SPL(64KB) = 256KB For Arria10, 'u-boot-splx4.sfp' contains: 4 x SPL(256KB) = 1024KB For Cyclone5 using NAND flash image layout for 128 KB memory blocks, user can 'make' the following target to generate 4 SPL images with padding: make u-boot-spl-padx4.sfp 'u-boot-spl-padx4.sfp' contains four 128KB SPL images (each 64KB SPL is followed by 64KB of zero-padding). 4 x (SPL(64KB) + zero-padding(64KB)) = 512KB Signed-off-by: Chee Hong Ang --- v3 changes: - add 'u-boot-splx4.sfp' make target (4 x SPL image without paddings) - add 'u-boot-spl-padx4.sfp' make target (4 x SPL image with 64KB paddings) - Update commit message (refer to commit message for details explanation) Makefile | 27 ++- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index 4483a9bc8a..20357adebb 100644 --- a/Makefile +++ b/Makefile @@ -1580,21 +1580,30 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE $(call if_changed,pad_cat) ifneq ($(CONFIG_ARCH_SOCFPGA),) +quiet_cmd_gensplx4 = GENSPLX4 $@ +cmd_gensplx4 = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ + spl/u-boot-spl.sfp spl/u-boot-spl.sfp > $@ || rm -f $@ +u-boot-splx4.sfp: spl/u-boot-spl.sfp FORCE + $(call if_changed,gensplx4) + quiet_cmd_socboot = SOCBOOT $@ -cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ - u-boot.img > $@ || rm -f $@ -u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE +cmd_socboot = cat u-boot-splx4.sfp u-boot.img > $@ || rm -f $@ +u-boot-with-spl.sfp: u-boot-splx4.sfp u-boot.img FORCE $(call if_changed,socboot) -quiet_cmd_socnandboot = SOCNANDBOOT $@ -cmd_socnandboot = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \ +quiet_cmd_gensplpadx4 = GENSPLPADX4 $@ +cmd_gensplpadx4 = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \ cat spl/u-boot-spl.sfp spl/u-boot-spl.pad \ spl/u-boot-spl.sfp spl/u-boot-spl.pad \ spl/u-boot-spl.sfp spl/u-boot-spl.pad \ - spl/u-boot-spl.sfp spl/u-boot-spl.pad \ - u-boot.img > $@ || rm -f $@ spl/u-boot-spl.pad -u-boot-with-nand-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE + spl/u-boot-spl.sfp spl/u-boot-spl.pad > $@ || \ + rm -f $@ spl/u-boot-spl.pad +u-boot-spl-padx4.sfp: spl/u-boot-spl.sfp FORCE + $(call if_changed,gensplpadx4) + +quiet_cmd_socnandboot = SOCNANDBOOT $@ +cmd_socnandboot = cat u-boot-spl-padx4.sfp u-boot.img > $@ || rm -f $@ +u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE $(call if_changed,socnandboot) endif -- 2.19.0
[PATCH v2] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required for booting up Cyclone5/Arria10. For Cyclone5 using NAND flash image layout for 128 KB memory blocks, 'make u-boot-with-nand-spl.sfp' to generate spl/u-boot-nand-splx4.sfp which contains four 128KB SPL images (each 64KB SPL is followed by 64KB of zero-padding). Signed-off-by: Chee Hong Ang --- Makefile | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 4483a9b..f4631f1 100644 --- a/Makefile +++ b/Makefile @@ -1582,8 +1582,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT $@ cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ - u-boot.img > $@ || rm -f $@ + spl/u-boot-spl.sfp \ + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \ + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@ u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socboot) @@ -1592,8 +1593,10 @@ cmd_socnandboot = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \ cat spl/u-boot-spl.sfp spl/u-boot-spl.pad \ spl/u-boot-spl.sfp spl/u-boot-spl.pad \ spl/u-boot-spl.sfp spl/u-boot-spl.pad \ - spl/u-boot-spl.sfp spl/u-boot-spl.pad \ - u-boot.img > $@ || rm -f $@ spl/u-boot-spl.pad + spl/u-boot-spl.sfp \ + spl/u-boot-spl.pad > spl/u-boot-nand-splx4.sfp ; \ + cat spl/u-boot-nand-splx4.sfp u-boot.img > $@ || \ + rm -f $@ spl/u-boot-spl.pad u-boot-with-nand-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socnandboot) -- 2.2.0
[PATCH v1] arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
Add timeout waiting for NOC idle ACK during FPGA bridge
disable/enable.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/reset_manager_s10.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index c743077..e5eb7f4 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,6 +55,8 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+ u32 reg;
+
if (enable) {
/* clear idle request to all bridges */
setbits_le32(socfpga_get_sysmgr_addr() +
@@ -64,9 +67,9 @@ void socfpga_bridges_reset(int enable)
~0);
/* Poll until all idleack to 0 */
- while (readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_NOC_IDLEACK))
- ;
+ read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
+ 30);
} else {
/* set idle request to all bridges */
writel(~0,
@@ -77,14 +80,18 @@ void socfpga_bridges_reset(int enable)
writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
- while ((readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEACK) ^
- (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
- ;
+ read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK, reg,
+ reg == (SYSMGR_NOC_H2F_MSK |
+ SYSMGR_NOC_LWH2F_MSK),
+ 1000, 30);
/* Poll until all idlestatus to 1 */
- while ((readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLESTATUS) ^
- (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
- ;
+ read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLESTATUS, reg,
+ reg == (SYSMGR_NOC_H2F_MSK |
+ SYSMGR_NOC_LWH2F_MSK),
+ 1000, 30);
/* Reset all bridges (except NOR DDR scheduler & F2S) */
setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
--
2.2.0
[PATCH v1 3/3] arm: socfpga: agilex: Enable FPGA Full Reconfiguration support
Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Kconfig | 1 + drivers/fpga/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 32549913cc..26f2cf8e47 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -35,6 +35,7 @@ config TARGET_SOCFPGA_AGILEX select ARMV8_SET_SMPEN select ARMV8_SPIN_TABLE select CLK + select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_CLK if SPL diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index dd0b39a8d1..425b52a926 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -33,7 +33,7 @@ config FPGA_CYCLON2 config FPGA_INTEL_SDM_MAILBOX bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" - depends on TARGET_SOCFPGA_STRATIX10 + depends on TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select FPGA_ALTERA help Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver -- 2.13.0
[PATCH v1 0/3] Rename Stratix10 FPGA driver and support Agilex
- Rename Stratix10 FPGA driver to 'Intel FPGA SDM Mailbox'.
- Add watchdog reset when configuring the FPGA.
- Enable 'Intel FPGA SDM Mailbox' for Agilex.
Chee Hong Ang (3):
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
fpga: intel_sdm_mb: Add watchdog reset
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support
arch/arm/mach-socfpga/Kconfig| 3 ++-
arch/arm/mach-socfpga/misc_s10.c | 2 +-
drivers/fpga/Kconfig | 14 +++---
drivers/fpga/Makefile| 2 +-
drivers/fpga/altera.c| 7 ---
drivers/fpga/{stratix10.c => intel_sdm_mb.c} | 5 -
include/altera.h | 9 +
7 files changed, 24 insertions(+), 18 deletions(-)
rename drivers/fpga/{stratix10.c => intel_sdm_mb.c} (97%)
--
2.13.0
[PATCH v1 2/3] fpga: intel_sdm_mb: Add watchdog reset
Ensure watchdog reset is not triggered if the fpga
reconfiguration is taking too long.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 3508231191..9a1dc2c0c8 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
@@ -113,6 +114,7 @@ static int reconfig_status_polling_resp(void)
puts(".");
udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ WATCHDOG_RESET();
}
return -ETIMEDOUT;
@@ -238,6 +240,7 @@ static int send_reconfig_data(const void *rbf_data, size_t
rbf_size,
if (resp_err && !xfer_count)
return resp_err;
}
+ WATCHDOG_RESET();
}
return 0;
--
2.13.0
[PATCH v1 1/3] fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver
because it is using generic SDM (Secure Device Manager) Mailbox
interface shared by other platform (e.g. Agilex) as well.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig| 2 +-
arch/arm/mach-socfpga/misc_s10.c | 2 +-
drivers/fpga/Kconfig | 12 ++--
drivers/fpga/Makefile| 2 +-
drivers/fpga/altera.c| 7 ---
drivers/fpga/{stratix10.c => intel_sdm_mb.c} | 2 +-
include/altera.h | 9 +
7 files changed, 19 insertions(+), 17 deletions(-)
rename drivers/fpga/{stratix10.c => intel_sdm_mb.c} (98%)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a3699e82a1..32549913cc 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -79,7 +79,7 @@ config TARGET_SOCFPGA_STRATIX10
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
select ARMV8_SPIN_TABLE
- select FPGA_STRATIX10
+ select FPGA_INTEL_SDM_MAILBOX
choice
prompt "Altera SOCFPGA board select"
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 670bfa1a31..1d658f5c60 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
static Altera_desc altera_fpga[] = {
{
/* Family */
- Intel_FPGA_Stratix10,
+ Intel_FPGA_SDM_Mailbox,
/* Interface type */
secure_device_manager_mailbox,
/* No limitation as additional data will be ignored */
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index fe398a1d49..dd0b39a8d1 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -31,16 +31,16 @@ config FPGA_CYCLON2
Enable FPGA driver for loading bitstream in BIT and BIN format
on Altera Cyclone II device.
-config FPGA_STRATIX10
- bool "Enable Altera FPGA driver for Stratix 10"
+config FPGA_INTEL_SDM_MAILBOX
+ bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
depends on TARGET_SOCFPGA_STRATIX10
select FPGA_ALTERA
help
- Say Y here to enable the Altera Stratix 10 FPGA specific driver
+ Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
- This provides common functionality for Altera Stratix 10 devices.
- Enable FPGA driver for writing bitstream into Altera Stratix10
- device.
+ This provides common functionality for Intel FPGA devices.
+ Enable FPGA driver for writing full bitstream into Intel FPGA
+ devices through SDM (Secure Device Manager) Mailbox.
config FPGA_XILINX
bool "Enable Xilinx FPGA drivers"
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 04e6480f20..83243fb107 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -16,9 +16,9 @@ ifdef CONFIG_FPGA_ALTERA
obj-y += altera.o
obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
+obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
-obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o
obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index bb27b3778f..10c0475d25 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -40,12 +40,13 @@ static const struct altera_fpga {
#if defined(CONFIG_FPGA_STRATIX_V)
{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
#endif
-#if defined(CONFIG_FPGA_STRATIX10)
- { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
-#endif
#if defined(CONFIG_FPGA_SOCFPGA)
{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
#endif
+#if defined(CONFIG_FPGA_INTEL_SDM_MAILBOX)
+ { Intel_FPGA_SDM_Mailbox, "Intel SDM Mailbox", intel_sdm_mb_load, NULL,
+ NULL },
+#endif
};
static int altera_validate(Altera_desc *desc, const char *fn)
diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/intel_sdm_mb.c
similarity index 98%
rename from drivers/fpga/stratix10.c
rename to drivers/fpga/intel_sdm_mb.c
index da8fa315e3..3508231191 100644
--- a/drivers/fpga/stratix10.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -247,7 +247,7 @@ static int send_reconfig_data(const void *rbf_data, size_t
rbf_size,
* This is the interface used by FPGA driver.
* Return 0 for success, non-zero for error.
*/
-int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
[PATCH v2] arm: socfpga: Use DM watchdog timer
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.
Signed-off-by: Chee Hong Ang
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi| 4
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 4
arch/arm/dts/socfpga_stratix10.dtsi | 1 -
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 1 +
arch/arm/mach-socfpga/spl_agilex.c | 2 +-
arch/arm/mach-socfpga/spl_s10.c | 2 +-
configs/socfpga_agilex_defconfig | 2 ++
7 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
index debeb8b..6cac36a 100644
--- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
@@ -40,3 +40,7 @@
{
status = "okay";
};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
index 58cd497..22e614d 100644
--- a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
@@ -15,3 +15,7 @@
{
u-boot,dm-pre-reloc;
};
+
+ {
+u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
b/arch/arm/dts/socfpga_stratix10.dtsi
index a8e61cf..cb799bc 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -386,7 +386,6 @@
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = < WATCHDOG0_RESET>;
- u-boot,dm-pre-reloc;
status = "disabled";
};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index a903040..2669abb 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -33,5 +33,6 @@
};
{
+ status = "okay";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_agilex.c
index bd971ec..6896c07 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -51,11 +51,11 @@ void board_init_f(ulong dummy)
socfpga_get_managers_addr();
-#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+#ifdef CONFIG_HW_WATCHDOG
/* Enable watchdog before initializing the HW */
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index b3c6f6a..ad15ed1 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -53,11 +53,11 @@ void board_init_f(ulong dummy)
socfpga_get_managers_addr();
-#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+#ifdef CONFIG_HW_WATCHDOG
/* Enable watchdog before initializing the HW */
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 2885c60..41bd925 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -60,4 +60,6 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
--
2.2.0
[PATCH v2] arm: socfpga: soc64: Check FPGA Config status register before bridge reset
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/misc.h | 5 +
.../mach-socfpga/include/mach/system_manager_soc64.h | 6 +-
arch/arm/mach-socfpga/misc_s10.c | 18 ++
3 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index a85c5ae..649d2f6 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -39,6 +39,11 @@ void socfpga_init_security_policies(void);
void socfpga_sdram_remap_zero(void);
#endif
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+ defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+int is_fpga_config_ready(void);
+#endif
+
void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index c90f63a..5e3f54a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -88,8 +88,12 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned
int *table_len);
#define SYSMGR_ECC_OCRAM_ENBIT(0)
#define SYSMGR_ECC_OCRAM_SERR BIT(3)
#define SYSMGR_ECC_OCRAM_DERR BIT(4)
-#define SYSMGR_FPGAINTF_USEFPGA0x1
+#define SYSMGR_FPGACONFIG_FPGA_COMPLETEBIT(0)
+#define SYSMGR_FPGACONFIG_EARLY_USERMODE BIT(1)
+#define SYSMGR_FPGACONFIG_READY_MASK (SYSMGR_FPGACONFIG_FPGA_COMPLETE | \
+SYSMGR_FPGACONFIG_EARLY_USERMODE)
+#define SYSMGR_FPGAINTF_USEFPGA0x1
#define SYSMGR_FPGAINTF_NAND BIT(4)
#define SYSMGR_FPGAINTF_SDMMC BIT(8)
#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 670bfa1..52868fb 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -151,17 +151,19 @@ int arch_early_init_r(void)
return 0;
}
+/* Return 1 if FPGA is ready otherwise return 0 */
+int is_fpga_config_ready(void)
+{
+ return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
+ SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
+}
+
void do_bridge_reset(int enable, unsigned int mask)
{
/* Check FPGA status before bridge enable */
- if (enable) {
- int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
-
- if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
- ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
-
- if (ret)
- return;
+ if (!is_fpga_config_ready()) {
+ puts("FPGA not ready. Bridge reset aborted!\n");
+ return;
}
socfpga_bridges_reset(enable);
--
2.2.0
[PATCH v1] arm: socfpga: Use DM watchdog timer
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.
Signed-off-by: Chee Hong Ang
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 4
arch/arm/dts/socfpga_stratix10.dtsi| 1 -
arch/arm/dts/socfpga_stratix10_socdk.dts | 4
arch/arm/mach-socfpga/spl_agilex.c | 2 +-
arch/arm/mach-socfpga/spl_s10.c| 2 +-
configs/socfpga_agilex_defconfig | 2 ++
7 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
index debeb8b..6cac36a 100644
--- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
@@ -40,3 +40,7 @@
{
status = "okay";
};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
index 58cd497..22e614d 100644
--- a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
@@ -15,3 +15,7 @@
{
u-boot,dm-pre-reloc;
};
+
+ {
+u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
b/arch/arm/dts/socfpga_stratix10.dtsi
index a8e61cf..cb799bc 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -386,7 +386,6 @@
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = < WATCHDOG0_RESET>;
- u-boot,dm-pre-reloc;
status = "disabled";
};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
b/arch/arm/dts/socfpga_stratix10_socdk.dts
index b7b48a5..fceae93 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -137,3 +137,7 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_agilex.c
index bd971ec..6896c07 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -51,11 +51,11 @@ void board_init_f(ulong dummy)
socfpga_get_managers_addr();
-#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+#ifdef CONFIG_HW_WATCHDOG
/* Enable watchdog before initializing the HW */
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index b3c6f6a..ad15ed1 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -53,11 +53,11 @@ void board_init_f(ulong dummy)
socfpga_get_managers_addr();
-#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+#ifdef CONFIG_HW_WATCHDOG
/* Enable watchdog before initializing the HW */
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 2885c60..41bd925 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -60,4 +60,6 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
--
2.2.0
[PATCH v1 0/2] Print reset information in SPL
Show reset information such as reset types (cold/warm) and which events triggered the reset. Chee Hong Ang (2): arm: socfpga: soc64: Add SDM triggered warm reset bit mask arm: socfpga: soc64: Show reset state in SPL .../include/mach/reset_manager_soc64.h | 12 ++-- arch/arm/mach-socfpga/reset_manager_s10.c | 22 ++ arch/arm/mach-socfpga/spl_agilex.c | 1 + arch/arm/mach-socfpga/spl_s10.c| 1 + 4 files changed, 34 insertions(+), 2 deletions(-) -- 2.2.0
[PATCH v1 1/2] arm: socfpga: soc64: Add SDM triggered warm reset bit mask
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 3f952bc..fc60f6a 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -21,8 +21,15 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X0040 #define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x0004 -/* Watchdogs and MPU warm reset mask */ -#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 +/* SDM, Watchdogs and MPU warm reset mask */ +#define RSTMGR_STAT_SDMWARMRST BIT(1) +#define RSTMGR_STAT_MPU0RST_BITPOS 8 +#define RSTMGR_STAT_L4WD0RST_BITPOS16 +#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ + GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \ + RSTMGR_STAT_MPU0RST_BITPOS) | \ + GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \ + RSTMGR_STAT_L4WD0RST_BITPOS)) /* * SocFPGA Stratix10 reset IDs, bank mapping is as follows: -- 2.2.0
[PATCH v1 2/2] arm: socfpga: soc64: Show reset state in SPL
Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.
Signed-off-by: Chee Hong Ang
---
.../include/mach/reset_manager_soc64.h | 1 +
arch/arm/mach-socfpga/reset_manager_s10.c | 22 ++
arch/arm/mach-socfpga/spl_agilex.c | 1 +
arch/arm/mach-socfpga/spl_s10.c| 1 +
4 files changed, 25 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index fc60f6a..c8bb727 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -8,6 +8,7 @@
void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
+void print_reset_info(void);
void socfpga_bridges_reset(int enable);
#define RSTMGR_SOC64_STATUS0x00
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index c743077..9f16bf9 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -104,3 +104,25 @@ int cpu_has_been_warmreset(void)
return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
RSTMGR_L4WD_MPU_WARMRESET_MASK;
}
+
+void print_reset_info(void)
+{
+ bool iswd;
+ int n;
+ u32 stat = cpu_has_been_warmreset();
+
+ printf("Reset state: %s%s", stat ? "Warm " : "Cold",
+ (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
+
+ stat &= ~RSTMGR_STAT_SDMWARMRST;
+ if (!stat) {
+ puts("\n");
+ return;
+ }
+
+ n = generic_ffs(stat) - 1;
+ iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
+ printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
+ iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
+ (n - RSTMGR_STAT_MPU0RST_BITPOS));
+}
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_agilex.c
index bd971ec..0121ff4 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -76,6 +76,7 @@ void board_init_f(ulong dummy)
}
preloader_console_init();
+ print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index b3c6f6a..1f71182 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -81,6 +81,7 @@ void board_init_f(ulong dummy)
#endif
preloader_console_init();
+ print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();
--
2.2.0
[PATCH v1] arm: socfpga: soc64: Check FPGA Config status register before bridge reset
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/misc.h | 5 +
.../mach-socfpga/include/mach/system_manager_soc64.h | 6 +-
arch/arm/mach-socfpga/misc_s10.c | 18 ++
3 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index a85c5ae..43cc3d4 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -39,6 +39,11 @@ void socfpga_init_security_policies(void);
void socfpga_sdram_remap_zero(void);
#endif
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+ defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+int socfpga_get_fpga_config(void);
+#endif
+
void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index c90f63a..5e3f54a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -88,8 +88,12 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned
int *table_len);
#define SYSMGR_ECC_OCRAM_ENBIT(0)
#define SYSMGR_ECC_OCRAM_SERR BIT(3)
#define SYSMGR_ECC_OCRAM_DERR BIT(4)
-#define SYSMGR_FPGAINTF_USEFPGA0x1
+#define SYSMGR_FPGACONFIG_FPGA_COMPLETEBIT(0)
+#define SYSMGR_FPGACONFIG_EARLY_USERMODE BIT(1)
+#define SYSMGR_FPGACONFIG_READY_MASK (SYSMGR_FPGACONFIG_FPGA_COMPLETE | \
+SYSMGR_FPGACONFIG_EARLY_USERMODE)
+#define SYSMGR_FPGAINTF_USEFPGA0x1
#define SYSMGR_FPGAINTF_NAND BIT(4)
#define SYSMGR_FPGAINTF_SDMMC BIT(8)
#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 670bfa1..c8751db 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -151,17 +151,19 @@ int arch_early_init_r(void)
return 0;
}
+/* Return 0 if FPGA is ready otherwise return non-zero */
+int socfpga_get_fpga_config(void)
+{
+ return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
+ SYSMGR_FPGACONFIG_READY_MASK) != SYSMGR_FPGACONFIG_READY_MASK;
+}
+
void do_bridge_reset(int enable, unsigned int mask)
{
/* Check FPGA status before bridge enable */
- if (enable) {
- int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
-
- if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
- ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
-
- if (ret)
- return;
+ if (socfpga_get_fpga_config()) {
+ puts("FPGA not ready. Bridge reset aborted!\n");
+ return;
}
socfpga_bridges_reset(enable);
--
2.2.0
[PATCH v2 2/2] sysreset: socfpga: agilex: Enable sysreset support
Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang --- arch/arm/Kconfig | 2 +- drivers/sysreset/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 03fc614..617d5ad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -991,7 +991,7 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 + select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index b812af9..70692f0 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -81,7 +81,7 @@ config SYSRESET_SOCFPGA config SYSRESET_SOCFPGA_SOC64 bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" - depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10 + depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX) help This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs. -- 2.2.0
[PATCH v2 0/2] Enable sysreset support for SoCFPGA SoC64 platforms
Rename S10 sysreset driver to common name (SoC64).
SoCFPGA sysreset driver supports S10 and Agilex platforms now.
Chee Hong Ang (2):
sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to
SoC64
sysreset: socfpga: agilex: Enable sysreset support
arch/arm/Kconfig | 2 +-
drivers/sysreset/Kconfig | 8
drivers/sysreset/Makefile | 2 +-
.../sysreset/{sysreset_socfpga_s10.c => sysreset_socfpga_soc64.c} | 0
4 files changed, 6 insertions(+), 6 deletions(-)
rename drivers/sysreset/{sysreset_socfpga_s10.c => sysreset_socfpga_soc64.c}
(100%)
--
2.2.0
[PATCH v2 1/2] sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64
Rename the driver from S10 to SoC64 because Intel Agilex platform
also using the this SYSRESET SoCFPGA driver for S10.
Signed-off-by: Chee Hong Ang
---
arch/arm/Kconfig| 2 +-
drivers/sysreset/Kconfig| 6 +++---
drivers/sysreset/Makefile | 2 +-
.../sysreset/{sysreset_socfpga_s10.c => sysreset_socfpga_soc64.c} | 0
4 files changed, 5 insertions(+), 5 deletions(-)
rename drivers/sysreset/{sysreset_socfpga_s10.c => sysreset_socfpga_soc64.c}
(100%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b8a32c..03fc614 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -991,7 +991,7 @@ config ARCH_SOCFPGA
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
+ select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 6ebc90e..b812af9 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -79,12 +79,12 @@ config SYSRESET_SOCFPGA
This enables the system reset driver support for Intel SOCFPGA SoCs
(Cyclone 5, Arria 5 and Arria 10).
-config SYSRESET_SOCFPGA_S10
- bool "Enable support for Intel SOCFPGA Stratix 10"
+config SYSRESET_SOCFPGA_SOC64
+ bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)"
depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10
help
This enables the system reset driver support for Intel SOCFPGA
- Stratix SoCs.
+ SoC64 SoCs.
config SYSRESET_TI_SCI
bool "TI System Control Interface (TI SCI) system reset driver"
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index df2293b..920c692 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
-obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
+obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
diff --git a/drivers/sysreset/sysreset_socfpga_s10.c
b/drivers/sysreset/sysreset_socfpga_soc64.c
similarity index 100%
rename from drivers/sysreset/sysreset_socfpga_s10.c
rename to drivers/sysreset/sysreset_socfpga_soc64.c
--
2.2.0
[PATCH v1] configs: socfpga: soc64: Avoid SPL enter infinite loop during exception
From: Chin Liang See In current implementation, any exception would trigger a CPU reset. But a bad written SPL would cause infinite loop where the system will reload the same SPL instead of loading factory safe image. Hence this patch is to ensure any exception will cause a hang. At this moment, watchdog shall be triggered and Remote System Update mechanism shall load the next production image or factory safe image. Signed-off-by: Chin Liang See Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_defconfig| 1 + configs/socfpga_stratix10_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 2885c60..acf0316 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -61,3 +61,4 @@ CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y # CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 9ae6ef6..8b4d1fb 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -67,3 +67,4 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y -- 2.2.0
[PATCH v1] spi: cadence_qspi: Probe fail if QSPI clock is not set
If the QSPI clock is not set (read as 0), QSPI driver probe shall fail and prevent further QSPI access. Signed-off-by: Chee Hong Ang --- drivers/spi/cadence_qspi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 1e85749209..3bb5c7031d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -170,6 +170,9 @@ static int cadence_spi_probe(struct udevice *bus) struct clk clk; int ret; + if (!CONFIG_CQSPI_REF_CLK) + return -ENODEV; + priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase; -- 2.19.0
[PATCH v1] sysreset: socfpga: agilex: Enable sysreset support
Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang --- arch/arm/Kconfig | 2 +- drivers/sysreset/Kconfig | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b8a32c38d..105b5f08a9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -991,7 +991,7 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10 + select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 6ebc90e1d3..d886d1c933 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -80,11 +80,11 @@ config SYSRESET_SOCFPGA (Cyclone 5, Arria 5 and Arria 10). config SYSRESET_SOCFPGA_S10 - bool "Enable support for Intel SOCFPGA Stratix 10" - depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10 + bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" + depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX) help This enables the system reset driver support for Intel SOCFPGA - Stratix SoCs. + SoC64 SoCs. config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" -- 2.19.0
[PATCH v1] spi: cadence-qspi: Fix QSPI write issues
QSPI driver perform chip select on every flash read/write access. The driver need to disable/enable the QSPI controller while performing chip select. This may cause some data lost especially the QSPI controller is configured to run at slower speed as it may take longer time to access the flash device. This patch prevent the driver from disable/enable the QSPI controller too soon and inadvertently halting any ongoing flash read/write access by ensuring the QSPI controller is always in idle mode after each read/write access. Signed-off-by: Chee Hong Ang --- drivers/spi/cadence_qspi_apb.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index f9675f7..5696eb3 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -648,6 +648,10 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; + return 0; failrd: @@ -763,6 +767,11 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, plat->regbase + CQSPI_REG_INDIRECTWR); if (bounce_buf) free(bounce_buf); + + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; + return 0; failwr: -- 2.2.0
[PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required for booting up Cyclone5/Arria10. Signed-off-by: Chee Hong Ang --- Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 2629a74..13429a0 100644 --- a/Makefile +++ b/Makefile @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT $@ cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ - u-boot.img > $@ || rm -f $@ + spl/u-boot-spl.sfp \ + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \ + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@ u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socboot) -- 2.2.0
[PATCH] arm: socfpga: soc64: Initialize timer in SPL only
Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/timer_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/timer_s10.c
b/arch/arm/mach-socfpga/timer_s10.c
index 3ad98bdb25..7d5598e1a3 100644
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -14,6 +14,7 @@
*/
int timer_init(void)
{
+#ifdef CONFIG_SPL_BUILD
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
@@ -22,6 +23,6 @@ int timer_init(void)
/* enable processor pysical counter */
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
-
+#endif
return 0;
}
--
2.19.0
[PATCH] arm: socfpga: soc64: Remove PHY interface setup from misc arch init
'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c | 84 +---
1 file changed, 1 insertion(+), 83 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 670bfa1a31..77c2b7764e 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -8,20 +8,12 @@
#include
#include
#include
-#include
#include
#include
-#include
-#include
#include
-#include
-#include
#include
-#include
-#include
#include
-
-#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -45,79 +37,6 @@ static Altera_desc altera_fpga[] = {
},
};
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-
-static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
-{
- u32 modereg;
-
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
- !strcmp(phymode, "sgmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- else if (!strcmp(phymode, "rgmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- else if (!strcmp(phymode, "rmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- else
- return -EINVAL;
-
- clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
- (gmac_index * sizeof(u32)),
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
-
- return 0;
-}
-
-static int socfpga_set_phymode(void)
-{
- const void *fdt = gd->fdt_blob;
- struct fdtdec_phandle_args args;
- const char *phy_mode;
- u32 gmac_index;
- int nodes[3]; /* Max. 3 GMACs */
- int ret, count;
- int i, node;
-
- count = fdtdec_find_aliases_for_id(fdt, "ethernet",
- COMPAT_ALTERA_SOCFPGA_DWMAC,
- nodes, ARRAY_SIZE(nodes));
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
-"#reset-cells", 1, 0,
-);
- if (ret || args.args_count != 1) {
- debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
- continue;
- }
-
- gmac_index = args.args[0] - EMAC0_RESET;
-
- phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
- ret = socfpga_phymode_setup(gmac_index, phy_mode);
- if (ret) {
- debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
- continue;
- }
- }
-
- return 0;
-}
-#else
-static int socfpga_set_phymode(void)
-{
- return 0;
-};
-#endif
/*
* Print CPU information
@@ -139,7 +58,6 @@ int arch_misc_init(void)
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
env_set("qspi_clock", qspi_string);
- socfpga_set_phymode();
return 0;
}
#endif
--
2.19.0
[PATCH v1 4/4] clk: agilex: Additional membus writes for HPS PLL
Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.
Signed-off-by: Chee Hong Ang
---
drivers/clk/altera/clk-agilex.c | 94 +++--
1 file changed, 78 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index c83eb2efb9..5b34731a24 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -47,8 +47,66 @@ static void clk_write_ctrl(struct socfpga_clk_platdata
*plat, u32 val)
#define MEMBUS_MAINPLL 0
#define MEMBUS_PERPLL 1
#define MEMBUS_TIMEOUT 1000
-#define MEMBUS_ADDR_CLKSLICE 0x27
-#define MEMBUS_CLKSLICE_SYNC_MODE_EN 0x80
+
+#define MEMBUS_CLKSLICE_REG0x27
+#define MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG0xb3
+#define MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG 0xe6
+#define MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG0x03
+#define MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG0x07
+
+static const struct {
+ u32 reg;
+ u32 val;
+ u32 mask;
+} membus_pll[] = {
+ {
+ MEMBUS_CLKSLICE_REG,
+ /*
+* BIT[7:7]
+* Enable source synchronous mode
+*/
+ BIT(7),
+ BIT(7)
+ },
+ {
+ MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
+ /*
+* BIT[0:0]
+* Sets synthcalfosc_init_centerfreq=1 to limit overshoot
+* frequency during lock
+*/
+ BIT(0),
+ BIT(0)
+ },
+ {
+ MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG,
+ /*
+* BIT[0:0]
+* Sets synthppm_watchdogtmr_vf0=1 to give the pll more time
+* to settle before lock is asserted.
+*/
+ BIT(0),
+ BIT(0)
+ },
+ {
+ MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG,
+ /*
+* BIT[6:0]
+* Centering duty cycle for clkslice0 output
+*/
+ 0x4a,
+ GENMASK(6, 0)
+ },
+ {
+ MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG,
+ /*
+* BIT[6:0]
+* Centering duty cycle for clkslice1 output
+*/
+ 0x4a,
+ GENMASK(6, 0)
+ },
+};
static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
int timeout)
@@ -126,6 +184,20 @@ static int membus_read_pll(struct socfpga_clk_platdata
*plat, u32 pll,
return 0;
}
+static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll)
+{
+ int i;
+ u32 rdata;
+
+ for (i = 0; i < ARRAY_SIZE(membus_pll); i++) {
+ membus_read_pll(plat, pll, membus_pll[i].reg,
+ , MEMBUS_TIMEOUT);
+ membus_write_pll(plat, pll, membus_pll[i].reg,
+((rdata & ~membus_pll[i].mask) | membus_pll[i].val),
+MEMBUS_TIMEOUT);
+ }
+}
+
static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
{
u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;
@@ -166,7 +238,6 @@ static void clk_basic_init(struct udevice *dev,
{
struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
u32 vcocalib;
- u32 rdata;
if (!cfg)
return;
@@ -226,19 +297,10 @@ static void clk_basic_init(struct udevice *dev,
CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
- /* Membus programming to set mainpll and perripll to
-* source synchronous mode
-*/
- membus_read_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, ,
- MEMBUS_TIMEOUT);
- membus_write_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE,
-(rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
-MEMBUS_TIMEOUT);
- membus_read_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, ,
- MEMBUS_TIMEOUT);
- membus_write_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE,
-(rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
-MEMBUS_TIMEOUT);
+ /* Membus programming for mainpll */
+ membus_pll_configs(plat, MEMBUS_MAINPLL);
+ /* Membus programming for peripll */
+ membus_pll_configs(plat, MEMBUS_PERPLL);
cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
--
2.19.0
[PATCH v1 3/4] clk: agilex: Handle clock configuration differently in SPL and U-Boot proper
Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc. Signed-off-by: Chee Hong Ang --- drivers/clk/altera/clk-agilex.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index b5cf187364..c83eb2efb9 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -171,6 +171,16 @@ static void clk_basic_init(struct udevice *dev, if (!cfg) return; +#ifdef CONFIG_SPL_BUILD + /* Always force clock manager into boot mode before any configuration */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); +#else + /* Skip clock configuration in SSBL if it's not in boot mode */ + if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE)) + return; +#endif + /* Put both PLLs in bypass */ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL); clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL); -- 2.19.0
[PATCH v1 0/4] Agilex's clock driver updates and fixes
- Add clock enable. - Add clock source for NAND. - Add additional PLL configurations via mebus writes. - U-Boot proper will not re-initialize the clock again if it's already initialized by SPL. Chee Hong Ang (2): clk: agilex: Handle clock configuration differently in SPL and U-Boot proper clk: agilex: Additional membus writes for HPS PLL Ley Foon Tan (2): clk: agilex: Add NAND clock support clk: agilex: Add clock enable support drivers/clk/altera/clk-agilex.c | 113 +++- 1 file changed, 97 insertions(+), 16 deletions(-) -- 2.19.0
[PATCH v1 1/4] clk: agilex: Add NAND clock support
From: Ley Foon Tan Add get nand_clk and nand_x clock support. Signed-off-by: Ley Foon Tan Signed-off-by: Chee Hong Ang --- drivers/clk/altera/clk-agilex.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 0042958f4c..2ef9292f93 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -533,7 +533,10 @@ static ulong socfpga_clk_get_rate(struct clk *clk) case AGILEX_EMAC2_CLK: return clk_get_emac_clk_hz(plat, clk->id); case AGILEX_USB_CLK: + case AGILEX_NAND_X_CLK: return clk_get_l4_mp_clk_hz(plat); + case AGILEX_NAND_CLK: + return clk_get_l4_mp_clk_hz(plat) / 4; default: return -ENXIO; } -- 2.19.0
[PATCH v1 2/4] clk: agilex: Add clock enable support
From: Ley Foon Tan
Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.
Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.
Signed-off-by: Ley Foon Tan
Signed-off-by: Chee Hong Ang
---
drivers/clk/altera/clk-agilex.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index 2ef9292f93..b5cf187364 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -542,6 +542,11 @@ static ulong socfpga_clk_get_rate(struct clk *clk)
}
}
+static int socfpga_clk_enable(struct clk *clk)
+{
+ return 0;
+}
+
static int socfpga_clk_probe(struct udevice *dev)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -565,6 +570,7 @@ static int socfpga_clk_ofdata_to_platdata(struct udevice
*dev)
}
static struct clk_ops socfpga_clk_ops = {
+ .enable = socfpga_clk_enable,
.get_rate = socfpga_clk_get_rate,
};
--
2.19.0
[PATCH v5 17/17] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
From: "Ang, Chee Hong" Booting Agilex and Stratix 10 with ATF support. SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The new boot flow with ATF support is as follow: SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux) U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE). ATF will occupy the address range starting from 0x1000. Signed-off-by: Ang, Chee Hong --- configs/socfpga_agilex_atf_defconfig| 63 ++ configs/socfpga_stratix10_atf_defconfig | 68 + 2 files changed, 131 insertions(+) create mode 100644 configs/socfpga_agilex_atf_defconfig create mode 100644 configs/socfpga_stratix10_atf_defconfig diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig new file mode 100644 index 000..2373f89 --- /dev/null +++ b/configs/socfpga_agilex_atf_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x20 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its" +CONFIG_BOOTDELAY=5 +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +# CONFIG_SPL_USE_TINY_PRINTF is not set diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig new file mode 100644 index 000..dc34357 --- /dev/null +++ b/configs/socfpga_stratix10_atf_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x20 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its" +CONFIG_BOOTDELAY=5 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C0 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set -- 2.7.4
[PATCH v5 16/17] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index f30e7f8..6b39576 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -330,6 +330,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -338,6 +341,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.7.4
[PATCH v5 15/17] arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/stratix10.c | 141 ++-
1 file changed, 140 insertions(+), 1 deletion(-)
diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c
index d8e3250..d726a1b 100644
--- a/drivers/fpga/stratix10.c
+++ b/drivers/fpga/stratix10.c
@@ -5,11 +5,148 @@
#include
#include
-#include
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#include
+#include
+
+#define BITSTREAM_CHUNK_SIZE 0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ break; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bistream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret == INTEL_SIP_SMC_STATUS_REJECTED)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, 3);
+ if (!ret) {
+ for (i = 0; i < 3; i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(2);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, NULL, 0, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bistream(rbf_data, rbf_size);
+ if (ret) {
+ printf("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ printf("FPGA reconfiguration failed!");
+ return ret;
+ }
+
+ puts("FP
[PATCH v5 11/17] net: designware: socfpga: Add ATF support for MAC driver
From: Chee Hong Ang
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
---
drivers/net/dwmac_socfpga.c | 43 +++
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561d..600b2e6 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -14,8 +14,10 @@
#include
#include
#include "designware.h"
+#include
#include
#include
+#include
#include
@@ -64,6 +66,35 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static int dwmac_socfpga_fw_setphy(struct udevice *dev, u32 modereg)
+{
+ struct ofnode_phandle_args pargs;
+ u64 args[2];
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
+1, 0, );
+ if (ret) {
+ dev_err(dev, "Failed to get syscon: %d\n", ret);
+ return ret;
+ }
+
+ if (pargs.args_count < 1) {
+ dev_err(dev, "No syscon args found\n");
+ return -EINVAL;
+ }
+
+ args[0] = ((u64)pargs.args[0] - SYSMGR_SOC64_EMAC0) >> 2;
+ args[1] = modereg;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0))
+ return -EIO;
+
+ return 0;
+}
+#endif
+
static int dwmac_socfpga_probe(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +102,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct reset_ctl_bulk reset_bulk;
int ret;
u32 modereg;
- u32 modemask;
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -97,9 +127,14 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ ret = dwmac_socfpga_fw_setphy(dev, modereg);
+ if (ret)
+ return ret;
+#else
+ clrsetbits_le32(pdata->phy_intf, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
+ pdata->reg_shift, modereg << pdata->reg_shift);
+#endif
reset_release_bulk(_bulk);
--
2.7.4
[PATCH v5 13/17] arm: socfpga: stratix10: Initialize timer in SPL
From: Chee Hong Ang
Initialize timer in SPL running in secure mode (EL3)
and skip timer initialization in U-Boot proper running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/timer_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/timer_s10.c
b/arch/arm/mach-socfpga/timer_s10.c
index 5723789..0fa56c3 100644
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -13,6 +13,7 @@
*/
int timer_init(void)
{
+#ifdef CONFIG_SPL_BUILD
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
@@ -21,6 +22,6 @@ int timer_init(void)
/* enable processor pysical counter */
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
-
+#endif
return 0;
}
--
2.7.4
[PATCH v5 12/17] arm: socfpga: Add ATF support for Reset Manager driver
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI services provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index c743077..c028e2d 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,10 +5,13 @@
*/
#include
+#include
#include
+#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,6 +57,12 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, , 1, NULL, 0))
+ hang();
+#else
if (enable) {
/* clear idle request to all bridges */
setbits_le32(socfpga_get_sysmgr_addr() +
@@ -94,6 +103,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.7.4
[PATCH v5 14/17] arm: socfpga: Add ATF support to query FPGA configuration status
From: Chee Hong Ang
In EL3, do_bridge_reset() directly send mailbox commands to SDM to
query the FPGA configuration status. If running in non-secure
mode (EL2), it invokes SMC service calls to ATF (EL3) to perform the
query.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index ba11bfa..6b5dd03 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -70,11 +71,24 @@ void do_bridge_reset(int enable, unsigned int mask)
{
/* Check FPGA status before bridge enable */
if (enable) {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 config_status = 1;
+
+ /* Send MBOX_RECONFIG_STATUS to SDM */
+ int ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (ret && ret != INTEL_SIP_SMC_STATUS_BUSY) {
+ /* Send MBOX_CONFIG_STATUS to SDM */
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE,
+_status, 1, NULL, 0);
+ }
+#else
int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
-
+#endif
if (ret)
return;
}
--
2.7.4
[PATCH v5 09/17] arm: socfpga: soc64: Remove PHY interface setup from misc arch init
From: Chee Hong Ang
'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c | 85 +---
1 file changed, 1 insertion(+), 84 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index adfff82..ba11bfa 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -8,18 +8,10 @@
#include
#include
#include
-#include
-#include
-#include
#include
-#include
-#include
#include
-#include
-#include
#include
-
-#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -44,80 +36,6 @@ static Altera_desc altera_fpga[] = {
};
/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-
-static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
-{
- u32 modereg;
-
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
- !strcmp(phymode, "sgmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- else if (!strcmp(phymode, "rgmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- else if (!strcmp(phymode, "rmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- else
- return -EINVAL;
-
- clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
- gmac_index,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
-
- return 0;
-}
-
-static int socfpga_set_phymode(void)
-{
- const void *fdt = gd->fdt_blob;
- struct fdtdec_phandle_args args;
- const char *phy_mode;
- u32 gmac_index;
- int nodes[3]; /* Max. 3 GMACs */
- int ret, count;
- int i, node;
-
- count = fdtdec_find_aliases_for_id(fdt, "ethernet",
- COMPAT_ALTERA_SOCFPGA_DWMAC,
- nodes, ARRAY_SIZE(nodes));
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
-"#reset-cells", 1, 0,
-);
- if (ret || args.args_count != 1) {
- debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
- continue;
- }
-
- gmac_index = args.args[0] - EMAC0_RESET;
-
- phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
- ret = socfpga_phymode_setup(gmac_index, phy_mode);
- if (ret) {
- debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
- continue;
- }
- }
-
- return 0;
-}
-#else
-static int socfpga_set_phymode(void)
-{
- return 0;
-};
-#endif
-
-/*
* Print CPU information
*/
#if defined(CONFIG_DISPLAY_CPUINFO)
@@ -137,7 +55,6 @@ int arch_misc_init(void)
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
env_set("qspi_clock", qspi_string);
- socfpga_set_phymode();
return 0;
}
#endif
--
2.7.4
[PATCH v5 10/17] mmc: dwmmc: socfpga: Add ATF support for MMC driver
From: Chee Hong Ang
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
---
drivers/mmc/socfpga_dw_mmc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 786cdc7..d4d1132 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -5,13 +5,16 @@
#include
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
#include
+#include
#include
#include
#include
@@ -45,6 +48,20 @@ static void socfpga_dwmci_reset(struct udevice *dev)
reset_deassert_bulk(_bulk);
}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static void socfpga_dwmci_fw_clksel(u32 sdmmc_mask)
+{
+ u64 args[2];
+
+ /* drvsel */
+ args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7;
+ /* smplsel */
+ args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7;
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0))
+ hang();
+}
+#endif
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
@@ -57,10 +74,14 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ socfpga_dwmci_fw_clksel(sdmmc_mask);
+#else
writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.7.4
[PATCH v5 08/17] arm: socfpga: Define SMC function identifiers for PSCI SiP services
From: Chee Hong Ang This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang --- include/linux/intel-smc.h | 445 ++ 1 file changed, 445 insertions(+) create mode 100644 include/linux/intel-smc.h diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 000..81b97c0 --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,445 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2020, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include +#include + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of kernel tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * value. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * FPGA configuration completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR: + * There is error during the FPGA configuration process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0x +#define INTEL_SIP_SMC_STATUS_OK0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + *0 full reconfiguration. + *1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any completed + * block, otherwise zero value. + * a2: 64bit physical address of 2nd completed memory block if any completed + * block, other
[PATCH v5 05/17] arm: socfpga: Override 'lowlevel_init' to support ATF
From: Chee Hong Ang Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Makefile | 2 + arch/arm/mach-socfpga/lowlevel_init_64.S | 81 2 files changed, 83 insertions(+) create mode 100644 arch/arm/mach-socfpga/lowlevel_init_64.S diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543..3758c0a 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o diff --git a/arch/arm/mach-socfpga/lowlevel_init_64.S b/arch/arm/mach-socfpga/lowlevel_init_64.S new file mode 100644 index 000..21402c0 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_64.S @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019, Intel Corporation + */ + +#include +#include +#include +#include + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_SPL_ATF + branch_if_slave x0, 2f +#else + branch_if_slave x0, 1f +#endif + + ldr x0, =GICD_BASE + bl gic_init_secure + b 2f + +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + +#ifdef CONFIG_ARMV8_MULTIENTRY + branch_if_master x0, x1, 3f + + /* +* Slave should wait for master clearing spin table. +* This sync prevent slaves observing incorrect +* value of spin table and jumping to wrong place. +*/ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* +* All slaves will enter EL2 and optionally EL1. +*/ + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el2 + +lowlevel_in_el2: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el1 + +lowlevel_in_el1: +#endif +#endif /* CONFIG_ARMV8_MULTIENTRY */ + +2: +#ifdef CONFIG_SPL_BUILD + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, checkslavecpu + br x5 +checkslavecpu: + branch_if_slave x0, 2b +#endif + +3: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) -- 2.7.4
[PATCH v5 07/17] arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
From: Chee Hong Ang
Allow U-Boot proper running in non-secure mode (EL2) to invoke
SMC call to ATF's PSCI runtime services such as System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration,
Remote System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/misc.h | 3 +++
arch/arm/mach-socfpga/misc_s10.c | 20
2 files changed, 23 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index f6de1cc..b5625e1 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -43,4 +43,7 @@ void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+#endif
#endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index a3f5b43..adfff82 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -164,3 +164,23 @@ void do_bridge_reset(int enable, unsigned int mask)
socfpga_bridges_reset(enable);
}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy([1], [0], arg_len * sizeof(u64));
+
+ smc_call();
+
+ if (ret_arg)
+ memcpy(_arg[0], [1], ret_len * sizeof(u64));
+
+ return regs.regs[0];
+}
+#endif
--
2.7.4
[PATCH v5 06/17] arm: socfpga: Disable "spin-table" method for booting Linux
From: Chee Hong Ang Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 38d6c1b..0b858af 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select CLK select NCORE_CACHE select SPL_CLK if SPL @@ -77,7 +76,6 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select FPGA_STRATIX10 choice -- 2.7.4
[PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot
From: "Ang, Chee Hong"
v5 changes:
This is another revision without the System Manager driver to handle the
secure/non-secure
access. DW MAC and MMC drivers will make direct calls to the high-level API to
ATF if
it's running in EL2 on Stratix10/Agilex otherwise these drivers work as it is.
[PATCH v5 08/17] arm: socfpga: Define SMC function identifiers for PSCI SiP
services
- Add documentation for high-level API supported by ATF:
- INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF (For setting PHY interface)
- INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK (For setting SDMMC clock phase)
[PATCH v5 10/17] mmc: dwmmc: socfpga: Add ATF support for MMC driver
- Call 'INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK' if U-Boot running in EL2
(non-secure)
[PATCH v5 11/17] net: designware: socfpga: Add ATF support for MAC driver
- Call 'INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF' if U-Boot running in EL2
(non-secure)
[PATCH v5 17/17] configs: socfpga: Add defconfig for Agilex and Stratix 10 with
ATF support
- Keep the existing Stratix10/Agilex defconfigs and add new defconfigs with ATF
support
v4:
https://lists.denx.de/pipermail/u-boot/2020-March/402289.html
These patchsets have dependency on:
https://lists.denx.de/pipermail/u-boot/2019-September/384906.html
Ang, Chee Hong (1):
configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
support
Chee Hong Ang (16):
configs: agilex: Remove CONFIG_OF_EMBED
arm: socfpga: add fit source file for pack itb with ATF
arm: socfpga: Add function for checking description from FIT image
arm: socfpga: Load FIT image with ATF support
arm: socfpga: Override 'lowlevel_init' to support ATF
arm: socfpga: Disable "spin-table" method for booting Linux
arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
arm: socfpga: Define SMC function identifiers for PSCI SiP services
arm: socfpga: soc64: Remove PHY interface setup from misc arch init
mmc: dwmmc: socfpga: Add ATF support for MMC driver
net: designware: socfpga: Add ATF support for MAC driver
arm: socfpga: Add ATF support for Reset Manager driver
arm: socfpga: stratix10: Initialize timer in SPL
arm: socfpga: Add ATF support to query FPGA configuration status
arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver
arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
mbox_reset_cold()
arch/arm/mach-socfpga/Kconfig | 2 -
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/board.c | 10 +
arch/arm/mach-socfpga/include/mach/misc.h | 3 +
arch/arm/mach-socfpga/lowlevel_init_64.S | 81
arch/arm/mach-socfpga/mailbox_s10.c| 4 +
arch/arm/mach-socfpga/misc_s10.c | 121 ++
arch/arm/mach-socfpga/reset_manager_s10.c | 10 +
arch/arm/mach-socfpga/timer_s10.c | 3 +-
board/altera/soc64/its/fit_spl_atf.its | 52 +++
...ilex_defconfig => socfpga_agilex_atf_defconfig} | 8 +-
configs/socfpga_agilex_defconfig | 1 -
...x_defconfig => socfpga_stratix10_atf_defconfig} | 23 +-
drivers/fpga/stratix10.c | 141 ++-
drivers/mmc/socfpga_dw_mmc.c | 21 +
drivers/net/dwmac_socfpga.c| 43 +-
include/configs/socfpga_soc64_common.h | 4 +
include/linux/intel-smc.h | 445 +
18 files changed, 871 insertions(+), 103 deletions(-)
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_64.S
create mode 100644 board/altera/soc64/its/fit_spl_atf.its
copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig} (87%)
copy configs/{socfpga_agilex_defconfig => socfpga_stratix10_atf_defconfig}
(68%)
create mode 100644 include/linux/intel-smc.h
--
2.7.4
[PATCH v5 03/17] arm: socfpga: Add function for checking description from FIT image
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/board.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 7c8c05c..5757041 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -86,3 +86,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.7.4
[PATCH v5 02/17] arm: socfpga: add fit source file for pack itb with ATF
From: Chee Hong Ang
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang
---
board/altera/soc64/its/fit_spl_atf.its | 52 ++
1 file changed, 52 insertions(+)
create mode 100644 board/altera/soc64/its/fit_spl_atf.its
diff --git a/board/altera/soc64/its/fit_spl_atf.its
b/board/altera/soc64/its/fit_spl_atf.its
new file mode 100644
index 000..b868da5
--- /dev/null
+++ b/board/altera/soc64/its/fit_spl_atf.its
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper, ATF bl31, DTB";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ data = /incbin/("../../../../u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0020>;
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("../../../../bl31.bin");
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x1000>;
+ entry = <0x1000>;
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat device-tree";
+ data = /incbin/("../../../../u-boot.dtb");
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+};
--
2.7.4
[PATCH v5 01/17] configs: agilex: Remove CONFIG_OF_EMBED
From: Chee Hong Ang CONFIG_OF_EMBED was primarily enabled to support the agilex spl hex file requirements. Since this option now produces a warning during build, and the spl hex can be created using alternate methods, CONFIG_OF_EMBED is no longer needed. Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 4fd84ad..693a774 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -- 2.7.4
[PATCH v5 04/17] arm: socfpga: Load FIT image with ATF support
From: Chee Hong Ang Instead of loading u-boot proper image (u-boot.img), SPL now loads FIT image (u-boot.itb) which includes u-boot proper, ATF and u-boot proper's DTB. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 87c7345..f035381 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -197,6 +197,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); /* SPL SDMMC boot support */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#ifdef CONFIG_SPL_LOAD_FIT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.itb" +#else #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img" +#endif #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ -- 2.7.4
[PATCH v4 21/21] configs: socfpga: Add defconfig for Agilex and Stratix 10 without ATF support
From: Chee Hong Ang Booting Agilex and Stratix 10 without ATF support. SPL -> U-Boot proper -> OS (Linux) Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_nofw_defconfig| 59 ++ configs/socfpga_stratix10_nofw_defconfig | 63 2 files changed, 122 insertions(+) create mode 100644 configs/socfpga_agilex_nofw_defconfig create mode 100644 configs/socfpga_stratix10_nofw_defconfig diff --git a/configs/socfpga_agilex_nofw_defconfig b/configs/socfpga_agilex_nofw_defconfig new file mode 100644 index 000..3d63f8b --- /dev/null +++ b/configs/socfpga_agilex_nofw_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +# CONFIG_PSCI_RESET is not set +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_BOOTDELAY=5 +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +# CONFIG_SPL_USE_TINY_PRINTF is not set diff --git a/configs/socfpga_stratix10_nofw_defconfig b/configs/socfpga_stratix10_nofw_defconfig new file mode 100644 index 000..22169a2 --- /dev/null +++ b/configs/socfpga_stratix10_nofw_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +# CONFIG_PSCI_RESET is not set +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_BOOTDELAY=5 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C0 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set -- 2.7.4
[PATCH v4 20/21] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index f30e7f8..6b39576 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -330,6 +330,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -338,6 +341,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.7.4
[PATCH v4 19/21] arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/stratix10.c | 141 ++-
1 file changed, 140 insertions(+), 1 deletion(-)
diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c
index d8e3250..d726a1b 100644
--- a/drivers/fpga/stratix10.c
+++ b/drivers/fpga/stratix10.c
@@ -5,11 +5,148 @@
#include
#include
-#include
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#include
+#include
+
+#define BITSTREAM_CHUNK_SIZE 0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ break; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bistream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret == INTEL_SIP_SMC_STATUS_REJECTED)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, 3);
+ if (!ret) {
+ for (i = 0; i < 3; i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(2);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, NULL, 0, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bistream(rbf_data, rbf_size);
+ if (ret) {
+ printf("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ printf("FPGA reconfiguration failed!");
+ return ret;
+ }
+
+ puts("FP
[PATCH v4 17/21] arm: socfpga: stratix10: Initialize timer in SPL
From: Chee Hong Ang
Initialize timer in SPL running in secure mode (EL3)
and skip timer initialization in U-Boot proper running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/timer_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/timer_s10.c
b/arch/arm/mach-socfpga/timer_s10.c
index 5723789..0fa56c3 100644
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -13,6 +13,7 @@
*/
int timer_init(void)
{
+#ifdef CONFIG_SPL_BUILD
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
@@ -21,6 +22,6 @@ int timer_init(void)
/* enable processor pysical counter */
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
-
+#endif
return 0;
}
--
2.7.4
[PATCH v4 18/21] arm: socfpga: Add ATF support to query FPGA configuration status
From: Chee Hong Ang
In EL3, do_bridge_reset() directly send mailbox commands to SDM to
query the FPGA configuration status. If running in non-secure
mode (EL2), it invokes SMC service calls to ATF (EL3) to perform the
query.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index ba11bfa..6b5dd03 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -70,11 +71,24 @@ void do_bridge_reset(int enable, unsigned int mask)
{
/* Check FPGA status before bridge enable */
if (enable) {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 config_status = 1;
+
+ /* Send MBOX_RECONFIG_STATUS to SDM */
+ int ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (ret && ret != INTEL_SIP_SMC_STATUS_BUSY) {
+ /* Send MBOX_CONFIG_STATUS to SDM */
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE,
+_status, 1, NULL, 0);
+ }
+#else
int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
-
+#endif
if (ret)
return;
}
--
2.7.4
[PATCH v4 16/21] arm: socfpga: Add ATF support for Reset Manager driver
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI services provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index c743077..c028e2d 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,10 +5,13 @@
*/
#include
+#include
#include
+#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,6 +57,12 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, , 1, NULL, 0))
+ hang();
+#else
if (enable) {
/* clear idle request to all bridges */
setbits_le32(socfpga_get_sysmgr_addr() +
@@ -94,6 +103,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.7.4
[PATCH v4 15/21] net: designware: socfpga: MAC driver access System Manager via 'altera_sysmgr'
From: Chee Hong Ang
MAC driver now access System Manger's EMAC0/EMAC1/EMAC2 registers
to set PHY mode via 'altera_sysmgr' driver.
Signed-off-by: Chee Hong Ang
---
drivers/net/dwmac_socfpga.c | 37 +
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561d..c825cbf 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -21,16 +22,14 @@
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
- void*phy_intf;
+ fdt_addr_t phy_reg_offset;
u32 reg_shift;
};
static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
- struct regmap *regmap;
struct ofnode_phandle_args args;
- void *range;
int ret;
ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
@@ -45,20 +44,7 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice
*dev)
return -EINVAL;
}
- regmap = syscon_node_to_regmap(args.node);
- if (IS_ERR(regmap)) {
- ret = PTR_ERR(regmap);
- dev_err(dev, "Failed to get regmap: %d\n", ret);
- return ret;
- }
-
- range = regmap_get_range(regmap, 0);
- if (!range) {
- dev_err(dev, "Failed to get regmap range\n");
- return -ENOMEM;
- }
-
- pdata->phy_intf = range + args.args[0];
+ pdata->phy_reg_offset = args.args[0];
pdata->reg_shift = args.args[1];
return designware_eth_ofdata_to_platdata(dev);
@@ -69,10 +55,20 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
struct eth_pdata *edata = >dw_eth_pdata.eth_pdata;
struct reset_ctl_bulk reset_bulk;
+ struct udevice *sysmgr;
int ret;
u32 modereg;
u32 modemask;
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
+ "altr,sysmgr-syscon", );
+
+ if (ret == -ENOENT) {
+ debug("%s: Could not find 'altr,sysmgr-syscon' phandle\n",
+ dev->name);
+ return -EINVAL;
+ }
+
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
@@ -97,9 +93,10 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+ misc_read(sysmgr, pdata->phy_reg_offset, , sizeof(modemask));
+ modemask &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift);
+ modemask |= (modereg << pdata->reg_shift);
+ misc_write(sysmgr, pdata->phy_reg_offset, , sizeof(modemask));
reset_release_bulk(_bulk);
--
2.7.4
[PATCH v4 13/21] mmc: dwmmc: socfpga: MMC driver access System Manager via 'altera_sysmgr'
From: Chee Hong Ang
MMC driver now access System Manager's SDMMC control register
to set SDMMC's clock phase shift via 'altera_sysmgr' driver.
Following entry need to be specified under MMC node in device tree:
altr,sysmgr-syscon = < 'x' 'y' 'z'>;
x = offset of the SDMCC control register in System Manager
y = start of drvsel's bit field
z = start of smplsel's bit field
Example:
altr,sysmgr-syscon = < 0x28 0 4>;
Signed-off-by: Chee Hong Ang
---
drivers/mmc/socfpga_dw_mmc.c | 63
1 file changed, 58 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 786cdc7..4a9627b 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -5,16 +5,17 @@
#include
#include
-#include
#include
#include
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -24,6 +25,13 @@ struct socfpga_dwmci_plat {
struct mmc mmc;
};
+/* System Manager's SDMMC CCLK phase shift register */
+struct sysmgr_sdmmc_reg {
+ u32 offset;
+ u32 drvsel_shift;
+ u32 smplsel_shift;
+};
+
/* socfpga implmentation specific driver private data */
struct dwmci_socfpga_priv_data {
struct dwmci_host host;
@@ -45,11 +53,54 @@ static void socfpga_dwmci_reset(struct udevice *dev)
reset_deassert_bulk(_bulk);
}
+static int get_sysmgr_sdmmc_reg(struct udevice *dev,
+ struct sysmgr_sdmmc_reg *reg)
+{
+ struct ofnode_phandle_args args;
+
+ int ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
+ 3, 0, );
+ if (ret) {
+ dev_err(dev, "Failed to get syscon: %d\n", ret);
+ return -EINVAL;
+ }
+
+ if (args.args_count != 3) {
+ dev_err(dev, "Invalid number of syscon args\n");
+ return -EINVAL;
+ }
+
+ reg->offset = args.args[0];
+ reg->drvsel_shift = args.args[1];
+ reg->smplsel_shift = args.args[2];
+
+ return 0;
+}
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
- u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
-((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
+ struct sysmgr_sdmmc_reg sdmmc_reg;
+ struct udevice *sysmgr;
+ u32 sdmmc_mask;
+
+ int ret = uclass_get_device_by_phandle(UCLASS_MISC, host->mmc->dev,
+ "altr,sysmgr-syscon", );
+
+ if (ret == -ENOENT) {
+ debug("%s: Could not find 'altr,sysmgr-syscon' phandle\n",
+ host->mmc->dev->name);
+ hang();
+ }
+
+ if (get_sysmgr_sdmmc_reg(host->mmc->dev, _reg)) {
+ debug("%s: Error reading sysmgr sdmmc reg info\n",
+ host->mmc->dev->name);
+ hang();
+ }
+
+ sdmmc_mask = ((priv->smplsel & 0x7) << sdmmc_reg.smplsel_shift) |
+((priv->drvsel & 0x7) << sdmmc_reg.drvsel_shift);
/* Disable SDMMC clock. */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
@@ -57,10 +108,12 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
- writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
+
+ misc_write(sysmgr, sdmmc_reg.offset, _mask, sizeof(sdmmc_mask));
+ misc_read(sysmgr, sdmmc_reg.offset, _mask, sizeof(sdmmc_mask));
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
- readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+ sdmmc_mask);
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.7.4
[PATCH v4 12/21] arch: arm: socfpga: Enable driver model for misc drivers.
From: Chee Hong Ang Enable this misc driver model for 'altera_sysmgr' driver for socfpga platforms. Signed-off-by: Chee Hong Ang --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8d9f7fc..4ee8ae0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -937,9 +937,11 @@ config ARCH_SOCFPGA select DM select DM_SERIAL select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select MISC select OF_CONTROL select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL + select SPL_DRIVERS_MISC_SUPPORT select SPL_LIBCOMMON_SUPPORT select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI -- 2.7.4
[PATCH v4 14/21] arch: arm: socfpga: Add 'altr, sysmgr-syscon' for MMC node in device tree
From: Chee Hong Ang
In device tree for all socfpga platforms, a phandle to System Manager
('altr,sysmgr-syscon') is needed for MMC node to enable the MMC driver
to configure the SDMMC's clock phase shift via System Manager driver
(altera_sysmgr).
This phandle specifies the offset of the SDMCC control register in
System Manager, start of bit field for drvsel and start of bit field
for smplsel.
Signed-off-by: Chee Hong Ang
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi| 1 +
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi| 1 +
arch/arm/dts/socfpga_cyclone5.dtsi | 1 +
arch/arm/dts/socfpga_stratix10.dtsi | 1 -
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 7 +++
arch/arm/dts/socfpga_stratix10_socdk.dts | 2 --
7 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
index 1908be4..56fd7d9 100644
--- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
@@ -34,6 +34,7 @@
{
drvsel = <3>;
smplsel = <0>;
+ altr,sysmgr-syscon = < 0x28 0 4>;
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index d6b6c2d..887673b 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -44,6 +44,7 @@
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
+ altr,sysmgr-syscon = < 0x28 0 4>;
};
{
diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
index dfaff4c..d2189f1 100644
--- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
@@ -20,6 +20,7 @@
};
{
+ altr,sysmgr-syscon = < 0x108 0 3>;
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi
b/arch/arm/dts/socfpga_cyclone5.dtsi
index 319a71e..c309681 100644
--- a/arch/arm/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5.dtsi
@@ -23,6 +23,7 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ altr,sysmgr-syscon = < 0x108 0 3>;
};
sysmgr@ffd08000 {
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
b/arch/arm/dts/socfpga_stratix10.dtsi
index a8e61cf..9c89065 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -228,7 +228,6 @@
interrupts = <0 96 4>;
fifo-depth = <0x400>;
resets = < SDMMC_RESET>, < SDMMC_OCP_RESET>;
- u-boot,dm-pre-reloc;
status = "disabled";
};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index a903040..ca91b40 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -28,6 +28,13 @@
u-boot,dm-pre-reloc;
};
+ {
+ drvsel = <3>;
+ smplsel = <0>;
+ altr,sysmgr-syscon = < 0x28 0 4>;
+ u-boot,dm-pre-reloc;
+};
+
{
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
b/arch/arm/dts/socfpga_stratix10_socdk.dts
index b7b48a5..ff6e1b2 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -91,8 +91,6 @@
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
- drvsel = <3>;
- smplsel = <0>;
};
{
--
2.7.4
[PATCH v4 09/21] arm: socfpga: Define SMC function identifiers for PSCI SiP services
From: Chee Hong Ang This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang --- include/linux/intel-smc.h | 393 ++ 1 file changed, 393 insertions(+) create mode 100644 include/linux/intel-smc.h diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 000..c5ce100 --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,393 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2020, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include +#include + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of kernel tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * value. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * FPGA configuration completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR: + * There is error during the FPGA configuration process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0x +#define INTEL_SIP_SMC_STATUS_OK0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + *0 full reconfiguration. + *1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any completed + * block, otherwise zero value. + * a2: 64bit physical address of 2nd completed memory block if any completed + * block, other
[PATCH v4 08/21] arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
From: Chee Hong Ang
Allow U-Boot proper running in non-secure mode (EL2) to invoke
SMC call to ATF's PSCI runtime services such as System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration,
Remote System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/misc.h | 3 +++
arch/arm/mach-socfpga/misc_s10.c | 20
2 files changed, 23 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index f6de1cc..b5625e1 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -43,4 +43,7 @@ void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+#endif
#endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index a3f5b43..adfff82 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -164,3 +164,23 @@ void do_bridge_reset(int enable, unsigned int mask)
socfpga_bridges_reset(enable);
}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy([1], [0], arg_len * sizeof(u64));
+
+ smc_call();
+
+ if (ret_arg)
+ memcpy(_arg[0], [1], ret_len * sizeof(u64));
+
+ return regs.regs[0];
+}
+#endif
--
2.7.4
[PATCH v4 10/21] arm: socfpga: soc64: Remove PHY interface setup from misc arch init
From: Chee Hong Ang
'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c | 85 +---
1 file changed, 1 insertion(+), 84 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index adfff82..ba11bfa 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -8,18 +8,10 @@
#include
#include
#include
-#include
-#include
-#include
#include
-#include
-#include
#include
-#include
-#include
#include
-
-#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -44,80 +36,6 @@ static Altera_desc altera_fpga[] = {
};
/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-
-static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
-{
- u32 modereg;
-
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
- !strcmp(phymode, "sgmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- else if (!strcmp(phymode, "rgmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- else if (!strcmp(phymode, "rmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- else
- return -EINVAL;
-
- clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
- gmac_index,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
-
- return 0;
-}
-
-static int socfpga_set_phymode(void)
-{
- const void *fdt = gd->fdt_blob;
- struct fdtdec_phandle_args args;
- const char *phy_mode;
- u32 gmac_index;
- int nodes[3]; /* Max. 3 GMACs */
- int ret, count;
- int i, node;
-
- count = fdtdec_find_aliases_for_id(fdt, "ethernet",
- COMPAT_ALTERA_SOCFPGA_DWMAC,
- nodes, ARRAY_SIZE(nodes));
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
-"#reset-cells", 1, 0,
-);
- if (ret || args.args_count != 1) {
- debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
- continue;
- }
-
- gmac_index = args.args[0] - EMAC0_RESET;
-
- phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
- ret = socfpga_phymode_setup(gmac_index, phy_mode);
- if (ret) {
- debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
- continue;
- }
- }
-
- return 0;
-}
-#else
-static int socfpga_set_phymode(void)
-{
- return 0;
-};
-#endif
-
-/*
* Print CPU information
*/
#if defined(CONFIG_DISPLAY_CPUINFO)
@@ -137,7 +55,6 @@ int arch_misc_init(void)
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
env_set("qspi_clock", qspi_string);
- socfpga_set_phymode();
return 0;
}
#endif
--
2.7.4
[PATCH v4 05/21] arm: socfpga: Override 'lowlevel_init' to support ATF
From: Chee Hong Ang Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Makefile | 2 + arch/arm/mach-socfpga/lowlevel_init_64.S | 81 2 files changed, 83 insertions(+) create mode 100644 arch/arm/mach-socfpga/lowlevel_init_64.S diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543..3758c0a 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o diff --git a/arch/arm/mach-socfpga/lowlevel_init_64.S b/arch/arm/mach-socfpga/lowlevel_init_64.S new file mode 100644 index 000..21402c0 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_64.S @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019, Intel Corporation + */ + +#include +#include +#include +#include + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_SPL_ATF + branch_if_slave x0, 2f +#else + branch_if_slave x0, 1f +#endif + + ldr x0, =GICD_BASE + bl gic_init_secure + b 2f + +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + +#ifdef CONFIG_ARMV8_MULTIENTRY + branch_if_master x0, x1, 3f + + /* +* Slave should wait for master clearing spin table. +* This sync prevent slaves observing incorrect +* value of spin table and jumping to wrong place. +*/ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* +* All slaves will enter EL2 and optionally EL1. +*/ + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el2 + +lowlevel_in_el2: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el1 + +lowlevel_in_el1: +#endif +#endif /* CONFIG_ARMV8_MULTIENTRY */ + +2: +#ifdef CONFIG_SPL_BUILD + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, checkslavecpu + br x5 +checkslavecpu: + branch_if_slave x0, 2b +#endif + +3: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) -- 2.7.4
[PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager driver
From: Chee Hong Ang
This driver (misc uclass) handle the read/write access to
System Manager. For 64 bits platforms, processor needs to be
in secure mode to has write access to most of the System Manager's
registers (except boot scratch registers). When the processor is
running in EL2 (non-secure), this driver will invoke the SMC call
to ATF to perform write access to the System Manager's registers.
All other drivers that require access to System Manager should
go through this driver.
Signed-off-by: Chee Hong Ang
---
drivers/misc/Makefile| 1 +
drivers/misc/altera_sysmgr.c | 115 +++
2 files changed, 116 insertions(+)
create mode 100644 drivers/misc/altera_sysmgr.c
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 2b843de..9fa2411 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -29,6 +29,7 @@ endif
endif
obj-$(CONFIG_ALI152X) += ali512x.o
obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
+obj-$(CONFIG_ARCH_SOCFPGA) += altera_sysmgr.o
obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
obj-$(CONFIG_DS4510) += ds4510.o
diff --git a/drivers/misc/altera_sysmgr.c b/drivers/misc/altera_sysmgr.c
new file mode 100644
index 000..b36ecae
--- /dev/null
+++ b/drivers/misc/altera_sysmgr.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IS_OUT_OF_SYSMGR(addr, range) ((addr) > (range))
+
+struct altera_sysmgr_priv {
+ fdt_addr_t base_addr;
+ fdt_addr_t base_size;
+};
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static int secure_write32(u32 val, fdt_addr_t addr)
+{
+ int ret;
+ u64 args[2];
+
+ args[0] = (u64)addr;
+ args[1] = val;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+ if (ret)
+ return -EIO;
+
+ return 0;
+}
+#endif
+
+static int write32(u32 val, fdt_addr_t addr)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ return secure_write32(val, addr);
+#else
+ writel(val, addr);
+
+ return 0;
+#endif
+}
+
+static int altera_sysmgr_read(struct udevice *dev,
+int offset, void *buf, int size)
+{
+ struct altera_sysmgr_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr = priv->base_addr + offset;
+
+ if (IS_OUT_OF_SYSMGR(addr, priv->base_addr + priv->base_size - size))
+ return -EINVAL;
+
+ if (size != sizeof(u32))
+ return -EIO;
+
+ *(u32 *)buf = readl(addr);
+
+ return 0;
+}
+
+static int altera_sysmgr_write(struct udevice *dev, int offset,
+ const void *buf, int size)
+{
+ struct altera_sysmgr_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr = priv->base_addr + offset;
+
+ if (IS_OUT_OF_SYSMGR(addr, priv->base_addr + priv->base_size - size))
+ return -EINVAL;
+
+ if (size != sizeof(u32))
+ return -EIO;
+
+ return write32(*(u32 *)buf, addr);
+}
+
+static int altera_sysmgr_probe(struct udevice *dev)
+{
+ struct altera_sysmgr_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = ofnode_get_addr_size_index(dev_ofnode(dev), 0, );
+
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base_addr = addr;
+ priv->base_size = size;
+
+ return 0;
+}
+
+static const struct misc_ops altera_sysmgr_ops = {
+ .read = altera_sysmgr_read,
+ .write = altera_sysmgr_write,
+};
+
+static const struct udevice_id altera_sysmgr_ids[] = {
+ { .compatible = "altr,sys-mgr" },
+ {}
+};
+
+U_BOOT_DRIVER(altera_sysmgr) = {
+ .name = "altr,sys-mgr",
+ .id = UCLASS_MISC,
+ .of_match = altera_sysmgr_ids,
+ .priv_auto_alloc_size = sizeof(struct altera_sysmgr_priv),
+ .probe = altera_sysmgr_probe,
+ .ops= _sysmgr_ops,
+};
--
2.7.4
[PATCH v4 04/21] arm: socfpga: Load FIT image with ATF support
From: Chee Hong Ang Instead of loading u-boot proper image (u-boot.img), SPL now loads FIT image (u-boot.itb) which includes u-boot proper, ATF and u-boot proper's DTB. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 87c7345..f035381 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -197,6 +197,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); /* SPL SDMMC boot support */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#ifdef CONFIG_SPL_LOAD_FIT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.itb" +#else #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img" +#endif #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ -- 2.7.4
[PATCH v4 07/21] arm: socfpga: Disable "spin-table" method for booting Linux
From: Chee Hong Ang Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 38d6c1b..0b858af 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select CLK select NCORE_CACHE select SPL_CLK if SPL @@ -77,7 +76,6 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select FPGA_STRATIX10 choice -- 2.7.4
[PATCH v4 06/21] configs: socfpga: Enable FIT image loading with ATF support
From: Chee Hong Ang SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The new boot flow with ATF support is as follow: SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux) U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE). ATF will occupy the address range starting from 0x1000. Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_defconfig| 7 ++- configs/socfpga_stratix10_defconfig | 7 ++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 693a774..2373f89 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_TEXT_BASE=0x20 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 @@ -10,10 +10,15 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its" CONFIG_BOOTDELAY=5 CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " CONFIG_CMD_MEMTEST=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 26db40f..dc34357 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_TEXT_BASE=0x20 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 @@ -10,9 +10,14 @@ CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its" CONFIG_BOOTDELAY=5 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C0 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " CONFIG_CMD_MEMTEST=y -- 2.7.4
[PATCH v4 03/21] arm: socfpga: Add function for checking description from FIT image
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/board.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 7c8c05c..5757041 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -86,3 +86,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.7.4
[PATCH v4 01/21] configs: agilex: Remove CONFIG_OF_EMBED
From: Chee Hong Ang CONFIG_OF_EMBED was primarily enabled to support the agilex spl hex file requirements. Since this option now produces a warning during build, and the spl hex can be created using alternate methods, CONFIG_OF_EMBED is no longer needed. Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 4fd84ad..693a774 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -- 2.7.4
[PATCH v4 02/21] arm: socfpga: add fit source file for pack itb with ATF
From: Chee Hong Ang
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang
---
board/altera/soc64/its/fit_spl_atf.its | 52 ++
1 file changed, 52 insertions(+)
create mode 100644 board/altera/soc64/its/fit_spl_atf.its
diff --git a/board/altera/soc64/its/fit_spl_atf.its
b/board/altera/soc64/its/fit_spl_atf.its
new file mode 100644
index 000..b868da5
--- /dev/null
+++ b/board/altera/soc64/its/fit_spl_atf.its
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper, ATF bl31, DTB";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ data = /incbin/("../../../../u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0020>;
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("../../../../bl31.bin");
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x1000>;
+ entry = <0x1000>;
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat device-tree";
+ data = /incbin/("../../../../u-boot.dtb");
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+};
--
2.7.4
[PATCH v4 00/21] Enable ARM Trusted Firmware for U-Boot
From: "Ang, Chee Hong"
v4 changes:
[PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager
- Add System Manager driver (UCLASS_MISC) to handle secure access for SoC64
[PATCH v4 13/21] mmc: dwmmc: socfpga: MMC driver access System Manager via
'altera_sysmgr'
- DW MMC driver access System Manager via the System Manager driver
[PATCH v4 14/21] arch: arm: socfpga: Add 'altr,sysmgr-syscon' for MMC
- DW MMC driver get DRVSEL & SMPLSEL clock settings from device tree
[PATCH v4 15/21] net: designware: socfpga: MAC driver access System via
'altera_sysmgr'
- DW MAC driver access System Manager via the System Manager driver
v3:
https://lists.denx.de/pipermail/u-boot/2020-February/400986.html
These patchsets have dependency on:
https://lists.denx.de/pipermail/u-boot/2019-September/384906.html
Chee Hong Ang (21):
configs: agilex: Remove CONFIG_OF_EMBED
arm: socfpga: add fit source file for pack itb with ATF
arm: socfpga: Add function for checking description from FIT image
arm: socfpga: Load FIT image with ATF support
arm: socfpga: Override 'lowlevel_init' to support ATF
configs: socfpga: Enable FIT image loading with ATF support
arm: socfpga: Disable "spin-table" method for booting Linux
arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
arm: socfpga: Define SMC function identifiers for PSCI SiP services
arm: socfpga: soc64: Remove PHY interface setup from misc arch init
misc: altera_sysmgr: Add Altera System Manager driver
arch: arm: socfpga: Enable driver model for misc drivers.
mmc: dwmmc: socfpga: MMC driver access System Manager via
'altera_sysmgr'
arch: arm: socfpga: Add 'altr,sysmgr-syscon' for MMC node in device
tree
net: designware: socfpga: MAC driver access System Manager via
'altera_sysmgr'
arm: socfpga: Add ATF support for Reset Manager driver
arm: socfpga: stratix10: Initialize timer in SPL
arm: socfpga: Add ATF support to query FPGA configuration status
arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver
arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
mbox_reset_cold()
configs: socfpga: Add defconfig for Agilex and Stratix 10 without ATF
support
arch/arm/Kconfig | 2 +
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 1 +
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 1 +
arch/arm/dts/socfpga_cyclone5.dtsi | 1 +
arch/arm/dts/socfpga_stratix10.dtsi| 1 -
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 7 +
arch/arm/dts/socfpga_stratix10_socdk.dts | 2 -
arch/arm/mach-socfpga/Kconfig | 2 -
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/board.c | 10 +
arch/arm/mach-socfpga/include/mach/misc.h | 3 +
arch/arm/mach-socfpga/lowlevel_init_64.S | 81 +
arch/arm/mach-socfpga/mailbox_s10.c| 4 +
arch/arm/mach-socfpga/misc_s10.c | 121 ++-
arch/arm/mach-socfpga/reset_manager_s10.c | 10 +
arch/arm/mach-socfpga/timer_s10.c | 3 +-
board/altera/soc64/its/fit_spl_atf.its | 52 +++
configs/socfpga_agilex_defconfig | 8 +-
...lex_defconfig => socfpga_agilex_nofw_defconfig} | 2 +-
configs/socfpga_stratix10_defconfig| 7 +-
..._defconfig => socfpga_stratix10_nofw_defconfig} | 2 +-
drivers/fpga/stratix10.c | 141 +++-
drivers/misc/Makefile | 1 +
drivers/misc/altera_sysmgr.c | 115 ++
drivers/mmc/socfpga_dw_mmc.c | 63 +++-
drivers/net/dwmac_socfpga.c| 37 +-
include/configs/socfpga_soc64_common.h | 4 +
include/linux/intel-smc.h | 393 +
29 files changed, 955 insertions(+), 122 deletions(-)
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_64.S
create mode 100644 board/altera/soc64/its/fit_spl_atf.its
copy configs/{socfpga_agilex_defconfig => socfpga_agilex_nofw_defconfig} (97%)
copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_nofw_defconfig}
(97%)
create mode 100644 drivers/misc/altera_sysmgr.c
create mode 100644 include/linux/intel-smc.h
--
2.7.4
[PATCH v1 2/2] clk: socfpga: Switch to use ofnode API
From: Chee Hong Ang
Replace FDT API with more generic ofnode API.
Signed-off-by: Chee Hong Ang
---
drivers/clk/altera/clk-arria10.c | 52 +++-
1 file changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c
index b7eed94..01bf5ec 100644
--- a/drivers/clk/altera/clk-arria10.c
+++ b/drivers/clk/altera/clk-arria10.c
@@ -190,16 +190,16 @@ static struct clk_ops socfpga_a10_clk_ops = {
static void socfpga_a10_handoff_workaround(struct udevice *dev)
{
struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
- const void *fdt = gd->fdt_blob;
struct clk_bulk *bulk = >clks;
- int i, ret, offset = dev_of_offset(dev);
+ ofnode node = dev_ofnode(dev);
+ int i, ret;
static const char * const socfpga_a10_fixedclk_map[] = {
"osc1", "altera_arria10_hps_eosc1",
"cb_intosc_ls_clk", "altera_arria10_hps_cb_intosc_ls",
"f2s_free_clk", "altera_arria10_hps_f2h_free",
};
- if (fdt_node_check_compatible(fdt, offset, "fixed-clock"))
+ if (!ofnode_device_is_compatible(node, "fixed-clock"))
return;
for (i = 0; i < ARRAY_SIZE(socfpga_a10_fixedclk_map); i += 2)
@@ -227,42 +227,41 @@ static void socfpga_a10_handoff_workaround(struct udevice
*dev)
static int socfpga_a10_clk_bind(struct udevice *dev)
{
- const void *fdt = gd->fdt_blob;
- int offset = dev_of_offset(dev);
bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
+ ofnode node;
int ret;
- for (offset = fdt_first_subnode(fdt, offset);
-offset > 0;
-offset = fdt_next_subnode(fdt, offset)) {
- name = fdt_get_name(fdt, offset, NULL);
+ for (node = dev_read_first_subnode(dev);
+ofnode_valid(node);
+node = ofnode_next_subnode(node)) {
+ name = ofnode_get_name(node);
if (!name)
return -EINVAL;
if (!strcmp(name, "clocks")) {
- offset = fdt_first_subnode(fdt, offset);
- name = fdt_get_name(fdt, offset, NULL);
+ node = ofnode_first_subnode(node);
+ name = ofnode_get_name(node);
if (!name)
return -EINVAL;
}
/* Filter out supported sub-clock */
- if (fdt_node_check_compatible(fdt, offset,
+ if (!ofnode_device_is_compatible(node,
"altr,socfpga-a10-pll-clock") &&
- fdt_node_check_compatible(fdt, offset,
+ !ofnode_device_is_compatible(node,
"altr,socfpga-a10-perip-clk") &&
- fdt_node_check_compatible(fdt, offset,
+ !ofnode_device_is_compatible(node,
"altr,socfpga-a10-gate-clk") &&
- fdt_node_check_compatible(fdt, offset, "fixed-clock"))
+ !ofnode_device_is_compatible(node, "fixed-clock"))
continue;
if (pre_reloc_only &&
- !dm_ofnode_pre_reloc(offset_to_ofnode(offset)))
+ !dm_ofnode_pre_reloc(node))
continue;
ret = device_bind_driver_to_node(dev, "clk-a10", name,
-offset_to_ofnode(offset),
+node,
NULL);
if (ret)
return ret;
@@ -273,18 +272,17 @@ static int socfpga_a10_clk_bind(struct udevice *dev)
static int socfpga_a10_clk_probe(struct udevice *dev)
{
+ ofnode node = dev_ofnode(dev);
struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
struct socfpga_a10_clk_platdata *pplat;
struct udevice *pdev;
- const void *fdt = gd->fdt_blob;
- int offset = dev_of_offset(dev);
clk_get_bulk(dev, >clks);
socfpga_a10_handoff_workaround(dev);
- if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
- plat->regs = devfdt_get_addr(dev);
+ if (ofnode_device_is_compatible(node, "altr,clk-mgr")) {
+ plat->regs = ofnode_get_addr(node);
} else {
pdev = dev_get_parent(dev);
if (!pdev)
@@ -298,18 +296,18 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
plat->regs = pplat->regs;
[PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function
From: Chee Hong Ang
This commit (82de42fa14682d408da935adfb0f935354c5008f) calls child's
ofdata_to_platdata() method before the parent is probed in dm core.
This has caused the driver no longer able to get the correct parent
clock's register base in the ofdata_to_platdata() method because the
parent clocks will only be probed after the child's ofdata_to_platdata().
To resolve this, the clock parent's register base will only be retrieved
by the child in probe() method instead of ofdata_to_platdata().
Signed-off-by: Chee Hong Ang
---
drivers/clk/altera/clk-arria10.c | 40 ++--
1 file changed, 18 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c
index affeb31..b7eed94 100644
--- a/drivers/clk/altera/clk-arria10.c
+++ b/drivers/clk/altera/clk-arria10.c
@@ -274,6 +274,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev)
static int socfpga_a10_clk_probe(struct udevice *dev)
{
struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
+ struct socfpga_a10_clk_platdata *pplat;
+ struct udevice *pdev;
const void *fdt = gd->fdt_blob;
int offset = dev_of_offset(dev);
@@ -281,6 +283,21 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
socfpga_a10_handoff_workaround(dev);
+ if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
+ plat->regs = devfdt_get_addr(dev);
+ } else {
+ pdev = dev_get_parent(dev);
+ if (!pdev)
+ return -ENODEV;
+
+ pplat = dev_get_platdata(pdev);
+ if (!pplat)
+ return -EINVAL;
+
+ plat->ctl_reg = dev_read_u32_default(dev, "reg", 0x0);
+ plat->regs = pplat->regs;
+ }
+
if (!fdt_node_check_compatible(fdt, offset,
"altr,socfpga-a10-pll-clock")) {
/* Main PLL has 3 upstream clock */
@@ -304,29 +321,8 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
static int socfpga_a10_ofdata_to_platdata(struct udevice *dev)
{
struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
- struct socfpga_a10_clk_platdata *pplat;
- struct udevice *pdev;
- const void *fdt = gd->fdt_blob;
unsigned int divreg[3], gatereg[2];
- int ret, offset = dev_of_offset(dev);
- u32 regs;
-
- regs = dev_read_u32_default(dev, "reg", 0x0);
-
- if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
- plat->regs = devfdt_get_addr(dev);
- } else {
- pdev = dev_get_parent(dev);
- if (!pdev)
- return -ENODEV;
-
- pplat = dev_get_platdata(pdev);
- if (!pplat)
- return -EINVAL;
-
- plat->ctl_reg = regs;
- plat->regs = pplat->regs;
- }
+ int ret;
plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
--
2.7.4
[PATCH v1 0/2] Fix A10 clock driver crash after changes in DM core
From: "Ang, Chee Hong" Changes in DM core from following patch crashed the A10 clock driver: commit: 82de42fa14682d408da935adfb0f935354c5008f Subject: dm: core: Allocate parent data separate from probing parent At present the parent is probed before the child's ofdata_to_platdata() method is called. Adjust the logic slightly so that probing parents is not done until afterwards. Signed-off-by: Simon Glass These patchsets fix the A10 driver issue and replce the FDT API with ofnode API. Chee Hong Ang (2): clk: socfpga: Read the clock parent's register base in probe function clk: socfpga: Switch to use ofnode API drivers/clk/altera/clk-arria10.c | 88 +++- 1 file changed, 41 insertions(+), 47 deletions(-) -- 2.7.4
[PATCH v3 20/21] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index f30e7f8..6b39576 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -330,6 +330,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -338,6 +341,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.7.4
[PATCH v3 19/21] arm: socfpga: stratix10: Add ATF support to FPGA reconfig driver
From: Chee Hong Ang
FPGA recpnfiguration driver will call the ATF's PSCI runtime
services if it's running in non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
drivers/fpga/stratix10.c | 141 ++-
1 file changed, 140 insertions(+), 1 deletion(-)
diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c
index d8e3250..050a179 100644
--- a/drivers/fpga/stratix10.c
+++ b/drivers/fpga/stratix10.c
@@ -5,11 +5,148 @@
#include
#include
-#include
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#include
+#include
+
+#define BITSTREAM_CHUNK_SIZE 0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ break; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bistream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, 3);
+ if (!ret) {
+ for (i = 0; i < 3; i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(2);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, NULL, 0, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bistream(rbf_data, rbf_size);
+ if (ret) {
+ printf("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ printf("FPGA reconfiguration failed!");
+ return ret;
+
[PATCH v3 21/21] configs: socfpga: Add defconfig for Agilex and Stratix 10 without ATF support
From: Chee Hong Ang Booting Agilex and Stratix 10 without ATF support. SPL -> U-Boot proper -> OS (Linux) Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_nofw_defconfig| 59 ++ configs/socfpga_stratix10_nofw_defconfig | 63 2 files changed, 122 insertions(+) create mode 100644 configs/socfpga_agilex_nofw_defconfig create mode 100644 configs/socfpga_stratix10_nofw_defconfig diff --git a/configs/socfpga_agilex_nofw_defconfig b/configs/socfpga_agilex_nofw_defconfig new file mode 100644 index 000..3d63f8b --- /dev/null +++ b/configs/socfpga_agilex_nofw_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +# CONFIG_PSCI_RESET is not set +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_BOOTDELAY=5 +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +# CONFIG_SPL_USE_TINY_PRINTF is not set diff --git a/configs/socfpga_stratix10_nofw_defconfig b/configs/socfpga_stratix10_nofw_defconfig new file mode 100644 index 000..22169a2 --- /dev/null +++ b/configs/socfpga_stratix10_nofw_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +# CONFIG_PSCI_RESET is not set +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_BOOTDELAY=5 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C0 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set -- 2.7.4
[PATCH v3 15/21] net: designware: socfpga: Secure register access in MAC driver
From: Chee Hong Ang
Allow MAC driver to access System Manager's EMAC control
registers in non-secure mode.
Signed-off-by: Chee Hong Ang
---
drivers/net/dwmac_socfpga.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561d..293c660 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -17,6 +17,7 @@
#include
#include
+#include
#include
struct dwmac_socfpga_platdata {
@@ -98,8 +99,8 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(_bulk);
modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+ socfpga_secure_reg_update32((phys_addr_t)pdata->phy_intf, modemask,
+ modereg << pdata->reg_shift);
reset_release_bulk(_bulk);
--
2.7.4
