As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng
---
MAINTAINERS | 2 +-
arch/riscv/Kconfig| 8
arch/riscv/cpu/fu540/Kconfig | 2 +-
arch/riscv/cpu/fu740/Kconfig | 2 +-
arch/riscv/cpu/generic/Kconfig| 4 ++--
arch/riscv/cpu/jh7110/Kconfig | 2 +-
arch/riscv/include/asm/global_data.h | 4 ++--
arch/riscv/include/asm/syscon.h | 2 +-
arch/riscv/lib/Makefile | 2 +-
.../lib/{sifive_clint.c => aclint_ipi.c} | 16 +++
board/openpiton/riscv64/Kconfig | 2 +-
board/sipeed/maix/Kconfig | 2 +-
drivers/timer/Makefile| 2 +-
...ive_clint_timer.c => riscv_aclint_timer.c} | 20 +--
14 files changed, 35 insertions(+), 35 deletions(-)
rename arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (73%)
rename drivers/timer/{sifive_clint_timer.c => riscv_aclint_timer.c} (75%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 228d8af433..91f125aed0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1328,7 +1328,7 @@ F:doc/arch/riscv.rst
F: doc/usage/sbi.rst
F: drivers/sysreset/sysreset_sbi.c
F: drivers/timer/andes_plmt_timer.c
-F: drivers/timer/sifive_clint_timer.c
+F: drivers/timer/riscv_aclint_timer.c
F: tools/prelink-riscv.c
RISC-V CANAAN KENDRYTE K210
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 9fcdd8c451..de7d5a9549 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -185,22 +185,22 @@ config DMA_ADDR_T_64BIT
bool
default y if 64BIT
-config SIFIVE_CLINT
+config RISCV_ACLINT
bool
depends on RISCV_MMODE
select REGMAP
select SYSCON
help
- The SiFive CLINT block holds memory-mapped control and status
registers
+ The RISC-V ACLINT block holds memory-mapped control and status
registers
associated with software and timer interrupts.
-config SPL_SIFIVE_CLINT
+config SPL_RISCV_ACLINT
bool
depends on SPL_RISCV_MMODE
select SPL_REGMAP
select SPL_SYSCON
help
- The SiFive CLINT block holds memory-mapped control and status
registers
+ The RISC-V ACLINT block holds memory-mapped control and status
registers
associated with software and timer interrupts.
config SIFIVE_CACHE
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 1604b412b4..c68209d8fb 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -11,7 +11,7 @@ config SIFIVE_FU540
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SPL_SIFIVE_CLINT
+ imply SPL_RISCV_ACLINT
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 3e0c1fddc8..d7ca968717 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -11,7 +11,7 @@ config SIFIVE_FU740
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SPL_SIFIVE_CLINT
+ imply SPL_RISCV_ACLINT
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index e025134b23..897765c3c6 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -9,8 +9,8 @@ config GENERIC_RISCV
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SIFIVE_CLINT if RISCV_MMODE
- imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
+ imply RISCV_ACLINT if RISCV_MMODE
+ imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 3f145415eb..4d9581165b 100644
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -25,4 +25,4 @@ config STARFIVE_JH7110
imply SPL_CPU
imply SPL_LOAD_FIT
imply SPL_OPENSBI
- imply SPL_SIFIVE_CLINT
+ imply SPL_RISCV_ACLINT
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index 31ba72693d..9d97517e12 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,8 +18,8 @@
struct arch_global_data {
long boot_hart; /* boot hart id */
phys_addr_t firmware_fdt_addr;
-#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
- void __iomem *clint;/* clint base address */
+#if CONFIG_IS_ENABLED(RISCV_ACLINT)
+ void __iomem *aclint;
