Re: [PATCH v2 03/14] clk: mtmips: add clock driver for MediaTek MT7621 SoC
On 12/27/21 3:06 AM, Weijie Gao wrote:
On Wed, 2021-12-15 at 11:11 -0500, Sean Anderson wrote:
It is fine to implement only the necessary functionality, but it
should
be done in a way which is easy to extend in the future, and which
won't
cause us compatibility problems.
Generally, I would like to preserve both source and binary
compatibility
with Linux where possible. I am not sure whether they are hard
requirements, so I made a post regarding that question [1]. For now,
addressing my above comments will be fine.
I agreed.
But now I decide to write a simple driver which provides only the bus
clock. It seems that I don't have much time for rewrite the full clock
driver at present.
Well, all you have to do is something like
switch (clk->id) {
case MT7621_CLK_TIMER:
mask = CLKCFG1_TIMER;
break;
/* etc */
}
or use an array if you like that style better.
--Sean
Re: [PATCH v2 03/14] clk: mtmips: add clock driver for MediaTek MT7621 SoC
On Wed, 2021-12-15 at 11:11 -0500, Sean Anderson wrote:
> Hi Weijie,
>
> (sorry for the delayed response)
>
> On 12/3/21 5:06 AM, Weijie Gao wrote:
> > On Fri, 2021-11-26 at 12:44 -0500, Sean Anderson wrote:
> > > On 11/18/21 8:35 PM, Weijie Gao wrote:
> > > > This patch adds a clock driver for MediaTek MT7621 SoC.
> > > > This driver provides clock gate control as well as getting
> > > > clock
> > > > frequency
> > > > for CPU/SYS/XTAL and some peripherals.
> > > >
> > > > Signed-off-by: Weijie Gao
> > > > ---
> > > > v2 changes: none
> > > > ---
> > > >drivers/clk/mtmips/Makefile| 1 +
> > > >drivers/clk/mtmips/clk-mt7621.c| 260
> > > > +
> > > >include/dt-bindings/clock/mt7621-clk.h | 42
> > > >3 files changed, 303 insertions(+)
> > > >create mode 100644 drivers/clk/mtmips/clk-mt7621.c
> > > >create mode 100644 include/dt-bindings/clock/mt7621-clk.h
> > > >
> > > > diff --git a/drivers/clk/mtmips/Makefile
> > > > b/drivers/clk/mtmips/Makefile
> > > > index 732e7f2545..ee8b5afe87 100644
> > > > --- a/drivers/clk/mtmips/Makefile
> > > > +++ b/drivers/clk/mtmips/Makefile
> > > > @@ -1,4 +1,5 @@
> > > ># SPDX-License-Identifier: GPL-2.0
> > > >
> > > >obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
> > > > +obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
> > > >obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
> > > > diff --git a/drivers/clk/mtmips/clk-mt7621.c
> > > > b/drivers/clk/mtmips/clk-mt7621.c
> > > > new file mode 100644
> > > > index 00..3799d1806a
> > > > --- /dev/null
> > > > +++ b/drivers/clk/mtmips/clk-mt7621.c
> > > > @@ -0,0 +1,260 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
> > > > + *
> > > > + * Author: Weijie Gao
> > > > + */
> > > > +
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +
> > > > +#define SYSC_MAP_SIZE 0x100
> > > > +#define MEMC_MAP_SIZE 0x1000
> > > > +
> > > > +/* SYSC */
> > > > +#define SYSCFG0_REG0x10
> > > > +#define XTAL_MODE_SEL_S6
> > > > +#define XTAL_MODE_SEL_M0x1c0
> > >
> > > Please use genmask to define this:
> > >
> > > #define XTAL_MODE_SEL_M GENMASK(8, 6)
> > >
> > > and SEL_S is unnecessary, see commentary below.
> > >
> > > > +
> > > > +#define CLKCFG0_REG0x2c
> > > > +#define CPU_CLK_SEL_S 30
> > > > +#define CPU_CLK_SEL_M 0xc000
> > > > +#define PERI_CLK_SEL 0x10
> > > > +
> > > > +#define CLKCFG1_REG0x30
> > > > +
> > > > +#define CUR_CLK_STS_REG0x44
> > > > +#define CUR_CPU_FDIV_S 8
> > > > +#define CUR_CPU_FDIV_M 0x1f00
> > > > +#define CUR_CPU_FFRAC_S0
> > > > +#define CUR_CPU_FFRAC_M0x1f
> > > > +
> > > > +/* MEMC */
> > > > +#define MEMPLL1_REG0x0604
> > > > +#define RG_MEPL_DIV2_SEL_S 1
> > > > +#define RG_MEPL_DIV2_SEL_M 0x06
> > > > +
> > > > +#define MEMPLL6_REG0x0618
> > > > +#define MEMPLL18_REG 0x0648
> > > > +#define RG_MEPL_PREDIV_S 12
> > > > +#define RG_MEPL_PREDIV_M 0x3000
> > > > +#define RG_MEPL_FBDIV_S4
> > > > +#define RG_MEPL_FBDIV_M0x7f0
> > > > +
> > > > +/* Clock sources */
> > > > +#define CLK_SRC_CPU-1
> > > > +#define CLK_SRC_CPU_D2 -2
> > > > +#define CLK_SRC_DDR-3
> > > > +#define CLK_SRC_SYS-4
> > > > +#define CLK_SRC_XTAL -5
> > > > +#define CLK_SRC_PERI -6
> > >
> > > Please use an enum. And why are these negative?
> >
> > I'll rewrite this
> >
> > >
> > > > +/* EPLL clock */
> > > > +#define EPLL_CLK 5000
> > > > +
> > > > +struct mt7621_clk_priv {
> > > > + void __iomem *sysc_base;
> > > > + void __iomem *memc_base;
> > > > + int cpu_clk;
> > > > + int ddr_clk;
> > > > + int sys_clk;
> > > > + int xtal_clk;
> > > > +};
> > > > +
> > > > +static const int mt7621_clks[] = {
> > > > + [CLK_SYS] = CLK_SRC_SYS,
> > > > + [CLK_DDR] = CLK_SRC_DDR,
> > > > + [CLK_CPU] = CLK_SRC_CPU,
> > > > + [CLK_XTAL] = CLK_SRC_XTAL,
> > > > + [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
> > > > + [CLK_UART3] = CLK_SRC_PERI,
> > > > + [CLK_UART2] = CLK_SRC_PERI,
> > > > + [CLK_UART1] = CLK_SRC_PERI,
> > > > + [CLK_SPI] = CLK_SRC_SYS,
> > > > + [CLK_I2C] = CLK_SRC_PERI,
> > > > + [CLK_TIMER] = CLK_SRC_PERI,
> > > > +};
> > > > +
> > > > +static
Re: [PATCH v2 03/14] clk: mtmips: add clock driver for MediaTek MT7621 SoC
Hi Weijie,
(sorry for the delayed response)
On 12/3/21 5:06 AM, Weijie Gao wrote:
On Fri, 2021-11-26 at 12:44 -0500, Sean Anderson wrote:
On 11/18/21 8:35 PM, Weijie Gao wrote:
This patch adds a clock driver for MediaTek MT7621 SoC.
This driver provides clock gate control as well as getting clock
frequency
for CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/clk/mtmips/Makefile| 1 +
drivers/clk/mtmips/clk-mt7621.c| 260
+
include/dt-bindings/clock/mt7621-clk.h | 42
3 files changed, 303 insertions(+)
create mode 100644 drivers/clk/mtmips/clk-mt7621.c
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/drivers/clk/mtmips/Makefile
b/drivers/clk/mtmips/Makefile
index 732e7f2545..ee8b5afe87 100644
--- a/drivers/clk/mtmips/Makefile
+++ b/drivers/clk/mtmips/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
+obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
diff --git a/drivers/clk/mtmips/clk-mt7621.c
b/drivers/clk/mtmips/clk-mt7621.c
new file mode 100644
index 00..3799d1806a
--- /dev/null
+++ b/drivers/clk/mtmips/clk-mt7621.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SYSC_MAP_SIZE 0x100
+#define MEMC_MAP_SIZE 0x1000
+
+/* SYSC */
+#define SYSCFG0_REG0x10
+#define XTAL_MODE_SEL_S6
+#define XTAL_MODE_SEL_M0x1c0
Please use genmask to define this:
#define XTAL_MODE_SEL_M GENMASK(8, 6)
and SEL_S is unnecessary, see commentary below.
+
+#define CLKCFG0_REG0x2c
+#define CPU_CLK_SEL_S 30
+#define CPU_CLK_SEL_M 0xc000
+#define PERI_CLK_SEL 0x10
+
+#define CLKCFG1_REG0x30
+
+#define CUR_CLK_STS_REG0x44
+#define CUR_CPU_FDIV_S 8
+#define CUR_CPU_FDIV_M 0x1f00
+#define CUR_CPU_FFRAC_S0
+#define CUR_CPU_FFRAC_M0x1f
+
+/* MEMC */
+#define MEMPLL1_REG0x0604
+#define RG_MEPL_DIV2_SEL_S 1
+#define RG_MEPL_DIV2_SEL_M 0x06
+
+#define MEMPLL6_REG0x0618
+#define MEMPLL18_REG 0x0648
+#define RG_MEPL_PREDIV_S 12
+#define RG_MEPL_PREDIV_M 0x3000
+#define RG_MEPL_FBDIV_S4
+#define RG_MEPL_FBDIV_M0x7f0
+
+/* Clock sources */
+#define CLK_SRC_CPU-1
+#define CLK_SRC_CPU_D2 -2
+#define CLK_SRC_DDR-3
+#define CLK_SRC_SYS-4
+#define CLK_SRC_XTAL -5
+#define CLK_SRC_PERI -6
Please use an enum. And why are these negative?
I'll rewrite this
+/* EPLL clock */
+#define EPLL_CLK 5000
+
+struct mt7621_clk_priv {
+ void __iomem *sysc_base;
+ void __iomem *memc_base;
+ int cpu_clk;
+ int ddr_clk;
+ int sys_clk;
+ int xtal_clk;
+};
+
+static const int mt7621_clks[] = {
+ [CLK_SYS] = CLK_SRC_SYS,
+ [CLK_DDR] = CLK_SRC_DDR,
+ [CLK_CPU] = CLK_SRC_CPU,
+ [CLK_XTAL] = CLK_SRC_XTAL,
+ [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
+ [CLK_UART3] = CLK_SRC_PERI,
+ [CLK_UART2] = CLK_SRC_PERI,
+ [CLK_UART1] = CLK_SRC_PERI,
+ [CLK_SPI] = CLK_SRC_SYS,
+ [CLK_I2C] = CLK_SRC_PERI,
+ [CLK_TIMER] = CLK_SRC_PERI,
+};
+
+static ulong mt7621_clk_get_rate(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 val;
+
+ if (clk->id >= ARRAY_SIZE(mt7621_clks))
+ return 0;
+
+ switch (mt7621_clks[clk->id]) {
+ case CLK_SRC_CPU:
+ return priv->cpu_clk;
+ case CLK_SRC_CPU_D2:
+ return priv->cpu_clk / 2;
+ case CLK_SRC_DDR:
+ return priv->ddr_clk;
+ case CLK_SRC_SYS:
+ return priv->sys_clk;
+ case CLK_SRC_XTAL:
+ return priv->xtal_clk;
+ case CLK_SRC_PERI:
+ val = readl(priv->sysc_base + CLKCFG0_REG);
+ if (val & PERI_CLK_SEL)
+ return priv->xtal_clk;
+ else
+ return EPLL_CLK;
+ default:
+ return 0;
-ENOSYS
+ }
+}
+
+static int mt7621_clk_enable(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 31)
Please compare with a symbol.
OK. actually the clock gate register is 32-bit,
Re: [PATCH v2 03/14] clk: mtmips: add clock driver for MediaTek MT7621 SoC
On Fri, 2021-11-26 at 12:44 -0500, Sean Anderson wrote:
> On 11/18/21 8:35 PM, Weijie Gao wrote:
> > This patch adds a clock driver for MediaTek MT7621 SoC.
> > This driver provides clock gate control as well as getting clock
> > frequency
> > for CPU/SYS/XTAL and some peripherals.
> >
> > Signed-off-by: Weijie Gao
> > ---
> > v2 changes: none
> > ---
> > drivers/clk/mtmips/Makefile| 1 +
> > drivers/clk/mtmips/clk-mt7621.c| 260
> > +
> > include/dt-bindings/clock/mt7621-clk.h | 42
> > 3 files changed, 303 insertions(+)
> > create mode 100644 drivers/clk/mtmips/clk-mt7621.c
> > create mode 100644 include/dt-bindings/clock/mt7621-clk.h
> >
> > diff --git a/drivers/clk/mtmips/Makefile
> > b/drivers/clk/mtmips/Makefile
> > index 732e7f2545..ee8b5afe87 100644
> > --- a/drivers/clk/mtmips/Makefile
> > +++ b/drivers/clk/mtmips/Makefile
> > @@ -1,4 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0
> >
> > obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
> > +obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
> > obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
> > diff --git a/drivers/clk/mtmips/clk-mt7621.c
> > b/drivers/clk/mtmips/clk-mt7621.c
> > new file mode 100644
> > index 00..3799d1806a
> > --- /dev/null
> > +++ b/drivers/clk/mtmips/clk-mt7621.c
> > @@ -0,0 +1,260 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
> > + *
> > + * Author: Weijie Gao
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#define SYSC_MAP_SIZE 0x100
> > +#define MEMC_MAP_SIZE 0x1000
> > +
> > +/* SYSC */
> > +#define SYSCFG0_REG0x10
> > +#define XTAL_MODE_SEL_S6
> > +#define XTAL_MODE_SEL_M0x1c0
>
> Please use genmask to define this:
>
> #define XTAL_MODE_SEL_M GENMASK(8, 6)
>
> and SEL_S is unnecessary, see commentary below.
>
> > +
> > +#define CLKCFG0_REG0x2c
> > +#define CPU_CLK_SEL_S 30
> > +#define CPU_CLK_SEL_M 0xc000
> > +#define PERI_CLK_SEL 0x10
> > +
> > +#define CLKCFG1_REG0x30
> > +
> > +#define CUR_CLK_STS_REG0x44
> > +#define CUR_CPU_FDIV_S 8
> > +#define CUR_CPU_FDIV_M 0x1f00
> > +#define CUR_CPU_FFRAC_S0
> > +#define CUR_CPU_FFRAC_M0x1f
> > +
> > +/* MEMC */
> > +#define MEMPLL1_REG0x0604
> > +#define RG_MEPL_DIV2_SEL_S 1
> > +#define RG_MEPL_DIV2_SEL_M 0x06
> > +
> > +#define MEMPLL6_REG0x0618
> > +#define MEMPLL18_REG 0x0648
> > +#define RG_MEPL_PREDIV_S 12
> > +#define RG_MEPL_PREDIV_M 0x3000
> > +#define RG_MEPL_FBDIV_S4
> > +#define RG_MEPL_FBDIV_M0x7f0
> > +
> > +/* Clock sources */
> > +#define CLK_SRC_CPU-1
> > +#define CLK_SRC_CPU_D2 -2
> > +#define CLK_SRC_DDR-3
> > +#define CLK_SRC_SYS-4
> > +#define CLK_SRC_XTAL -5
> > +#define CLK_SRC_PERI -6
>
> Please use an enum. And why are these negative?
I'll rewrite this
>
> > +/* EPLL clock */
> > +#define EPLL_CLK 5000
> > +
> > +struct mt7621_clk_priv {
> > + void __iomem *sysc_base;
> > + void __iomem *memc_base;
> > + int cpu_clk;
> > + int ddr_clk;
> > + int sys_clk;
> > + int xtal_clk;
> > +};
> > +
> > +static const int mt7621_clks[] = {
> > + [CLK_SYS] = CLK_SRC_SYS,
> > + [CLK_DDR] = CLK_SRC_DDR,
> > + [CLK_CPU] = CLK_SRC_CPU,
> > + [CLK_XTAL] = CLK_SRC_XTAL,
> > + [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
> > + [CLK_UART3] = CLK_SRC_PERI,
> > + [CLK_UART2] = CLK_SRC_PERI,
> > + [CLK_UART1] = CLK_SRC_PERI,
> > + [CLK_SPI] = CLK_SRC_SYS,
> > + [CLK_I2C] = CLK_SRC_PERI,
> > + [CLK_TIMER] = CLK_SRC_PERI,
> > +};
> > +
> > +static ulong mt7621_clk_get_rate(struct clk *clk)
> > +{
> > + struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
> > + u32 val;
> > +
> > + if (clk->id >= ARRAY_SIZE(mt7621_clks))
> > + return 0;
> > +
> > + switch (mt7621_clks[clk->id]) {
> > + case CLK_SRC_CPU:
> > + return priv->cpu_clk;
> > + case CLK_SRC_CPU_D2:
> > + return priv->cpu_clk / 2;
> > + case CLK_SRC_DDR:
> > + return priv->ddr_clk;
> > + case CLK_SRC_SYS:
> > + return priv->sys_clk;
> > + case CLK_SRC_XTAL:
> > + return priv->xtal_clk;
> > + case CLK_SRC_PERI:
> > + val = readl(priv->sysc_base + CLKCFG0_REG);
> > + if (val & PERI_CLK_SEL)
> > + return
Re: [PATCH v2 03/14] clk: mtmips: add clock driver for MediaTek MT7621 SoC
On 11/18/21 8:35 PM, Weijie Gao wrote:
This patch adds a clock driver for MediaTek MT7621 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/clk/mtmips/Makefile| 1 +
drivers/clk/mtmips/clk-mt7621.c| 260 +
include/dt-bindings/clock/mt7621-clk.h | 42
3 files changed, 303 insertions(+)
create mode 100644 drivers/clk/mtmips/clk-mt7621.c
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile
index 732e7f2545..ee8b5afe87 100644
--- a/drivers/clk/mtmips/Makefile
+++ b/drivers/clk/mtmips/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
+obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
diff --git a/drivers/clk/mtmips/clk-mt7621.c b/drivers/clk/mtmips/clk-mt7621.c
new file mode 100644
index 00..3799d1806a
--- /dev/null
+++ b/drivers/clk/mtmips/clk-mt7621.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SYSC_MAP_SIZE 0x100
+#define MEMC_MAP_SIZE 0x1000
+
+/* SYSC */
+#define SYSCFG0_REG0x10
+#define XTAL_MODE_SEL_S6
+#define XTAL_MODE_SEL_M0x1c0
Please use genmask to define this:
#define XTAL_MODE_SEL_M GENMASK(8, 6)
and SEL_S is unnecessary, see commentary below.
+
+#define CLKCFG0_REG0x2c
+#define CPU_CLK_SEL_S 30
+#define CPU_CLK_SEL_M 0xc000
+#define PERI_CLK_SEL 0x10
+
+#define CLKCFG1_REG0x30
+
+#define CUR_CLK_STS_REG0x44
+#define CUR_CPU_FDIV_S 8
+#define CUR_CPU_FDIV_M 0x1f00
+#define CUR_CPU_FFRAC_S0
+#define CUR_CPU_FFRAC_M0x1f
+
+/* MEMC */
+#define MEMPLL1_REG0x0604
+#define RG_MEPL_DIV2_SEL_S 1
+#define RG_MEPL_DIV2_SEL_M 0x06
+
+#define MEMPLL6_REG0x0618
+#define MEMPLL18_REG 0x0648
+#define RG_MEPL_PREDIV_S 12
+#define RG_MEPL_PREDIV_M 0x3000
+#define RG_MEPL_FBDIV_S4
+#define RG_MEPL_FBDIV_M0x7f0
+
+/* Clock sources */
+#define CLK_SRC_CPU-1
+#define CLK_SRC_CPU_D2 -2
+#define CLK_SRC_DDR-3
+#define CLK_SRC_SYS-4
+#define CLK_SRC_XTAL -5
+#define CLK_SRC_PERI -6
Please use an enum. And why are these negative?
+/* EPLL clock */
+#define EPLL_CLK 5000
+
+struct mt7621_clk_priv {
+ void __iomem *sysc_base;
+ void __iomem *memc_base;
+ int cpu_clk;
+ int ddr_clk;
+ int sys_clk;
+ int xtal_clk;
+};
+
+static const int mt7621_clks[] = {
+ [CLK_SYS] = CLK_SRC_SYS,
+ [CLK_DDR] = CLK_SRC_DDR,
+ [CLK_CPU] = CLK_SRC_CPU,
+ [CLK_XTAL] = CLK_SRC_XTAL,
+ [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
+ [CLK_UART3] = CLK_SRC_PERI,
+ [CLK_UART2] = CLK_SRC_PERI,
+ [CLK_UART1] = CLK_SRC_PERI,
+ [CLK_SPI] = CLK_SRC_SYS,
+ [CLK_I2C] = CLK_SRC_PERI,
+ [CLK_TIMER] = CLK_SRC_PERI,
+};
+
+static ulong mt7621_clk_get_rate(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 val;
+
+ if (clk->id >= ARRAY_SIZE(mt7621_clks))
+ return 0;
+
+ switch (mt7621_clks[clk->id]) {
+ case CLK_SRC_CPU:
+ return priv->cpu_clk;
+ case CLK_SRC_CPU_D2:
+ return priv->cpu_clk / 2;
+ case CLK_SRC_DDR:
+ return priv->ddr_clk;
+ case CLK_SRC_SYS:
+ return priv->sys_clk;
+ case CLK_SRC_XTAL:
+ return priv->xtal_clk;
+ case CLK_SRC_PERI:
+ val = readl(priv->sysc_base + CLKCFG0_REG);
+ if (val & PERI_CLK_SEL)
+ return priv->xtal_clk;
+ else
+ return EPLL_CLK;
+ default:
+ return 0;
-ENOSYS
+ }
+}
+
+static int mt7621_clk_enable(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 31)
Please compare with a symbol.
+ return -1;
-ENOSYS
+
+ setbits_32(priv->sysc_base + CLKCFG1_REG, BIT(clk->id));
+
+ return 0;
+}
+
+static int mt7621_clk_disable(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv =
[PATCH v2 03/14] clk: mtmips: add clock driver for MediaTek MT7621 SoC
This patch adds a clock driver for MediaTek MT7621 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/clk/mtmips/Makefile| 1 +
drivers/clk/mtmips/clk-mt7621.c| 260 +
include/dt-bindings/clock/mt7621-clk.h | 42
3 files changed, 303 insertions(+)
create mode 100644 drivers/clk/mtmips/clk-mt7621.c
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile
index 732e7f2545..ee8b5afe87 100644
--- a/drivers/clk/mtmips/Makefile
+++ b/drivers/clk/mtmips/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
+obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
diff --git a/drivers/clk/mtmips/clk-mt7621.c b/drivers/clk/mtmips/clk-mt7621.c
new file mode 100644
index 00..3799d1806a
--- /dev/null
+++ b/drivers/clk/mtmips/clk-mt7621.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SYSC_MAP_SIZE 0x100
+#define MEMC_MAP_SIZE 0x1000
+
+/* SYSC */
+#define SYSCFG0_REG0x10
+#define XTAL_MODE_SEL_S6
+#define XTAL_MODE_SEL_M0x1c0
+
+#define CLKCFG0_REG0x2c
+#define CPU_CLK_SEL_S 30
+#define CPU_CLK_SEL_M 0xc000
+#define PERI_CLK_SEL 0x10
+
+#define CLKCFG1_REG0x30
+
+#define CUR_CLK_STS_REG0x44
+#define CUR_CPU_FDIV_S 8
+#define CUR_CPU_FDIV_M 0x1f00
+#define CUR_CPU_FFRAC_S0
+#define CUR_CPU_FFRAC_M0x1f
+
+/* MEMC */
+#define MEMPLL1_REG0x0604
+#define RG_MEPL_DIV2_SEL_S 1
+#define RG_MEPL_DIV2_SEL_M 0x06
+
+#define MEMPLL6_REG0x0618
+#define MEMPLL18_REG 0x0648
+#define RG_MEPL_PREDIV_S 12
+#define RG_MEPL_PREDIV_M 0x3000
+#define RG_MEPL_FBDIV_S4
+#define RG_MEPL_FBDIV_M0x7f0
+
+/* Clock sources */
+#define CLK_SRC_CPU-1
+#define CLK_SRC_CPU_D2 -2
+#define CLK_SRC_DDR-3
+#define CLK_SRC_SYS-4
+#define CLK_SRC_XTAL -5
+#define CLK_SRC_PERI -6
+
+/* EPLL clock */
+#define EPLL_CLK 5000
+
+struct mt7621_clk_priv {
+ void __iomem *sysc_base;
+ void __iomem *memc_base;
+ int cpu_clk;
+ int ddr_clk;
+ int sys_clk;
+ int xtal_clk;
+};
+
+static const int mt7621_clks[] = {
+ [CLK_SYS] = CLK_SRC_SYS,
+ [CLK_DDR] = CLK_SRC_DDR,
+ [CLK_CPU] = CLK_SRC_CPU,
+ [CLK_XTAL] = CLK_SRC_XTAL,
+ [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
+ [CLK_UART3] = CLK_SRC_PERI,
+ [CLK_UART2] = CLK_SRC_PERI,
+ [CLK_UART1] = CLK_SRC_PERI,
+ [CLK_SPI] = CLK_SRC_SYS,
+ [CLK_I2C] = CLK_SRC_PERI,
+ [CLK_TIMER] = CLK_SRC_PERI,
+};
+
+static ulong mt7621_clk_get_rate(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 val;
+
+ if (clk->id >= ARRAY_SIZE(mt7621_clks))
+ return 0;
+
+ switch (mt7621_clks[clk->id]) {
+ case CLK_SRC_CPU:
+ return priv->cpu_clk;
+ case CLK_SRC_CPU_D2:
+ return priv->cpu_clk / 2;
+ case CLK_SRC_DDR:
+ return priv->ddr_clk;
+ case CLK_SRC_SYS:
+ return priv->sys_clk;
+ case CLK_SRC_XTAL:
+ return priv->xtal_clk;
+ case CLK_SRC_PERI:
+ val = readl(priv->sysc_base + CLKCFG0_REG);
+ if (val & PERI_CLK_SEL)
+ return priv->xtal_clk;
+ else
+ return EPLL_CLK;
+ default:
+ return 0;
+ }
+}
+
+static int mt7621_clk_enable(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 31)
+ return -1;
+
+ setbits_32(priv->sysc_base + CLKCFG1_REG, BIT(clk->id));
+
+ return 0;
+}
+
+static int mt7621_clk_disable(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 31)
+ return -1;
+
+ clrbits_32(priv->sysc_base + CLKCFG1_REG, BIT(clk->id));
+
+ return 0;
+}
+
+const struct clk_ops mt7621_clk_ops = {
+ .enable = mt7621_clk_enable,
+ .disable = mt7621_clk_disable,
+ .get_rate
