Re: [PATCH v6 05/18] video: tegra20: dc: add PLLD2 parent support

[Thierry Reding]

On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> T30+ SOC have second PLLD - PLLD2 which can be actively used by
> DC and act as main DISP1/2 clock parent.
>
> Tested-by: Agneli  # Toshiba AC100 T20
> Tested-by: Robert Eckelmann  # ASUS TF101
> Tested-by: Andreas Westman Dorcsak  # ASUS Grouper E1565
> Tested-by: Ion Agorria  # HTC One X
> Tested-by: Svyatoslav Ryhel  # Nvidia Tegratab T114
> Signed-off-by: Svyatoslav Ryhel 
> ---
>  drivers/video/tegra20/tegra-dc.c | 6 ++
>  1 file changed, 6 insertions(+)

Reviewed-by: Thierry Reding 


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[PATCH v6 05/18] video: tegra20: dc: add PLLD2 parent support

[Svyatoslav Ryhel]

T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.

Tested-by: Agneli  # Toshiba AC100 T20
Tested-by: Robert Eckelmann  # ASUS TF101
Tested-by: Andreas Westman Dorcsak  # ASUS Grouper E1565
Tested-by: Ion Agorria  # HTC One X
Tested-by: Svyatoslav Ryhel  # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel 
---
 drivers/video/tegra20/tegra-dc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 0e94e665ef..56a23b3c97 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -304,6 +304,12 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
if (priv->dc_clk[1] == CLOCK_ID_DISPLAY)
rate /= 2;
 
+#ifndef CONFIG_TEGRA20
+   /* PLLD2 obeys same rules as PLLD but it is present only on T30+ */
+   if (priv->dc_clk[1] == CLOCK_ID_DISPLAY2)
+   rate /= 2;
+#endif
+
/*
 * HOST1X is init by default at 150MHz with PLLC as parent
 */
-- 
2.40.1