Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka Jain
Signed-off-by: York Sun
---
Changes for v2:
Udpated description related to ODT off, Removed
cpo, write_data_delay, force_2t parameters as they
are not longer used.
board/freescale/t104xrdb/ddr.c | 13 +++--
board/freescale/t104xrdb/ddr.h | 38 --
include/configs/T1040RDB.h |2 +-
include/configs/T1042RDB_PI.h |2 +-
4 files changed, 25 insertions(+), 30 deletions(-)
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 9009afa..57d0f9c 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -46,7 +46,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
pbsp = udimms[0];
- /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+ /* Get clk_adjust according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 100;
@@ -54,14 +54,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
@@ -74,13 +70,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
@@ -112,8 +105,8 @@ found:
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
}
phys_size_t initdram(int board_type)
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index 9276b59..09b30b9 100644
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -6,7 +6,6 @@
#ifndef __DDR_H__
#define __DDR_H__
-
dimm_params_t ddr_raw_timing = {
.n_ranks = 2,
.rank_density = 2147483648u,
@@ -14,22 +13,21 @@ dimm_params_t ddr_raw_timing = {
.primary_sdram_width = 64,
.ec_sdram_width = 8,
.registered_dimm = 0,
- .mirrored_dimm = 1,
+ .mirrored_dimm = 0,
.n_row_addr = 15,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 2,/* ECC */
.burst_lengths_bitmask = 0x0c,
-
.tckmin_x_ps = 1071,
- .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
- .taa_ps = 13910,
+ .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
+ .taa_ps = 13125,
.twr_ps = 15000,
- .trcd_ps = 13910,
+ .trcd_ps = 13125,
.trrd_ps = 6000,
- .trp_ps = 13910,
+ .trp_ps = 13125,
.tras_ps = 34000,
- .trc_ps = 48910,
+ .trc_ps = 48125,
.trfc_ps = 26,
.twtr_ps = 7500,
.trtp_ps = 7500,
@@ -45,9 +43,6 @@ struct board_specific_parameters {
u32 wrlvl_start;
