Re: [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe But we have HYP enabled. In this case why are the series dependent on this patch? Well, if the HYP is enabled, the host OS will use the Physical timer, and these CNTVOFFs could be cleared in kernel too. When and where to clear them is better ? In uboot or in kernel when needed? If HYP mode is available CNTVOFF is cleared in Linux. What I am trying to say is that it will work also without the patch you mentioned. Diana Yes, it will work, but the time won't be correct sometimes till the CNTVOFFs are cleared in Linux, which we can see from the Linux boot logs with the following is enabled: CONFIG_PRINTK_TIME=y This is because, if the HYP mode is available for Host OS, the Physical timers Will be used, but the ARCH ARM Timer will still use the Virtual timer's counter To count the xtime. Thanks, BRs Xiubo ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
On 07/04/2014 04:31 AM, Xiubo Li-B47053 wrote: This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe But we have HYP enabled. In this case why are the series dependent on this patch? Well, if the HYP is enabled, the host OS will use the Physical timer, and these CNTVOFFs could be cleared in kernel too. When and where to clear them is better ? In uboot or in kernel when needed? If HYP mode is available CNTVOFF is cleared in Linux. What I am trying to say is that it will work also without the patch you mentioned. Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe timers that are not synchronized, effectively seeing time going backward... Patch work: http://patchwork.ozlabs.org/patch/343084/ Xiubo Li (4): ARM: fix the ARCH Timer frequency setting. ARM: add the pen address byte reverting support. ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +-- board/freescale/ls1021aqds/ls1021aqds.c | 110 +++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 -- include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-) -- 1.8.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
On 07/03/2014 12:51 PM, Xiubo Li wrote: This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe But we have HYP enabled. In this case why are the series dependent on this patch? timers that are not synchronized, effectively seeing time going backward... Patch work: http://patchwork.ozlabs.org/patch/343084/ Xiubo Li (4): ARM: fix the ARCH Timer frequency setting. ARM: add the pen address byte reverting support. ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +-- board/freescale/ls1021aqds/ls1021aqds.c | 110 +++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 -- include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-) Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe But we have HYP enabled. In this case why are the series dependent on this patch? Well, if the HYP is enabled, the host OS will use the Physical timer, and these CNTVOFFs could be cleared in kernel too. When and where to clear them is better ? In uboot or in kernel when needed? Thanks, BRs Xiubo timers that are not synchronized, effectively seeing time going backward... Patch work: http://patchwork.ozlabs.org/patch/343084/ Xiubo Li (4): ARM: fix the ARCH Timer frequency setting. ARM: add the pen address byte reverting support. ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +- - board/freescale/ls1021aqds/ls1021aqds.c | 110 +++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 -- include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-) Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
