USB spec says that the minimum disconnect threshold should be
over 525 mV. However, internal USB PHY threshold value is below
this specified value. Due to this some devices disconnect at
run-time. Hence, phy settings are tweaked to increased disconnect
threshold to be above 525mV by using this workaround.
Signed-off-by: Suresh Gupta suresh.gu...@freescale.com
---
Changes for v2:
- Incorporated missing SOC's affected by errata
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 62 +++
arch/powerpc/include/asm/config_mpc85xx.h | 7
arch/powerpc/include/asm/fsl_errata.h | 34 +
include/fsl_usb.h | 23 +++-
5 files changed, 128 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7693899..2a15802 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -265,6 +265,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
(SVR_REV(svr) = CONFIG_SYS_FSL_A004447_SVR_REV))
puts(Work-around for Erratum I2C-A004447 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+ if (has_erratum_a006261())
+ puts(Work-around for Erratum A006261 enabled\n);
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b31efb7..81aeadd 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -36,6 +36,54 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
+{
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+ u32 xcvrprg = in_be32(usb_phy-port1.xcvrprg);
+
+ /* Increase Disconnect Threshold by 50mV */
+ xcvrprg = ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+ INC_DCNT_THRESHOLD_50MV;
+ /* Enable programming of USB High speed Disconnect threshold */
+ xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+ out_be32(usb_phy-port1.xcvrprg, xcvrprg);
+
+ xcvrprg = in_be32(usb_phy-port2.xcvrprg);
+ /* Increase Disconnect Threshold by 50mV */
+ xcvrprg = ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+ INC_DCNT_THRESHOLD_50MV;
+ /* Enable programming of USB High speed Disconnect threshold */
+ xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+ out_be32(usb_phy-port2.xcvrprg, xcvrprg);
+#else
+
+ u32 temp = 0;
+ u32 status = in_be32(usb_phy-status1);
+
+ u32 squelch_prog_rd_0_2 =
+ (status CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+ u32 squelch_prog_rd_3_5 =
+ (status CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+ setbits_be32(usb_phy-config1,
+CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+ setbits_be32(usb_phy-config2,
+CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+
+ temp = squelch_prog_rd_0_2 CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+ out_be32(usb_phy-config2, in_be32(usb_phy-config2) | temp);
+
+ temp = squelch_prog_rd_3_5 CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+ out_be32(usb_phy-config2, in_be32(usb_phy-config2) | temp);
+#endif
+}
+#endif
+
+
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -625,6 +673,10 @@ skip_l2:
{
struct ccsr_usb_phy __iomem *usb_phy1 =
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+ if (has_erratum_a006261())
+ fsl_erratum_a006261_workaround(usb_phy1);
+#endif
out_be32(usb_phy1-usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
@@ -633,6 +685,10 @@ skip_l2:
{
struct ccsr_usb_phy __iomem *usb_phy2 =
(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+ if (has_erratum_a006261())
+ fsl_erratum_a006261_workaround(usb_phy2);
+#endif
out_be32(usb_phy2-usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
@@ -672,8 +728,14 @@ skip_l2:
CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
setbits_be32(usb_phy-port2.pwrfltcfg,
CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+ if (has_erratum_a006261())
+
