Re: [U-Boot] [RFC 5/5] B4860QDS: Add support of 2 stage NAND boot loader
Dear Prabhakar Kushwaha, Prabhakar Kushwaha prabhakar at freescale.com writes: snipped Thank you for the replies. You mention you use the PBL... but probably not a pblimage. The patch correctly fixes RAMBOOT_PBL as a trigger to generate the pblimage (u- boot.pbl) but there seems to be no RCW or PBI file defined. B4860 does support PBL based NAND boot. but I have yet to integrate u-boot-spl.bin to generated u-boot-spl.pbl. This is in my TODO list This is my understanding (if need be, take it with a grain of salt) The Makefiles need to be modified so that SPL build will create a pblimage. The mkimage pblimage needs to be executed only on the SPL binary. Then the top-level Makefile proceeds in concatenating the u-boot-spl.bin (now a pblimage) and u-boot.bin. I have one question, can this scenario be implemented on a P5040? i.e. simulate that CPC is around 128Kb and load u-boot via SPL? Now all corenet processors seem to only support pblimage booting. yes. This scenario can be implemented for P5040. Only need to create spl.c file + define constants. Seems easy enough :-) though I probably don't have the resources to actually implement it. Just a note. The pblimage booting is not very flexible now. Currently it assumes that u-boot.pbl will fit into CPC (configured as SRAM). This is OK for most processors (i.e P5040 with 1Mb CPC) but it will not work for others (i.e T1040/1042 with only 256Kb CPC). So there is a need to have SPL in this case. All the best, Rommel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC 5/5] B4860QDS: Add support of 2 stage NAND boot loader
On 09/20/2013 04:51 AM, Rommel Custodio wrote: Dear Prabhakar Kushwaha, Prabhakar Kushwaha prabhakar at freescale.com writes: snipped Thank you for the replies. You mention you use the PBL... but probably not a pblimage. The patch correctly fixes RAMBOOT_PBL as a trigger to generate the pblimage (u- boot.pbl) but there seems to be no RCW or PBI file defined. B4860 does support PBL based NAND boot. but I have yet to integrate u-boot-spl.bin to generated u-boot-spl.pbl. This is in my TODO list This is my understanding (if need be, take it with a grain of salt) The Makefiles need to be modified so that SPL build will create a pblimage. The mkimage pblimage needs to be executed only on the SPL binary. Then the top-level Makefile proceeds in concatenating the u-boot-spl.bin (now a pblimage) and u-boot.bin. yes. This is my next plan. I have one question, can this scenario be implemented on a P5040? i.e. simulate that CPC is around 128Kb and load u-boot via SPL? Now all corenet processors seem to only support pblimage booting. yes. This scenario can be implemented for P5040. Only need to create spl.c file + define constants. Seems easy enough :-) though I probably don't have the resources to actually implement it. Just a note. The pblimage booting is not very flexible now. Currently it assumes that u-boot.pbl will fit into CPC (configured as SRAM). This is OK for most processors (i.e P5040 with 1Mb CPC) but it will not work for others (i.e T1040/1042 with only 256Kb CPC). So there is a need to have SPL in this case. Me along with others are owner of T1040 platform. This whole exercise is done for T1040 future soc which may have 512K CPC. Once base patch of T1040QDS has been accepted(already in review state). I will send a patch set to add support of 2 Stage boot loader. Regards, Prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC 5/5] B4860QDS: Add support of 2 stage NAND boot loader
Thanks Rommel for checking this patch. Please find my reply in-lined On 09/18/2013 03:28 AM, Rommel Custodio wrote: Dear Prabhakar Kushwaha, Prabhakar Kushwaha prabhakar at freescale.com writes: Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(96K). This further initialise DDR using SPD and environment and copy u-boot(512 kb) from NAND to DDR. Finally SPL transer control to u-boot. These are just some quick comments after a build test and a quick code review. The environment is latest with some patches from patchworks. 1) Your code does not build with http://patchwork.ozlabs.org/patch/274193/ powerpc-linux-objcopy --gap-fill=0xff -O binary /export/home/git.denx.de/local/obj-B4860QDS_NAND/u-boot /export/home/git.denx.de/local/obj-B4860QDS_NAND/u-boot.bin /export/home/git.denx.de/local/obj-B4860QDS_NAND/tools/mkimage -n \ -R -T pblimage \ -d /export/home/git.denx.de/local/obj-B4860QDS_NAND/u- boot.bin /export/home//git.denx.de/local/obj-B4860QDS_NAND/u-boot.pbl Error:-R - Can't open make: *** [/export/home/git.denx.de/local/obj-B4860QDS_NAND/u-boot.pbl] Error 1 You mention you use the PBL... but probably not a pblimage. The patch correctly fixes RAMBOOT_PBL as a trigger to generate the pblimage (u- boot.pbl) but there seems to be no RCW or PBI file defined. B4860 does support PBL based NAND boot. but I have yet to integrate u-boot-spl.bin to generated u-boot-spl.pbl. This is in my TODO list 2) Use the new SPDX identifiers http://patchwork.ozlabs.org/patch/261356/ Sure This was mainlined a few revisions ago. 3) Watch out for the new boards.cfg layout I will take care of it while providing the patch. I have one question, can this scenario be implemented on a P5040? i.e. simulate that CPC is around 128Kb and load u-boot via SPL? Now all corenet processors seem to only support pblimage booting. yes. This scenario can be implemented for P5040. Only need to create spl.c file + define constants. Thanks, Prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC 5/5] B4860QDS: Add support of 2 stage NAND boot loader
Dear Prabhakar Kushwaha, Prabhakar Kushwaha prabhakar at freescale.com writes: Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(96K). This further initialise DDR using SPD and environment and copy u-boot(512 kb) from NAND to DDR. Finally SPL transer control to u-boot. These are just some quick comments after a build test and a quick code review. The environment is latest with some patches from patchworks. 1) Your code does not build with http://patchwork.ozlabs.org/patch/274193/ powerpc-linux-objcopy --gap-fill=0xff -O binary /export/home/git.denx.de/local/obj-B4860QDS_NAND/u-boot /export/home/git.denx.de/local/obj-B4860QDS_NAND/u-boot.bin /export/home/git.denx.de/local/obj-B4860QDS_NAND/tools/mkimage -n \ -R -T pblimage \ -d /export/home/git.denx.de/local/obj-B4860QDS_NAND/u- boot.bin /export/home//git.denx.de/local/obj-B4860QDS_NAND/u-boot.pbl Error:-R - Can't open make: *** [/export/home/git.denx.de/local/obj-B4860QDS_NAND/u-boot.pbl] Error 1 You mention you use the PBL... but probably not a pblimage. The patch correctly fixes RAMBOOT_PBL as a trigger to generate the pblimage (u- boot.pbl) but there seems to be no RCW or PBI file defined. 2) Use the new SPDX identifiers http://patchwork.ozlabs.org/patch/261356/ This was mainlined a few revisions ago. 3) Watch out for the new boards.cfg layout I have one question, can this scenario be implemented on a P5040? i.e. simulate that CPC is around 128Kb and load u-boot via SPL? Now all corenet processors seem to only support pblimage booting. All the best, Rommel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC 5/5] B4860QDS: Add support of 2 stage NAND boot loader
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(96K). This further
initialise DDR using SPD and environment and copy u-boot(512 kb) from NAND to
DDR.
Finally SPL transer control to u-boot.
Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
This is a prototype done on B4860.It has 512K internal RAM.
We only configured SRAM as 256K and made sure only 128KB is used
throught SPL execution.
board/freescale/b4860qds/Makefile |7 +-
board/freescale/b4860qds/ddr.c|6 +-
board/freescale/b4860qds/spl.c| 128 +
board/freescale/b4860qds/tlb.c| 10 +++
boards.cfg|2 +-
include/configs/B4860QDS.h| 58 +++--
6 files changed, 203 insertions(+), 8 deletions(-)
create mode 100644 board/freescale/b4860qds/spl.c
diff --git a/board/freescale/b4860qds/Makefile
b/board/freescale/b4860qds/Makefile
index a864c0b..42819a6 100644
--- a/board/freescale/b4860qds/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -8,10 +8,15 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o
+endif
+ifndef CONFIG_SPL_BUILD
COBJS-y+= $(BOARD).o
-COBJS-y+= ddr.o
COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o
COBJS-$(CONFIG_PCI)+= pci.o
+endif
+COBJS-y+= ddr.o
COBJS-y+= law.o
COBJS-y+= tlb.o
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index b82b3d4..467be3c 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -181,12 +181,16 @@ phys_size_t initdram(int board_type)
puts(Initializingusing SPD\n);
+#ifdef CONFIG_SPL_BUILD
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x10);
dram_size *= 0x10;
- puts(DDR: );
+#else
+ puts(DDR has been initialised by pre loader\n);
+ dram_size = 0x8000;
+#endif
return dram_size;
}
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
new file mode 100644
index 000..55891fc
--- /dev/null
+++ b/board/freescale/b4860qds/spl.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include common.h
+#include asm/processor.h
+#include asm/mmu.h
+#include ns16550.h
+#include asm/spl.h
+#include asm/fsl_law.h
+#include asm/fsl_ddr_sdram.h
+#include malloc.h
+#include nand.h
+#include i2c.h
+#include ../common/qixis.h
+#include b4860qds_qixis.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((sysclk_conf 0x0C) 2) {
+ case QIXIS_CLK_100:
+ return 1;
+ case QIXIS_CLK_125:
+ return 12500;
+ case QIXIS_CLK_133:
+ return 1;
+ }
+ return ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (ddrclk_conf 0x03) {
+ case QIXIS_CLK_100:
+ return 1;
+ case QIXIS_CLK_125:
+ return 12500;
+ case QIXIS_CLK_133:
+ return 1;
+ }
+ return ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, uart_clk;
+ u32 stack = CONFIG_SPL_RELOC_STACK;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ /* plat_ratio = 10; */
+ plat_ratio = (in_be32(gur-rcwsr[0]) 25) 0x1f;
+ uart_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+uart_clk / 16 / CONFIG_BAUDRATE);
+
+ /* clear BSS segment */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Set STACK pointer */
+ asm
