Re: [PULL] u-boot-riscv/master
On Thu, Oct 19, 2023 at 07:41:24PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 9a0cf3993f71043ba08c315572c54622de42d447: > > Merge branch '2023-10-17-spl-test-some-load-methods' (2023-10-18 08:28:00 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to bc5a50452bd42029d6587e1596b44ff235655e90: > > riscv: Add Zbb support for building U-Boot (2023-10-19 17:29:50 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18215 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Oct 05, 2023 at 04:10:55PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 65b9b3462bec2966911658836983819ab4e4823e: > > Merge branch 'next_pinctrl_sync' of > https://source.denx.de/u-boot/custodians/u-boot-sh (2023-10-02 15:19:02 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 7cfdacbe8020292845bd5eba63b576b8586c433c: > > configs: sifive: enable poweroff command on Unmatched (2023-10-04 18:23:59 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18005 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Tue, Sep 26, 2023 at 01:21:50PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 15155ab0a3d1f839509bcac620bfb38f950bead6: > > Merge tag 'u-boot-imx-20230923' of > https://source.denx.de/u-boot/custodians/u-boot-imx (2023-09-24 17:15:31 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 16dbe3d9d45527f67d479535a22dc4054ae93e99: > > riscv: set fdtfile on VisionFive 2 (2023-09-26 10:43:02 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17879 > > However, this patch has landed in the "next" branch. > Could we cherry-pick this commit to have this patch on master branch ? > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Sep 21, 2023 at 09:36:01AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit b9b83a86f0e84e837191db120c279a9cc0e3434b: > > Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh > (2023-09-17 09:25:42 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 43177705ab29ed1ccca970096de1ef3c6095e7e6: > > board: visionfive2: Fixup memory size passed to kernel (2023-09-20 20:30:30 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/1 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Tue, Sep 05, 2023 at 11:30:34AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 493fd3363f6da6a784514657d689c7cda0f390d5: > > nokia_rx51: Remove platform (2023-09-04 21:14:32 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to dfe08374943c0e898fcfaf7327f69e0fb56b7d23: > > risc-v: implement DBCN based debug console (2023-09-05 10:53:55 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17650 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Aug 10, 2023 at 06:32:30PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ec58228830a1f68e8e65099387cf12c5a91c9e72: > > Merge tag 'x86-pull-20230809' of > https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-09 13:17:34 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 47ed15125cccd98e041cdff3b6bbe675a2418ec2: > > riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE (2023-08-10 10:58:55 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17276 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On 2023/8/2 17:31, Leo Liang wrote: > Hi Bin, > > On Wed, Aug 02, 2023 at 02:27:29PM +0800, Bin Meng wrote: >> Hi Leo, >> >> On Wed, Aug 2, 2023 at 1:49 PM Leo Liang wrote: >> > >> > Hi Tom, >> > >> > The following changes since commit >> > 7755b2200777f72dca87dd169138e95f011bbcb9: >> > >> > Merge tag 'x86-pull-20230801' of >> > https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 >> > -0400) >> > >> > are available in the Git repository at: >> > >> > https://source.denx.de/u-boot/custodians/u-boot-riscv.git >> > >> > for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d: >> > >> > acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800) >> > >> > CI result shows no issue: >> > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177 >> > >> > >> > >> > + Fix compilation error for CI when enabling RTL8169 driver >> > + Fix compilation error for pci_mmc.c by adding acpi_table header file >> > + Support StarFive JH7110 PCIe driver >> > + Enable PCI on Unmatched board >> > >> > >> > >> > Heinrich Schuchardt (2): >> > riscv: sifive: initialize PCI on Unmatched >> > acpi: Add missing RISC-V acpi_table header >> > >> > Mason Huo (3): >> > starfive: pci: Add StarFive JH7110 pcie driver >> > configs: starfive-jh7110: Add support for PCIe host driver >> > riscv: dts: starfive: Enable PCIe host controller >> > >> > Minda Chen (5): >> > i2c: designware: Add Kconfig for designware_i2c_pci.c >> > net: rtl8169: Fix compile warning in rtl8169 >> > net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V >> > net: rtl8169: Add one device ID 0x8161 >> > configs: starfive-jh7110: Add CONFIG_RTL8169 >> > >> >> Looks the second half of this series is missed? >> https://patchwork.ozlabs.org/project/uboot/list/?series=365237 >> >> Regards, >> Bin > > Thanks for the reminder! > I did omit this second half of the series by accident! > I will re-send the PR again ASAP! > > Best regards, > Leo Hi Leo and Bin Thanks!
Re: [PULL] u-boot-riscv/master
Hi Bin, On Wed, Aug 02, 2023 at 02:27:29PM +0800, Bin Meng wrote: > Hi Leo, > > On Wed, Aug 2, 2023 at 1:49 PM Leo Liang wrote: > > > > Hi Tom, > > > > The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9: > > > > Merge tag 'x86-pull-20230801' of > > https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 > > -0400) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d: > > > > acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177 > > > > > > > > + Fix compilation error for CI when enabling RTL8169 driver > > + Fix compilation error for pci_mmc.c by adding acpi_table header file > > + Support StarFive JH7110 PCIe driver > > + Enable PCI on Unmatched board > > > > > > > > Heinrich Schuchardt (2): > > riscv: sifive: initialize PCI on Unmatched > > acpi: Add missing RISC-V acpi_table header > > > > Mason Huo (3): > > starfive: pci: Add StarFive JH7110 pcie driver > > configs: starfive-jh7110: Add support for PCIe host driver > > riscv: dts: starfive: Enable PCIe host controller > > > > Minda Chen (5): > > i2c: designware: Add Kconfig for designware_i2c_pci.c > > net: rtl8169: Fix compile warning in rtl8169 > > net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V > > net: rtl8169: Add one device ID 0x8161 > > configs: starfive-jh7110: Add CONFIG_RTL8169 > > > > Looks the second half of this series is missed? > https://patchwork.ozlabs.org/project/uboot/list/?series=365237 > > Regards, > Bin Thanks for the reminder! I did omit this second half of the series by accident! I will re-send the PR again ASAP! Best regards, Leo
Re: [PULL] u-boot-riscv/master
Hi Leo, On Wed, Aug 2, 2023 at 1:49 PM Leo Liang wrote: > > Hi Tom, > > The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9: > > Merge tag 'x86-pull-20230801' of > https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d: > > acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177 > > > > + Fix compilation error for CI when enabling RTL8169 driver > + Fix compilation error for pci_mmc.c by adding acpi_table header file > + Support StarFive JH7110 PCIe driver > + Enable PCI on Unmatched board > > > > Heinrich Schuchardt (2): > riscv: sifive: initialize PCI on Unmatched > acpi: Add missing RISC-V acpi_table header > > Mason Huo (3): > starfive: pci: Add StarFive JH7110 pcie driver > configs: starfive-jh7110: Add support for PCIe host driver > riscv: dts: starfive: Enable PCIe host controller > > Minda Chen (5): > i2c: designware: Add Kconfig for designware_i2c_pci.c > net: rtl8169: Fix compile warning in rtl8169 > net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V > net: rtl8169: Add one device ID 0x8161 > configs: starfive-jh7110: Add CONFIG_RTL8169 > Looks the second half of this series is missed? https://patchwork.ozlabs.org/project/uboot/list/?series=365237 Regards, Bin
Re: [PULL] u-boot-riscv/master
On Mon, Jul 24, 2023 at 08:01:22AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 247aa5a191159ea7e03bf1918e22fbbb784cd410: > > Merge branch '2023-07-21-assorted-TI-platform-updates' (2023-07-21 19:33:05 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 6aabe229f8440c4960b904baf3aa33f692eea9a1: > > riscv: define a cache line size for the generic CPU (2023-07-24 13:22:24 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17015 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Wed, Jul 12, 2023 at 06:58:21AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 8e21064cb3452950b09301baec06d86e37342471: > > Merge tag 'efi-2023-07-rc7' of > https://source.denx.de/u-boot/custodians/u-boot-efi (2023-07-11 13:27:32 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git master > > for you to fetch changes up to 478fedfda42ea2a444991de1696fa0adc8bb16d4: > > doc: t-head: lpi4a: document Lichee PI 4A board (2023-07-12 13:21:41 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16856 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Fri, Apr 21, 2023 at 12:41:14AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79: > > Merge tag 'u-boot-nand-20230417' of > https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17 > 10:47:33 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 04d16be55404ee07134b4171dea37eff9ad8fa5a: > > riscv: Support CONFIG_REMAKE_ELF (2023-04-20 20:45:08 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16065 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Fri, Feb 17, 2023 at 10:01:54AM -0500, Tom Rini wrote: > On Fri, Feb 17, 2023 at 12:12:18PM +, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0: > > > > Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 7574b6476afc1fd76816be6567458f6ca4f44234: > > > > riscv: binman: Add help message for missing blobs (2023-02-17 19:07:48 > > +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15225 > > > > I've taken this to u-boot/master, but for the rest of the cycle please > make sure any changes for master are clearly bug fixes, and otherwise > apply to next instead. Thanks! Hi Tom, Understood! Thanks for merging this! Best regards, Leo > > -- > Tom
Re: [PULL] u-boot-riscv/master
On Fri, Feb 17, 2023 at 12:12:18PM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0: > > Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 7574b6476afc1fd76816be6567458f6ca4f44234: > > riscv: binman: Add help message for missing blobs (2023-02-17 19:07:48 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15225 > I've taken this to u-boot/master, but for the rest of the cycle please make sure any changes for master are clearly bug fixes, and otherwise apply to next instead. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Feb 02, 2023 at 06:30:07AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 73a3f5139182a0389d505bf29b0ad4bc29424cf8: > > Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-01-31 > 18:28:07 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 2b0af9feb594b68a75e4f111bde7f55ddb14995d: > > board: sifive: unmatched: enable booting on a second NVME device > (2023-02-01 16:17:59 +0800) > > CI result show no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15011 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Dec 08, 2022 at 11:23:37AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 14f2d087a3d6347ba0ff7a7e9aaff6955e53e7a8: > > Merge tag 'sound-2023-01-rc4' of > https://source.denx.de/u-boot/custodians/u-boot-efi (2022-12-06 10:07:01 > -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 57b9900cd59ad492f74390515901788459f1e8aa: > > riscv: use imply instead of select for SPL_SEPARATE_BSS (2022-12-08 > 15:50:22 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14369 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Wed, Nov 16, 2022 at 06:16:25AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit c4ee4fe92e9be120be6d12718273dec6b63cc7d9: > > Merge tag 'u-boot-imx-20221114' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-11-14 09:33:36 > -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 591e0f878083925e7afff82e1774ba295a7767aa: > > riscv: enable reset via SBI on PolarFire Icicle Kit (2022-11-15 15:37:17 > +0800) > > CI shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14105 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
Hi Tom, On Thu, Nov 03, 2022 at 12:57:05PM -0400, Tom Rini wrote: > On Thu, Nov 03, 2022 at 07:04:33AM +, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7: > > > > Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support' > > (2022-11-01 09:32:21 -0400) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > Can you please start including a few line summary of the changes in your > pull requests? > Sorry for not including any summary before, will for sure summarize the PRs in the pull requests. > > > > for you to fetch changes up to 7321bad25f18684b53cff4346543fb2da2a2c0d0: > > > > riscv: Update Microchip MPFS Icicle Kit support (2022-11-03 13:27:56 > > +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13999 > > > > Applied to u-boot/master, thanks! > > -- > Tom Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Nov 03, 2022 at 07:04:33AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7: > > Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support' > (2022-11-01 09:32:21 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git Can you please start including a few line summary of the changes in your pull requests? > > for you to fetch changes up to 7321bad25f18684b53cff4346543fb2da2a2c0d0: > > riscv: Update Microchip MPFS Icicle Kit support (2022-11-03 13:27:56 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13999 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Oct 20, 2022 at 12:36:23PM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 3724ddf157aab3bd009c1da234b9a1af1621b544: > > Merge branch '2022-10-18-TI-platform-updates' (2022-10-18 18:13:39 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to b3b44c674a473bdd3d53cf5196fae897107af619: > > riscv: ae350: Check firmware_fdt_addr header (2022-10-20 15:26:31 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13866 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Tue, Sep 06, 2022 at 06:07:36AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 427aa3c9b72b6672f714389a6f71b6cc2841d559: > > Merge tag 'tpm-03092022' of > https://source.denx.de/u-boot/custodians/u-boot-tpm (2022-09-03 14:55:37 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 4a98207b2335b7108e964b831dc92f046c87: > > RISC-V: enable CONFIG_SYSRESET_SBI by default (2022-09-06 13:00:58 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13361 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Aug 11, 2022 at 09:38:31PM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit cdebee1fd9fa04cc4c972f826bae19b28c253eb0: > > Merge branch '2022-08-10-assorted-updates' (2022-08-10 17:49:20 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to aa0eda17cf98448c3ef826204f38c76bf48b3345: > > spl: opensbi: convert scratch options to config (2022-08-11 18:46:41 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13119 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Mon, May 30, 2022 at 11:05:54AM -0400, Tom Rini wrote: > On Sat, May 28, 2022 at 09:02:09AM +, Leo Liang wrote: > > On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote: > > > On Fri, May 27, 2022 at 02:36:29AM +, Leo Liang wrote: > > > > > > > Hi Tom, > > > > > > > > The following changes since commit > > > > 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > > > > > > > Merge branch 'master' of > > > > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 > > > > 23:29:00 -0400) > > > > > > > > are available in the Git repository at: > > > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > > > > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: > > > > > > > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 > > > > 18:42:34 +0800) > > > > > > > > CI result shows no issue: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 > > > > > > First, I've applied this to u-boot/master now. Second, will > > > https://patchwork.ozlabs.org/project/uboot/patch/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/ > > > be coming soon? Thanks! > > > > Hi Tom, > > > > This patch you mentioned will not pass CI, and the reason for that > > is the toolchain used for RISC-V in CI does not have corresponding > > settings for zifencei and zicsr. > > (detailed disscussion: > > https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.gh...@canonical.com/) > > (CI result: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/440735) > > > > The patch looks valid, but will fail CI on 32-bit configs. > > If we use 32-bit toolchain to test 32-bit configs, then > > problems solved. > > > > Do you have any comments? > > I guess I'm OK with saying we should use a 32bit toolchain for 32bit > riscv, if that's how things should be handled moving forward for > everyone else. > > -- > Tom Hi Tom, Sorry for taking such a long time to reply. Recap: All the "riscv: fix compitible with binutils 2.38" patches that try to support new RISC-V ISA extension will cause U-Boot CI to fail because the toolchain used in U-Boot CI do not support the new multilib settings. (original discussion: https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.gh...@canonical.com/) We found that current RISC-V toolchains from kernel.org do not support zifencei and zicsr extensions' multilib settings, regardless of the toolchain version. (Both gcc 11.1.0, 12.1.0 do not support the needed settings. https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/ https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.1.0/) But we also found that if we use recent upstream riscv-gnu-toolchain, we could build an gcc-12.1.0 toolchain that does support multilib settings and could fix this issue. We have provided a Dockerfile as a reference build script[1] and a prebuilt toolchain[2] for U-Boot CI to use. We have also verified the CI process could execute successfully with your base image and the provided riscv64-linux toolchain[3]. I guess the coming update of the toolchain in kernel.org should contain the new multilib settings, so I was wondering if we could replace the riscv64-linux toolchain from kernel.org with this prebuilt toolchain we've provided on github[2] temporarily? After studying a bit of the buildman tool, the earlier idea that "use different toolchains for different board configs" would require an amount of modification, thus we think its best to replace the toolchain temporarily to fix this issue, then the patch could be applied without CI failure. [1] https://github.com/ycliang-andes/riscv-toolchain/blob/master/Dockerfile [2] https://github.com/ycliang-andes/riscv-toolchain/releases/download/v1.0/x86_64-gcc-12.1.0-nolibc-riscv64-linux.tar.xz [3] https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13129
Re: [PULL] u-boot-riscv/master
On Sat, May 28, 2022 at 09:02:09AM +, Leo Liang wrote: > On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote: > > On Fri, May 27, 2022 at 02:36:29AM +, Leo Liang wrote: > > > > > Hi Tom, > > > > > > The following changes since commit > > > 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > > > > > Merge branch 'master' of > > > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 > > > 23:29:00 -0400) > > > > > > are available in the Git repository at: > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: > > > > > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 > > > 18:42:34 +0800) > > > > > > CI result shows no issue: > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 > > > > First, I've applied this to u-boot/master now. Second, will > > https://patchwork.ozlabs.org/project/uboot/patch/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/ > > be coming soon? Thanks! > > Hi Tom, > > This patch you mentioned will not pass CI, and the reason for that > is the toolchain used for RISC-V in CI does not have corresponding > settings for zifencei and zicsr. > (detailed disscussion: > https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.gh...@canonical.com/) > (CI result: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/440735) > > The patch looks valid, but will fail CI on 32-bit configs. > If we use 32-bit toolchain to test 32-bit configs, then > problems solved. > > Do you have any comments? I guess I'm OK with saying we should use a 32bit toolchain for 32bit riscv, if that's how things should be handled moving forward for everyone else. -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote: > On Fri, May 27, 2022 at 02:36:29AM +, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > > > Merge branch 'master' of > > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 > > -0400) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: > > > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 > > 18:42:34 +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 > > First, I've applied this to u-boot/master now. Second, will > https://patchwork.ozlabs.org/project/uboot/patch/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/ > be coming soon? Thanks! Hi Tom, This patch you mentioned will not pass CI, and the reason for that is the toolchain used for RISC-V in CI does not have corresponding settings for zifencei and zicsr. (detailed disscussion: https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.gh...@canonical.com/) (CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/440735) The patch looks valid, but will fail CI on 32-bit configs. If we use 32-bit toolchain to test 32-bit configs, then problems solved. Do you have any comments? Best regards. Leo > -- > Tom
Re: [PULL] u-boot-riscv/master
On Fri, May 27, 2022 at 02:36:29AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > Merge branch 'master' of > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 > 18:42:34 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 First, I've applied this to u-boot/master now. Second, will https://patchwork.ozlabs.org/project/uboot/patch/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/ be coming soon? Thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Wed, Apr 06, 2022 at 04:43:30AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 59bffec43a657598b194b9eb30dc01eec06078c7: > > Merge branch '2022-04-04-platform-updates' (2022-04-05 13:45:22 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 776e8aca0bad2900dc9c12b87dedb732a9f8e39b: > > riscv: alloc space exhausted (2022-04-06 10:58:13 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11595 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Wed, Mar 16, 2022 at 10:56:40AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit c149bf41404e34014e37de32fac332892b11bd4a: > > Prepare v2022.04-rc4 (2022-03-14 16:39:08 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to aa34e13346cf727197981c599f688b406005049a: > > pinctrl: k210: Fix bias-pull-up (2022-03-15 17:43:11 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11297 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Feb 10, 2022 at 03:16:03PM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 531c00894577a0a852431adf61ade76925f8b162: > > Merge branch '2022-02-08-TI-platform-updates' (2022-02-08 12:28:04 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 7c08680aa32db12e5a7e2765cfc8b7e8ce8895ff: > > doc: qemu-riscv: Update documentation for QEMU spike machine (2022-02-10 > 11:19:15 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/10941 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Fri, Dec 03, 2021 at 02:19:32PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 4a14bfffd42f968ed9d72a780a8d44a9053c5b95: > > Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-11-30 > 08:59:22 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to c0ffc12a701621dc72dfc896965cbfe5b0dbf9b4: > > riscv: Enable SPI flash env for SiFive Unmatched. (2021-12-02 16:43:56 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/10128 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Tue, Nov 09, 2021 at 10:40:01AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 52207514ba419a69a8105d16997b025f966c8879: > > Merge branch '2021-11-05-Kconfig-syncs' (2021-11-05 15:38:46 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 990e1e4beae546ddc9c50854c0588d1bea494cd2: > > Fix syntax error (2021-11-08 15:35:55 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9775 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Wed, Oct 20, 2021 at 03:14:00PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit fb1018106a7bbb1a0d723029f6760b1b1b4d306d: > > Merge branch '2021-10-19-assorted-changes' (2021-10-19 20:45:12 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to ddf4972834fdf33f0a3360ff4a68fde333995113: > > riscv: Avoid io read/write cause wrong result (2021-10-20 10:59:17 +0800) > > SI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9532 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Oct 07, 2021 at 07:51:00PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ea67f467a43e4c8852bd1ce1bb75f5dc6c3788d1: > > Merge branch '2021-10-06-assorted-improvements' (2021-10-06 13:46:31 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 1b2b52f29402b5aaadfe4ba11bd3f29bd414: > > riscv: ae350: enable Coherence Manager for ae350 (2021-10-07 16:08:23 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9388 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Tue, Sep 07, 2021 at 04:20:50PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ad320c237bea7ece659efaf6c1d43475e0e5db6a: > > Merge tag 'u-boot-stm32-20210906' of > https://source.denx.de/u-boot/custodians/u-boot-stm (2021-09-06 10:31:56 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 30fa33dc808b8f28185bca9c812225cbc1ec6e8f: > > riscv: lib: modify the indent (2021-09-07 10:34:29 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9018 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Aug 19, 2021 at 04:56:39PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit a0da2dda4ed9d0aee5265e9cd8876734f9f80e09: > > Prepare v2021.10-rc2 (2021-08-16 14:18:45 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 47d73ba4f4a40f17622d93f96b48e285b73c3061: > > board: sifive: overwrite board_fdt_blob_setup in u-boot proper (2021-08-17 > 19:28:37 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8749 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Jul 22, 2021 at 10:15:10AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit c9204859bbdb924cda811813c545032971656480: > > Merge branch 'master' of git://source.denx.de/u-boot-sh (2021-07-20 > 19:31:40 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 219cb173114c9cfaf1dc7fed21281f2c43c88c9f: > > board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device > in SPL (2021-07-21 22:25:15 +0800) > > CI result show no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8344 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Wed, Jul 07, 2021 at 11:21:13PM +0800, Leo Liang wrote: > Hi Tom, > > This is a follow up PR for OpenPiton's dts. > > Thanks for the catch. > > The following changes since commit 5617efd2c882562b716a61bc0dc0edda46b045df: > > Merge branch '2021-07-06-platform-updates' (2021-07-06 18:10:10 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to c9135d5a7af2df0e273e0f7e2f6c8132b34aba82: > > riscv: dts: add OpenPiton RISC-V board dts support (2021-07-07 20:34:02 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8100 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
Hi Tom, Leo, Apologies for making that mistake, and many many thanks for merging our patches! We’ve already fixed the problem with another patch. Many thanks, Tianrui -Original Message- From: Tom Rini Date: Wednesday, July 7, 2021 at 3:52 AM To: Leo Liang Cc: u-boot@lists.denx.de , r...@andestech.com , Tianrui Wei Subject: Re: [PULL] u-boot-riscv/master On Wed, Jul 07, 2021 at 12:02:05AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de: > > Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400) > > are available in the Git repository at: > > > g...@source.denx.de<mailto:g...@source.denx.de>:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829: > > board: sifive: support spl multi-dtb on unmatched board (2021-07-06 > 20:24:26 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081 > Please note: w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #address-cells (1) differs from / (2) w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #size-cells (1) differs from / (2) need to be fixed in a follow up PR (and the relevant dts files should be added to the board MAINTAINER file too). That said, applied to u-boot/master, thanks! -- Tom
Re: [PULL] u-boot-riscv/master
On Wed, Jul 07, 2021 at 12:02:05AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de: > > Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829: > > board: sifive: support spl multi-dtb on unmatched board (2021-07-06 > 20:24:26 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081 > Please note: w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #address-cells (1) differs from / (2) w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #size-cells (1) differs from / (2) need to be fixed in a follow up PR (and the relevant dts files should be added to the board MAINTAINER file too). That said, applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Jun 17, 2021 at 11:31:12AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 9301a5cc99dd0c298e2f7fe2fa98a7287fcda772: > > Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-06-15 > 08:23:04 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54: > > riscv: andes_plic: Fix riscv_get_ipi() mask (2021-06-17 09:39:46 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7864 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Mon, May 31, 2021 at 06:16:19PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ffd810487ec2ff6095edf3f3d058d7ed6eb85ff3: > > Merge tag 'u-boot-stm32-20210528' of > https://source.denx.de/u-boot/custodians/u-boot-stm (2021-05-28 14:11:06 > -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to d7da718bd94943309a7f25f14e694226a45b2aef: > > drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-31 > 16:35:55 +0800) > > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/ > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, May 27, 2021 at 7:20 PM Tom Rini wrote: > On Thu, May 27, 2021 at 06:41:35PM +0800, Leo Liang wrote: > > On Thu, May 27, 2021 at 04:57:17PM +0800, Green Wan wrote: > > > Hi Tom, > > > > > > Thanks for the comments. > > > > > > Not sure whether it catches differentconcerns, I plan to remove > fdt_high and initrd_high sincethe bootm_* settings should be > sufficient to calculate the values related to fdt_high and initrd_high. And > I checked the bootm_* settings as below, the system can > > > boot without fdt_high and initrd_high. > > > > > > - bootm_low is set toCONFIG_SYS_SDRAM_BASE > > > - bootm_size is set to gd-ram_size (which comes from DT) > > > - bootm_mapsize is now equal to bootm_size > > > - boot log without fdt_high and initrd_high > > > "## Flattened Device Tree blob at 8800 > > > Booting using the fdt blob at 0x8800 > > > Loading Device Tree to a000, end f64d ... > OK" > > > > > > Hi Leo/Rick, > > > > > > Should I create v12 for fu740 series patchset based on > u-boot-riscv.git ? or revert [PATCH v11 7/8] plus a patch? Thanks a lot! > > > > > > Regards, > > > Green > > > > Hi Green, > > > > I think you could just create v12 patch. > > I will do the revert, thanks! > Hi Leo, Thanks for the help. I just posted the v12 patchset. -- Green > > Thanks for sorting this out quickly! > > -- > Tom >
Re: [PULL] u-boot-riscv/master
On Thu, May 27, 2021 at 06:41:35PM +0800, Leo Liang wrote: > On Thu, May 27, 2021 at 04:57:17PM +0800, Green Wan wrote: > > Hi Tom, > > > > Thanks for the comments. > > > > Not sure whether it catches differentconcerns, I plan to remove > > fdt_high and initrd_high sincethe bootm_* settings should be > > sufficient to calculate the values related to fdt_high and initrd_high. And > > I checked the bootm_* settings as below, the system can > > boot without fdt_high and initrd_high. > > > > - bootm_low is set toCONFIG_SYS_SDRAM_BASE > > - bootm_size is set to gd-ram_size (which comes from DT) > > - bootm_mapsize is now equal to bootm_size > > - boot log without fdt_high and initrd_high > > "## Flattened Device Tree blob at 8800 > > Booting using the fdt blob at 0x8800 > > Loading Device Tree to a000, end f64d ... OK" > > > > Hi Leo/Rick, > > > > Should I create v12 for fu740 series patchset based on u-boot-riscv.git ? > > or revert [PATCH v11 7/8] plus a patch? Thanks a lot! > > > > Regards, > > Green > > Hi Green, > > I think you could just create v12 patch. > I will do the revert, thanks! Thanks for sorting this out quickly! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, May 27, 2021 at 04:57:17PM +0800, Green Wan wrote: > Hi Tom, > > Thanks for the comments. > > Not sure whether it catches differentconcerns, I plan to remove > fdt_high and initrd_high sincethe bootm_* settings should be sufficient > to calculate the values related to fdt_high and initrd_high. And I checked > the bootm_* settings as below, the system can > boot without fdt_high and initrd_high. > > - bootm_low is set toCONFIG_SYS_SDRAM_BASE > - bootm_size is set to gd-ram_size (which comes from DT) > - bootm_mapsize is now equal to bootm_size > - boot log without fdt_high and initrd_high > "## Flattened Device Tree blob at 8800 > Booting using the fdt blob at 0x8800 > Loading Device Tree to a000, end f64d ... OK" > > Hi Leo/Rick, > > Should I create v12 for fu740 series patchset based on u-boot-riscv.git ? or > revert [PATCH v11 7/8] plus a patch? Thanks a lot! > > Regards, > Green Hi Green, I think you could just create v12 patch. I will do the revert, thanks! Best regards, Leo > > > > On Wed, May 26, 2021 at 11:24 PM Tom Rini tr...@konsulko.com wrote: > > > > > > On Wed, May 26, 2021 at 04:12:50PM 0800, Leo Liang wrote: > > > > Hi Tom, > > > > The following changes since commit > > eb53b943be2949ca40a8e05532cd74cda058: > > > > Merge https://source.denx.de/u-boot/custodians/u-boot-sh (2021-05-23 > > 10:15:15 -0400) > > > > are available in the Git repository at: > > > > > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 9358576a281ab5e3b7348685bbd5f713833a5048: > > > > drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-24 > > 23:54:54 0800) > > > > Gitlab CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7620 > > NAK. > ERROR: fdt or initrd relocation disabled at boot time > #993: FILE: include/configs/sifive-unmatched.h:65: >fdt_high=0x\0 \ > > ERROR: fdt or initrd relocation disabled at boot time > #994: FILE: include/configs/sifive-unmatched.h:66: >initrd_high=0x\0 \ > > You can, but shouldn't disable initrd relocation. You cannot disable > device tree relocation as that leads to too many issues due to > misalignment later. Make use of bootm_size or similar to make sure > everything is within an appropriate area of memory. Thanks. > > -- > Tom
Re: [PULL] u-boot-riscv/master
Hi Tom, Thanks for the comments. Not sure whether it catches different concerns, I plan to remove fdt_high and initrd_high since the bootm_* settings should be sufficient to calculate the values related to fdt_high and initrd_high. And I checked the bootm_* settings as below, the system can boot without fdt_high and initrd_high. - bootm_low is set to CONFIG_SYS_SDRAM_BASE - bootm_size is set to gd->ram_size (which comes from DT) - bootm_mapsize is now equal to bootm_size - boot log without fdt_high and initrd_high "## Flattened Device Tree blob at 8800 Booting using the fdt blob at 0x8800 Loading Device Tree to a000, end f64d ... OK" Hi Leo/Rick, Should I create v12 for fu740 series patchset based on u-boot-riscv.git ? or revert [PATCH v11 7/8] plus a patch? Thanks a lot! Regards, Green On Wed, May 26, 2021 at 11:24 PM Tom Rini wrote: > On Wed, May 26, 2021 at 04:12:50PM +0800, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit > eb53b943be2949ca40a8e05532cd74cda058: > > > > Merge https://source.denx.de/u-boot/custodians/u-boot-sh (2021-05-23 > 10:15:15 -0400) > > > > are available in the Git repository at: > > > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 9358576a281ab5e3b7348685bbd5f713833a5048: > > > > drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-24 > 23:54:54 +0800) > > > > Gitlab CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7620 > > > > NAK. > ERROR: fdt or initrd relocation disabled at boot time > #993: FILE: include/configs/sifive-unmatched.h:65: > + "fdt_high=0x\0" \ > > ERROR: fdt or initrd relocation disabled at boot time > #994: FILE: include/configs/sifive-unmatched.h:66: > + "initrd_high=0x\0" \ > > You can, but shouldn't disable initrd relocation. You cannot disable > device tree relocation as that leads to too many issues due to > misalignment later. Make use of bootm_size or similar to make sure > everything is within an appropriate area of memory. Thanks. > > -- > Tom >
Re: [PULL] u-boot-riscv/master
On Wed, May 26, 2021 at 04:12:50PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit eb53b943be2949ca40a8e05532cd74cda058: > > Merge https://source.denx.de/u-boot/custodians/u-boot-sh (2021-05-23 > 10:15:15 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 9358576a281ab5e3b7348685bbd5f713833a5048: > > drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-24 > 23:54:54 +0800) > > Gitlab CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7620 > NAK. ERROR: fdt or initrd relocation disabled at boot time #993: FILE: include/configs/sifive-unmatched.h:65: + "fdt_high=0x\0" \ ERROR: fdt or initrd relocation disabled at boot time #994: FILE: include/configs/sifive-unmatched.h:66: + "initrd_high=0x\0" \ You can, but shouldn't disable initrd relocation. You cannot disable device tree relocation as that leads to too many issues due to misalignment later. Make use of bootm_size or similar to make sure everything is within an appropriate area of memory. Thanks. -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, May 20, 2021 at 10:19:54AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 428bec7cf956c3558bbdfda4d2ba23beb73a68ba: > > Merge branch '2021-05-17-assorted-fixes' (2021-05-18 14:17:54 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to a4691f363ef75783bee626bb8337c3a34d8c0e96: > > riscv: ae350: Increase malloc size for binman spl flow (2021-05-19 17:01:52 > +0800) > > Gitlab CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7583 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Tue, May 18, 2021 at 09:48:43AM +0800, Leo Liang wrote: > Hi Tom, > > CI result: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7572 > > The following changes since commit e644dfbb1786a4a3308b068e1f61cd9e2dfac237: > > configs: Resync with savedefconfig (2021-05-15 08:10:13 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 89419279f4fe6bfd68dd518059ef2007295f1cb4: > > riscv: Group assembly optimized implementation of memory routines into a > submenu (2021-05-17 16:47:33 +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Fri, May 14, 2021 at 07:10:10PM +0800, Leo Liang wrote: > Hi Tom, > > CI result: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7504 > > The following changes since commit 530c8d4af2e18c6142ab7cac6f11dd92c02b2bc9: > > Merge branch > '2021-05-13-extension-board-detection-and-DT-overlay-application' (2021-05-13 > 13:09:14 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to ffdc71bc0977c1e6b7b6e6a5a005e1f77213bf21: > > Revert "riscv: cpu: fu740: clear feature disable CSR" (2021-05-14 16:26:20 > +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
Hi Leo, On Fri, May 14, 2021 at 7:10 PM Leo Liang wrote: > > Hi Tom, > > CI result: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7504 > > The following changes since commit 530c8d4af2e18c6142ab7cac6f11dd92c02b2bc9: > > Merge branch > '2021-05-13-extension-board-detection-and-DT-overlay-application' (2021-05-13 > 13:09:14 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to ffdc71bc0977c1e6b7b6e6a5a005e1f77213bf21: > > Revert "riscv: cpu: fu740: clear feature disable CSR" (2021-05-14 16:26:20 > +0800) > > > Bin Meng (1): > Revert "riscv: cpu: fu740: clear feature disable CSR" The following patches are not applied. Without them, SiFive Unleashed is still not bootable. http://patchwork.ozlabs.org/project/uboot/patch/20210511120412.25065-1-bmeng...@gmail.com/ http://patchwork.ozlabs.org/project/uboot/list/?series=243574 Could you please apply ASAP? Regards, Bin
Re: [PULL] u-boot-riscv/master
On Fri, May 07, 2021 at 09:49:08AM +0800, Sean Anderson wrote: > Hi Leo, > > Are you maintaining RISC-V now? Should I be CC-ing you on my series? > Can you update MAINTAINERS with this information? Thanks. > > --Sean > Hi Sean, Yes, I am now co-maintaining RISC-V tree with Rick. I will update the information as soon as possible, thanks for the reminder. And yes, please do CC your work to me, thanks again! Best regards, Leo > On 5/6/21 9:06 PM, Leo Liang wrote: > > Hi Tom, > > > > CI result: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400 > > > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b: > > > >Merge tag 'dm-pull-29apr21' of > > https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 > > -0400) > > > > are available in the Git repository at: > > > >https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2: > > > >cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 > > +0800) > > > > > > Dylan Jhong (1): > >atcspi200: Add timeout mechanism in spi_xfer() > > > > Green Wan (2): > >riscv: cpu: Add callback to init each core > >riscv: cpu: fu740: clear feature disable CSR > > > > Heinrich Schuchardt (1): > >cmd/exception: support ebreak exception on RISC-V > > > > arch/riscv/cpu/cpu.c| 11 +++ > > arch/riscv/cpu/fu540/spl.c | 15 +++ > > arch/riscv/cpu/start.S | 4 > > cmd/riscv/exception.c | 10 ++ > > doc/usage/exception.rst | 3 +++ > > drivers/spi/atcspi200_spi.c | 10 -- > > 6 files changed, 51 insertions(+), 2 deletions(-) > > > > Best regards, > > Leo > >
Re: [PULL] u-boot-riscv/master
On Thu, May 06, 2021 at 09:55:17PM -0400, Sean Anderson wrote: > On 5/6/21 9:41 PM, Leo Liang wrote: > > On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote: > > > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote: > > > > > > > Hi Tom, > > > > > > > > CI result: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400 > > > > > > > > The following changes since commit > > > > 8ddaf943589756442bba21e5be645cd47526d82b: > > > > > > > >Merge tag 'dm-pull-29apr21' of > > > > https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 > > > > -0400) > > > > > > > > are available in the Git repository at: > > > > > > > >https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > > > > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2: > > > > > > > >cmd/exception: support ebreak exception on RISC-V (2021-05-05 > > > > 16:13:12 +0800) > > > > > > > > > > > > Dylan Jhong (1): > > > >atcspi200: Add timeout mechanism in spi_xfer() > > > > > > > > Green Wan (2): > > > >riscv: cpu: Add callback to init each core > > > >riscv: cpu: fu740: clear feature disable CSR > > > > > > > > Heinrich Schuchardt (1): > > > >cmd/exception: support ebreak exception on RISC-V > > > > > > > > arch/riscv/cpu/cpu.c| 11 +++ > > > > arch/riscv/cpu/fu540/spl.c | 15 +++ > > > > arch/riscv/cpu/start.S | 4 > > > > cmd/riscv/exception.c | 10 ++ > > > > doc/usage/exception.rst | 3 +++ > > > > drivers/spi/atcspi200_spi.c | 10 -- > > > > 6 files changed, 51 insertions(+), 2 deletions(-) > > > > > > Please note that currently > > > https://patchwork.ozlabs.org/project/uboot/list/?series==20174 > > > shows 55 patches. Most of them have been posted long enough that I > > > would expect them to be applied if there's no further feedback. Can you > > > please take a look? Thanks! > > > > > > > No problem, sorry for the delay! > > > > Two quick questions. > > > > Some of the patches delegated to Andes do not own a RISC-V tag but rather > > clk or driver etc. > > Do you mind if we pull them through RISC-V tree? > > Clock patches should go though Lukasz's tree, but given the scope of the > patches I think it is OK for them to be in RISC-V. I would like to get an > Acked-by from him, but unfortunately he hasn't commented on them at all. In general, I believe it is OK for non-subsystem-core changes to go via the architecture / SoC tree. -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote: > Hi Tom, > > CI result: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400 > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b: > > Merge tag 'dm-pull-29apr21' of > https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2: > > cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 > +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Fri, May 07, 2021 at 03:21:13PM +0100, Dimitri John Ledkov wrote: > Hi, > > On Fri, May 7, 2021 at 2:42 AM Leo Liang wrote: > > > > On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote: > > > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote: > > > > > > > Hi Tom, > > > > > > > > CI result: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400 > > > > > > > > The following changes since commit > > > > 8ddaf943589756442bba21e5be645cd47526d82b: > > > > > > > > Merge tag 'dm-pull-29apr21' of > > > > https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 > > > > -0400) > > > > > > > > are available in the Git repository at: > > > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > > > > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2: > > > > > > > > cmd/exception: support ebreak exception on RISC-V (2021-05-05 > > > > 16:13:12 +0800) > > > > > > > > > > > > Dylan Jhong (1): > > > > atcspi200: Add timeout mechanism in spi_xfer() > > > > > > > > Green Wan (2): > > > > riscv: cpu: Add callback to init each core > > > > riscv: cpu: fu740: clear feature disable CSR > > > > > > > > Heinrich Schuchardt (1): > > > > cmd/exception: support ebreak exception on RISC-V > > > > > > > > arch/riscv/cpu/cpu.c| 11 +++ > > > > arch/riscv/cpu/fu540/spl.c | 15 +++ > > > > arch/riscv/cpu/start.S | 4 > > > > cmd/riscv/exception.c | 10 ++ > > > > doc/usage/exception.rst | 3 +++ > > > > drivers/spi/atcspi200_spi.c | 10 -- > > > > 6 files changed, 51 insertions(+), 2 deletions(-) > > > > > > Please note that currently > > > https://patchwork.ozlabs.org/project/uboot/list/?series==20174 > > > shows 55 patches. Most of them have been posted long enough that I > > > would expect them to be applied if there's no further feedback. Can you > > > please take a look? Thanks! > > > > > > > No problem, sorry for the delay! > > > > Two quick questions. > > > > Some of the patches delegated to Andes do not own a RISC-V tag but rather > > clk or driver etc. > > Do you mind if we pull them through RISC-V tree? > > > > And for these patches, > > do you prefer them pulled into this release or for-next branch? > > > Although > https://patchwork.ozlabs.org/project/uboot/patch/20210421114201.57994-1-x...@ubuntu.com/ > is not strictly for riscv64 it does prevent me from using the same > Ubuntu rootfs for riscv boards or qemu. I would appreciate it if it > could be pulled in via qemu or riscv maintainers. As that's a PXE change I've assigned it to the network maintainer, and I've cc'd him here. Thanks. -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
Hi, On Fri, May 7, 2021 at 2:42 AM Leo Liang wrote: > > On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote: > > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote: > > > > > Hi Tom, > > > > > > CI result: > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400 > > > > > > The following changes since commit > > > 8ddaf943589756442bba21e5be645cd47526d82b: > > > > > > Merge tag 'dm-pull-29apr21' of > > > https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 > > > -0400) > > > > > > are available in the Git repository at: > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2: > > > > > > cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 > > > +0800) > > > > > > > > > Dylan Jhong (1): > > > atcspi200: Add timeout mechanism in spi_xfer() > > > > > > Green Wan (2): > > > riscv: cpu: Add callback to init each core > > > riscv: cpu: fu740: clear feature disable CSR > > > > > > Heinrich Schuchardt (1): > > > cmd/exception: support ebreak exception on RISC-V > > > > > > arch/riscv/cpu/cpu.c| 11 +++ > > > arch/riscv/cpu/fu540/spl.c | 15 +++ > > > arch/riscv/cpu/start.S | 4 > > > cmd/riscv/exception.c | 10 ++ > > > doc/usage/exception.rst | 3 +++ > > > drivers/spi/atcspi200_spi.c | 10 -- > > > 6 files changed, 51 insertions(+), 2 deletions(-) > > > > Please note that currently > > https://patchwork.ozlabs.org/project/uboot/list/?series==20174 > > shows 55 patches. Most of them have been posted long enough that I > > would expect them to be applied if there's no further feedback. Can you > > please take a look? Thanks! > > > > No problem, sorry for the delay! > > Two quick questions. > > Some of the patches delegated to Andes do not own a RISC-V tag but rather clk > or driver etc. > Do you mind if we pull them through RISC-V tree? > > And for these patches, > do you prefer them pulled into this release or for-next branch? Although https://patchwork.ozlabs.org/project/uboot/patch/20210421114201.57994-1-x...@ubuntu.com/ is not strictly for riscv64 it does prevent me from using the same Ubuntu rootfs for riscv boards or qemu. I would appreciate it if it could be pulled in via qemu or riscv maintainers. -- Regards, Dimitri.
Re: [PULL] u-boot-riscv/master
On 5/6/21 9:41 PM, Leo Liang wrote: On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote: On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote: Hi Tom, CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400 The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b: Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2: cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800) Dylan Jhong (1): atcspi200: Add timeout mechanism in spi_xfer() Green Wan (2): riscv: cpu: Add callback to init each core riscv: cpu: fu740: clear feature disable CSR Heinrich Schuchardt (1): cmd/exception: support ebreak exception on RISC-V arch/riscv/cpu/cpu.c| 11 +++ arch/riscv/cpu/fu540/spl.c | 15 +++ arch/riscv/cpu/start.S | 4 cmd/riscv/exception.c | 10 ++ doc/usage/exception.rst | 3 +++ drivers/spi/atcspi200_spi.c | 10 -- 6 files changed, 51 insertions(+), 2 deletions(-) Please note that currently https://patchwork.ozlabs.org/project/uboot/list/?series==20174 shows 55 patches. Most of them have been posted long enough that I would expect them to be applied if there's no further feedback. Can you please take a look? Thanks! No problem, sorry for the delay! Two quick questions. Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc. Do you mind if we pull them through RISC-V tree? Clock patches should go though Lukasz's tree, but given the scope of the patches I think it is OK for them to be in RISC-V. I would like to get an Acked-by from him, but unfortunately he hasn't commented on them at all. --Sean And for these patches, do you prefer them pulled into this release or for-next branch? Best regards, Leo
Re: [PULL] u-boot-riscv/master
Hi Leo, Are you maintaining RISC-V now? Should I be CC-ing you on my series? Can you update MAINTAINERS with this information? Thanks. --Sean On 5/6/21 9:06 PM, Leo Liang wrote: Hi Tom, CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400 The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b: Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2: cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800) Dylan Jhong (1): atcspi200: Add timeout mechanism in spi_xfer() Green Wan (2): riscv: cpu: Add callback to init each core riscv: cpu: fu740: clear feature disable CSR Heinrich Schuchardt (1): cmd/exception: support ebreak exception on RISC-V arch/riscv/cpu/cpu.c| 11 +++ arch/riscv/cpu/fu540/spl.c | 15 +++ arch/riscv/cpu/start.S | 4 cmd/riscv/exception.c | 10 ++ doc/usage/exception.rst | 3 +++ drivers/spi/atcspi200_spi.c | 10 -- 6 files changed, 51 insertions(+), 2 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote: > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote: > > > Hi Tom, > > > > CI result: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400 > > > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b: > > > > Merge tag 'dm-pull-29apr21' of > > https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 > > -0400) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2: > > > > cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 > > +0800) > > > > > > Dylan Jhong (1): > > atcspi200: Add timeout mechanism in spi_xfer() > > > > Green Wan (2): > > riscv: cpu: Add callback to init each core > > riscv: cpu: fu740: clear feature disable CSR > > > > Heinrich Schuchardt (1): > > cmd/exception: support ebreak exception on RISC-V > > > > arch/riscv/cpu/cpu.c| 11 +++ > > arch/riscv/cpu/fu540/spl.c | 15 +++ > > arch/riscv/cpu/start.S | 4 > > cmd/riscv/exception.c | 10 ++ > > doc/usage/exception.rst | 3 +++ > > drivers/spi/atcspi200_spi.c | 10 -- > > 6 files changed, 51 insertions(+), 2 deletions(-) > > Please note that currently > https://patchwork.ozlabs.org/project/uboot/list/?series==20174 > shows 55 patches. Most of them have been posted long enough that I > would expect them to be applied if there's no further feedback. Can you > please take a look? Thanks! > No problem, sorry for the delay! Two quick questions. Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc. Do you mind if we pull them through RISC-V tree? And for these patches, do you prefer them pulled into this release or for-next branch? Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote: > Hi Tom, > > CI result: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400 > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b: > > Merge tag 'dm-pull-29apr21' of > https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2: > > cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 > +0800) > > > Dylan Jhong (1): > atcspi200: Add timeout mechanism in spi_xfer() > > Green Wan (2): > riscv: cpu: Add callback to init each core > riscv: cpu: fu740: clear feature disable CSR > > Heinrich Schuchardt (1): > cmd/exception: support ebreak exception on RISC-V > > arch/riscv/cpu/cpu.c| 11 +++ > arch/riscv/cpu/fu540/spl.c | 15 +++ > arch/riscv/cpu/start.S | 4 > cmd/riscv/exception.c | 10 ++ > doc/usage/exception.rst | 3 +++ > drivers/spi/atcspi200_spi.c | 10 -- > 6 files changed, 51 insertions(+), 2 deletions(-) Please note that currently https://patchwork.ozlabs.org/project/uboot/list/?series==20174 shows 55 patches. Most of them have been posted long enough that I would expect them to be applied if there's no further feedback. Can you please take a look? Thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Thu, Apr 08, 2021 at 06:44:45PM +0800, Leo Liang wrote: > Hi Tom, > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7078 > > The following changes since commit e9c99db7787e3b5c2ef05701177c43ed1c023c27: > > Merge branch '2021-04-07-CI-improvements' (2021-04-07 15:54:07 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to e7bb113cc4d03aeb573ff938a1d897d4b3ca99df: > > riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodes > (2021-04-08 15:37:30 +0800) > Please note that there's a lot of stuff still under: https://patchwork.ozlabs.org/project/uboot/list/?series==20174 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
